AI4100

Ver1.0 1 A1 PROs A1 PROs FEATURES ㆍOperating voltage : 2.7V ~ 3.6V ㆍLow power consumption : 70mW (Typ.) ㆍPower down mode : less than 30μW ㆍAccepts a direct signal input to ADC or PGA at 1.0 VPP (Typ.) ㆍCCD signal input level : 1.1 VP-P (Max.) ㆍ10-bit ADC (up to 20MHz) - DNL : ±0.6 LSB (Typ.) ㆍBlack level neutralizer, target setting : 16~127 LSB ㆍBuilt-in serial interface Ai4100 CCD CDS/PGA/10b-20M-ADC ㆍIndependent ADC input conversion clock and data output clock ㆍIndependent CDS and PGA gain control - CDS : -1.94/ 0/ 6/ 12dB - PGA : 0~24dB ㆍWide gain range : -1.94 ~ 36dB ㆍHigh speed sample and hold circuit : pulse width 11ns (Min.) ㆍ48-pin LQFP package GENERAL DESCRIPTION The Ai4100 is a CMOS single-chip signal processing devices for CCD area sensors. It consists of a clamp circuit, Correlated Double Sampler (CDS), Programmable Gain Amplifier (PGA), reference voltage generator, black level detection circuit, voltage generator, black level detection circuit, 20MHz 10-bit A/D converter (ADC), timing generator for internally required pulses and serial interface for internal function control and PGA gain control. BLOCK DIAGRAM OBP ADCLK BLK CLPCAP DC Clamp CCDCLP REFIN CCDIN CCD ADIN OBCAP OBP DAC Compare Black Level Register ADCLP -1.94/0/6/12dB 0~6dB 0/6/12/18dB (0.047dB/Step) ADCLP/CCDCLP CSN SCK SDATA MONOUT Timing Generator Serial Register BandGap Circuit VRP VCOM VRN CDS PGA Rough PGA Fine 10-Bit ADC DO0~DO9 VDD VSS RESET STBY SHP SHD OUTCK 1 Ai4100 PIN ASSIGNMENT DVDD2 DVSS2 DO0 DO3 DO1 DO2 DO6 DO4 DO7 DO5 DO8 DO9 NC AVDD4 NC REFB REFT AVDD3 AVDD2 AVSS3 AVSS2 CML CCDIN REFIN OUTCK RESETN DVDD1 DVSS1 STBY Ai4100 CSN SDATA SCK OBP CCDCLP BLK ADCLP SHD NC SHP ADCLK MONOUT AISET AVSS1 AVDD1 OBCAP NC ADIN CLPCAP 2 Ai4100 PIN DESCRIPTION Pin No. 1, 3, 17, 21 2, 6~7, 19 4 5 8~9, 20 10 11 12 13 14 15 16 18 22 23 24 25 26 27 28 29 30 31 32 33, 42 34, 43 35 36 37~41, 44~48 NC AVDD REFB REFT AVSS CML CCDIN REFIN CLPCAP ADIN OBCAP MONOUT AISET ADCLK SHP SHD ADCLP BLK CCDCLP OBP SCK SDATA CSN STBY DVSS DVDD RESETN OUTCK D0~D9 Pin Name I/O O O O I I O I O O I I I I I I I I I I I I I I O No Connection Analog Power (+3.3V) Description ADC Internal Bottom Reference Voltage ADC Internal Top Reference Voltage Analog Ground ADC Internal Common Reference Voltage CDS Input Data Input CDS Circuit Reference Input Clamp Level Output ADIN Signal Input Black Level Integration Voltage Monitor Output of CDS or PGA External Bias Current Setting ADC Sampling Clock Input Reference Sampling Pulse Input Data Sampling Pulse Input Pulse Input for ADIN Clamp and Black Calibration Control Blanking Pulse Input Clamp Control Input Black Level Period Pulse Input Serial Port Clock Input Serial Port Data Input Serial Port Chip Selection (Active Low) Power Down Control (Power Down at Low) Digital GND Digital Power (+3.3V) Reset Signal Input (Active Low) Clock Input for ADC Output Timing ADC Digital Output ABSOLUTE MAXIMUM RATINGS Characteristics Supply Voltage Input Voltage Storage Temperature Operating Temperature Symbol VCC VIN TSTG TOP Value GND-0.3 to GND+6.0 V VSS-0.3 to VDD+0.3 -55 to +150 -20 to +70 ℃ Unit Note : These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Rating” may cause substantial damage to the devices. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability 3 Ai4100 DC CHARACTERISTICS Test Conditions Symbol VIH VIL IIH IIL IMD IMA ISS VCCDIN Analog Input Range VADIN VCLPCAP tBLKCAL VBLKCAL G (0) G (1) G (2) G (3) GMIN GMAX GSTEP ERPA RES DNL SN SND VCOM VRP VRN CCAL STCAL Clamp Voltage Black Calibration Time Maximum Calibration Offset Voltage CDS Gain (Set 0 dB) CDS Gain (Set 6.02 dB) CDS Gain (Set 12.04 dB) CDS Gain (Set -1.94 dB) PGA Gain (Minimum Gain) PGA Gain (Maximum Gain) PGA Gain (Gain Step) Total (CDS+PGA) Gain Monotony Resolution Differential Nonlinearity S/N S/(N+D) ADC Common Voltage VRP Voltage (Positive) VRN Voltage (Negative) ADC Output Black Level Calibration Code Calibration Code Resolution 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V Relative gain 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V fS=20MHz 1 1 127 LSB LSB 0 1.25 1.55 1.05 16 0.047 ±0.6 58 56 1.4 1.65 1.15 0.094 ±4 10 ±1.0 1.55 1.75 1.25 127 dB LSB Bits LSB dB dB V V V LSB Absolute gain Relative gain ADIN input, fIN=1MHz Absolute gain 1.5 -2 5.52 11.54 -2.44 -1.2 22.906 1.0 1.7 ±200 -1 6.02 12.04 -1.94 -0.2 23.906 1.9 200 0 6.52 12.04 -1.44 0.8 24.906 VP-P V Pixel mV dB dB dB dB dB dB (Ta = 25℃) Min. VDD Conditions VIL=0V VIH=3.0V fS=20MHz fS=20MHz CCDIN input, fIN=1MHz 0.7VDD 0 23 26 1.1 VDD 0.3VDD 200 1 10 V V μA μA mA mA μA VP-P 3V 3V 3V 3V 3V 3V 3V 3V Parameter High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Operation Current at Monitor Disable Supply Current at Monitor Active Power Down Current Typ. Max. Unit Note : Black calibration period is specified when CCAL is from 16 to 127LSB. Although black level codes of 1 to 15 could be set, tBLKCAL is not guaranteed for these codes. 4 Ai4100 AC CHARACTERISTICS (VSS = 0V, Ta = 25℃) Test Conditions Symbol fS tCYC tR tF tL tH tWR tWD tDR tDD tPSUP tHOLD tSP tSUPE tHOLDE tSUPOC tHOLDOC tDLD tDLE tDL Parameter VDD Conversion Frequency Clock Cycle Time Clock Rising Time Clock Falling Time Clock Low Period Clock High Period SHP Pulse Width SHD Pulse Width SHP Pulse Width SHD Sampling Aperture Data Pulse Setup Data Pulse Hold Sampling Pulse Non-overlay Enable Pulse Setup Enable Pulse Hold OUTCK Setup OUTCK Hold 3-state Disable Delay 3-state Disable Delay ADC Output Data Delay 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V Active High–Z High-Z Active Min. Conditions 0.5 50 23 23 11 11 2 5 1 10 10 0 10 - Typ. 20 20 6 Max. 20 2 2 4 4 - Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 Ai4100 FUNCTIONAL DESCRIPTION CDS ( Co rrelated Double Sampling) Circuit C onnect the CCDIN pin to the CCD sensor through a capacitor. Connect also the REFIN pin to VSS through a capacitor. The CDS circuit holds the pre-charge voltage of the CCD at SHP pulse and do sampling of the CCD pixel data at SHD pulse, Correlated noise is removed by subtracting the pre-charge voltage from the pixel data level. CDS could choose a gain setting from 0, 6.02, 12 or -1.94dB (Mode 3, register D4 and D5 bits). A CDS gain is controlled by PGA gain. It is recommended to increase the CDS gain then increase the PGA gain to reduce the noise level. ㆍClamp target (Mode 2 register D5 and D4), input signal(REFIN and CCDIN) to be clamped are selected. CDS ( Co rrelated Double Sampling) Circuit The purpose of a black level cancel circuit is to control the DC level of the PGA input. The ADC output code at an optical black period may correspond to the black level code set up by the register. A black level code of (1 to)16 to 127 LSB is available (the default is 64 LSB) While the OBP pin is active a black level cancel loop is established. In the loop, a comparison is made between the ADC output code and the black level code, the result controls the voltage of the OBCAP capacitor. Hence, the OBCAP voltage settles gradually and the signal level of the optical black period corresponds to the established value. The following conditions will reset the OBCAP capacitor: ㆍ Set the black level reset register to “1” (Mode 1 register D1=1). ㆍSet the RESETN pin to low ㆍPower down by STBY pin or register control The DC clamping (CCDCLP) is allowed while the DBP pin is low. The black level cancellation is available at “ADIN signal to PGA” mode. The black level cancellation is available at the ADCLP period in this mode. The clamping function and black level canceling function are done simultaneously. Clamp Circuits ㆍ DC clamp The DC level of the CCDIN/REFIN input is fixed by an internal DC clamp circuit. The DC level of the C-coupled CCD signal at the CDS input is set to CLPCAP by the internal DC clamp circuit. The clamp switches are usually turned on at the black level calibration period. The CLPCAP pin connects to VSS through a 0.1μF capacitor. ㆍ ADIN signal clamp Clamp operation can also be used for the ADIN path. The clamp voltage is different from the CCDIN/REFIN signal and it could be turned off by register setting. At “ADIN signal to ADC” mode, the ADCLP signal controls the “clamp circuit”. Black level calibration circuit is also controlled by ADCLP at “ADIN signal to PGA” mode ㆍ Clamp control ㆍClamp current (Mode 2 register D7). Charge current can select normal or fast clamp. CCD OB ADCLK Effective Pixel Blanking BLK OBP CCDCLP OUTCK DO0~DO9 Data Output Black Code 6 Ai4100 Blanking CCD Effective Pixel Signal Optical Black Period Blanking Effective Pixel Signal ADCLK OBP Previous Black Level Resulting Black Calibration Level (Hold) OBCAP Black Level Calibration Timing High-speed Black Level Cancellation T he A i 4100 has a high speed black level cancellation function, which by means of a register setting enhances the setting speed within a fixed period from access to the serial interface, It increases the gain of the setting DAC within a fixed a fixed period and in turn increases the charge/discharge current to the OBCAP capacitor. The Mode 3 register D3 to D0 data controls the black level boost function. The default setting is always low gain (D3~D0-5’b0). By setting the register D2~D0, the gain becomes high by 1 to 7 times that of the OBP pulse period after any access to the serial interface. After that period, the gain returns to low. When setting D3 to 1’b1, the gain is always high. The CSN signal becomes the starting point of the OBP pulse count. The following figure shows the black loop setting gain boost timing chart when the boost controls is on (D3=“0”) and the boost period is set to 3. CSN tSUCS OBP tHCS Counter 0 1 2 3 3 0 1 2 0 1 2 Black loop gain High gain Low gain High gain Black Loop Setting Gain Boost Timing Symbol tSUCS tHCS Parameter CSN Setup Time CSN Hold Time Condition Min. 10 10 Typ. Max. Unit ns ns Gain Control Circuit The total gain for a CCD input signal covers from -1.94dB to 36dB. The CDS range is 0/6/12/-1.94 dB. The PGA rough is 0/6/12/18 dB and ADC fine is 0 to 6dB, 0.047dB/step. The CDS gain is controlled by a 2-bit register and the PGA gain is controlled by a 9-bit register ㆍThe signal from the CCDIN input through a CDS and PGA ㆍThe signal from the ADIN input through an PGA at the ADIN mode. ㆍThe signal from the ADIN input at the ADIN mode. A/D Conversion Range The analog input range of the ADC is determined by the internal reference voltage. The full scale of the ADC is 1.0 VPP A/D Converter Circuit The Ai4100 includes one 20MHz 10-bits AD converter. The ADC converters the following signals. 7 Ai4100 A/D Converter Output Code (Mode 1 Register D5=1) The format of an ADC digital output is a straight binary. When in the input zero reference voltage, the output code will be all zero and when the input is a full scale voltage, the output code will be all one the ADCLK input after a 5.5 clock of pipeline delay. High-Z Control of ADC Digital Output ADC digital outputs become High-Z under the following conditions ㆍ Set the ADC output bit to one. (Mode 1 register D2=1) ㆍ Set the STBY pin to low ㆍ Set the power control bit to one (Mode 1 register D0=1) Clock, Pipeline Delay, Digital Data Output Timing The ADCLK input is used for an A/D conversion. The ADC input signal is sampled at the falling edge of the ADCLK input and 10 bits parallel data is output at the rising edge of Digital Output Code A/D Input MSB D9 Full Scale : : : : Zero Scale 1 : 1 0 : 0 D8 1 : 0 1 : 0 D7 1 : 0 1 : 0 D6 1 : 0 1 : 0 D5 1 : 0 1 : 0 D4 1 : 0 1 : 0 D3 1 : 0 1 : 0 D2 1 : 0 1 : 0 D1 1 : 0 1 : 0 LSB D0 1 : 0 1 : 0 ADC Data Output (Coding : Straight Binary) Miscellaneous Functions (ADC Direct Input, ADIN Mode) The direct input path to the ADC or the PGA is achieved by means of a register setting. The selectable paths are as follows: ㆍFunction disable (default, Mode 1 register D5=0, D4=0) ㆍADIN input to the PGA (Mode 1 register D5=0, D4=1) ㆍADIN input to the PGA (Mode 1 register D5=1, D4=Don’t Care) The BLK, SHD and SHP inputs are ignored at the ADIN mode. Polarity Inversion The following input polarities can be inverted by register setting: ㆍADCLK (A/D converter sampling clock, Mode 1 register D6) ㆍSHP and SHD (CDS sampling clock, Mode 2 register D3 and D2) ㆍBLK, OBP, CCDCLP and ADCLP (Mode 2 register D3 and D2) Data Output Clock The ADCK input or the OUTCK input is selectable as an ADC data output clock. Power Down Mode The power mode can be set either by register setting or by the STBY pin. Serial Interface Circuit The internal registers of the Ai4110 are controlled by a 3wire serial interface. The data is a 16-bit length serial data that consists of a 2-bit operation code, 4 bits address and 10bits data. Each bit is fetched at the rising edge of the CSN input. Keep CSN to high when not access Ai4110. it is prohibited to write to a non-defined address. When a data length is below 16 bits, the data is not executed. Monitor Output When setting Mode 2 (D1 and D0), the signal from MONOUT is selectable. The alternatives are OFF, CDS output, PGA output or REFIN/CCDIN output. The MONOUT pin gain is fixed to 0dB regardless of the gain control register setting when the CDS output is selected. The MONOUT level becomes V COM at zero reference level. The signals are output in reverse for the CCD input Registers The A i 4100 has 10 bitsX7 registers that control the operations. All registers are write only, the serial registers are written by the serial interface. 8 Ai4100 Address R/W A3 W W W W W 0 0 0 0 0 A2 0 0 0 0 1 A1 0 0 1 1 0 A0 0 1 0 1 0 Mode 1 Mode 2 Mode 3 / CDS gain PGA gain Black level DOUT timing control/OUTCK polarity/ADCLK polarity/ADIN connection/ADC output/Black level reset/Power down Clamp current/ADIN clamp/Clamp target/S/H, enable logic/Monitor selection CDS gain control/Black loop gain boost/Boost period PGA gain ADC code at black level (1 LSB step) Register Name Function Description Register Map Register Bit Assignment D9 Mode 1 Default Functions DOUT timing control OUTCK polarity ADCLK polarity ADIN connection Reserved ADC output Black level reset Power down Mode 2 Default Functions Clamp current ADIN clamp Clamp target S/H, enable logic Monitor selection Mode 3 Default Functions CDS gain control Black loop gain boost Boost period PGA Gain Default Functions PGA gain Black Level Default Functions Black level -------------------------------------------------X X X 1 O O O O O O ---------------------------------------------------------------X O O O O O O O O O ----√ --------------X X X X O O O O O O √ √ ------------X X O O O O O O O O √ √ √ ----√ √ √ √ X O O O O O O O O O D8 D7 D6 D5 D4 D3 D2 D1 D0 9 Ai4100 Register Operations Control D9 Mode 1 DOUT timing control OUTCK polarity 0 1 0 1 0 1 0 ADIN connection 0 1 Reserved 0 1 X 0 1 0 1 0 1 0 1 DOUT synchronizes to ADCLK DOUT synchronizes to OUTCK DOUT changes at OUTCK rising edge DOUT changes at OUTCK falling edge Normal operation as timing chart ADCLK clock inversion ADIN function OFF ADIN signal to PGA ADIN signal to ADC Reserved Reserved Normal operation, ADC data output ADC output high-Z, or logic of STBY Normal operation Black level reset, or logic of RESET Normal operation Power down, or logic of STBY D8 D7 D6 D5 D4 D3 D2 D1 D0 Operations ADCLK polarity ADC output Black level reset Power down Mode 2 Clamp current 0 1 0 1 0 Clamp target 0 1 1 0 1 0 1 0 S/H, enable logic 0 1 1 0 1 0 1 0 Monitor selection 0 1 1 Mode 3 0 CDS gain control 0 1 1 Black loop gain boost 0 1 0 1 0 1 Normal clamp ±50μA Fast clamp ±100μA Clamp operation active for ADIN No clamp for ADIN Normal mode, clamp both REFIN and CCDIN Clamp REFIN only Clamp CCDIN only Clamp off Normal operation as timing chart S/H control polarity inversion Enable control polarity inversion Both of S/H and enable inversion 0 1 0 1 Monitor off CDS signal to monitor PGA output monitor Output REFIN and CCDIN ADIN clamp CDS gain=0 dB CDS gain=6.02 dB CDS gain=12.04 dB CDS gain=-1.94 dB Boost control on Always high gain 10 Ai4100 Control Operations D9 D8 D7 D6 D5 D4 D3 0 0 0 0 Boost period 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 High gain for 4 OBP pulse High gain for 5 OBP pulse High gain for 6 OBP pulse High gain for 7 OBP pulse D2 0 0 0 0 D1 0 0 1 1 D0 0 1 0 1 Always low gain High gain for 1 OBP pulse High gain for 2 OBP pulse High gain for 3 OBP pulse Control D9 0 0 0 0 0 0 0 0 0 0 0 0 PGA gain 0 0 0 0 0 0 0 0 0 0 0 D8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 D7 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 D6 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 D5 0 0 0 0 0 ↓ 1 1 0 0 ↓ 1 0 0 ↓ 0 ↓ 1 0 0 ↓ 0 ↓ 1 0 0 ↓ 0 ↓ 1 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 D4 0 0 0 0 0 D3 0 0 0 0 0 D2 0 0 0 0 1 D1 0 0 1 1 0 D0 0 1 0 1 0 0 1 2 3 4 Decimal 0 1 2 3 4 ↓ 3E 3F 40 41 ↓ 7F 80 81 ↓ C0 ↓ FF HEX PGA Gain (dB) 0 0.046 0.093 0.142 0.187 ↓ 2.915 2.962 3.011 3.056 ↓ 5.972 6.021 6.058 ↓ 9.031 ↓ 11.994 12.041 12.087 ↓ 15.05 ↓ 18.14 18.061 18.108 ↓ 21.071 ↓ 23.987 24.032 ↓ 62 63 64 65 ↓ 127 128 129 ↓ 192 ↓ 255 256 257 ↓ 320 ↓ 383 384 385 ↓ 448 ↓ 510 511 100 101 ↓ 140 ↓ 17F 180 181 ↓ 1C0 ↓ 1FE 1FF 11 Ai4100 Operation, ADC Code D9 D8 D7 D6 0 0 D5 0 0 D4 0 0 D3 0 0 ↓ 0 0 0 0 0 Black level 0 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 ↓ 0 ↓ 1 0 0 0 ↓ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 1 1 0 1 0 1 D2 0 0 D1 0 0 D0 0 1 Decimal Forbidden 1 ↓ 15 16 17 18 19 ↓ 32 ↓ 64 ↓ 124 125 126 127 Black Code HEX Forbidden 1 ↓ F 10 11 12 13 ↓ 20 ↓ 40 ↓ 7C 7D 7E 7F TIMING DIAGRAMS tDR CCD Reference Sampling Data Sampling SHP tWD SHD tCYC ADCLK BLK OBP CCDCLP ADCLP OUTCK tOL DO0~DO9 tHOLDE tH tHOLDC tSUPOC tL tSUPE tHOLD tPSUP tSP tWR tDD 12 Ai4100 AD Conversion Timing (at ADIN (ADC) Input Mode 1 Register D5=1) Falling Edge 0.7AVDD ADCLK 0.3AVDD N+5 N+4 N+6 N+1 ADCLK Input N 0.7AVDD OUTCK 0.3AVDD tDL Digital Output N-6 N-5 N-2 N-1 N ADC Direct Input Chart ADCK Rising Edge tHOLDC ADCK Input N N+1 OUTCK tSUPOC ADCK Sampling Point ADCLK Inversion Chart OUTCK Timing Chart These figures are shown when the Mode 1 D8 bit is set to “1”, and an external clock is input to the OUTCK pin. When setting D8 bit to “0”, the ADCLK is used as OUTCK. Note : At default condition in ADIN mode, data are sampled at the falling edge of the ADCK clock, and are output at the rising edge of the OUTCK clock. Set the ADCLK polarity register to “1” when the data are sampled and are output at the falling edge of the ADCK clock. The diagram on the upper portion of this page shows the default timing and the lower left figure shows the inverted timing Delay from data sampling to data output ADCLK normal : At Mode 1 register D6=0; 5.5 clk delay ADCLK inversion : At Mode 1 register D6=1; 6.0 clk delay In ADIN input mode, the above mentioned register setting is available. At ADIN (PGA) input Mode 1 register D5=0 and D4=1, digital data output is delayed by 2 clks. ADCLK Clock Waveform tH 0.7VDD 0.3VDD tR tF tCYC tL 13 Ai4100 Control Interface Timing Test Conditions Symbol SCYC SLO SHI SSU SH SR SF SNUM Parameter VDD SCK Clock Frequency SCK Clock Low Level Width SCK Clock High Level Width Data Setup Time Period Data Hold Time Period SCK, CSN Rising Time Period SCK, CSN Falling Time Period Number of Serial Data 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 30% 70% Conditions 70% 30% 40 40 20 20 16 10 6 6 MHz ns ns ns ns ns ns pcs Min. Typ. Max. Unit (VSS = 0V, Ta = 25℃) CSN SSU SCYC SLO SHI SH 50% VDD SCK 50% VDD SSU SDATA O0 O1 A0… SNUM SH D8 D9 50% VDD Serial I/F Timing Chart Data Output Sequence CCD 0 1 2 3 4 5 6 7 8 SHP SHD ADCLK OUTCK BLK DO0~DO9 Black Level Code 0 1 2 3 Pixel Data Readout Sequence (1) : Start of Conversion 14 Ai4100 CCD (N-1) SHP N SHD ADCLK OUTCK BLK DO0~DO9 N-8 N-7 N-6 N-5 N-4 N-3 N-2 N-1 N Black Level Code Pixel Data Readout Sequence (2) : End of Conversion Clock Timing Variations by Register Setting Clock timing variations when it is inverted by register settings. • No inversion Mode 1 register D6=0, Mode 2 register D2=0; Default CCD SHP SHD ADCLK OUTCK DO0~DO9 Pulse Control (Default : No Inversion) 15 Ai4100 • ADCK inversion Mode 1 register D6=1, Mode 2 register D2=0 CCD SHP SHD ADCLK OUTCK DO0~DO9 Pulse Control (ADCLK Inversion) • SHP & SHD inversion Mode 1 register D6=0, Mode 2 register D2=1 CCD SHP SHD ADCLK OUTCK DO0~DO9 Pulse Control (SHR & SHD Inversion) • ADCLK, SHP & SHD inversion Mode 1 register D6=1, Mode 2 register D2=1 CCD SHP SHD ADCLK OUTCK DO0~DO9 Pulse Control (ADCLK, SHR & SHD Inversion) 16 Ai4100 APPLICATION CIRCUITS 0.1uF Power In DO0 DO1 DO3 DO2 DO6 DVDD2 DO4 DVSS2 DO7 DO5 DO8 DO9 Power In NC AVDD4 0.1uF NC REFB REFT 0.1uF 0.1uF AVDD3 10uF 0.1uF AVDD2 AVSS3 AVSS2 CML 0.1uF 0.1uF CCD 0.1uF OUTCK RESETN DVDD1 DVSS1 STBY Power In 0.1uF Ai4100 CSN SDATA SCK OBP CCDCLP BLK ADCLP SHD SHP ADCLK NC CCDIN REFIN MONOUT CLPCAP OBCAP AISET AVDD1 AVSS1 ADIN 0.1uF ** 0.1uF 0.1uF Note : “*” Pin 18 can also connect to ground through a 4.7K resistor. “**” The capacitor connecting to OBCAP pin may need adjustment depending on user application from 0.1uF to 1uF typically. NC * 0.1uF Power In 17 Ai4100 PKG DIMENSION 48-pin LQFP (7X7) C D 36 25 H G I 37 24 F A B E 48 13 K α J 1 12 Dimensions in mm Symbol Min. A B C D E F G H I J K α 8.90 6.90 8.90 6.90 --1.35 --0.45 0.10 0˚ Nom. ----0.50 0.20 --0.10 ---Max. 9.10 7.10 9.10 7.10 --1.45 1.60 -0.75 0.20 7˚ 18