23LC1024-I/P

23A1024/23LC1024 1Mbit SPI Serial SRAM with SDI and SQI Interface Device Selection Table Part Number VCC Range Temp. Ranges Dual I/O (SDI) Quad I/O (SQI) Max. Clock Frequency Packages 23A1024 1.7-2.2V I, E Yes Yes 20 MHz(1) SN, ST, P 23LC1024 2.5-5.5V I, E Yes Yes 20 MHz(1) SN, ST, P Note 1: 16 MHz for E-temp. Features Description • SPI Bus Interface: - SPI compatible - SDI (dual) and SQI (quad) compatible - 20 MHz Clock rate for all modes • Low-Power CMOS Technology: - Read Current: 3 mA at 5.5V, 20 MHz - Standby Current: 4 A at +85°C • Unlimited Read and Write Cycles • Zero Write Time • 128K x 8-bit Organization: - 32-byte page • Byte, Page and Sequential Mode for Reads and Writes • High Reliability • Temperature Ranges Supported: - Industrial (I): -40C to +85C - Automotive (E): -40C to +125C The Microchip Technology Inc. 23A1024/23LC1024 are 1 Mbit Serial SRAM devices. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK), a data in line (SI) and a data out line (SO). Access to the device is controlled through a Chip Select (CS) input. Additionally, SDI (Serial Dual Interface) and SQI (Serial Quad Interface) is supported if your application needs faster data rates. This device also supports unlimited reads and writes to the memory array. The 23A1024/23LC1024 is available in standard packages including 8-lead SOIC, PDIP and advanced 8-lead TSSOP. Package Types (not to scale) • RoHS Compliant SOIC/TSSOP/PDIP • 8 Lead SOIC, TSSOP and PDIP Packages Pin Function Table Name CS Function Chip Select Input Pin SO/SIO1 Serial Output/SDI/SQI Pin SIO2 SQI Pin VSS Ground Pin SI/SIO0 Serial Input/SDI/SQI Pin SCK Serial Clock Pin HOLD/SIO3 Hold/SQI Pin VCC Power Supply Pin  2012-2015 Microchip Technology Inc. CS 1 8 VCC SO/SIO1 2 7 HOLD/SIO3 SIO2 3 6 SCK VSS 4 5 SI/SIO0 DS20005142C-page 1 23A1024/23LC1024 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC .............................................................................................................................................................................6.5V All Inputs and Outputs w.r.t. VSS ........................................................................................................ -0.3V to VCC +0.3V Storage Temperature...............................................................................................................................-65°C to +150°C Ambient Temperature under Bias............................................................................................................-40°C to +125°C † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Param. No. Sym. D001 VCC D002 Industrial (I): TA = -40°C to +85°C Automotive (E): TA = -40°C to +125°C Min. Typ.(3) Max. Units Supply Voltage 1.7 — 2.2 V 23A1024 5.5 V 23LC1024 VIH High-level Input Voltage 0.7VCC — VCC + 0.3 V D003 VIL Low-level Input Voltage -0.3 — 0.2 VCC V 0.1 VCC V 23LC1024 D004 VOL Low-level Output Voltage — — 0.2 V IOL = 1 mA D005 VOH High-level Output Voltage VCC - 0.5 — — V IOH = -400 A D006 ILI Input Leakage Current — — ±1 A CS = VCC, VIN = VSS OR VCC D007 ILO Output Leakage Current — — ±1 A CS = VCC, VOUT = VSS OR VCC — 1 10 mA FCLK = 20 MHz; SO = O, 2.2V 3 10 mA FCLK = 20 MHz; SO = O, 5.5V 1 4 A CS = VCC = 2.2V, Inputs tied to VCC or VSS, I-Temp — 12 A CS = VCC = 2.2V, Inputs tied to VCC or VSS, E-Temp 4 10 A CS = VCC = 5.5V, Inputs tied to VCC or VSS, I-Temp — 20 A CS = VCC = 5.5V, Inputs tied to VCC or VSS, E-Temp Characteristic 2.5 D008 ICC Read Operating Current ICCS D009 Standby Current — Test Conditions 23A1024 D010 CINT Input Capacitance — — 7 pF VCC = 5.0V, f = 1 MHz, TA = 25°C (Note 1) D011 VDR RAM Data Retention Voltage — 1.0 — V (Note 2) Note 1: 2: 3: This parameter is periodically sampled and not 100% tested. This is the limit to which VCC can be lowered without losing RAM data. This parameter is periodically sampled and not 100% tested. Typical measurements taken at room temperature. DS20005142C-page 2  2012-2015 Microchip Technology Inc. 23A1024/23LC1024 TABLE 1-2: AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C Automotive (E): TA = -40°C to +125°C AC CHARACTERISTICS Param. Sym. No. Characteristic FCLK Clock Frequency 1 Min. Max. Units Test Conditions — 20 MHz I-Temp 16 MHz E-Temp 25 — ns I-Temp E-Temp 2 TCSS CS Setup Time 32 — ns 3 TCSH CS Hold Time 50 — ns 4 TCSD CS Disable Time 25 — ns I-Temp 32 — ns E-Temp — ns 5 TSU Data Setup Time 10 6 THD Data Hold Time 10 — ns 7 TR CLK Rise Time — 20 ns (Note 1) 8 TF CLK Fall Time — 20 ns (Note 1) 9 THI Clock High Time 25 — ns I-Temp 32 — ns E-Temp 10 TLO Clock Low Time 25 — ns I-Temp 32 — ns E-Temp 25 — ns I-Temp 11 TCLD 12 TV Clock Delay Time Output Valid from Clock Low 32 — ns E-Temp — 25 ns I-Temp 32 ns E-Temp 0 — ns (Note 1) 13 THO Output Hold Time 14 TDIS Output Disable Time — 20 ns 15 THS HOLD Setup Time 10 — ns 16 THH HOLD Hold Time 10 — ns 17 THZ HOLD Low to Output High-Z 10 — ns 18 THV HOLD High to Output Valid — 50 ns Note 1: This parameter is periodically sampled and not 100% tested. TABLE 1-3: AC TEST CONDITIONS AC Waveform Input Pulse Level 0.1 VCC to 0.9 VCC Input Rise/Fall Time 5 ns CL = 30 pF — Timing Measurement Reference Level Input 0.5 VCC Output 0.5 VCC  2012-2015 Microchip Technology Inc. DS20005142C-page 3 23A1024/23LC1024 FIGURE 1-1: HOLD TIMING CS 16 15 16 15 SCK 17 SO n+2 SI n+2 n+1 n 18 High-Impedance n 5 Don’t Care n+1 n-1 n n n-1 HOLD FIGURE 1-2: SERIAL INPUT TIMING (SPI MODE) 4 CS 2 7 11 8 3 SCK 5 SI 6 MSB in LSB in High-Impedance SO FIGURE 1-3: SERIAL OUTPUT TIMING (SPI MODE) CS 9 3 10 SCK 12 13 SO SI DS20005142C-page 4 MSB out 14 LSB out Don’t Care  2012-2015 Microchip Technology Inc. 23A1024/23LC1024 2.0 FUNCTIONAL DESCRIPTION 2.1 Principles of Operation The 23A1024/23LC1024 is an 1 Mbit Serial SRAM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PIC® microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly in firmware to match the SPI protocol. In addition, the 23A1024/23LC1024 is capable of operation in SDI and SQI modes. In SDI mode, the SI and SO data lines are bidirectional, allowing the transfer of two bits per clock pulse. In SQI mode, two additional data lines enable the transfer of four bits per clock pulse. The 23A1024/23LC1024 contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low for the entire operation. Table 2-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses and data are transferred MSB first, LSB last. 2.2 Modes of Operation The 23X1024 has three modes of operation that are selected by setting bits 7 and 6 in the MODE register. The modes of operation are Byte, Page and Burst. Byte Operation – is selected when bits 7 and 6 in the MODE register are set to 00. In this mode, the read/write operations are limited to only one byte. The Command followed by the 24-bit address is clocked into the device and the data to/from the device is transferred on the next eight clocks (Figure 2-1, Figure 2-2). Page Operation – is selected when bits 7 and 6 in the MODE register are set to 10. The 23X1024 has 4096 pages of 32 bytes. In this mode, the read and write operations are limited to within the addressed page (the address is automatically incremented internally). If the data being read or written reaches the page boundary, then the internal address counter will increment to the start of the page (Figure 2-3, Figure 2-4). 2.3 Read Sequence The device is selected by pulling CS low. The 8-bit READ instruction is transmitted to the 23A1024/23LC1024 followed by the 24-bit address, with the first seven MSB’s of the address being “don’t care” bits. After the correct READ instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. If operating in Sequential mode, the data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal Address Pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (1FFFFh), the address counter rolls over to address 00000h, allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the CS pin. 2.4 Write Sequence Prior to any attempt to write data to the 23A1024/23LC1024, the device must be selected by bringing CS low. Once the device is selected, the Write command can be started by issuing a WRITE instruction, followed by the 24-bit address, with the first seven MSB’s of the address being “don’t care” bits, and then the data to be written. A write is terminated by the CS being brought high. If operating in Page mode, after the initial data byte is shifted in, additional bytes can be shifted into the device. The Address Pointer is automatically incremented. This operation can continue for the entire page (32 bytes) before data will start to be overwritten. If operating in Sequential mode, after the initial data byte is shifted in, additional bytes can be clocked into the device. The internal Address Pointer is automatically incremented. When the Address Pointer reaches the highest address (1FFFFh), the address counter rolls over to (00000h). This allows the operation to continue indefinitely, however, previous data will be overwritten. Sequential Operation – is selected when bits 7 and 6 in the MODE register are set to 01. Sequential operation allows the entire array to be written to and read from. The internal address counter is automatically incremented and page boundaries are ignored. When the internal address counter reaches the end of the array, the address counter will roll over to 0x00000 (Figure 2-5, Figure 2-6).  2012-2015 Microchip Technology Inc. DS20005142C-page 5 23A1024/23LC1024 TABLE 2-1: INSTRUCTION SET Instruction Format Hex Code Description READ 0000 0011 0x03 Read data from memory array beginning at selected address WRITE 0000 0010 0x02 Write data to memory array beginning at selected address EDIO 0011 1011 0x3B Enter Dual I/O access (enter SDI bus mode) Instruction Name EQIO 0011 1000 0x38 Enter Quad I/O access (enter SQI bus mode) RSTIO 1111 1111 0xFF Reset Dual and Quad I/O access (revert to SPI bus mode) RDMR 0000 0101 0x05 Read Mode Register WRMR 0000 0001 0x01 Write Mode Register FIGURE 2-1: BYTE READ SEQUENCE (SPI MODE) CS 0 1 2 0 0 0 3 4 5 6 7 8 9 10 11 0 1 1 23 22 21 20 29 30 31 32 33 34 35 36 37 38 39 SCK Instruction SI 0 0 24-bit Address 2 1 0 Data Out High-Impedance 7 SO FIGURE 2-2: 6 5 4 3 2 1 0 BYTE WRITE SEQUENCE (SPI MODE) CS 0 1 2 0 0 0 3 4 8 5 6 7 9 10 11 0 1 0 23 22 21 20 29 30 31 32 33 34 35 36 37 38 39 SCK Instruction SI 0 0 24-bit Address Data Byte 2 1 0 7 6 5 4 3 2 1 0 High-Impedance SO DS20005142C-page 6  2012-2015 Microchip Technology Inc. 23A1024/23LC1024 FIGURE 2-3: PAGE READ SEQUENCE (SPI MODE) CS 0 1 2 0 0 0 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 SCK Instruction SI 0 24-bit Address 0 0 1 2 1 23 22 21 20 1 0 Page X, Word Y Page X, Word Y High-Impedance SO 7 6 5 4 3 2 1 0 CS 40 41 42 43 44 45 46 47 SCK SI Page X, Word Y+1 7 SO 6 FIGURE 2-4: 5 4 3 2 1 Page X, Word 31 0 7 6 5 4 3 2 Page X, Word 0 1 0 7 6 5 4 3 2 1 0 PAGE WRITE SEQUENCE (SPI MODE) CS 0 1 2 0 0 0 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 SCK Instruction SI 0 0 Page X, Word Y 24-bit Address 0 1 2 0 23 22 21 20 1 0 7 6 5 4 3 2 1 0 Page X, Word Y SO High-Impedance CS 40 41 42 43 44 45 46 47 SCK Page X, Word Y+1 SI SO 7 6 5 4 3 2 1 Page X, Word 0 Page X, Word 31 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 High-Impedance  2012-2015 Microchip Technology Inc. DS20005142C-page 7 23A1024/23LC1024 FIGURE 2-5: SEQUENTIAL READ SEQUENCE (SPI MODE) CS 0 1 2 0 0 0 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 SCK Instruction SI 0 0 24-bit Address 0 1 1 23 22 21 20 2 1 0 Page X, Word Y 7 SO 6 5 4 3 2 1 0 CS SCK SI Page X, Word 31 7 SO 6 5 4 3 2 Page X+1, Word 0 1 0 7 6 5 4 3 2 Page X+1, Word 1 1 0 7 6 5 4 3 2 1 0 CS SCK SI Page X+1, Word 31 SO 7 6 DS20005142C-page 8 5 4 3 2 Page X+n, Word 31 Page X+n, Word 1 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0  2012-2015 Microchip Technology Inc. 23A1024/23LC1024 FIGURE 2-6: SEQUENTIAL WRITE SEQUENCE (SPI MODE) CS 0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39 SCK Instruction SI SO 0 0 0 0 0 24-bit Address 0 1 Data Byte 1 2 0 23 22 21 20 1 0 7 6 5 4 7 6 5 3 2 1 0 High-Impedance CS 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 SCK Data Byte 2 SI SO 7 6 5 4 3 2 Data Byte n Data Byte 3 1 0 7 6 5 4 3 2 1 0 4 3 2 1 0 High-Impedance  2012-2015 Microchip Technology Inc. DS20005142C-page 9 23A1024/23LC1024 2.5 Read Mode Register Instruction (RDMR) The mode bits indicate the operating mode of the SRAM. The possible modes of operation are: 0 0 = Byte mode The Read Mode Register instruction (RDMR) provides access to the MODE register. The MODE register may be read at any time. The MODE register is formatted as follows: TABLE 2-2: 1 0 = Page mode 0 1 = Sequential mode (default operation) 1 1 = Reserved Bits 0 through 5 are reserved and should always be set to ‘0’. MODE REGISTER 7 6 5 4 3 2 1 0 W/R W/R – – – – – – 0 0 0 0 0 0 MODE MODE See Figure 2-7 for the RDMR timing sequence. W/R = writable/readable FIGURE 2-7: READ MODE REGISTER TIMING SEQUENCE (RDMR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 SCK Instruction SI 0 0 0 0 0 1 0 1 Data from MODE Register High-Impedance SO DS20005142C-page 10 7 6 5 4 3 2  2012-2015 Microchip Technology Inc. 23A1024/23LC1024 2.6 Write Mode Register Instruction (WRMR) The Write Mode Register instruction (WRMR) allows the user to write to the bits in the MODE register as shown in Table 2-2. This allows for setting of the Device operating mode. Several of the bits in the MODE register must be cleared to ‘0’. See Figure 2-8 for the WRMR timing sequence. FIGURE 2-8: WRITE MODE REGISTER TIMING SEQUENCE (WRMR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 SCK Instruction SI 0 0 0 0 Data to MODE Register 0 0 0 1 7 6 5 4 3 2 High-Impedance SO 2.7 Power-On State The 23A1024/23LC1024 powers on in the following state: • The device is in low-power Standby mode (CS = 1) • A high-to-low-level transition on CS is required to enter active state  2012-2015 Microchip Technology Inc. DS20005142C-page 11 23A1024/23LC1024 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE SOIC/PDIP/TSSOP Symbol Description Chip Select Input 1 CS 2 SO/SIO1 3 SIO2 Serial I/O 2 (SQI) 4 VSS Ground 5 SI/SIO0 6 SCK 7 HOLD/SIO3 8 VCC FIGURE 3-1: Serial Output (SPI)/Serial I/O 1 (SDI)/Serial I/O 1 (SQI) Serial Input (SPI)/Serial I/O 0 (SDI)/Serial I/O 0 (SQI) Serial Clock Input Hold/Serial I/O 3 Power Supply SPI, SDI and SQI Pin Configurations SDI Mode: SPI Mode: CS 1 8 VCC SO 2 7 HOLD NU 3 6 SCK Vss 4 5 SI Note: 3.1 CS 1 8 VCC SIO1 2 7 NU 3 6 Vss 4 5 Chip Select (CS) Serial Output, Serial I/O (SO/SIO1) The SO/SIO1 pin is used to transfer data out of the 23A1024/23LC1024 when the SPI bus is being used. When in SDI or SQI bus modes, the SO/SIO1 pin is a bidirectional I/O pin. Data is shifted out on this pin after the falling edge of the serial clock, and it is latched in on the rising edge of the serial clock. 3.3 CS 1 8 VCC HOLD SIO1 2 7 SIO3 SCK SIO2 3 6 SCK SIO0 Vss 4 5 SIO0 Pin 3 is not used in SPI and SDI modes, and should not be left floating (see Section 3.3 “Serial I/O (SIO2)”). A low level on this pin selects the device. A high level deselects the device and forces it into Standby mode. When the device is deselected, SO goes to the high-impedance state, allowing multiple parts to share the same SPI bus. After power-up, a low level on CS is required, prior to any sequence being initiated. 3.2 SQI Mode: Serial I/O 2 (SIO2) The SIO2 pin is a bidirectional I/O pin used only in SQI mode. If not using SQI bus mode, this pin should not be left floating. Deciding to pull the SIO2 pin high would allow successful recovery of the bus from SQI bus mode in case an accidental EQIO command has been registered. DS20005142C-page 12 3.4 Serial Input, Serial I/O 0 (SI/SIO0) The SI pin is used to transfer data into the device when the SPI bus is being used. When in SDI or SQI bus modes, the SI/SIO0 pin is a bidirectional I/O pin. 3.5 Serial Clock (SCK) The SCK is used to synchronize the communication between a master and the 23A1024/23LC1024. Instructions, addresses or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input. 3.6 Hold, Serial I/O 3 (HOLD/SIO3) When the device is in SQI bus mode, pin HOLD/SIO3 is a bidirectional I/O pin. When in SPI or SDI bus modes, the pin has the HOLD function. The HOLD pin is used to suspend transmission to the 23A1024/23LC1024 while in the middle of a serial sequence without having to avoid retransmitting the entire sequence over again. It must be held high any time this function is not being used. Once the device is  2012-2015 Microchip Technology Inc. 23A1024/23LC1024 selected and a serial sequence is underway, the HOLD pin may be pulled low to pause further serial communication without resetting the serial sequence. The HOLD pin should be brought low while SCK is low, otherwise the HOLD function will not be invoked until the next SCK high-to-low transition. The 23A1024/23LC1024 must remain selected during this sequence. The SI and SCK levels are “don’t cares” during the time the device is paused and any transitions on these pins will be ignored. To resume serial communication, HOLD should be brought high while the SCK pin is low, otherwise serial communication will not be resumed until the next SCK high-to-low transition. The SO line will tri-state immediately upon a high-to low transition of the HOLD pin, and will begin outputting again immediately upon a subsequent low-to-high transition of the HOLD pin, independent of the state of SCK. Hold functionality is not available when operating in SQI bus mode.  2012-2015 Microchip Technology Inc. DS20005142C-page 13 23A1024/23LC1024 4.0 DUAL AND QUAD SERIAL MODE The 23A1024/23LC1024 also supports SDI (Serial Dual) and SQI (Serial Quad) mode of operation when used with compatible master devices. As a convention for SDI mode of operation, two bits are entered per clock using the SIO0 and SIO1 pins. Bits are clocked MSB first. For SQI mode of operation, four bits of data are entered per clock, or one nibble per clock. The nibbles are clocked MSB first. 4.1 Dual Interface Mode The 23A1024/23LC1024 supports Serial Dual Input (SDI) mode of operation. To enter SDI mode the EDIO command must be clocked in (Figure 4-1). It should be noted that if the MCU resets before the SRAM, the user will need to determine the serial mode of operation of the SRAM and reset it accordingly. Byte read and write sequence in SDI mode is shown in Figure 4-2 and Figure 4-3. FIGURE 4-1: ENTER SDI MODE (EDIO) FROM SPI MODE CS 0 1 2 3 4 5 6 7 SCK SI 0 0 1 1 1 0 1 1 High-Impedance SO DS20005142C-page 14  2012-2015 Microchip Technology Inc. 23A1024/23LC1024 FIGURE 4-2: BYTE READ MODE SDI CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK 0 SIO0 0 1 22 20 18 16 14 12 10 0 0 0 0 6 4 0 2 6 24-Bit Address Instruction SIO1 8 1 23 21 19 17 15 13 11 9 Dummy Byte 7 5 1 3 4 2 0 Data Out 7 5 3 1 Note 1: Page and Sequential mode are similar in that additional bytes can be clocked out before CS is brought high. 2: The first byte read after the address will be a dummy byte. FIGURE 4-3: BYTE WRITE MODE SDI CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 SCK SIO0 0 0 0 0 22 20 18 16 14 12 10 Note: 0 0 0 6 4 2 0 6 24-Bit Address Instruction SIO1 8 1 23 21 19 17 15 13 11 9 4 2 0 Data In 7 5 3 1 7 5 3 1 Page and Sequential mode are similar in that additional bytes can be clocked in before CS is brought high.  2012-2015 Microchip Technology Inc. DS20005142C-page 15 23A1024/23LC1024 4.2 Quad Interface Mode In addition to the Serial Dual interface (SDI) mode of operation Serial Quad Interface (SQI) is also supported. In this mode the HOLD functionality is not available. To enter SQI mode the EQIO command must be clocked in (Figure 4-4). FIGURE 4-4: ENTER SQI MODE (EQIO) FROM SPI MODE CS 0 1 2 3 4 5 6 7 SCK 0 SI 0 1 1 1 0 0 0 High-Impedance SO FIGURE 4-5: BYTE READ MODE SQI CS 0 1 2 3 4 5 6 SIO0 0 1 20 16 12 8 4 SIO1 0 1 21 17 13 9 SIO2 0 0 22 18 14 SIO3 0 0 23 19 15 7 8 9 10 11 0 4 0 5 1 5 1 10 6 2 6 2 11 7 3 7 3 SCK Instruction 24-Bit Address Dummy Byte Data Out Note 1: Page and Sequential mode is similar in that additional bytes can be clocked out before CS is brought high. 2: The first byte read after the address will be a dummy byte. DS20005142C-page 16  2012-2015 Microchip Technology Inc. 23A1024/23LC1024 FIGURE 4-6: BYTE WRITE MODE SQI CS 0 1 2 3 4 5 6 7 8 9 SCK SIO0 0 0 20 16 12 8 4 0 4 0 SIO1 0 1 21 17 13 9 5 1 5 1 0 0 22 18 14 10 6 2 6 2 0 0 23 19 15 11 7 3 7 3 SIO2 SIO3 Note: 4.3 24-Bit Address Instruction Data In Page and Sequential mode are similar in that additional bytes can be clocked out before CS is brought high. Exit SDI or SQI Mode To exit from SDI mode, the RSTIO command must be issued. The command must be entered in the current device configuration, either SDI or SQI, see Figure 4-7 and Figure 4-8. FIGURE 4-7: RESET SDI MODE (RSTIO) – FROM SDI MODE CS 0 1 2 3 SCK SIO0 SIO1  2012-2015 Microchip Technology Inc. 1 1 1 1 1 1 1 1 DS20005142C-page 17 23A1024/23LC1024 FIGURE 4-8: RESET SDI/SQI MODE (RSTIO) – FROM SQI MODE CS 0 1 SCK DS20005142C-page 18 SIO0 1 1 SIO1 1 1 SIO2 1 1 SIO3 1 1  2012-2015 Microchip Technology Inc. 23A1024/23LC1024 5.0 PACKAGING INFORMATION 5.1 Package Marking Information 8-Lead PDIP Example: XXXXXXXX T/XXXNNN YYWW 23A1024 I/P e3 1L7 1343 8-Lead SOIC (3.90 mm) Example: XXXXXXXT XXXXYYWW NNN 23A1024I SN e3 1328 1L7 Example: 8-Lead TSSOP 3ABI XXXT YYWW NNN 1328 1L7 1st Line Marking Codes Part Number 23A1024 23LC1024 Note: PDIP SOIC TSSOP 23A1024 23A1024T 3ABT 23LC1024 23LCBT 3LBT T = Temperature grade (I, E) Legend: XX...X T Y YY WW NNN e3 Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code (2 characters for small packages) Pb-free JEDEC® designator for Matte Tin (Sn) Note: For very small packages with no room for the Pb-free JEDEC® designator e3 , the marking will only appear on the outer carton or reel label. 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