24LC01B-I/P

24AA01/24LC01B/24FC01 1K I2C Serial EEPROM Device Selection Table Part Number VCC Range 24AA01 1.7V-5.5V 24LC01B 2.5V-5.5V 24FC01 1.7V-5.5V Max. Clock Frequency Temp. Ranges (1) Available Packages I MC, MS, P, LT, SN, OT, MNY, ST 400 kHz I, E MC, MS, P, LT, SN, OT, MNY, ST 1 MHz I, E MS, P, SN, OT, ST, Q4B, Q6B 400 kHz Note 1: 100 kHz for VCC < 2.5V Features Description • Single Supply with Operation down to 1.7V for 24AA01 and 24FC01 Devices, 2.5V for 24LC01B Devices • Low-Power CMOS Technology: - Read current 1 mA, maximum - Standby current 1 µA, maximum (I-temp.) • Two-Wire Serial Interface, I2C Compatible • Schmitt Trigger Inputs for Noise Suppression • Output Slope Control to Eliminate Ground Bounce • 100 kHz, 400 kHz and 1 MHz Compatibility • Page Write Time: 5 ms, Maximum • Self-Timed Erase/Write Cycle • 8-Byte Page Write Buffer • Hardware Write-Protect • ESD Protection >4,000V • More than 1 Million Erase/Write Cycles • Data Retention >200 Years • Factory Programming Available • RoHS Compliant • Temperature Ranges: - Industrial (I): -40°C to +85°C - Extended (E): -40°C to +125°C • Automotive AEC-Q100 Qualified The Microchip Technology Inc. 24XX01(1) is a 1-Kbit Electrically Erasable PROM (EEPROM). The device is organized as one block of 128 x 8-bit memory with a two-wire serial interface. Its low-voltage design permits operation down to 1.7V with standby and active currents of only 1 µA and 1 mA, respectively. The 24XX01 also has a page write capability for up to 8 bytes of data. Note 1: 24XX01 is used in this document as a generic part number for the 24AA01/24LC01B/24FC01 devices. Package Types (1) A0 (1) A1 (1) A2 VSS  2007-2021 Microchip Technology Inc. 1 8 VCC 7 WP A1 (1) 6 SCL A2 2 7 WP 3 6 SCL 5 SDA VSS 4 5 SDA 8 VCC 1 2 3 4 1 8 VCC 2 7 WP A2 3 6 SCL VSS 4 5 A0 • 8-Lead DFN, 8-Lead MSOP, 8-Lead PDIP, 5-Lead SC-70, 8-Lead SOIC, 5-Lead SOT-23, 8-Lead TDFN, 8-Lead TSSOP, 8-Lead UDFN and 8-Lead Wettable Flanks UDFN (1) A0 (1) SOIC, TSSOP (Top view) (1) Packages: PDIP, MSOP (Top view) DFN/TDFN/UDFN (Top view) (1) A1 (1) Note 1: SOT-23/SC-70 (Top view) SCL 1 Vss 2 SDA SDA 3 5 WP 4 Vcc Pins A0, A1 and A2 are not used by the 24XX01 (no internal connections). DS20001711N-page 1 24AA01/24LC01B/24FC01 Block Diagram WP I/O Control Logic Memory Control Logic HV Generator XDEC EEPROM Array Page Latches I/O SCL YDEC SDA VCC VSS DS20001711N-page 2 Sense Amp. R/W Control  2007-2021 Microchip Technology Inc. 24AA01/24LC01B/24FC01 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ..........................................................................................................-0.3V to VCC +1.0V Storage temperature ............................................................................................................................... -65°C to +150°C Ambient temperature with power applied................................................................................................ -40°C to +125°C ESD protection on all pins 4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Param. Symbol No. Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V Extended (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V (24LC01B) Extended (E): TA = -40°C to +125°C, VCC = +1.7V to +5.5V (24FC01) Characteristic Min. Typ. Max. Units Conditions D1 VIH High-Level Input Voltage 0.7 VCC — — V D2 VIL Low-Level Input Voltage — — 0.3 VCC V D3 VHYS Hysteresis of Schmitt Trigger Inputs 0.05 VCC — — V D4 VOL Low-Level Output Voltage — — 0.40 V IOL = 3.0 mA, VCC = 2.5V D5 ILI Input Leakage Current — — ±1 µA VIN = VSS or VCC D6 ILO Output Leakage Current — — ±1 µA VOUT = VSS or VCC D7 CIN, COUT D8 ICCWRITE D9 ICCREAD D10 Note 1: ICCS Pin Capacitance (all inputs/outputs) Operating Current Standby Current Note 1 — — 10 pF VCC = 5.0V (Note 1) TA = +25°C, FCLK = 1 MHz — — 3 mA VCC = 5.5V, SCL = 400 kHz — — 1 mA VCC = 5.5V, SCL = 400 kHz — — 1 µA SDA = SCL = VCC WP = VSS, I-Temp. — — 3 µA SDA = SCL = VCC WP = VSS, E-Temp. (24FC01) — — 5 µA SDA = SCL = VCC WP = VSS, E-Temp. (24LC01B) This parameter is periodically sampled and not 100% tested.  2007-2021 Microchip Technology Inc. DS20001711N-page 3 24AA01/24LC01B/24FC01 TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Param. Symbol No. 1 FCLK 2 THIGH 3 TLOW 4 TR 5 TF 6 Characteristic Clock Frequency Clock High Time Clock Low Time SDA and SCL Rise Time SDA and SCL Fall Time THD:STA Start Condition Hold Time 7 TSU:STA Start Condition Setup Time 8 THD:DAT Data Input Hold Time TSU:DAT Data Input Setup Time 9 Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V Extended (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V (24LC01B) Extended (E): TA = -40°C to +125°C, VCC = +1.7V to +5.5V (24FC01) Min. Typ. Max. Units Conditions — — 400 kHz 2.5V ≤ VCC ≤ 5.5V — — 100 kHz 1.7V ≤ VCC < 2.5V (24AA01) 1.7V ≤ VCC ≤ 5.5V (24FC01) — — 1000 kHz 600 — — ns 2.5V ≤ VCC ≤ 5.5V 4000 — — ns 1.7V ≤ VCC < 2.5V (24AA01) 260 — — ns 1.7V ≤ VCC ≤ 5.5V (24FC01) 1300 — — ns 2.5V ≤ VCC ≤ 5.5V 4700 — — ns 1.7V ≤ VCC < 2.5V (24AA01) 500 — — ns 1.7V ≤ VCC ≤ 5.5V (24FC01) — — 300 ns 2.5V ≤ VCC ≤ 5.5V (Note 1) — — 1000 ns 1.7V ≤ VCC < 2.5V (24AA01) (Note 1) — — 1000 ns 1.7V ≤ VCC ≤ 5.5V (24FC01) (Note 1) — — 300 ns Note 1 600 — — ns 2.5V ≤ VCC ≤ 5.5V 4000 — — ns 1.7V ≤ VCC < 2.5V (24AA01) 250 — — ns 1.7V ≤ VCC ≤ 5.5V (24FC01) 600 — — ns 2.5V ≤ VCC ≤ 5.5V 4700 — — ns 1.7V ≤ VCC < 2.5V (24AA01) 250 — — ns 1.7V ≤ VCC ≤ 5.5V (24FC01) 0 — — ns Note 2 100 — — ns 2.5V ≤ VCC ≤ 5.5V 250 — — ns 1.7V ≤ VCC < 2.5V (24AA01) 50 — — ns 1.7V ≤ VCC ≤ 5.5V (24FC01) 600 — — ns 2.5V ≤ VCC ≤ 5.5V 4000 — — ns 1.7V ≤ VCC < 2.5V (24AA01) 10 TSU:STO Stop Condition Setup Time 250 — — ns 1.7V ≤ VCC ≤ 5.5V (24FC01) 11 TSU:WP WP Setup Time 0 — — ns 1.7V ≤ VCC ≤ 5.5V (24FC01) 12 THD:WP WP Hold Time 1000 — — ns 1.7V ≤ VCC ≤ 5.5V (24FC01) — — 900 ns 2.5V ≤ VCC ≤ 5.5V (Note 2) — — 3500 ns 1.7V ≤ VCC < 2.5V (24AA01) (Note 2) — — 450 ns 1.7V ≤ VCC ≤ 5.5V (24FC01) (Note 2) 13 TAA Note 1: 2: 3: 4: Output Valid from Clock Characterized but not 100% tested. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. CB = total capacitance of one bus line in pF. This parameter is not tested but ensured by characterization. DS20001711N-page 4  2007-2021 Microchip Technology Inc. 24AA01/24LC01B/24FC01 TABLE 1-2: AC CHARACTERISTICS (CONTINUED) Industrial (I): TA = -40°C to +85°C, VCC = +1.7V to +5.5V Extended (E): TA = -40°C to +125°C, VCC = +2.5V to +5.5V (24LC01B) Extended (E): TA = -40°C to +125°C, VCC = +1.7V to +5.5V (24FC01) AC CHARACTERISTICS (Continued) Param. Symbol No. 14 TBUF 15 Characteristic Min. Bus Free Time: The time the bus must be free before a new transmission can start 1300 — — ns 2.5V ≤ VCC ≤ 5.5V 4700 — — ns 1.7V ≤ VCC < 2.5V (24AA01) 500 — — ns 1.7V ≤ VCC ≤ 5.5V (24FC01) 20+0.1CB — 250 ns 2.5V ≤ VCC ≤ 5.5V (24LC01B) (Note 1 and Note 3) — — 250 ns 1.7V ≤ VCC < 2.5V (24AA01) (Note 4) Note 1 Output Fall Time from VIH Minimum to VIL Maximum TOF Typ. Max. Units 16 TSP Input Filter Spike Suppression (SDA and SCL pins) — — 50 ns 17 TWC Write Cycle Time (byte or page) — — 5 ms 1,000,000 — — 18 Endurance Note 1: 2: 3: 4: cycles +25°C, 5.5V, Page Mode (Note 4) Characterized but not 100% tested. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. CB = total capacitance of one bus line in pF. This parameter is not tested but ensured by characterization. FIGURE 1-1: BUS TIMING DATA 5 SCL Conditions 7 SDA IN 3 4 D3 2 8 10 9 6 16 14 13 SDA OUT WP  2007-2021 Microchip Technology Inc. (protected) (unprotected) 11 12 DS20001711N-page 5 24AA01/24LC01B/24FC01 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: Name PIN FUNCTION TABLE SOT-23 TDFN(1) TSSOP UDFN(1) DFN MSOP PDIP SC-70 SOIC Description A0 1 1 1 — 1 — 1 1 1 Not Connected A1 2 2 2 — 2 — 2 2 2 Not Connected A2 3 3 3 — 3 — 3 3 3 Not Connected VSS 4 4 4 2 4 2 4 4 4 Ground SDA 5 5 5 3 5 3 5 5 5 Serial Address/Data I/O SCL 6 6 6 1 6 1 6 6 6 Serial Clock WP 7 7 7 5 7 5 7 7 7 Write-Protect Input VCC 8 8 8 4 8 4 8 8 8 Power Supply Note 1: The exposed pad on the TDFN/UDFN package can be connected to VSS or left floating. 2.1 A0, A1, A2 2.3 Serial Clock (SCL) The A0, A1 and A2 pins are not used by the 24XX01. They may be left floating or tied to either VSS or VCC. The SCL input is used to synchronize the data transfer to and from the device. 2.2 2.4 Serial Address/Data Input/Output (SDA) The SDA input is a bidirectional pin used to transfer addresses and data into and out of the device. Since it is an open-drain terminal, the SDA bus requires a pull-up resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for 400 kHz and 1 MHz). For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating Start and Stop conditions. DS20001711N-page 6 Write-Protect (WP) This pin must be connected to either VSS or VCC. If tied to VSS, normal memory operation is enabled (read/write the entire memory 00-7F). If tied to VCC, write operations are inhibited. The entire memory will be write-protected. Read operations are not affected.  2007-2021 Microchip Technology Inc. 24AA01/24LC01B/24FC01 3.0 FUNCTIONAL DESCRIPTION The 24XX01 supports a bidirectional, two-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, while defining a device receiving data as a receiver. The bus has to be controlled by a host device which generates the Serial Clock (SCL), controls the bus access and generates the Start and Stop conditions, while the 24XX01 works as client. Both host and client can operate as transmitter or receiver, but the host device determines which mode is activated. 4.0 BUS CHARACTERISTICS The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 4-1). 4.1 4.4 The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of data bytes transferred between the Start and Stop conditions is determined by the host device and is, theoretically, unlimited (although only the last eight will be stored when doing a write operation). When an overwrite does occur, it will replace data based on the First-In First-Out (FIFO) principle. 4.5 Both data and clock lines remain high. 4.2 Start Data Transfer (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. 4.3 Stop Data Transfer (C) A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition. FIGURE 4-1: (A) Acknowledge Each receiving device, when addressed, is obliged to generate an Acknowledge after the reception of each byte. The host device must generate an extra clock pulse which is associated with this Acknowledge bit. Note: Bus Not Busy (A) Data Valid (D) The 24XX01 does not generate any Acknowledge bits if an internal programming cycle is in progress. The device that acknowledges has to pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable-low during the high period of the Acknowledge-related clock pulse. Moreover, setup and hold times must be taken into account. During reads, a host must signal an end of data to the client by not generating an Acknowledge bit on the last byte that has been clocked out of the client. In this case, the client (24XX01) will leave the data line high to enable the host to generate the Stop condition. DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (D) Start Condition Address or Acknowledge Valid (D) (C) (A) SCL SDA  2007-2021 Microchip Technology Inc. Data Allowed to Change Stop Condition DS20001711N-page 7 24AA01/24LC01B/24FC01 5.0 DEVICE ADDRESSING FIGURE 5-1: A control byte is the first byte received following the Start condition from the host device. The control byte consists of a four-bit control code. For the 24XX01, this is set as ‘1010’ binary for read and write operations. The next three bits of the control byte are “don’t cares” for the 24XX01. The combination of the 4-bit control code and the next three bits are called the client address. The last bit of the control byte is the Read/Write (R/W) bit and it defines the operation to be performed. When set to ‘1’, a read operation is selected. When set to ‘0’, a write operation is selected. Following the Start condition, the 24XX01 monitors the SDA bus, checking the device type identifier being transmitted. Upon receiving a valid client address and the R/W bit, the client device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24XX01 will select a read or write operation. CONTROL BYTE ALLOCATION Read/Write Bit Block Select Bits Control Code S 1 0 1 0 x x x R/W ACK Client Address Acknowledge Bit Start Bit x = “don’t care” The next byte received defines the address of the first data byte within the selected block (Figure 5-2). Because only A6…A0 are used, the upper address bit is a “don’t care”. Operation Control Code Block Select R/W Read 1010 Block Address 1 Write 1010 Block Address 0 FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS Control Byte 1 0 1 Control Code 0 x x Word Address Byte x R/W x A 6 • • • • • A 0 Block Select bits x = “don’t care” DS20001711N-page 8  2007-2021 Microchip Technology Inc. 24AA01/24LC01B/24FC01 6.0 WRITE OPERATION 6.1 Byte Write 6.2 Following the Start condition from the host, the device code (4 bits), the block address (3 bits, “don’t cares”) and the R/W bit, which is a logic-low, is placed onto the bus by the host transmitter. This indicates to the addressed client receiver that a byte with a word address will follow after it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the host is the word address and will be written into the Address Pointer of the 24XX01. After receiving another Acknowledge signal from the 24XX01, the host device will transmit the data word to be written into the addressed memory location. The 24XX01 acknowledges again and the host generates a Stop condition. This initiates the internal write cycle and during this time, the 24XX01 will not generate Acknowledge signals (Figure 6-1). Page Write The write control byte, word address and first data byte are transmitted to the 24XX01 in the same way as in a byte write. However, instead of generating a Stop condition, the host transmits up to 8 data bytes to the 24XX01, which are temporarily stored in the on-chip page buffer and will be written into the memory once the host has transmitted a Stop condition. Upon receipt of each word, the three lower-order Address Pointer bits, which form the byte counter, are internally incremented by one. The higher-order five bits of the word address remain constant. If the host should transmit more than eight words prior to generating the Stop condition, the Address Pointer will roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop condition is received, an internal write cycle will begin (Figure 6-2). Note: 6.3 Page write operations are limited to writing bytes within a single physical page regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of page size – 1. If a page write command attempts to write across a physical page boundary, the result is that the data wrap around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. Write Protection The WP pin allows the user to write-protect the entire array (00-7F) when the pin is tied to VCC. If tied to VSS, the write protection is disabled. FIGURE 6-1: BYTE WRITE Bus Activity Host S T A R T SDA Line S Control Byte 1 0 1 0 Bus Activity x = “don’t care”  2007-2021 Microchip Technology Inc. x x Word Address S T O P Data x 0 Block Select Bits P A C K A C K A C K DS20001711N-page 9 24AA01/24LC01B/24FC01 FIGURE 6-2: PAGE WRITE Bus Activity Host S T A R T SDA Line S 10 10 x x x0 Bus Activity x = “don’t care” DS20001711N-page 10 Control Byte Block Select Bits Word Address (n) Data (n) S T O P Data (n + 7) Data (n + 1) P A C K A C K A C K A C K A C K  2007-2021 Microchip Technology Inc. 24AA01/24LC01B/24FC01 7.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a write command has been issued from the host, the device initiates the internally-timed write cycle. ACK polling can then be initiated immediately. This involves the host sending a Start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, no ACK will be returned. If the cycle is complete, the device will return the ACK and the host can then proceed with the next read or write operation. See Figure 7-1 for a flow diagram of this operation. FIGURE 7-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? No Yes Next Operation  2007-2021 Microchip Technology Inc. DS20001711N-page 11 24AA01/24LC01B/24FC01 8.0 READ OPERATION 8.3 Sequential Read Read operations are initiated in the same way as write operations, with the exception that the R/W bit of the client address is set to ‘1’. There are three basic types of read operations: current address read, random read and sequential read. Sequential reads are initiated in the same way as a random read, except that once the 24XX01 transmits the first data byte, the host issues an Acknowledge (as opposed to a Stop condition in a random read). This directs the 24XX01 to transmit the next sequentially addressed 8-bit word (Figure 8-3). 8.1 To provide sequential reads the 24XX01 contains an internal Address Pointer which is incremented by one at the completion of each operation. This Address Pointer allows the entire memory contents to be serially read during one operation. Current Address Read The 24XX01 contains an Address Pointer that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the client address with R/W bit set to ‘1’, the 24XX01 issues an Acknowledge and transmits the 8-bit data word. The host will not acknowledge the transfer, but does generate a Stop condition and the 24XX01 discontinues transmission (Figure 8-1). 8.2 8.4 Noise Protection The SCL and SDA inputs have Schmitt Trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. Random Read Random read operations allow the host to access any memory location in a random manner. To perform this type of read operation, the word address must first be set. This is accomplished by sending the word address to the 24XX01 as part of a write operation. Once the word address is sent, the host generates a Start condition following the Acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. The host then issues the control byte again, but with the R/W bit set to a ‘1’. The 24XX01 will then issue an Acknowledge and transmits the 8-bit data word. The host will not acknowledge the transfer, but does generate a Stop condition and the 24XX01 discontinues transmission (Figure 8-2). FIGURE 8-1: CURRENT ADDRESS READ Bus Activity Host S T A R T SDA Line S 1 0 1 0 x x x 1 Bus Activity x = “don’t care” DS20001711N-page 12 Control Byte Block Select Bits S T O P Data (n) P A C K N o A C K  2007-2021 Microchip Technology Inc. 24AA01/24LC01B/24FC01 FIGURE 8-2: RANDOM READ S T Control A Byte R T S 10 1 0 x x x 0 Bus Activity Host SDA Line Control Byte A C K Block Select Bits A C K x = “don’t care” FIGURE 8-3: Bus Activity Host SDA Line Bus Activity S T O P P Data (n) S1010 xxx 1 A Block C Select K Bits Bus Activity S T A R T Word Address (n) N o A C K SEQUENTIAL READ Control Byte Data (n) Data (n + 1) Data (n + 2) S T O P Data (n + x) P 1 A C K  2007-2021 Microchip Technology Inc. A C K A C K A C K N o A C K DS20001711N-page 13 24AA01/24LC01B/24FC01 9.0 PACKAGING INFORMATION 9.1 Package Marking Information* 8-Lead 2x3 DFN Example XXX YWW NN 214 120 13 8-Lead MSOP Example XXXXXX YWWNNN 4L1BI 12013F 8-Lead PDIP (300 mil) Example XXXXXXXX T/XXXNNN YYWW 24LC01B I/P e3 13F 2120 5-Lead SC-70 Example XXNN B13F 8-Lead SOIC (3.90 mm) Example XXXXXXXX XXXXYYWW 24LC01BI SN e3 2120 NNN 13F DS20001711N-page 14  2007-2021 Microchip Technology Inc. 24AA01/24LC01B/24FC01 5-Lead SOT-23 (1-Line Marking) XXNN 5-Lead SOT-23 (2-Line Marking) XXXXYY WWNNN 8-Lead 2x3 TDFN XXX YWW NN 8-Lead TSSOP Example 2K3F Example AAEU21 2013F Example A14 120 13 Example XXXX 4L1B XYWW I120 NNN 13F 8-Lead 2x3 UDFN (Q4B) Example XXX YWW NN ADM 120 13 8-Lead 2x3 UDFN (Q6B) Example XXX YWW NN AAJ 120 13  2007-2021 Microchip Technology Inc. DS20001711N-page 15 24AA01/24LC01B/24FC01 Part Number 1st Line Marking Codes 24AA01 24LC01B TSSOP MSOP 4A01 4A01T(1) 4L1B (1) 4L1BT — — 24FC01 AADP Note 1: T = Temperature grade (I, E) 2: 3: 4: 24FC01 UDFN UDFN (Q4B) (Q6B) ADM SOT-23 DFN I-Temp E-Temp — B1NN(2,3) — — (2,3) AAJ M1NN AAEUYY (4) N1NN AAEUYY (4) SC-70 I-Temp E-Temp I-Temp E-Temp 211 (2,3) TDFN — A11 — 214 215 A14 A15 — — — — I-Temp E-Temp B2NN(2) — B1NN — (2) B3NN(2) — NN = Alphanumeric traceability code These parts use the 1-line SOT-23 marking format These parts use the 2-line SOT-23 marking format Legend: XX...X T Y YY WW NNN e3 Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code (2 characters for small packages) JEDEC® designator for Matte Tin (Sn) * Standard OTP marking consists of Microchip part number, year code, week code, and traceability code. Note: For very small packages with no room for the JEDEC® designator e3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS20001711N-page 16  2007-2021 Microchip Technology Inc. 24AA01/24LC01B/24FC01 /HDG3ODVWLF'XDO)ODW1R/HDG3DFNDJH0&[[PP%RG\>')1@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ ' $ % 1 '$780$ '$780% ( 127( ;  &  ;  &  7239,(:  & & $ $ 6($7,1* 3/$1( ; $  & 6,'(9,(: '  127(  & $ %   & $ % ( . / 1 ;E H %277209,(:   & $ % & 0LFURFKLS7HFKQRORJ\'UDZLQJ&5HY(6KHHWRI  2007-2021 Microchip Technology Inc. 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