24LC128-E/P

24AA128/24LC128/24FC128 128-Kbit I2C Serial EEPROM Device Selection Table VCC Range Maximum Clock Frequency 24AA128 1.7V-5.5V 400 kHz(1) I 24LC128 2.5V-5.5V 400 kHz I, E MF, MS, P, SN, SM, MNY, ST 24FC128 1.7V-5.5V 1 MHz(2) I MF, MS, P, SN, SM, MNY, ST Part Number Note 1: 2: Temperature Ranges Available Packages MF, MS, P, SN, SM, MNY, ST 100 kHz for VCC < 2.5V. 400 kHz for VCC < 2.5V. Features Description • Single Supply with Operation down to 1.7V for 24AA128/24FC128 devices, 2.5V for 24LC128 Devices • Low-Power CMOS Technology: - Write current 3 mA, maximum - Standby current 1 µA, maximum (I-temp.) • Two-Wire Serial Interface, I2C Compatible • Cascadable up to Eight Devices • Schmitt Trigger Inputs for Noise Suppression • Output Slope Control to Eliminate Ground Bounce • 100 kHz, 400 kHz and 1 MHz Compatibility • Page Write Time: 5 ms, Maximum • Self-Timed Erase/Write Cycle • 64-Byte Page Write Buffer • Hardware Write-Protect • ESD Protection > 4,000V • More than 1 Million Erase/Write Cycles • Data Retention > 200 years • Factory Programming Available • RoHS Compliant • Temperature Ranges: - Industrial (I): -40C to +85C - Extended (E) -40C to +125C The Microchip Technology Inc. 24XX128(1) is a 16K x 8 (128 Kbit) Serial Electrically Erasable PROM (EEPROM), capable of operation across a broad voltage range (1.7V to 5.5V). It has been developed for advanced, low-power applications such as personal communications or data acquisition. This device also has a page write capability of up to 64 bytes of data. This device is capable of both random and sequential reads up to the 128K boundary. Functional address lines allow up to eight devices on the same bus, for up to 1 Mbit address space. Note 1: 24XX128 is used in this document as a generic part number for the 24AA128/24LC128/24FC128 devices. Package Types PDIP/MSOP (1) 1 A1 2 A2 3 VSS 4 8 VCC A0 1 7 WP A1 2 A2 3 VSS 4 6 SCL 5 SDA 8 VCC 7 WP 6 SCL 5 SDA Packages • 8-Lead DFN, 8-Lead MSOP, 8-Lead PDIP, 8-Lead SOIC, 8-Lead SOIJ, 8-Lead TDFN and 8-Lead TSSOP Note 1: A0 1 A1 2 A2 3 VSS 4 24XX128 SOIC/SOIJ/TSSOP • Automotive AEC-Q100 Qualified  2010-2021 Microchip Technology Inc. and its subsidiaries 24XX128 A0 24XX128 DFN/TDFN 8 VCC 7 WP 6 SCL 5 SDA Pins A0 and A1 are no-connects for the MSOP package only. DS20001191U-page 1 24AA128/24LC128/24FC128 Block Diagram A0 A1 A2 WP I/O Control Logic Memory Control Logic HV Generator XDEC EEPROM Array Page Latches I/O SCL YDEC SDA VCC VSS DS20001191U-page 2 Sense Amp. R/W Control  2010-2021 Microchip Technology Inc. and its subsidiaries 24AA128/24LC128/24FC128 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VCC +1.0V Storage temperature ............................................................................................................................... -65°C to +150°C Ambient temperature with power applied................................................................................................ -40°C to +125°C ESD protection on all pins  4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Industrial (I): Extended (E): DC CHARACTERISTICS Param. Symbol No. D1 VIH Characteristic High-Level Input Voltage Minimum VCC = +1.7V to 5.5V TA = -40°C to +85°C VCC = +2.5V to 5.5V TA = -40°C to +125°C Maximum Units Conditions 0.7 VCC — V — 0.3 VCC V VCC 2.5V — 0.2 VCC V VCC < 2.5V 0.05 VCC — V VCC  2.5V (Note 1) D2 VIL Low-Level Input Voltage D3 VHYS Hysteresis of Schmitt Trigger Inputs (SDA, SCL pins) D4 VOL Low-Level Output Voltage — 0.40 V IOL = 3.0 mA @ VCC = 4.5V IOL = 2.1 mA @ VCC = 2.5V D5 ILI Input Leakage Current — ±1 µA VIN = VSS or VCC, WP = VSS VIN = VSS or VCC, WP = VCC D6 ILO Output Leakage Current — ±1 µA VOUT = VSS or VCC D7 CIN, COUT Pin Capacitance (all inputs/outputs) — 10 pF VCC = 5.0V (Note 1) TA = +25°C, FCLK = 1 MHz D8 ICC Read — 400 µA VCC = 5.5V, SCL = 400 kHz D9 ICC Write — 3 mA VCC = 5.5V — 1 µA SDA = SCL = VCC = 5.5V A0, A1, A2, WP = VSS, I-Temp — 5 µA SDA = SCL = VCC = 5.5V A0, A1, A2, WP = VSS, E-Temp D10 Note 1: ICCS Operating Current Standby Current This parameter is periodically sampled and not 100% tested.  2010-2021 Microchip Technology Inc. and its subsidiaries DS20001191U-page 3 24AA128/24LC128/24FC128 TABLE 1-2: AC CHARACTERISTICS Industrial (I): Extended (E): AC CHARACTERISTICS Param. Symbol No. 1 FCLK 2 THIGH 3 TLOW 4 TR 5 TF Characteristic Clock Frequency Clock High Time Clock Low Time SDA and SCL Rise Time SDA and SCL Fall Time THD:STA Start Condition Hold Time 6 7 TSU:STA Start Condition Setup Time 8 THD:DAT Data Input Hold Time 9 TSU:DAT Data Input Setup Time TSU:STO Stop Condition Setup Time 10 Note 1: 2: 3: 4: VCC = +1.7V to 5.5V TA = -40°C to +85°C VCC = +2.5V to 5.5V TA = -40°C to +125°C Minimum Maximum Units Conditions — 100 kHz 1.7V  VCC  2.5V — 400 kHz 2.5V  VCC  5.5V — 400 kHz 1.7V  VCC  2.5V (24FC128) — 1000 kHz 2.5V  VCC  5.5V (24FC128) 4000 — ns 1.7V  VCC  2.5V 600 — ns 2.5V  VCC  5.5V 600 — ns 1.7V  VCC  2.5V (24FC128) 500 — ns 2.5V  VCC  5.5V (24FC128) 4700 — ns 1.7V  VCC  2.5V 1300 — ns 2.5V  VCC  5.5V 1300 — ns 1.7V  VCC  2.5V (24FC128) 500 — ns 2.5V  VCC  5.5V (24FC128) — 1000 ns 1.7V  VCC  2.5V (Note 1) — 300 ns 2.5V  VCC  5.5V (Note 1) — 300 ns 1.7V  VCC  5.5V (24FC128) (Note 1) — 300 ns All except, 24FC128 (Note 1) — 100 ns 1.7V  VCC  5.5V (24FC128) (Note 1) 4000 — ns 1.7V  VCC  2.5V 600 — ns 2.5V  VCC  5.5V 600 — ns 1.7V  VCC  2.5V (24FC128) 250 — ns 2.5V  VCC  5.5V (24FC128) 4700 — ns 1.7V  VCC  2.5V 600 — ns 2.5V  VCC  5.5V 600 — ns 1.7V  VCC  2.5V (24FC128) 250 — ns 2.5V  VCC  5.5V (24FC128) 0 — ns Note 2 250 — ns 1.7V  VCC  2.5V 100 — ns 2.5V  VCC  5.5V 100 — ns 1.7V  VCC  5.5V (24FC128) 4000 — ns 1.7V  VCC  2.5V 600 — ns 2.5V  VCC  5.5V 600 — ns 1.7V  VCC  2.5V (24FC128) 250 — ns 2.5V  VCC  5.5V (24FC128) Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. This parameter is not tested but ensured by characterization. DS20001191U-page 4  2010-2021 Microchip Technology Inc. and its subsidiaries 24AA128/24LC128/24FC128 TABLE 1-2: AC CHARACTERISTICS (CONTINUED) Industrial (I): Extended (E): AC CHARACTERISTICS Param. Symbol No. 11 TSU:WP THD:WP 12 13 TAA 14 TBUF Characteristic WP Setup Time WP Hold Time Output Valid From Clock Bus Free Time: The Time The Bus Must Be Free Before a New Transmission Can Start VCC = +1.7V to 5.5V TA = -40°C to +85°C VCC = +2.5V to 5.5V TA = -40°C to +125°C Minimum Maximum Units Conditions 4000 — ns 1.7V  VCC  2.5V 600 — ns 2.5V  VCC  5.5V 600 — ns 1.7V  VCC  5.5V (24FC128) 4700 — ns 1.7V  VCC  2.5V 1300 — ns 2.5V  VCC  5.5V 1300 — ns 1.7V  VCC  5.5V (24FC128) — 3500 ns 1.7V  VCC  2.5V (Note 2) — 900 ns 2.5V  VCC  5.5V (Note 2) — 900 ns 1.7V  VCC  2.5V (24FC128) (Note 2) — 400 ns 2.5V  VCC  5.5V (24FC128) (Note 2) 4700 — ns 1.7V  VCC  2.5V 1300 — ns 2.5V  VCC  5.5V 1300 — ns 1.7V  VCC  2.5V (24FC128) 500 — ns 2.5V  VCC  5.5V (24FC128) 10 + 0.1CB 250 ns All except, 24FC128 (Note 1) TOF Output Fall Time from VIH Minimum to VIL Maximum CB  100 pF — 250 ns 24FC128 (Note 1) 16 TSP Input Filter Spike Suppression (SDA and SCL pins) — 50 ns All except, 24FC128 (Notes 1 and Note 3) 17 TWC Write Cycle Time (byte or page) — 5 ms 1,000,000 — 15 18 Endurance Note 1: 2: 3: 4: cycles +25°C, 5.5V, Page Mode (Note 4) Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. This parameter is not tested but ensured by characterization.  2010-2021 Microchip Technology Inc. and its subsidiaries DS20001191U-page 5 24AA128/24LC128/24FC128 FIGURE 1-1: BUS TIMING DATA 5 SCL 7 SDA IN 3 4 D3 2 8 10 9 6 16 14 13 SDA OUT WP DS20001191U-page 6 (protected) (unprotected) 11 12  2010-2021 Microchip Technology Inc. and its subsidiaries 24AA128/24LC128/24FC128 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: Name PIN FUNCTION TABLE DFN (1) MSOP PDIP SOIC SOIJ TDFN(1) TSSOP Function A0 1 — 1 1 1 1 1 User Configurable Chip Select A1 2 — 2 2 2 2 2 User Configurable Chip Select A2 3 3 3 3 3 3 3 User Configurable Chip Select VSS 4 4 4 4 4 4 4 Ground SDA 5 5 5 5 5 5 5 Serial Address/Data I/O SCL 6 6 6 6 6 6 6 Serial Clock WP 7 7 7 7 7 7 7 Write-Protect Input VCC 8 8 8 8 8 8 8 Power Supply Note 1: 2.1 The exposed pad on the DFN/TDFN package can be connected to VSS or left floating. A0, A1, A2 Chip Address Inputs The A0, A1 and A2 inputs are used by the 24XX128 for multiple device operations. The levels on these inputs are compared with the corresponding bits in the client address. The chip is selected if the compare is true. Note: For the MSOP package only, pins A0 and A1 are not connected. Up to eight devices (two for the MSOP package) may be connected to the same bus by using different Chip Select bit combinations. These inputs must be connected to either VCC or VSS. 2.3 Serial Clock (SCL) This input is used to synchronize the data transfer to and from the device. 2.4 Write-Protect (WP) This pin must be connected to either VSS or VCC. If tied to VSS, write operations are enabled. If tied to VCC, write operations are inhibited but read operations are not affected. In most applications, the chip address inputs A0, A1 and A2 are hardwired to logic ‘0’ or logic ‘1’. For applications in which these pins are controlled by a microcontroller or other programmable device, the chip address pins must be driven to logic ‘0’ or logic ‘1’ before normal device operation can proceed. 2.2 Serial Data (SDA) This is a bidirectional pin used to transfer addresses and data into and out of the device. It is an open-drain terminal. Therefore, the SDA bus requires a pull-up resistor to VCC (typical 10 k for 100 kHz, 2 k for 400 kHz and 1 MHz). For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions.  2010-2021 Microchip Technology Inc. and its subsidiaries DS20001191U-page 7 24AA128/24LC128/24FC128 3.0 FUNCTIONAL DESCRIPTION The 24XX128 supports a bidirectional two-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The bus must be controlled by a host device which generates the Serial Clock (SCL), controls the bus access and generates the Start and Stop conditions while the 24XX128 works as a client. Both host and client can operate as a transmitter or receiver, but the host device determines which mode is activated. 4.0 BUS CHARACTERISTICS The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 4-1). 4.1 4.4 Data Valid (D) The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the host device and is, theoretically, unlimited (although only the last 64 will be stored when doing a write operation). When an overwrite does occur, it will replace data in a First-In First-Out (FIFO) principle. 4.5 Acknowledge Each receiving device, when addressed, is obliged to generate an Acknowledge signal after the reception of each byte. The host device must generate an extra clock pulse, which is associated with this Acknowledge bit. Note: Bus Not Busy (A) The 24XX128 does not generate any Acknowledge bits if an internal programming cycle is in progress. Both data and clock lines remain high. 4.2 Start Data Transfer (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. 4.3 Stop Data Transfer (C) A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must end with a Stop condition. FIGURE 4-1: (A) A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable-low during the high period of the Acknowledge-related clock pulse. Moreover, setup and hold times must be taken into account. During reads, a host must signal an end of data to the client by not generating an Acknowledge bit on the last byte that has been clocked out of the client. In this case, the client (24XX128) will leave the data line high to enable the host to generate the Stop condition. DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (D) Start Condition Address or Acknowledge Valid (D) (C) (A) SCL SDA DS20001191U-page 8 Data Allowed to Change Stop Condition  2010-2021 Microchip Technology Inc. and its subsidiaries 24AA128/24LC128/24FC128 FIGURE 4-2: ACKNOWLEDGE TIMING Acknowledge Bit SCL SDA 1 2 3 4 5 6 7 Data from transmitter Transmitter must release the SDA line at this point, allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data.  2010-2021 Microchip Technology Inc. and its subsidiaries 8 9 1 2 3 Data from transmitter Receiver must release the SDA line at this point, allowing the Transmitter to continue sending data. DS20001191U-page 9 24AA128/24LC128/24FC128 5.0 DEVICE ADDRESSING FIGURE 5-1: A control byte is the first byte received following the Start condition from the host device. The control byte consists of a 4-bit control code. For the 24XX128, this is set as ‘1010’ binary for read and write operations. The next three bits of the control byte are the Chip Select bits (A2, A1, A0). The Chip Select bits allow the use of up to eight 24XX128 devices on the same bus and are used to select which device is accessed. The Chip Select bits in the control byte must correspond to the logic levels on the corresponding A2, A1 and A0 pins for the device to respond. These bits, in effect, are the three Most Significant bits of the word address. The combination of the 4-bit control code and the next three bits are called the client address. For the MSOP package, the A0 and A1 pins are not connected. During device addressing, the A0 and A1 Chip Select bits (Figure 5-1 and Figure 5-2) should be set to ‘0’. Only two 24XX128 MSOP packages can be connected to the same bus. The last bit of the control byte is the Read/Write (R/W) bit and it defines the operation to be performed. When set to a ‘1’, a read operation is selected. When set to a ‘0’, a write operation is selected. The next two bytes received define the address of the first data byte (Figure 5-2). Because only A13…A0 are used, the upper two address bits are “don’t care” bits. The upper address bits are transferred first, followed by the Less Significant bits. Following the Start condition, the 24XX128 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving a ‘1010’ code and appropriate device select bits, the client device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24XX128 will select a read or write operation. FIGURE 5-2: 0 1 Read/Write Bit Chip Select Bits Control Code S 1 0 1 0 A2 A1 A0 R/W ACK Client Address Start Bit 5.1 Acknowledge Bit Contiguous Addressing Across Multiple Devices The Chip Select bits A2, A1 and A0 can be used to expand the contiguous address space for up to 1 Mbit by adding up to eight 24XX128 devices on the same bus. In this case, software can use A0 of the control byte as address bit A14; A1 as address bit A15; and A2 as address bit A16. It is not possible to sequentially read across device boundaries. For the MSOP package, up to two 24XX128 devices can be added for up to 256 Kbit of address space. In this case, software can use A2 of the control byte as address bit A16. Bits A0 (A14) and A1 (A15) of the control byte must always be set to logic ‘0’ for the MSOP. ADDRESS SEQUENCE BIT ASSIGNMENTS Control Byte 1 CONTROL BYTE FORMAT 0 A 2 Control Code DS20001191U-page 10 A 1 Chip Select Bits Address High Byte A 0 R/W x x A A A A 13 12 11 10 Address Low Byte A 9 A 8 A 7 • • • • • • A 0 x = “don’t care” bit  2010-2021 Microchip Technology Inc. and its subsidiaries 24AA128/24LC128/24FC128 6.0 WRITE OPERATIONS 6.1 Byte Write once the host has transmitted a Stop condition. Upon receipt of each word, the six lower Address Pointer bits, which form the byte counter, are internally incremented by one. If the host should transmit more than 64 bytes prior to generating the Stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop condition is received, an internal write cycle will begin (Figure 6-1). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command, but no write cycle will occur, no data will be written and the device will immediately accept a new command. Following the Start condition from the host, the control code (4 bits), the Chip Select (3 bits) and the R/W bit (which is a logic low) are clocked onto the bus by the host transmitter. This indicates to the addressed client receiver that the address high byte will follow after it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the host is the high-order byte of the word address and will be written into the Address Pointer of the 24XX128. The next byte is the Least Significant Address Byte. After receiving another Acknowledge signal from the 24XX128, the host device will transmit the data word to be written into the addressed memory location. The 24XX128 acknowledges again and the host generates a Stop condition. This initiates the internal write cycle and during this time, the 24XX128 will not generate Acknowledge signals (Figure 6-1). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command, but no write cycle will occur, no data will be written and the device will immediately accept a new command. After a byte write command, the internal address counter will point to the address location following the one that was just written. Note: 6.2 Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of page size – 1. If a page write command attempts to write across a physical page boundary, the result is that the data wrap around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. It is, therefore, necessary for the application software to prevent page write operations that would attempt to cross a page boundary. When doing a write of less than 64 bytes, the data in the rest of the page are refreshed along with the data bytes being written. This will force the entire page to endure a write cycle, for this reason endurance is specified per page. 6.3 Page Write The WP pin allows the user to write-protect the entire array (0000-3FFF) when the pin is tied to VCC. If tied to VSS the write protection is disabled. The WP pin is sampled at the Stop bit for every write command (Figure 1-1). Toggling the WP pin after the Stop bit will have no effect on the execution of the write cycle. The write control byte, word address and the first data byte are transmitted to the 24XX128 in much the same way as in a byte write. The exception is that instead of generating a Stop condition, the host transmits up to 63 additional bytes, which are temporarily stored in the on-chip page buffer and will be written into memory FIGURE 6-1: Bus Activity Host SDA Line Bus Activity Write Protection BYTE WRITE S T A R T Control Byte Address High Byte AA S1010A 2 10 0 Address Low Byte S T O P Data xx A C K  2010-2021 Microchip Technology Inc. and its subsidiaries P A C K A C K A C K x = “don’t care” bit DS20001191U-page 11 24AA128/24LC128/24FC128 FIGURE 6-1: PAGE WRITE Bus Activity Host S T A R T SDA Line AAA S10102 1 00 Bus Activity Control Byte Address High Byte Address Low Byte S T O P Data Byte 63 Data Byte 0 P xx A C K A C K A C K A C K A C K x = “don’t care” bit 7.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a write command has been issued from the host, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the host sending a Start condition, followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, the Start bit and control byte must be resent. If the cycle is complete, then the device will return the ACK and the host can then proceed with the next read or write command. See Figure 7-1 for flow diagram. FIGURE 7-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? No Yes Next Operation DS20001191U-page 12  2010-2021 Microchip Technology Inc. and its subsidiaries 24AA128/24LC128/24FC128 8.0 READ OPERATION 8.2 Random read operations allow the host to access any memory location in a random manner. To perform this type of read operation, the word address must first be set. This is done by sending the word address to the 24XX128 as part of a write operation (R/W bit set to ‘0’). Once the word address is sent, the host generates a Start condition following the Acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. The host then issues the control byte again, but with the R/W bit set to a ‘1’. Read operations are initiated in much the same way as write operations with the exception that the R/W bit of the control byte is set to one. There are three basic types of read operations: current address read, random read and sequential read. 8.1 Current Address Read The 24XX128 contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous read access was to address n (n is any legal address), the next current address read operation would access data from address n + 1. The 24XX128 will then issue an Acknowledge and transmit the 8-bit data word. The host will not acknowledge the transfer but does generate a Stop condition, which causes the 24XX128 to discontinue transmission (Figure 8-2). After a random read command, the internal address counter will point to the address location following the one that was just read. Upon receipt of the control byte with R/W bit set to ‘1’, the 24XX128 issues an Acknowledge and transmits the 8-bit data word. The host will not acknowledge the transfer, but does generate a Stop condition and the 24XX128 discontinues transmission (Figure 8-1). FIGURE 8-1: S T A R T SDA Line S 1 0 1 0 A AA 1 2 1 0 P A C K FIGURE 8-2: Sequential Read Sequential reads are initiated in the same way as a random read except that after the 24XX128 transmits the first data byte, the host issues an Acknowledge (as opposed to the Stop condition used in a random read). This Acknowledge directs the 24XX128 to transmit the next sequentially addressed 8-bit word (Figure 8-3). Following the final byte transmitted to the host, the host will not generate an Acknowledge but will generate a Stop condition. S T O P Data Byte Control Byte Bus Activity N O To provide sequential reads, the 24XX128 contains an internal Address Pointer which is incremented by one at the completion of each operation. This Address Pointer allows the entire memory contents to be serially read during one operation. The internal Address Pointer will automatically roll over from address 3FFF to address 0000 if the host acknowledges the byte received from the array address 3FFF. A C K RANDOM READ S T A R T Bus Activity Host SDA Line 8.3 CURRENT ADDRESS READ Bus Activity Host Random Read Control Byte Address High Byte S1010AAA0 2 1 0 Bus Activity S T A R T Address Low Byte xx A C K x = “don’t care” bit  2010-2021 Microchip Technology Inc. and its subsidiaries A C K A C K Control Byte S 1 0 1 0 A A A1 2 1 0 S T O P Data Byte P A C K N O A C K DS20001191U-page 13 24AA128/24LC128/24FC128 FIGURE 8-3: Bus Activity Host SEQUENTIAL READ Control Byte Data (n) Data (n + 1) Data (n + 2) P SDA Line Bus Activity DS20001191U-page 14 S T O P Data (n + x) A C K A C K A C K A C K N O A C K  2010-2021 Microchip Technology Inc. and its subsidiaries 24AA128/24LC128/24FC128 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead DFN-S Example XXXXXXX XXXXXXX YYWW NNN 24LC128 I/MF 2136 13F 8-Lead MSOP Example XXXXXX 4L128I YWWNNN 13613F 8-Lead PDIP (300 mil) Example XXXXXXXX XXXXXNNN YYWW 24AA128 I/P e3 13F 2136 8-Lead SOIC (3.90 mm) XXXXXXXX XXXXYYWW NNN  2010-2021 Microchip Technology Inc. and its subsidiaries Example 24LC128I SN e3 2136 13F DS20001191U-page 15 24AA128/24LC128/24FC128 Package Marking Information (Continued) 8-Lead SOIJ (5.28 mm) Example XXXXXXXX XXXXXXXX YYWWNNN 24LC128 I/SM e3 213613F 8-Lead 2x3 TDFN Example XXX YWW NN A84 136 13 Example 8-Lead TSSOP XXXX XYWW NNN 4LC I136 13F 1st Line Marking Codes Part Number TSSOP MSOP SOIC SOIJ PDIP DFN (1) 24AA128T(1) TDFN I-Temp E-Temp 24AA128 4AC 4A128T 24AA128 24AA128 24AA128 A81 — 24LC128 4LC 4L128T(1) 24LC128T(1) 24LC128 24LC128 24LC128 A84 A85 24FC128 4FC 4F128T(1) 24FC128T(1) 24FC128 24FC128 24FC128 A8A — Note 1: T = Temperature grade (I, E) Legend: XX...X T Y YY WW NNN e3 * Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code (2 characters for small packages) JEDEC® designator for Matte Tin (Sn) Standard OTP marking consists of Microchip part number, year code, week code and traceability code. Note: For very small packages with no room for the JEDEC® designator e3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS20001191U-page 16  2010-2021 Microchip Technology Inc. and its subsidiaries 24AA128/24LC128/24FC128 /HDG3ODVWLF'XDO)ODW1R/HDG3DFNDJH0)[PP%RG\>')16@ 6DZ6LQJXODWHG 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ ' $ % 1 '$780$ '$780% ( 127( ;  &  ;  & & 6($7,1* 3/$1(  7239,(: $  & $ ; $  & 6,'(9,(:  '  & $ %   127( & $ % ( . / 1 ;E H %277209,(:   & $ % & 0LFURFKLS7HFKQRORJ\'UDZLQJ&5HY&6KHHWRI  2010-2021 Microchip Technology Inc. and its subsidiaries DS20001191U-page 17 24AA128/24LC128/24FC128 /HDG3ODVWLF'XDO)ODW1R/HDG3DFNDJH0)[PP%RG\>')16@ 6DZ6LQJXODWHG 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ 1RWHV     8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI7HUPLQDOV 1 H 3LWFK 2YHUDOO+HLJKW $ 6WDQGRII $ 7HUPLQDO7KLFNQHVV $ 2YHUDOO/HQJWK ' ([SRVHG3DG/HQJWK ' 2YHUDOO:LGWK ( ([SRVHG3DG:LGWK ( 7HUPLQDO:LGWK E 7HUPLQDO/HQJWK / . 7HUPLQDOWR([SRVHG3DG 0,1        0,//,0(7(56 120  %6&   5() %6&  %6&     0$;        3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD 3DFNDJHPD\KDYHRQHRUHPRUHH[SRVHGWLHEDUVDWHQGV 3DFNDJHLVVDZVLQJXODWHG 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(')16@ 6DZ6LQJXODWHG 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ ; (9  ‘9 &