25LC320/S

Not recommended for new designs – Please use 25AA320A or 25LC320A. 25AA320/25LC320/25C320 32K SPI Bus Serial EEPROM Device Selection Table Description: Part Number VCC Range Max. Clock Frequency 25AA320 1.8-5.5V 1 MHz I 25LC320 2.5-5.5V 2 MHz I,E 25C320 4.5-5.5V 3 MHz I,E Temp. Ranges The Microchip Technology Inc. 25AA320/25LC320/ 25C320 (25XX320*) are 32 Kbit serial Electrically Erasable PROMs. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS) input. Features: Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts. • Low-Power CMOS Technology: - Write current: 3 mA maximum - Read current: 500 μA, typical - Standby current: 500 nA, typical • 4096 x 8 Bit Organization • 32 Byte Page • Write Cycle Time: 5 ms Maximum • Self-Timed Erase and Write Cycles • Block Write Protection: - Protect none, 1/4, 1/2 or all of array • Built-in Write Protection: - Power on/off data protection circuitry - Write enable latch - Write-protect pin • Sequential Read • High Reliability: - Endurance: 1M E/W cycles - Data retention: > 200 years - ESD protection: > 4000V • 8-Pin PDIP, SOIC and TSSOP Packages • 14-Lead TSSOP Package • Temperature Ranges Supported: - Industrial (I): -40°C to +85°C - Automotive (E): -40°C to +125°C Block Diagram STATUS Register I/O Control Logic HV Generator EEPROM Array Memory Control Logic XDEC Page Latches SI Y Decoder SO CS SCK Sense Amp. R/W Control HOLD WP VCC VSS Package Types SO 2 WP 3 VSS 4 8 VCC 7 HOLD 6 SCK 5 SI HOLD 1 VCC 2 CS 3 SO 4 TSSOP 8 SCK 7 SI 6 VSS 5 WP CS SO NC NC NC WP VSS 1 2 3 4 5 6 7 25XX320 1 TSSOP 25XX320 CS 25XX320 PDIP, SOIC 14 13 12 11 10 9 8 VCC HOLD NC NC NC SCK SI *25XX320 is used in this document as a generic part number for the 25AA320/25LC320/25C320 devices. © 2008 Microchip Technology Inc. DS21227F-page 1 25AA320/25LC320/25C320 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC .............................................................................................................................................................................7.0V All inputs and outputs w.r.t. VSS ........................................................................................................ -0.6V to VCC + 1.0V Storage temperature .................................................................................................................................-65°C to 150°C Ambient temperature under bias ...............................................................................................................-40°C to 125°C ESD protection on all pins ..........................................................................................................................................4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Param. No. Sym. D1 VIH1 D2 VIH2 Characteristics High-level input voltage Low-level input voltage Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V Automotive (E):TA = -40°C to +125°C VCC = 2.5V to 5.5V Min. Max. Units Conditions 2.0 VCC+1 V VCC ≥ 2.7V (Note) 0.7 VCC VCC+1 V VCC< 2.7V (Note) -0.3 0.8 V VCC ≥ 2.7V (Note) -0.3 0.3 VCC V VCC < 2.7V (Note) D3 VIL1 D4 VIL2 D5 VOL Low-level output voltage — 0.2 V IOL = 1.0 mA, VCC < 2.5V D6 VOH High-level output voltage VCC -0.5 — V IOH = -400 μA D7 ILI Input leakage current — ±1 μA CS = VCC, VIN = VSS TO VCC D8 ILO Output leakage current — ±1 μA CS = VCC, VOUT = VSS TO VCC D9 CINT Internal Capacitance (all inputs and outputs) — 7 pF TA = 25°C, CLK = 1.0 MHz, VCC = 5.0V (Note) D10 ICC Read Operating Current — — 1 500 mA μA VCC = 5.5V; FCLK = 3.0 MHz; SO = Open VCC = 2.5V; FCLK = 2.0 MHz; SO = Open D11 ICC Write — — 5 3 mA mA VCC = 5.5V VCC = 2.5V D12 ICCS — — 5 1 μA μA CS = VCC = 5.5V, Inputs tied to VCC or VSS CS = VCC = 2.5V, Inputs tied to VCC or VSS Note: Standby Current This parameter is periodically sampled and not 100% tested. DS21227F-page 2 © 2008 Microchip Technology Inc. 25AA320/25LC320/25C320 TABLE 1-2: AC CHARACTERISTICS Industrial (I): Automotive (E): AC CHARACTERISTICS Param. No. Sym. Characteristic TA = -40°C to +85°C TA = -40°C to +125°C VCC = 1.8V to 5.5V VCC = 2.5V to 5.5V Min. Max. Units Conditions — — — 3 2 1 MHz MHz MHz VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V 1 FCLK Clock Frequency 2 TCSS CS Setup Time 100 250 500 — — — ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V 3 TCSH CS Hold Time 150 250 475 — — — ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V 4 TCSD CS Disable Time 500 — ns — 5 TSU Data Setup Time 30 50 50 — — — ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V 6 THD Data Hold Time 50 100 100 — — — ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V 7 TR CLK Rise Time — 2 TF CLK Fall Time — 2 μs μs (Note 1) 8 9 THI Clock High Time 150 230 475 — — — ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V 10 TLO Clock Low Time 150 230 475 — — — ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V 11 TCLD Clock Delay Time 50 — ns — 12 TCLE Clock Enable Time 50 — ns — 13 TV Output Valid from Clock Low — — — 150 230 — ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V 14 THO Output Hold Time 0 — ns (Note 1) 15 TDIS Output Disable Time — — — 200 250 — ns ns ns VCC = 4.5V to 5.5V (Note 1) VCC = 2.5V to 5.5V (Note 1) VCC = 1.8V to 5.5V 16 THS HOLD Setup Time 100 100 200 — — — ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V 17 THH HOLD Hold Time 100 100 200 — — — ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V 18 THZ HOLD Low to Output High-Z 100 150 200 — — — ns ns ns VCC = 4.5V to 5.5V (Note 1) VCC = 2.5V to 5.5V (Note 1) VCC = 1.8V to 5.5V 19 THV HOLD High to Output Valid 100 150 200 — — — ns ns ns VCC = 4.5V to 5.5V VCC = 2.5V to 5.5V VCC = 1.8V to 5.5V 20 TWC Internal Write Cycle Time — 5 ms — 21 — Endurance 1M — E/W Cycles (Note 1) (Note 2) Note 1: This parameter is periodically sampled and not 100% tested. 2: This parameter is not tested but established by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at: www.microchip.com. © 2008 Microchip Technology Inc. DS21227F-page 3 25AA320/25LC320/25C320 FIGURE 1-1: HOLD TIMING CS 17 16 16 17 SCK 18 SO n+2 n+1 n 19 High-Impedance n 5 Don’t Care n+2 SI n+1 n-1 n n n-1 HOLD FIGURE 1-2: SERIAL INPUT TIMING 4 CS 12 2 7 Mode 1,1 11 8 3 SCK Mode 0,0 5 SI 6 MSB in LSB in High-Impedance SO FIGURE 1-3: SERIAL OUTPUT TIMING CS 9 3 10 Mode 1,1 SCK Mode 0,0 13 14 SO SI DS21227F-page 4 MSB out 15 ISB out Don’t Care © 2008 Microchip Technology Inc. 25AA320/25LC320/25C320 TABLE 1-3: AC TEST CONDITIONS FIGURE 1-4: AC Waveform: AC TEST CIRCUIT VCC VLO = 0.2V — VHI = VCC - 0.2V (Note 1) VHI = 4.0V (Note 2) Timing Measurement Reference Level Input 0.5 VCC Output 0.5 VCC 2.25 KΩ SO 1.8 KΩ 100 pF Note 1: For VCC ≤ 4.0V 2: For VCC > 4.0V © 2008 Microchip Technology Inc. DS21227F-page 5 25AA320/25LC320/25C320 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: 2.1 PIN FUNCTION TABLE Name PDIP SOIC 8-pin TSSOP 14-lead TSSOP CS 1 1 3 1 Chip Select Input Serial Data Output SO 2 2 4 2 NC — — — 3,4,5 WP 3 3 5 6 Write-Protect Pin 4 4 6 7 Ground SI 5 5 7 8 Serial Data Input SCK 6 6 8 9 NC — — — 10,11,12 HOLD 7 7 1 13 Hold Input Vcc 8 8 2 14 Supply Voltage Chip Select (CS) Serial Output (SO) The SO pin is used to transfer data out of the 25XX320. During a read cycle, data is shifted out on this pin after the falling edge of the serial clock. 2.3 Not Connected Vss A low level on this pin selects the device. A high level deselects the device and forces it into Standby mode. However, a programming cycle which is already initiated or in progress will be completed, regardless of the CS input signal. If CS is brought high during a program cycle, the device will go into Standby mode as soon as the programming cycle is complete. When the device is deselected, SO goes to the high-impedance state, allowing multiple parts to share the same SPI bus. A low-to-high transition on CS after a valid write sequence initiates an internal write cycle. After powerup, a low level on CS is required prior to any sequence being initiated. 2.2 Description Write-Protect (WP) This pin is used in conjunction with the WPEN bit in the STATUS register to prohibit writes to the nonvolatile bits in the STATUS register. When WP is low and WPEN is high, writing to the nonvolatile bits in the STATUS register is disabled. All other operations function normally. When WP is high, all functions, including writes to the nonvolatile bits in the STATUS register operate normally. If the WPEN bit is set, WP low during a STATUS register write sequence will disable writing to the STATUS register. If an internal write cycle has already begun, WP going low will have no effect on the write. DS21227F-page 6 Serial Clock Input Not Connected The WP pin function is blocked when the WPEN bit in the STATUS register is low. This allows the user to install the 25XX320 in a system with WP pin grounded and still be able to write to the STATUS register. The WP pin functions will be enabled when the WPEN bit is set high. 2.4 Serial Input (SI) The SI pin is used to transfer data into the device. It receives instructions, addresses, and data. Data is latched on the rising edge of the serial clock. 2.5 Serial Clock (SCK) The SCK is used to synchronize the communication between a master and the 25XX320. Instructions, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input. 2.6 Hold (HOLD) The HOLD pin is used to suspend transmission to the 25XX320 while in the middle of a serial sequence without having to re-transmit the entire sequence again. It must be held high any time this function is not being used. Once the device is selected and a serial sequence is underway, the HOLD pin may be pulled low to pause further serial communication without resetting the serial sequence. The HOLD pin must be brought low while SCK is low, otherwise the HOLD function will not be invoked until the next SCK high-tolow transition. The 25XX320 must remain selected during this sequence. The SI, SCK, and SO pins are in a high-impedance state during the time the device is paused and transitions on these pins will be ignored. To resume serial communication, HOLD must be brought high while the SCK pin is low, otherwise serial communication will not resume. Lowering the HOLD line at any time will tri-state the SO line. © 2008 Microchip Technology Inc. 25AA320/25LC320/25C320 3.0 FUNCTIONAL DESCRIPTION 3.3 3.1 Principles Of Operation Prior to any attempt to write data to the 25XX320, the write enable latch must be set by issuing the WREN instruction (Figure 3-4). This is done by setting CS low and then clocking out the proper instruction into the 25XX320. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set. The 25XX320 are 4096 byte Serial EEPROMs designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PIC16C6X/7X microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly with the software. The 25XX320 contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation. Table 3-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses and data are transferred MSB first, LSB last. Data is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25XX320 in ‘HOLD’ mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted. 3.2 Read Sequence The device is selected by pulling CS low. The 8-bit READ instruction is transmitted to the 25XX320 followed by the 16-bit address, with the four MSBs of the address being “don’t care” bits. After the correct READ instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal Address Pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (0FFFh), the address counter rolls over to address 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the CS pin (Figure 3-1). TABLE 3-1: Write Sequence Once the write enable latch is set, the user may proceed by setting the CS low, issuing a WRITE instruction, followed by the 16-bit address, with the four MSBs of the address being “don’t care” bits, and then the data to be written. Up to 32 bytes of data can be sent to the 25XX320 before a write cycle is necessary. The only restriction is that all of the bytes must reside in the same page. A page address begins with xxxx xxxx xxx0 0000 and ends with xxxx xxxx xxx1 1111. If the internal address counter reaches xxxx xxxx xxx1 1111 and the clock continues, the counter will roll back to the first address of the page and overwrite any data in the page that may have been written. For the data to be actually written to the array, the CS must be brought high after the Least Significant bit (D0) of the nth data byte has been clocked in. If CS is brought high at any other time, the write operation will not be completed. Refer to Figure 3-2 and Figure 3-3 for more detailed illustrations on the byte write sequence and the page write sequence, respectively. While the write is in progress, the STATUS register may be read to check the status of the WPEN, WIP, WEL, BP1 and BP0 bits (Figure 3-6). A read attempt of a memory array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset. INSTRUCTION SET Instruction Name Instruction Format Description READ 0000 0011 Read data from memory array beginning at selected address WRITE 0000 0010 Write data to memory array beginning at selected address WRDI 0000 0100 Reset the write enable latch (disable write operations) WREN 0000 0110 Set the write enable latch (enable write operations) RDSR 0000 0101 Read STATUS register WRSR 0000 0001 Write STATUS register © 2008 Microchip Technology Inc. DS21227F-page 7 25AA320/25LC320/25C320 FIGURE 3-1: READ SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction 0 SI 0 0 0 0 16-bit Address 0 1 15 14 13 12 1 2 1 0 Data Out High-Impedance 7 SO FIGURE 3-2: 6 5 4 3 2 1 0 BYTE WRITE SEQUENCE CS Twc 0 1 2 0 0 0 3 4 5 6 7 8 9 10 11 0 1 0 15 14 13 12 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 0 0 16-bit Address Data Byte 2 1 0 7 6 5 4 3 2 1 0 High-Impedance SO FIGURE 3-3: PAGE WRITE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 SCK Instruction SI 0 0 0 0 0 16-bit Address 0 1 Data Byte 1 2 0 15 14 13 12 1 0 7 6 5 4 3 2 1 0 CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK Data Byte 2 SI 7 DS21227F-page 8 6 5 4 3 2 Data Byte 3 1 0 7 6 5 4 3 2 Data Byte n (32 max) 1 0 7 6 5 4 3 2 1 0 © 2008 Microchip Technology Inc. 25AA320/25LC320/25C320 3.4 Write Enable (WREN) and Write Disable (WRDI) The following is a list of conditions under which the write enable latch will be reset: • • • • The 25XX320 contains a write enable latch. See Table 3-3 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch, and the WRDI will reset the latch. FIGURE 3-4: Power-up WRDI instruction successfully executed WRSR instruction successfully executed WRITE instruction successfully executed WRITE ENABLE SEQUENCE CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 1 0 High-Impedance SO FIGURE 3-5: WRITE DISABLE SEQUENCE CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 10 0 High-Impedance SO © 2008 Microchip Technology Inc. DS21227F-page 9 25AA320/25LC320/25C320 3.5 Read Status Register Instruction (RDSR) The Write Enable Latch (WEL) bit indicates the status of the write enable latch. When set to a ‘1’, the latch allows writes to the array, when set to a ‘0’, the latch prohibits writes to the array. The state of this bit can always be updated via the WREN or WRDI commands regardless of the state of write protection on the STATUS register. This bit is read-only. The Read Status Register instruction (RDSR) provides access to the STATUS register. The STATUS register may be read at any time, even during a write cycle. The STATUS register is formatted as follows: 7 6 5 4 3 2 1 0 WPEN X X X BP1 BP0 WEL WIP The Block Protection (BP0 and BP1) bits indicate which blocks are currently write-protected. These bits are set by the user issuing the WRSR instruction. These bits are nonvolatile. The Write-In-Process (WIP) bit indicates whether the 25XX320 is busy with a write operation. When set to a ‘1’, a write is in progress; when set to a ‘0’, no write is in progress. This bit is read-only. FIGURE 3-6: See Figure 3-6 for the RDSR timing sequence. READ STATUS REGISTER TIMING SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction SI 0 0 0 0 0 1 0 1 Data from STATUS Register High-Impedance SO DS21227F-page 10 7 6 5 4 3 2 1 0 © 2008 Microchip Technology Inc. 25AA320/25LC320/25C320 3.6 Write Status Register Instruction (WRSR) When the chip is hardware write-protected, only writes to nonvolatile bits in the STATUS register are disabled. See Table 3-3 for a matrix of functionality on the WPEN bit. The Write Status Register instruction (WRSR) allows the user to select one of four levels of protection for the array by writing to the appropriate bits in the STATUS register. The array is divided up into four segments. The user has the ability to write-protect none, one, two, or all four of the segments of the array. The partitioning is controlled as shown in Table 3-2. See Figure 3-7 for the WRSR timing sequence. TABLE 3-2: The Write-Protect Enable (WPEN) bit is a nonvolatile bit that is available as an enable bit for the WP pin. The Write-Protect (WP) pin and the Write-Protect Enable (WPEN) bit in the STATUS register control the programmable hardware write-protect feature. Hardware write protection is enabled when WP pin is low and the WPEN bit is high. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is low. FIGURE 3-7: ARRAY PROTECTION BP1 BP0 Array Addresses Write-Protected 0 0 none 0 1 upper 1/4 (0C00h-0FFFh) 1 0 upper 1/2 (0800h-0FFFh) 1 1 all (0000h-0FFFh) WRITE STATUS REGISTER TIMING SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK Instruction SI 0 0 0 0 0 Data to STATUS Register 0 0 1 7 6 5 4 3 2 1 0 High-Impedance SO © 2008 Microchip Technology Inc. DS21227F-page 11 25AA320/25LC320/25C320 3.7 Data Protection 3.8 The following protection has been implemented to prevent inadvertent writes to the array: • The write enable latch is reset on power-up • A WRITE ENABLE instruction must be issued to set the write enable latch • After a byte write, page write or STATUS register write, the write enable latch is reset • CS must be set high after the proper number of clock cycles to start an internal write cycle • Access to the array during an internal write cycle is ignored and programming is continued Power-On State The 25XX320 powers on in the following state: • The device is in low-power Standby mode (CS = 1) • The write enable latch is reset • SO is in high-impedance state • A low level on CS is required to enter active state . TABLE 3-3: WRITE-PROTECT FUNCTIONALITY MATRIX WPEN WP WEL Protected Blocks Unprotected Blocks STATUS Register x x 0 Protected Protected Protected Writable Writable 0 x 1 Protected 1 Low 1 Protected Writable Protected x High 1 Protected Writable Writable DS21227F-page 12 © 2008 Microchip Technology Inc. 25AA320/25LC320/25C320 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW Example: 25LC320 /PNNN YYWW 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN Example: 25LC320 I/SN e3 YYWW NNN Example: 8-Lead TSSOP XXXX XYWW NNN Example: 14-Lead TSSOP XXXXXXXX YYWW NNN Legend: XX...X Y YY WW NNN e3 * Note: * 5LBX IYWW NNN 25L32 YYWW NNN Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Standard marking consists of Microchip part number, year code, week code, and traceability code. For device markings beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. © 2008 Microchip Technology Inc. DS21227F-page 13 25AA320/25LC320/25C320           3 &' !&" &4# *!(!!& 4%&  &#& &&255***'  '54 N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b 6&! 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