48L512/48LM01
512-Kbit/1-Mbit SPI Serial EERAM
Serial SRAM Features
• Unlimited Reads/Unlimited Writes:
- Standard serial SRAM protocol
- Symmetrical timing for reads and writes
• SRAM Array:
- 65,536 x 8 bit (48L512)
- 131,072 x 8 bit (48LM01)
• High-Speed SPI Interface:
- Up to 66 MHz
- Schmitt Trigger inputs for noise suppression
• Low-Power CMOS Technology:
- Active current: 5 mA (maximum)
- Standby current: 200 μA (at 85°C maximum)
- Hibernate current: 3 μA (at 85°C maximum)
Package Types (not to scale)
8-Lead SOIC/SOIJ
(Top View)
CS
1
8
VCC
SO
2
7
HOLD
VCAP
3
6
SCK
VSS
4
5
SI
Pin Function Table
Name
Hidden EEPROM Backup Features
• Cell-Based Nonvolatile Backup:
- Mirrors SRAM array cell-for-cell
- Transfers all data to/from SRAM cells in
parallel (all cells at same time)
• Invisible-to-User Data Transfers:
- VCC level monitored inside device
- SRAM automatically saved on power disrupt
- SRAM automatically restored on VCC return
• 100,000 Backups Minimum (at 85°C)
• 100 Years Retention (at 55°C)
Function
CS
Chip Select Input
SO
Serial Data Output
VCAP
External Capacitor
VSS
Ground
SI
Serial Data Input
SCK
Serial Clock Input
HOLD
Hold Input
VCC
Supply Voltage
Other Features of the 48L512/48LM01
• Operating Voltage Range: 2.7V-3.6V
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
• ESD Protection: >2,000V
Packages
• 48L512: 8-Lead SOIC
• 48LM01: 8-Lead SOIJ
2018-2019 Microchip Technology Inc.
DS20006008C-page 1
48L512/48LM01
General Description
The Microchip Technology Inc. 48L512/48LM01
(48LXXX) serial EERAM has an SRAM memory core
with hidden EEPROM backup. The device can be
treated by the user as a full symmetrical read/write
SRAM. Backup to EEPROM is handled by the device
on any power disrupt, so the user can effectively view
this device as an SRAM that never loses its data.
The device is structured as a 512/1024-Kbit SRAM
with EEPROM backup in each memory cell. The
SRAM is organized as 65,536 x 8 bits or
131,072 x 8 bits, and uses the SPI serial interface.
The SPI bus uses three signal lines for
communication: clock input (SCK), data in (SI), and
data out (SO). Access to the device is controlled
through a Chip Select (CS) input, allowing any number
of devices to share the same bus.
The SRAM is a conventional serial SRAM: it allows
symmetrical reads and writes and has no limits on cell
usage. The backup EEPROM is invisible to the user
and cannot be accessed by the user independently.
The device includes circuitry that detects VCC
dropping below a certain threshold, shuts its
connection to the outside environment, and transfers
all SRAM data to the EEPROM portion of each cell for
safe keeping. When VCC returns, the circuitry
automatically returns the data to the SRAM and the
user’s interaction with the SRAM can continue with the
same data set.
Block Diagram
Powering the Device During SRAM to
EEPROM Backup (VCAP)
A small capacitor (typically 47 μF to 100 μF) is required
for the proper operation of the device. This capacitor is
placed between VCAP (pin 3) and the system VSS (see
Normal Device Operation). When power is first applied
to the device, this capacitor is charged to VCC through
the device (see Normal Device Operation). During normal SRAM operation, the capacitor remains charged to
VCC and the level of system VCC is monitored by the
device. If system VCC drops below a set threshold, the
device interprets this as a power-off or brown-out
event. The device suspends all I/O operation, shuts off
its connection with the VCC pin, and uses the saved
energy in the capacitor to power the device through the
VCAP pin as it transfers all SRAM data to EEPROM
(see Vcc Power-Off Event). On the next power-up of
VCC, the data is transfered back to SRAM, the capacitor is recharged, and the SRAM operation continues.
Normal Device Operation
VCC (pin 8)
System VCC
VCC Monitor
VCAP (pin 3)
CS
SO
SI
SCK
HOLD
CVCAP
Normal
SRAM
Operation
Charged to VCC
VSS (pin 4)
System VSS
VCC
VCAP
Power
Control
Block
VCC Power-Off Event
CS
SO
SI
SCK
HOLD
SPI Control Logic
and Address
Decoder
Memory Address
and Data Control
Logic
Automatic
Backup
EEPROM
EEPROM
128K x 8
64K x 8
STATUS
Register
SRAM
128K x 8
64K x 8
STORE
SRAM
CS
SO
SI
SCK
HOLD
SRAM to
EEPROM
Transfer
VCC (pin 8)
System VCC
VCAP (pin 3)
CVCAP
Temporary VCC
VSS (pin 4)
System VSS
RECALL
2018-2019 Microchip Technology Inc.
DS20006008C-page 2
48L512/48LM01
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
VCC.............................................................................................................................................................................4.5V
All inputs and outputs w.r.t. VSS ................................................................................................................... -0.6V to 4.5V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature under bias............................................................................................................... -40°C to +85°C
ESD protection on all pins.......................................................................................................................................... 2 kV
† NOTICE: Stresses above those listed under ‘Maximum ratings’ may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended
period of time may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
Electrical Characteristics:
Industrial (I):
TA = -40°C to +85°C
Min.
Typical
Max.
Units
VCC = 2.7V to 3.6V
Conditions
D1
VIH
High-Level Input
Voltage
VCC x 0.8
—
VCC + 0.5
V
D2
VIL
Low-Level Input
Voltage
-0.5
—
VCC x 0.2
V
D3
VOH
High-Level Output
Voltage
VCC - 0.5
—
—
V
IOH = -0.4 mA
D4
VOL
Low-Level Output
Voltage
—
—
0.4
V
IOL = 2.0 mA
D5
ILI
Input Leakage Current
—
—
±3
μA
VIN = VSS or VCC
D6
ILO
Output Leakage
Current
—
—
±3
μA
CS = VCC, VOUT = VSS or VCC
D7
CIN
Internal Capacitance
(all input pins)
—
—
5
pF
TA = 25°C, FREQ = 1 MHz,
VCC = 3.6V (Note 1)
D8
COUT
Internal Capacitance
(SO pin)
—
—
7
pF
TA = 25°C, FREQ = 1 MHz,
VCC = 3.6V (Note 1)
D9
ICC
Active
Operating Current
—
—
5
mA
TA = 85°C, VCC = 3.6V,
FCLK = 66 MHz (Note 3)
D10
ICC
Store
Store Current
—
—
2
mA
TA = 85°C,
2.7V < VCC ≤ 3.6V (Note 2)
D11
ICCS
Standby Current
—
—
200
μA
TA = 85°C, SI, CS, VCAP,
VCC = 3.6V
D12
ICCH
Hibernate Current
—
—
3
μA
TA = 85°C, SI, CS, VCAP,
VCC = 3.6V
D13
VTRIP
AutoStore/AutoRecall
Trip Voltage
2.30
—
2.65
V
D14
VHYS
Trip Voltage Hysteresis
—
300
—
mV
Note 1:
2:
3:
This parameter is periodically sampled and not 100% tested.
Store current is specified as an average current across the entire store operation.
ICC Active measured with SO pin unloaded. Current can vary with output loading and clock frequency.
2018-2019 Microchip Technology Inc.
Note 1
DS20006008C-page 3
48L512/48LM01
TABLE 1-1:
DC CHARACTERISTICS (CONTINUED)
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
Electrical Characteristics:
Industrial (I):
TA = -40°C to +85°C
Min.
Typical
Max.
Units
VCC = 2.7V to 3.6V
Conditions
D15
VPOR
Power-on Reset
Voltage
—
1.8
—
V
Note 1
D16
CVCAP
VCAP Capacitance
47
68
100
μF
Rated 6.3V or higher (Note 1)
Note 1:
2:
3:
This parameter is periodically sampled and not 100% tested.
Store current is specified as an average current across the entire store operation.
ICC Active measured with SO pin unloaded. Current can vary with output loading and clock frequency.
2018-2019 Microchip Technology Inc.
DS20006008C-page 4
48L512/48LM01
TABLE 1-2:
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
TA = -40°C to +85°C
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristic
Min.
Max.
Units Conditions
1
FCLK
Clock Frequency
—
66
MHz
2
TCSS
CS Setup Time
6
—
ns
3
TCSH
CS Hold Time
6
—
ns
4
TCSD
CS Disable Time
7
—
ns
5
TSU
Data Setup Time
4
—
ns
6
THD
Data Hold Time
4
—
ns
7
TR
CLK Rise Time
—
100
ns
Note 1
8
TF
CLK Fall Time
—
100
ns
Note 1
9
THI
Clock High Time
7
—
ns
10
TLO
Clock Low Time
7
—
ns
11
TCLD
Clock Delay Time
7
—
ns
12
TCLE
Clock Enable Time
3
—
ns
13
TV
Output Valid from Clock Low
—
10
ns
14
THO
Output Hold Time
0
—
ns
Note 1
15
TDIS
Output Disable Time
—
20
ns
Note 1
16
THZ
HOLD Low to Output High Z
—
10
ns
Note 1
17
THV
HOLD High to Output Valid
—
10
ns
18
THS
HOLD Setup Time
0
THH
HOLD Hold Time
19
20
TRESTORE Power-up AutoRecall/Hibernation
Wake-up Operation Duration
ns
5
ns
—
200
μs
21
TRECALL
SW Recall Operation Duration
—
50
μs
22
TSTORE
Store Operation Duration
—
10
ms
23
TVRISE
VCC Rise Rate
30
—
μs/V
Note 1
24
TvFALL
VCC Fall Rate
30
—
μs/V
Note 1
25
Endurance
100,000
—
Store Note 1
Cycles
26
Retention
100
—
Years At 55°C
10
—
Years At 85°C
Note 1:
VCC = 2.7V to 3.6V
This parameter is not tested but ensured by characterization.
2018-2019 Microchip Technology Inc.
DS20006008C-page 5
48L512/48LM01
FIGURE 1-1:
HOLD TIMING
CS
18
19
18
19
18
19
18
19
SCK
16
n
n+1
SO
High-Impedance
Don’t Care
SI
n+1
17
16
n
n-1
High-Impedance
n-2
Don’t Care
5
n
n
17
n-2
n-1
HOLD
FIGURE 1-2:
SERIAL INPUT TIMING MODE 0,0
4
12
CS
2
7
10
SCK
8
11
3
9
5
6
SI
MSb In
LSb In
High-Impedance
SO
FIGURE 1-3:
SERIAL INPUT TIMING MODE 1,1
4
12
CS
2
7
10
SCK
3
9
5
SI
11
8
6
MSb In
SO
2018-2019 Microchip Technology Inc.
LSb In
High-Impedance
DS20006008C-page 6
48L512/48LM01
FIGURE 1-4:
SERIAL OUTPUT TIMING
CS
9
3
10
Mode 1,1
SCK
Mode 0,0
13
14
MSB Out
SO
15
LSB Out
Don’t Care
SI
TABLE 1-3:
AC TEST CONDITIONS
AC Waveform
VLO = 0.2V
VHI = VCC - 0.2V
CL = 30 pF
Timing Measurement Reference Level
Input
0.5 VCC
Output
0.5 VCC
FIGURE 1-5:
AUTOSTORE/AUTORECALL TIMING DATA
D13
VCAP
D15
22
22
AutoStore
20
20
AutoRecall
Device Access
Enabled
2018-2019 Microchip Technology Inc.
DS20006008C-page 7
48L512/48LM01
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
2.1
PIN FUNCTION TABLE
Name
8-Lead SOIC
8-Lead SOIJ
CS
1
1
Chip Select Input
SO
2
2
Serial Data Output
VCAP
3
3
External Capacitor
VSS
4
4
Ground
SI
5
5
Serial Data Input
SCK
6
6
Serial Clock Input
HOLD
7
7
Hold Input
VCC
8
8
Supply Voltage
Chip Select (CS)
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
When the device is deselected, SO goes to the
high-impedance state, allowing multiple parts to share
the same SPI bus. A low-to-high transition on CS after
a valid write sequence completes the SRAM write
cycle. After power-up, a high-to-low transition on CS is
required prior to any sequence being initiated.
2.2
Serial Output (SO)
The SO pin is used to transfer data out of the
48L512/48LM01. During a read cycle, data is shifted
out on this pin after the falling edge of the serial clock.
2.3
Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses, and data. Data is
latched on the rising edge of the serial clock.
2.4
Serial Clock (SCK)
The SCK is used to synchronize the communication
between a master and the 48L512/48LM01.
Instructions, addresses, or data present on the SI pin
are latched on the rising edge of the clock input, while
data on the SO pin is updated after the falling edge of
the clock input.
2018-2019 Microchip Technology Inc.
Description
2.5
Hold (HOLD)
The HOLD pin is used to suspend transmission to the
48L512/48LM01 while in the middle of a serial
sequence without having to retransmit the entire
sequence over again. It must be held high any time this
function is not being used. Once the device is selected
and a serial sequence is underway, the HOLD pin may
be pulled low to pause further serial communication
without resetting the serial sequence.
The HOLD pin should be brought low while SCK is low,
otherwise the Hold function will not be invoked until the
next SCK high-to-low transition. The 48L512/48LM01
must remain selected during this sequence. The SI and
SCK levels are “don’t cares” during the time the device
is paused and any transitions on these pins will be
ignored. To resume serial communication, HOLD pin
should be brought high while the SCK pin is low,
otherwise serial communication will not be resumed
until the next SCK high-to-low transition.
The SO line will tri-state immediately upon a
high-to-low transition of the HOLD pin, and will begin
outputting again immediately upon a subsequent
low-to-high transition of the HOLD pin, independent of
the state of SCK.
DS20006008C-page 8
48L512/48LM01
3.0
MEMORY ORGANIZATION
3.1
Data Array Organization
The 48L512/48LM01 is internally organized as a
continuous SRAM array for both reading and writing,
along with a nonvolatile EEPROM array that is not
directly accessible to the user, but which can be
refreshed or recalled on power cycles or on software
commands. The SRAM array is continuously
addressable, so the entire array can be written without
having to access pages.
3.2
16-Byte Nonvolatile User Space
The 48L512/48LM01 devices contain a 16-byte
nonvolatile user space, separate from the SRAM
memory array. The nonvolatile user space can be
written with the Write Nonvolatile User Space
(WRNUR) command and read with the Read
Nonvolatile User Space (RDNUR) command. Once
written, these 16 bytes remain volatile and can be
rewritten. They are copied to nonvolatile memory – at
the same time as the SRAM array and STATUS register
– automatically on any power disruption or by using the
Software Store command described in Section 11.0
“Store/Recall Operations”.
Reading and writing to the nonvolatile user space does
not use address bits, only the specific access
instruction to precede the operation. Writing to the
nonvolatile user space requires writing all of its bits in
one operation. Failing to write to all nonvolatile user
space bits will abort the write operation and leave the
nonvolatile user space value unchanged from its
previous value. Similarly, reading the nonvolatile user
space memory uses no address bits, but partial reads
are allowed.
3.3
Device Registers
The 48L512/48LM01 contains a STATUS register for
controlling and monitoring functions of the device.
3.3.1
STATUS REGISTER
The STATUS register is an 8-bit combination of writable
and read-only bits. It is used to modify the write
protection functions as well as store various aspects of
the current status of the device. The writable bit values
written to the STATUS register are volatile – until they
are copied to nonvolatile memory automatically on any
power disruption or by using the Software Store
command described in Section 11.0 “Store/Recall
Operations” – and can be overwritten from a previous
status in a recall operation. Details about the STATUS
register are covered in Section 6.0 "STATUS
Register".
2018-2019 Microchip Technology Inc.
DS20006008C-page 9
48L512/48LM01
4.0
FUNCTIONAL DESCRIPTION
The 48L512/48LM01 supports the two most common
modes, SPI Modes 0 and 3. With SPI Modes 0 and 3,
data is always latched in on the rising edge of SCK
and always output on the falling edge of SCK. The
only difference between SPI Modes 0 and 3 is the
polarity of the SCK signal when in the inactive state
(when the SPI Master is in Standby mode and not
transferring any data). SPI Mode 0 is defined as a low
SCK while CS is not asserted (high) and SPI Mode 3
has SCK high in the inactive state. The SCK Idle state
must match when the CS is deasserted both before
and after the communication sequence in SPI Mode 0
and 3.
The 48L512/48LM01 is controlled by a set of
instructions that are sent from a host controller,
commonly referred to as the SPI Master. The SPI
Master communicates with the 48L512/48LM01 via the
SPI bus which is comprised of four signal lines:
•
•
•
•
Chip Select (CS)
Serial Clock (SCK)
Serial Input (SI)
Serial Output (SO)
The SPI protocol defines a total of four modes of
operation (Mode 0, 1, 2, or 3) with each mode differing
in respect to the SCK polarity and phase and how the
polarity and phase control the flow of data on the SPI
bus.
FIGURE 4-1:
The figures in this document depict Mode 0 with a
solid line on SCK while CS is inactive and Mode 3 with
a dotted line.
SPI MODE 0 AND MODE 3
CS
SCK
SI
Mode 3
Mode 3
Mode 0
Mode 0
MSb
MSb
SO
4.1
Interfacing the 48L512/48LM01 on
the SPI Bus
Communication to and from the 48L512/48LM01 must
be initiated by the SPI Master device. The SPI Master
device must generate the serial clock for the
48L512/48LM01 on the SCK pin. The 48L512/48LM01
always operates as a slave due to the fact that the
Serial Clock pin (SCK) is always an input.
4.1.1
LSb
SELECTING THE DEVICE
The 48L512/48LM01 is selected when the CS pin is
low. When the device is not selected, data will not be
accepted via the SI pin and the SO pin will remain in a
high-impedance state.
2018-2019 Microchip Technology Inc.
4.1.2
LSb
SENDING DATA TO THE DEVICE
The 48L512/48LM01 uses the Serial Data Input (SI) pin
to receive information. All instructions, addresses, and
data input bytes are clocked into the device with the
Most Significant bit (MSb) first.
The SI pin samples on the first rising edge of the SCK
line after the CS has been asserted.
4.1.3
RECEIVING DATA FROM THE
DEVICE
Data output from the device is transmitted on the Serial
Data Output (SO) pin with the MSb output first. The SO
data is latched on the falling edge of the first SCK clock
cycle after the instruction has been clocked into the
device, such as the Read from Memory Array and
Read STATUS Register instructions. See Section 6.0
"STATUS Register" for more details.
DS20006008C-page 10
48L512/48LM01
4.2
DEVICE OPCODES
4.2.1
SERIAL OPCODE
After the device is selected by driving CS low, the first
byte sent must be the opcode that defines the
operation to be performed.
TABLE 4-1:
Command
The 48L512/48LM01 utilizes an 8-bit instruction
register. The list of instructions and their operation
codes are contained in Table 4-1. All instructions,
addresses, and data are transferred with the MSb first
and are initiated with a high-to-low CS transition and
completed with a low-to-high CS transition.
INSTRUCTION SET FOR 48L512/48LM01
Operation Description
Opcode
Address Data
Bytes
Bytes
Reference
Section
Write Control Commands
WREN
Set Write Enable Latch (WEL)
WRDI
Reset Write Enable Latch (WEL)
06h
0000 0110
0
0
5.1
04h
0000 0100
0
0
5.2
SRAM Commands
WRITE
Write to SRAM Array
02h
0000 0010
2/3
1+
8.0
READ
Read from SRAM Array
03h
0000 0011
2/3
1+
7.1
Secure
WRITE
Secure Write to SRAM Array with CRC
12h
0001 0010
2/3
64/128
10.1
Secure
READ
Secure Read from SRAM Array with CRC
13h
0001 0011
2/3
64/128
10.2
STATUS Register Commands
WRSR
Write STATUS Register (SR)
01h
0000 0001
0
1
6.5
RDSR
Read STATUS Register (SR)
05h
0000 0101
0
1
6.4
STORE
Store SRAM data to EEPROM array
08h
0000 1000
0
0
11.3
RECALL
Copy EEPROM data to SRAM array
09h
0000 1001
0
0
11.4
Store/Recall Commands
Nonvolatile User Space Commands
WRNUR
Write Nonvolatile User Space
C2h
1100 0010
0
16
9.1
RDNUR
Read Nonvolatile User Space
C3h
1100 0011
0
16
9.2
1011 1001
0
0
12.0
Hibernate Commands
Hibernate
4.2.2
Enter Hibernate Mode
HOLD FUNCTION
The HOLD pin is used to pause the serial
communication with the device without having to stop
or reset the clock sequence. The Hold mode, however,
does not have an effect on the internal write cycle.
Therefore, if a write cycle is in progress, asserting the
HOLD pin will not pause the operation and the write
cycle will continue until it is finished.
The Hold mode can only be entered while the CS pin is
asserted. The Hold mode is activated by asserting the
HOLD pin during the SCK low pulse. If the HOLD pin is
asserted during the SCK high pulse, then the Hold
mode will not be started until the beginning of the next
SCK low pulse. The device will remain in the Hold
mode as long as the HOLD pin and CS pin are
asserted.
B9h
To end the Hold mode and resume serial
communication, the HOLD pin must be deasserted
during the SCK low pulse. If the HOLD pin is
deasserted during the SCK high pulse, then the Hold
mode will not end until the beginning of the next SCK
low pulse.
If the CS pin is deasserted while the HOLD pin is still
asserted, then any operation that may have been
started will be aborted and the device will reset the
WEL bit in the STATUS register back to the logic ‘0’
state.
While in Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin and the SCK pin
will be ignored.
2018-2019 Microchip Technology Inc.
DS20006008C-page 11
48L512/48LM01
FIGURE 4-2:
HOLD MODE
CS
SCK
Hold
Hold
Hold
HOLD
2018-2019 Microchip Technology Inc.
DS20006008C-page 12
48L512/48LM01
5.0
WRITE ENABLE AND DISABLE
The WEL bit will also be reset to a logic ‘0’ in the
following circumstances:
5.1
Write Enable Instruction (WREN)
• Upon power-up as the power on default condition
is the Write Disable state (Section 6.2 "Write
Enable Latch")
• The completion of any write operation (WRITE,
WRSR)
• A write operation of any type to a memory location
or register that is protected or locked
• Executing a Write Disable (WRDI) instruction
(Section 5.2
"Write
Disable
Instruction
(WRDI)")
• A Hold abort occurs as noted in Section 4.2.2
"Hold Function" (CS deasserted while HOLD pin
is low)
The Write Enable Latch (WEL) bit of the STATUS
register must be set to a logic ‘1’ prior to each WRSR or
WRITE instruction. The WEL bit is set to a logic ‘1’ by
sending a WREN (06h) command to the
48L512/48LM01. First, the CS pin is driven low to
select the device and then a 06h instruction is clocked
in on the SI pin. Then the CS pin is driven high. The
WEL bit will be immediately updated in the STATUS
register to a logic ‘1’.
FIGURE 5-1:
WREN WAVEFORM
CS
0
1
2
3
4
5
6
7
SCK
WREN Opcode
0
SI
0
0
0
0
1
1
0
MSb
High-Impedance
SO
5.2
Write Disable Instruction (WRDI)
To protect the device against inadvertent writes, the
Write Disable instruction (opcode 04h) disables all
programming modes by setting the WEL bit to a
logic ‘0’.
FIGURE 5-2:
WRDI WAVEFORM
CS
0
1
2
3
4
5
6
7
SCK
WRDI Opcode
SI
0
0
0
0
0
1
0
0
MSb
High-Impedance
SO
2018-2019 Microchip Technology Inc.
DS20006008C-page 13
48L512/48LM01
6.0
STATUS REGISTER
The 48L512/48LM01 includes a 1-byte STATUS
register which is a combination of four nonvolatile bits
and four volatile bits. The STATUS register bits control
or indicate various features of the device as shown in
Register 6-1. These bits can be read or modified by
specific instructions that are detailed in the subsequent
sections.
REGISTER 6-1:
STATUS REGISTER
R/W
R/W
R/W
R-0
R/W
R/W
R-0
R-0
Reserved
ASE
Reserved
SWM
BP1
BP0
WEL
RDY/BSY
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Reserved: Must be set to ‘0’
bit 6
ASE: AutoStore Enable bit
1 = AutoStore is disabled.
0 = AutoStore is enabled (factory default).
bit 5
Reserved: Must be set to ‘0’
bit 4
SWM: Secure Write Monitoring bit – Read-Only
1 = The last secure write operation has failed.
0 = No error reported in Secure Write.
bit 3-2
BP[1:0]: Block Protection bits (see Table 6-2)
00 = (Level 0) No SRAM array write protection (factory default)
01 = (Level 1) Upper quarter SRAM memory array protection
10 = (Level 2) Upper half SRAM memory array protection
11 = (Level 3) Entire SRAM memory array protection
bit 1
WEL: Write Enable Latch bit – Read-Only
1 = WREN has been executed and device is enabled for writing.
0 = Device is not write-enabled.
bit 0
RDY/BSY: Ready/Busy Status bit – Read-Only
1 = Device is busy with an internal store or recall operation.
0 = Device is ready for standard SRAM Read/Write commands.
6.1
x = Bit is unknown
Block Write-Protect Bits
The 48L512/48LM01 contains four levels of SRAM
write protection using the block protection function. The
nonvolatile Block Write-Protect bits (BP1, BP0) are
located in bits three and two of the STATUS register
byte and define the region of the SRAM that are to be
treated as read-only.
The address ranges that are protected for each SRAM
Block Write Protection level and the corresponding
STATUS register control bits are shown in Table 6-2.
2018-2019 Microchip Technology Inc.
DS20006008C-page 14
48L512/48LM01
TABLE 6-2:
BLOCK WRITE-PROTECT BITS
STATUS Register Bits [3:2]
Level
6.2
Protected Address Range
BP1
BP0
0
0
0
None
None
1
0
1
C000-FFFF
18000-1FFFF
2
1
0
8000-FFFF
10000-1FFFF
3
1
1
0000-FFFF
00000-1FFFF
Write Enable Latch
A logic ‘0’ bit in this position indicates the device is
ready to accept new SRAM Read/Write commands.
6.4
Read STATUS Register (RDSR)
The Read STATUS Register (RDSR) instruction
provides access to the contents of the STATUS
register. The STATUS register is read by asserting the
CS pin followed by sending in a 05h opcode. The
device will return the 8-bit STATUS register value on
the SO pin.
Ready/Busy Status Latch
The Ready/Busy Status Latch is used to indicate
whether the device is currently active in a nonvolatile
write operation. This bit is read-only and automatically
updated by the device. This bit is provided in bit position ‘0’.
FIGURE 6-1:
48LM01
A logic ‘1’ bit indicates that the device is currently busy
performing an SRAM to EEPROM transfer or EEPROM
to SRAM restore operation. During this time, only the
Read STATUS Register (RDSR) command will be executed by the device.
Enabling and disabling writing to the STATUS register,
Memory Partition register, Under-Voltage Lockout
register and the SRAM array is accomplished through
the Write Enable (WREN) instruction as shown in
Section 5.1 "Write Enable Instruction (WREN)" and
the Write Disable (WRDI) instruction as shown in
Section 5.2 "Write Disable Instruction (WRDI)".
These functions change the status of the WEL bit (bit 1)
in the STATUS register.
6.3
48L512
The STATUS register can be continuously read for data
by continuing to read beyond the first 8-bit value
returned. The 48L512/48LM01 will update the STATUS
register value upon the completion of every eight bits,
thereby allowing new STATUS register values to be
read without having to issue a new RDSR instruction.
RDSR WAVEFORM
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCK
RDSR Opcode
SI
SO
0
0
0
0
High-Impedance
2018-2019 Microchip Technology Inc.
0
1
0
1
STATUS Register
D D
D D D D
D D
DS20006008C-page 15
48L512/48LM01
6.5
Write STATUS Register (WRSR)
Note:
The Write STATUS Register (WRSR) instruction enables
the SPI Master to change selected bits of the STATUS
register. Before a WRSR sequence can be initiated, a
WREN instruction must be executed to set the WEL bit
to logic ‘1’. Upon completion of a WREN sequence, a
WRSR sequence can be executed.
The updated STATUS register value will
only be stored into nonvolatile memory
when there is a store operation.
The WRSR command can be used to modify the
writable bits in the STATUS register. The SWM and
RDY/BSY bits are read-only. The 48L512/48LM01 will
respond to commands immediately after a WRSR
sequence.
FIGURE 6-2:
WRSR WAVEFORM
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCK
SI
WRSR Opcode
0 0 0 0 0 0 0
MSb
D D
MSb
High-Impedance
1
STATUS Register
D D D D D D
SO
2018-2019 Microchip Technology Inc.
DS20006008C-page 16
48L512/48LM01
7.0
READ OPERATIONS
7.1
Reading from the SRAM (READ)
Reading the SRAM contents can be done whenever
the device is not in an internal store or recall cycle, as
indicated by the Ready/Busy bit of the STATUS
register. To read the SRAM, first the CS line is pulled
low to select the device and the Read opcode 03h is
transmitted via the SI line followed by the 16- or 24-bit
address to be read.
FIGURE 7-1:
Upon completion of the address bytes, any data on the
SI line will be ignored. The data (D7–D0) at the
specified address is then shifted out onto the SO line.
Any number of bytes can be clocked out, and if the
address reaches the end of the array, it can continue at
the beginning of the array. Read operations are not
limited by page boundaries.
The read sequence can be terminated at any point of
the operation. The CS line should be driven high after
the data is clocked out.
READ SRAM (READ) WAVEFORM
CS
0
1
2
3
4
5
6
7
SCK
READ Opcode
SI
0 0 0 0 0 0
MSb
Address Bits (24/16)
1 1 A A A A A A A A
MSb
Data Byte
SO
High-Impedance
D7 D6 D5 D4 D3 D2 D1 D0
MSb
2018-2019 Microchip Technology Inc.
DS20006008C-page 17
48L512/48LM01
8.0
WRITE COMMANDS
Note:
In order to write to the SRAM in the 48L512/48LM01,
the device must be write-enabled via the Write Enable
(WREN) instruction. If the device is not Write Enabled
(WREN), the device will ignore the SRAM WRITE
instruction and will return to the Standby state when CS
is brought high. Each unique write to the SRAM array
is not immediately transferred to EEPROM so there is
no delay after one write to begin another SRAM
read/write operation. Contents of the SRAM are only
automatically transferred to EEPROM on any power
disruption. The user may also force a transfer from
SRAM to EEPROM using the Software Store command
or at power-down with AutoStore. (see Section 11.3
"Software Store Command").
8.1
8.1.1
If the CS pin is deselected at somewhere
other than the end of an 8-bit byte
boundary, the incomplete SRAM byte
write will be aborted. Data written is using
the WRITE instruction to the SRAM array.
The 48L512/48LM01 is automatically returned to the
Write Disable state (STATUS register bit WEL = 0) at
the completion of an SRAM write operation.
Write Instruction Sequences
SRAM BYTE WRITE
Once a WREN command has been completed, an
SRAM byte write sequence can be performed as
shown in Figure 8-1. After the CS line is pulled low to
select the device, the opcode is transmitted via the SI
line, followed by the rest of up to 16- or 24-bit address
and the data (D7-D0) to be programmed, depending on
the device.
FIGURE 8-1:
SRAM BYTE WRITE WAVEFORM
CS
0
1
2
3
4
5
6
7
SCK
WRITE Opcode
SI
0
0 0
MSb
0
0 0
Address (2 or 3 bytes)
1 0
Data In
A A A A A A A A D7 D6 D5 D4 D3 D2 D1 D0
MSb
MSb
High-Impedance
SO
2018-2019 Microchip Technology Inc.
DS20006008C-page 18
48L512/48LM01
8.1.2
CONTINUOUS WRITE
Note:
Writing to a number of SRAM bytes is similar to a byte
write, however, more bytes can be added after the first
byte in the same write cycle. If more bytes of data are
transmitted than what will fit to the end of that memory
array, the address counter will “roll over” to the
beginning of the SRAM array. Previously written data
will be overwritten.
If the CS pin is deselected at somewhere
other than the end of an 8-bit byte
boundary, the last partial byte operation
will be aborted and the completed bytes
will be written to the SRAM array.
Upon completion of the write, the 48L512/48LM01
automatically returns to the Write Disable state
(STATUS register bit WEL = 0).
FIGURE 8-2:
CONTINUOUS SRAM WRITE WAVEFORM
CS
0
1
2
3
4
5
6
7
SCK
WRITE Opcode
SI
0 0
0
0 0 0
1 0
MSb
SO
2018-2019 Microchip Technology Inc.
Data In Byte 1
Address (2 or 3 bytes)
A A A A A A A A D D D D D D D D
MSb
MSb
Data In Byte n
D
D D D D D D
D
MSb
High-Impedance
DS20006008C-page 19
48L512/48LM01
9.0
NONVOLATILE USER SPACE
ACCESS
9.1
Writing to the 16-byte nonvolatile user space requires
the WEL bit to be set, such as with a WREL instruction.
The nonvolatile user space write operation must
include the CS pin to be brought low, the WRNUR
instruction to be sent on SI, and the whole NU value
clocked in (16-bytes). Then the CS pin is set high. The
value is stored immediately in the volatile memory.
The nonvolatile user space value is not transferred to
EEPROM until the next power disruption, though a
Software Store can be executed at any time. The
nonvolatile user space content is then permanent only
until rewritten by the user.
Both the 512K and 1M devices have 16 bytes (128
bits) of nonvolatile user space memory.
The nonvolatile user space memory is accessed
through the WRNUR and RDNUR instructions. Data
written to the nonvolatile user space memory is volatile
but will be transferred to EEPROM automatically on
any power disruption. The last content will then be
restored from EEPROM on the next power up.
Software Store and Software Recall can also be
executed by the user as described in Section 11.0
"Store/Recall Operations".
FIGURE 9-1:
Write Nonvolatile User Space
(WRNUR)
NONVOLATILE USER SPACE WRITE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCK
WRNUR Instruction
SI
9.2
1
1
0
0
0
0
NU byte 0
1
7
0
6
5
4
3
2
Read Nonvolatile User Space
(RDNUR)
1
0
7
6
5
4
3
2
1
0
The user can also use the Software Recall command
(Section 11.0 "Store/Recall Operations") to recover
the nonvolatile user space content moved to EEPROM
on the last power event or the last Software Store
event.
Reading the nonvolatile user space is possible with
the RDNUR command. The nonvolatile user space
read operation must include the CS pin to be brought
low, the RDNUR instruction to be sent on SI, and the
whole NU value clocked out on SO (16 bytes). Then
the CS pin is set high. The value read is from the
volatile SRAM memory, so this will be the last value
restored from EEPROM on power-up or any new value
written into these 16 bytes since the last power-up.
FIGURE 9-2:
NU byte 15
READ NONVOLATILE USER SPACE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCK
RDNUR Instruction
SI
SO
1
1
0
0
0
0
High Impedance
2018-2019 Microchip Technology Inc.
1
1
NU Byte 15
NU Byte 0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
DS20006008C-page 20
48L512/48LM01
10.0
SECURE OPERATIONS
The 48LXXX devices support secure write and read
operations, which add another layer of protection to
data. The secure write and read operations use a CRC
checksum on a fixed number of bytes and the address
bits, to be sure the data beginning at that address
matches the given checksum before it is considered
valid.
The 512 Kbit uses a 64-byte, and 1 Mbit device uses a
128-byte, and address CRC calculation. The devices
accept or transmit a 2-byte CRC value calculated from
the SRAM data and address bits. Only valid address
bits are used in the calculation (upper address bits that
extend beyond the array size are ignored in the CRC
calculation). The range of the secure write and read
operations is limited to the exact number of bytes
within the 64-byte or 128-byte page boundary.
10.1
Secure Write
To enable the secure write operation, a WEL bit has to
be set first. The CS line is set low, the Secure Write
command is sent, followed by the address bytes.
Only the valid address bits are used in the CRC
calculation (see Table 10-1 below). Then, data is sent
to the required number of bytes, and the expected
CRC value is calculated internally as bytes are sent in.
After the last byte is written, the 16-bit CRC is to be
clocked in on SI, then the CS pin is set high.
The CRC16-CCITT polynomial used is x16+x12+x5+1.
The boundary for the write operation should align with
the size of the range, 64 bytes for 512K device, and
128 bytes for 1M device. It is possible to write to an
address that does not begin at the page boundary, but
the address pointer will roll-over from the end of the
page to the beginning and the required checksum
bytes will likely be different.
10.2
Secure Read
The secure read operation requires the CS pin to be
brought low and the secure read opcode sent in on the
SI pin. Following that is the address (2 or 3 bytes,
depending on device). The valid address bits are part
of the CRC calculation. Only the correct number of bits
can be read, which are 64 or 128 bytes, depending on
the device, clocked out on the SO pin (see Table 10-1
for details). As the data is sent out, a CRC checksum
is calculated. The CRC16-CCITT polynomial used is
x16+x12+x5+1. After the data bytes are sent, then the
two CRC bytes are sent, and the master sets the CS
pin high to finish the operation. The master reading the
SRAM can do a CRC calculation to confirm that the
address and data agree with the checksum bytes
provided by the device.
The secure read should align with a SRAM address
boundary of 64 bytes for 512K device or 128 bytes for
1M device. It is possible to read from an address that
does not begin at the page boundary, but the address
pointer will roll-over from the end of the page to the
beginning and the checksum bytes read will likely be
different.
The SWM bit in the STATUS register is not affected by
secure read operations.
TABLE 10-1:
Device
48L512
48LM01
SECURE WRITE BITS
Address Address
Bytes
Bits
2
3
16
17
Data
Bytes
Required
CRC
Bits
64
128
16
16
The initial value for the CRC calculation is 0xFFFF.
The checksum must be transmitted with MSb first. In
addition, the internally calculated CRC has to match
the transmitted CRC. If they match, the data will be
accepted and written to the array. If the CRC values do
not match, data will be ignored and the existing
memory data will stay as it was and the SWM bit in the
STATUS register will be set to ‘1’, indicating a secure
write error. The status of the SWM bit should be read
after every secure write operation to confirm the
operation was successful. The SWM bit in the
STATUS register is read-only and will automatically
reset to ‘0’ at the beginning of the next secure write
operation.
With the low-to-high transition of the CS pin, the
device is automatically returned to the Write Disable
state, with the WEL bit returning to ‘0’.
2018-2019 Microchip Technology Inc.
DS20006008C-page 21
48L512/48LM01
TABLE 10-1:
SECURE SRAM WRITE WAVEFORM
CS
0
1
2
3
4
5
6
7
SCK
Secure Write Instruction
SI
0
0
7
6
0
1
0
0
1
Address MSB
0
A
A
A
A
A
A
Address LSB
A
A
A A
A
A A
A
A
A
CS
SCK
64/128 Bytes Data
SI
5
4
3
2
1
Checksum Byte 1
0
7
6
5
4
3
2
Checksum Byte 2
1
0
7
6
5
4
3
2
1
0
High-Impedance
SO
FIGURE 10-1: SECURE SRAM READ WAVEFORM
CS
0
1
2
3
4
5
6
7
SCK
Secure Read Instruction
SI
0
0
0
1
0
0
1
Address MSB
1
A
A
A
A
A
A
Address LSB
A
A
A
A
A
A
A
A
A
A
CS
SCK
SI
64/128 Bytes Data
SO
7
6
5
4
3
2
1
2018-2019 Microchip Technology Inc.
Checksum Byte 1
0
7
6
5
4
3
2
Checksum Byte 2
1
0
7
6
5
4
3
2
1
0
DS20006008C-page 22
48L512/48LM01
11.0
STORE/RECALL OPERATIONS
11.2
An automatic recall of EEPROM to SRAM (AutoRecall) is performed on power-up, regardless of the state
of the ASE bit. This feature ensures that the SRAM
data duplicates the EEPROM data on power-up. The
AutoRecall is initiated when VCAP rises above VTRIP,
and the 48LXXX cannot be accessed for TRESTORE
time after the AutoRecall is initiated.
This EERAM device is intended to be serial SRAM
with internal management of all backup transfers to
and from EEPROM on power disruption, so the
EEPROM portion of the SRAM memory cell is not
directly
accessible
to
the
user.
However,
user-managed Software Store and Software Recall
commands are included. The factory default for the
ASE bit in the STATUS register is ‘0’, enabling the
AutoStore function.
11.1
Automatic Recall to SRAM
Note 1: If power is lost during an AutoRecall
operation, the AutoRecall is aborted and
the AutoStore is not performed.
Automatic Store on Any Power
Disruption
2: AutoRecall is performed every time VCAP
rises above VTRIP.
To enable this feature, the user must place a capacitor
on the VCAP pin and ensure the ASE bit in the
STATUS register is set to ‘0’. The capacitor is charged
through the VCC pin. When the 48LXXX detects a
power-down event, the device automatically switches
to the capacitor for power and initiates the AutoStore
operation.
11.3
Software Store Command
The Software Store command must be user-initiated
and will store the contents of the SRAM bits, the
nonvolatile user space, and the Configuration bits of
the STATUS register (BP[1:0] and ASE) into
nonvolatile storage. The Software Store command
functions even if the contents of the array and registers have not changed since the last store or recall.
Reading the STATUS register during the store cycle
will indicate a busy bit. Other operations will be
ignored.
Note that to minimize the transfer events to EEPROM,
this automatic store will only be initiated if the SRAM
array has been modified since the last store or recall
operation.
The automatic store cycle (AutoStore) is initiated when
VCAP falls below VTRIP. Even if power is restored, the
48LXXX cannot be accessed for TSTORE time after the
AutoStore is initiated.
Note: If power is restored during an AutoStore
operation, the AutoStore will continue
and the AutoRecall will not be
performed because the SRAM content
is still valid.
FIGURE 11-1:
SOFTWARE STORE
CS
0
1
2
3
4
5
6
7
SCK
STORE Opcode
SI
0
0
0
0
1
0
0
0
MSb
High-Impedance
SO
2018-2019 Microchip Technology Inc.
DS20006008C-page 23
48L512/48LM01
11.4
Software Recall Command
The Software Recall command must be user-initiated
and replaces the contents of the SRAM array, the
nonvolatile user space, and the Configuration bits of
the STATUS register (BP[1:0] and ASE) from a
previous store into the user corresponding
user-accessible areas.
The Software Recall command can be given and the
operation completed, even if the contents of the array
and registers have not changed since the last store or
recall. Reading the STATUS register during the recall
cycle will indicate a busy bit. Other operations will be
ignored.
FIGURE 11-2:
SOFTWARE RECALL
CS
0
1
2
3
4
5
6
7
SCK
RECALL Opcode
0
SI
0
0
0
1
0
0
1
MSb
High-Impedance
SO
TABLE 11-1:
STORE ENABLE TRUTH TABLE
ASE Bit
Array Modified
AutoStore
Enabled
Software Store
Enabled
AutoRecall
Enabled
Software Recall
Enabled
x
1
0
No
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
2018-2019 Microchip Technology Inc.
DS20006008C-page 24
48L512/48LM01
11.5
Polling Routine
When operating in the more common automatic store
and recall mode (AutoStore/AutoRecall), the master
can poll the RDY/BSY bit on power-up to see when the
SRAM is ready for new Read/Write commands. See
Figure 11-3 beginning with the “Send RDSR Instruction
to the Device”.
Polling can also be used if the user-initiated Software
Store and Software Recall commands are used. Polling
allows the application to query whether the EERAM
has completed the transfer operations between the
SRAM and EEPROM portions of the memory cell. This
polling routine can be initiated after every power-up to
confirm that AutoRecall has completed, or after the
user-executed Software Store and Software Recall
commands have started processing.
The polling routine is repeatedly sending a Read
STATUS Register (RDSR) command to determine if
the device has completed its self-timed internal store or
recall cycles (see Figure 11-3). If the RDY/BSY bit = 1
from RDSR, the write cycle is still in progress. If
RDY/BSY bit = 0 from RDSR, this indicates the
operation has ended. If the device is still in a busy state,
repeated RDSR commands can be executed until the
RDY/BSY bit = 0, signaling that the device is ready to
execute a new instruction.
With the 48L512/48LM01 device, it is also possible to
poll the busy flag by sending the RDSR command only
once, and repeatedly clocking out the data until the
busy bit is clear. Only the RDSR instruction is enabled
during the store and recall cycles.
2018-2019 Microchip Technology Inc.
FIGURE 11-3:
POLLING FLOW
Send Store or Recall
Command
Deassert CS High to
Initiate Operation
Send RDSR
Instruction to the Device
NO
RDY/BSY = 0?
YES
Next Operation
DS20006008C-page 25
48L512/48LM01
FIGURE 11-4:
AUTOSTORE/AUTORECALL SCENARIOS (WITH ASE = 0, ARRAY MODIFIED)
VCC
VCAP
VTRIP
VPOR
AutoStore
TSTORE
AutoRecall
TRESTORE
Device Access
Enabled
Array Modified
CHARGE_CAP
(1)
VCC
VCAP
AutoStore
VTRIP
VPOR
TSTORE
AutoRecall
Device Access
Enabled
Array Modified
(1)
CHARGE_CAP
VCC
VCAP
AutoStore
VTRIP
VPOR
TSTORE
AutoRecall
TRESTORE
Device Access
Enabled
Array Modified
CHARGE_CAP (1)
Note 1:
When CHARGE_CAP is a ‘0’, VCC is connected to VCAP, allowing VCC to charge the external capacitor. See
Section 13.1 "Power Switchover" for details.
2018-2019 Microchip Technology Inc.
DS20006008C-page 26
48L512/48LM01
FIGURE 11-5:
AUTOSTORE/AUTORECALL SCENARIOS (WITH ASE = 1 OR ARRAY NOT
MODIFIED)
VCC
VCAP
VTRIP
VPOR
AutoStore
AutoRecall
Device Access
Enabled
Array Modified
CHARGE_CAP
(1)
VCC
VCAP
VTRIP
VPOR
AutoStore
AutoRecall
TRESTORE
Device Access
Enabled
Array Modified
CHARGE_CAP
Note 1:
(1)
When CHARGE_CAP is a ‘0’, VCC is connected to VCAP, allowing VCC to charge the external capacitor. See
Section 13.1 "Power Switchover" for details.
2018-2019 Microchip Technology Inc.
DS20006008C-page 27
48L512/48LM01
12.0
HIBERNATION
Exiting the Hibernation state requires either a power
cycle, or that the CS pin be brought low to begin
awakening from hibernation. After a time of TRESTORE,
the device will again be ready to operate. All data in
the EEPROM portion of the memory cells will be
transferred back to the SRAM portion of the memory
cells, and the nonvolatile user space and register
values will also be restored.
The 48LXXX devices include a very low-power Hibernation mode. The Hibernation mode is initiated by
sending the Hibernate instruction. Once received, the
CS pin returns high, the device performs a store operation if the array has been modified since the last store
or recall, and then the device enters a low-power state.
FIGURE 12-1:
HIBERNATE WAVEFORM
CS
TSTORE THIBERNATE TRESTORE
0
1
2
3
4
5
6
Instruction
7
SCK
Hibernate Opcode
SI
1
0
1
1
1
0
0
1
MSb
High-Impedance
SO
13.0
TRIP VOLTAGE
The 48LXXX has an internal voltage reference that is
used to create a trip voltage threshold (VTRIP). When
VCAP rises above VTRIP, a power-up event is detected.
If this is the first power-up event after a POR, then an
AutoRecall operation is initiated. When VCAP falls
below VTRIP, a power-down event is detected and an
AutoStore operation is initiated if the ASE in the
STATUS register is set to ‘1’ and if the array has been
modified.
Note: When VCAP is below VTRIP, the 48LXXX
cannot be accessed and will not
Acknowledge any commands.
13.1
Power Switchover
Once VCC is disconnected, it will not be reconnected
until both VCC is greater than VCAP and any internal
store cycles (AutoStore or Software Store) are complete. This guards against continuously connecting
and disconnecting VCC when VCAP falls faster than
VCC.
To support the AutoStore feature, the 48LXXX must be
able to charge the capacitor connected to the VCAP pin
when power is available on VCC, and also automatically
switch to being powered from the VCAP pin when power
is removed internal to the device from VCC. Since the
VCAP pin is used as part of the internal power bus, this
means that the VCC pin must be disconnected internally to the device when power to the system ceases.
2018-2019 Microchip Technology Inc.
To accomplish this, the 48LXXX has an intelligent
power switchover circuit that continuously monitors the
voltages on both the VCC and VCAP pins.
During a power-up event, VCC is initially connected
internally in the device to the VCAP pin, allowing it to
rise above the VCAP pin voltage level. Once the VCC pin
voltage level is above the VCAP pin voltage level, the
VCAP pin is connected to the VCC pin internally,
charging the external capacitor back through the
device. When the VCAP pin voltage level rises to VTRIP,
the AutoRecall operation is triggered.
During a power-down event, the VCC pin is initially connected to the internal power bus. As Vcc falls, it discharges the external cap, causing VCAP to also fall.
Once the VCAP pin voltage level falls below VTRIP, the
AutoStore operation is triggered, and the VCC pin is disconnected internally to prevent discharging the external VCAP capacitor any further through the VCC pin.
Once the VCC pin is disconnected internally, it will not
be reconnected until both the VCC pin voltage is greater
than the VCAP pin voltage and any internal store cycles
(AutoStore or Software Store) are complete.This
guards against continuously internally connecting and
disconnecting the VCC pin to the VCAP pin when the
VCAP voltage falls faster than the VCC voltage as it
moves the SRAM data to EEPROM backup.
DS20006008C-page 28
48L512/48LM01
14.0
PACKAGING INFORMATION
14.1
Package Marking Information
8-Lead SOIC
Example
48L512
SN e3 1940
13F
8-Lead SOIJ
Example
48LM01
SM e3
194013F
2018-2019 Microchip Technology Inc.
DS20006008C-page 29
48L512/48LM01
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
D
NOTE 5
N
E
2
E1
2
E1
E
NOTE 1
2
1
e
B
NX b
0.25
C A–B D
NOTE 5
TOP VIEW
0.10 C
C
A A2
SEATING
PLANE
8X
A1
SIDE VIEW
0.10 C
h
R0.13
h
R0.13
H
SEE VIEW C
VIEW A–A
0.23
L
(L1)
VIEW C
Microchip Technology Drawing No. C04-057-SN Rev E Sheet 1 of 2
2018-2019 Microchip Technology Inc.
DS20006008C-page 30
48L512/48LM01
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Molded Package Thickness
A2
§
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Chamfer (Optional)
h
Foot Length
L
Footprint
L1
Foot Angle
c
Lead Thickness
b
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
1.25
0.10
0.25
0.40
0°
0.17
0.31
5°
5°
MILLIMETERS
NOM
8
1.27 BSC
6.00 BSC
3.90 BSC
4.90 BSC
1.04 REF
-
MAX
1.75
0.25
0.50
1.27
8°
0.25
0.51
15°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-SN Rev E Sheet 2 of 2
2018-2019 Microchip Technology Inc.
DS20006008C-page 31
48L512/48LM01
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
C
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
MIN
MILLIMETERS
NOM
1.27 BSC
5.40
MAX
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2057-SN Rev E
2018-2019 Microchip Technology Inc.
DS20006008C-page 32
48L512/48LM01
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2018-2019 Microchip Technology Inc.
DS20006008C-page 33
48L512/48LM01
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2018-2019 Microchip Technology Inc.
DS20006008C-page 34
48L512/48LM01
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2018-2019 Microchip Technology Inc.
DS20006008C-page 35
48L512/48LM01
APPENDIX A:
REVISION HISTORY
Revision C (10/2019)
Updated Electrical Characteristics and Product Identification System sections.
Revision B (10/2018)
Revised references to EEPROM; Corrected waveforms; Updated Electrical Characteristics section;
Changed ASDIS bit name to ASE bit.
Revision A (04/2018)
Initial release of this document.
2018-2019 Microchip Technology Inc.
DS20006008C-page 36
48L512/48LM01
THE MICROCHIP WEBSITE
CUSTOMER SUPPORT
Microchip provides online support via our website at
www.microchip.com. This website is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the website contains the following information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers
should
contact
their
distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the website
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
2018-2019 Microchip Technology Inc.
DS20006008C-page 37
48L512/48LM01
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
[X]
PART NO.
Device
(1)
Tape and Reel
Option
-X
/XX
Temperature
Range
Package
Device:
48L512 = 512-Kbit SPI Serial EERAM
48LM01 = 1-Mbit SPI Serial EERAM
Tape and Reel
Option:
Blank
T
= Standard packaging (tube or tray)
= Tape and Reel(1)
Temperature
Range:
I
= -40°C to +85°C (Industrial)
Package:
SN
Examples:
a) 48L512T-I/SN =Tape and Reel, Industrial Temp.,
2.7V-3.6V, SOIC Package.
b) 48LM01-I/SM = Industrial Temp., 2.7V-3.6V,
SOIJ Package.
Note
SM
= 8-Lead Plastic Small Outline – Narrow, 3.90 mm
Body SOIC (512K only)
= 8-Lead Plastic Small Outline – Medium, 5.28 mm
Body SOIJ (1M only)
2018-2019 Microchip Technology Inc.
1:
Tape and Reel identifier only appears in
the catalog part number description. This
identifier is used for ordering purposes
and is not printed on the device package.
Check with your Microchip Sales Office
for package availability with the Tape and
Reel option.
DS20006008C-page 38
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2018-2019, Microchip Technology Incorporated, All Rights
Reserved.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2018-2019 Microchip Technology Inc.
ISBN: 978-1-5224-5202-7
DS20006008C-page 39
Worldwide Sales and Service
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2018-2019 Microchip Technology Inc.
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DS20006008C-page 40
05/14/19
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