Features
• Single 2.7V − 3.6V Supply
• Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 and 3
Supports Atmel RapidS Operation
Supports Dual-Input Program and Dual-Output Read
• Very High Operating Frequencies
100MHz for RapidS
75MHz for SPI
Clock-to-Output (tV) of 5ns Maximum
• Flexible, Optimized Erase Architecture for Code + Data Storage Applications
Uniform 4-Kbyte Block Erase
Uniform 32-Kbyte Block Erase
Uniform 64-Kbyte Block Erase
Full Chip Erase
64-Mbit, 2.7V
Minimum Serial
Peripheral Interface
Serial Flash Memory
Atmel AT25DF641
• Individual Sector Protection with Global Protect/Unprotect Feature
128 Sectors of 64-Kbytes Each
• Hardware Controlled Locking of Protected Sectors via WP Pin
• Sector Lockdown
Make Any Combination of 64-Kbyte Sectors Permanently Read-Only
• 128-Byte Programmable OTP Security Register
• Flexible Programming
Byte/Page Program (1- to 256-Bytes)
• Fast Program and Erase Times
1.0ms Typical Page Program (256-Bytes) Time
50ms Typical 4-Kbyte Block Erase Time
250ms Typical 32-Kbyte Block Erase Time
400ms Typical 64-Kbyte Block Erase Time
• Program and Erase Suspend/Resume
• Automatic Checking and Reporting of Erase/Program Failures
• Software Controlled Reset
• JEDEC Standard Manufacturer and Device ID Read Methodology
• Low Power Dissipation
5mA Active Read Current (Typical at 20MHz)
5µA Deep Power-Down Current (Typical)
• Endurance: 100,000 Program/Erase Cycles
• Data Retention: 20 Years
• Complies with Full Industrial Temperature Range
• Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
16-Lead SOIC (300-mil wide)
8-Contact Very Thin DFN (6 x 8mm)
3680F–DFLASH–4/10
Description
The Atmel® AT25DF641 is a serial interface Flash memory device designed for use in a wide variety of highvolume consumer based applications in which program code is shadowed from Flash memory into embedded or
external RAM for execution. The flexible erase architecture of the AT25DF641, with its erase granularity as small
as 4-Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM
devices.
The physical sectoring and the erase block sizes of the AT25DF641 have been optimized to meet the needs of
today's code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the
memory space can be used much more efficiently. Because certain code modules and data storage segments
must reside by themselves in their own protected sectors, the wasted and unused memory space that occurs with
large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory
space efficiency allows additional code routines and data storage segments to be added while still maintaining the
same overall device density.
The AT25DF641 also offers a sophisticated method for protecting individual sectors against erroneous or
malicious program and erase operations. By providing the ability to individually protect and unprotect sectors, a
system can unprotect a specific sector to modify its contents while keeping the remaining sectors of the memory
array securely protected. This is useful in applications where program code is patched or updated on a subroutine
or module basis or in applications where data storage segments need to be modified without running the risk of
errant modifications to the program code segments. In addition to individual sector protection capabilities, the
AT25DF641 incorporates Global Protect and Global Unprotect features that allow the entire memory array to be
either protected or unprotected all at once. This reduces overhead during the manufacturing process since
sectors do not have to be unprotected one-by-one prior to initial programming.
To take code and data protection to the next level, the AT25DF641 incorporates a sector lockdown mechanism
that allows any combination of individual 64-Kbyte sectors to be locked down and become permanently read-only.
This addresses the need of certain secure applications that require portions of the Flash memory array to be
permanently protected against malicious attempts at altering program code, data modules, security information, or
encryption/decryption algorithms, keys, and routines. The device also contains a specialized OTP (One-Time
Programmable) Security Register that can be used for purposes such as unique device serialization, system-level
Electronic Serial Number (ESN) storage, locked key storage, etc.
Specifically designed for use in 3-volt systems, the AT25DF641 supports read, program, and erase operations
with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for programming and erasing.
2
Atmel AT25DF641
3680F–DFLASH–4/10
Atmel AT25DF641
1.
Pin Descriptions and Pinouts
Table 1-1.
Symbol
CS
Pin Descriptions
Name and Function
CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is
deasserted, the device will be deselected and normally be placed in standby
mode (not Deep Power-Down mode), and the SO pin will be in a high-impedance
state. When the device is deselected, data will not be accepted on the SI pin.
A high-to-low transition on the CS pin is required to start an operation, and a lowto-high transition is required to end an operation. When ending an internally selftimed operation such as a program or erase cycle, the device will not enter the
standby mode until the completion of the operation.
SCK
SI (SIO)
SERIAL CLOCK: This pin is used to provide a clock to the device and is used to
control the flow of data to and from the device. Command, address, and input
data present on the SI pin is always latched in on the rising edge of SCK, while
output data on the SO pin is always clocked out on the falling edge of SCK.
SERIAL INPUT (SERIAL INPUT/OUTPUT): The SI pin is used to shift data into
the device. The SI pin is used for all data input including command and address
sequences. Data on the SI pin is always latched in on the rising edge of SCK.
With the Dual-Output Read Array command, the SI pin becomes an output pin
(SIO) to allow two bits of data (on the SO and SIO pins) to be clocked out on
every falling edge of SCK. To maintain consistency with SPI nomenclature, the
SIO pin will be referenced as SI throughout the document with exception to
sections dealing with the Dual-Output Read Array command in which it will be
referenced as SIO.
Data present on the SI pin will be ignored whenever the device is deselected
Asserted
State
Type
Low
Input
−
Input
−
Input/Output
−
Output/Input
Low
Input
( CS is deasserted).
SERIAL OUTPUT (SERIAL OUTPUT/INPUT): The SO pin is used to shift data
out from the device. Data on the SO pin is always clocked out on the falling edge
of SCK.
SO (SOI)
With the Dual-Input Byte/Page Program command, the SO pin becomes an input
pin (SOI) to allow two bits of data (on the SOI and SI pins) to be clocked in on
every rising edge of SCK. To maintain consistency with SPI nomenclature, the
SOI pin will be referenced as SO throughout the document with exception to
sections dealing with the Dual-Input Byte/Page Program command in which it will
be referenced as SOI.
The SO pin will be in a high-impedance state whenever the device is deselected
( CS is deasserted).
WP
WRITE PROTECT: The WP pin controls the hardware locking feature of the
device. Please refer to “Protection Commands and Features” on page 21 for more
details on protection features and the WP pin.
The WP pin is internally pulled-high and may be left floating if hardware
controlled protection will not be used. However, it is recommended that the WP
pin also be externally connected to VCC whenever possible.
3
3680F–DFLASH–4/10
Table 1-1.
Pin Descriptions (Continued)
Asserted
State
Type
Low
Input
VCC
DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the
device.
Operations at invalid VCC voltages may produce spurious results and should not be
attempted.
−
Power
GND
GROUND: The ground reference for the power supply. GND should be connected to the
system ground.
−
Power
Symbol
Name and Function
HOLD: The HOLD pin is used to temporarily pause serial communication without
deselecting or resetting the device. While the HOLD pin is asserted, transitions on the
SCK pin and data on the SI pin will be ignored, and the SO pin will be in a highimpedance state.
HOLD
The CS pin must be asserted, and the SCK pin must be in the low state in order for a
Hold condition to start. A Hold condition pauses serial communication only and does not
have an effect on internally self-timed operations such as a program or erase cycle.
Please refer to “Hold” on page 45 for additional details on the Hold operation.
The HOLD pin is internally pulled-high and may be left floating if the Hold function will not
be used. However, it is recommended that the HOLD pin also be externally connected to
VCC whenever possible.
Figure 1-1.
CS
SO (SOI)
WP
GND
4
8-VDFN (Top View)
1
8 VCC
2
7 HOLD
3
6 SCK
4
5 SI (SIO)
Figure 1-2.
16-SOIC (Top View)
HOLD
VCC
1
16
2
15
NC
NC
NC
NC
CS
SO (SOI)
3
14
4
13
5
12
6
11
7
10
8
9
SCK
SI(SIO)
NC
NC
NC
NC
GND
WP
Atmel AT25DF641
3680F–DFLASH–4/10
Atmel AT25DF641
Block Diagram
Figure 2-1.
Block Diagram
CONTROL AND
PROTECTION LOGIC
CS
SCK
SI (SIO)
SO (SOI)
WP
HOLD
I/O BUFFERS
AND LATCHES
SRAM
DATA BUFFER
INTERFACE
CONTROL
AND
LOGIC
Y-DECODER
ADDRESS LATCH
2.
X-DECODER
Y-GATING
FLASH
MEMORY
ARRAY
5
3680F–DFLASH–4/10
3.
Memory Array
To provide the greatest flexibility, the memory array of the Atmel® AT25DF641 can be erased in four levels of
granularity including a full chip erase. In addition, the array has been divided into physical sectors of uniform size,
of which each sector can be individually protected from program and erase operations. The size of the physical
sectors is optimized for both code and data storage applications, allowing both code and data segments to reside
in their own isolated regions. The Memory Architecture Diagram illustrates the breakdown of each erase level as
well as the breakdown of each physical sector.
Memory Architecture Diagram
Block Erase Detail
64KB
Block Erase
(D8h Command)
32KB
Block Erase
(52h Command)
32KB
64KB
(Sector 127)
64KB
32KB
32KB
64KB
(Sector 126)
64KB
•••
•••
•••
32KB
32KB
64KB
(Sector 0)
64KB
32KB
6
4KB
Block Erase
(20h Command)
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
Block Address
Range
7FFFFFh – 7FF000h
7FEFFFh– 7FE000h
7FDFFFh – 7FD000h
7FCFFFh – 7FC000h
7FBFFFh – 7FB000h
7FAFFFh – 7FA000h
7F9FFFh – 7F9000h
7F8FFFh – 7F8000h
7F7FFFh – 7F7000h
7F6FFFh – 7F6000h
7F5FFFh – 7F5000h
7F4FFFh – 7F4000h
7F3FFFh – 7F3000h
7F2FFFh – 7F2000h
7F1FFFh – 7F1000h
7F0FFFh – 7F0000h
7EFFFFh– 7EF000h
7EEFFFh– 7EE000h
7EDFFFh – 7ED000h
7ECFFFh– 7EC000h
7EBFFFh– 7EB000h
7EAFFFh – 7EA000h
7E9FFFh – 7E9000h
7E8FFFh – 7E8000h
7E7FFFh – 7E7000h
7E6FFFh – 7E6000h
7E5FFFh – 7E5000h
7E4FFFh – 7E4000h
7E3FFFh – 7E3000h
7E2FFFh – 7E2000h
7E1FFFh – 7E1000h
7E0FFFh – 7E0000h
•••
Internal Sectoring for
Protection, Lockdown,
and Suspend Functions
Page Program Detail
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
4KB
00FFFFh – 00F000h
00EFFFh – 00E000h
00DFFFh – 00D000h
00CFFFh – 00C000h
00BFFFh – 00B000h
00AFFFh – 00A000h
009FFFh – 009000h
008FFFh – 008000h
007FFFh – 007000h
006FFFh – 006000h
005FFFh – 005000h
004FFFh – 004000h
003FFFh – 003000h
002FFFh – 002000h
001FFFh – 001000h
000FFFh – 000000h
1-256 Byte
Page Program
(02h Command)
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
Page Address
Range
7FFFFFh – 7FFF00h
7FFEFFh– 7FFE00h
7FFDFFh – 7FFD00h
7FFCFFh – 7FFC00h
7FFBFFh – 7FFB00h
7FFAFFh – 7FFA00h
7FF9FFh – 7FF900h
7FF8FFh – 7FF800h
7FF7FFh – 7FF700h
7FF6FFh – 7FF600h
7FF5FFh – 7FF500h
7FF4FFh – 7FF400h
7FF3FFh – 7FF300h
7FF2FFh – 7FF200h
7FF1FFh – 7FF100h
7FF0FFh – 7FF000h
7FEFFFh– 7FEF00h
7FEEFFh– 7FEE00h
7FEDFFh – 7FED00h
7FECFFh– 7FEC00h
7FEBFFh– 7FEB00h
7FEAFFh – 7FEA00h
7FE9FFh – 7FE900h
7FE8FFh – 7FE800h
•••
Figure 3-1.
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
0017FFh – 001700h
0016FFh – 001600h
0015FFh – 001500h
0014FFh – 001400h
0013FFh – 001300h
0012FFh – 001200h
0011FFh – 001100h
0010FFh – 001000h
000FFFh – 000F00h
000EFFh – 000E00h
000DFFh – 000D00h
000CFFh – 000C00h
000BFFh – 000B00h
000AFFh – 000A00h
0009FFh – 000900h
0008FFh – 000800h
0007FFh – 000700h
0006FFh – 000600h
0005FFh – 000500h
0004FFh – 000400h
0003FFh – 000300h
0002FFh – 000200h
0001FFh – 000100h
0000FFh – 000000h
Atmel AT25DF641
3680F–DFLASH–4/10
Atmel AT25DF641
4.
Device Operation
The Atmel® AT25DF641 is controlled by a set of instructions that are sent from a host controller, commonly
referred to as the SPI Master. The SPI Master communicates with the AT25DF641 via the SPI bus which is
comprised of four signal lines: Chip Select ( CS ), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).
The AT25DF641 features a dual-input program mode in which the SO pin become an input. Similarly, the device
also features a dual-output read mode in which the SI pin becomes an output. In the Dual-Input Byte/Page
Program command description, the SO pin will be referred to as the SOI (Serial Output/Input) pin, and in the DualOutput Read Array command, the SI pin will be referenced as the SIO (Serial Input/Output) pin.
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in
respect to the SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus.
The AT25DF641 supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI
Modes 0 and 3 is the polarity of the SCK signal when in the inactive state (when the SPI Master is in standby
mode and not transferring any data). With SPI Modes 0 and 3, data is always latched in on the rising edge of
SCK and always output on the falling edge of SCK.
Figure 4-1.
SPI Mode 0 and 3
CS
SCK
SI
MS B
SO
5.
LS B
MS B
LS B
Commands and Addressing
A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been
asserted, the host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode,
instruction dependent information such as address and data bytes would then be clocked out by the host
controller. All opcode, address, and data bytes are transferred with the most-significant bit (MSB) first. An
operation is ended by deasserting the CS pin.
Opcodes not supported by the AT25DF641 will be ignored by the device and no operation will be started. The
device will continue to ignore any data presented on the SI pin until the start of the next operation ( CS pin being
deasserted and then reasserted). In addition, if the CS pin is deasserted before complete opcode and address
information is sent to the device, then no operation will be performed and the device will simply return to the idle
state and wait for the next operation.
Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23A0. Since the upper address limit of the AT25DF641 memory array is 7FFFFFh, address bit A23 is always
ignored by the device.
7
3680F–DFLASH–4/10
Table 5-1.
Command Listing
Command
Opcode
Clock
Frequency
Address
Bytes
Dummy
Bytes
Data
Bytes
Read Commands
1Bh
0001 1011
Up to 75MHz
3
2
1+
0Bh
0000 1011
Up to 75MHz
3
1
1+
03h
0000 0011
Up to 45MHz
3
0
1+
3Bh
0011 1011
Up to 55MHz
3
1
1+
Block Erase (4-KBytes)
20h
0010 0000
Up to 75MHz
3
0
0
Block Erase (32-KBytes)
52h
0101 0010
Up to 75MHz
3
0
0
Block Erase (64-KBytes)
D8h
1101 1000
Up to 75MHz
3
0
0
60h
0110 0000
Up to 75 MHz
0
0
0
Read Array
Dual-Output Read Array
Program and Erase Commands
Chip Erase
C7h
1100 0111
Up to 75MHz
0
0
0
Byte/Page Program (1 to 256 Bytes)
02h
0000 0010
Up to 75MHz
3
0
1+
Dual-Input Byte/Page Program (1 to 256 Bytes)
A2h
1010 0010
Up to 75MHz
3
0
1+
Program/Erase Suspend
B0h
1011 0000
Up to 75MHz
0
0
0
Program/Erase Resume
D0h
1101 0000
Up to 75MHz
0
0
0
Write Enable
06h
0000 0110
Up to 75MHz
0
0
0
Write Disable
04h
0000 0100
Up to 75MHz
0
0
0
Protect Sector
36h
0011 0110
Up to 75MHz
3
0
0
Unprotect Sector
39h
0011 1001
Up to 75MHz
3
0
0
Protection Commands
Global Protect/Unprotect
Read Sector Protection Registers
Use Write Status Register Byte 1 Command
3Ch
0011 1100
Up to 75MHz
3
0
1+
Sector Lockdown
33h
0011 0011
Up to 75MHz
3
0
1
Freeze Sector Lockdown State
34h
0011 0100
Up to 75MHz
3
0
1
Read Sector Lockdown Registers
35h
0011 0101
Up to 75MHz
3
0
1+
Program OTP Security Register
9Bh
1001 1011
Up to 75MHz
3
0
1+
Read OTP Security Register
77h
0111 0111
Up to 75MHz
3
2
1+
Read Status Register
05h
0000 0101
Up to 75MHz
0
0
1+
Write Status Register Byte 1
01h
0000 0001
Up to 75MHz
0
0
1
Write Status Register Byte 2
31h
0011 0001
Up to 75MHz
0
0
1
F0h
1111 0000
Up to 75MHz
0
0
1
Read Manufacturer and Device ID
9Fh
1001 1111
Up to 75MHz
0
0
1 to 4
Deep Power-Down
B9h
1011 1001
Up to 75MHz
0
0
0
Resume from Deep Power-Down
ABh
1010 1011
Up to 75MHz
0
0
0
Security Commands
Status Register Commands
Miscellaneous Commands
Reset
8
Atmel AT25DF641
3680F–DFLASH–4/10
Atmel AT25DF641
6.
Read Commands
6.1.
Read Array
The Read Array command can be used to sequentially read a continuous stream of data from the device by
simply providing the clock signal once the initial starting address has been specified. The device incorporates an
internal address counter that automatically increments on every clock cycle.
Three opcodes (1Bh, 0Bh, and 03h) can be used for the Read Array command. The use of each opcode depends
on the maximum clock frequency that will be used to read data from the device. The 0Bh opcode can be used at
any clock frequency up to the maximum specified by fCLK, and the 03h opcode can be used for lower frequency
read operations up to the maximum specified by fRDLF. The 1Bh opcode allows the highest read performance
possible and can be used at any clock frequency up to the maximum specified by fMAX; however, use of the 1Bh
opcode at clock frequencies above fCLK should be reserved to systems employing the RapidS protocol.
To perform the Read Array operation, the CS pin must first be asserted and the appropriate opcode (1Bh, 0Bh, or
03h) must be clocked into the device. After the opcode has been clocked in, the three address bytes must be
clocked in to specify the starting address location of the first byte to read within the memory array. Following the
three address bytes, additional dummy bytes may need to be clocked into the device depending on which opcode
is used for the Read Array operation. If the 1Bh opcode is used, then two dummy bytes must be clocked into the
device after the three address bytes. If the 0Bh opcode is used, then a single dummy byte must be clocked in
after the address bytes.
After the three address bytes (and the dummy bytes or byte if using opcodes 1Bh or 0Bh) have been clocked in,
additional clock cycles will result in data being output on the SO pin. The data is always output with the MSB of a
byte first. When the last byte (7FFFFFh) of the memory array has been read, the device will continue reading
back at the beginning of the array (000000h). No delays will be incurred when wrapping around from the end of
the array to the beginning of the array.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS
pin can be deasserted at any time and does not require that a full byte of data be read.
Figure 6-1.
Read Array - 1Bh Opcode
CS
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
10 11 12
SCK
OPCODE
SI
0
0
0
1
1
MS B
DON'T CAR E
ADDR E S S BITS A23-A0
0
1
1
A
MS B
A
A
A
A
A
A
A
A
X
MS B
X
X
X
X
X
DON'T CAR E
X
X
X
X
X
X
X
X
X
X
MS B
DATA BYTE 1
SO
HIGH-IMPE DANCE
D
MS B
D
D
D
D
D
D
D
D
D
MS B
9
3680F–DFLASH–4/10
Figure 6-2.
Read Array - 0Bh Opcode
CS
0
1
2
3
4
6
5
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
SCK
OP C ODE
SI
0
0
0
0
ADDR E S S B ITS A23-A0
1
0
1
1
MS B
A
A
A
A
A
A
A
DON'T C AR E
A
A
MS B
X
X
X
X
X
X
X
X
MS B
DATA B Y TE 1
SO
HIG H-IMP E DANC E
D
D
D
MS B
Figure 6-3.
D
D
D
D
D
D
D
MS B
Read Array - 03h Opcode
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40
SCK
OP C ODE
SI
0
0
0
0
0
ADDR E S S B IT S A23-A0
0
MS B
1
1
A
A
A
A
A
A
A
A
A
MS B
DAT A B Y T E 1
SO
HIG H-IMP E DANC E
D
MS B
10
D
D
D
D
D
D
D
D
D
MS B
Atmel AT25DF641
3680F–DFLASH–4/10
Atmel AT25DF641
6.2.
Dual-Output Read Array
The Dual-Output Read Array command is similar to the standard Read Array command and can be used to
sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial
starting address has been specified. Unlike the standard Read Array command, however, the Dual-Output Read
Array command allows two bits of data to be clocked out of the device on every clock cycle rather than just one.
The Dual-Output Read Array command can be used at any clock frequency up to the maximum specified by fRDDO.
To perform the Dual-Output Read Array operation, the CS pin must first be asserted and the opcode of 3Bh must
be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to
specify the starting address location of the first byte to read within the memory array. Following the three address
bytes, a single dummy byte must also be clocked into the device.
After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data
being output on both the SO and SIO pins. The data is always output with the MSB of a byte first, and the MSB is
always output on the SO pin. During the first clock cycle, bit seven of the first data byte will be output on the SO
pin while bit six of the same data byte will be output on the SIO pin. During the next clock cycle, bits five and four
of the first data byte will be output on the SO and SIO pins, respectively. The sequence continues with each byte
of data being output after every four clock cycles. When the last byte (7FFFFFh) of the memory array has been
read, the device will continue reading back at the beginning of the array (000000h). No delays will be incurred
when wrapping around from the end of the array to the beginning of the array.
Deasserting the CS pin will terminate the read operation and put the SO and SIO pins into a high-impedance
state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.
Figure 6-4.
Dual-Output Read Array
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
SCK
SI
0
0
1
1
1
MS B
SO
HIG H-IMP E DANC E
0
1
1
A
MS B
A
A
A
A
A
A
OUT P UT
OUT P UT
DAT A B Y T E 1 DAT A B Y T E 2
DON'T C AR E
ADDR E S S B ITS A23-A0
OP C ODE
A
A
X
X
X
X
X
X
X
X
D6 D4 D2 D0 D6 D4 D2 D0 D6 D4
MS B
D7 D5 D3 D1 D7 D5 D3 D1 D7 D5
MS B
MS B
11
3680F–DFLASH–4/10
7.
Program and Erase Commands
7.1.
Byte/Page Program
The Byte/Page Program command allows anywhere from a single byte of data to 256-bytes of data to be
programmed into previously erased memory locations. An erased memory location is one that has all eight bits
set to the logical “1” state (a byte value of FFh). Before a Byte/Page Program command can be started, the Write
Enable command must have been previously issued to the device (see “Write Enable” on page 21) to set the
Write Enable Latch (WEL) bit of the Status Register to a logical “1” state.
To perform a Byte/Page Program command, an opcode of 02h must be clocked into the device followed by the
three address bytes denoting the first byte location of the memory array to begin programming at. After the
address bytes have been clocked in, data can then be clocked into the device and will be stored in an internal
buffer.
If the starting memory address denoted by A23-A0 does not fall on an even 256-byte page boundary (A7-A0 are
not all 0), then special circumstances regarding which memory locations to be programmed will apply. In this
situation, any data that is sent to the device that goes beyond the end of the page will wrap around back to the
beginning of the same page. For example, if the starting address denoted by A23-A0 is 0000FEh, and three bytes
of data are sent to the device, then the first two bytes of data will be programmed at addresses 0000FEh and
0000FFh while the last byte of data will be programmed at address 000000h. The remaining bytes in the page
(addresses 000001h through 0000FDh) will not be programmed and will remain in the erased state (FFh). In
addition, if more than 256-bytes of data are sent to the device, then only the last 256-bytes sent will be latched
into the internal buffer.
When the CS pin is deasserted, the device will take the data stored in the internal buffer and program it into the
appropriate memory array locations based on the starting address specified by A23-A0 and the number of data
bytes sent to the device. If less than 256-bytes of data were sent to the device, then the remaining bytes within
the page will not be programmed and will remain in the erased state (FFh). The programming of the data bytes is
internally self-timed and should take place in a time of tPP or tBP if only programming a single byte.
The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin
is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the
device will abort the operation and no data will be programmed into the memory array. In addition, if the address
specified by A23-A0 points to a memory location within a sector that is in the protected state (see “Protect Sector”
on page 22) or locked down (see “Sector Lockdown” on page 28), then the Byte/Page Program command will not
be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the
Status Register will be reset back to the logical “0” state if the program cycle aborts due to an incomplete address
being sent, an incomplete byte of data being sent, the CS pin being deasserted on uneven byte boundaries, or
because the memory location to be programmed is protected or locked down.
While the device is programming, the Status Register can be read and will indicate that the device is busy. For
faster throughput, it is recommended that the Status Register be polled rather than waiting the tBP or tPP time to
determine if the data bytes have finished programming. At some point before the program cycle completes, the
WEL bit in the Status Register will be reset back to the logical “0” state.
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to
program properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register
12
Atmel AT25DF641
3680F–DFLASH–4/10
Atmel AT25DF641
Figure 7-1.
Byte Program
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 3 9
SCK
O P C O DE
SI
0
0
0
0
ADDR E S S B IT S A23-A0
0
0
1
0
MS B
SO
Figure 7-2.
A
A
A
A
A
A
A
DAT A IN
A
A
MS B
D
D
D
D
D
D
D
D
MS B
HIG H-IMP E DANC E
Page Program
CS
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38 39
SCK
OP C ODE
SI
0
0
0
0
0
ADDR E S S B IT S A23-A0
0
MS B
SO
7.2.
1
0
A
MS B
A
A
A
A
A
DAT A IN B Y T E 1
D
MS B
D
D
D
D
D
D
DAT A IN B Y T E n
D
D
D
D
D
D
D
D
D
MS B
HIG H-IMP E DANC E
Dual-Input Byte/Page Program
The Dual-Input Byte/Page Program command is similar to the standard Byte/Page Program command and can be
used to program anywhere from a single byte of data up to 256-bytes of data into previously erased memory
locations. Unlike the standard Byte/Page Program command, however, the Dual-Input Byte/Page Program
command allows two bits of data to be clocked into the device on every clock cycle rather than just one.
Before the Dual-Input Byte/Page Program command can be started, the Write Enable command must have been
previously issued to the device (see “Write Enable” on page 21) to set the Write Enable Latch (WEL) bit of the
Status Register to a logical “1” state. To perform a Dual-Input Byte/Page Program command, an opcode of A2h
must be clocked into the device followed by the three address bytes denoting the first byte location of the memory
array to begin programming at. After the address bytes have been clocked in, data can then be clocked into the
device two bits at a time on both the SOI and SI pins.
The data is always input with the MSB of a byte first, and the MSB is always input on the SOI pin. During the first
clock cycle, bit seven of the first data byte would be input on the SOI pin while bit six of the same data byte would
be input on the SI pin. During the next clock cycle, bits five and four of the first data byte would be input on the
SOI and SI pins, respectively. The sequence would continue with each byte of data being input after every four
clock cycles. Like the standard Byte/Page Program command, all data clocked into the device is stored in an
internal buffer.
13
3680F–DFLASH–4/10
If the starting memory address denoted by A23-A0 does not fall on an even 256-byte page boundary (A7-A0 are
not all 0), then special circumstances regarding which memory locations to be programmed will apply. In this
situation, any data that is sent to the device that goes beyond the end of the page will wrap around back to the
beginning of the same page. For example, if the starting address denoted by A23-A0 is 0000FEh, and three bytes
of data are sent to the device, then the first two bytes of data will be programmed at addresses 0000FEh and
0000FFh while the last byte of data will be programmed at address 000000h. The remaining bytes in the page
(addresses 000001h through 0000FDh) will not be programmed and will remain in the erased state (FFh). In
addition, if more than 256-bytes of data are sent to the device, then only the last 256-bytes sent will be latched
into the internal buffer.
When the CS pin is deasserted, the device will take the data stored in the internal buffer and program it into the
appropriate memory array locations based on the starting address specified by A23-A0 and the number of data
bytes sent to the device. If less than 256-bytes of data were sent to the device, then the remaining bytes within
the page will not be programmed and will remain in the erased state (FFh). The programming of the data bytes is
internally self-timed and should take place in a time of tPP or tBP if only programming a single byte.
The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin
is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the
device will abort the operation and no data will be programmed into the memory array. In addition, if the address
specified by A23-A0 points to a memory location within a sector that is in the protected state (see “Protect Sector”
on page 22) or locked down (see “Sector Lockdown” on page 28), then the Byte/Page Program command will not
be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the
Status Register will be reset back to the logical “0” state if the program cycle aborts due to an incomplete address
being sent, an incomplete byte of data being sent, the CS pin being deasserted on uneven byte boundaries, or
because the memory location to be programmed is protected or locked down.
While the device is programming, the Status Register can be read and will indicate that the device is busy. For
faster throughput, it is recommended that the Status Register be polled rather than waiting the tBP or tPP time to
determine if the data bytes have finished programming. At some point before the program cycle completes, the
WEL bit in the Status Register will be reset back to the logical “0” state.
The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to
program properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.
Figure 7-3.
Dual-Input Byte Program
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35
SCK
OP C ODE
SI
1
0
1
0
0
0
MS B
SOI
INP UT
DAT A B Y T E
ADDR E S S B IT S A23-A0
HIG H-IMP E DANC E
1
0
A
A
A
A
A
A
A
A
A
D6
D4
D2
D0
D7
D5
D3
D1
MS B
MS B
14
Atmel AT25DF641
3680F–DFLASH–4/10
Atmel AT25DF641
Figure 7-4.
Dual-Input Page Program
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39
SCK
ADDR E S S B IT S A23-A0
OP C ODE
SI
1
0
1
0
0
MS B
SOI
HIG H-IMP E DANC E
0
1
0
A
A
A
A
A
A
A
A
A
INP UT
DAT A B Y T E 1
INP UT
DAT A B Y T E 2
INP UT
DAT A B Y T E n
D6
D4
D2
D0
D6
D4
D2
D0
D6
D4
D2
D0
D7
D5
D3
D1
D7
D5
D3
D1
D7
D5
D3
D1
MS B
MS B
7.3.
MS B
MS B
Block Erase
A block of 4-, 32-, or 64-Kbytes can be erased (all bits set to the logical “1” state) in a single operation by using
one of three different opcodes for the Block Erase command. An opcode of 20h is used for a 4-Kbyte erase, an
opcode of 52h is used for a 32-Kbyte erase, and an opcode of D8h is used for a 64-Kbyte erase. Before a Block
Erase command can be started, the Write Enable command must have been previously issued to the device to
set the WEL bit of the Status Register to a logical “1” state.
To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h, 52h, or D8h) must
be clocked into the device. After the opcode has been clocked in, the three address bytes specifying an address
within the 4-, 32-, or 64-Kbyte block to be erased must be clocked in. Any additional data clocked into the device
will be ignored. When the CS pin is deasserted, the device will erase the appropriate block. The erasing of the
block is internally self-timed and should take place in a time of tBLKE.
Since the Block Erase command erases a region of bytes, the lower order address bits do not need to be
decoded by the device. Therefore, for a 4-Kbyte erase, address bits A11-A0 will be ignored by the device and
their values can be either a logical “1” or “0”. For a 32-Kbyte erase, address bits A14-A0 will be ignored, and for a
64-Kbyte erase, address bits A15-A0 will be ignored by the device. Despite the lower order address bits not being
decoded by the device, the complete three address bytes must still be clocked into the device before the CS pin is
deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the
device will abort the operation and no erase operation will be performed.
If the address specified by A23-A0 points to a memory location within a sector that is in the protected or locked
down state, then the Block Erase command will not be executed, and the device will return to the idle state once
the CS pin has been deasserted.
The WEL bit in the Status Register will be reset back to the logical “0” state if the erase cycle aborts due to an
incomplete address being sent, the CS pin being deasserted on uneven byte boundaries, or because a memory
location within the region to be erased is protected or locked down.
While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the
device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the
tBLKE time to determine if the device has finished erasing. At some point before the erase cycle completes, the
WEL bit in the Status Register will be reset back to the logical “0” state.
The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase
properly. If an erase error occurs, it will be indicated by the EPE bit in the Status Register.
15
3680F–DFLASH–4/10
Figure 7-5.
Block Erase
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
26 27 28 29 30 31
SCK
ADDR E S S B IT S A23-A0
OP C ODE
SI
C
C
C
C
C
C
MS B
SO
7.4.
C
C
A
A
A
A
A
A
A
A
A
A
A
A
MS B
HIG H-IMP E DANC E
Chip Erase
The entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chip
Erase command can be started, the Write Enable command must have been previously issued to the device to
set the WEL bit of the Status Register to a logical “1” state.
Two opcodes, 60h and C7h, can be used for the Chip Erase command. There is no difference in device
functionality when utilizing the two opcodes, so they can be used interchangeably. To perform a Chip Erase, one
of the two opcodes (60h or C7h) must be clocked into the device. Since the entire memory array is to be erased,
no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored.
When the CS pin is deasserted, the device will erase the entire memory array. The erasing of the device is
internally self-timed and should take place in a time of tCHPE.
The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be
deasserted on an even byte boundary (multiples of eight bits); otherwise, no erase will be performed. In addition,
if any sector of the memory array is in the protected or locked down state, then the Chip Erase command will not
be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the
Status Register will be reset back to the logical “0” state if the CS pin is deasserted on uneven byte boundaries or
if a sector is in the protected or locked down state.
While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the
device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the
tCHPE time to determine if the device has finished erasing. At some point before the erase cycle completes, the
WEL bit in the Status Register will be reset back to the logical “0” state.
The device also incorporates an intelligent erase algorithm that can detect when a byte location fails to erase
properly. If an erase error occurs, it will be indicated by the EPE bit in the Status Register.
16
Atmel AT25DF641
3680F–DFLASH–4/10
Atmel AT25DF641
Figure 7-6.
Chip Erase
CS
0
1
2
3
4
5
6
7
SCK
OP C ODE
SI
C
C
C
C
C
C
C
C
MS B
SO
7.5.
HIG H-IMP E DANC E
Program/Erase Suspend
In some code plus data storage applications, it is often necessary to process certain high-level system interrupts
that require relatively immediate reading of code or data from the Flash memory. In such an instance, it may not
be possible for the system to wait the microseconds or milliseconds required for the Flash memory to complete a
program or erase cycle. The Program/Erase Suspend command allows a program or erase operation in progress
to a particular 64-Kbyte sector of the Flash memory array to be suspended so that other device operations can be
performed. For example, by suspending an erase operation to a particular sector, the system can perform
functions such as a program or read operation within another 64-Kbyte sector in the device. Other device
operations, such as a Read Status Register, can also be performed while a program or erase operation is
suspended. Table 7-1 outlines the operations that are allowed and not allowed during a program or erase
suspend.
Since the need to suspend a program or erase operation is immediate, the Write Enable command does not need
to be issued prior to the Program/Erase Suspend command being issued. Therefore, the Program/Erase Suspend
command operates independently of the state of the WEL bit in the Status Register.
To perform a Program/Erase Suspend, the CS pin must first be asserted and the opcode of B0h must be clocked
into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode
will be ignored. When the CS pin is deasserted, the program or erase operation currently in progress will be
suspended within a time of tSUSP. The Program Suspend (PS) bit or the Erase Suspend (ES) bit in the Status
Register will then be set to the logical “1” state to indicate that the program or erase operation has been
suspended. In addition, the RDY/BSY bit in the Status Register will indicate that the device is ready for another
operation. The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin
must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no suspend operation will be
performed.
Read operations are not allowed to a 64-Kbyte sector that has had its program or erase operation suspended. If a
read is attempted to a suspended sector, then the device will output undefined data. Therefore, when performing
a Read Array operation to an unsuspended sector and the device’s internal address counter increments and
crosses the sector boundary to a suspended sector, the device will then start outputting undefined data
continuously until the address counter increments and crosses a sector boundary to an unsuspended sector.
17
3680F–DFLASH–4/10
A program operation is not allowed to a sector that has been erase suspended. If a program operation is
attempted to an erase suspended sector, then the program operation will abort and the WEL bit in the Status
Register will be reset back to the logical “0” state. Likewise, an erase operation is not allowed to a sector that has
been program suspended. If attempted, the erase operation will abort and the WEL bit in the Status Register will
be reset to a logical “0” state.
During an Erase Suspend, a program operation to a different 64-Kbyte sector can be started and subsequently
suspended. This results in a simultaneous Erase Suspend/Program Suspend condition and will be indicated by
the states of both the ES and PS bits in the Status Register being set to the logical “1” state.
If a Reset operation (see “Reset” on page 40) is performed while a sector is erase suspended, the suspend
operation will abort and the contents of the block in the suspended sector will be left in an undefined state.
However, if a Reset is performed while a sector is program suspended, the suspend operation will abort but only
the contents of the page that was being programmed and subsequently suspended will be undefined. The
remaining pages in the 64-Kbyte sector will retain their previous contents.
If an attempt is made to perform an operation that is not allowed during a program or erase suspend, such as a
Protect Sector operation, then the device will simply ignore the opcode and no operation will be performed. The
state of the WEL bit in the Status Register, as well as the SPRL (Sector Protection Registers Locked) and SLE
(Sector Lockdown Enabled) bits, will not be affected.
18
Atmel AT25DF641
3680F–DFLASH–4/10
Atmel AT25DF641
Table 7-1.
Operations Allowed and Not Allowed During a Program or Erase Suspend
Operation During
Program Suspend
Operation During
Erase Suspend
Allowed
Allowed
Block Erase
Not Allowed
Not Allowed
Chip Erase
Not Allowed
Not Allowed
Byte/Page Program (All Opcodes)
Not Allowed
Allowed
Program/Erase Suspend
Not Allowed
Allowed
Program/Erase Resume
Allowed
Allowed
Write Enable
Not Allowed
Allowed
Write Disable
Not Allowed
Allowed
Protect Sector
Not Allowed
Not Allowed
Unprotect Sector
Not Allowed
Not Allowed
Global Protect/Unprotect
Not Allowed
Not Allowed
Allowed
Allowed
Sector Lockdown
Not Allowed
Not Allowed
Freeze Sector Lockdown State
Not Allowed
Not Allowed
Allowed
Allowed
Not Allowed
Not Allowed
Allowed
Allowed
Allowed
Allowed
Not Allowed
Not Allowed
Reset
Allowed
Allowed
Read Manufacturer and Device ID
Allowed
Allowed
Deep Power-Down
Not Allowed
Not Allowed
Resume from Deep Power-Down
Not Allowed
Not Allowed
Command
Read Commands
Read Array (All Opcodes)
Program and Erase Commands
Protection Commands
Read Sector Protection Registers
Security Commands
Read Sector Lockdown Registers
Program OTP Security Register
Read OTP Security Register
Status Register Commands
Read Status Register
Write Status Register (All Opcodes)
Miscellaneous Commands
19
3680F–DFLASH–4/10
Figure 7-7.
Program/Erase Suspend
CS
0
1
2
3
4
5
6
7
SCK
OP C ODE
SI
1
0
1
1
0
0
0
0
MS B
SO
7.6.
HIG H-IMP E DANC E
Program/Erase Resume
The Program/Erase Resume command allows a suspended program or erase operation to be resumed and
continue programming a Flash page or erasing a Flash memory block where it left off. As with the Program/Erase
Suspend command, the Write Enable command does not need to be issued prior to the Program/Erase Resume
command being issued. Therefore, the Program/Erase Resume command operates independently of the state of
the WEL bit in the Status Register.
To perform a Program/Erase Resume, the CS pin must first be asserted and the opcode of D0h must be clocked
into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode
will be ignored. When the CS pin is deasserted, the program or erase operation currently suspended will be
resumed within a time of tRES. The PS bit or the ES bit in the Status Register will then be reset back to the logical
“0” state to indicate that the program or erase operation is no longer suspended. In addition, the RDY/BSY bit in
the Status Register will indicate that the device is busy performing a program or erase operation. The complete
opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on
an even byte boundary (multiples of eight bits); otherwise, no resume operation will be performed.
During a simultaneous Erase Suspend/Program Suspend condition, issuing the Program/Erase Resume
command will result in the program operation resuming first. After the program operation has been completed, the
Program/Erase Resume command must be issued again in order for the erase operation to be resumed.
While the device is busy resuming a program or erase operation, any attempts at issuing the Program/Erase
Suspend command will be ignored. Therefore, if a resumed program or erase operation needs to be subsequently
suspended again, the system must either wait the entire tRES time before issuing the Program/Erase Suspend
command, or it must check the status of the RDY/BSY bit or the appropriate PS or ES bit in the Status Register to
determine if the previously suspended program or erase operation has resumed.
20
Atmel AT25DF641
3680F–DFLASH–4/10
Atmel AT25DF641
Figure 7-8.
Program/Erase Resume
CS
0
1
2
3
4
5
6
7
SCK
OP C ODE
1
SI
1
0
1
0
0
0
0
MS B
HIG H-IMP E DANC E
SO
8.
Protection Commands and Features
8.1.
Write Enable
The Write Enable command is used to set the Write Enable Latch (WEL) bit in the Status Register to a logical “1”
state. The WEL bit must be set before a Byte/Page Program, erase, Protect Sector, Unprotect Sector, Sector
Lockdown, Freeze Sector Lockdown State, Program OTP Security Register, or Write Status Register command
can be executed. This makes the issuance of these commands a two step process, thereby reducing the chances
of a command being accidentally or erroneously executed. If the WEL bit in the Status Register is not set prior to
the issuance of one of these commands, then the command will not be executed.
To issue the Write Enable command, the CS pin must first be asserted and the opcode of 06h must be clocked
into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode
will be ignored. When the CS pin is deasserted, the WEL bit in the Status Register will be set to a logical “1”. The
complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be
deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and
the state of the WEL bit will not change.
Figure 8-1.
Write Enable
CS
0
1
2
3
4
5
6
7
SCK
OP C ODE
SI
0
0
0
0
0
1
1
0
MS B
SO
HIG H-IMP E DANC E
21
3680F–DFLASH–4/10
8.2.
Write Disable
The Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Register to the logical
"0" state. With the WEL bit reset, all Byte/Page Program, erase, Protect Sector, Unprotect Sector, Sector
Lockdown, Freeze Sector Lockdown State, Program OTP Security Register, and Write Status Register
commands will not be executed. Other conditions can also cause the WEL bit to be reset; for more details, refer to
the WEL bit section of the Status Register description.
To issue the Write Disable command, the CS pin must first be asserted and the opcode of 04h must be clocked
into the device. No address bytes need to be clocked into the device, and any data clocked in after the opcode
will be ignored. When the CS pin is deasserted, the WEL bit in the Status Register will be reset to a logical “0”.
The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be
deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and
the state of the WEL bit will not change.
Figure 8-2.
Write Disable
CS
0
1
2
3
4
5
6
7
SCK
OP C ODE
0
SI
0
0
0
0
1
0
0
MS B
HIG H-IMP E DANC E
SO
8.3.
Protect Sector
Every physical 64-Kbyte sector of the device has a corresponding single-bit Sector Protection Register that is
used to control the software protection of a sector. Upon device power-up, each Sector Protection Register will
default to the logical “1” state indicating that all sectors are protected and cannot be programmed or erased.
Issuing the Protect Sector command to a particular sector address will set the corresponding Sector Protection
Register to the logical “1” state. The following table outlines the two states of the Sector Protection Registers.
Table 8-1.
Value
22
Sector Protection Register Values
Sector Protection Status
0
Sector is unprotected and can be programmed and erased
1
Sector is protected and cannot be programmed or erased
This is the default state
Atmel AT25DF641
3680F–DFLASH–4/10
Atmel AT25DF641
Before the Protect Sector command can be issued, the Write Enable command must have been previously issued
to set the WEL bit in the Status Register to a logical “1”. To issue the Protect Sector command, the CS pin must
first be asserted and the opcode of 36h must be clocked into the device followed by three address bytes
designating any address within the sector to be protected. Any additional data clocked into the device will be
ignored. When the CS pin is deasserted, the Sector Protection Register corresponding to the physical sector
addressed by A23-A0 will be set to the logical “1” state, and the sector itself will then be protected from program
and erase operations. In addition, the WEL bit in the Status Register will be reset back to the logical “0” state.
The complete three address bytes must be clocked into the device before the CS pin is deasserted, and the CS
pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the
operation. When the device aborts the Protect Sector operation, the state of the Sector Protection Register will be
unchanged, and the WEL bit in the Status Register will be reset to a logical “0”.
As a safeguard against accidental or erroneous protecting or unprotecting of sectors, the Sector Protection
Registers can themselves be locked from updates by using the SPRL (Sector Protection Registers Locked) bit of
the Status Register (please refer to the Status Register Commands description for more details). If the Sector
Protection Registers are locked, then any attempts to issue the Protect Sector command will be ignored, and the
device will reset the WEL bit in the Status Register back to a logical “0” and return to the idle state once the CS
pin has been deasserted.
Figure 8-3.
Protect Sector
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
26 27 28 29 30 31
SCK
ADDR E S S B IT S A23-A0
OP C ODE
0
SI
0
1
1
0
MS B
SO
8.4.
1
1
0
A
A
A
A
A
A
A
A
A
A
A
A
MS B
HIG H-IMP E DANC E
Unprotect Sector
Issuing the Unprotect Sector command to a particular sector address will reset the corresponding Sector
Protection Register to the logical “0” state (see Table 8-1 for Sector Protection Register values). Every physical
sector of the device has a corresponding single-bit Sector Protection Register that is used to control the software
protection of a sector.
Before the Unprotect Sector command can be issued, the Write Enable command must have been previously
issued to set the WEL bit in the Status Register to a logical “1”. To issue the Unprotect Sector command, the CS
pin must first be asserted and the opcode of 39h must be clocked into the device. After the opcode has been
clocked in, the three address bytes designating any address within the sector to be unprotected must be clocked
in. Any additional data clocked into the device after the address bytes will be ignored. When the CS pin is
deasserted, the Sector Protection Register corresponding to the sector addressed by A23-A0 will be reset to the
logical “0” state, and the sector itself will be unprotected. In addition, the WEL bit in the Status Register will be
reset back to the logical “0” state.
23
3680F–DFLASH–4/10
The complete three address bytes must be clocked into the device before the
pin is deasserted, and the
CS
CS
pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, the device will abort the
operation, the state of the Sector Protection Register will be unchanged, and the WEL bit in the Status Register
will be reset to a logical “0”.
As a safeguard against accidental or erroneous locking or unlocking of sectors, the Sector Protection Registers
can themselves be locked from updates by using the SPRL (Sector Protection Registers Locked) bit of the Status
Register (please refer to the Status Register description for more details). If the Sector Protection Registers are
locked, then any attempts to issue the Unprotect Sector command will be ignored, and the device will reset the
WEL bit in the Status Register back to a logical “0” and return to the idle state once the CS pin has been
deasserted.
Figure 8-4.
Unprotect Sector
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
26 27 28 29 30 31
SCK
ADDR E S S B IT S A23-A0
OP C ODE
SI
0
0
1
1
1
0
MS B
SO
8.5.
0
1
A
A
A
A
A
A
A
A
A
A
A
A
MS B
HIG H-IMP E DANC E
Global Protect/Unprotect
The Global Protect and Global Unprotect features can work in conjunction with the Protect Sector and Unprotect
Sector functions. For example, a system can globally protect the entire memory array and then use the Unprotect
Sector command to individually unprotect certain sectors and individually re-protect them later by using the
Protect Sector command. Likewise, a system can globally unprotect the entire memory array and then individually
protect certain sectors as needed.
Performing a Global Protect or Global Unprotect is accomplished by writing a certain combination of data to the
Status Register using the Write Status Register Byte 1 command (see “Write Status Register Byte 1” on page 38
for command execution details). The Write Status Register command is also used to modify the SPRL (Sector
Protection Registers Locked) bit to control hardware and software locking.
To perform a Global Protect, the appropriate WP pin and SPRL conditions must be met, and the system must
write a logical “1” to bits five, four, three, and two of the first byte of the Status Register. Conversely, to perform a
Global Unprotect, the same WP and SPRL conditions must be met but the system must write a logical “0” to bits
five, four, three, and two of the first byte of the Status Register. Table 8-1 details the conditions necessary for a
Global Protect or Global Unprotect to be performed.
Sectors that have been erase or program suspended must remain in the unprotected state. If a Global Protect
operation is attempted while a sector is erase or program suspended, the protection operation will abort, the
protection states of all sectors in the Flash memory array will not change, and WEL bit in the Status Register will
be reset back to a logical “0”.
24
Atmel AT25DF641
3680F–DFLASH–4/10
Atmel AT25DF641
Table 8-2.
Valid SPRL and Global Protect/Unprotect Conditions
New Write Status
Register Byte 1
Data
WP
State
0
Current
SPRL
Value
New
SPRL
Value
Bit
76543210
Protection Operation
0x0000xx
0x0001xx
↕
0x1110xx
0x1111xx
Global Unprotect – all Sector Protection Registers reset to 0
No change to current protection.
No change to current protection.
No change to current protection.
Global Protect – all Sector Protection Registers set to 1
0
0
0
0
0
1x0000xx
1x0001xx
↕
1x1110xx
1x1111xx
Global Unprotect – all Sector Protection Registers reset to 0
No change to current protection.
No change to current protection.
No change to current protection.
Global Protect – all Sector Protection Registers set to 1
1
1
1
1
1
0
No change to the current protection level. All sectors currently protected will remain protected
and all sectors currently unprotected will remain unprotected.
0
1
1
1
xxxxxxxx
The Sector Protection Registers are hard-locked and cannot be changed when the WP pin is
LOW and the current state of SPRL is 1. Therefore, a Global Protect/Unprotect will not occur.
In addition, the SPRL bit cannot be changed (the WP pin must be HIGH in order to change
SPRL back to a 0).
0x0000xx
0x0001xx
↕
0x1110xx
0x1111xx
Global Unprotect – all Sector Protection Registers reset to 0
No change to current protection.
No change to current protection.
No change to current protection.
Global Protect – all Sector Protection Registers set to 1
0
0
0
0
0
1x0000xx
1x0001xx
↕
1x1110xx
1x1111xx
Global Unprotect – all Sector Protection Registers reset to 0
No change to current protection.
No change to current protection.
No change to current protection.
Global Protect – all Sector Protection Registers set to 1
1
1
1
1
1
0x0000xx
0x0001xx
↕
0x1110xx
0x1111xx
No change to the current protection level. All sectors currently
protected will remain protected, and all sectors currently
unprotected will remain unprotected.
0
0
0
0
0
0
1
1x0000xx
1x0001xx
↕
1x1110xx
1x1111xx
The Sector Protection Registers are soft-locked and cannot be
changed when the current state of SPRL is 1. Therefore, a Global
Protect/Unprotect will not occur. However, the SPRL bit can be
changed back to a 0 from a 1 since the WP pin is HIGH. To
perform a Global Protect/Unprotect, the Write Status Register
command must be issued again after the SPRL bit has been
changed from a 1 to a 0.
1
1
1
1
1
Essentially, if the SPRL bit of the Status Register is in the logical “0” state (Sector Protection Registers are not
locked), then writing a 00h to the first byte of the Status Register will perform a Global Unprotect without changing
the state of the SPRL bit. Similarly, writing a 7Fh to the first byte of the Status Register will perform a Global
Protect and keep the SPRL bit in the logical “0” state. The SPRL bit can, of course, be changed to a logical “1” by
writing an FFh if software-locking or hardware-locking is desired along with the Global Protect.
25
3680F–DFLASH–4/10
If the desire is to only change the SPRL bit without performing a Global Protect or Global Unprotect, then the
system can simply write a 0Fh to the first byte of the Status Register to change the SPRL bit from a logical “1” to a
logical “0” provided the WP pin is deasserted. Likewise, the system can write an F0h to change the SPRL bit from
a logical “0” to a logical “1” without affecting the current sector protection status (no changes will be made to the
Sector Protection Registers).
When writing to the first byte of the Status Register, bits five, four, three, and two will not actually be modified but
will be decoded by the device for the purposes of the Global Protect and Global Unprotect functions. Only bit
seven, the SPRL bit, will actually be modified. Therefore, when reading the first byte of the Status Register, bits
five, four, three, and two will not reflect the values written to them but will instead indicate the status of the WP pin
and the sector protection status. Please refer to “Status Register Commands” on page 34 and Table 10-1 on page
34 for details on the Status Register format and what values can be read for bits five, four, three, and two.
8.6.
Read Sector Protection Registers
The Sector Protection Registers can be read to determine the current software protection status of each sector.
Reading the Sector Protection Registers, however, will not determine the status of the WP pin.
To read the Sector Protection Register for a particular sector, the CS pin must first be asserted and the opcode of
3Ch must be clocked in. Once the opcode has been clocked in, three address bytes designating any address
within the sector must be clocked in. After the last address byte has been clocked in, the device will begin
outputting data on the SO pin during every subsequent clock cycle. The data being output will be a repeating byte
of either FFh or 00h to denote the value of the appropriate Sector Protection Register.
At clock frequencies above fCLK, the first byte of data output will not be valid. Therefore, if operating at clock
frequencies above fCLK, at least two bytes of data must be clocked out from the device in order to determine the
correct status of the appropriate Sector Protection Register.
Table 8-3.
Output Data
Read Sector Protection Register - Output Data
Sector Protection Register Value
00h
Sector Protection Register value is 0 (sector is unprotected)
FFh
Sector Protection Register value is 1 (sector is protected)
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS
pin can be deasserted at any time and does not require that a full byte of data be read.
In addition to reading the individual Sector Protection Registers, the Software Protection Status (SWP) bits in the
Status Register can be read to determine if all, some, or none of the sectors are software protected (refer to
“Read Status Register” on page 34 for more details).
26
Atmel AT25DF641
3680F–DFLASH–4/10
Atmel AT25DF641
Figure 8-5.
Read Sector Protection Register
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 3 6 37 38 39 40
SCK
OP C ODE
0
SI
0
1
1
1
MS B
ADDR E S S B IT S A23-A0
1
0
0
A
A
A
A
A
A
A
A
A
MS B
DAT A B Y T E
HIG H-IMP E DANC E
SO
D
D
D
D
D
D
D
MS B
8.7.
D
D
D
MS B
Protected States and the Write Protect (WP ) Pin
The WP pin is not linked to the memory array itself and has no direct effect on the protection status or lockdown
status of the memory array. Instead, the WP pin, in conjunction with the SPRL (Sector Protection Registers
Locked) bit in the Status Register, is used to control the hardware locking mechanism of the device. For hardware
locking to be active, two conditions must be met-the WP pin must be asserted and the SPRL bit must be in the
logical “1” state.
When hardware locking is active, the Sector Protection Registers are locked and the SPRL bit itself is also locked.
Therefore, sectors that are protected will be locked in the protected state, and sectors that are unprotected will be
locked in the unprotected state. These states cannot be changed as long as hardware locking is active, so the
Protect Sector, Unprotect Sector, and Write Status Register commands will be ignored. In order to modify the
protection status of a sector, the WP pin must first be deasserted, and the SPRL bit in the Status Register must be
reset back to the logical “0” state using the Write Status Register command. When resetting the SPRL bit back to
a logical “0”, it is not possible to perform a Global Protect or Global Unprotect at the same time since the Sector
Protection Registers remain soft-locked until after the Write Status Register command has been executed.
If the WP pin is permanently connected to GND, then once the SPRL bit is set to a logical “1”, the only way to
reset the bit back to the logical “0” state is to power-cycle the device. This allows a system to power-up with all
sectors software protected but not hardware locked. Therefore, sectors can be unprotected and protected as
needed and then hardware locked at a later time by simply setting the SPRL bit in the Status Register.
When the WP pin is deasserted, or if the WP pin is permanently connected to VCC, the SPRL bit in the Status
Register can still be set to a logical “1” to lock the Sector Protection Registers. This provides a software locking
ability to prevent erroneous Protect Sector or Unprotect Sector commands from being processed. When changing
the SPRL bit to a logical “1” from a logical “0”, it is also possible to perform a Global Protect or Global Unprotect at
the same time by writing the appropriate values into bits five, four, three, and two of the first byte of the Status
Register.
Table 8-1 and Table 8-2 detail the various protection and locking states of the device.
Table 8-4.
Sector Protection Register States
WP
Sector Protection Register
n(1)
Sector
n(1)
0
Unprotected
1
Protected
X
(Don't Care)
Note:
1. “n” represents a sector number.
27
3680F–DFLASH–4/10
Table 8-5.
Hardware and Software Locking
WP
SPRL
0
0
0
1
1
0
1
1
Locking
Hardware
Locked
Software
Locked
SPRL Change Allowed
Sector Protection Registers
Can be modified from 0 to 1
Unlocked and modifiable using the Protect and Unprotect
Sector commands. Global Protect and Unprotect can also be
performed.
Locked
Locked in current state. Protect and Unprotect Sector
commands will be ignored. Global Protect and Unprotect
cannot be performed.
Can be modified from 0 to 1
Unlocked and modifiable using the Protect and Unprotect
Sector commands. Global Protect and Unprotect can also be
performed.
Can be modified from 1 to 0
Locked in current state. Protect and Unprotect Sector
commands will be ignored. Global Protect and Unprotect
cannot be performed.
9.
Security Commands
9.1.
Sector Lockdown
Certain applications require that portions of the Flash memory array be permanently protected against malicious
attempts at altering program code, data modules, security information, or encryption/decryption algorithms, keys,
and routines. To address these applications, the device incorporates a sector lockdown mechanism that allows
any combination of individual 64-Kbyte sectors to be permanently locked so that they become read only. Once a
sector is locked down, it can never be erased or programmed again, and it can never be unlocked from the locked
down state.
Each 64-Kbyte physical sector has a corresponding single-bit Sector Lockdown Register that is used to control
the lockdown status of that sector. These registers are nonvolatile and will retain their state even after a device
power-cycle or reset operation. The following table outlines the two states of the Sector Lockdown Registers.
Table 9-1.
Value
Sector Lockdown Register Values
Sector Lockdown Status
0
Sector is not locked down and can be programmed and erased. This is the default state.
1
Sector is permanently locked down and can never be programmed or erased again.
Issuing the Sector Lockdown command to a particular sector address will set the corresponding Sector Lockdown
Register to the logical “1” state. Each Sector Lockdown Register can only be set once; therefore, once set to the
logical “1” state, a Sector Lockdown Register cannot be reset back to the logical “0” state.
28
Atmel AT25DF641
3680F–DFLASH–4/10
Atmel AT25DF641
Before the Sector Lockdown command can be issued, the Write Enable command must have been previously
issued to set the WEL bit in the Status Register to a logical “1”. In addition, the Sector Lockdown Enabled (SLE)
bit in the Status Register must have also been previously set to the logical “1” state by using the Write Status
Register Byte 2 command (see “Write Status Register Byte 2” on page 39). To issue the Sector Lockdown
command, the CS pin must first be asserted and the opcode of 33h must be clocked into the device followed by
three address bytes designating any address within the 64-Kbyte sector to be locked down. After the three
address bytes have been clocked in, a confirmation byte of D0h must also be clocked in immediately following the
three address bytes. Any additional data clocked into the device after the first byte of data will be ignored. When
the CS pin is deasserted, the Sector Lockdown Register corresponding to the sector addressed by A23-A0 will be
set to the logical “1” state, and the sector itself will then be permanently locked down from program and erase
operations within a time of tLOCK. In addition, the WEL bit in the Status Register will be reset back to the logical “0”
state.
The complete three address bytes and the correct confirmation byte value of D0h must be clocked into the device
before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight
bits); otherwise, the device will abort the operation. When the device aborts the Sector Lockdown operation, the
state of the corresponding Sector Lockdown Register as well as the SLE bit in the Status Register will be
unchanged; however, the WEL bit in the Status Register will be reset to a logical “0”.
As a safeguard against accidental or erroneous locking down of sectors, the Sector Lockdown command can be
enabled and disabled as needed by using the SLE bit in the Status Register. In addition, the current sector
lockdown state can be frozen so that no further modifications to the Sector Lockdown Registers can be made
(see “Freeze Sector Lockdown State”). If the Sector Lockdown command is disabled or if the sector lockdown
state is frozen, then any attempts to issue the Sector Lockdown command will be ignored, and the device will
reset the WEL bit in the Status Register back to a logical “0” and return to the idle state once the CS pin has been
deasserted.
Figure 9-1.
Sector Lockdown
CS
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38 39
SCK
OP C ODE
SI
0
0
1
1
0
MS B
SO
ADDR E S S B IT S A23-A0
0
1
1
A
MS B
A
A
A
A
A
C ONF IR MAT ION B Y T E IN
1
1
0
1
0
0
0
0
MS B
HIG H-IMP E DANC E
29
3680F–DFLASH–4/10
9.2.
Freeze Sector Lockdown State
The current sector lockdown state can be permanently frozen so that no further modifications to the Sector
Lockdown Registers can be made; therefore, the Sector Lockdown command will be permanently disabled, and
no additional sectors can be locked down aside from those already locked down. Any attempts to issue the Sector
Lockdown command after the sector lockdown state has been frozen will be ignored.
Before the Freeze Sector Lockdown State command can be issued, the Write Enable command must have been
previously issued to set the WEL bit in the Status Register to a logical “1”. In addition, the Sector Lockdown
Enabled (SLE) bit in the Status Register must have also been previously set to the logical “1” state. To issue the
Freeze Sector Lockdown State command, the CS pin must first be asserted and the opcode of 34h must be
clocked into the device followed by three command specific address bytes of 55AA40h. After the three address
bytes have been clocked in, a confirmation byte of D0h must be clocked in immediately following the three
address bytes. Any additional data clocked into the device will be ignored. When the CS pin is deasserted, the
current sector lockdown state will be permanently frozen within a time of tLOCK. In addition, the WEL bit in the
Status Register will be reset back to the logical “0” state, and the SLE bit will be permanently reset to a logical “0”
to indicate that the Sector Lockdown command is permanently disabled.
The complete and correct three address bytes and the confirmation byte must be clocked into the device before
the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits);
otherwise, the device will abort the operation. When the device aborts the Freeze Sector Lockdown State
operation, the WEL bit in the Status Register will be reset to a logical “0”; however, the state of the SLE bit will be
unchanged.
Figure 9-2.
Freeze Sector Lockdown State
CS
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38 39
SCK
OP C ODE
SI
0
0
1
1
0
ADDR E S S B IT S A23-A0
1
MS B
SO
30
0
0
0
MS B
1
0
0
0
0
C ONF IR MAT ION B Y T E IN
1
1
0
1
0
0
0
0
MS B
HIG H-IMP E DANC E
Atmel AT25DF641
3680F–DFLASH–4/10
Atmel AT25DF641
9.3.
Read Sector Lockdown Registers
The Sector Lockdown Registers can be read to determine the current lockdown status of each physical 64-Kbyte
sector. To read the Sector Lockdown Register for a particular 64-Kbyte sector, the CS pin must first be asserted
and the opcode of 35h must be clocked in. Once the opcode has been clocked in, three address bytes
designating any address within the 64-Kbyte sector must be clocked in. After the address bytes have been
clocked in, data will be output on the SO pin during every subsequent clock cycle. The data being output will be a
repeating byte of either FFh or 00h to denote the value of the appropriate Sector Lockdown Register.
At clock frequencies above fCLK, the first byte of data output will not be valid. Therefore, if operating at clock
frequencies above fCLK, at least two bytes of data must be clocked out from the device in order to determine the
correct status of the appropriate Sector Lockdown Register.
Table 9-3.
Output Data
Read Sector Lockdown Register – Output Data
Sector Lockdown Register Value
00h
Sector Lockdown Register value is 0 (sector is not locked down)
FFh
Sector Lockdown Register value is 1 (sector is permanently locked down)
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS
pin can be deasserted at any time and does not require that a full byte of data be read.
Figure 9-3.
Read Sector Lockdown Register
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
SCK
OPC ODE
SI
0
0
1
1
0
ADDR E S S BITS A23-A0
1
0
1
MS B
A
MS B
A
A
A
A
A
A
DON'T C AR E
A
A
X
X
X
X
X
X
X
X
MS B
DATA BYTE
SO
HIGH-IMPE DANC E
D
MS B
9.4.
D
D
D
D
D
D
D
D
D
MS B
Program OTP Security Register
The device contains a specialized OTP (One-Time Programmable) Security Register that can be used for
purposes such as unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key
storage, etc. The OTP Security Register is independent of the main Flash memory array and is comprised of a
total of 128-bytes of memory divided into two portions. The first 64-bytes (byte locations 0 through 63) of the OTP
Security Register are allocated as a one-time user-programmable space. Once these 64-bytes have been
programmed, they cannot be erased or reprogrammed. The remaining 64-bytes of the OTP Security Register
(byte locations 64 through 127) are factory programmed by Atmel and will contain a unique value for each device.
The factory programmed data is fixed and cannot be changed.
31
3680F–DFLASH–4/10
Table 9-4.
OTP Security Register
Security Register
Byte Number
0
1
...
62
One-Time User Programmable
63
64
65
...
126
127
Factory Programmed by Atmel
The user-programmable portion of the OTP Security Register does not need to be erased before it is
programmed. In addition, the Program OTP Security Register command operates on the entire 64-byte userprogrammable portion of the OTP Security Register at one time. Once the user-programmable space has been
programmed with any number of bytes, the user-programmable space cannot be programmed again; therefore, it
is not possible to only program the first two bytes of the register and then program the remaining 62-bytes at a
later time.
Before the Program OTP Security Register command can be issued, the Write Enable command must have been
previously issued to set the WEL bit in the Status Register to a logical “1”. To program the OTP Security Register,
the CS pin must first be asserted and an opcode of 9Bh must be clocked into the device followed by the three
address bytes denoting the first byte location of the OTP Security Register to begin programming at. Since the
size of the user-programmable portion of the OTP Security Register is 64-bytes, the upper order address bits do
not need to be decoded by the device. Therefore, address bits A23-A6 will be ignored by the device and their
values can be either a logical “1” or “0”. After the address bytes have been clocked in, data can then be clocked
into the device and will be stored in the internal buffer.
If the starting memory address denoted by A23-A0 does not start at the beginning of the OTP Security Register
memory space (A5-A0 are not all 0), then special circumstances regarding which OTP Security Register locations
to be programmed will apply. In this situation, any data that is sent to the device that goes beyond the end of the
64-byte user-programmable space will wrap around back to the beginning of the OTP Security Register. For
example, if the starting address denoted by A23-A0 is 00003Eh, and three bytes of data are sent to the device,
then the first two bytes of data will be programmed at OTP Security Register addresses 00003Eh and 00003Fh
while the last byte of data will be programmed at address 000000h. The remaining bytes in the OTP Security
Register (addresses 000001h through 00003Dh) will not be programmed and will remain in the erased state
(FFh). In addition, if more than 64-bytes of data are sent to the device, then only the last 64-bytes sent will be
latched into the internal buffer.
When the CS pin is deasserted, the device will take the data stored in the internal buffer and program it into the
appropriate OTP Security Register locations based on the starting address specified by A23-A0 and the number
of data bytes sent to the device. If less than 64-bytes of data were sent to the device, then the remaining bytes
within the OTP Security Register will not be programmed and will remain in the erased state (FFh). The
programming of the data bytes is internally self-timed and should take place in a time of tOTPP. It is not possible to
suspend the programming of the OTP Security Register.
The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin
is deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the
device will abort the operation and the user-programmable portion of the OTP Security Register will not be
programmed. The WEL bit in the Status Register will be reset back to the logical “0” state if the OTP Security
Register program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent,
the CS pin being deasserted on uneven byte boundaries, or because the user-programmable portion of the OTP
Security Register was previously programmed.
While the device is programming the OTP Security Register, the Status Register can be read and will indicate that
the device is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting
the tOTPP time to determine if the data bytes have finished programming. At some point before the OTP Security
Register programming completes, the WEL bit in the Status Register will be reset back to the logical “0” state.
32
Atmel AT25DF641
3680F–DFLASH–4/10
Atmel AT25DF641
If the device is powered-down during the OTP Security Register program cycle, then the contents of the 64-byte
user programmable portion of the OTP Security Register cannot be guaranteed and cannot be programmed
again.
The Program OTP Security Register command utilizes the internal 256-buffer for processing. Therefore, the
contents of the buffer will be altered from its previous state when this command is issued.
Figure 9-4.
Program OTP Security Register
CS
0
1
2
3
4
5
6
7
8
29 30 31 32 33 34 35 36 37 38 39
9
SCK
1
SI
0
0
1
1
0
1
SO
9.5.
A
1
MS B
A
A
A
A
A
DAT A IN B Y T E n
DAT A IN B Y T E 1
ADDR E S S B IT S A23-A0
OP C ODE
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
MS B
MS B
MS B
HIG H-IMP E DANC E
Read OTP Security Register
The OTP Security Register can be sequentially read in a similar fashion to the Read Array operation up to the
maximum clock frequency specified by fMAX. To read the OTP Security Register, the CS pin must first be asserted
and the opcode of 77h must be clocked into the device. After the opcode has been clocked in, the three address
bytes must be clocked in to specify the starting address location of the first byte to read within the OTP Security
Register. Following the three address bytes, two dummy bytes must be clocked into the device before data can
be output.
After the three address bytes and the dummy bytes have been clocked in, additional clock cycles will result in
OTP Security Register data being output on the SO pin. When the last byte (00007Fh) of the OTP Security
Register has been read, the device will continue reading back at the beginning of the register (000000h). No
delays will be incurred when wrapping around from the end of the register to the beginning of the register.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS
pin can be deasserted at any time and does not require that a full byte of data be read.
Figure 9-5.
Read OTP Security Register
CS
0
1
2
3
4
5
6
7
8
9
10 11 12
29 30 31 32 33 34 35 36
SCK
ADDR E S S B IT S A23-A0
O P C O DE
SI
0
1
1
1
0
MS B
1
1
1
A
MS B
A
A
A
A
A
A
DO N'T C AR E
A
A
X
X
X
X
X
X
X
X
X
MS B
DAT A B Y T E 1
SO
H IG H -IMP E DANC E
D
MS B
D
D
D
D
D
D
D
D
D
MS B
33
3680F–DFLASH–4/10
10.
Status Register Commands
10.1. Read Status Register
The two-byte Status Register can be read to determine the device’s ready/busy status, as well as the status of
many other functions such as Hardware Locking and Software Protection. The Status Register can be read at any
time, including during an internally self-timed program or erase operation.
To read the Status Register, the CS pin must first be asserted and the opcode of 05h must be clocked into the
device. After the opcode has been clocked in, the device will begin outputting Status Register data on the SO pin
during every subsequent clock cycle. After the second byte of the Status Register has been clocked out, the
sequence will repeat itself starting again with the first byte of the Status Register as long as the CS pin remains
asserted and the clock pin is being pulsed. The data in the Status Register is constantly being updated, so each
repeating sequence will output new data. The RDY/BSY status is available for both bytes of the Status Register
and is updated for each byte.
At clock frequencies above fCLK, the first two bytes of data output from the Status Register will not be valid.
Therefore, if operating at clock frequencies above fCLK, at least four bytes of data must be clocked out from the
device in order to read the correct values of both bytes of the Status Register.
Deasserting the CS pin will terminate the Read Status Register operation and put the SO pin into a
high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be
read.
Table 10-1.
Status Register Format – Byte 1
Bit(1)
Name
Type(2)
Description
R/W
0
1
Sector Protection Registers are unlocked (default)
Sector Protection Registers are locked
Reserved for future use
R
0
Reserved for future use
EPE
Erase/Program Error
R
0
1
Erase or program operation was successful
Erase or program error detected
WPP
R
0
Write Protect (WP ) Pin Status
WP is asserted
1
0
WP is deasserted
All sectors are software unprotected (all Sector
Protection Registers are 0)
Some sectors are software protected
Read individual Sector Protection Registers to
determine which sectors are protected
Reserved for future use
All sectors are software protected (all Sector Protection
Registers are 1 – default)
Device is not write enabled (default)
1
Device is write enabled
0
Device is ready
1
Device is busy with an internal operation
7
SPRL
Sector Protection Registers
Locked
6
RES
5
4
00
3:2
SWP
Software Protection Status
R
01
10
11
1
WEL
0
RDY/BSY
Write Enable Latch Status
R
Ready/Busy Status
R
Notes: 1. Only bit 7 of Status Register Byte 1 will be modified when using the Write Status Register
Byte 1 command
2. R/W = Readable and writeable
R = Readable only
34
Atmel AT25DF641
3680F–DFLASH–4/10
Atmel AT25DF641
Table 10-2.
Status Register Format – Byte 2
Bit(1)
Name
Type(2)
Description
7
RES
Reserved for future use
R
0
Reserved for future use.
6
RES
Reserved for future use
R
0
Reserved for future use.
5
RES
Reserved for future use
R
0
Reserved for future use.
0
Reset command is disabled (default).
4
RSTE
1
Reset command is enabled.
0
Sector Lockdown and Freeze Sector Lockdown
State commands are disabled (default).
1
Sector Lockdown and Freeze Sector Lockdown
State commands are enabled.
0
No sectors are program suspended (default).
1
A sector is program suspended.
0
No sectors are erase suspended (default).
1
A sector is erase suspended.
0
Device is ready.
1
Device is busy with an internal operation.
3
SLE
2
PS
1
0
ES
Reset Enabled
Sector Lockdown Enabled
Program Suspend Status
Erase Suspend Status
RDY/BSY Ready/Busy Status
R/W
R/W
R
R
R
Notes: 1. Only bits 4 and 3 of Status Register Byte 2 will be modified when using the Write Status Register
Byte 2 command
2. R/W = Readable and writeable
R = Readable only
10.1.1. SPRL Bit
The SPRL bit is used to control whether the Sector Protection Registers can be modified or not. When the SPRL
bit is in the logical “1” state, all Sector Protection Registers are locked and cannot be modified with the Protect
Sector and Unprotect Sector commands (the device will ignore these commands). In addition, the Global Protect
and Global Unprotect features cannot be performed. Any sectors that are presently protected will remain
protected, and any sectors that are presently unprotected will remain unprotected.
When the SPRL bit is in the logical “0” state, all Sector Protection Registers are unlocked and can be modified
(the Protect Sector and Unprotect Sector commands, as well as the Global Protect and Global Unprotect features,
will be processed as normal). The SPRL bit defaults to the logical “0” state after device power-up. The Reset
command has no effect on the SPRL bit.
The SPRL bit can be modified freely whenever the WP pin is deasserted. However, if the WP pin is asserted, then
the SPRL bit may only be changed from a logical “0” (Sector Protection Registers are unlocked) to a logical “1”
(Sector Protection Registers are locked). In order to reset the SPRL bit back to a logical “0” using the Write Status
Register Byte 1 command, the WP pin will have to first be deasserted.
The SPRL bit is the only bit of Status Register Byte 1 that can be user modified via the Write Status Register Byte
1 command.
35
3680F–DFLASH–4/10
10.1.2. EPE Bit
The EPE bit indicates whether the last erase or program operation completed successfully or not. If at least one
byte during the erase or program operation did not erase or program properly, then the EPE bit will be set to the
logical “1” state. The EPE bit will not be set if an erase or program operation aborts for any reason such as an
attempt to erase or program a protected region or a locked down sector, an attempt to erase or program a
suspended sector, or if the WEL bit is not set prior to an erase or program operation. The EPE bit will be updated
after every erase and program operation.
10.1.3. WPP Bit
The WPP bit can be read to determine if the WP pin has been asserted or not.
10.1.4. SWP Bits
The SWP bits provide feedback on the software protection status for the device. There are three possible
combinations of the SWP bits that indicate whether none, some, or all of the sectors have been protected using
the Protect Sector command or the Global Protect feature. If the SWP bits indicate that some of the sectors have
been protected, then the individual Sector Protection Registers can be read with the Read Sector Protection
Registers command to determine which sectors are in fact protected.
10.1.5. WEL Bit
The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is in the logical “0”
state, the device will not accept any Byte/Page Program, erase, Protect Sector, Unprotect Sector, Sector
Lockdown, Freeze Sector Lockdown State, Program OTP Security Register, or Write Status Register commands.
The WEL bit defaults to the logical “0” state after a device power-up or reset operation. In addition, the WEL bit
will be reset to the logical “0” state automatically under the following conditions:
• Write Disable operation completes successfully
• Write Status Register operation completes successfully or aborts
• Protect Sector operation completes successfully or aborts
• Unprotect Sector operation completes successfully or aborts
• Sector Lockdown operation completes successfully or aborts
• Freeze Sector Lockdown State operation completes successfully or aborts
• Program OTP Security Register operation completes successfully or aborts
• Byte/Page Program operation completes successfully or aborts
• Block Erase operation completes successfully or aborts
• Chip Erase operation completes successfully or aborts
• Hold condition aborts
If the WEL bit is in the logical “1” state, it will not be reset to a logical “0” if an operation aborts due to an
incomplete or unrecognized opcode being clocked into the device before the CS pin is deasserted. In order for the
WEL bit to be reset when an operation aborts prematurely, the entire opcode for a Byte/Page Program, erase,
Protect Sector, Unprotect Sector, Sector Lockdown, Freeze Sector Lockdown State, Program OTP Security
Register, or Write Status Register command must have been clocked into the device.
36
Atmel AT25DF641
3680F–DFLASH–4/10
Atmel AT25DF641
10.1.6. RSTE Bit
The RSTE bit is used to enable or disable the Reset command. When the RSTE bit is in the logical “0” state (the
default state after power-up), the Reset command is disabled and any attempts to reset the device using the
Reset command will be ignored. When the RSTE bit is in the logical “1” state, the Reset command is enabled.
The RSTE bit will retain its state as long as power is applied to the device. Once set to the logical “1” state, the
RSTE bit will remain in that state until it is modified using the Write Status Register Byte 2 command or until the
device has been power cycled. The Reset command itself will not change the state of the RSTE bit.
10.1.7. SLE Bit
The SLE bit is used to enable and disable the Sector Lockdown and Freeze Sector Lockdown State commands.
When the SLE bit is in the logical “0” state (the default state after power-up), the Sector Lockdown and Freeze
Sector Lockdown commands are disabled. If the Sector Lockdown and Freeze Sector Lockdown commands are
disabled, then any attempts to issue the commands will be ignored. This provides a safeguard for these
commands against accidental or erroneous execution. When the SLE bit is in the logical “1” state, the Sector
Lockdown and Freeze Sector Lockdown State commands are enabled.
Unlike the WEL bit, the SLE bit does not automatically reset after certain device operations. Therefore, once set,
the SLE bit will remain in the logical “1” state until it is modified using the Write Status Register Byte 2 command
or until the device has been power cycled. The Reset command has no effect on the SLE bit.
If the Freeze Sector Lockdown State command has been issued, then the SLE bit will be permanently reset in the
logical “0” state to indicate that the Sector Lockdown command has been disabled.
10.1.8. PS Bit
The PS bit indicates whether or not a sector is in the Program Suspend state.
10.1.9. ES Bit
The ES bit indicates whether or not a sector is in the Erase Suspend state.
10.1.10. RDY/BSY Bit
The RDY/BSY bit is used to determine whether or not an internal operation, such as a program or erase, is in
progress. To poll the RDY/BSY bit to detect the completion of a program or erase cycle, new Status Register data
must be continually clocked out of the device until the state of the RDY/BSY bit changes from a logical “1” to a
logical “0”.
Figure 10-1. Read Status Register
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SCK
OPCODE
SI
0
0
0
0
0
1
0
1
MS B
SO
HIG H-IMP E DANC E
S TATUS R E GIS TE R
BYTE 2
S TATUS R E GIS TE R
BYTE 1
D
MS B
D
D
D
D
D
D
D
D
MS B
D
D
D
D
D
D
S TATUS R E GIS TE R
BYTE 1
D
D
D
D
D
D
D
D
D
MS B
37
3680F–DFLASH–4/10
10.2. Write Status Register Byte 1
The Write Status Register Byte 1 command is used to modify the SPRL bit of the Status Register and/or to
perform a Global Protect or Global Unprotect operation. Before the Write Status Register Byte 1 command can be
issued, the Write Enable command must have been previously issued to set the WEL bit in the Status Register to
a logical “1”.
To issue the Write Status Register Byte 1 command, the CS pin must first be asserted and the opcode of 01h
must be clocked into the device followed by one byte of data. The one byte of data consists of the SPRL bit value,
a don’t care bit, four data bits to denote whether a Global Protect or Unprotect should be performed, and two
additional don’t care bits (see Table 10-1). Any additional data bytes that are sent to the device will be ignored.
When the CS pin is deasserted, the SPRL bit in the Status Register will be modified, and the WEL bit in the Status
Register will be reset back to a logical “0”. The values of bits five, four, three, and two and the state of the SPRL
bit before the Write Status Register Byte 1 command was executed (the prior state of the SPRL bit) will determine
whether or not a Global Protect or Global Unprotect will be performed. Please refer to “Global Protect/Unprotect”
on page 24 for more details.
The complete one byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin
must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the
operation, the state of the SPRL bit will not change, no potential Global Protect or Unprotect will be performed,
and the WEL bit in the Status Register will be reset back to the logical “0” state.
If the WP pin is asserted, then the SPRL bit can only be set to a logical “1”. If an attempt is made to reset the
SPRL bit to a logical “0” while the WP pin is asserted, then the Write Status Register Byte 1 command will be
ignored, and the WEL bit in the Status Register will be reset back to the logical “0” state. In order to reset the
SPRL bit to a logical “0”, the WP pin must be deasserted.
Table 10-3.
Write Status Register Byte 1 Format
Bit 7
Bit 6
SPRL
X
Bit 5
Bit 4
Bit 3
Bit 2
Global Protect/Unprotect
Bit 1
Bit 0
X
X
Figure 10-2. Write Status Register Byte 1
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
S TATUS R E GIS TE R IN
BYTE 1
OPCODE
SI
0
0
0
0
0
0
MS B
SO
38
0
1
D
X
D
D
D
D
X
X
MS B
HIG H-IMP E DANC E
Atmel AT25DF641
3680F–DFLASH–4/10
Atmel AT25DF641
10.3. Write Status Register Byte 2
The Write Status Register Byte 2 command is used to modify the RSTE and SLE bits of the Status Register.
Using the Write Status Register Byte 2 command is the only way to modify the RSTE and SLE bits in the Status
Register during normal device operation, and the SLE bit can only be modified if the sector lockdown state has
not been frozen. Before the Write Status Register Byte 2 command can be issued, the Write Enable command
must have been previously issued to set the WEL bit in the Status Register to a logical “1”.
To issue the Write Status Register Byte 2 command, the CS pin must first be asserted and the opcode of 31h
must be clocked into the device followed by one byte of data. The one byte of data consists of three don’t care
bits, the RSTE bit value, the SLE bit value, and three additional don’t care bits (see Table 10-1). Any additional
data bytes that are sent to the device will be ignored. When the CS pin is deasserted, the RSTE and SLE bits in
the Status Register will be modified, and the WEL bit in the Status Register will be reset back to a logical “0”. The
SLE bit will only be modified if the Freeze Sector Lockdown State command has not been previously issued.
The complete one byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin
must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the
operation, the state of the RSTE and SLE bits will not change, and the WEL bit in the Status Register will be reset
back to the logical “0” state.
Table 10-4.
Write Status Register Byte 2 Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
RSTE
SLE
X
X
X
Figure 10-3. Write Status Register Byte 2
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
S TATUS R E GIS TE R IN
BYTE 2
OPCODE
SI
0
0
1
1
0
MS B
SO
0
0
1
X
X
X
D
D
X
X
X
MS B
HIG H-IMP E DANC E
39
3680F–DFLASH–4/10
11.
Other Commands and Functions
11.1. Reset
In some applications, it may be necessary to prematurely terminate a program or erase cycle early rather than
wait the hundreds of microseconds or milliseconds necessary for the program or erase operation to complete
normally. The Reset command allows a program or erase operation in progress to be ended abruptly and returns
the device to an idle state. Since the need to reset the device is immediate, the Write Enable command does not
need to be issued prior to the Reset command being issued. Therefore, the Reset command operates
independently of the state of the WEL bit in the Status Register.
The Reset command can only be executed if the command has been enabled by setting the Reset Enabled
(RSTE) bit in the Status Register to a logical “1”. If the Reset command has not been enabled (the RSTE bit is in
the logical “0” state), then any attempts at executing the Reset command will be ignored.
To perform a Reset, the CS pin must first be asserted and the opcode of F0h must be clocked into the device. No
address bytes need to be clocked in, but a confirmation byte of D0h must be clocked into the device immediately
after the opcode. Any additional data clocked into the device after the confirmation byte will be ignored. When the
CS pin is deasserted, the program or erase operation currently in progress will be terminated within a time of tRST.
Since the program or erase operation may not complete before the device is reset, the contents of the page being
programmed or the block being erased cannot be guaranteed to be valid.
The Reset command has no effect on the states of the Sector Protection Registers, the Sector Lockdown
Registers, or the SPRL, RSTE, and SLE bits in the Status Register. The WEL, PS, and ES bits, however, will be
reset back to their default states. If a Reset operation is performed while a sector is erase suspended, the
suspend operation will abort, and the contents of the block being erased in the suspended sector will be left in an
undefined state. If a Reset is performed while a sector is program suspended, the suspend operation will abort,
and the contents of the page that was being programmed and subsequently suspended will be undefined. The
remaining pages in the 64-Kbyte sector will retain their previous contents.
The complete opcode and confirmation byte must be clocked into the device before the CS pin is deasserted, and
the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no Reset operation
will be performed.
Figure 11-1. Reset
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
OPCODE
SI
1
1
1
1
0
CONFIR MATION BYTE IN
0
MS B
SO
40
0
0
1
1
0
1
0
0
0
0
MS B
HIG H-IMP E DANC E
Atmel AT25DF641
3680F–DFLASH–4/10
Atmel AT25DF641
11.2. Read Manufacturer and Device ID
Identification information can be read from the device to enable systems to electronically query and identify the
device while it is in system. The identification method and the command opcode comply with the JEDEC standard
for “Manufacturer and Device ID Read Methodology for SPI Compatible Serial Interface Memory Devices”. The
type of information that can be read from the device includes the JEDEC defined Manufacturer ID, the vendor
specific Device ID, and the vendor specific Extended Device Information.
The Read Manufacturer and Device ID command is limited to a maximum clock frequency of fCLK. Since not all
Flash devices are capable of operating at very high clock frequencies, applications should be designed to read
the identification information from the devices at a reasonably low clock frequency to ensure that all devices to be
used in the application can be identified properly. Once the identification process is complete, the application can
then increase the clock frequency to accommodate specific Flash devices that are capable of operating at the
higher clock frequencies.
To read the identification information, the CS pin must first be asserted and the opcode of 9Fh must be clocked
into the device. After the opcode has been clocked in, the device will begin outputting the identification data on
the SO pin during the subsequent clock cycles. The first byte that will be output will be the Manufacturer ID
followed by two bytes of Device ID information. The fourth byte output will be the Extended Device Information
String Length, which will be 00h indicating that no Extended Device Information follows. After the Extended
Device Information String Length byte is output, the SO pin will go into a high-impedance state; therefore,
additional clock cycles will have no affect on the SO pin and no data will be output. As indicated in the JEDEC
standard, reading the Extended Device Information String Length and any subsequent data is optional.
Deasserting the CS pin will terminate the Manufacturer and Device ID read operation and put the SO pin into a
high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be
read.
Table 11-1.
Byte No.
Manufacturer and Device ID Information
Data Type
Value
1
Manufacturer ID
1Fh
2
Device ID (Part 1)
48h
3
Device ID (Part 2)
00h
4
Extended Device Information String Length
00h
Table 11-2.
Manufacturer and Device ID Details
Data Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
0
0
Hex
Value Details
JEDEC Assigned Code
Manufacturer ID
1Fh JEDEC Code:
0
0
0
1
1
Family Code
1
Density Code
Device ID (Part 1)
0
1
0
0
0
0
Sub Code
1
0
0
0
48h
Family Code:
Density Code:
00h
Sub Code:
000 (Standard series)
Product Version: 00000 (Initial version)
Product Version Code
Device ID (Part 2)
0
0
0
0
0001 1111 (1Fh for Atmel)
010 (AT25DF/26DFxxx series)
01000 (64-Mbit)
41
3680F–DFLASH–4/10
Figure 11-2. Read Manufacturer and Device ID
CS
0
6
7
8
14 15 16
22 23 24
38
30 31 32
SCK
OP C ODE
9F h
SI
SO
Note:
42
HIG H-IMP E DANC E
Each transition
1F h
48h
00h
00h
MANUF AC T UR E R ID
DE V IC E ID
BYTE 1
DE V IC E ID
BYTE 2
E XT E NDE D
DE V IC E
INF OR MAT ION
S T R ING LE NG T H
shown for SI and SO represents one byte (8-bits).
Atmel AT25DF641
3680F–DFLASH–4/10
Atmel AT25DF641
11.3. Deep Power-Down
During normal operation, the device will be placed in the standby mode to consume less power as long as the CS
pin remains deasserted and no internal operation is in progress. The Deep Power-Down command offers the
ability to place the device into an even lower power consumption state called the Deep Power-Down mode.
When the device is in the Deep Power-Down mode, all commands including the Read Status Register command
will be ignored with the exception of the Resume from Deep Power-Down command. Since all commands will be
ignored, the mode can be used as an extra protection mechanism against program and erase operations.
Entering the Deep Power-Down mode is accomplished by simply asserting the CS pin, clocking in the opcode of
B9h, and then deasserting the CS pin. Any additional data clocked into the device after the opcode will be
ignored. When the CS pin is deasserted, the device will enter the Deep Power-Down mode within the maximum
time of tEDPD.
The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin must be deasserted on
an even byte boundary (multiples of eight bits); otherwise, the device will abort the operation and return to the
standby mode once the CS pin is deasserted. In addition, the device will default to the standby mode after a
power-cycle.
The Deep Power-Down command will be ignored if an internally self-timed operation such as a program or erase
cycle is in progress. The Deep Power-Down command must be reissued after the internally self-timed operation
has been completed in order for the device to enter the Deep Power-Down mode.
Figure 11-3. Deep Power-Down
CS
tE DP D
0
1
2
3
4
5
6
7
SCK
OP C ODE
SI
1
0
1
1
1
0
0
1
MS B
SO
HIG H-IMP E DANC E
Active C urrent
ICC
S tandby Mode C urrent
Deep P ower-Down Mode C urrent
43
3680F–DFLASH–4/10
11.4. Resume from Deep Power-Down
In order to exit the Deep Power-Down mode and resume normal device operation, the Resume from Deep PowerDown command must be issued. The Resume from Deep Power-Down command is the only command that the
device will recognized while in the Deep Power-Down mode.
To resume from the Deep Power-Down mode, the CS pin must first be asserted and opcode of ABh must be
clocked into the device. Any additional data clocked into the device after the opcode will be ignored. When the CS
pin is deasserted, the device will exit the Deep Power-Down mode within the maximum time of tRDPD and return to
the standby mode. After the device has returned to the standby mode, normal command operations such as Read
Array can be resumed.
If the complete opcode is not clocked in before the CS pin is deasserted, or if the CS pin is not deasserted on an
even byte boundary (multiples of eight bits), then the device will abort the operation and return to the Deep
Power-Down mode.
Figure 11-4. Resume from Deep Power-Down
CS
tR DP D
0
1
2
3
4
5
6
7
SCK
OP C ODE
SI
1
0
1
0
1
0
1
1
MS B
SO
HIG H-IMP E DANC E
Active C urrent
ICC
Deep P ower-Down Mode C urrent
44
S tandby Mode C urrent
Atmel AT25DF641
3680F–DFLASH–4/10
Atmel AT25DF641
11.5. Hold
The HOLD pin is used to pause the serial communication with the device without having to stop or reset the clock
sequence. The Hold mode, however, does not have an affect on any internally self-timed operations such as a
program or erase cycle. Therefore, if an erase cycle is in progress, asserting the HOLD pin will not pause the
operation, and the erase cycle will continue until it is finished.
The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated simply by asserting
the HOLD pin during the SCK low pulse. If the HOLD pin is asserted during the SCK high pulse, then the Hold
mode won’t be started until the beginning of the next SCK low pulse. The device will remain in the Hold mode as
long as the HOLD pin and CS pin are asserted.
While in the Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin and the SCK pin
will be ignored. The WP pin, however, can still be asserted or deasserted while in the Hold mode.
To end the Hold mode and resume serial communication, the HOLD pin must be deasserted during the SCK low
pulse. If the HOLD pin is deasserted during the SCK high pulse, then the Hold mode won’t end until the beginning
of the next SCK low pulse.
If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will
be aborted, and the device will reset the WEL bit in the Status Register back to the logical “0” state.
Figure 11-5. Hold Mode
CS
SCK
HOLD
Hold
Hold
Hold
45
3680F–DFLASH–4/10
12.
Atmel RapidS Implementation
To implement Atmel® RapidS and operate at clock frequencies higher than what can be achieved in a viable SPI
implementation, a full clock cycle can be used to transmit data back and forth across the serial bus. The Atmel
AT25DF641 is designed to always clock its data out on the falling edge of the SCK signal and clock data in on the
rising edge of SCK.
For full clock cycle operation to be achieved, when the AT25DF641 is clocking data out on the falling edge of
SCK, the host controller should wait until the next falling edge of SCK to latch the data in. Similarly, the host
controller should clock its data out on the rising edge of SCK in order to give the AT25DF641 a full clock cycle to
latch the incoming data in on the next rising edge of SCK.
Implementing RapidS allows a system to run at higher clock frequencies since a full clock cycle is used to
accommodate a device’s clock-to-output time, input setup time, and associated rise/fall times. For example, if the
system clock frequency is 100MHz (10ns cycle time) with a 50% duty cycle, and the host controller has an input
setup time of 2ns, then a standard SPI implementation would require that the slave device be capable of
outputting its data in less than 3ns to meet the 2ns host controller setup time [(10ns x 50%) - 2ns] not accounting
for rise/fall times. In an SPI mode 0 or 3 implementation, the SPI master is designed to clock in data on the next
immediate rising edge of SCK after the SPI slave has clocked its data out on the preceding falling edge. This
essentially makes SPI a half-clock cycle protocol and requires extremely fast clock-to-output times and input
setup times in order to run at high clock frequencies. With a RapidS implementation of this example, however, the
full 10ns cycle time is available which gives the slave device up to 8ns, not accounting for rise/fall times, to clock
its data out. Likewise, with RapidS, the host controller has more time available to output its data to the slave since
the slave device would be clocking that data in a full clock cycle later.
Figure 12-1. RapidS Operation
Slave CS
1
8
2
3
4
5
6
1
8
7
2
3
4
5
6
1
7
SCK
B
A
MOSI
C
tV
MSB
E
D
LSB
H
BYTE A
G
I
F
MISO
MSB
LSB
BYTE B
MOSI = Master Out, Slave In MISO = Master In, Slave Out
The Master is the ASIC/MCU and the Slave is the memory device.
The Master always clocks data out on the rising edge of SCK and always clocks data in on the falling edge of SCK.
The Slave always clocks data out on the falling edge of SCK and always clocks data in on the rising edge of SCK.
A.
B.
C.
D.
E.
F.
G.
H.
I.
46
Master clocks out first bit of BYTE A on the rising edge of SCK
Slave clocks in first bit of BYTE A on the next rising edge of SCK
Master clocks out second bit of BYTE A on the same rising edge of SCK
Last bit of BYTE A is clocked out from the Master
Last bit of BYTE A is clocked into the slave
Slave clocks out first bit of BYTE B
Master clocks in first bit of BYTE B
Slave clocks out second bit of BYTE B
Master clocks in last bit of BYTE B
Atmel AT25DF641
3680F–DFLASH–4/10
Atmel AT25DF641
13.
Electrical Specifications
13.1. Absolute Maximum Ratings*
Temperature under Bias......................... −55°C to +125°C
Storage Temperature ........................... −65°C to + 150°C
All Input Voltages (including NC Pins)
with Respect to Ground ............................... − 0.6 V +4.1V
All Output Voltages
with Respect to Ground .................... − 0.6 V to VCC +0.5V
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only
and functional operation of the device at these or
any other conditions beyond those indicated in
the operational sections of this specification are
not implied. Exposure to absolute maximum
rating conditions for extended periods may affect
device reliability.
13.2. DC and AC Operating Range
Atmel AT25DF641
Operating Temperature (Case)
Ind.
-40°C to 85°C
VCC Power Supply
2.7V to 3.6V
13.3. DC Characteristics
Symbol Parameter
Condition
ISB
Standby Current
CS , WP , HOLD = VCC,
all inputs at CMOS levels
IDPD
Deep Power-down Current
Min
CS , WP , HOLD = VCC,
all inputs at CMOS levels
f = 75MHz; IOUT = 0mA;
CS = VIL, VCC = Max
f = 66MHz; IOUT = 0mA;
CS = VIL, VCC = Max
ICC1
Active Current, Read Operation
f = 50MHz; IOUT = 0mA;
CS = VIL, VCC = Max
f = 33MHz; IOUT = 0mA;
CS = VIL, VCC = Max
f = 20MHz; IOUT = 0mA;
CS = VIL, VCC = Max
Typ
Max
Units
25
50
µA
15
25
µA
13
17
12
14
11
13
10
12
9
11
mA
ICC2
Active Current, Program Operation
CS = VCC, VCC = Max
12
18
mA
ICC3
Active Current, Erase Operation
CS = VCC, VCC = Max
12
18
mA
ILI
Input Leakage Current
VIN = CMOS levels
1
µA
ILO
Output Leakage Current
VOUT = CMOS levels
1
µA
VIL
Input Low Voltage
0.3 x VCC
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 1.6mA; VCC = Min
VOH
Output High Voltage
IOH = -100 µA; VCC = Min
0.7 x VCC
V
0.4
VCC - 0.2V
V
V
47
3680F–DFLASH–4/10
13.4. AC Characteristics - Maximum Clock Frequencies
Symbol Parameter
Min
Max
Units
Atmel RapidS and SPI Operation
fMAX
Maximum Clock Frequency for All Operations – Atmel RapidS Operation Only
(excluding 0Bh, 03h, 3Bh, and 9F opcodes)
100
MHz
fCLK
Maximum Clock Frequency for All Operations
(excluding 03h and 3Bh opcodes)
75
MHz
fRDLF
Maximum Clock Frequency for 03h Opcode (Read Array – Low Frequency)
45
MHz
fRDDO
Maximum Clock Frequency for 3Bh Opcode (Dual-Output Read)
55
MHz
Max
Units
13.5. AC Characteristics – All Other Parameters
Symbol Parameter
tCLKH
Clock High Time
4.3
ns
tCLKL
Clock Low Time
4.3
ns
tCLKR(1)
Clock Rise Time, Peak-to-Peak (Slew Rate)
0.1
V/ns
t
(1)
CLKF
Clock Fall Time, Peak-to-Peak (Slew Rate)
0.1
V/ns
tCSH
Chip Select High Time
50
ns
tCSLS
Chip Select Low Setup Time (relative to Clock)
5
ns
tCSLH
Chip Select Low Hold Time (relative to Clock)
5
ns
tCSHS
Chip Select High Setup Time (relative to Clock)
5
ns
tCSHH
Chip Select High Hold Time (relative to Clock)
5
ns
tDS
Data In Setup Time
2
ns
tDH
Data In Hold Time
1
ns
tDIS(1)
Output Disable Time
tV
(2)
5
Output Valid Time
ns
5
ns
tOH
Output Hold Time
2
ns
tHLS
HOLD Low Setup Time (relative to Clock)
5
ns
tHLH
HOLD Low Hold Time (relative to Clock)
5
ns
tHHS
HOLD High Setup Time (relative to Clock)
5
ns
tHHH
HOLD High Hold Time (relative to Clock)
5
ns
tHLQZ(1)
HOLD Low to Output High-Z
5
ns
(1)
HOLD High to Output Low-Z
5
ns
tHHQX
tWPS
t
(1)(3)
(1)(3)
WPH
tSECP(1)
tSECUP
tLOCK
(1)
(1)
Write Protect Setup Time
20
Write Protect Hold Time
100
ns
ns
Sector Protect Time (from Chip Select High)
20
ns
Sector Unprotect Time (from Chip Select High)
20
ns
Sector Lockdown and Freeze Sector Lockdown State Time (from Chip Select High)
200
µs
t
(1)
EDPD
Chip Select High to Deep Power-Down
1
µs
t
(1)
RDPD
Chip Select High to Standby Mode
30
µs
Reset Time
30
µs
tRST
Notes:
48
Min
1. Not 100% tested (value guaranteed by design and characterization)
2. 15pF load at frequencies above 70MHz, 30pF otherwise
3. Only applicable as a constraint for the Write Status Register Byte 1 command when SPRL = 1
Atmel AT25DF641
3680F–DFLASH–4/10
Atmel AT25DF641
13.6. Program and Erase Characteristics
Symbol
tPP
(1)
tBP
Parameter
Min
Page Program Time (256 Bytes)
Byte Program Time
Typ
Max
Units
1.0
3.0
ms
7
µs
4-Kbytes
50
200
32-Kbytes
250
600
64-Kbytes
tBLKE(1)
Block Erase Time
400
950
tCHPE(1)(2)
Chip Erase Time
64
112
sec
tSUSP
Program/Erase Suspend Time
10
20
µs
tRES
Program/Erase Resume Time
10
20
µs
tOTPP(1)
OTP Security Register Program Time
200
500
µs
tWRSR(2)
Write Status Register Time
200
ns
ms
Notes: 1. Maximum values indicate worst-case performance after 100,000 erase/program cycles
2. Not 100% tested (value guaranteed by design and characterization)
13.7. Power-up Conditions
Symbol
Parameter
tVCSL
Minimum VCC to Chip Select Low Time
tPUW
Power-up Device Delay Before Program or Erase Allowed
VPOR
Power-on Reset Voltage
Min
Max
µs
50
1.5
Units
10
ms
2.5
V
13.8. Input Test Waveforms and Measurement Levels
AC
DRIVING
LEVELS
0.9VCC
VCC/2
0.1VCC
AC
MEASUREMENT
LEVEL
tR, tF < 2 ns (10% to 90%)
13.9. Output Test Load
DEVICE
UNDER
TEST
15pF (frequencies above 70MHz)
or
30pF
49
3680F–DFLASH–4/10
14.
AC Waveforms
Figure 14-1. Serial Input Timing
tC S H
CS
tC S LH
tC LK L
tC S LS
tC LK H
tC S HH
tC S HS
SCK
tDH
tDS
MS B
SI
SO
LS B
MS B
HIG H-IMP E DANC E
Figure 14-2. Serial Output Timing
CS
tC LK H
tC LK L
tDIS
SCK
SI
tOH
tV
tV
SO
Figure 14-3. WP Timing for Write Status Register Byte 1 Command When SPRL = 1
CS
tWP H
tWP S
WP
SCK
SI
0
MS B OF
WR IT E S T AT US R E G IS T E R
B Y T E 1 OP C ODE
SO
50
0
0
X
MS B
LS B OF
WR IT E S T AT US R E G IS T E R
DAT A B Y T E
MS B OF
NE XT OP C ODE
HIG H-IMP E DANC E
Atmel AT25DF641
3680F–DFLASH–4/10
Atmel AT25DF641
Figure 14-4. HOLD Timing – Serial Input
CS
SCK
tHHH
tHLS
tHLH
tHHS
tHLH
tHHS
HOLD
SI
SO
HIG H-IMP E DANC E
Figure 14-5. HOLD Timing – Serial Output
CS
SCK
tHLS
tHHH
HOLD
SI
tHLQZ
tHHQX
SO
51
3680F–DFLASH–4/10
15.
Ordering Information
15.1. Ordering Code Detail
AT 2 5 D F 6 4 1 - S 3 H - B
Atmel Designator
Shipping Carrier Option
B = Bulk (tubes)
Y = Bulk (trays)
T = Tape and reel
Product Family
Device Grade
H = Green, NiPdAu lead finish,
Industrial Temperature range
-40°C to +85°C
Device Density
64 = 64-megabit
Package Option
Interface
1 = Serial
S3 = 16-lead, 0.300” wide SOIC
MW= 8-contract, 6mm x 8mm VDFN
15.2. Green Package Options (Pb/Halide-free/RoHS Compliant)
Ordering Code
AT25DF641-S3H-B
AT25DF641-S3H-T
AT25DF641-MWH-Y
AT25DF641-MWH-T
Note:
Package
Lead
Finish
Voltage
Max. Freq.
(MHz)
NiPdAu
2.7V to 3.6V
75
Operating Range
16S
Industrial Temperature
(−40°C to 85°C)
8MW1
The shipping carrier option code is not marked on the devices
Package Type
52
16S
16-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC)
8MW1
8-contact, 6 x 8mm, Very Thin Dual Flat No Lead Package (VDFN)
Atmel AT25DF641
3680F–DFLASH–4/10
Atmel AT25DF641
16.
Packaging Information
16S – SOIC
1
End View
E
H
E
N
L
Top View
C
e
b
A1
A
D
COMMON DIMENSIONS
(Unit of Measure = mm)
Side View
SYMBOL
Notes: 1. This drawing is for general information only; refer to
JEDEC Drawing MS-013, Variation AA for additional
information.
2. Dimension D does not include mold Flash, protrusions
or gate burrs. Mold Flash, protrusion and gate burrs
shall not exceed 0.15 mm (0.006") per side.
3. Dimension E does not include inter-lead Flash or
protrusion. Inter-lead flash and protrusions shall not
exceed 0.25 mm (0.010") per side.
4. L is the length of the terminal for soldering to a
substrate.
MIN
NOM
MAX
A
2.35
–
2.65
A1
0.10
–
0.30
b
0.31
–
0.51
NOTE
D
10.30 BSC
2
E
7.50 BSC
3
H
10.30 BSC
L
0.40
e
C
1.27
–
4
1.27 BSC
0.20
0.33
11/02/05
TITLE
16S, 16-lead, 0.300" Wide Body, Plastic Gull
Package Drawing Contact:
packagedrawings@atmel.com Wing Small Outline Package (SOIC)
DRAWING NO.
REV.
16S
A
53
3680F–DFLASH–4/10
8MW1 – VDFN
C
E
Pin 1 ID
Side View
D
Top View
A1
A
E1
8
1
Pin #1 ID
Pin #1
Option A Chamfer
(C 0.30)
COMMON DIMENSIONS
(Unit of Measure = mm)
2
7
SYMBOL
D1
6
3
e
Option B
NOM
MAX
0.80
–
1.00
A1
–
–
0.05
0.35
0.40
0.48
b
4
5
MIN
A
C
b
L
K
Bottom View
Pin #1
Notch
(0.20 R)
0.203 REF
D
5.90
6.00
6.10
D1
4.70
4.80
4.90
E
7.90
8.00
8.10
E1
4.80
4.90
5.00
e
L
NOTE
1.27
0.45
K
0.55
0.50
1.05 REF
1/12/09
TITLE
8MW1, 8-pad (6 x 8 x 1.0 mm Body), Thermally
Package Drawing Contact:
packagedrawings@atmel.com Enhanced Plastic Very Thin Dual Flat No Lead
Package (VDFN)
54
DRAWING NO.
REV.
8MW1
E
Atmel AT25DF641
3680F–DFLASH–4/10
Atmel AT25DF641
17.
Revision History
Doc. Rev.
Date
3680F
04/2010
Comments
Changed Deep Power Down Current
– Increased typical value from 5µA to 15µA
– Increased max value from 10µA to 25µA
Changed Active Current, Read Operation
– Removed ICC1 for 100MHz
– Decreased ICC1 frequency from 85MHz to 75MHz
– Increased typical ICC1 value from 10mA to 13mA
– Increased typical ICC1 value for 66MHz from 8mA to 12mA
– Increased typical ICC1 value for 50MHz from 7mA to 11mA and max value from 12mA to 13mA
– Increased typical ICC1 value for 33MHz from 6mA to 10mA and max value from 10mA to 12mA
– Increased typical ICC1 value for 20MHz from 5mA to 9mA and max value from 8mA to 11mA
Changed the Read Array frequencies
– 1Bh command: Decreased max value from 100MHz to 75MHz
– 0Bh command: Decreased max value from 85MHz to 75MHz
– 03h command: Decreased max value from 50MHz to 45MHz
– 3Bh command: Decreased max value from 85MHz to 55MHz
Removed “Preliminary” status from datasheet
Removed the Errata section
3680E
12/2008
Changed Standby Current value
– Increased maximum value from 35µA to 50µA
Changed Deep Power-Down Current values
– Increased typical value from 1µA to 5µA
– Increased maximum value from 5µA to 10µA
3680D
11/2008
Added Errata (Section 18) regarding Erase Suspend and AC Characteristics
Corrected clock frequency values in Table 5-1
3680C
06/2008
Replaced the technical illustration (16S2) with the correct one (16S) on page 53
3680B
02/2008
Minor text edits throughout document
Changed Standby Current values
– Increased typical value from 10µA to 25µA
– Increased maximum value from 20µA to 35µA
Changed minimum Clock High Time and minimum Clock Low Time from 3.7ns to 4.3ns
3680A
12/2007
Initial document release
55
3680F–DFLASH–4/10
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In t er n at io n al
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3680F–DFLASH–4/10