Features
• Utilizes the AVR® RISC Architecture
• AVR – High-performance and Low-power RISC Architecture
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– 118 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General-purpose Working Registers
– Up to 8 MIPS Throughput at 8 MHz
Data and Nonvolatile Program Memory
– 8K Bytes of In-System Programmable Flash
Endurance: 1,000 Write/Erase Cycles
– 512 Bytes of SRAM
– 512 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
– One 16-bit Timer/Counter with Separate Prescaler
Compare, Capture Modes and Dual 8-, 9-, or 10-bit PWM
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
– Programmable Serial UART
– Master/Slave SPI Serial Interface
Special Microcontroller Features
– Low-power Idle and Power-down Modes
– External and Internal Interrupt Sources
Specifications
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
Power Consumption at 4 MHz, 3V, 25°C
– Active: 3.0 mA
– Idle Mode: 1.0 mA
– Power-down Mode: 2 XTAL1 clock cycles
High: > 2 XTAL1 clock cycles
Serial Programming
Algorithm
When writing serial data to the AT90S8515, data is clocked on the rising edge of SCK.
When reading data from the AT90S8515, data is clocked on the falling edge of SCK.
See Figure 65, Figure 66 and Table 33 on page 89 for timing details.
To program and verify the AT90S8515 in the Serial Programming Mode, the following
sequence is recommended (see 4-byte instruction formats in Table 32):
1. Power-up sequence:
Apply power between VCC and GND while RESET and SCK are set to “0”. If a crystal is not connected across pins XTAL1 and XTAL2, apply a clock signal to the
XTAL1 pin. In some systems, the programmer cannot guarantee that SCK is held
low during power-up. In this case, RESET must be given a positive pulse of at least
two XTAL1 cycles duration after SCK has been set to “0”.
2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to the MOSI (PB5) pin.
3. The serial programming instructions will not work if the communication is out of
synchronization. When in sync, the second byte ($53) will echo back when issu-
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AT90S8515
ing the third byte of the Programming Enable instruction. Whether the echo is
correct or not, all four bytes of the instruction must be transmitted. If the $53 did
not echo back, give SCK a positive pulse and issue a new Programming Enable
instruction. If the $53 is not seen within 32 attempts, there is no functional device
connected.
4. If a Chip Erase is performed (must be done to erase the Flash), wait tWD_ERASE
after the instruction, give RESET a positive pulse and start over from step 2. See
Table 34 on page 89 for tWD_ERASE value.
5. The Flash or EEPROM array is programmed one byte at a time by supplying the
address and data together with the appropriate Write instruction. An EEPROM
memory location is first automatically erased before new data is written. Use
Data Polling to detect when the next byte in the Flash or EEPROM can be written. If polling is not used, wait tWD_PROG before transmitting the next instruction.
See Table 35 on page 89 for tWD_PROG value. In an erased device, no $FFs in the
data file(s) need to be programmed.
6. Any memory location can be verified by using the Read instruction that returns
the content at the selected address at the serial output MISO (PB6) pin.
7. At the end of the programming session, RESET can be set high to commence
normal operation.
8. Power-off sequence (if needed):
Set XTAL1 to “0” (if a crystal is not used).
Set RESET to “1”.
Turn VCC power off.
Data Polling EEPROM
When a byte is being programmed into the EEPROM, reading the address location
being programmed will give the value P1 until the auto-erase is finished and then the
value P2. See Table 31 for P1 and P2 values.
At the time the device is ready for a new EEPROM byte, the programmed value will read
correctly. This is used to determine when the next byte can be written. This will not work
for the values P1 and P2, so when programming these values, the user will have to wait
for at least the prescribed time tWD_PROG before programming the next byte. See Table
34 for tWD_PROG value. As a chip-erased device contains $FF in all locations, programming of addresses that are meant to contain $FF can be skipped. This does not apply if
the EEPROM is reprogrammed without first chip-erasing the device.
Table 31. Read Back Value during EEPROM Polling
Data Polling Flash
Part
P1
P2
AT90S8515
$80
$7F
When a byte is being programmed into the Flash, reading the address location being
programmed will give the value $7F. At the time the device is ready for a new byte, the
programmed value will read correctly. This is used to determine when the next byte can
be written. This will not work for the value $7F, so when programming this value, the
user will have to wait for at least tWD_PROG before programming the next byte. As a chiperased device contains $FF in all locations, programming of addresses that are meant
to contain $FF can be skipped.
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Figure 65. Serial Programming Waveforms
Table 32. Serial Programming Instruction Set
Instruction Format
Instruction
Programming Enable
Chip Erase
Read Program Memory
Write Program Memory
Read EEPROM Memory
Write EEPROM Memory
Write Lock Bits
Byte 1
Byte 2
Byte 3
Byte4
Operation
1010 1100
0101 0011
xxxx xxxx
xxxx xxxx
Enable serial programming while
RESET is low.
1010 1100
100x xxxx
xxxx xxxx
xxxx xxxx
Chip Erase Flash and EEPROM
memory arrays.
0010 H000
xxxx aaaa
bbbb bbbb
oooo oooo
Read H (high or low) data o from
program memory at word address a:b.
0100 H000
xxxx aaaa
bbbb bbbb
iiii iiii
Write H (high or low) data i to program
memory at word address a:b.
1010 0000
xxxx xxxa
bbbb bbbb
oooo oooo
Read data o from EEPROM memory at
address a:b.
1100 0000
xxxx xxxa
bbbb bbbb
iiii iiii
Write data i to EEPROM memory at
address a:b.
1010 1100
111x x21x
xxxx xxxx
xxxx xxxx
Write Lock bits. Set bits 1,2 = “0” to
program Lock bits.
Read Signature Bytes
0011 0000
xxxx xxxx
xxxx xxbb
oooo oooo Read signature byte o at address b.(1)
Note:
1. The signature bytes are not readable in lock mode 3, i.e., both Lock bits programmed.
a = address high bits
b = address low bits
H = 0 – Low byte, 1 – High Byte
o = data out
i = data in
x = don’t care
1 = Lock bit 1
2 = Lock bit 2
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Serial Programming
Characteristics
Figure 66. Serial Programming Timing
MOSI
SCK
tSLSH
tSHOX
tOVSH
tSHSL
MISO
tSLIV
Table 33. Serial Programming Characteristics, TA = -40°C to 85°C, VCC = 2.7V - 6.0V
(unless otherwise noted)
Symbol
Parameter
Min
1/tCLCL
Oscillator Frequency (VCC = 2.7 - 4.0V)
tCLCL
Oscillator Period (VCC = 2.7 - 4.0V)
1/tCLCL
Oscillator Frequency (VCC = 4.0 - 6.0V)
tCLCL
Oscillator Period (VCC = 4.0 - 6.0V)
tSHSL
Typ
0
Max
Units
4.0
MHz
250.0
ns
0
8.0
MHz
125.0
ns
SCK Pulse Width High
2.0 tCLCL
ns
tSLSH
SCK Pulse Width Low
2.0 tCLCL
ns
tOVSH
MOSI Setup to SCK High
tCLCL
ns
tSHOX
MOSI Hold after SCK High
2.0 tCLCL
ns
tSLIV
SCK Low to MISO Valid
10.0
16.0
32.0
ns
Table 34. Minimum Wait Delay after the Chip Erase Instruction
Symbol
3.2V
3.6V
4.0V
5.0V
tWD_ERASE
18 ms
14 ms
12 ms
8 ms
Table 35. Minimum Wait Delay after Writing a Flash or EEPROM Location
Symbol
3.2V
3.6V
4.0V
5.0V
tWD_PROG
9 ms
7 ms
6 ms
4 ms
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Electrical Characteristics
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C
*NOTICE:
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin except RESET
with Respect to Ground .............................-1.0V to VCC + 0.5V
Voltage on RESET
with Respect to Ground ...................................-1.0V to +13.0V
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Maximum Operating Voltage ............................................ 6.6V
DC Current per I/O Pin ............................................... 40.0 mA
DC Current VCC and GND Pins................................ 200.0 mA
DC Characteristics
TA = -40°C to 85°C, VCC = 2.7V to 6.0V (unless otherwise noted)
Symbol
VIL
VIL1
Parameter
Condition
Input Low Voltage
(Except XTAL1)
Input Low Voltage
(XTAL1)
Min
Typ
Max
Units
0.3 VCC
(1)
V
0.2 VCC
(1)
V
(2)
VCC + 0.5
V
-0.5
-0.5
VIH
Input High Voltage
(Except XTAL1, RESET)
0.6 VCC
VIH1
Input High Voltage
(XTAL1)
0.8 VCC(2)
VCC + 0.5
V
VIH2
Input High Voltage
(RESET)
0.9 VCC(2)
VCC + 0.5
V
0.6
0.5
V
V
(3)
VOL
Output Low Voltage
(Ports A, B, C, D)
IOL = 20 mA, VCC = 5V
IOL = 10 mA, VCC = 3V
VOH
Output High Voltage(4)
(Ports A, B, C, D)
IOH = -3 mA, VCC = 5V
IOH = -1.5 mA, VCC = 3V
IIL
Input Leakage
Current I/O Pin
VCC = 6V, pin low
(absolute value)
8.0
µA
IIH
Input Leakage
Current I/O Pin
VCC = 6V, pin high
(absolute value)
980.0
nA
RRST
Reset Pull-up Resistor
100.0
500.0
kΩ
RI/O
I/O Pin Pull-up Resistor
35.0
120.0
kΩ
Active Mode, VCC = 3V, 4 MHz
3.0
mA
Idle Mode VCC = 3V, 4 MHz
1.2
mA
Power Supply Current
ICC
Power-down mode(5)
V
V
WDT enabled, VCC = 3V
9.0
15.0
µA
WDT disabled, VCC = 3V