ATF1504ASVL-20AU100

ATF1504ASV/ATF1504ASVL ATF1504ASV(L) 3.3V 64-Macrocell CPLD Data Sheet Features Enhanced Features • High-Density, High-Performance, Electrically-Erasable Complex Programmable Logic Device: - 3.0V to 3.6V operating range - 64 macrocells - 5 product terms per macrocell, expandable up to 40 per macrocell - 44 and 100 pins - 15 ns maximum pin-to-pin delay - Registered operation up to 77 MHz - Enhanced routing resources • In-System Programmability (ISP) via JTAG • Flexible Logic Macrocell: - D/T/Latch configurable flip-flops - Global and individual register control signals - Global and individual output enable - Programmable output slew rate - Programmable output open-collector option - Maximum logic utilization by burying a register with a COM output • Advanced Power Management Features: - Automatic 5 µA Standby (ATF1504ASVL) - Pin-controlled 100 µA Standby mode (typical) - Programmable pin-keeper circuits on inputs and I/Os - Reduced-power feature per macrocell • Available in Industrial Temperature Range • Robust EEPROM Technology: - 100% tested - Completely reprogrammable - 10,000 Program/Erase cycles - 20-year data retention - 2000V ESD protection - 200 mA latch-up immunity • JTAG Boundary-Scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported • PCI-Compliant • Security Fuse Feature • Green (Pb/Halide-Free/RoHS Compliant) Package Options • Improved Connectivity (Additional Feedback Routing, Alternate Input Routing) • Output Enable Product Terms • Transparent-Latch Mode • Combinatorial Output with Registered Feedback within any Macrocell • Three Global Clock Pins • ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O • Fast Registered Input from Product Term • Programmable “Pin-keeper” Option • VCC Power-Up Reset Option • Pull-Up Option on JTAG Pins (TMS and TDI) • Advanced Power Management Features: - Edge-controlled power-down (ATF1504ASVL) - Individual macrocell power option - Disable ITD on global clocks  2019 Microchip Technology Inc. Packages • 44-Lead PLCC • 44-Lead and 100-Lead TQFP Description The ATF1504ASV(L) is a high-performance, high-density complex programmable logic device (CPLD) that utilizes Microchip’s proven electrically-erasable memory technology. With 64 logic macrocells and up to 68 inputs and I/Os, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1504ASV(L)’s enhanced routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications. The ATF1504ASV(L) has up to 64 bidirectional I/O pins and four dedicated input pins, depending on the type of device package selected. Each dedicated pin can also serve as a global control signal (register clock, register Reset or output enable). Each of these control signals can be selected for use individually within each macrocell. DS20006185A-page 1 ATF1504ASV/ATF1504ASVL Each of the 64 macrocells generates a buried feedback that goes to the global bus. Each input and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus. Each macrocell also generates a foldback logic term that goes to a regional bus. Cascade logic between macrocells in the ATF1504ASV(L) allows fast, efficient generation of complex logic functions. The ATF1504ASV(L) contains four such logic chains, each capable of creating sum term logic with a fan-in of up to 40 product terms. The ATF1504ASV(L) macrocell (see ATF1504ASV(L) Macrocell), is flexible enough to support highly complex logic functions operating at high speed. The macrocell consists of five sections: product terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select and enable, and logic array inputs. ATF1504ASV(L) Macrocell  2019 Microchip Technology Inc. DS20006185A-page 2 ATF1504ASV/ATF1504ASVL Pin Configurations and Pinouts 44-Lead TQFP (Top View) 33 32 31 30 29 28 27 26 25 24 23 I/O I/O/TDO I/O I/O VCC I/O I/O I/O/TCK I/O GND I/O I/O GCLK3/I/O GND GCLK1/I I/OE1 GCLR/I GCLK2/OE2/I Vcc I/O I/O I/O 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 I/O I/O I/O PD2/I/O I/O Vcc GND I/O I/O I/O I/O I/O/TDI I/O I/O GND PD1/I/O I/O TMS/I/O I/O VCC I/O I/O 1 2 3 4 5 6 7 8 9 10 11 39 38 37 36 35 34 33 32 31 30 29 18 19 20 21 22 23 24 25 26 27 28 7 8 9 10 11 12 13 14 15 16 17 I/O I/O I/O I/O GND VCC I/O PD2/I/O I/O I/O I/O TDI/I/O I/O I/O GND PD1/I/O I/O I/O/TMS I/O VCC I/O I/O 6 5 4 3 2 1 44 43 42 41 40 I/O I/O I/O VCC GCLK2/OE2/I GCLR/I OE1/I GCLK1/I GND GCLK3/I/O I/O I/O I/O/TDO I/O I/O VCC I/O I/O I/O/TCK I/O GND I/O 44-Lead PLCC (Top View) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 I/O GND I/O/TDO NC I/O NC I/O I/O I/O VCCIO I/O I/O I/O I/O/TCK I/O I/O GND I/O I/O I/O NC I/O NC I/O VCCIO 100-Lead TQFP (Top View) I/O NC NC I/O I/O I/O 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 NC NC I/O I/O I/O I/O I/O GND I/O/PD2 I/O I/O VCCINT GND I/O I/O I/O VCCIO I/O I/O I/O I/O I/O NC NC GND  2019 Microchip Technology Inc. VCCIO I/O/TDI NC I/O NC I/O I/O I/O GND I/O/PD1 I/O I/O I/O/TMS I/O I/O VCCIO I/O I/O I/O NC I/O NC I/O NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 VCCIO I/O I/O I/O/GCLK3 GND NPUT/GCLK1 INPUT/OE1 INPUT/GCLR INPUT/OE2/GCLK2 VCCINT I/O I/O I/O GND I/O I/O I/O I/O I/O 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 DS20006185A-page 3 ATF1504ASV/ATF1504ASVL Block Diagram Unused product terms are automatically disabled by the compiler to decrease power consumption. A security fuse, when programmed, protects the contents of the ATF1504ASV(L). Two bytes (16 bits) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the security fuse. The ATF1504ASV(L) device is an in-system programmable (ISP) device. It uses the industry-standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundary-scan Description Language (BSDL). ISP allows the device to be programmed without removing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software.  2019 Microchip Technology Inc. DS20006185A-page 4 ATF1504ASV/ATF1504ASVL PRODUCT TERMS AND SELECT MUX EXTRA FEEDBACK Each ATF1504ASV(L) macrocell has five product terms. Each product term receives as its inputs all signals from both the global bus and regional bus. The product term select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic gates and control signals. The PTMUX programming is determined by the design compiler, which selects the optimum macrocell configuration. The ATF1504ASV(L) macrocell output can be selected as registered or combinatorial. The extra buried feedback signal can be either combinatorial or a registered signal regardless of whether the output is combinatorial or registered. (This enhancement function is automatically implemented by the fitter software.) Feedback of a buried combinatorial output allows the creation of a second latch within a macrocell. OR/XOR/CASCADE LOGIC I/O CONTROL The ATF1504ASV(L)’s logic structure is designed to efficiently support all types of logic. Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5-input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with little additional delay. The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be individually configured as an input, output or for bidirectional operation. The output enable for each macrocell can be selected from the true or compliment of the two output enable pins, a subset of the I/O pins, or a subset of the I/O macrocells. This selection is automatically done by the fitter software when the I/O is configured as an input, all macrocell resources are still available, including the buried feedback, expander and cascade logic. The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions. One input to the XOR comes from the OR sum term. The other XOR input can be a product term or a fixed high- or low-level. For combinatorial outputs, the fixed level input allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimization of product terms. The XOR gate is also used to emulate T- and JK-type flip-flops. FLIP-FLOP The ATF1504ASV(L)’s flip-flop has very flexible data and control functions. The data input can come from either the XOR gate, from a separate product term or directly from the I/O pin. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial output macrocell. (This feature is automatically implemented by the fitter software). In addition to D, T, JK and SR operation, the flip-flop can also be configured as a flow-through latch. In this mode, data passes through when the clock is high and is latched when the clock is low. The clock itself can either be one of the Global CLK Signal (GCK[0:2]) or an individual product term. The flip-flop changes state on the clock’s rising edge. When the GCK signal is used as the clock, one of the macrocell product terms can be selected as a clock enable. When the clock enable function is active and the enable signal (product term) is low, all clock edges are ignored. The flip-flop’s asynchronous Reset signal (AR) can be either the Global Clear (GCLEAR), a product term, or always off. AR can also be a logic OR of GCLEAR with a product term. The asynchronous preset (AP) can be a product term or always off.  2019 Microchip Technology Inc. GLOBAL BUS/SWITCH MATRIX The global bus contains all input and I/O pin signals as well as the buried feedback signal from all 64 macrocells. The switch matrix in each logic block receives as its inputs all signals from the global bus. Under software control, up to 40 of these signals can be selected as inputs to the logic block. FOLDBACK BUS Each macrocell also generates a foldback product term. This signal goes to the regional bus and is available to four macrocells. The foldback is an inverse polarity of one of the macrocell’s product terms. The four foldback terms in each region allow generation of high fan-in sum terms (up to nine product terms) with little additional delay. Programmable Pin-Keeper Option for Inputs and I/Os The ATF1504ASV(L) offers the option of programming all input and I/O pins so that pin-keeper circuits can be utilized. When any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level. This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which causes unnecessary power consumption and system noise. The keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption. DS20006185A-page 5 ATF1504ASV/ATF1504ASVL Input Diagram I/O Diagram Speed/Power Management The ATF1504ASV(L) has several built-in speed and power management features. The ATF1504ASVL contains circuitry that automatically puts the device into a low-power Standby mode when no logic transitions are occurring. This not only reduces power consumption during inactive periods, but also provides proportional power savings for most applications running at system speeds below 5 MHz. All ATF1504ASV(L) also have an optional Power-Down mode. In this mode, current drops to below 5 mA. When the power-down option is selected, either PD1 or PD2 pins (or both) can be used to power down the part. The power-down option is selected in the design software or design source file. When enabled, the device goes into power-down when either PD1 or PD2 is high. In the Power-Down mode, all internal logic signals are latched and held, as are any enabled outputs. To further reduce power, each ATF1504ASV(L) macrocell has a reduced-power bit feature. This feature allows individual macrocells to be configured for maximum power savings. This feature may be selected as a design option. All pin transitions are ignored until the PD pin is brought low. When the power-down feature is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s macrocell may still be used to generate buried foldback and cascade logic signals.  2019 Microchip Technology Inc. DS20006185A-page 6 ATF1504ASV/ATF1504ASVL All power-down AC characteristic parameters are computed from external input or I/O pins, with reduced-power bit turned on. For macrocells in Reduced-Power mode (reduced-power bit turned on), the reduced-power adder, tRPA, must be added to the AC parameters, which include the data paths tLAD, tLAC, tIC, tACL or tACH, tEN and tSEXP. The ATF1504ASV(L) macrocell also has an option whereby the power can be reduced on a per macrocell basis. By enabling this power-down option, macrocells that are not used in an application can be turned down, thereby reducing the overall power consumption of the device. This option is automatically set by the device fitter software. Each output also has individual slew rate control. This may be used to reduce system noise by slowing down outputs that do not need to operate at maximum speed. Outputs default to slow switching, and may be specified as fast switching in the design software or design file. Design Software Support ATF1504ASV(L) designs are supported by Microchip’s ProChip Designer and WinCUPL software tools as well as Precision Synthesis from Mentor Graphic as described in the “Programmable Logic Device Design Software Overview”. Power-Up Reset The ATF1504ASV/ATF1504ASVL is designed with a power-up Reset, a feature critical for state machine initialization. At a point delayed slightly from VCC crossing VRST, all registers will be initialized, and the state of each output will depend on the polarity of its buffer. However, due to the asynchronous nature of Reset and uncertainty of how VCC actually rises in the system, the following conditions are required: • The VCC rise must be monotonic • After Reset occurs, all input and feedback setup times must be met before driving the clock pin high • The clock must remain stable during Power-up Reset The ATF1504ASV/ATF1504ASVL has two options for the hysteresis about the Reset level, VRST, Small and Large. To ensure a robust operating environment in applications where the device is operated near 3.0V, it is recommended that during the fitting process users configure the device with the Power-up Reset hysteresis set to Large. Users of the POF2JED conversion utility should include the flag “-power_reset” on the command line after “filename.POF”. To allow the registers to be properly reinitialized with the Large hysteresis option selected, the following condition is added: When the Large hysteresis option is active, ICC is reduced by several hundred microamps as well. Details on the power Reset hysteresis feature are available in the “ATF15XX Power-on Reset Hysteresis Feature” application note. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF1504ASV(L) fuse patterns. Once programmed, fuse verify is inhibited. However, the 16-bit User Signature remains accessible. Programming ATF1504ASV(L) devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG protocol. This capability eliminates package handling normally required for programming and facilitates rapid design iterations and field changes. Microchip provides ISP hardware and software to allow programming of the ATF1504ASV(L) via the PC. ISP is performed by using either a download cable, a comparable board tester or a simple microprocessor interface. To facilitate ISP programming by the Automated Test Equipment (ATE) vendors, Serial Vector Format (SVF) files can be created by Microchip provided software utilities. ATF1504ASV(L) devices can also be programmed using standard third-party programmers. With a third-party programmer, the JTAG ISP port can be disabled, thereby allowing four additional I/O pins to be used for logic. Refer to Programming of PLDs application note for more details. ISP Programming Protection The ATF1504ASV(L) has a special feature that locks the device and prevents the inputs and I/O from driving if the programming process is interrupted for any reason. The inputs and I/O default to high Z state during such a condition. In addition, the pin-keeper option preserves the former state during device programming, if this circuit was previously programmed on the device. This prevents disturbing the operation of other circuits in the system while the ATF1504ASV(L) is being programmed via ISP. All ATF1504ASV(L) devices are initially shipped in the erased state, thereby making them ready to use for ISP. • If VCC falls below 2.0V, it must shut off completely before the device is turned on again  2019 Microchip Technology Inc. DS20006185A-page 7 ATF1504ASV/ATF1504ASVL 1.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (†) Temperature under bias ............................................................................................................................-40°C to +85°C Storage temperature ............................................................................................................................... -65°C to +150°C Voltage on any pin with respect to ground(1) .............................................................................................. -2.0V to +7.0V † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Note 1: Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V DC, which may overshoot to 7.0V for pulses of less than 20 ns. TABLE 1-1: DC AND AC OPERATING CONDITIONS Industrial Operating Temperature (Ambient) -40°C to +85°C VCC (VCCIO/VCCINT) Power Supply 3.0V to 3.6V TABLE 1-2: Symbol DC CHARACTERISTICS Parameter Minimum Typical Maximum Units Condition IIL Input or I/O Low Leakage Current — -2 -10 µA VIN = GND IIH Input or I/O High Leakage Current — 2 10 µA VIN = VCC IOZ Tri-State Output Off-State Current -40 — 40 µA VO = VCC or GND ICC1 Power Supply Current, Standby — 75 — mA VCC = Max VIN = 0, VCC Std power — 5 — µA VCC = Max VIN = 0, VCC “L” power ICC2 Power Supply Current, Power-Down mode — 0.1 5 mA VCC = Max VIN = 0, VCC “PD” mode ICC3(1) Reduced Power mode Supply Current, Standby — 55 — mA VCC = Max VIN = 0, VCC Std power V VIL Input Low Voltage -0.3 — 0.8 VIH Input High Voltage 1.7 — VCCIO + 0.3 V VOL Output Low Voltage (3.3V TTL) — — 0.45 V VIN = VIH or VIL VCCIO = Min, IOL = 8 mA Output Low Voltage (3.3V CMOS) — — 0.2 V VIN = VIH or VIL VCCIO = Min, IOL = 0.1 mA Output High Voltage (3.3V TTL) 2.4 — — V VIN = VIH or VIL VCCIO = Min, IOH = -1.5 mA Output High Voltage (3.3V CMOS) VCCIO - 0.2 — — V VIN = VIH or VIL VCCIO = Min, IOH = -0.1 mA VOH Note 1: When macrocell reduced-power feature is enabled.  2019 Microchip Technology Inc. DS20006185A-page 8 ATF1504ASV/ATF1504ASVL TABLE 1-3: PIN CAPACITANCE Typical Maximum Units Conditions CIN — 8 pF VIN = 0V; f = 1.0 MHz CI/O — 8 pF VOUT = 0V; f = 1.0 MHz Note 1: 2: Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. The OGI pin (high-voltage pin during programming) has a maximum capacitance of 12 pF. Timing Model Internal Output Enable Delay tIOE Global Control Delay tGLOB Input Delay tIN Logic Array Delay tLAD Switch Matrix tUIM Register Control Delay tLAC tIC tEN Foldback Term Delay tSEXP TABLE 1-4: Register Delay tSU tH tPRE tCLR tRD tCOMB tFSU tFH Cascade Logic Delay tPEXP Fast Input Delay tFIN Output Delay tOD1 tOD2 tOD3 tXZ tZX1 tZX2 tZX3 I/O Delay tIO AC CHARACTERISTICS Symbol Parameter -15 -20 Min. Max. Min. Max. Units tPD1 Input or Feedback to Non-Registered Output 3 15 — 20 ns tPD2 I/O Input or Feedback to Non-Registered Feedback 3 12 — 16 ns tSU Global Clock Setup Time 11 — 13.5 — ns tH Global Clock Hold Time 0 — 0 — ns tFSU Global Clock Setup Time of Fast Input 3 — 3 — ns tFH Global Clock Hold Time of Fast Input 1.0 — 2 — ns tCOP Global Clock to Output Delay — 9 — 12 ns tCH Global Clock High Time 5 — 6 — ns tCL Global Clock Low Time 5 — 6 — ns tASU Array Clock Setup Time 5 — 7 — ns tAH Array Clock Hold Time 4 — 4 — ns tACOP Array Clock Output Delay — 15 — 18.5 ns tACH Array Clock High Time 6 — 8 — ns  2019 Microchip Technology Inc. DS20006185A-page 9 ATF1504ASV/ATF1504ASVL TABLE 1-4: AC CHARACTERISTICS (CONTINUED) Symbol Parameter -15 -20 Min. Max. Min. Max. Units tACL Array Clock Low Time 6 — 8 — ns tCNT Minimum Clock Global Period — 13 — 17 ns fCNT Maximum Internal Global Clock Frequency 76.9 — 66 — MHz tACNT Minimum Array Clock Period — 13 — 17 ns fACNT Maximum Internal Array Clock Frequency 76.9 — 58.8 — MHz fMAX Maximum Clock Frequency 100 — 83.3 — MHz tIN Input Pad and Buffer Delay — 2 — 2.5 ns tIO I/O Input Pad and Buffer Delay — 2 — 2.5 ns tFIN Fast Input Delay — 2 — 2 ns tSEXP Foldback Term Delay — 8 — 10 ns tPEXP Cascade Logic Delay — 1 — 1 ns tLAD Logic Array Delay — 6 — 8 ns tLAC Logic Control Delay — 3.5 — 4.5 ns tIOE Internal Output Enable Delay — 3 — 3 ns tOD1 Output Buffer and Pad Delay (Slow slew rate = OFF; VCCIO = 3.3V; CL = 35 pF) — 3 — 4 ns tOD3 Output Buffer and Pad Delay (Slow slew rate = ON; VCCIO = 3.3V; CL = 35 pF) — 5 — 6 ns tZX1 Output Buffer Enable Delay (Slow slew rate = OFF; VCCIO = 3.3V; CL = 35 pF) — 7 — 9 ns tZX3 Output Buffer Enable Delay (Slow slew rate = ON; VCCIO = 3.3V; CL = 35 pF) — 10 — 11 ns tXZ Output Buffer Disable Delay (CL = 5 pF) — 6 — 7 ns tSU Register Setup Time 5 — 6 — ns tH Register Hold Time 4 — 5 — ns tFSU Register Setup Time of Fast Input 2 — 2 — ns tFH Register Hold Time of Fast Input 2 — 2 — ns tRD Register Delay — 2 — 2.5 ns tCOMB Combinatorial Delay — 2 — 3 ns tIC Array Clock Delay — 6 — 7 ns tEN Register Enable Time — 6 — 7 ns tGLOB Global Control Delay — 2 — 3 ns tPRE Register Preset Time — 4 — 5 ns tCLR Register Clear Time — 4 — 5 ns tUIM Switch Matrix Delay — 2 — 2.5 ns  2019 Microchip Technology Inc. DS20006185A-page 10 ATF1504ASV/ATF1504ASVL TABLE 1-4: AC CHARACTERISTICS (CONTINUED) Symbol Parameter tRPA Note 1: -15 Reduced-Power Adder(1) -20 Min. Max. Min. Max. — 10 — 13 Units ns The tRPA parameter must be added to the tLAD, tLAC, tIC, tACL or tACH, tEN and tSEXP parameters for macrocells running in the Reduced-Power mode. FIGURE 1-1: Note: FIGURE 1-2: INPUT TEST WAVEFORMS AND MEASUREMENT LEVELS tR, tF = 1.5 ns typical OUTPUT AC TEST LOADS 3.0V R1 = 703Ÿ OUTPUT PIN R2 = 8060Ÿ Power-Down Mode The ATF1504ASV(L) includes an optional pin-controlled power-down feature. When this mode is enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply current is reduced to less than 5 mA. During power-down, all output data and internal logic states are latched internally and held. Therefore, all registered and combinatorial output data remain valid. Any outputs that were in a high Z state at the onset will remain at high Z. During power-down, all input signals except the Power-Down pin are blocked.  2019 Microchip Technology Inc. CL = 35 pF Input and I/O hold latches remain active to ensure that pins do not float to indeterminate levels, further reducing system power. The Power-Down mode feature is enabled in the logic design file or as a design software option. Designs using the Power-Down pin may not use the PD pin as a logic array input. However, all other PD pin macrocell resources may still be used, including the buried feedback and foldback product term array inputs. DS20006185A-page 11 ATF1504ASV/ATF1504ASVL TABLE 1-5: POWER-DOWN AC CHARACTERISTICS(1)(2)(3) Symbol tIVDH Parameter Valid I, I/O before PD High (2) before PD High -15 -20 Units Min. Max. Min. Max. 15 — 20 — ns 15 — 20 — ns 15 — 20 — ns tGVDH Valid OE tCVDH Valid Clock(2) before PD High tDHIX I, I/O Don’t Care after PD High — 25 — 30 ns tDHGX OE(2) Don’t Care after PD High — 25 — 30 ns tDHCX Clock(2) Don’t Care after PD High — 25 — 30 ns tDLIV PD Low to Valid I, I/O — 1 — 1 µs tDLGV PD Low to Valid OE (Pin or Term) — 1 — 1 µs tDLCV PD Low to Valid Clock (Pin or Term) — 1 — 1 µs tDLOV PD Low to Valid Output — 1 — 1 µs Note 1: 2: 3: For slow slew outputs, add tSSO. Pin or product term. Includes tRPA for reduced-power bit enabled. JTAG-BST/ISP Overview JTAG Boundary-Scan Cell (BSC) The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the ATF1504ASV(L). The boundary-scan technique involves the inclusion of a shift-register stage (contained in a boundary-scan cell) adjacent to each component so that signals at component boundaries can be controlled and observed using scan testing principles. Each input pin and I/O pin has its own boundary-scan cell (BSC) in order to support boundary-scan testing. The ATF1504ASV(L) contains up to 64 I/O pins and four input pins, depending on the device type and package type selected. Each input pin and I/O pin has its own boundary-scan cell (BSC) in order to support boundary-scan testing as described in detail by IEEE Standard 1149.1. A typical BSC consists of three capture registers or scan registers and up to two update registers. The ATF1504ASV(L) does not include a Test Reset (TRST) input pin because the TAP controller is automatically reset at power-up. The five JTAG modes supported include: SAMPLE/PRELOAD, EXTEST, BYPASS, IDCODE and HIGHZ. The ATF1504ASV(L)’s ISP can be fully described using JTAG’s BSDL as described in IEEE Standard 1149.1. This allows ATF1504ASV(L) programming to be described and implemented using any one of the third-party development tools supporting this standard. There are two types of BSCs, one for input or I/O pin, and one for the macrocells. The BSCs in the device are chained together through the capture registers. Input to the capture register chain is fed in from the TDI pin while the output is directed to the TDO pin. Capture registers are used to capture active device data signals, to shift data in and out of the device and to load data into the update registers. Control signals are generated internally by the JTAG TAP controller. The BSC configuration for the input and I/O pins and macrocells are shown in Figure 1-3 and Figure 1-4. The ATF1504ASV(L) has the option of using four JTAG-standard I/O pins for boundary-scan testing (BST) and in-system programming (ISP) purposes. The ATF1504ASV(L) is programmable through the four JTAG pins using the IEEE standard JTAG programming protocol established by IEEE Standard 1149.1 using 3.3V TTL/CMOS-level programming signals from the ISP interface for in-system programming. The JTAG feature is a programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are available as I/O pins.  2019 Microchip Technology Inc. DS20006185A-page 12 ATF1504ASV/ATF1504ASVL FIGURE 1-3: Note: BSC CONFIGURATION FOR INPUT AND I/O PINS (EXCEPT JTAG TAP PINS) The ATF1504ASV(L) has pull-up option on TMS and TDI pins. This feature is selected as a design option. FIGURE 1-4: BSC CONFIGURATION FOR MACROCELL Pin BSC TDO 0 1 Pin DQ Capture DR Clock TDI Shift TDO OEJ 0 0 1 D Q D Q 1 OUTJ 0 0 Pin 1 D Q D Q Capture DR Update DR 1 Mode TDI Shift Clock Macrocell BSC  2019 Microchip Technology Inc. DS20006185A-page 13 ATF1504ASV/ATF1504ASVL TABLE 1-6: DEDICATED PINOUTS Dedicated Pin 44-Lead TQFP 44-Lead J-lead 100-Lead TQFP INPUT/OE2 /GCLK2 40 2 90 INPUT/GCLR(3) 39 1 89 38 44 88 37 43 87 (1) INPUT/OE1 (2) (1) INPUT/GCLK1(2) (2) I/O /GCLK3 I/O / PD (1,2)(4) 35 41 85 5, 19 11, 25 12, 42 I/O / TDI (JTAG)(5) 1 7 4 I/O / TMS (JTAG)(5) 7 13 15 I/O / TCK (JTAG)(5) 26 32 62 I/O / TDO (JTAG)(5) 32 38 73 GND(6) 4, 16, 24, 36 10, 22, 30, 42 11, 26, 38, 43, 59, 74, 86, 95 VCC(7) 9, 17, 29, 41 3, 15, 23, 35 3, 18, 34, 39, 51, 66, 82, 91 N/C — — 1, 2, 5, 7, 22, 24, 27, 28, 49, 50, 53, 55, 70, 72, 77, 78 # of Signal Pins 36 36 68 # User I/O Pins 32 32 64 Note 1: OE (1, 2) = Global OE pins 2: GCLK (1, 2, 3) = Global Clock pins 3: GCLR = Global Clear pin 4: PD (1, 2) = Power-Down pins 5: TDI, TMS, TCK. TDO = JTAG pins used for boundary-scan testing or in-system programming 6: GND = Ground pins 7: VCC = VCC (VCCINT/VCCIO) pins for the device  2019 Microchip Technology Inc. DS20006185A-page 14 ATF1504ASV/ATF1504ASVL TABLE 1-7: I/O PINOUTS MC PLC 44-Lead PLCC 44-Lead TQFP 100-Lead TQFP MC PLC 44-Lead PLCC 44-Lead TQFP 100-Lead TQFP 1 A 12 6 14 33 C 24 18 40 2 A — — 13 34 C — — 41 3 A/PD1 11 5 12 35 C/PD2 25 19 42 4 A 9 3 10 36 C 26 20 44 5 A 8 2 9 37 C 27 21 45 6 A — — 8 38 C — — 46 7 A — — 6 39 C — — 47 8/TDI A 7 1 4 40 C 28 22 48 9 A — — 100 41 C 29 23 52 10 A — — 99 42 C — — 54 11 A 6 44 98 43 C — — 56 12 A — — 97 44 C — — 57 13 A — — 96 45 C — — 58 14 A 5 43 94 46 C 31 25 60 15 A — — 93 47 C — — 61 16 A 4 42 92 48/TCK C 32 26 62 17 B 21 15 37 49 D 33 27 63 18 B — — 36 50 D — — 64 19 B 20 14 35 51 D 34 28 65 20 B 19 13 33 52 D 36 30 67 21 B 18 12 32 53 D 37 31 68 22 B — — 31 54 D — — 69 23 B — — 30 55 D — — 71 24 B 17 11 29 56/TDO D 38 32 73 25 B 16 10 25 57 D 39 33 75 26 B — — 23 58 D — — 76 27 B — — 21 59 D — — 79 28 B — — 20 60 D — — 80 29 B — — 19 61 D — — 81 30 B 14 8 17 62 D 40 34 83 31 B — — 16 63 D — — 84 32/TMS B 13 7 15 64 D/GCLK3 41 35 85  2019 Microchip Technology Inc. DS20006185A-page 15 ATF1504ASV/ATF1504ASVL FIGURE 1-5: SUPPLY CURRENT VS. SUPPLY VOLTAGE – ATF1504ASV (TA = 25°C, F = 0) FIGURE 1-8: 25 100 20 Standard Power ICC (μA) 75 ICC (mA) SUPPLY CURRENT VS. SUPPLY VOLTAGE – ATF1504ASVL (TA = 25°C, F = 0) 50 15 10 Reduced Power Mode 5 25 0 0 2.5 2.5 2.75 3.75 3 3.25 3.5 Supply Voltage (V) FIGURE 1-9: SUPPLY CURRENT VS. SUPPLY VOLTAGE – PIN-CONTROLLED POWER-DOWN MODE (TA = 25°C, F = 0) SUPPLY CURRENT VS. FREQUENCY – ATF1504ASVL (TA = 25°C) 80.0 700 Standard Power 60.0 40.0 Reduced Power 20.0 Standard & Reduced Power Mode 600 0.0 0.00 5.00 500 400 2.5 2.75 3 3.25 3.5 Supply Voltage (V) 3.75 4 FIGURE 1-10: SUPPLY CURRENT VS. FREQUENCY – ATF1504ASV (TA = 25°C) IOH (mA) FIGURE 1-7: 150.0 125.0 ICC (mA) 4 3.75 100.0 800 ICC (μA) 2.75 4 ICC (mA) FIGURE 1-6: 3 3.25 3.5 Supply Voltage (V) Standard Power 100.0 75.0 Reduced Power Mode 50.0 0 -2 -4 -6 -8 -10 -12 -14 -16 2.75 10.00 Frequency (MHz) 15.00 20.00 OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (VOH = 2.4V, TA = 25°C) 3 3.25 3.5 Supply Voltage (V) 3.75 4 25.0 0.0 0.00 20.00 40.00 60.00 Frequency (MHz)  2019 Microchip Technology Inc. 80.00 100.00 DS20006185A-page 16 ATF1504ASV/ATF1504ASVL FIGURE 1-11: OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (VCC = 3.3V, TA = 25°C) FIGURE 1-14: INPUT CLAMP CURRENT VS. INPUT VOLTAGE (VCC = 3.3V, TA = 25°C) 0 10 Input Current (mA) 0 -10 IOH (mA) -20 -30 -40 -50 -20 -40 -60 -80 -60 -100 -70 0.0 0.5 1.0 FIGURE 1-12: 1.5 2.0 2.5 3.0 Output Voltage (V) 3.5 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 Input Voltage (V) 4.0 OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (VOL = 0.5V, TA = 25°C) FIGURE 1-15: 0 INPUT CURRENT VS. INPUT VOLTAGE (VCC = 3.3V, TA = 25°C) 20 40 15 Input Current (μA) IOL (mA) 35 30 25 10 5 0 -5 -10 20 2.75 3 3.25 3.5 Supply Voltage (V) 3.75 4 -15 0 FIGURE 1-13: OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE (VCC = 3.3V, TA = 25°C) 0.5 1 1.5 2 Input Voltage (V) 2.5 3 3.5 100 IOL (mA) 80 60 40 20 0 0 0.5 1 1.5 2 2.5 Output Voltage (V)  2019 Microchip Technology Inc. 3 3.5 4 DS20006185A-page 17 ATF1504ASV/ATF1504ASVL 2.0 PACKAGING INFORMATION 2.1 Package Marking Information 44-Lead PLCC XXXXXXXXXX XXXXXXXX YYWWNNN 44-Lead TQFP XXXXXXXXXX XXXXXXXX YYWWNNN 100-Lead TQFP XXXXXXXXXX XXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN * Note: Example ATF1504ASV 15JU44 1902610 Example ATF1504ASV 15AU44 1902610 Example ATF1504ASV 15AU100 1902610 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code This packages are RoHs compliant. The JEDEC® designator can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2019 Microchip Technology Inc. DS20006185A-page 18 ATF1504ASV/ATF1504ASVL /HDG3ODVWLF/HDGHG&KLS&DUULHU/±6TXDUH>3/&&@ 1RWH 2 &' !&" &3# *!(!!& 3%&  &#& &&455***'  '53 D D1 CH2 x 45° E E1 NOTE 1 N123 CH1 x 45° CH3 x 45° c A A2 A1 b1 b e E2 D2 6&! '! 9'&! 7"')  %! A3 7,8. 7 7 7: ;  &  :  8&  1