ATSAMA5D31-EK

ARM-based Embedded MPUs SAMA5D3x-EK User Guide USER GUIDE Introduction This user guide introduces the evaluation kits for the Atmel® SAMA5D3 series embedded MPUs listed below:  SAMA5D31  SAMA5D33  SAMA5D34  SAMA5D35  SAMA5D36 It pertains to the following evaluation kit references:  SAMA5D31-EK  SAMA5D33-EK  SAMA5D34-EK  SAMA5D35-EK  SAMA5D36-EK 11180B–ATARM–29-Oct-13 Contents Important:  Boards  One SAMA5D3 main board (MB)  One of the five available CPU module (CM) boards     Unpack and assemble the kit carefully, following the assembly guide provided in the box.  SAMA5D31-CM  SAMA5D33-CM  SAMA5D34-CM  SAMA5D35-CM  SAMA5D36-CM One optional Display Module (DM) board (5"_WVGA_R-DM), available for all SAMA5D3x evaluation kits that feature an LCD interface: SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D36 Power supply  One universal input AC/DC power supply with US, Europe and UK plug adapters  One 3V lithium battery type CR1225 Cables  One micro A/B-type USB cable  One RJ45 crossed cable A welcome letter Related Items  Atmel SAMA5D3 Series Datasheet SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 2 Table of Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Related Items . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. Evaluation Kit Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 Electrostatic Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 2.2 Power up the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Sample Code and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3. Evaluation Kit Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4. CPU Module (CM) Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 4.2 4.3 4.4 4.5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Equipment List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Embest/Flextronics Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Ronetix Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5. Main Board (MB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.1 5.2 5.3 5.4 5.5 Main Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Function Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 PIO Usage and Interface Connectors Details . . . . . . . . . . . . . . . . . . . . . . . . . 76 Main Board Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6. Optional Display Module (DM) Board . . . . . . . . . . . . . . . . . . . . . . 116 6.1 6.2 DM Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 7. Troubleshooting and Recommendations . . . . . . . . . . . . . . . . . . . . 120 7.1 Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 3 1. Evaluation Kit Specifications Table 1-1. Evaluation Kit Specifications Characteristic Specifications Clock speed Up to 536 MHz PCK, up to 166 MHz MCK Ports 10/100/1000 Ethernet, USB, RS232, JTAG, CAN, Audio, HDMI, SD card Board supply voltage 5V DC from connector Dimensions: MB (Main Board) 165 * 135 * 20 mm CM (Computer Module) Board 67.60 * (40 to 47) * 5 mm DM (Display Module) Board 135 * 80 * 6 mm RoHS status Compliant CE and FCC Part 15 status Compliant Kit Identification SAMA5D31-EK SAMA5D33-EK SAMA5D34-EK SAMA5D35-EK SAMA5D36-EK 1.1 Electrostatic Warning Warning: ESD-Sensitive Electronic Equipment! The evaluation kit is shipped in a protective anti-static package. The board system must not be subjected to high electrostatic potentials. We strongly recommend using a grounding strap or similar ESD protective device when handling the board in hostile ESD environments (offices with synthetic carpet, for example). Avoid touching the component pins or any other metallic element on the board. SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 4 2. Power Up 2.1 Power up the Board Unpack the board, taking care to avoid electrostatic discharge. Unpack the power supply, select the right power plug adapter corresponding to that of your country and insert it in the power supply. Connect the power supply DC connector to the board and plug the power supply to an AC power plug. The LCD should light up and display a welcome page. Click or touch icons displayed on the screen and view the demo (the red ones need to be replaced by demo software). 2.2 Sample Code and Technical Support After booting up the board, you can run sample code or your own application on the development kit. You can download sample code and get technical support from the Atmel web site. Linux software and demos can be found on the web site Linux4SAM. SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 5 3. Evaluation Kit Hardware 3.1 Introduction The Atmel SAMA5D3 series evaluation kit is a fully-featured evaluation platform for Atmel SAMA5D3 series microcontrollers. The evaluation kit allows users to extensively evaluate, prototype and create application-specific designs. The Atmel SAMA5D3 series evaluation kit is a platform architecture based on a main board, a computer module equipped with a SAMA5D3 series processor and an optional display module, providing maximum flexibility for kit users. The SAMA5D3 series evaluation kit consists of three boards:  The computer module (CM) board, is a single-board computer that integrates all the core components and is mounted onto an application-specific main board (MB). The computer module has specified pinouts based on the SODIMM200 connector. It provides the functional requirements for an embedded application. These functions include, but are not limited to, graphics, audio, mass storage, network and multiple serial and USB ports. A single SODIMM200 connector provides the main board interface to carry all the I/O signals to and from the computer module.  The main board (MB) provides all the interface connectors required to attach the system to the application specific peripherals. This versatility allows the designer to create a densely-packed solution, which results in a more reliable product while simplifying system integration.  The display module board (DM) integrates LCD, touchscreen and Qtouch® technology Table 3-1. Evaluation Kit Features Feature SAMA5D31 SAMA5D34 SAMA5D35 SAMA5D36 CAN0 X X X CAN1 X X X X X X X X GMAC SAMA5D33 X EMAC X HSMCI1 X HSMCI2 X X X X X X X X X X LCDC X X UART0 X X X UART1 X X X ISI X X X X X SHA X X X X X AES X X X X X TDES X X X X X TC1 X X X X X SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 6 4. CPU Module (CM) Board 4.1 Overview The CPU module (CM) board is the heart of the SAMA5D3x-EK. It connects to the main board through a SODIMM200 interface and integrates the SAMA5D3 series processor and external memories. The CM board serves as a minimal CPU sub-system. All five SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 and SAMA5D36 processors share the same CM board circuitry with minor configuration settings. The CM board connects to a carrier board containing its connectors, power supply and any expansion I/O through a standard gold-plated SODIMM 200-pin connection. Note: There are five CM boards from three different manufacturers. The five processors are implemented as shown in Table 4-1. Table 4-1. CM Board Implementation Manufacturer and Module Kind SAMA5D31-CM Embest/Flextronics X Ronetix X SAMA5D33-CM SAMA5D34-CM SAMA5D35-CM X X X SAMA5D36-CM X X The five CM boards share the same circuitry design with different designator information and PCB layouts. The circuitry reference in this guide, for common design parts, refers to schematics from SAMA5D3 series-CM (mfg2). All the other schematics are provided in the Section 4.4 “Embest/Flextronics Schematics” and Section 4.5 “Ronetix Schematics”. SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 7 Figure 4-1. CPU Module Board from Embest/Flextronics Figure 4-2. CPU Module Board from Ronetix SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 8 Figure 4-3. Board Architecture Nand Flash Nand Fllas F ash NAND FLASH 2Gb DDR2 DDR2 No N Nor or Flash Fllas F ash Gigabit ig igabit gab ab biit Ethernet bit Eth Ethe E thern net et et t Sodimm200 S di 200 to Data Data ata Flash Fllas F ash Led Led ed Led DDR2 2Gb NOR FLASH 128Mb Serial Data FLASH OneWire OneWire OneWire Gigabit Ethernet Gigabit Ethernet RGMII RGMII EBI EBI E BI SPI SPI PIO PIO External Memory External Memory SAMA5D3x-CM_BGA324 SAMA5D3x-CM_BGA324 System System Controller Controller 32Khz 12Mhz Os Osc sc c Power A A B B PIO PIO C C D D E E Power 3v3 1V8 1V2 So D So SoDIMM200 DIMM200 IMM2 200 00 00 SAMA5D3 Series Note: Different interfaces on the main board share the same connections to the CPU module. The actual usage depends on the CPU module featured in your evaluation kit. SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 9 4.2 Equipment List The CM board is built around an ARM® Cortex®-A5-based microcontroller (BGA 324 package) with external memory and Gigabit Ethernet PHYsical layer transceiver. 4.2.1 Devices Table 4-2. CPU Module Specifications Characteristic Specifications PCB CPU Module (10 layers) Dimensions in mm: (L x W x H) 67.60 *(40 to 47) * 5 max Processor SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 and SAMA5D36 (324-ball BGA package) Clock speed 12 MHz crystal 32.768 kHz Memory 2 x DDR2 2 Gb 16 Meg x 16 x 8 banks 1 x SLC NAND Flash 2/4Gb 8-bit data 1 x NOR 128 Mb 16-bit data On-board I/O Ports One Serial EEPROM SPI One 1-Wire EEPROM DS2431 One user-powered red LED and one user blue LED One gigabit Ethernet PHY Connector SODIMM200 Board supply voltage 3.3V from SODIMM200 connector On-board power regulation Temperature: - operating 0°C to +60°C - storage -40°C to +85°C Relative humidity 0 to 90% (non condensing) RoHS status Compliant SAMA5D31-CM Board Identification SAMA5D33-CM SAMA5D34-CM Silkscreen top SAMA5D35-CM SAMA5D36-CM 4.2.2 Interface Connection  4.2.3 SODIMM200 card edge interface Configuration Items  One jumper for SPI DataFlash chip select connection SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 10 4.2.4 Boot Options Table 4-3 lists the supported boot options Table 4-3. Boot Options Boot Mode Boot Device Type Note BMS OPEN Embedded ROM Boot ROM Boot followed by: Default boot is from embedded ROM - SPI0, NPCS0 - SD/MMC MCI0, MCI1 - NAND Flash - SPI0, NPCS1 - TWI0 - SAM-BA® BMS CLOSE 4.2.4.1 NOR Flash On-board NOR Flash using NCS0 Boot from external NOR Flash memory Boot Configuration In order to use SAM-BA boot, the NAND Flash and SPI DataFlash must be deselected. Pressing the pushbutton PB4 (CS boot disable) disconnects these two components from the system while the ROM Boot is searching for a boot device after reset. A reset can be forced by pressing the PB1 (NRST) pushbutton. Note that PB1 and PB4 pushbuttons are located on the main board (MB). In order to boot from SAM-BA, both PB1 and PB4 should be pressed, then PB1 released while PB4 is kept pressed until SAM-BA boots. SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 11 4.3 Functional Blocks 4.3.1 Processor The CM board is equipped with one Atmel SAMA5D3 ARM-based embedded MPU from the list below:  SAMA5D31  SAMA5D33  SAMA5D34  SAMA5D35  SAMA5D36 The SAMA5D3x devices are packaged in a BGA324-ball BGA package and share an identical footprint. .As different interfaces can be defined using the same pins, the functions available on the evaluation board depend on the actual configuration of the CPU. The Atmel SAMA5D3 series is a high-performance, power-efficient embedded MPU based on the ARM Cortex-A5 processor, achieving 536 MHz with power consumption levels below 0.5 mW in low-power mode. The device features a floating point unit for high-precision computing and accelerated data processing, and a high data bandwidth architecture. It integrates advanced user interface and connectivity peripherals and security features. The SAMA5D3 series features an internal multi-layer bus architecture associated with 39 DMA channels to sustain the high bandwidth required by the processor and the high-speed peripherals. The device offers support for DDR2/LPDDR/LPDDR2 and MLC NAND Flash memory with 24-bit ECC. The comprehensive peripheral set includes an LCD controller with overlays for hardware-accelerated image composition, a touchscreen interface and a CMOS sensor interface. Connectivity peripherals include Gigabit EMAC with IEEE1588, 10/100 EMAC, multiple CAN, UART, SPI and I2C. With its secure boot mechanism, hardware accelerated engines for encryption (AES, TDES) and hash function (SHA), the SAMA5D3 ensures anti-cloning, code protection and secure external data transfers. Refer to Section 4. “CPU Module (CM) Board” on page 7 for details. The processor runs at frequencies up to 536 MHz for the core and up to 166 MHz for the system bus. 4.3.2 Clock Circuitry The CM board includes three clock sources:  Two clocks are alternatives for the SAMA5D3 series processor main clock  One crystal oscillator is used for the Ethernet RGMII chip Table 4-4. Quantity 4.3.3 Main Components Associated with the Clock Systems Component Assignment Description 1 Crystal for internal clock, 12 MHz Y1 1 Crystal for RTC clock, 32.768 kHz Y2 1 Oscillator for ethernet clock RGMII, 25 MHz Y3 Reset Circuitry The reset sources for the CM board are:  Power-on reset  Pushbutton reset (Pushbutton is equipped on main board)  JTAG reset from an in-circuit emulator (MB features an on-board JTAG interface) SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 12 4.3.4 Power Supplies The CM board is driven by +3.3V input power rail from the MB through the SODIMM200 connector. The CM board embeds all necessary power rails required for the microprocessor. When additional voltages are required, they are generated on-board from the 3.3V supply (power source is a linear regulator or a switching regulator). The detailed power supply requirements for given modules are specified within the corresponding product documentation. Table 4-5 summarizes the power specifications. Table 4-5. Supply Group Configuration Nominal Name Powers Component 3.0V VDDBU the Slow Clock oscillator, the internal 32K RC, the internal 12M RC and a part of the System Controller From VBAT 3V, SODIMM200 connector 3.3V VDDIOP0 a part of peripheral I/O lines From main 3.3V, SODIMM200 connector 3.3V VDDIOP1 a part of peripheral I/O lines From main 3.3V, SODIMM200 connector 3.3V VDDUTMII the USB device and host UTMI + interface From main 3.3V, SODIMM200 connector 3.3V VDDOSC the main oscillator cells From main 3.3V, SODIMM200 connector 3.3V VDDANA the analog-to-digital converter From main 3.3V, SODIMM200 connector 1.2V VDDCORE the core, including the processor, the embedded memories and the peripherals Regulator on-board 1.2V VDDUTMIC the USB device and host UTMI + core Regulator on-board 1.2V VDDPLLA the PLLA cell Regulator on-board 1.8V VDDIODDR DDR2 interface I/O lines Regulator on-board 1.8V VDDIOM NAND, NOR Flash and SMC interface I/O lines Regulator on-board ADVREF ADC reference voltage From ADVREF, SODIMM200 connector VDDFUSE Fuse box for programming Regulator on-board 3.0V to 3.3V 2.5V SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 13 Embest/Flextronics Power Supply L1 180ohm at 100MHz 1 2 VCC_3V3 VCC_1V2 TDI TP3 SMD TMS TP4 SMD C2 100nF L2 180ohm at 100MHz 1 2 MN15 6 C131 100nF C0603 C134 R46 10uF 23.7K 1% C0805 R0402 TP7 SMD VDDBU R51 47K 1% R0402 VDDIOP0 BMS {7} {7} WKUP SHDN TDI TMS TCK TDO NTRST NRST VDDIOP0 VDDBU WKUP SHDN C8 100nF C3 100nF C4 100nF C9 100nF C10 100nF C5 100nF U15 U9 R8 10K R6 R7 100K 100K T10 T12 JTAGSEL TDI TMS TCK TDO NTRST NRST 1 2 U8 C31 20pF C5 C7 D14 T7 T15 U17 V7 VDDIOM_1 VDDIOM_2 VDDIODDR_1 VDDIODDR_2 VDDIODDR_3 VDDIODDR_4 VDDIODDR_5 TST BMS P12 T16 C17 100nF D13 F14 G10 G13 H11 VDDFUSE C23 100nF C20 100nF R38 200K 1% R0402 VCC_3V3 RT8010GQW VIN LX 3 C13 22pF C0402 10uF C25 C0805 6 FB WDFN-6L_2X2 EN 2 PWR_EN PWR_EN {7} R49 DNP R0402 C21 100nF C24 100nF VCC_3V3 C29 100nF VDDOSC U13 TP16 SMD V13 HHSDMA HHSDPA L5 10uH/150mA L6 C33 100nF 1R C38 4.7uF C37 4.7uF TP18 SMD L7 10uH/150mA VCC_3V3 GNDUTMI C41 100nF R16 1R GNDANA GNDUTMI_1 C35 100nF R11 ADVREF ADVREF L5 TP19 SMD C42 4.7uF C43 100nF MN14 XC6206P251MR-G Voltage Detector L4 GNDIOM_1 GNDIOM_2 J11 T17 R12 GNDIOP_1 GNDIOP_2 GNDIOP_3 GNDIOP_4 VCC_3V3 TP17 SMD C34 100nF R111 0R C40 100nF J7 N11 U7 E5 GNDIODDR_1 GNDIODDR_2 GNDIODDR_3 GNDIODDR_4 GNDIODDR_5 HHSDMC HHSDPC GNDCORE_1 GNDCORE_2 GNDCORE_3 GNDCORE_4 GNDCORE_5 GNDCORE_6 VDDANA L6 10uH/150mA VDDOSC VCC_1V2 R10 VDDANA HHSDMB HHSDPB VBG VDDPLLA R10 C39 100nF E14 F10 F13 F15 H14 R19 C44 5.62K 1% 10pF U11 VCC_1V2 VDDUTMIC A16 C9 N13 T8 T14 V17 V14 U14 R11 SUP1 VDDUTMII DIBN DIBP GNDOSC GNDFUSE HHSDMC HHSDPC V10 U10 V12 U12 C130 10uF C0805 1R GNDPLL U6 V6 4 R3 C32 100nF GNDBU {7} {7} PWR_EN R44 DNP R0402 VCC_3V3 C19 100nF XOUT32 T11 P4 HHSDMA HHSDPA HHSDMB HHSDPB 2 XOUT XIN32 T13 {7} {7} VDDOSC 32.768 kHz DIBN DIBP {7} {7} 5 3D16-2 R39 100K 1% R0402 C28 100nF VDDPLLA V16 MN16 2.2uH L15 C18 100nF XIN P10 20pF U16 2 C36 EN WKUP SHDN MN2H SAMA5D3x_BGA324 Y2 {7} {7} V8 4 TP15 SMD 20pF 3 SHDN C30 VDDIODDR C128 100nF C0603 VDDIOM 20pF 1 TP14 SMD NC VCC_3V3 TP12 SMD Y1 12MHz WKUP ADJ C132 10uF VCC_3V3 FUSE_2V5 C27 PGOOD 7 VCC_3V3 3 4 SOP_8__50_154X193_69 C15 4.7uF TP11 SMD VDDCORE_1 VDDCORE_2 VDDCORE_3 VDDCORE_4 VDDCORE_5 VDDCORE_6 VDDCORE_7 {7} T9 R8 N10 P9 M11 P11 V9 G7 V11 R4 DNP VDDIOP0_1 VDDIOP0_2 RR1A RR1B RR1C RR1D JTAGSEL TDI TMS TCK TDO NTRST NRST C7 100nF C12 100nF 1 R40 100K 1% R0402 VIN VDD VDDBU 1 2 3 4 {7} {7} {7} {7} {7} {7} {3,6,7} C11 100nF VDDIOP1_1 VDDIOP1_2 TP10 SMD NRST C6 100nF VDDIOP0 V15 TP9 SMD TP6 SMD L11 M4 TDO TP8 SMD VDDBU TP5 SMD 8 100K 7 100K 6 100K 5 100K TCK C14 10nF C0402 RT9018B-18GSP VOUT 9 8 C1 100nF TP2 SMD NC PAD GND NTRST GND(PAD) GND TP1 SMD VDDIOP1 1 7 5 Figure 4-4. FUSE_2V5 VCC_3V3 2 R109 0R C121 1uF 1 Vo Vin 3 Vss GNDUTMI C127 1uF GNDUTMI DNP CA89405MF GNDUTMI SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 14 Figure 4-5. Ronetix Power Supply Soft-Start Time Typ 100 us EN Input High Threshold EN Input Low Threshold Min Max 1.2 V 0.4 V SEE TABLE 1 VDD_CORE 3V3 U1 1 VIN 2 GND 3 EN LX L1 5 3V3 LQM2HPN1R0MG0L C3 22u/6V3 GND 0402 R1 100k GND VOUT 0402 POWER_ENABLE GND 10k/1% 10n/25V 2;3 RS1 2k49/1% RS2 C5 0402 SC189ASKTRT 1V0 C4 22u/6V3 RS1 4 SEE TABLE 1 GND pins are provided and should be GND VDDIODDR 3V3 U2 1 VIN 2 GND 3 EN LX L2 5 LQM2HPN1R0MG0L C6 22u/6V3 GND GND VOUT R3 5k1/1% 4 22u/6V3 0402 GND C8 R2 6k34/1% 0402 SC189ASKTRT 1V0 C7 10n/25V GND VDD_CORE 0603 VDD_PLL 3V3 US1 C9 R4 0R DNP 1 VIN 2 GND 3 STBY VOUT 5 NC 4 C10 1uF/10V 1uF/10V GND GND BU12TD3WG-TR OR BU10TD3WG-TR Start Time Typ 50 EN Input High Threshold EN Input Low Threshold Min Max 1.2 V 0.3 V us C11 10n/25V SEE TABLE 1 GND GND SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 15 Figure 4-6. Ronetix Power Supply (Continued) (3V3) VDD_IOM VDD_IOP0 VDD_IOP1 VDD_CORE U3-A C12 100n/10V T16 C13 100n/10V P12 VDDIOM VDDIOM VDDCORE VDDCORE J11 GNDIOM GNDIOM VDDCORE VDDCORE VDDCORE VDDCORE T17 C20 C22 100n/10V 100n/10V V11 G7 VDDIOP0 VDDIOP0 VDDCORE C21 100n/10V M4 C24 100n/10V L11 VDDIOP1 VDDIOP1 GNDCORE GNDCORE GNDIOP GNDIOP GNDCORE GNDCORE GNDCORE GNDCORE U7 N11 J7 GND Vbat C25 VDD_ANA 100n/10V E5 V15 T13 VDDBU GNDBU L6 L4 VDDANA GNDANA R3 P4 VDDFUSE GNDFUSE R10 P10 VDDPLLA GND L3 top/bot BLM15AG121SN1D C33 C32 VDDFUSE 470p/50V C31 4u7/6V3/X5R GNDIOP GNDIOP 0603 R9 470n/16V/Y5V 0R GND AGND VDD_PLL top/bot top/bot VDD_PLL L5 BLM15AG121SN1D C39 470p/50V C37 4u7/6V3/X5R V13 U13 R12 C105 100n/10V C14 100n/10V C16 C15 100n/10V 100n/10V T15 C18 100n/10V U17 V7 T7 C17 C19 C23 100n/10V 100n/10V 100n/10V C9 GND N13 T8 T14 GND V17 A16 VDDIODDR VDDIODDR VDDIODDR D13 C26 100n/10V F14 C28 100n/10V VDDIODDR VDDIODDR VDDIODDR G10 G13 H11 C27 C30 C29 100n/10V 100n/10V 100n/10V GNDIODDR GNDIODDR GNDIODDR GNDIODDR GNDIODDR E14 VDDOSC GNDOSC U11 T11 GND F10 F13 F15 H14 GND GNDPLL VDDUTMIC VDDUTMII GNDUTMI ADVREF top/bot 3V3 BLM15AG121SN1D C36 4u7/6V3/X5R L5 C35 SAMA5D3x 470n/16V/Y5V ADVREF UTMI_GND A cooper for UTMI_GND net cover all USB Components GND L4 470p/50V C34 C38 470n/16V/Y5V 3V3 GND top/bot C5 C7 D14 L6 2;4 GND C40 100n/10V GND BLM15AG121SN1D R57 C41 4u7/6V3/X5R 0603 C43 470p/50V C42 0R UTMI_GND GND 470n/16V/Y5V UTMI_GND SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 16 4.3.5 Memory 4.3.5.1 Memory Organization The SAMA5D3 series processor features a DDR/SDR memory interface and an External Bus Interface (EBI) to interface to a wide range of external memories and to almost any kind of parallel peripheral. 4.3.5.2 Resource Allocation This section describes the memory devices that equip the SAMA5D3 series CM board.  Figure 4-7. Two SDRAM/DDR2 are used as main system memory. MT47H128M16 - 2 Gb - 16 Meg x 16 x 8 banks, the board provides up to 2 Gb of on-board, soldered DDR2 SDRAM. The memory bus is 32 bits wide and operates at up to 166 MHz. Embest/Flextronics DDR2 Memory {3} DDR_D[0..31] {3} DDR_A[0..13] MN8 {3} {3} {3} DDR_BA0 DDR_BA1 DDR_BA2 {3} DDR_CKE {3} {3} DDR_CLK DDR_CLKN {3} DDR_CS {3} {3} DDR_CAS DDR_RAS {3} DDR_WE {3} DDR_DQS1 DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 R8 DDR_BA0 DDR_BA1 DDR_BA2 L2 L3 L1 VDDIODDR R93 DNP R94 0R DDR_CKE K9 K2 DDR_CLK DDR_CLKN J8 K8 DDR_CS L8 DDR_CAS DDR_RAS L7 K7 DDR_WE K3 B7 A8 A0 DDR2 SDRAM A1 A2 MT47H128M16RT A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 BA0 BA1 BA2 ODT DDR_DQS0 {3} {3} DDR_DQM1 DDR_DQM0 F7 E8 VDD VDD VDD VDD VDD VDDL CK CK CS CAS RAS WE VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VREF UDQS UDQS LDQS LDQS VSS VSS VSS VSS VSS R99 4.7K B3 F3 A2 E2 R3 R7 UDM LDM RFU1 RFU2 RFU3 RFU4 G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9 MN9 DDR2 SDRAM DDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15 VDDIODDR CKE R98 4.7K {3} DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSDL A1 E1 J9 M9 R1 C53 C55 C57 C59 C61 J1 A3 E3 J3 N1 P9 100nF 100nF 100nF 100nF 100nF C65 C67 C69 C71 C73 C75 C77 C79 C81 C83 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 R8 DDR_BA0 DDR_BA1 DDR_BA2 L2 L3 L1 R91 DNP R92 C63 100nF A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 J2 VDDIODDR DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF K9 A0 DDR2 SDRAM A1 A2 MT47H128M16RT A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 BA0 BA1 BA2 ODT 0R DDR_CKE K2 DDR_CLK DDR_CLKN J8 K8 DDR_CS L8 DDR_CAS DDR_RAS L7 K7 DDR_WE K3 VDDL CK CK CS CAS RAS B7 A8 DDR_DQS3 WE C85 100nF R100 4.7K {3} DDR_DQS2 {3} {3} DDR_DQM3 DDR_DQM2 F7 E8 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VREF UDQS UDQS LDQS LDQS VSS VSS VSS VSS VSS R101 4.7K A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 J7 B3 F3 A2 E2 R3 R7 UDM LDM RFU1 RFU2 RFU3 RFU4 G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9 DDR_D16 DDR_D17 DDR_D18 DDR_D19 DDR_D20 DDR_D21 DDR_D22 DDR_D23 DDR_D24 DDR_D25 DDR_D26 DDR_D27 DDR_D28 DDR_D29 DDR_D30 DDR_D31 VDDIODDR VDD VDD VDD VDD VDD CKE DDR_VREF {3} DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSDL A1 E1 J9 M9 R1 C54 C56 C58 C60 C62 J1 C64 100nF A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 J2 100nF 100nF 100nF 100nF 100nF C66 C68 C70 C72 C74 C76 C78 C80 C82 C84 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF DDR_VREF A3 E3 J3 N1 P9 C86 100nF A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 J7 VDDIODDR L8 10uH/150mA C87 4.7uF R64 1R C88 100nF R65 1.5K 1% DDR_VREF C89 4.7uF C90 100nF TP22 SMD DDR_VREF {3} R66 1.5K 1% SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 17 Ronetix DDR2 Memory Address and control traces may not exceed 1.3 inches (33.0 mm). Address and control traces must be length-matched to within 0.1 inch (2.54 mm). Address and control traces must match the data group trace lengths to within 0.25 inches (6.35 mm). DDR_ADDR U3-H From MT47H64M16HR-25H to MT47H128M16RT-3:C DDR_A3 A9 DDR_A2 D11 DDR_A3 DDR_A4 DDR_A5 B9 DDR_A4 E10 DDR_A5 DDR_A6 D10 DDR_A6 DDR_ADDR DDR_A7 A8 DDR_A7 C10 DDR_A8 DDR_A[0-13] DDR_A8 DDR_A9 DDR_A10 B8 DDR_A9 F11 DDR_A10 DDR_A11 DDR_A12 A7 DDR_A11 D9 DDR_A12 A6 DDR_A13 H12 H17 H13 G17 G16 H15 F17 G15 F16 E17 G14 E16 D17 C18 D16 C17 B16 B18 C15 A18 C16 C14 DDR_A13 DDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15 DDR_D16 DDR_D17 DDR_D18 DDR_D19 DDR_D20 DDR_D21 DDR_D22 group 3AB DDR_DATA DDR_A0 DDR_A1 M8 M3 A0 A1 DDR_A2 DDR_A3 M7 DDR_D[0-31] DDR_A4 N8 DDR_D0 DDR_A5 N3 DDR_D1 DDR_A6 N7 DDR_D2 DDR_A7 P2 DDR_D3 DDR_A8 P8 DDR_D4 DDR_A9 P3 DDR_D5 DDR_A10 DDR_A11 DDR_A12 DDR_A13 M2 N2 DDR_CKE R8 DDR_A8 P8 DDR_A9 P3 DDR_A10 DDR_A11 DDR_A12 DDR_A13 M2 VDDIODDR R50 0R 0402 R51 CS# UDM B3 DDR_DQM1 5 ODT NC A2 K2 CKE CK NC E2 CK# VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ R1 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 VDDL J1 VREF J2 DNP 5 J8 K8 DDR_CK DDR_CK# group 1AB DDR_DQM2 5 DDR_DQM3 D12 DDR_DQM3 5 E7 DDR_DQS0 DDR_DQS1 E18 DDR_DQS0 F2 DDR_DQS1 DDR_DQS2 5 5 F8 H2 H8 J7 5 5 5 DDR_CALP E13 DDR_VREF C13 A1 100n/10V VDDIODDR R52 C48 C49 100n/10V A2 A3 DQ2 DQ3 H7 DQ4 H3 H1 DDR_D18 DDR_D19 DQ5 H9 R7 A4 A5 A6 A7 A8 A9 A10 A11 A12 RFU(A13) RFU RFU P7 R2 R8 5 DDR_BA0 L2 BA0 5 DDR_BA1 L3 BA1 5 DDR_BA2 L1 BA2 DDR_CK DDR_CK# LDQS F7 DQ12 DQ13 DQ14 LDQS#/NU 0R E8 DDR_DQS2 R70 0402 B7 WE# L7 CAS# K7 RAS# LDM F3 DDR_DQM2 5 5 DDR_CS# L8 CS# UDM B3 DDR_DQM3 5 K9 ODT NC A2 K2 CKE CK NC E2 CK# VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ R1 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 VDDL J1 VREF J2 DNP 0R 5 5 J8 K8 DDR_CK DDR_CK# 100n/10V J3 N1 group 1AB 100n/10V P9 100n/10V A7 B2 100n/10V C79 100n/10V 100n/10V B8 D2 C76 100n/10V D8 100n/10V E7 C111 100n/10V F2 100n/10V C112 100n/10V F8 H2 H8 J7 GND VSS VSS VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSDL A1 R71 5 K3 UDQS#/NU A8 5 4k7 DDR_DQS3 DDR_RAS# 100n/10V C108 5 DQ15 C2 D7 D3 D1 D9 B1 B9 DQ11 DDR_CAS# A3 E3 DDR_VREF C8 DQ9 DDR_WE# C53 C57 DQ8 DQ10 DDR_D21 DDR_D22 DDR_D23 DDR_D24 DDR_D25 DDR_D26 DDR_D27 DDR_D28 DDR_D29 DDR_D30 DDR_D31 5 C52 C56 DQ7 DDR_D20 5 100n/10V C77 F1 F9 5 C110 GND DQ6 UDQS 0402 C109 DDR_D16 DDR_D17 N2 B 0402 4k7 GND VDDIODDR C46 100n/10V C47 100n/10V E1 J9 C117 M9 100n/10V C118 100n/10V C50 100n/10V C116 100n/10V C51 100n/10V C114 100n/10V C54 100n/10V C55 C115 100n/10V 100n/10V C58 100n/10V C59 100n/10V C120 100n/10V C113 100n/10V C119 100n/10V DDR_VREF 5 group 1AB GND MT47H128M16RT-3:C GND C61 100n/10V 100n/10V 5 Differential 5 100 ohms GND VDDIODDR 5 GND VDDIODDR L7 R10 200R 5 BLM15AG121SN1D R11 R12 1k5/1% C62 group 1AB 100n/10V top/bot 100n/10V R13 200R 0402 5 0402 DDR_VREF group 1AB 100n/10V C45 M9 5 1R C63 C44 E1 J9 DDR_CKE 5 R53 C60 0402 DDR_CALN C12 VSSDL GND G8 G2 R3 0402 group 1AB 0402 DDR_BA1 DDR_BA2 VSSQ VSSQ VSSQ VSSQ 4k7 group 1AB 0402 5 DDR_BA0 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ 0402 VDDIODDR GND top/bot top/bot B6 F9 VSS VSS VSS VSS VSS R73 DQ0 DQ1 MT47H128M16RT-3:C GND DDR_CS# UDQS#/NU A8 5 K9 D8 5 DDR_DQS1 L8 B8 D2 TP13 5 4k7 DDR_CS# 5 5 B7 0402 5 5 DDR_VREF R72 5 GND DDR_DQS3 DDR_DQS0 E8 DDR_DQM0 0R 0402 F7 F3 5 E9 LDQS LDQS#/NU LDM DDR_DQM2 DDR_WE DQ15 RAS# DDR_DQM0 DDR_DQM1 DDR_BA2 DQ14 CAS# DDR_D31 DDR_BA0 DDR_BA1 DQ13 WE# E11 5 DQ12 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15 K7 B15 5 DQ11 DDR_D10 L7 G12 E15 DDR_WE# DDR_D9 K3 A7 B2 DDR_CAS# DDR_D8 C2 D7 D3 D1 D9 B1 B9 DDR_RAS# P9 DDR_CKE DDR_RAS# C8 DQ9 DDR_CAS# DDR_D30 B5 DQ8 DQ10 DDR_WE# DDR_D29 A5 DQ7 DDR_D7 5 A10 B7 G11 DDR_D6 5 F12 TP12 DDR_D5 F1 F9 5 DDR_D29 DDR_D30 SAMA5D3x P2 H9 UDQS J3 N1 A12 N7 DDR_A7 BA2 DDR_D27 DDR_D28 B12 N3 DDR_A6 BA1 A11 B11 DDR_CS DDR_A5 L1 DDR_D26 DDR_D27 DDR_D28 DDR_CLK DQ5 L3 A3 E3 DDR_CLKN DDR_CKE DDR_RAS DDR_CAS N8 DDR_BA2 DDR_D26 DDR_DQSN3 DDR_A4 DDR_BA1 DDR_D25 A17 A13 C8 DDR_A2 DDR_A3 DDR_D4 5 DDR_D24 F18 DDR_D2 DDR_D3 M7 H3 H1 5 E12 D18 H7 DQ4 BA0 A14 DDR_DQS3 DQ2 DQ3 L2 A15 DDR_DQSN1 DDR_DQSN2 A2 A3 DDR_BA0 DDR_D25 DDR_DQSN0 A0 A1 5 DDR_D24 G18 B17 B13 M8 M3 L3 & L8 DDR_D[16-31] U5 DDR_A0 DDR_A1 DQ6 group 2B DDR_DATA DDR_A[0-13] DDR_D0 DDR_D1 R7 R2 L3 & L8 G8 G2 R3 DDR_D8 DDR_ADDR group 2A DQ0 DQ1 DDR_D10 DDR_D7 P7 DDR_D23 DDR_DQS2 A DDR_D9 DDR_D6 5 minimizing crosstalk with [DQ, DQS, DQM] DDR_D[0-15] A4 A5 A6 A7 A8 A9 A10 A11 A12 RFU(A13) RFU RFU DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15 DDR_D16 DDR_D17 DDR_D18 DDR_D19 DDR_D20 DDR_D21 Zo=50 ohms DDR_DATA DDR_D22 DDR_D23 DDR_DQM1 L3 & L8 U4 D15 B14 DDR_D31 DDR_DQM0 12.09.2012 Chenged U4 and U5 DQS-4w-DQ-3w-DQM-4w-DQS Zo=50 ohms keeping propagation delay equal (between 2A & 2B too) C11 DDR_A1 Data traces may not exceed 1.3 inches (33.0 mm). Data traces must be length-matched to within 0.1 inch (2.54 mm). Data traces must match the data group trace lengths to within 0.25 inches (6.35 mm). DDR_A1 DDR_A2 DDR_A[0-13] Zo=50 ohms B10 DDR_A0 DQS-4w-DQ-3w-DQM-4w-DQS DDR_A0 keeping propagation delay equal (between 2A & 2B too) Figure 4-8. C64 1k5/1% 4u7/6V3/X5R GND R14 GND GND DDR_VREF 5 Keep nets as short as possible, therefore, DDR2 devices have to be placed close as possible of MIURA. The layout EBI DDR2 should use controlled impedance traces of ZO = 50Ohm characteristic impedance. Trace width = 0.13mm: target 50Ohm impedance. Trace space = 0.30 to 0.38 mm. C65 100n/10V GND  One NAND Flash: NAND is connected to the processor. Maximum size is 256 bytes.  One NOR Flash (optional, not populated): NOR Flash is 16 bits wide. Maximum size is 128 Mbytes. SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 18 Figure 4-9. Embest/Flextronics External Memory MN5 JS28F128P33TF70A FLASH_A1 FLASH_A2 FLASH_A3 FLASH_A4 FLASH_A5 FLASH_A6 FLASH_A7 FLASH_A8 FLASH_A9 FLASH_A10 FLASH_A11 FLASH_A12 FLASH_A13 FLASH_A14 FLASH_A15 FLASH_A16 FLASH_A17 FLASH_A18 FLASH_A19 FLASH_A20 FLASH_A21 FLASH_A22 FLASH_A23 VDDIOM {2,6,7} NRST R27 0R 45 R29 100K 44 R30 100K 15 30 32 14 VDDIOM NRD NWE R31 10K 43 VDDIOM MN6 NL17SZ126 1 {5} OE_Nandflash 2 NCS3 3 OE VCC IN OUT GND VDDIOM 29 25 24 23 22 21 20 19 8 7 6 5 4 3 2 1 55 18 17 16 11 10 9 NCS0 R34 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 CLK DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 WAIT ADV# RFU1 RFU2 NC 34 36 39 41 47 49 51 53 35 37 40 42 48 50 52 54 M_EBI_D0 M_EBI_D1 M_EBI_D2 M_EBI_D3 M_EBI_D4 M_EBI_D5 M_EBI_D6 M_EBI_D7 M_EBI_D8 M_EBI_D9 M_EBI_D10 M_EBI_D11 M_EBI_D12 M_EBI_D13 M_EBI_D14 M_EBI_D15 56 46 26 27 13 RST# WP# VDDIOM VCC VCCQ CE# OE# WE# VSS VSS VSS 33 38 C47 100nF 12 28 31 C48 100nF VPP 470K 5 4 C49 100nF MN7 MT29F2G08ABAEAWP VDDIOM VDDIOM NRD R41 NWE R43 NANDCE R45 NANDRDY R48 R50 R52 NANDCLE NANDALE 0R 0R 470K 0R 470K 470K R58 DNP TP13 SMD VCC_3V3 VDDIOM 1 2 L13 180ohm at 100MHz 16 17 8 18 9 7 19 1 2 3 4 5 6 10 11 14 15 20 23 24 35 21 22 38 CLE ALE RE WE CE R/B WP N.C1 N.C2 N.C3 N.C4 N.C5 N.C6 N.C7 N.C8 N.C9 N.C10 N.C11 N.C12 N.C13 N.C14 DNU1 DNU2 DNU3 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8_N.C I/O9_N.C I/O10_N.C I/O11_N.C I/O12_N.C I/O13_N.C I/O14_N.C I/O15_N.C 29 30 31 32 41 42 43 44 26 27 28 33 40 45 46 47 M_EBI_D0 M_EBI_D1 M_EBI_D2 M_EBI_D3 M_EBI_D4 M_EBI_D5 M_EBI_D6 M_EBI_D7 VDDIOM VCC VCC VCC_N.C VCC_N.C VSS VSS VSS_N.C VSS_N.C 12 37 34 39 C51 100nF C52 100nF 13 36 25 48 SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 19 Figure 4-10. Ronetix External Memory U3-G PE1/A1 PE2/A2 PE3/A3 PE4/A4 PE5/A5 PE6/A6 PE7/A7 PE8/A8 PE9/A9 PE10/A10 PE11/A11 PE12/A12 PE13/A13 PE14/A14 PE15/A15/SCK3 PE16/A16/CTS3 PE17/A17/RTS3 PE18/A18/RXD3 PE19/A19/TXD3 R14 R13 A1_NOR A2_NOR V18 P14 A3_NOR A4_NOR U18 A5_NOR 6 6 T18 R15 A6_NOR A7_NOR 6 P17 P15 A8_NOR A9_NOR P18 A10_NOR 6 6 6 D0 E3 DQ0 E# F2 R16 N16 A11_NOR A12_NOR 6 6 W# A13_NOR D3 H4 DQ2 DQ3 G# RP# A5 G2 R17 6 6 H3 E4 DQ1 6 6 D1 D2 N17 R18 A14_NOR A15_NOR D4 D5 H5 E5 N18 P16 A16_NOR A17_NOR D6 D7 H6 E6 M18 N15 M15 M16 N12 PE25/A25/RXD2 PE26/NCS0/TXD2 PE27/NCS1/TIOA2/LCDDAT22 PE30/NWAIT PE31/IRQ/PWML1 NOR FLASH U6 6 6 6 6 6 6 6 A18_NOR 6 6 A19_NOR A20_NOR 6 6 A21_NOR/NAND_ALE A22_NOR/NAND_CLE PE23/A23_NOR/CTS2 PE24/RTS2 PE25/RXD2/1-Wire M14 PE28/NCS2/TIOB2/LCDDAT23 PE29/NWR1(NBS1)/TCLK2 VDD_IOM 6 6 N14 M17 M13 PE24/A24/RTS2 6 6 6 PE26/NCS0/TXD2 M12 PE27/NCS1/TIOA2/LCDDAT22 L13 PE28/NCS2/TIOB2/LCDDAT23 L15 PE29/NWR1(NBS1)/TCLK2 L14 PE30/NWAIT L16 PE31/IRQ/PWML1 6 G3 F4 DQ9 D11 D12 G4 F5 D13 G6 DQ12 DQ13 D14 D15 F6 G7 DQ14 A1_NOR A2_NOR E2 D2 A3_NOR A4_NOR C2 A2 A5_NOR B2 A3 A4 A6_NOR A7_NOR D3 C3 A5 A8_NOR A9_NOR A3 B6 6 2;6;8 2;6 6 2 6 2 2 6 6 2 2 6 6 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 NCS3 NANDRDY NRD NWE(NWR0) D0 B4 D9 D10 2;8 D1 D2 VPP/WP# 6 2;6 K12 R/B# F3 6 6 K15 K14 BYTE# DQ5 DQ6 D8 6 D0 D1 DQ4 6 6 6 6 6 DQ15/A-1 A0 VCCQ A1 A2 VCCQ VCC NC NC D3 6 6 6 6 A10_NOR A6 A8 A9 NC NC 6 6 C6 D6 NC J12 D6 6 6 A11_NOR A12_NOR A10 6 6 A13_NOR B7 A11 A12 NC NC D7 6 6 A14_NOR A15_NOR A7 C7 A13 NC A16_NOR A17_NOR D7 E7 A14 A15 NC NC NC NC D9 D10 J17 D11 J15 J18 D12 D13 H16 H18 D14 D15 6 6 6 6 6 6 6 6 A18_NOR B3 A16 A17 6 6 6 A19_NOR A20_NOR C4 D5 A18 6 6 L12 NAND_CS/NCS3 6 6 L18 L17 NAND_RD/BY NRD_NOR/NAND_OE 6 K11 NWE_NOR/NAND_WE D4 C5 A21_NOR/NAND_ALE A22_NOR/NAND_CLE 6 6 2;6 PE23/A23_NOR/CTS2 B8 0402 22R PE26/NCS0/TXD2 2;6 NWE_NOR/NAND_WE NRD_NOR/NAND_OE NRST 6 6 2;7;8 D8 F1 C66 C68 100n/10V 100n/10V G5 C67 100n/10V GND A6 A7 D4 D5 D8 R16 VDD_IOM K13 K17 J16 J13 100k DQ10 DQ11 K16 K18 J14 R15 B5 F7 A4 DQ7 DQ8 6 6 6 A19 A20 VSS A21 A22 VSS VSS A1 A8 B1 C1 C8 D1 E1 F8 G1 G8 H1 H8 E8 H2 H7 M29W128GL70ZA6E 6 6 EN29GL128H90BAIP GND Alternative component : EN29GL128H90BAIP SAMA5D3x VDD_IOM 0402 NAND FLASH 6 R17 100k U8 16 17 A22_NOR/NAND_CLE A21_NOR/NAND_ALE CLE DQ0 ALE RE# DQ1 DQ2 NRD_NOR/NAND_OE 8 NWE_NOR/NAND_WE NAND_CS_R/NCS3 6 18 9 WE# DQ3 CE# DQ4 DQ5 10 14 NC NC DQ6 DQ7 15 4 NC R19 0R 0402 VDD_IOM 5 6 R23 100k 6 NAND_RD/BY R24 10k 0402 6 6 6 0402 Static Memory Controller and External Bus Interface PE20/A20/SCK2 PE21/A21(NANDALE) PE22/A22(NANDCLE) PE23/A23/CTS2 P13 0402 PE0/A0(NBS0) R22 0R 0402 NAND_WP 29 30 D0 D1 31 D2 32 41 D3 D4 42 43 D5 D6 44 D7 NC NC NC 35 NC NC 11 19 WP# NC 20 21 NC NC VDD_IOM C70 100n/10V 12 C71 100n/10V 37 13 6 6 1 NC RD/BY# 48 6 6 6 2 3 NC 7 39 25 6 6 NC NC 26 34 6 VCC! NC NC VCC! NC VSS! VSS! NC NC VCC VCC 36 VSS VSS 38 DNU NC NC 22 23 24 27 28 33 40 45 NC 46 DNU 47 GND MT29F2G08ABAEAWP-IT HY27UF082G2B-TPCB Alternative component : HY27UF082G2B-TPCB SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 20 4.3.6 Serial Peripheral Interface Controller (SPI) The SAMA5D3 series processor provides two high-speed Serial Peripheral Interface (SPI) controllers. One port is used to interface with the on-board serial DataFlash. Note that the on-board serial DataFlash is enabled through a jumper: JP1 on Embest modules, J1 on Ronetix modules. The jumper must be in place access (and boot) the serial DataFlash. Figure 4-11. Embest/Flextronics Serial DataFlash on SPI VDDIOP1 R67 470K PD11 PD10 PD12 (SPI0_MOSI) R68 (SPI0_MIS0) R69 (SPI0_SPCK) R70 MN10 AT25DF321A 5 2 6 0R 0R 0R 1 SI SO SCK VDDIOP1 VCC WP HOLD CS GND 8 C91 100nF 3 7 4 JP1 (SPI0_NPCS0) VDDIOP1 R71 10K MN11 NL17SZ126 2 OE_Nandflash 1 {3} 1 OE_Dataflash 3 OE VCC IN OUT VDDIOP1 5 4 GND C92 100nF 3 D1 BAT54C 2 PD13 SERIAL DATAFLASH {7} BOOT_CS_OFF Ronetix Serial DataFlash on SPI VDD_IOM VDD_IOM 100n/10V Populate either R25 or J1 /J2/ 10k U9 5 GND VCC 6 2 A NAND_CS/NCS3 Y 4 J2 NAND_CS_R/NCS3 6 HEADER TH 2x1/2mm/90dgr VDD_IOP0 1 OE 3 VDD_IOP0 CS_BOOT_DISABLE 2 SN74LVC1G126DBVT D1 1 2 R26 R25 0R GND 0402 R27 10k VDD_IOP0 GND VCC Y PD10/SPI0_MISO 2;6;9 PD12/SPI0_SPCK R65 0402 22R PD11/SPI0_MOSI 100n/10V 5 2 A 2;6;9 2;6;9 4 VDD_IOP0 U10 DNP 0402 BAT54CWT1G U11 PD13/SPI0_CS0 HEADER SMD 2x1/2mm/90dgr 100k C72 2;6;9 SERIAL FLASH J1 GND 0402 0402 C69 R21 1 2 Figure 4-12. 1 2 CS# VCC SO (SOI) SI (SIO) WP# 5 6 SCK 7 HOLD# 8 3 C73 100n/10V VDD_IOP0 GND 4 AT25DF321A-SH GND 1 OE GND 3 SN74LVC1G126DBVT GND SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 21 4.3.7 1-Wire EEPROM The SAMA5D3 series CM board uses a 1-wire device as a “soft label” to store information such as chip type, manufacture name, production date, etc. Only page 1 is used. Warning: Do not modify the information contained in this page. Pages 2 to n remain free for the user. Figure 4-13. Embest 1-Wire EEPROM VDDIOM R72 1.5K 2 0R IO GND R73 NC1 NC2 NC3 NC4 3 4 5 6 1 PE25 MN12 DS2431P+ 1-WIRE EEPROM Ronetix 1-Wire EEPROM VDD_IOM 1-Wire EEPROM R18 0402 Figure 4-14. 2;6;8 PE25/RXD2/1-Wire R20 1k5/1% 0R 2 0402 1 GND U7 IO GND NC 3 NC 4 5 NC NC 6 DS2431P SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 22 4.3.8 Tri-Speed Ethernet PHY The SAMA5D3 series CM board is equipped with a MICREL PHY device (MICREL KSZ9021/31) operating at 10/100/1000 Mbps. The board supports the RGMII interface mode. The Ethernet interface consists of four pairs of lowvoltage differential pair signals designated from GRX± and GTx± plus control signals for link activity indicators. These signals can be used to connect to a 10/100/1000 Base-T RJ45 connector integrated on the main board. For more information about the Ethernet controller device, refer to the MICREL KSZ89021RN controller manufacturer's datasheet. Figure 4-15. Embest/Flextronics GEthernet ETH0 AVDDL_PLL + C93 10uF AVDDH + C96 10uF C97 10nF C98 10nF R77 27R R78 R79 4.7K 1K R80 R81 R82 27R 27R 27R C99 10nF R83 C101 10nF ETH0_RX2+ ETH0_RX2- C106 10nF 48 47 46 45 44 43 42 41 40 39 38 37 P_GND C105 10nF 1 2 3 4 5 6 7 8 9 10 11 12 AVDDH TXRXP_A TXRXM_A AVDDL TXRXP_B TXRXM_B TXRXP_C TXRXM_C AVDDL TXRXP_D TXRXM_D AVDDH KSZ9021RN ISET AVDDH XI XO AVDDL_PLL LDO_O RESET_N CLK125_NDO DVDDH DVDDL INT_N MDIO 49 {7} {7} C102 10nF + C103 10uF KSZ9021RN 48-pin QFN VDDIOP1 R90 R95 R96 R97 4.7K 4.7K 4.7K 4.7K MDC RX_CLK DVDDH RX_DV RXD0 RXD1 DVDDL VSS RXD2 RXD3 DVDDL TX_EN 36 35 34 33 32 31 30 29 28 27 26 25 R84 R85 GMDC GRXCK PB16 PB11 GRX_CTL GRX0 GRX1 PB13 PB4 PB5 GRX2 GRX3 PB6 PB7 GTX_CTL PB9 27R GTXCK PB8 27R 27R 27R 27R GTX3 GTX2 GTX1 GTX0 PB3 PB2 PB1 PB0 27R 27R R102 27R 3 RR24C 6 27R 4 RR24D 5 27R RR25A RR25B 1 2 R87 8 27R 7 27R 27R 13 14 15 16 17 18 19 20 21 22 23 24 VSS_PS DVDDL LED2 DVDDH LED1 DVDDL TXD0 TXD1 TXD2 TXD3 DVDDL GTX_CLK ETH0_RX1+ ETH0_RX1ETH0_TX2+ ETH0_TX2- PB[0..31] {5,7} G125CK PB18 INT_GETHR PB25 GMDIO PB17 MN17 + C104 10uF {7} {7} {7} {7} VDDIOP1 VDDIOP1 AVDDL ETH0_TX1+ ETH0_TX1- {2,3,7} 4.99K 1% C100 10nF {7} {7} NRST C95 10nF XI XO VDDIOP1 L9 180ohm at 100MHz 1 2 C94 10nF DVDDL VDDIOP1 C110 10nF C111 10nF C112 10nF C113 10nF R88 LED2 LED1 MN13 SC189ASKTRT VCC_3V3 1 C115 10uF 2 3 VIN LX L14 LQM2HPN1R0MG0L C120 10nF GND EN AVDDL_PMOS 5 VOUT 4 C117 10nF RR25C RR25D RR26A RR26B L10 180ohm at 100MHz 1 2 AVDDL_PLL L11 180ohm at 100MHz 1 2 AVDDL L12 180ohm at 100MHz 1 2 DVDDL C114 R32 2K 1% R33 10K 1% 6 5 8 7 C118 22uF + C116 47uF 20pF XI Y3 25MHz 3 {7} {7} 3 4 1 2 1 C109 10nF 2 C108 10nF C119 20pF SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 4 + C107 10uF R89 4.7K XO 23 Figure 4-16. Ronetix GEthernet ETH0 ETH_DVDDL L8 2A ! max 345mA--> BLM21PG221SN1D C74 C128 22u/6V3 22u/6V3 ETH_AVDDL L11 2A ! GND GND max 205mA--> BLM21PG221SN1D C78 ETH_AVDDH VDD_IOP1 C129 22u/6V3 22u/6V3 max ?mA--> GND 2A ! U15 max ?mA--> max 563mA--> C75 1 22u/6V3 22u/6V3 GND GND 2 GND 3 EN 4 VOUT SC189ASKTRT 1V0 GND 10n/25V RS3 2k/1% RS4 10k/1% ETH_AVDDL_PLL 0.5A ! ETH_V1 max 13mA--> BLM15AG121SN1D 0402 C127 ETH_DVDDH L12 L13 L10 5 LX VIN LQM2HPN1R0MG0L C131 0402 L9 BLM21PG221SN1D GND C106 C107 10n/25V 100n/10V GND GND C81 C130 22u/6V3 22u/6V3 GND C92 10u/6V3 GND GND GND GND 2A ! max ?mA--> C132 0402 0402 0402 R28 0402 GND R45 R54 R55 R56 R58 GND RGMII Routing Constraints (Reduced Gigabit Media Independent Interface): The RGMII signals must be length-matched by TX and RX groups. That is, the TX group should be matched within 0.25 inch (6.35 mm), and the RX group should be matched within 0.25 inch (6.35 mm). Total length should not exceed 1.75 inch (44.5 mm). There is no requirement to match the TX and RX groups because their clocks are not related. ETH_DVDDH 22u/6V3 0402 C80 22u/6V3 0402 BLM21PG221SN1D 4k7 2 3 TXD2 22 TXD3 TXRXP_B 5 PB5/GRX1/PWML1 PB6/GRX2/TD1 T4 PB7/GRX3/RK1 24 25 GTX_CLK TX_EN TXRXM_B 6 TXRXP_C 7 top/bot TXRXM_C 8 top/bot PB12/GRXDV/PWMH3 PB13/GRXER/PWML3 PB14/GCRS/CANRX1 PB15/GCOL/CANTX1 PB16/GMDC PB17/GMDIO P5 TXRXP_D TXRXM_D 10 top/bot top/bot R4 U1 R5 R30 0402 22R P3 R29 0402 22R R6 V1 2 PB15/GCOL/CANTX1 PB16/GMDC PB17/GMDIO 2 7 PB28/RXD1 PB29/TXD1 PB30/DRXD PB31/DTXD 4k7 PB20/MCI1_DA0/GTX5 PB21/MCI1_DA1/GTX6 PB22/MCI1_DA2/GTX7 PB23/MCI1_DA3/GRX4 M8 top/bot T5 PB25/SCK1/GRX6 U4 M7 U5 7 4k7 7 7 7 7 7 7 2;7 7 2 R77 0R R60 0402 22R 31 RXD1/MODE1 R61 0402 22R 28 22R 22R 27 35 RXD2/MODE2 RXD3/MODE3 0402 0R 32 RXD0/MODE0 33 PB25/SCK1/GRX6 7 PB18/CLK125_NDO R37 38 top/bot R34 22R RX_DV/CLK125_EN 2 7 PB16/GMDC 7 PB17/GMDIO 22R place close to KSZ9021RN place close to U3 C82 22p/50V top/bot top/bot ETH_DVDDH Y4 2;7 2 N9 V4 PB26/CTS1/GRX7 PB27/RTS1/PWMH1 M9 P8 PB28/RXD1 PB29/TXD1 2 M10 PB30/DRXD R9 PB31/DTXD 2 2 2 100k 2 2;6;8 NRST D2 BAS316 R40 0402 DNP 0R C99 1uF/10V 2 C86 0402 4k99/1% 22p/50V Cl=Cs+[C1xC2]/[C1+C2] GNDif C1=C2 => C1,2=2[Cl-Cs] !!! Cl is load capacitance of the cristal. CS is the stray capacitance on the printed circuit board, typically a value of 5pf can be used for calculation C87 10n/25V C91 10n/25V C90 10n/25V 2 2 ETH0_RX1- 2 ETH0_TX2+ ETH0_TX2- 2 ETH0_RX2+ 2 2 ETH0_RX2- 2 ETH_DVDDH 2 R35 4k7 LED2 15 LED1 17 INT_N CLK125_NDO/LED_MODE 36 37 MDC MDIO AVDDH 1 C84 10n/25V 42 RESET_N AVDDH AVDDH 12 C83 10n/25V 47 C85 10n/25V ETH_AVDDH 46 XI 45 XO 2 2 R36 1k GND ETH_AVDDL R38 CPX32-25.000MHz R39 GND PB24/MCI1_CK/GRX5 LED2/PHYAD1 LED1/PHYAD0 41 48 ISET 16 34 DVDDH 40 DVDDH AVDDL 4 9 AVDDL_PLL LDO_O 44 43 VSS_PS VSS 13 29 P_GND 49 AVDDL ETH_DVDDH 2 2 11 ETH0_TX1+ ETH0_TX1ETH0_RX1+ RX_CLK/PHYAD2 4k7 0402 2;7 DNP 2 2 0402 22R R62 R33 0402 7 GND SAMA5D3x PB7/GRX3 PB11/RX_CLK PB12/RX_DV R75 DNP 7 PB18/CLK125_NDO PB19/MCI1_CDA/GTX4 R32 0402 N8 R31 7 7 R59 R76 0402 PB20/MCI1_DA0/GTX5 PB21/MCI1_DA1/GTX6 PB22/MCI1_DA2/GTX7 PB23/MCI1_DA3/GRX4 PB24/MCI1_CK/GRX5 7 PB13/GRXER/PWML3 PB14/GCRS/CANRX1 T6 7 PB12/RX_DV P7 V2 7 PB4/GRX0 PB5/GRX1 PB6/GRX2 place close to KSZ9021RN 2;7 PB11/RX_CLK PB9/GTXEN 7 2 R7 U3 V5 PB25/SCK1/GRX6 PB26/CTS1/GRX7 PB10/GTXER/RF1 V3 P6 PB18/G125CK PB19/MCI1_CDA/GTX4 PB27/RTS1/PWMH1 PB6/GRX2 PB7/GRX3 PB8/GTX_CLK PB9/GTXEN 7 top/bot top/bot top/bot 0402 PB10/GTXER/RF1 PB11/GRXCK/RD1 0402 22R PB8/GTX_CLK 7 GND PB8/GTXCK/PWMH2 PB9/GTXEN/PWML2 0402 0402 R66 PB1/GTX1 PB2/GTX2 PB3/GTX3 PB4/GRX0 PB5/GRX1 0402 PB3/GTX3/TF1 PB4/GRX0/PWMH1 N6 PB2/GTX2/TK1 22R 22R 0402 ETH_DVDDH 7 7 0402 R68 R67 PB0/GTX0 top/bot 0402 TXRXM_A 21 PB3/GTX3 0402 N7 T3 22R 0402 top/bot TXRXP_A PB2/GTX2 7 0402 R69 4k7 4k7 T2 PB0/GTX0/PWMH0 PB1/GTX1/PWML0 4k7 4k7 4k7 place close to CPU KSZ9021RN TXD1 7 7 U3-D U12 19 20 TXD0 7 PB0/GTX0 PB1/GTX1 C89 C88 ETH_DVDDL C93 C95 10n/25V 10n/25V 14 18 DVDDL DVDDL C94 10n/25V 23 C97 C96 10n/25V 10n/25V 26 30 C98 10n/25V 39 DVDDL DVDDL DVDDL DVDDL 10n/25V 10n/25V ETH_AVDDL_PLL DVDDH GND C121 10n/25V GND GND C122 100n/10V GND GND L14 BLM15AG121SN1D GND SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 24 4.3.9 Indicators There are two LEDs on the SAMA5D3 series CM board that can be controlled by the user. Both are controlled by GPIO lines PE24 and PE25 as shown below. Figure 4-17. Embest/Flextronics LED Indicators VCC_3V3 {3,7} PE[23..31] R74 470R PE25 D2 Blue D3 red R75 100K PE24 1 3 2 R76 470R Q1 IRLML2502 LED Figure 4-18. Ronetix LED Indicators VDD_IOM VDD_IOM LEDS DL2 LED 0603 - BLUE - LTST-C193TBKT-5A DL1 LED 0603 - RED - LTST-C190CKT 0402 R46 1M 0402 0402 R47 200R R49 200R D 2;6 PE24/RTS2 G S Q1 BSS138W-7-F 2;6 PE25/RXD2/1-Wire GND SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 25 4.3.10 SODIMM200 Interface The SAMA5D3 series CM board uses SODIMM200 card edge connector to interface with the MB board. Refer to Section 5.4.22 “SODIMM Card Edge Socket”. 4.3.11 Connectors Figure 4-19 shows the mechanical dimensions of the SAMA5D3 series CM board outline and the mounting holes. Figure 4-19. CPU Module Board Dimensions Holes for mounting screws on carrier board. SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 26 4.4 Embest/Flextronics Schematics This SAMA5D3x-EK CM board manufactured by Embest/Flextronics is available in Revision D and Revision E. In this section, schematics are provided for both revisions. 4.4.1 CPU Module Revision D Schematics This section contains the following schematics:  Block diagram  SAMA5D3x power  SAMA5D3x NOR and NAND  4 Gb DDR2  SAMA5D3x DataFlash, 1-wire, LED  Ethernet  200-pin SODIMM SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 27 5 D 4 S O D I M M PIO PIO PIO CONNECTOR CONNECTOR CONNECTOR B 1 3V3 INPUT D VBAT 128Mb NOR FLASH ANALOG Reference ATMEL SAMA5D3 SERIES ARM CORTEX A5-BASED PROCESSOR USB A,B,C C O N N E C T O R C 2 3 DIB 4Gb DDR2 SDRAM EBI ICE 2Gb NAND FLASH PIO A,...E C PIO A,...E PIO A&D B PIO B&E ONE WIRE EEPROM PIO C SERIAL EEPROM SERIAL DATA FLASH 10/100/1000 FAST ETHERNET A A http://arm.embedinfo.com Title: SAMA5D3x-CM Size: A3 Document Number: BLOCK DIAGRAM Draw By: Zhu Xueliang 5 4 3 2 Rev: D Date: Monday, September 17, 2012 1 Sheet: 1 of 7 4 3 TP1 SMD L1 180ohm at 100MHz 1 2 VDDIOP1 2 1 VCC_3V3 VCC_1V2 C2 100nF L2 180ohm at 100MHz 1 2 D TP3 SMD TMS TP4 SMD C134 R46 10uF 23.7K 1% C0805 R0402 TP7 SMD VDDBU TP5 SMD {7} {7} {7} BMS VDDIOP0 VDDBU WKUP SHDN WKUP SHDN U15 U9 R8 10K R6 R7 100K 100K T10 T12 C8 100nF C3 100nF C4 100nF C9 100nF C10 100nF C5 100nF 1 2 U8 C31 20pF 20pF U16 C5 C7 D14 T7 T15 U17 V7 P12 T16 C17 100nF D13 F14 G10 G13 H11 VDDFUSE U6 V6 DIBN DIBP VDDUTMII XIN32 C19 100nF C23 100nF C20 100nF U11 C21 100nF VDDUTMIC TP16 SMD 2 PWR_EN PWR_EN {7} R49 DNP R0402 VCC_3V3 C29 100nF V13 HHSDMA HHSDPA L5 10uH/150mA L6 TP17 SMD C34 100nF 1R C38 4.7uF C37 4.7uF B TP18 SMD L7 10uH/150mA VCC_3V3 GNDUTMI C41 100nF R16 1R ADVREF GNDANA GNDUTMI_1 C35 100nF R11 ADVREF L5 TP19 SMD C42 4.7uF C43 100nF L4 GNDIOM_1 GNDIOM_2 R12 J11 T17 GNDIOP_1 GNDIOP_2 GNDIOP_3 GNDIOP_4 VCC_3V3 R111 0R C40 100nF J7 N11 U7 E5 E14 F10 F13 F15 H14 GNDCORE_1 GNDCORE_2 GNDCORE_3 GNDCORE_4 GNDCORE_5 GNDCORE_6 HHSDMC HHSDPC GNDIODDR_1 GNDIODDR_2 GNDIODDR_3 GNDIODDR_4 GNDIODDR_5 VDDANA L6 10uH/150mA VDDOSC VCC_1V2 C33 100nF R10 VDDANA HHSDMB HHSDPB VBG VDDPLLA R10 C39 100nF A16 C9 N13 T8 T14 V17 R19 C44 5.62K 1% 10pF EN 10uF C25 C0805 C24 100nF U13 VCC_1V2 DIBN DIBP GNDOSC GNDFUSE R11 FB WDFN-6L_2X2 1R GNDPLL V14 U14 6 3 VDDOSC C32 100nF T11 P4 HHSDMC HHSDPC 3D16-2 C13 22pF C0402 VCC_3V3 VIN VCC_3V3 XOUT32 GNDBU {7} {7} V12 U12 R38 200K 1% R0402 RT8010GQW LX XOUT T13 HHSDMB HHSDPB C130 10uF C0805 R39 100K 1% R0402 C28 100nF VDDOSC P10 {7} {7} V10 U10 4 C18 100nF XIN VDDPLLA V16 MN16 2.2uH L15 R3 B HHSDMA HHSDPA PWR_EN R44 DNP R0402 WKUP SHDN 32.768 kHz 2 Y2 {7} {7} 2 D C VDDIODDR_1 VDDIODDR_2 VDDIODDR_3 VDDIODDR_4 VDDIODDR_5 TST BMS MN2H SAMA5D3x_BGA324 C36 {7} {7} V8 4 TP15 SMD 20pF 3 SHDN C30 VDDIODDR C128 100nF C0603 VDDIOM VDDIOM_1 VDDIOM_2 20pF 1 TP14 SMD EN 5 VCC_3V3 TP11 SMD Y1 12MHz WKUP ADJ C132 10uF VCC_3V3 FUSE_2V5 C27 7 NC VCC_3V3 3 4 SOP_8__50_154X193_69 C15 4.7uF TP12 SMD VDDCORE_1 VDDCORE_2 VDDCORE_3 VDDCORE_4 VDDCORE_5 VDDCORE_6 VDDCORE_7 JTAGSEL TDI TMS TCK TDO NTRST NRST G7 V11 L11 M4 V15 T9 R8 N10 P9 M11 P11 V9 TDI TMS TCK TDO NTRST NRST VDDIOP1_1 VDDIOP1_2 RR1A RR1B RR1C RR1D R4 DNP 1 2 3 4 C JTAGSEL TDI TMS TCK TDO NTRST NRST C7 100nF C12 100nF PGOOD VIN VDD VDDBU 8 100K 7 100K 6 100K 5 100K TP10 SMD {7} {7} {7} {7} {7} {7} {3,6,7} C11 100nF VDDIOP0 VDDIOP0_1 VDDIOP0_2 TP9 SMD NRST TP6 SMD C6 100nF VDDBU TDO TP8 SMD 1 R40 100K 1% R0402 R51 47K 1% R0402 VDDIOP0 TCK C14 10nF C0402 RT9018B-18GSP VOUT NC PAD GND TDI MN15 6 C131 100nF C0603 9 8 C1 100nF TP2 SMD 1 7 5 NTRST GND(PAD) GND 5 SUP1 GNDUTMI GNDUTMI MN14 XC6206P251MR-G Voltage Detector A FUSE_2V5 R109 0R VCC_3V3 2 C121 1uF GNDUTMI A DNP CA89405MF 1 Vo Vin Vss 3 http://arm.embedinfo.com C127 1uF Title: SAMA5D3x-CM Size: A3 Document Number: SAMA5D3x-I&POWER Draw By: Zhu Xueliang 5 4 3 2 Rev: D Date: Friday, September 21, 2012 1 Sheet: 2 of 7 5 4 MN2E SAMA5D3x_BGA324 MN2F SAMA5D3x_BGA324 D C DDR_A[0..13] DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15 DDR_D16 DDR_D17 DDR_D18 DDR_D19 DDR_D20 DDR_D21 DDR_D22 DDR_D23 DDR_D24 DDR_D25 DDR_D26 DDR_D27 DDR_D28 DDR_D29 DDR_D30 DDR_D31 DDR_BA0 DDR_BA1 DDR_BA2 DDR_RAS DDR_CAS DDR_CKE DDR_CLK DDR_CLKN B 3 DDR_CS DDR_WE DDR_DQM0 DDR_DQM1 DDR_DQM2 DDR_DQM3 DDR_DQS0 DDR_DQSN0 DDR_DQS1 DDR_DQSN1 DDR_DQS2 DDR_DQSN2 DDR_DQS3 DDR_DQSN3 B10 C11 A9 D11 B9 E10 D10 A8 C10 B8 F11 A7 D9 A6 DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 H12 H17 H13 G17 G16 H15 F17 G15 F16 E17 G14 E16 D17 C18 D16 C17 B16 B18 C15 A18 C16 C14 D15 B14 A15 A14 E12 A11 B11 F12 A10 E11 DDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15 DDR_D16 DDR_D17 DDR_D18 DDR_D19 DDR_D20 DDR_D21 DDR_D22 DDR_D23 DDR_D24 DDR_D25 DDR_D26 DDR_D27 DDR_D28 DDR_D29 DDR_D30 DDR_D31 DDR_CALN DDR_CALP {4} M_EBI_A0 PE0_A0/NBS0 PE1_A1 PE2_A2 PE3_A3 PE4_A4 PE5_A5 PE6_A6 PE7_A7 PE8_A8 PE9_A9 PE10_A10 PE11_A11 PE12_A12 PE13_A13 PE14_A14 PE15_A15_SCK3 PE16_A16_CTS3 PE17_A17_RTS3 PE18_A18_RXD3 PE19_A19_TXD3 PE20_A20_SCK2 PE21_A21/NANDALE PE22_A22/NANDCLE PE23_A23_CTS2 PE24_A24_RTS2 PE25_A25_RXD2 PE26_NCS0_TXD2 PE27_NCS1_TIOA2 PE28_NCS2_TIOB2 PE29_NWR1/NBS1_TCLK2 PE30_NWAIT PE31_IRQ_PWML1 P13 R14 R13 V18 P14 U18 T18 R15 P17 P15 P18 R16 N16 R17 N17 R18 N18 P16 M18 N15 M15 N14 M17 M13 M16 N12 M14 M12 L13 L15 L14 L16 E9 B6 F9 M_EBI_A21 M_EBI_A22 M_EBI_A23 R20 R21 R22 27R 27R 27R R23 0R R24 R25 R26 R28 0R 0R 0R 0R FLASH_A1 FLASH_A2 FLASH_A3 FLASH_A4 FLASH_A5 FLASH_A6 FLASH_A7 FLASH_A8 FLASH_A9 FLASH_A10 FLASH_A11 FLASH_A12 FLASH_A13 FLASH_A14 FLASH_A15 FLASH_A16 FLASH_A17 FLASH_A18 FLASH_A19 FLASH_A20 FLASH_A21 FLASH_A22 FLASH_A23 PE24 PE25 PE26 PE27 PE28 PE29 PE30 PE31 PE[23..31] {5,7} PE23 NANDCLE NANDALE NCS0 VDDIOM NRST R31 10K 1 NCS3 2 3 OE VCC DDR_DQM0 DDR_DQM1 DDR_DQM2 DDR_DQM3 E18 D18 G18 F18 B17 A17 B13 A13 {4} {4} {4} {4} DDR_DQS0 {4} DDR_DQS1 {4} DDR_DQS2 {4} DDR_DQS3 {4} 100nF C13 DDR_VREF R62 200R 1% 45 R29 100K 44 R30 100K 15 30 32 14 VDDIODDR E13 {4} IN OUT VDDIOM NCS0 R34 CLK DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 WAIT ADV# RFU1 RFU2 NC 34 36 39 41 47 49 51 53 35 37 40 42 48 50 52 54 M_EBI_D0 M_EBI_D1 M_EBI_D2 M_EBI_D3 M_EBI_D4 M_EBI_D5 M_EBI_D6 M_EBI_D7 M_EBI_D8 M_EBI_D9 M_EBI_D10 M_EBI_D11 M_EBI_D12 M_EBI_D13 M_EBI_D14 M_EBI_D15 56 46 26 27 13 C RST# WP# VDDIOM VCC VCCQ CE# OE# WE# VSS VSS VSS 33 38 C47 100nF 12 28 31 C48 100nF VPP 470K 4 C49 100nF GND MN7 MT29F2G08ABAEAWP NRD R41 NWE R43 NANDCE R45 NANDRDY R48 R50 R52 VDDIOM MN2G SAMA5D3x_BGA324 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D16 NCS3 R63 200R 1% 43 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 5 DDR_CS {4} DDR_WE {4} G12 E15 B15 D12 0R VDDIOM {5} OE_Nandflash 29 25 24 23 22 21 20 19 8 7 6 5 4 3 2 1 55 18 17 16 11 10 9 R27 NRD NWE DDR_CKE {4} DDR_CLK {4} DDR_CLKN {4} C8 B5 C12 FLASH_A1 FLASH_A2 FLASH_A3 FLASH_A4 FLASH_A5 FLASH_A6 FLASH_A7 FLASH_A8 FLASH_A9 FLASH_A10 FLASH_A11 FLASH_A12 FLASH_A13 FLASH_A14 FLASH_A15 FLASH_A16 FLASH_A17 FLASH_A18 FLASH_A19 FLASH_A20 FLASH_A21 FLASH_A22 FLASH_A23 VDDIOM DDR_RAS {4} DDR_CAS {4} B7 B12 A12 D MN5 JS28F128P33TF70A {2,6,7} DDR_BA0 {4} DDR_BA1 {4} DDR_BA2 {4} G11 A5 1 TP21 SMD MN6 NL17SZ126 C50 DDR_VREF DDR_D[0..31] {4} 2 NRD NWE_NWR0 NANDRDY K12 K15 K14 K16 K13 K17 J12 K18 J14 J16 J13 J17 J15 J18 H16 H18 M_EBI_D0 M_EBI_D1 M_EBI_D2 M_EBI_D3 M_EBI_D4 M_EBI_D5 M_EBI_D6 M_EBI_D7 M_EBI_D8 M_EBI_D9 M_EBI_D10 M_EBI_D11 M_EBI_D12 M_EBI_D13 M_EBI_D14 M_EBI_D15 L12 NCS3 L17 K11 NRD NWE L18 VDDIOM 16 17 8 18 9 NANDCLE NANDALE 0R 0R 470K 0R 470K 470K 7 19 1 2 3 4 5 6 10 11 14 15 20 23 24 35 21 22 38 R58 DNP TP13 SMD VCC_3V3 VDDIOM 1 2 L13 180ohm at 100MHz CLE ALE RE WE CE R/B WP N.C1 N.C2 N.C3 N.C4 N.C5 N.C6 N.C7 N.C8 N.C9 N.C10 N.C11 N.C12 N.C13 N.C14 DNU1 DNU2 DNU3 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8_N.C I/O9_N.C I/O10_N.C I/O11_N.C I/O12_N.C I/O13_N.C I/O14_N.C I/O15_N.C 29 30 31 32 41 42 43 44 26 27 28 33 40 45 46 47 M_EBI_D0 M_EBI_D1 M_EBI_D2 M_EBI_D3 M_EBI_D4 M_EBI_D5 M_EBI_D6 M_EBI_D7 B VDDIOM VCC VCC VCC_N.C VCC_N.C VSS VSS VSS_N.C VSS_N.C 12 37 34 39 C51 100nF C52 100nF 13 36 25 48 NANDRDY A A http://arm.embedinfo.com Title: SAMA5D3x-CM Size: A3 Document Number: SAMA5D3x-II&NOR&NAND Draw By: Zhu Xueliang 5 4 3 2 Rev: D Date: Wednesday, September 19, 2012 1 Sheet: 3 of 7 5 4 3 2 1 D D {3} DDR_D[0..31] {3} DDR_A[0..13] MN8 {3} {3} {3} DDR_BA0 DDR_BA1 DDR_BA2 DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 R8 DDR_BA0 DDR_BA1 DDR_BA2 L2 L3 L1 VDDIODDR R93 DNP K9 BA0 BA1 BA2 ODT C {3} DDR_CKE {3} {3} DDR_CLK DDR_CLKN {3} DDR_CS {3} {3} DDR_CAS DDR_RAS {3} DDR_WE {3} R94 0R DDR_CKE K2 DDR_CLK DDR_CLKN J8 K8 DDR_CS L8 DDR_CAS DDR_RAS L7 K7 DDR_WE K3 B7 A8 DDR_DQS1 DDR_DQS0 {3} {3} DDR_DQM1 DDR_DQM0 F7 E8 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 VDD VDD VDD VDD VDD VDDL CK CK CS CAS RAS WE VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VREF UDQS UDQS LDQS LDQS VSS VSS VSS VSS VSS R99 4.7K B3 F3 UDM LDM B A2 E2 R3 R7 RFU1 RFU2 RFU3 RFU4 G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9 DDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15 VDDIODDR CKE R98 4.7K {3} MN9 A0 DDR2 SDRAM A1 A2 MT47H128M16RT A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSDL A1 E1 J9 M9 R1 C53 C55 C57 C59 C61 J1 A3 E3 J3 N1 P9 100nF 100nF 100nF 100nF 100nF C65 C67 C69 C71 C73 C75 C77 C79 C81 C83 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 R8 DDR_BA0 DDR_BA1 DDR_BA2 L2 L3 L1 R91 DNP R92 C63 100nF A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 J2 VDDIODDR DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF K9 A0 DDR2 SDRAM A1 A2 MT47H128M16RT A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 BA0 BA1 BA2 ODT 0R DDR_CKE K2 DDR_CLK DDR_CLKN J8 K8 DDR_CS L8 DDR_CAS DDR_RAS L7 K7 DDR_WE K3 VDDL CK CK CS CAS RAS WE {3} DDR_DQS3 C85 100nF R100 4.7K {3} DDR_DQS2 {3} {3} DDR_DQM3 DDR_DQM2 F7 E8 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VREF UDQS UDQS LDQS LDQS VSS VSS VSS VSS VSS R101 4.7K A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 J7 B3 F3 A2 E2 R3 R7 UDM LDM RFU1 RFU2 RFU3 RFU4 G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9 DDR_D16 DDR_D17 DDR_D18 DDR_D19 DDR_D20 DDR_D21 DDR_D22 DDR_D23 DDR_D24 DDR_D25 DDR_D26 DDR_D27 DDR_D28 DDR_D29 DDR_D30 DDR_D31 VDDIODDR VDD VDD VDD VDD VDD CKE DDR_VREF B7 A8 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSDL A1 E1 J9 M9 R1 C54 C56 C58 C60 C62 J1 100nF 100nF 100nF 100nF 100nF C C64 100nF A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 J2 C66 C68 C70 C72 C74 C76 C78 C80 C82 C84 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF DDR_VREF A3 E3 J3 N1 P9 C86 100nF A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 J7 B DDR2 SDRAM VDDIODDR L8 10uH/150mA C87 4.7uF R64 1R C88 100nF R65 1.5K 1% DDR_VREF A C89 4.7uF C90 100nF TP22 SMD DDR_VREF {3} A R66 1.5K 1% http://arm.embedinfo.com Title: SAMA5D3x-CM Size: A3 Document Number: 4Gb DDR2 Draw By: Zhu Xueliang 5 4 3 2 Rev: D Date: Wednesday, September 19, 2012 1 Sheet: 4 of 7 5 4 3 2 1 VDDIOP1 R67 470K C PC0_ETX0 PC1_ETX1 PC2_ERX0 PC3_ERX1 PC4_ETXEN PC5_ECRSDV PC6_ERXER PC7_EREFCK PC8_EMDC PC9_EMDIO PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 D8 A4 E8 A3 A2 F8 B3 G8 B4 F7 A1 D7 C6 E7 B2 F6 B1 E6 C3 D6 C4 D5 C2 G9 C1 H10 H9 D4 H8 G5 D3 E4 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 (SPI0_MOSI) R68 (SPI0_MIS0) R69 (SPI0_SPCK) R70 MN10 AT25DF321A 5 2 6 0R 0R 0R 1 SI SO SCK VDDIOP1 D 8 VCC C91 100nF 3 7 WP HOLD CS 4 GND JP1 VDDIOP1 (SPI0_NPCS0) PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PD11 PD10 PD12 R71 10K MN11 NL17SZ126 {3} OE_Dataflash OE_Nandflash 1 PA0_LCDDAT0 PA1_LCDDAT1 PA2_LCDDAT2 PA3_LCDDAT3 PA4_LCDDAT4 PA5_LCDDAT5 PA6_LCDDAT6 PA7_LCDDAT7 PA8_LCDDAT8 PA9_LCDDAT9 PA10_LCDDAT10 PA11_LCDDAT11 PA12_LCDDAT12 PA13_LCDDAT13 PA14_LCDDAT14 PA15_LCDDAT15 PA16_LCDDAT16 PA17_LCDDAT17 PA18_LCDDAT18 PA19_LCDDAT19 PA20_LCDDAT20 PA21_LCDDAT21 PA22_LCDDAT22 PA23_LCDDAT23 PA24_LCDPWM PA25_LCDDISP PA26_LCDVSYNC PA27_LCDHSYNC PA28_LCDPCK PA29_LCDDEN PA30_TWD0 PA31_TWCK0 E3 F5 D2 F4 D1 J10 G4 J9 F3 J8 E2 K8 F2 G6 E1 H5 H3 H6 H4 H7 H2 J6 G2 J5 F1 J4 G3 J3 G1 K4 H1 K3 PC[0..31] {7} MN2C SAMA5D3x_BGA324 1 2 PA[0..31] {7} MN2A SAMA5D3x_BGA324 PD13 D1 BAT54C 2 3 OE VCC IN OUT SERIAL DATAFLASH VDDIOP1 5 4 C92 100nF GND 3 D C {7} BOOT_CS_OFF VDDIOM B PD[0..31] {7} MN2D SAMA5D3x_BGA324 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 K5 P1 K6 R1 L7 P2 L8 R2 K7 U2 K9 M5 K10 N4 L9 N3 L10 N5 M6 T1 N2 M3 M2 L3 M1 N1 L1 L2 K1 K2 J1 J2 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 R72 1.5K PE25 R73 MN12 DS2431P+ 2 0R IO NC1 NC2 NC3 NC4 3 4 5 6 1 PB0_GTX0 PB1_GTX1 PB2_GTX2 PB3_GTX3 PB4_GRX0 PB5_GRX1 PB6_GRX2 PB7_GRX3 PB8_GTXCK PB9_GTXEN PB10_GTXER PB11_GRXCK PB12_GRXDV PB13_GRXER PB14_GCRS PB15_GCOL PB16_GMDC PB17_GMDIO PB18_G125CK PB19_GTX4 PB20_GTX5 PB21_GTX6 PB22_GTX7 PB23_GRX4 PB24_GRX5 PB25_GRX6 PB26_GRX7 PB27 PB28 PB29 PB30 PB31 T2 N7 T3 N6 P5 T4 R4 U1 R5 P3 R6 V3 P6 V1 R7 U3 P7 V2 V5 T6 N8 U4 M7 U5 M8 T5 N9 V4 M9 P8 M10 R9 GND PB[0..31] {6,7} MN2B SAMA5D3x_BGA324 B 1-WIRE EEPROM VCC_3V3 {3,7} PE[23..31] R74 470R PE25 D2 Blue D3 red R75 100K PE24 1 2 3 R76 470R Q1 IRLML2502 LED A A http://arm.embedinfo.com Title: SAMA5D3x-CM Size: A3 Document Number: SAMA5D3x-III&DATAFLASH&1-WIRE,LED Draw By: Zhu Xueliang 5 4 3 2 Date: Wednesday, September 19, 2012 1 Rev: D Sheet: 5 of 7 5 4 3 2 1 AVDDL_PLL D + C93 10uF L9 180ohm at 100MHz 1 2 AVDDH + C96 10uF C97 10nF C98 10nF R77 27R R78 R79 4.7K 1K R80 R81 R82 27R 27R 27R C99 10nF R83 {7} {7} ETH0_RX2+ ETH0_RX2- C106 10nF 48 47 46 45 44 43 42 41 40 39 38 37 P_GND C105 10nF C102 10nF 1 2 3 4 5 6 7 8 9 10 11 12 AVDDH TXRXP_A TXRXM_A AVDDL TXRXP_B TXRXM_B TXRXP_C TXRXM_C AVDDL TXRXP_D TXRXM_D AVDDH KSZ9021RN ISET AVDDH XI XO AVDDL_PLL LDO_O RESET_N CLK125_NDO DVDDH DVDDL INT_N MDIO 49 ETH0_RX1+ ETH0_RX1ETH0_TX2+ ETH0_TX2- C101 10nF + C103 10uF KSZ9021RN 48-pin QFN VDDIOP1 R90 R95 R96 R97 4.7K 4.7K 4.7K 4.7K MDC RX_CLK DVDDH RX_DV RXD0 RXD1 DVDDL VSS RXD2 RXD3 DVDDL TX_EN 36 35 34 33 32 31 30 29 28 27 26 25 R84 R85 27R 27R GMDC GRXCK PB16 PB11 GRX_CTL GRX0 GRX1 PB13 PB4 PB5 GRX2 GRX3 PB6 PB7 GTX_CTL PB9 27R GTXCK PB8 27R 27R 27R 27R GTX3 GTX2 GTX1 GTX0 PB3 PB2 PB1 PB0 C R102 27R 3 RR24C 6 27R 4 RR24D 5 27R RR25A RR25B 1 2 R87 8 27R 7 27R 27R 13 14 15 16 17 18 19 20 21 22 23 24 VSS_PS DVDDL LED2 DVDDH LED1 DVDDL TXD0 TXD1 TXD2 TXD3 DVDDL GTX_CLK {7} {7} {7} {7} PB[0..31] {5,7} G125CK PB18 INT_GETHR PB25 PB17 GMDIO MN17 + C104 10uF ETH0_TX1+ ETH0_TX1- VDDIOP1 VDDIOP1 AVDDL {7} {7} D {2,3,7} 4.99K 1% C100 10nF C NRST C95 10nF XI XO VDDIOP1 C94 10nF DVDDL VDDIOP1 C110 10nF C111 10nF C112 10nF C113 10nF R88 R89 4.7K 3 4 1 2 B {7} {7} LED2 LED1 MN13 SC189ASKTRT VCC_3V3 1 C115 10uF 2 3 VIN LX L14 LQM2HPN1R0MG0L C120 10nF GND EN AVDDL_PMOS VOUT L10 180ohm at 100MHz 1 2 5 4 6 5 8 7 B AVDDL_PLL C114 R32 2K 1% R33 10K 1% + C116 47uF C118 22uF L11 180ohm at 100MHz 1 2 AVDDL L12 180ohm at 100MHz 1 2 DVDDL 20pF XI Y3 25MHz 3 C117 10nF RR25C RR25D RR26A RR26B C119 A 1 C109 10nF 2 C108 10nF 4 + C107 10uF 20pF XO A http://arm.embedinfo.com Title: SAMA5D3x-CM Size: A3 Document Number: ETHERNET Draw By: Zhu Xueliang 5 4 3 2 Rev: D Date: Friday, September 21, 2012 1 Sheet: 6 of 7 5 4 3 2 VCC_5V 1 VCC_5V J1 {5} PE23 PE24 PE25 PE26 PA[0..31] PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 D VDDIOM PC25 PC23 PC21 PC18 PC16 PC8 PC6 PC4 PC2 PC0 {2} PWR_EN VCC_3V3 PE27 PC10 PC12 PC14 PC27 PC29 PC31 VDDIOP0 PA0 PA2 PA5 PA7 PA9 PA11 PA12 PA14 PA16 PA18 PB[0..31] PB10 PB13 PB14 PB15 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 {5} PA21 PA23 PA25 PA27 PA28 PA30 VDDANA PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 A PD30 PD28 PD26 PD24 PD22 PD20 PD18 PD16 PD14 PC[0..31] B VCC_5V_1 VCC_5V_3 GND1 PE23 PE24 PE25 PE26 VDDIOM_1 PC25 PC23 PC21 GND3 PC18 PC16 PC8 PC6 PC4 PC2 PC0 Enable_0 VCC_5V_2 VCC_5V_4 VBAT PE29 PE30 PE31 GND2 VDDIOM_2 PC24 PC22 PC20 PC19 PC17 PC9 PC7 GND4 PC5 PC3 PC1 Enable_1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 VDDBU PE29 PE30 PE31 PD12 PD10 PD8 PD6 PD5 PD3 PD1 VDDIOP1 PB10 PB14 PB19 PB21 PB23 PB24 {2} {2} HHSDPA HHSDMA {2} {2} HHSDPB HHSDMB {2} {2} HHSDPC HHSDMC {6} {6} {6} {6} ETH0_TX1+ ETH0_TX1ETH0_RX1+ ETH0_RX1- {6} {6} {6} {6} ETH0_TX2+ ETH0_TX2ETH0_RX2+ ETH0_RX2- {6} {6} LED2 LED1 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 C122 1uF VDDIOM PC24 PC22 PC20 PC19 PC17 PC9 PC7 C123 4.7uF D PC5 PC3 PC1 BOOT_CS_OFF {5} KEY C {5,6} 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 VCC_3V3 VCC_3V3_1 VCC_3V3_3 Enable_2 NC1 PE27 PC10 GND5 PC12 PC14 PC27 PC29 PC31 VDDIOP0_1 PA0 PA2 GND7 PA5 PA7 PA9 PA11 PA12 PA14 PA16 PA18 GND9 PA21 PA23 PA25 PA27 PA28 PA30 VDDANA_1 PD30 GND11 PD28 PD26 PD24 PD22 PD20 PD18 PD16 PD14 GND13 PD12 PD10 PD8 PD6 PD5 PD3 PD1 VDDIOP1_1 GND15 PB10 PB14 PB19 PB21 PB23 PB24 GND17 USBA_DP USBA_DM GND18 USBB_DP USBB_DM GND19 USBC_DP USBC_DM GND_ETH1 ETH0_TX1+ ETH0_TX1ETH0_RX1+ ETH0_RX1GND_ETH2 ETH0_TX2+ ETH0_TX2ETH0_RX2+ ETH0_RX2GND23 LED2 LED1 VCC_3V3_2 VCC_3V3_4 Enable_3 ADVREF PE28 PC11 PC13 PC15 PC26 PC28 GND6 PC30 VDDIOP0_2 PA1 PA3 PA4 PA6 PA8 PA10 GND8 PA13 PA15 PA17 PA19 PA20 PA22 PA24 PA26 GND10 PA29 PA31 VDDANA_2 PD31 PD29 PD27 PD25 PD23 GND12 PD21 PD19 PD17 PD15 PD13 PD11 PD9 PD7 GND14 PD4 PD2 PD0 VDDIOP1_2 PB13 PB12 PB15 PB20 PB22 GND16 PB25 PB27 PB29 PB31 PB30 PB26 PB28 GND20 DIBP DIBN GND22 JTAGSEL WKUP SHDN BMS nRST nTRST TDI TCK TMS TDO RTCK GND24 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 C124 10uF PE28 PC11 PC13 PC15 PC26 PC28 PE[23..31] {3,5} PE23 PE24 PE25 PE26 PE27 PE28 PE29 PE30 PE31 ADVREF C125 1uF PC30 PA1 PA3 PA4 PA6 PA8 PA10 VDDIOP0 C PA13 PA15 PA17 PA19 PA20 PA22 PA24 PA26 PA29 PA31 PD[0..31] {5} PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 VDDANA PD31 PD29 PD27 PD25 PD23 C126 1uF PD21 PD19 PD17 PD15 PD13 PD11 PD9 PD7 PD4 PD2 PD0 VDDIOP1 R104 PB15 PB20 PB22 R105 DNP PB13 0R PB12 DIBP DIBN {2} {2} JTAGSEL WKUP SHDN BMS NRST NTRST TDI TCK TMS TDO {2} {2} {2} {2} {2,3,6} {2} {2} {2} {2} {2} PB25 PB27 PB29 PB31 PB30 PB26 PB28 A http://arm.embedinfo.com Title: SODIMM_2 SAMA5D3x-CM Size: A3 Document Number: 200-PIN SODIMM Draw By: Zhu Xueliang 5 4 B 3 2 Rev: D Date: Monday, September 17, 2012 1 Sheet: 7 of 7 4.4.2 CPU Module Revision E Schematics This section contains the following schematics:  Main sheet  SODIMM 200  Power supply  CPU power supply  DDR2 interface  FI: NAND, NOR, Serial, I2C, 1-wire  Ethernet  USB, JTAG, LEDs  Bus interface SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 35 5 D 4 S O D I M M C O N N E C T O R C PIO PIO PIO CONNECTOR CONNECTOR CONNECTOR B 3 2 1 3V3 INPUT D VBAT 128Mb NOR FLASH ANALOG Reference ATMEL ARMA5 PROCESSOR ATSAMA5D3x-CU USB A,B,C DIB 4Gb DDR2 SDRAM EBI ICE 2Gb NAND FLASH PIO A,...E C PIO A,...E PIO A&D B PIO B&E ONE WIRE EEPROM PIO C TWO LED SERIAL DATA FLASH 10/100/1000 FAST ETHERNET A A E D C B A REV SAMA5D3x-CM CW CS CS CS CS MODIF. SCALE DES. 15-Apr-13 28-Sep-12 15-Mar-12 1-Feb-12 11-Nov-11 CW CW CW CW DATE VER. DATE REV. SHEET 1/1 E BLOCK DIAGRAM This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 3 2 1 30-Sep-12 16-Mar-12 3-Feb-12 12-Nov-11 1 7 4 3 TP17 SMD L12 180ohm at 100MHz 1 2 VDDIOP1 2 1 VCC_3V3 VCC_1V2 C73 100nF L11 180ohm at 100MHz 1 2 D TP14 SMD TP8 SMD VDDIOP0 C {7} {7} {7} BMS VDDIOP0 VDDBU W KUP SHDN W KUP SHDN V15 T9 R8 N10 P9 M11 P11 V9 TDI TMS TCK TDO NTRST NRST U15 U9 R15 10K R55 R53 100K 100K T10 T12 VDDBU RR4A 1 RR4B 2 RR4C 3 RR4D 4 JTAGSEL TDI TMS TCK TDO NTRST NRST C79 100nF C52 100nF C80 100nF C82 100nF C81 100nF 1 2 U8 20pF C6 20pF JTAGSEL TDI TMS TCK TDO NTRST NRST U6 V6 DIBN DIBP VDDFUSE C61 100nF VDDUTMII XIN32 D13 F14 G10 G13 H11 C74 100nF C60 100nF C71 100nF C54 100nF U11 VDDUTMIC EN 2 PW R_EN PW R_EN {7} R33 DNP VCC_3V3 C17 100nF U13 TP5 SMD VDDPLLA V13 HHSDMA HHSDPA R16 L6 C90 100nF R21 1R C100 4.7uF C2 4.7uF B TP12 SMD L5 10uH/150mA VCC_3V3 GNDUTMI C16 100nF R25 1R ADVREF GNDANA GNDUTMI_1 TP19 SMD C91 100nF ADVREF L5 TP15 SMD C110 4.7uF C85 100nF L4 GNDIOM_1 GNDIOM_2 J11 T17 R12 GNDIOP_1 GNDIOP_2 GNDIOP_3 GNDIOP_4 VCC_3V3 0R C106 100nF J7 N11 U7 E5 GNDCORE_1 GNDCORE_2 GNDCORE_3 GNDCORE_4 GNDCORE_5 GNDCORE_6 HHSDMC HHSDPC GNDIODDR_1 GNDIODDR_2 GNDIODDR_3 GNDIODDR_4 GNDIODDR_5 VDDANA L10 10uH/150mA VDDOSC VCC_1V2 C3 100nF R17 VDDANA HHSDMB HHSDPB VBG L2 10uH/150mA R10 C66 100nF E14 F10 F13 F15 H14 R52 C62 5.62K 1% 10pF FB VDDOSC VCC_1V2 DIBN DIBP A16 C9 N13 T8 T14 V17 R11 10uF C27 C15 22pF C4 100nF 1R GNDOSC GNDFUSE V14 U14 R28 200K 1% R3 C5 100nF GNDPLL HHSDMC HHSDPC C13 10uF VCC_3V3 3 VCC_3V3 XOUT32 T11 P4 {7} {7} V12 U12 VIN XOUT GNDBU HHSDMB HHSDPB V10 U10 RT8010GQW LX R27 100K 1% C86 100nF VDDOSC T13 {7} {7} PW R_EN R32 DNP MN7 4 6 C51 100nF XIN P10 HHSDMA HHSDPA 2 D WKUP SHDN VDDPLLA V16 2.2uH L6 P12 T16 B {7} {7} 5 C VDDIODDR_1 VDDIODDR_2 VDDIODDR_3 VDDIODDR_4 VDDIODDR_5 TST BMS 32.768 kHz 2 Y1 20pF U16 VDDIODDR C14 100nF VDDIOM VDDIOM_1 VDDIOM_2 MN4H ATSAMA5D3x-CU C8 {7} {7} V8 4 TP18 SMD C10 3 SHDN EN C23 10uF VCC_3V3 TP3 SMD 20pF 1 TP10 SMD NC VCC_3V3 3 4 VCC_3V3 TP1 SMD Y2 12MHz W KUP ADJ R30 100K C101 4.7uF FUSE_2V5 C11 PGOOD VIN VDD VDDBU R54 DNP {7} {7} {7} {7} {7} {7} {3,6,7} C48 100nF 1 NC PAD GND TP4 SMD C46 100nF C75 100nF C5 C7 D14 T7 T15 U17 V7 NRST C72 100nF VDDCORE_1 VDDCORE_2 VDDCORE_3 VDDCORE_4 VDDCORE_5 VDDCORE_6 VDDCORE_7 TP9 SMD C19 10nF RT9018B-18GSP VOUT 7 TP13 SMD C63 100nF G7 V11 TDO TP16 SMD VDDIOP0_1 VDDIOP0_2 TP21 SMD R31 27K 1% R29 47K 1% VDDIOP0 8 100K 7 100K 6 100K 5 100K TCK VDDBU L11 M4 TMS C26 10uF TP2 SMD VDDIOP1_1 VDDIOP1_2 TDI MN8 6 C24 100nF 9 8 C97 100nF TP11 SMD 1 7 5 NTRST GND(PAD) GND 5 SUP1 GNDUTMI GNDUTMI MN11 XC6206P252MR-G Voltage Detector A FUSE_2V5 R51 0R VCC_3V3 2 C89 1uF GNDUTMI A DNP CA89405MF 1 Vo Vin Vss E D C B A 3 C107 1uF REV SAMA5D3x-CM CW CS CS CS CS MODIF. SCALE DES. 15-Apr-13 28-Sep-12 15-Mar-12 1-Feb-12 11-Nov-11 CW CW CW CW DATE VER. DATE REV. SHEET 1/1 E SAMA5D3x-I&POW ER This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 3 2 1 30-Sep-12 16-Mar-12 3-Feb-12 12-Nov-11 2 7 5 4 MN4E ATSAMA5D3x-CU MN4F ATSAMA5D3x-CU D C DDR_A[0..13] DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 DDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15 DDR_D16 DDR_D17 DDR_D18 DDR_D19 DDR_D20 DDR_D21 DDR_D22 DDR_D23 DDR_D24 DDR_D25 DDR_D26 DDR_D27 DDR_D28 DDR_D29 DDR_D30 DDR_D31 DDR_BA0 DDR_BA1 DDR_BA2 DDR_RAS DDR_CAS DDR_CKE DDR_CLK DDR_CLKN B 3 DDR_CS DDR_WE DDR_DQM0 DDR_DQM1 DDR_DQM2 DDR_DQM3 DDR_DQS0 DDR_DQSN0 DDR_DQS1 DDR_DQSN1 DDR_DQS2 DDR_DQSN2 DDR_DQS3 DDR_DQSN3 B10 C11 A9 D11 B9 E10 D10 A8 C10 B8 F11 A7 D9 A6 DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 H12 H17 H13 G17 G16 H15 F17 G15 F16 E17 G14 E16 D17 C18 D16 C17 B16 B18 C15 A18 C16 C14 D15 B14 A15 A14 E12 A11 B11 F12 A10 E11 DDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15 DDR_D16 DDR_D17 DDR_D18 DDR_D19 DDR_D20 DDR_D21 DDR_D22 DDR_D23 DDR_D24 DDR_D25 DDR_D26 DDR_D27 DDR_D28 DDR_D29 DDR_D30 DDR_D31 DDR_CALN DDR_CALP {4} M_EBI_A0 PE0_A0/NBS0 PE1_A1 PE2_A2 PE3_A3 PE4_A4 PE5_A5 PE6_A6 PE7_A7 PE8_A8 PE9_A9 PE10_A10 PE11_A11 PE12_A12 PE13_A13 PE14_A14 PE15_A15_SCK3 PE16_A16_CTS3 PE17_A17_RTS3 PE18_A18_RXD3 PE19_A19_TXD3 PE20_A20_SCK2 PE21_A21/NANDALE PE22_A22/NANDCLE PE23_A23_CTS2 PE24_A24_RTS2 PE25_A25_RXD2 PE26_NCS0_TXD2 PE27_NCS1_TIOA2 PE28_NCS2_TIOB2 PE29_NWR1/NBS1_TCLK2 PE30_NWAIT PE31_IRQ_PWML1 P13 R14 R13 V18 P14 U18 T18 R15 P17 P15 P18 R16 N16 R17 N17 R18 N18 P16 M18 N15 M15 N14 M17 M13 M16 N12 M14 M12 L13 L15 L14 L16 E9 B6 F9 M_EBI_A21 M_EBI_A22 M_EBI_A23 R12 R9 R8 27R 27R 27R R40 0R R7 R10 R11 R41 0R 0R 0R 0R FLASH_A1 FLASH_A2 FLASH_A3 FLASH_A4 FLASH_A5 FLASH_A6 FLASH_A7 FLASH_A8 FLASH_A9 FLASH_A10 FLASH_A11 FLASH_A12 FLASH_A13 FLASH_A14 FLASH_A15 FLASH_A16 FLASH_A17 FLASH_A18 FLASH_A19 FLASH_A20 FLASH_A21 FLASH_A22 FLASH_A23 PE24 PE25 PE26 PE27 PE28 PE29 PE30 PE31 PE[23..31] {5,7} PE23 NANDCLE NANDALE NCS0 VDDIOM NRST R38 10K 1 NCS3 2 3 OE VCC DDR_DQM0 DDR_DQM1 DDR_DQM2 DDR_DQM3 E18 D18 G18 F18 B17 A17 B13 A13 {4} {4} {4} {4} DDR_DQS0 {4} DDR_DQS1 {4} DDR_DQS2 {4} DDR_DQS3 {4} 100nF C13 DDR_VREF R43 200R 1% 45 R36 100K 44 R59 100K 15 30 32 14 VDDIODDR E13 {4} IN OUT VDDIOM NCS0 R37 CLK DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 WAIT ADV# RFU1 RFU2 NC 34 36 39 41 47 49 51 53 35 37 40 42 48 50 52 54 M_EBI_D0 M_EBI_D1 M_EBI_D2 M_EBI_D3 M_EBI_D4 M_EBI_D5 M_EBI_D6 M_EBI_D7 M_EBI_D8 M_EBI_D9 M_EBI_D10 M_EBI_D11 M_EBI_D12 M_EBI_D13 M_EBI_D14 M_EBI_D15 56 46 26 27 13 C RST# WP# VDDIOM VCC VCCQ CE# OE# WE# VSS VSS VSS 33 38 C1 100nF 12 28 31 C12 100nF VPP 470K 4 C32 100nF GND MN3 MT29F2G08ABAEAW P NRD R4 NW E R3 NANDCE R39 NANDRDY R6 R5 R2 VDDIOM MN4G ATSAMA5D3x-CU D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D16 NCS3 R18 200R 1% 43 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 5 DDR_CS {4} DDR_W E {4} G12 E15 B15 D12 0R VDDIOM {5} OE_Nandflash 29 25 24 23 22 21 20 19 8 7 6 5 4 3 2 1 55 18 17 16 11 10 9 R35 NRD NW E DDR_CKE {4} DDR_CLK {4} DDR_CLKN {4} C8 B5 C12 FLASH_A1 FLASH_A2 FLASH_A3 FLASH_A4 FLASH_A5 FLASH_A6 FLASH_A7 FLASH_A8 FLASH_A9 FLASH_A10 FLASH_A11 FLASH_A12 FLASH_A13 FLASH_A14 FLASH_A15 FLASH_A16 FLASH_A17 FLASH_A18 FLASH_A19 FLASH_A20 FLASH_A21 FLASH_A22 FLASH_A23 VDDIOM DDR_RAS {4} DDR_CAS {4} B7 B12 A12 D MN10 JS28F128P33TF70A {2,6,7} DDR_BA0 {4} DDR_BA1 {4} DDR_BA2 {4} G11 A5 1 TP7 SMD MN1 NL17SZ126 C9 DDR_VREF DDR_D[0..31] {4} 2 NRD NWE_NWR0 NANDRDY K12 K15 K14 K16 K13 K17 J12 K18 J14 J16 J13 J17 J15 J18 H16 H18 M_EBI_D0 M_EBI_D1 M_EBI_D2 M_EBI_D3 M_EBI_D4 M_EBI_D5 M_EBI_D6 M_EBI_D7 M_EBI_D8 M_EBI_D9 M_EBI_D10 M_EBI_D11 M_EBI_D12 M_EBI_D13 M_EBI_D14 M_EBI_D15 L12 NCS3 L17 K11 NRD NW E L18 NANDRDY VDDIOM NANDCLE NANDALE 0R 0R 470K 0R 470K 470K R1 DNP TP20 SMD VCC_3V3 VDDIOM 1 2 L1 180ohm at 100MHz 16 17 8 18 9 7 19 1 2 3 4 5 6 10 11 14 15 20 23 24 35 21 22 38 CLE ALE RE WE CE R/B WP N.C1 N.C2 N.C3 N.C4 N.C5 N.C6 N.C7 N.C8 N.C9 N.C10 N.C11 N.C12 N.C13 N.C14 DNU1 DNU2 DNU3 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8_N.C I/O9_N.C I/O10_N.C I/O11_N.C I/O12_N.C I/O13_N.C I/O14_N.C I/O15_N.C 29 30 31 32 41 42 43 44 26 27 28 33 40 45 46 47 M_EBI_D0 M_EBI_D1 M_EBI_D2 M_EBI_D3 M_EBI_D4 M_EBI_D5 M_EBI_D6 M_EBI_D7 B VDDIOM VCC VCC VCC_N.C VCC_N.C VSS VSS VSS_N.C VSS_N.C 12 37 34 39 C34 100nF C33 100nF 13 36 25 48 A A E D C B A REV SAMA5D3x-CM CW CS CS CS CS MODIF. SCALE DES. 15-Apr-13 28-Sep-12 15-Mar-12 1-Feb-12 11-Nov-11 CW CW CW CW DATE VER. DATE REV. SHEET 1/1 E SAMA5D3x-II&NOR&NAND This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 3 2 1 30-Sep-12 16-Mar-12 3-Feb-12 12-Nov-11 3 7 5 4 3 2 1 VDDIOP1 R71 470K C PC0_ETX0 PC1_ETX1 PC2_ERX0 PC3_ERX1 PC4_ETXEN PC5_ECRSDV PC6_ERXER PC7_EREFCK PC8_EMDC PC9_EMDIO PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 D8 A4 E8 A3 A2 F8 B3 G8 B4 F7 A1 D7 C6 E7 B2 F6 B1 E6 C3 D6 C4 D5 C2 G9 C1 H10 H9 D4 H8 G5 D3 E4 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 PD11 PD10 PD12 (SPI0_MOSI) R79 (SPI0_MIS0) R76 (SPI0_SPCK) R77 MN13 AT25DF321A 5 2 6 0R 0R 0R 1 SI SO SCK VDDIOP1 D 8 VCC C114 100nF 3 7 WP HOLD CS 4 GND JP1 VDDIOP1 (SPI0_NPCS0) PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 {7} R78 10K MN12 NL17SZ126 {3} OE_Dataflash OE_Nandflash 1 PA0_LCDDAT0 PA1_LCDDAT1 PA2_LCDDAT2 PA3_LCDDAT3 PA4_LCDDAT4 PA5_LCDDAT5 PA6_LCDDAT6 PA7_LCDDAT7 PA8_LCDDAT8 PA9_LCDDAT9 PA10_LCDDAT10 PA11_LCDDAT11 PA12_LCDDAT12 PA13_LCDDAT13 PA14_LCDDAT14 PA15_LCDDAT15 PA16_LCDDAT16 PA17_LCDDAT17 PA18_LCDDAT18 PA19_LCDDAT19 PA20_LCDDAT20 PA21_LCDDAT21 PA22_LCDDAT22 PA23_LCDDAT23 PA24_LCDPWM PA25_LCDDISP PA26_LCDVSYNC PA27_LCDHSYNC PA28_LCDPCK PA29_LCDDEN PA30_TWD0 PA31_TWCK0 E3 F5 D2 F4 D1 J10 G4 J9 F3 J8 E2 K8 F2 G6 E1 H5 H3 H6 H4 H7 H2 J6 G2 J5 F1 J4 G3 J3 G1 K4 H1 K3 PC[0..31] MN4C ATSAMA5D3x-CU 1 OE SERIAL DATAFLASH VDDIOP1 VCC 5 2 PA[0..31] {7} MN4A ATSAMA5D3x-CU PD13 D3 BAT54C 2 3 IN OUT 4 C123 100nF GND 3 D C {7} BOOT_CS_OFF VDDIOM B PD[0..31] MN4D ATSAMA5D3x-CU PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 K5 P1 K6 R1 L7 P2 L8 R2 K7 U2 K9 M5 K10 N4 L9 N3 L10 N5 M6 T1 N2 M3 M2 L3 M1 N1 L1 L2 K1 K2 J1 J2 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 {7} R70 1.5K PE25 R72 MN14 DS2431P+ 2 0R IO NC1 NC2 NC3 NC4 3 4 5 6 1 PB0_GTX0 PB1_GTX1 PB2_GTX2 PB3_GTX3 PB4_GRX0 PB5_GRX1 PB6_GRX2 PB7_GRX3 PB8_GTXCK PB9_GTXEN PB10_GTXER PB11_GRXCK PB12_GRXDV PB13_GRXER PB14_GCRS PB15_GCOL PB16_GMDC PB17_GMDIO PB18_G125CK PB19_GTX4 PB20_GTX5 PB21_GTX6 PB22_GTX7 PB23_GRX4 PB24_GRX5 PB25_GRX6 PB26_GRX7 PB27 PB28 PB29 PB30 PB31 T2 N7 T3 N6 P5 T4 R4 U1 R5 P3 R6 V3 P6 V1 R7 U3 P7 V2 V5 T6 N8 U4 M7 U5 M8 T5 N9 V4 M9 P8 M10 R9 GND PB[0..31] {6,7} MN4B ATSAMA5D3x-CU B 1-WIRE EEPROM VCC_3V3 {3,7} PE[23..31] R42 470R PE25 D1 Blue D2 red R48 100K PE24 1 2 3 R44 470R Q1 IRLML2502 LED A A E D C B A REV SAMA5D3x-CM CW CS CS CS CS MODIF. SCALE DES. 15-Apr-13 28-Sep-12 15-Mar-12 1-Feb-12 11-Nov-11 CW CW CW CW DATE VER. DATE REV. SHEET 1/1 E SAMA5D3x-III&DATAFLASH&1-W IRE,LED This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 3 2 1 30-Sep-12 16-Mar-12 3-Feb-12 12-Nov-11 4 7 5 4 3 2 1 D D {3} DDR_D[0..31] {3} DDR_A[0..13] MN2 {3} {3} {3} DDR_BA0 DDR_BA1 DDR_BA2 VDDIODDR R50 DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 R8 DDR_BA0 DDR_BA1 DDR_BA2 L2 L3 L1 DNP K9 BA0 BA1 BA2 ODT C R49 {3} DDR_CKE {3} {3} DDR_CLK DDR_CLKN {3} DDR_CS {3} {3} DDR_CAS DDR_RAS {3} DDR_W E {3} 0R DDR_CKE K2 DDR_CLK DDR_CLKN J8 K8 DDR_CS L8 DDR_CAS DDR_RAS L7 K7 DDR_W E K3 B7 A8 DDR_DQS1 DDR_DQS0 {3} {3} DDR_DQM1 DDR_DQM0 F7 E8 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 VDD VDD VDD VDD VDD VDDL CK CK CS CAS RAS WE VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VREF UDQS UDQS LDQS LDQS VSS VSS VSS VSS VSS R46 4.7K B3 F3 UDM LDM B A2 E2 R3 R7 RFU1 RFU2 RFU3 RFU4 G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9 DDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15 VDDIODDR CKE R47 4.7K {3} MN5 A0 DDR2 SDRAM A1 A2 MT47H128M16RT A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSDL A1 E1 J9 M9 R1 C35 C49 C55 C57 C36 J1 A3 E3 J3 N1 P9 100nF 100nF 100nF 100nF 100nF C56 C39 C45 C77 C58 C53 C50 C59 C43 C37 M8 M3 M7 N2 N8 N3 N7 P2 P8 P3 M2 P7 R2 R8 DDR_BA0 DDR_BA1 DDR_BA2 L2 L3 L1 R67 DNP R66 C38 100nF A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 J2 VDDIODDR DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF K9 A0 DDR2 SDRAM A1 A2 MT47H128M16RT A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 BA0 BA1 BA2 ODT 0R DDR_CKE K2 DDR_CLK DDR_CLKN J8 K8 DDR_CS L8 DDR_CAS DDR_RAS L7 K7 DDR_W E K3 VDDL CK CK CS CAS RAS WE {3} DDR_DQS3 C40 100nF R57 {3} DDR_DQS2 {3} {3} DDR_DQM3 DDR_DQM2 F7 E8 R56 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 J7 4.7K VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VREF UDQS UDQS LDQS LDQS VSS VSS VSS VSS VSS 4.7K B3 F3 A2 E2 R3 R7 UDM LDM RFU1 RFU2 RFU3 RFU4 G8 G2 H7 H3 H1 H9 F1 F9 C8 C2 D7 D3 D1 D9 B1 B9 DDR_D16 DDR_D17 DDR_D18 DDR_D19 DDR_D20 DDR_D21 DDR_D22 DDR_D23 DDR_D24 DDR_D25 DDR_D26 DDR_D27 DDR_D28 DDR_D29 DDR_D30 DDR_D31 VDDIODDR VDD VDD VDD VDD VDD CKE DDR_VREF B7 A8 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSDL A1 E1 J9 M9 R1 C87 C84 C68 C92 C44 J1 C C93 100nF A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 J2 100nF 100nF 100nF 100nF 100nF C95 C88 C67 C64 C83 C69 C94 C70 C78 C65 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF DDR_VREF A3 E3 J3 N1 P9 C76 100nF A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 J7 B DDR2 SDRAM VDDIODDR L3 10uH/150mA C7 4.7uF R45 1R C42 100nF R13 1.5K 1% DDR_VREF A C47 4.7uF C41 100nF TP6 SMD DDR_VREF A {3} R14 1.5K 1% E D C B A REV SAMA5D3x-CM CW CS CS CS CS MODIF. SCALE DES. 15-Apr-13 28-Sep-12 15-Mar-12 1-Feb-12 11-Nov-11 CW CW CW CW DATE VER. DATE REV. SHEET 1/1 E 4Gb DDR2 This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 3 2 1 30-Sep-12 16-Mar-12 3-Feb-12 12-Nov-11 5 7 5 4 3 2 1 AVDDL_PLL D + C125 10uF L13 180ohm at 100MHz 1 2 AVDDH + C121 10uF C115 10nF C122 10nF R26 27R R69 R68 4.7K 1K R24 R23 R22 27R 27R 27R C118 10nF R75 {7} {7} ETH0_RX2+ ETH0_RX2- C119 10nF 48 47 46 45 44 43 42 41 40 39 38 37 P_GND C120 10nF C99 10nF 1 2 3 4 5 6 7 8 9 10 11 12 AVDDH TXRXP_A TXRXM_A AVDDL TXRXP_B TXRXM_B TXRXP_C TXRXM_C AVDDL TXRXP_D TXRXM_D AVDDH KSZ9021RNI ISET AVDDH XI XO AVDDL_PLL LDO_O RESET_N CLK125_NDO DVDDH DVDDL INT_N MDIO 49 ETH0_RX1+ ETH0_RX1ETH0_TX2+ ETH0_TX2- C111 10nF + C96 10uF KSZ9021RNI 48-pin QFN VDDIOP1 R64 R63 R58 R61 4.7K 4.7K 4.7K 4.7K MDC RX_CLK DVDDH RX_DV RXD0 RXD1 DVDDL VSS RXD2 RXD3 DVDDL TX_EN 36 35 34 33 32 31 30 29 28 27 26 25 R19 R20 27R 27R GMDC GRXCK PB16 PB11 C RR1C RR1D R65 3 4 27R 6 27R 5 27R GRX_CTL GRX0 GRX1 PB13 PB4 PB5 RR2A RR2B 1 2 8 27R 7 27R GRX2 GRX3 PB6 PB7 GTX_CTL PB9 27R GTXCK PB8 27R 27R 27R 27R GTX3 GTX2 GTX1 GTX0 PB3 PB2 PB1 PB0 R60 27R 13 14 15 16 17 18 19 20 21 22 23 24 VSS_PS DVDDL LED2 DVDDH LED1 DVDDL TXD0 TXD1 TXD2 TXD3 DVDDL GTX_CLK {7} {7} {7} {7} PB[0..31] {5,7} G125CK PB18 INT_GETHR PB25 PB17 GMDIO MN6 + C124 10uF ETH0_TX1+ ETH0_TX1- VDDIOP1 VDDIOP1 AVDDL {7} {7} D {2,3,7} 4.99K 1% C105 10nF C NRST C112 10nF XI XO VDDIOP1 C109 10nF DVDDL VDDIOP1 C116 10nF C102 10nF C108 10nF C98 10nF C104 10nF R62 RR2C RR2D RR3A RR3B B LED2 LED1 MN9 SC189ASKTRT VCC_3V3 1 C25 10uF 2 3 VIN LX L4 LQM2HPN1R0MG0L C113 10nF GND EN AVDDL_PMOS VOUT L8 180ohm at 100MHz 1 2 5 4 6 5 8 7 B C21 AVDDL_PLL 20pF XI Y3 25MHz R73 2K 1% 3 {7} {7} 3 4 1 2 2 R34 4.7K C117 10nF 1 C103 10nF R74 10K 1% + C20 47uF C22 22uF A L9 180ohm at 100MHz 1 2 AVDDL L7 180ohm at 100MHz 1 2 DVDDL C18 4 + C126 10uF 20pF XO A E D C B A REV SAMA5D3x-CM CW CS CS CS CS MODIF. SCALE DES. 15-Apr-13 28-Sep-12 15-Mar-12 1-Feb-12 11-Nov-11 CW CW CW CW DATE VER. DATE REV. SHEET 1/1 E ETHERNET This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 3 2 1 30-Sep-12 16-Mar-12 3-Feb-12 12-Nov-11 6 7 5 4 3 2 VCC_5V 1 VCC_5V J1 {5} PE23 PE24 PE25 PE26 PA[0..31] PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 D VDDIOM PC25 PC23 PC21 PC18 PC16 PC8 PC6 PC4 PC2 PC0 {2} PW R_EN VCC_3V3 PE27 PC10 PC12 PC14 PC27 PC29 PC31 VDDIOP0 PA0 PA2 PA5 PA7 PA9 PA11 PA12 PA14 PA16 PA18 PB[0..31] PB10 PB13 PB14 PB15 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 {5} PA21 PA23 PA25 PA27 PA28 PA30 VDDANA PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 A PD30 PD28 PD26 PD24 PD22 PD20 PD18 PD16 PD14 PC[0..31] B VCC_5V_1 VCC_5V_3 GND1 PE23 PE24 PE25 PE26 VDDIOM_1 PC25 PC23 PC21 GND3 PC18 PC16 PC8 PC6 PC4 PC2 PC0 Enable_0 VCC_5V_2 VCC_5V_4 VBAT PE29 PE30 PE31 GND2 VDDIOM_2 PC24 PC22 PC20 PC19 PC17 PC9 PC7 GND4 PC5 PC3 PC1 Enable_1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 VDDBU PE29 PE30 PE31 PD12 PD10 PD8 PD6 PD5 PD3 PD1 VDDIOP1 PB10 PB14 PB19 PB21 PB23 PB24 {2} {2} HHSDPA HHSDMA {2} {2} HHSDPB HHSDMB {2} {2} HHSDPC HHSDMC {6} {6} {6} {6} ETH0_TX1+ ETH0_TX1ETH0_RX1+ ETH0_RX1- {6} {6} {6} {6} ETH0_TX2+ ETH0_TX2ETH0_RX2+ ETH0_RX2- {6} {6} LED2 LED1 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 C31 1uF VDDIOM PC24 PC22 PC20 PC19 PC17 PC9 PC7 C29 4.7uF D PC5 PC3 PC1 BOOT_CS_OFF {5} KEY C {5,6} 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 VCC_3V3 VCC_3V3_1 VCC_3V3_3 Enable_2 NC1 PE27 PC10 GND5 PC12 PC14 PC27 PC29 PC31 VDDIOP0_1 PA0 PA2 GND7 PA5 PA7 PA9 PA11 PA12 PA14 PA16 PA18 GND9 PA21 PA23 PA25 PA27 PA28 PA30 VDDANA_1 PD30 GND11 PD28 PD26 PD24 PD22 PD20 PD18 PD16 PD14 GND13 PD12 PD10 PD8 PD6 PD5 PD3 PD1 VDDIOP1_1 GND15 PB10 PB14 PB19 PB21 PB23 PB24 GND17 USBA_DP USBA_DM GND18 USBB_DP USBB_DM GND19 USBC_DP USBC_DM GND_ETH1 ETH0_TX1+ ETH0_TX1ETH0_RX1+ ETH0_RX1GND_ETH2 ETH0_TX2+ ETH0_TX2ETH0_RX2+ ETH0_RX2GND23 LED2 LED1 VCC_3V3_2 VCC_3V3_4 Enable_3 ADVREF PE28 PC11 PC13 PC15 PC26 PC28 GND6 PC30 VDDIOP0_2 PA1 PA3 PA4 PA6 PA8 PA10 GND8 PA13 PA15 PA17 PA19 PA20 PA22 PA24 PA26 GND10 PA29 PA31 VDDANA_2 PD31 PD29 PD27 PD25 PD23 GND12 PD21 PD19 PD17 PD15 PD13 PD11 PD9 PD7 GND14 PD4 PD2 PD0 VDDIOP1_2 PB13 PB12 PB15 PB20 PB22 GND16 PB25 PB27 PB29 PB31 PB30 PB26 PB28 GND20 DIBP DIBN GND22 JTAGSEL WKUP SHDN BMS nRST nTRST TDI TCK TMS TDO RTCK GND24 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 C30 10uF PE28 PC11 PC13 PC15 PC26 PC28 PE[23..31] {3,5} PE23 PE24 PE25 PE26 PE27 PE28 PE29 PE30 PE31 ADVREF C127 1uF PC30 PA1 PA3 PA4 PA6 PA8 PA10 VDDIOP0 C PA13 PA15 PA17 PA19 PA20 PA22 PA24 PA26 PA29 PA31 PD[0..31] VDDANA PD31 PD29 PD27 PD25 PD23 C28 1uF PD21 PD19 PD17 PD15 PD13 PD11 PD9 PD7 PD4 PD2 PD0 VDDIOP1 R81 PB15 PB20 PB22 R80 DNP PB13 0R PB12 DIBP DIBN {2} {2} JTAGSEL W KUP SHDN BMS NRST NTRST TDI TCK TMS TDO {2} {2} {2} {2} {2,3,6} {2} {2} {2} {2} {2} {5} PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 PB25 PB27 PB29 PB31 PB30 PB26 PB28 B A E D C B A REV SODIMM_2 SAMA5D3x-CM CW CS CS CS CS MODIF. SCALE DES. 15-Apr-13 28-Sep-12 15-Mar-12 1-Feb-12 11-Nov-11 CW CW CW CW DATE VER. DATE REV. SHEET 1/1 E 200-PIN SODIMM This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 3 2 1 30-Sep-12 16-Mar-12 3-Feb-12 12-Nov-11 7 7 4.5 Ronetix Schematics This section contains the schematics for the CM board manufactured by Ronetix:  Main sheet  SODIMM200  Power supply  CPU power supply  DDR2 interface  FI: NAND, NOR, Serial, I2C, 1-wire  Ethernet  USB, JTAG, LEDs  Bus interface SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 43 1 2 3 4 5 6 SCHEMATICS: SAMA5D3x-CM D D SHEET # SHEET NAME MAIN 2 SODIM200 3 POWER SUPPLY 4 CPU-POWER SUPPLY 5 DDR2 INTERFACE ETHERNET 8 USB/JTAG/LEDS 9 BUS INTERFACE STATUS 15.03.2012 SAMA5D3x-CM v2.0 2.0 OPEN 20.09.2012 SAMA5D3x-CM v2.0 2.0 CLOSE 1. SoDIMM200 change: * PB13 pin 144 with 0R DNP * PB12 pin 146 with 0R populated Fl: NAND/NOR/SERIAL/I2C/1-WIRE 7 REVISION C 6 DESCRIPTION Changes Rev2.0 C 1 DATE: 2. VDD_CORE from 1.20V to 1.25V 3. US1 - From TPS71712DCKR to BU12TD3WG-TR and attribute DNP 4. Replaced Q2 with U15 SC189ASKTRT 1V0 5. Q1 from BSS138W(SOT323) to BSS138(SOT23) 6. C74 - from 47uF Tant to 22uF 0805 Added - C128 22uF 0805 C78 - from 47uF Tant to 22uF 0805 Added - C129 22uF 0805 C81 - from 47uF Tant to 22uF 0805 Added - C130 22uF 0805 C75 - from 47uF Tant to 22uF 0805 Added - C131 22uF 0805 C80 - from 47uF Tant to 22uF 0805 Added - C132 22uF 0805 C92 - from 10u Tant to 10u 0805 7. R4 - Changed attribute Note from DNP to "empty" 8. Y1 changed to CM200C-32.768KDZF-UT 9. U6 changed to EN29GL128H-70BAIP 10. U8 changed to HY27UF082G2B-TPCB B B Mechanical Z5 Z8 Z9 Z10 Drill No plated 1.65mm Drill No plated 1.65mm Drill No plated 1.65mm Drill No plated 1.65mm Z1 Drill No plated 1.8 mm Z2 Drill No plated 1.8 mm Z11 Z12 Z13 Z14 Passer 0.7 mm Passer 0.7 mm Passer 0.7 mm Passer 0.7 mm A A Z6 Drill No plated 0.85mm Z7 Drill No plated 0.85mm Z3 Z4 Drill No plated 3.2 mm Drill No plated 3.2 mm Note: To each Signal Reference have one or more digits. These are the numbers of sheets to which is connected this signal. FILE SAMA5D3x-CM MAIN SAMA5D3x-CM v2.0f.scm SHEET NO SIZE REV DROWN PROJECT TITLE SHEET TITLE A4 1 2 3 DATE 20.9.2012 4 DESCRIPTION FILE ISSUED 5 1 OF 9 development tool www.ronetix.at 6 A B C D CN1 Power Supply 2.5V SODIM200_PCB_PADS 1 A1 3 A2 A3 6;8 PE24/RTS2 PE25/RXD2/1-Wire 9 11 6 PE26/NCS0/TXD2 6 6;8 PC23/SPI1_MOSI PC21/RD0 19 21 A7 A8 A9 A10 A11 23 9 9 9 9 9 9 9 3 PC18/TD0 PC16/TK0 25 27 PC8/EMDC/TCLK5 PC6/ERXER/TIOA5 29 31 PC4/ETXEN/TIOB4 33 PC2/ERX0/TCLK3 PC0/ETX0/TIOA3 35 37 POWER_ENABLE Enable_0 A12 A13 A14 A15 A16 A17 A18 A19 A20 39 3V3 C1 GND Enable_2 9 PC10/MCI2_CDA//LCDDAT20 51 PC12/MCI2_DA1/TIOA1/LCDDAT18 53 55 PC14/MCI2_DA3/TCLK1/LCDDAT16 PC27/SPI1_NPCS2/TWCK1/ISI_D10 57 59 9 9 9 PC29/URXD0/PWMFI2/ISI_D8 61 PC31/FIQ/PWMFI1 63 65 9 PA0/LCDDAT0 PA2/LCDDAT2 VDD_IOP0 9 67 69 71 9 9 9 9 9 9 9 9 PA9/LCDDAT9 PA11/LCDDAT11 PA12/LCDDAT12 PA14/LCDDAT14 PA16/LCDDAT16/ISI_D0 77 79 81 83 85 PA18/LCDDAT18/TWD2/ISI_D2 87 89 91 93 95 9 9 9 9 PA27/LCDHSYNC PA28/LCDPCK PA30/TWD0/URXD1/ISI_VSYNC PD30/AD10 97 99 101 103 105 PD28/AD8 PD26/AD6 PD24/AD4 PD22/AD2 107 109 111 113 115 VDD_ANA 9 9 9 9 9 9 9 9 9 PD20/AD0 PD18/TXD0 PD16/RTS0/SPI0_NPCS3/PWMFI3 PD14/SCK0/SPI0_NPCS1/CANRX0 8 8 USBA_DP USBA_DM 8 8 USBB_DP USBB_DM 8 8 USBC_DP USBC_DM 7 7 7 7 ETH0_TX1+ ETH0_TX1ETH0_RX1+ ETH0_RX1- 7 7 7 7 ETH0_TX2+ ETH0_TX2ETH0_RX2+ ETH0_RX2- 7 7 LED2 LED1 B14 B15 B16 B17 B18 B19 B20 14 16 PE30/NWAIT PE31/IRQ/PWML1 6 VDD_IOM 18 PC24/SPI1_SPCK 20 22 PC22/SPI1_MISO PC20/RF0 24 26 PC19/RK0 PC17/TF0 28 PC9/EMDIO 9 9 9 9 9 30 32 PC7/EREFCK/TIOB5 9 9 34 36 PC5/ECRSDV/TCLK4 PC3/ERX1/TIOA4 9 38 PC1/ETX1/TIOB3 9 6 40 Enable_1 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 B21 B22 A23 B23 A24 B24 A25 B25 A26 B26 A27 B27 A28 B28 A29 B29 A30 B30 A31 B31 A32 B32 A33 B33 A34 B34 A35 B35 A36 B36 A37 B37 A38 B38 A39 B39 A40 B40 A41 B41 A42 B42 A43 B43 A44 B44 A45 B45 A46 B46 A47 B47 A48 B48 A49 B49 A50 B50 A51 B51 A52 B52 A53 B53 A54 B54 A55 B55 A56 B56 A57 B57 A58 B58 A59 B59 A60 B60 A61 B61 A62 B62 A63 B63 A64 B64 A65 B65 A66 B66 A67 B67 A68 B68 A69 B69 A70 B70 A71 B71 A72 B72 A73 B73 A74 B74 A75 B75 A76 B76 A77 B77 A78 B78 A79 B79 A80 B80 A81 B81 A82 B82 A83 B83 A84 B84 A85 B85 A86 B86 A87 B87 A88 B88 A89 B89 A90 B90 A91 B91 A92 B92 A93 B93 A94 B94 A95 B95 A96 B96 A97 B97 A98 B98 A99 B99 A100 B100 42 44 46 C2 Enable_3 CS_BOOT_DISABLE 9 100n/10V GND ADVREF PE28/NCS2/TIOB2/LCDDAT23 48 50 52 PC11/MCI2_DA0//LCDDAT19 PC13/MCI2_DA2/TIOB1/LCDDAT17 54 56 PC15/MCI2_CK/PCK2/LCDDAT21 58 60 PC26/SPI1_NPCS1/TWD1/ISI_D11 PC28/SPI1_NPCS3/PWMFI0/ISI_D9 4 6 9 9 9 9 9 62 PC30/UTXD0//ISI_PCK 64 66 9 VDD_IOP0 68 70 PA1/LCDDAT1 PA3/LCDDAT3 72 PA4/LCDDAT4 PA6/LCDDAT6 9 9 9 74 76 78 80 PA8/LCDDAT8 PA10/LCDDAT10 9 9 82 84 86 88 90 PA13/LCDDAT13 PA15/LCDDAT15 PA17/LCDDAT17/ISI_D1 PA19/LCDDAT19/TWCK2/ISI_D3 PA20/LCDDAT20/PWMH0 9 9 9 9 92 94 96 98 100 PA22/LCDDAT22/PWMH1 PA24/LCDPWM PA26/LCDVSYNC PA29/LCDDEN 102 104 106 108 PA31/TWCK0/UTXD1/SI_HSYNC PD31/AD11 PD29/AD9 PD27/AD7 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 9 9 9 9 9 9 9 VDD_ANA VDDIOP1 R78 R74 9 9 PD25/AD5 PD23/AD3 9 9 9 PD21/AD1 PD19/ADTRG 9 PD17/RXD0 PD15/CTS0/SPI0_NPCS2/CANTX0 PD13/SPI0_CS0 PD11/SPI0_MOSI PD9/MCI0_CK PD7/MCI0_DA6/TCLK0/PWMH3 9 9 9 6;9 6;9 9 9 PD4/MCI0_DA3 PD2/MCI0_DA1 PD0/MCI0_CDA 9 9 9 PB13/GRXER/PWML3 PB12/RX_DV PB15/GCOL/CANTX1 PB20/MCI1_DA0/GTX5 PB22/MCI1_DA2/GTX7 7 7 7 7 7 VDD_IOP1 0R DNP 0R PB25/SCK1/GRX6 PB27/RTS1/PWMH1 PB29/TXD1 PB31/DTXD PB30/DRXD PB26/CTS1/GRX7 PB28/RXD1 7 7 7 7 7 7 7 DIBP DIBN 8 8 JTAGSEL WKUP SHDN BMS NRST NTRST TDI/SWD TCK/SWCLK TMS/SWDIO TDO 8 8 8 8 6;7;8 8 8 8 8 8 RTCK GND MECHANICAL KEYING SODDIM200 : 6 6 5 5 7 7 7 7 7 7 PB10/GTXER/RF1 PB14/GCRS/CANRX1 PB19/MCI1_CDA/GTX4 PB21/MCI1_DA1/GTX6 PB23/MCI1_DA3/GRX4 PB24/MCI1_CK/GRX5 B13 PE29/NWR1(NBS1)/TCLK2 GND SHEET NO SIZE DROWN A4 REV DATE DESCRIPTION FILE 20.9.2012 ISSUED C Power Supply 1.8V -> distance between pin 39 and center notch = 2.70mm 2 OF 9 6 B A 6 SAMA5D3x-CM SHEET TITLE SODIM200 FILE SAMA5D3x-CM v2.0f.scm PROJECT TITLE Power Supply 2.5V -> distance between pin 39 and center notch = 1.80mm development tool www.ronetix.at D 4 VDDIOP1 VDD_IOP1 B11 B12 8 10 12 4 PD12/SPI0_SPCK PD10/SPI0_MISO PD8/MCI0_DA7//PWML3 PD6/MCI0_DA5/TIOB0/PWML2 PD5/MCI0_DA4/TIOA0/PWMH2 PD3/MCI0_DA2 PD1/MCI0_DA0 6;9 6;9 9 9 9 9 9 B8 B9 B10 Vbat 3 73 75 PA21/LCDDAT21/PWML0/ISI_D5 PA23/LCDDAT23/PWML1/ISI_D7 PA25/LCDDISP 9 9 3 PA5/LCDDAT5 PA7/LCDDAT7 B6 B7 VCC 5V 2 47 49 2 PE27/NCS1/TIOA2/LCDDAT22 9 9 A21 A22 43 45 6 B4 B5 VCC 5V 4 6 3V3 41 100n/10V B3 2 1 PC25/SPI1_NPCS0 15 17 1 9 A6 13 VDD_IOM 9 9 A4 A5 B1 B2 0402 PE23/A23_NOR/CTS2 5 7 0402 VCC 5V VCC 5V 1 2 3 Soft-Start Time EN Input High Threshold Typ Min 100 us 1.2 V EN Input Low Threshold Max 0.4 V 3V3 VIN LX TABLE 1 RS1=(Vout-1)xRS2 1.0V 1.2V RS1 0R (JUMP) 2kOhm 1% 2k5ohm 1% 1.25V RS2 DNP 10kOhm 1% 10kOhm 1% US1 BU10TD3WG-TR BU12TD3WG-TR 2k49ohm 1% LQM2HPN1R0MG0L D GND GND 3 EN 0402 2 GND VOUT 0402 C5 0402 SC189ASKTRT 1V0 RS1 2k49/1% RS2 10k/1% 10n/25V POWER_ENABLE C4 22u/6V3 RS1 4 D C3 22u/6V3 2;3 SEE TABLE 1 VDD_CORE 6 L1 5 3V3 R1 100k 5 VDD_CORE U1 1 4 GND SEE TABLE 1 GND VDDIODDR 3V3 U2 1 VIN 2 GND 3 EN LX L2 5 LQM2HPN1R0MG0L C6 22u/6V3 GND R3 5k1/1% 4 GND C8 0402 C SC189ASKTRT 1V0 22u/6V3 0402 C GND VOUT C7 10n/25V R2 6k34/1% 3V3 VDDFUSE U13 MCP1700T-2502E/TT GND 3 In VDD_CORE Out 1 GND 2 C123 C124 1uF/10V 1uF/10V 0603 VDD_PLL 3V3 US1 1 C9 2 R4 0R 3V3 GND GND GND DNP VIN VOUT GND B 50 us 1.2 V EN Input Low Threshold Max 0.3 V VDD_CORE VDDIODDR TP3 VDDIODDR VDD_IOP0 TP4 VDD_IOP0 VDD_IOP1 TP5 STBY NC 4 VDD_IOP1 VDD_IOM TP6 GND BU12TD3WG-TR VDD_IOM VDD_ANA TP7 VDD_ANA TP8 GND TP9 POWER_ENABLE C11 10n/25V B 3 OR BU10TD3WG-TR Typ Min VDD_CORE 5 1uF/10V Start Time EN Input High Threshold 3V3 TP2 C10 1uF/10V GND TP1 SEE TABLE 1 GND GND GND POWER_ENABLE 2;3 VDD_IOP0 VDD_IOP1 3V3 R5 R6 SODIM200 (65-66) 0R SODIM200 (141-142) 0603 R7 GND pins are provided and should be connected as shortly as possible to the system ground plane. 0R SODIM200 (15-16) 0603 R8 A Close to SODIM200 VDD_ANA 0R 0603 A VDD_IOM 0R SODIM200 (103-104) 0603 FILE SAMA5D3x-CM POWER SUPPLY SAMA5D3x-CM v2.0f.scm SHEET NO SIZE REV DROWN PROJECT TITLE SHEET TITLE A4 1 2 3 DATE 20.9.2012 4 DESCRIPTION FILE ISSUED 5 3 OF 9 development tool www.ronetix.at 6 1 2 3 4 5 6 2;4 ADVREF TP10ADVREF TP11GND GND VDD_IOP0 VDD_IOP1 D D (3V3) VDD_IOM VDD_CORE U3-A C12 C13 100n/10V 100n/10V VDDIOM VDDIOM T17 J11 GNDIOM GNDIOM VDDIOP0 VDDIOP0 VDDIOP1 VDDIOP1 C20 C22 100n/10V 100n/10V V11 G7 C21 C24 100n/10V 100n/10V M4 L11 U7 N11 GND Vbat C25 100n/10V GNDIOP GNDIOP GNDIOP V15 T13 VDDBU L6 L4 VDDANA GNDANA R3 P4 VDDFUSE GNDFUSE R10 P10 VDDPLLA GNDPLL GND L3 top/bot BLM15AG121SN1D C33 C32 GNDBU VDDFUSE 470p/50V C31 4u7/6V3/X5R GNDIOP J7 E5 0603 R9 470n/16V/Y5V 0R GND AGND VDD_PLL VDD_PLL top/bot top/bot L5 BLM15AG121SN1D C39 470p/50V C37 4u7/6V3/X5R V13 U13 R12 C105 100n/10V VDDUTMIC VDDUTMII GNDUTMI C14 C16 C15 100n/10V 100n/10V 100n/10V VDDCORE VDDCORE VDDCORE VDDCORE T15 U17 V7 T7 C18 C17 C19 C23 100n/10V 100n/10V 100n/10V 100n/10V GNDCORE GNDCORE GNDCORE C9 N13 T8 T14 V17 GNDCORE GNDCORE GNDCORE VDDIODDR VDDIODDR VDDIODDR VDDIODDR VDDIODDR GND GND A16 VDDIODDR D13 F14 G10 G13 H11 GNDIODDR GNDIODDR GNDIODDR E14 F10 F13 GNDIODDR GNDIODDR F15 H14 VDDOSC GNDOSC U11 ADVREF L5 C26 C28 C27 100n/10V 100n/10V 100n/10V C30 C29 100n/10V 100n/10V GND GND top/bot T11 L4 470p/50V C34 3V3 BLM15AG121SN1D C36 4u7/6V3/X5R C35 SAMA5D3x 470n/16V/Y5V C38 ADVREF 2;4 GND UTMI_GND B A cooper for UTMI_GND net cover all USB Components GND L6 B 470n/16V/Y5V 3V3 GND top/bot VDDCORE VDDCORE VDDCORE C5 C7 D14 C VDD_ANA C T16 P12 C40 100n/10V GND BLM15AG121SN1D R57 C41 4u7/6V3/X5R 0603 C43 470p/50V C42 0R GND UTMI_GND 470n/16V/Y5V UTMI_GND A A FILE SAMA5D3x-CM CPU-POWER SUPPLY SAMA5D3x-CM v2.0f.scm SHEET NO SIZE REV DROWN PROJECT TITLE SHEET TITLE A4 1 2 3 DATE 20.9.2012 4 DESCRIPTION FILE ISSUED 5 4 OF 9 development tool www.ronetix.at 6 1 2 U3-H DDR_D3 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D13 DDR_D14 DDR_D15 DDR_D16 DDR_D17 DDR_D18 DDR_D19 DDR_D20 DDR_D21 DDR_D22 DDR_D23 DDR_D24 DDR_D25 DDR_D26 DDR_D27 DDR_D28 E10 DDR_A5 D10 DDR_A6 A8 DDR_A7 C10 B8 F11 A7 D9 B U4 DDR_A0 DDR_A1 DDR_A2 DDR_A3 M8 M3 M7 N2 DDR_D0 DDR_D1 DDR_D2 DDR_D3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 N8 N3 N7 P2 P8 H15 F17 G15 F16 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 P3 M2 P7 R2 R8 E17 G14 E16 D17 C18 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_BA0 DDR_BA1 DDR_BA2 R3 R7 L2 L3 L1 D16 C17 B16 B18 C15 DDR_D14 DDR_D15 DDR_D16 DDR_D17 DDR_D18 A18 C16 C14 D15 B14 DDR_D19 DDR_D20 DDR_D21 DDR_D22 DDR_D23 A15 A14 E12 A11 B11 DDR_D24 DDR_D25 DDR_D26 DDR_D27 DDR_D28 A6 DDR_A13 H12 H17 H13 G17 G16 DDR_DATA DDR_D[0-31] 5 5 5 VDDIODDR R50 R51 0R 5 C8 B12 A12 B7 G11 TP12 DDR_CK DDR_CK# group 1AB 5 5 DQ3 DQ4 DQ5 DQ6 DQ7 A8 A9 A10 A11 A12 DQ8 DQ9 DQ10 DQ11 DQ12 RFU(A13) RFU RFU BA0 BA1 DQ13 DQ14 DQ15 BA2 WE# CAS# RAS# K2 J8 K8 CKE CK D8 E7 F2 F8 H2 H8 J7 DQ0 DQ1 DQ2 A3 A4 A5 A6 A7 K9 A3 E3 J3 N1 A A0 A1 A2 CS# ODT P9 A7 B2 B8 D2 TP13 DDR_CS# LDQS LDQS#/NU UDQS UDQS#/NU LDM UDM CK# M8 M3 M7 N2 H1 H9 F1 F9 C8 DDR_D4 DDR_D5 DDR_D6 DDR_D7 DDR_D8 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 N8 N3 N7 P2 P8 C2 D7 D3 D1 D9 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13 P3 M2 P7 R2 R8 B1 B9 DDR_D14 DDR_D15 F7 E8 R72 B7 A8 DDR_DQS1 R73 0402 4k7 F3 B3 NC NC A2 E2 VDD VDD VDD A1 VDDQ VDDQ VDDQ C1 C3 C7 VSSQ VSSQ VDDQ VDDQ C9 E9 VSSQ VSSQ VSSQ VDDQ VDDQ VDDQ G1 G3 VSSQ VSSQ VSSQ VSSDL VDDQ VDDL G7 G9 J1 VREF J2 5 5 GND C44 C45 C48 C49 C52 C53 C56 C57 DDR_CKE 5 VDDIODDR R52 0R R53 K3 L7 K7 L8 DNP 0R 5 5 0402 100n/10V C77 100n/10V C79 100n/10V DDR_WE# DDR_CAS# DDR_RAS# DDR_CS# 5 100n/10V C109 100n/10V C110 100n/10V C108 5 5 5 5 5 R3 R7 L2 L3 L1 DDR_BA0 DDR_BA1 DDR_BA2 5 5 0402 100n/10V GND DDR_CK DDR_CK# group 1AB 100n/10V 100n/10V 100n/10V 100n/10V GND DQ8 DQ9 DQ10 DQ11 DQ12 RFU(A13) RFU RFU BA0 BA1 DQ13 DQ14 DQ15 BA2 WE# CAS# RAS# LDQS LDQS#/NU UDQS UDQS#/NU DDR_D16 DDR_D17 DDR_D18 DDR_D19 H1 H9 F1 F9 C8 DDR_D20 DDR_D21 DDR_D22 DDR_D23 DDR_D24 C2 D7 D3 D1 D9 DDR_D25 DDR_D26 DDR_D27 DDR_D28 DDR_D29 B1 B9 DDR_D30 DDR_D31 F7 E8 B7 A8 0402 5 R71 DDR_DQS3 4k7 0402 F3 B3 NC NC A2 E2 VDDIODDR VDD VDD VDD A1 DDR_DQM2 DDR_DQM3 C46 VDD VDD VDDQ E1 J9 M9 R1 A9 VDDQ VDDQ VDDQ C1 C3 C7 VSSQ VSSQ VDDQ VDDQ C9 E9 C55 VSSQ VSSQ VSSQ VDDQ VDDQ VDDQ G1 G3 C58 VSSQ VSSQ VSSQ VSSDL VDDQ VDDL G7 G9 J1 VREF J2 VSS VSS VSS VSS VSS VSSQ VSSQ GND C60 C47 C50 C51 C54 C59 5 GND 5 100n/10V C117 100n/10V C118 100n/10V C116 100n/10V 100n/10V 100n/10V 100n/10V C114 100n/10V 100n/10V C115 100n/10V 100n/10V C113 100n/10V 100n/10V C119 100n/10V 100n/10V C120 100n/10V DDR_VREF group 1AB 5 GND C61 100n/10V 100n/10V 5 Differential 5 100 ohms GND VDDIODDR DDR_DQS2 4k7 5 R70 UDM LDM CK# G8 G2 H7 H3 group 2B L3 & L8 MT47H128M16RT-3:C GND DDR_CK DDR_CK# A8 A9 A10 A11 A12 CKE CK H8 J7 5 DQ3 DQ4 DQ5 DQ6 DQ7 K2 J8 K8 D8 E7 F2 F8 H2 DQ0 DQ1 DQ2 A3 A4 A5 A6 A7 K9 P9 A7 B2 B8 D2 B A0 A1 A2 CS# ODT A3 E3 J3 N1 C76 100n/10V 100n/10V C111 100n/10V 100n/10V C112 100n/10V DDR_VREF group 1AB group 1AB GND VDDIODDR L7 BLM15AG121SN1D R12 1k5/1% C62 100n/10V 0402 5 R13 200R C64 4u7/6V3/X5R GND GND 2 GND R14 1k5/1% Keep nets as short as possible, therefore, DDR2 devices have to be placed close as possible of MIURA. The layout EBI DDR2 should use controlled impedance traces of ZO = 50Ohm characteristic impedance. Trace width = 0.13mm: target 50Ohm impedance. Trace space = 0.30 to 0.38 mm. group 1AB DDR_VREF 5 A R11 1R 0402 R10 200R 0402 GND 5 VDDIODDR 5 0402 C63 DDR_DQS0 4k7 0402 DDR_DQM0 DDR_DQM1 top/bot DDR_VREF group 1AB U5 DDR_A0 DDR_A1 DDR_A2 DDR_A3 VDD VDD VDDQ VSS VSS VSSQ VSSQ DDR_DATA DDR_D[16-31] DDR_D0 DDR_D1 DDR_D2 DDR_D3 E1 J9 M9 R1 A9 VSS VSS VSS DDR_ADDR DDR_A[0-13] MT47H128M16RT-3:C top/bot top/bot 5 5 5 5 5 5 5 group 2A L3 & L8 G8 G2 H7 H3 5 100n/10V 1 K3 L7 K7 L8 5 5 DDR_DQS3 DDR_CAS# DDR_WE# DDR_BA0 DDR_BA1 DDR_BA2 5 5 GND B13 D18 F18 A17 A13 A5 B5 E9 B6 F9 C12 E13 C13 DDR_WE# DDR_CAS# DDR_RAS# DDR_CS# DNP 0402 5 5 5 SAMA5D3x 0R 0402 DDR_DQM2 DDR_DQM3 DDR_DQS0 DDR_DQS1 DDR_DQS2 DDR_CKE DDR_RAS# 5 5 5 5 DDR_D29 DDR_D30 DDR_D31 DDR_DQM0 DDR_DQM1 DDR_VREF DDR_CKE 5 0402 DDR_CLKN DDR_CKE DDR_RAS DDR_CAS DDR_WE DDR_BA0 DDR_BA1 DDR_BA2 DDR_CALN DDR_CALP DDR_VREF DDR_DATA DDR_D[0-15] B DDR_CS DDR_CLK DDR_ADDR DDR_A[0-13] DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 F12 A10 E11 DDR_DQM0 G12 E15 DDR_DQM1 DDR_DQM2 B15 DDR_DQM3 D12 DDR_DQS0 E18 DDR_DQS1 G18 DDR_DQS2 B17 DDR_DQSN2 DDR_DQSN3 Chenged U4 and U5 minimizing crosstalk with [DQ, DQS, DQM] D11 DDR_A3 B9 DDR_A4 DDR_D29 DDR_D30 DDR_D31 DDR_DQS3 DDR_DQSN0 DDR_DQSN1 Zo=50 ohms C C DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 L3 & L8 DQS-4w-DQ-3w-DQM-4w-DQS Zo=50 ohms keeping propagation delay equal (between 2A & 2B too) DDR_A12 DDR_A13 DDR_D0 DDR_D1 DDR_D2 12.09.2012 Data traces may not exceed 1.3 inches (33.0 mm). Data traces must be length-matched to within 0.1 inch (2.54 mm). Data traces must match the data group trace lengths to within 0.25 inches (6.35 mm). D DDR_A8 DDR_A9 DDR_A10 DDR_A11 6 D DDR_A5 DDR_A6 DDR_A7 5 From MT47H64M16HR-25H to MT47H128M16RT-3:C group 3AB DQS-4w-DQ-3w-DQM-4w-DQS DDR_A4 DDR_A[0-13] C11 DDR_A1 A9 DDR_A2 Zo=50 ohms keeping propagation delay equal (between 2A & 2B too) DDR_A2 DDR_A3 B10 DDR_A0 4 Address and control traces may not exceed 1.3 inches (33.0 mm). Address and control traces must be length-matched to within 0.1 inch (2.54 mm). Address and control traces must match the data group trace lengths to within 0.25 inches (6.35 mm). GND DDR_A0 DDR_A1 A 3 DDR_ADDR C65 FILE SAMA5D3x-CM DDR2 INTERFACE SAMA5D3x-CM v2.0f.scm SHEET NO SIZE REV DROWN PROJECT TITLE 100n/10V GND SHEET TITLE A4 3 DATE 20.9.2012 4 DESCRIPTION FILE ISSUED 5 5 OF 9 development tool www.ronetix.at 6 1 2 3 4 5 6 7 8 U3-G 6 6 6 A9_NOR A10_NOR PE12/A12 R16 N16 A11_NOR A12_NOR PE13/A13 R17 A13_NOR PE14/A14 PE15/A15/SCK3 PE16/A16/CTS3 N17 R18 A14_NOR A15_NOR N18 P16 A16_NOR A17_NOR M18 A18_NOR N15 M15 A19_NOR A20_NOR PE10/A10 PE11/A11 PE17/A17/RTS3 PE18/A18/RXD3 PE19/A19/TXD3 PE20/A20/SCK2 PE21/A21(NANDALE) PE22/A22(NANDCLE) PE23/A23/CTS2 PE24/A24/RTS2 PE25/A25/RXD2 PE26/NCS0/TXD2 PE27/NCS1/TIOA2/LCDDAT22 PE28/NCS2/TIOB2/LCDDAT23 PE29/NWR1(NBS1)/TCLK2 PE30/NWAIT PE31/IRQ/PWML1 6 L3 & L8 6 6 Zo=60 ohms +/-10% 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 N12 L15 L14 L16 6 2 L13 PE28/NCS2/TIOB2/LCDDAT23 2 2 PE29/NWR1(NBS1)/TCLK2 PE30/NWAIT 2 2 PE31/IRQ/PWML1 D0 K15 K14 K16 K13 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 J14 J16 J13 D12 D13 D14 D15 NCS3 NANDRDY NRD NWE(NWR0) K17 J12 K18 J17 J15 J18 H16 H18 L12 L18 D13 D14 D15 NAND_CS/NCS3 NAND_RD/BY L17 K11 NRD_NOR/NAND_OE NWE_NOR/NAND_WE H5 E5 D6 D7 H6 E6 DQ4 DQ5 DQ6 6 6 6 6 6 6 6 6 E# W# DQ2 G# F3 D9 D10 G3 F4 D11 D12 G4 F5 D13 G6 DQ13 6 D14 D15 F6 G7 DQ14 DQ15/A-1 6 A1_NOR E2 A0 6 6 A2_NOR D2 A3_NOR A4_NOR C2 A2 A5_NOR A6_NOR B2 D3 A7_NOR C3 A6 A8_NOR A9_NOR A10_NOR A11_NOR A12_NOR A13_NOR A14_NOR A3 B6 A6 C6 D6 B7 A7 A7 A8 A9 A10 A11 A12 A15_NOR A16_NOR A17_NOR A18_NOR A19_NOR C7 D7 E7 B3 C4 A20_NOR D5 D4 C5 B8 6 6 R16 F2 22R 0402 PE26/NCS0/TXD2 A5 G2 NWE_NOR/NAND_WE NRD_NOR/NAND_OE B5 RP# BYTE# NRST 6 6 6 6 2;7;8 6 6 F7 A4 R/B# A22_NOR/NAND_CLE A21_NOR/NAND_ALE 16 CLE 17 8 ALE NRD_NOR/NAND_OE NWE_NOR/NAND_WE NAND_CS_R/NCS3 6 18 9 DQ8 DQ9 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 A21_NOR/NAND_ALE A22_NOR/NAND_CLE 2;6 PE23/A23_NOR/CTS2 6 6 6 0R 0402 VDD_IOM DQ10 DQ11 DQ12 R23 VDD_IOM B4 VPP/WP# A1 A2 R24 100k 6 6 6 R19 VCCQ D8 C66 100n/10V VCCQ VCC F1 C68 100n/10V G5 C67 100n/10V NAND_RD/BY 10k R22 0R 0402 NAND_WP DQ0 DQ1 RE# WE# DQ2 DQ3 CE# DQ4 DQ5 6 D2 32 41 D3 D4 6 6 D5 D6 D7 NC DQ6 42 43 14 NC DQ7 44 15 4 NC NC 5 6 NC NC 26 35 NC NC 7 19 NC 1 2 3 RD/BY# NC NC NC WP# NC VCC! NC NC A1 25 A8 B1 C1 C8 D1 E1 F8 48 VSS! VSS! 12 37 13 36 38 VCC VCC VSS VSS NC NC NC NC NC 28 NC NC DNU 47 NC G1 G8 H1 H8 VSS VSS VSS E8 H2 H7 NC NC NC 100n/10V 100n/10V DNU 6 6 21 NC NC C70 C71 6 6 22 23 VCC! NC NC NC NC NC 6 11 20 NC NC VDD_IOM GND A18 A19 A20 A21 A22 D0 D1 31 34 39 A4 A5 A13 A14 A15 A16 A17 29 30 10 A3 24 27 33 40 45 46 GND HY27UF082G2B-TPCB MT29F2G08ABAEAWP-IT Alternative component : MT29F2G08ABAEAWP-IT EN29GL128H-70BAIP M29W128GL70ZA6E Alternative component : M29W128GL70ZA6E GND C 2;6;9 NAND_RD/BY TP14 NAND_RD/BY NAND_CS/NCS3 PD13/SPI0_CS0 PD10/SPI0_MISO PD11/SPI0_MOSI PD12/SPI0_SPCK TP15 TP16 TP17 TP18 TP19 NAND_CS/NCS3 PD13/SPI0_CS0 PD10/SPI0_MISO PD11/SPI0_MOSI PD12/SPI0_SPCK TP20 GND C 6 6 2;6;9 2;6;9 2;6;9 SAMA5D3x VDD_IOM L3 & L8 Zo=60 ohms +/-10% U8 2;6 DQ7 D8 6 6 6 6 6 6 6 6 6 6 DQ0 DQ1 R17 100k D D0 D1 D2 D3 D4 D5 D6 D7 K12 D8 D9 D10 D11 D12 DQ3 D4 D5 6 2;6;8 2;6 M14 PE26/NCS0/TXD2 M12 PE27/NCS1/TIOA2/LCDDAT22 H4 6 6 2;6 2;8 PE24/RTS2 PE25/RXD2/1-Wire H3 E4 D3 6 A21_NOR/NAND_ALE A22_NOR/NAND_CLE PE23/A23_NOR/CTS2 D1 D2 6 6 N14 M17 M13 M16 6 E3 6 6 100k U6 D0 NAND FLASH R15 0402 A8_NOR P15 P18 NOR FLASH 0402 P17 VDD_IOM 6 6 0402 A6_NOR A7_NOR VDD_IOM E T18 R15 PE8/A8 PE9/A9 Static Memory Controller and External Bus Interface 6 A3_NOR A4_NOR A5_NOR PE7/A7 E A1_NOR A2_NOR P14 U18 PE4/A4 PE5/A5 PE6/A6 D R13 V18 0402 PE3/A3 R14 split up (close as possible to microcontroller) each trace into X traces according to the number of device targets: in this case NAND Flash and NOR Flash F PE2/A2 P13 F PE0/A0(NBS0) PE1/A1 VDD_IOM GND 100n/10V Populate either R25 or J1 /J2/ 5 GND VCC NAND_CS/NCS3 2 A Y 4 J2 NAND_CS_R/NCS3 HEADER TH 2x1/2mm/90dgr 6 VDD_IOP0 1 OE 2 CS_BOOT_DISABLE D1 BAT54CWT1G VDD_IOP0 DNP R65 0402 2;6;9 PD12/SPI0_SPCK top/bot VCC 1 2 5 6 CS# SO (SOI) SI (SIO) SCK VCC WP# 1-Wire EEPROM 8 3 100n/10V 7 4 R18 C73 VDD_IOP0 GND Y 22R 100n/10V 5 2 A PD10/SPI0_MISO PD11/SPI0_MOSI VDD_IOM HOLD# AT25DF321A-SH GND 2;6;8 R20 PE25/RXD2/1-Wire 1k5/1% 0R 2 0402 U7 IO 4 1 GND 1 OE GND B B 0402 2;6;9 2;6;9 VDD_IOP0 U10 0402 U11 PD13/SPI0_CS0 R26 100k R25 0R GND R27 10k C72 2;6;9 HEADER SMD 2x1/2mm/90dgr 1 2 GND 3 SN74LVC1G126DBVT VDD_IOP0 SERIAL FLASH J1 0402 6 0402 U9 1 2 0402 C69 R21 10k GND NC NC NC NC 3 4 5 6 DS2431P GND 3 SN74LVC1G126DBVT GND A A FILE SAMA5D3x-CM Fl: NAND/NOR/SERIAL/I2C/1-WIRE SAMA5D3x-CM v2.0f.scm SHEET NO SIZE REV DROWN PROJECT TITLE SHEET TITLE A3 1 2 3 4 5 DATE 20.9.2012 6 DESCRIPTION FILE ISSUED 7 6 OF 9 development tool www.ronetix.at 8 2 3 4 5 6 7 8 F F 1 ETH_DVDDL L8 2A ! max 345mA--> BLM21PG221SN1D C74 C128 22u/6V3 22u/6V3 ETH_AVDDL L11 2A ! GND GND max 205mA--> BLM21PG221SN1D ETH_AVDDH VDD_IOP1 C78 C129 22u/6V3 22u/6V3 E E max ?mA--> GND 2A ! U15 max ?mA--> max 563mA--> BLM21PG221SN1D C75 1 22u/6V3 22u/6V3 GND VIN L10 5 LX GND 2 GND 3 EN 4 VOUT SC189ASKTRT 1V0 GND C127 RS4 ETH_AVDDL_PLL GND 0.5A ! ETH_V1 max 13mA--> BLM15AG121SN1D 0402 10n/25V ETH_DVDDH L12 L13 LQM2HPN1R0MG0L C131 0402 L9 C106 C107 10n/25V 100n/10V C81 C130 22u/6V3 22u/6V3 C92 10u/6V3 RS3 2k/1% 10k/1% GND GND GND GND GND GND GND 2A ! max ?mA--> D C132 0402 0402 0402 R28 0402 GND 0402 R45 R54 R55 R56 R58 GND RGMII Routing Constraints (Reduced Gigabit Media Independent Interface): The RGMII signals must be length-matched by TX and RX groups. That is, the TX group should be matched within 0.25 inch (6.35 mm), and the RX group should be matched within 0.25 inch (6.35 mm). Total length should not exceed 1.75 inch (44.5 mm). There is no requirement to match the TX and RX groups because their clocks are not related. ETH_DVDDH 22u/6V3 22u/6V3 D C80 0402 BLM21PG221SN1D 4k7 0402 0402 22R 22R C 7 PB8/GTX_CLK PB9/GTXEN R31 4k7 0402 7 7 7 7 7 0402 PB5/GRX1 PB6/GRX2 PB7/GRX3 PB8/GTX_CLK PB9/GTXEN 7 7 7 R32 4k7 7 2;7 top/bot 25 place close to KSZ9021RN R59 0402 22R R60 0402 22R PB4/GRX0 PB5/GRX1 PB6/GRX2 PB7/GRX3 PB11/RX_CLK PB12/RX_DV R75 R61 R62 R33 0402 2;7 PB25/SCK1/GRX6 PB11/RX_CLK 7 PB12/RX_DV PB13/GRXER/PWML3 7 2;7 2 7 7 R77 0R DNP R37 PB18/CLK125_NDO place close to U3 C82 top/bot 22p/50V R34 Y4 CPX32-25.000MHz R39 100k GND 2 D2 BAS316 C86 0402 C87 C91 C90 Cl=Cs+[C1xC2]/[C1+C2] GNDif C1=C2 => C1,2=2[Cl-Cs] !!! Cl is load capacitance of the cristal. CS is the stray capacitance on the printed circuit board, typically a value of 5pf can be used for calculation R40 NRST 0402 DNP 0R C99 1uF/10V 10n/25V 10n/25V 10n/25V C93 C95 C94 C97 C96 C98 GND SAMA5D3x 2 2 TXD3 GTX_CLK TX_EN TXRXP_B TXRXM_B 5 top/bot top/bot ETH0_RX1+ 6 ETH0_RX1- 2 2 TXRXP_C TXRXM_C 7 8 top/bot top/bot ETH0_TX2+ ETH0_TX2- 2 2 TXRXP_D TXRXM_D 10 11 top/bot top/bot ETH0_RX2+ ETH0_RX2- 2 2 RXD0/MODE0 RXD1/MODE1 RXD2/MODE2 RXD3/MODE3 RX_CLK/PHYAD2 RX_DV/CLK125_EN LED2/PHYAD1 38 41 INT_N CLK125_NDO/LED_MODE 36 37 42 MDC MDIO RESET_N 46 45 XI XO 48 ISET R35 4k7 15 17 LED2 LED1 ETH_AVDDH ETH_DVDDH 16 34 40 AVDDH AVDDH AVDDH 1 12 47 AVDDL AVDDL 4 9 AVDDL_PLL LDO_O 44 43 C84 C83 C85 10n/25V 10n/25V 10n/25V 2 2 R36 1k GND 14 18 23 26 30 39 C89 C88 10n/25V 10n/25V DVDDH DVDDH DVDDH ETH_AVDDL_PLL GND ETH_DVDDL 10n/25V 10n/25V 10n/25V 10n/25V 10n/25V 10n/25V ETH_DVDDH ETH_AVDDL R38 4k99/1% 22p/50V ETH0_TX1+ ETH0_TX1- DVDDL DVDDL DVDDL DVDDL DVDDL DVDDL B 2;6;8 22R top/bot top/bot ETH_DVDDH top/bot top/bot LED1/PHYAD0 22R place close to KSZ9021RN 28 27 35 33 2 3 4k7 0402 PB16/GMDC PB17/GMDIO R76 7 0402 22R 22R 22R 0R DNP 7 0402 32 31 TXRXP_A TXRXM_A 0402 R6 PB10/GTXER/RF1 2 V3 P6 V1 R7 PB14/GCRS/CANRX1 2 U3 PB15/GCOL/CANTX1 2 P7 PB16/GMDC 7 V2 PB17/GMDIO 7 V5 PB18/CLK125_NDO T6 PB19/MCI1_CDA/GTX4 2 N8 PB20/MCI1_DA0/GTX5 2 U4 PB21/MCI1_DA1/GTX6 2 M7 PB22/MCI1_DA2/GTX7 2 U5 PB23/MCI1_DA3/GRX4 2 M8 top/bot PB24/MCI1_CK/GRX5 T5 PB25/SCK1/GRX6 2;7 N9 PB26/CTS1/GRX7 2 V4 PB27/RTS1/PWMH1 2 M9 PB28/RXD1 2 P8 PB29/TXD1 2 M10 PB30/DRXD 2 R9 PB31/DTXD 2 7 7 7 0402 B 0402 ETH_DVDDH 7 7 7 7 0402 0402 PB0/GTX0 PB1/GTX1 PB2/GTX2 PB3/GTX3 PB4/GRX0 0402 R30 R29 0402 22R 22R 22R 22R GND T4 R4 U1 R5 P3 0402 0402 PB9/GTXEN/PWML2 PB10/GTXER/RF1 PB11/GRXCK/RD1 PB12/GRXDV/PWMH3 PB13/GRXER/PWML3 PB14/GCRS/CANRX1 PB15/GCOL/CANTX1 PB16/GMDC PB17/GMDIO PB18/G125CK PB19/MCI1_CDA/GTX4 PB20/MCI1_DA0/GTX5 PB21/MCI1_DA1/GTX6 PB22/MCI1_DA2/GTX7 PB23/MCI1_DA3/GRX4 PB24/MCI1_CK/GRX5 PB25/SCK1/GRX6 PB26/CTS1/GRX7 PB27/RTS1/PWMH1 PB28/RXD1 PB29/TXD1 PB30/DRXD PB31/DTXD R69 R68 R67 R66 KSZ9021RN TXD0 TXD1 TXD2 C PB4/GRX0/PWMH1 PB5/GRX1/PWML1 PB6/GRX2/TD1 PB7/GRX3/RK1 PB8/GTXCK/PWMH2 T2 N7 T3 N6 P5 0402 PB0/GTX0/PWMH0 PB1/GTX1/PWML0 PB2/GTX2/TK1 PB3/GTX3/TF1 U12 19 20 21 22 24 0402 4k7 4k7 4k7 4k7 4k7 place close to CPU U3-D PB0/GTX0 PB1/GTX1 PB2/GTX2 PB3/GTX3 7 7 7 C121 VSS_PS VSS P_GND 13 29 49 C122 10n/25V GND GND 100n/10V GND GND L14 BLM15AG121SN1D GND A A FILE SAMA5D3x-CM ETHERNET SAMA5D3x-CM v2.0f.scm SHEET NO SIZE REV DROWN PROJECT TITLE SHEET TITLE A3 1 2 3 4 5 DATE 20.9.2012 6 DESCRIPTION FILE ISSUED 7 7 OF 9 development tool www.ronetix.at 8 1 2 3 SOFT MODEM Oscillators D U8 V8 27p/50V Y3 CPX32-12.000MHz C101 top/bot top/bot U16 V16 XIN32 XOUT32 top/bot top/bot GND 27p/50V NX3215SA-32.768K C102 RA1 4x100k T10 T12 U9 WKUP SHDN BMS 2 2 V9 NRST 2;6;7 T9 P11 JTAGSEL NTRST R8 P9 N10 M11 TDI/SWD TCK/SWCLK TMS/SWDIO TST U15 DIBP DIBN V6 U6 2 DIBP DIBN 2 2 2 2 2 2 2 R44 10k 0402 TDO 2 C JTAG R43 10k NTRST TDI/SWD TCK/SWCLK TMS/SWDIO TDO JTAGSEL C 0402 BMS R42 0R DNP GND NRST R41 100k 0402 0402 18p/50V WKUP SHDN VDD_IOP0 Vbat 18p/50V Y1 CM200C-32.768KDZF-UT C103 Y2 DNP 6 D XIN XOUT 5 Cl=Cs+[C1xC2]/[C1+C2] if C1=C2 => C1,2=2[Cl-Cs] !!! Cl is load capacitance of the cristal CS is the stray capacitance on the printed circuit board, typically a value of 5pf can be used for calculation C100 U3-B 4 SAMA5D3x GND VDD_IOM VDD_IOM B B U3-I LEDS USB USBB_DP USBB_DM top/bot top/bot top/bot U10 V10 R11 USBA_DP USBA_DM 2 90 ohms differential trace impedance 2 2 90 ohms differential trace impedance 2 2 90 ohms differential trace impedance 2 DL1 R47 R49 200R D 2;6 C104 G PE24/RTS2 Q1 BSS138 0402 R48 5k62/1% LED 0603 - BLUE - LTST-C193TBKT-5A 200R Max trace-length mismatch between USB signal pairs should be no greater than 3.8mm SAMA5D3x DL2 LED 0603 - RED - LTST-C190CKT R46 1M 0402 HHSDMA VBG U12 V12 USBC_DP USBC_DM 0402 HHSDMB HHSDPA top/bot top/bot top/bot 0402 HHSDPC HHSDMC HHSDPB U14 V14 10p/50V S 2;6 PE25/RXD2/1-Wire GND A A UTMI_GND FILE SAMA5D3x-CM USB/JTAG/LEDS SAMA5D3x-CM v2.0f.scm SHEET NO SIZE REV DROWN PROJECT TITLE SHEET TITLE A4 1 2 3 DATE 20.9.2012 4 DESCRIPTION FILE ISSUED 5 8 OF 9 development tool www.ronetix.at 6 A B U3-C C D SAMA5D3x PA0/LCDDAT0 E3 PA1/LCDDAT1 PA2/LCDDAT2 F5 PA0/LCDDAT0 2 PA1/LCDDAT1 PA2/LCDDAT2 PA3/LCDDAT3 PA4/LCDDAT4 PA5/LCDDAT5 D1 J10 PA4/LCDDAT4 PA5/LCDDAT5 PA6/LCDDAT6 G4 PA6/LCDDAT6 PA7/LCDDAT7 PA8/LCDDAT8 PA9/LCDDAT9 J9 F3 PA7/LCDDAT7 PA8/LCDDAT8 J8 E2 PA9/LCDDAT9 PA10/LCDDAT10 PA10/LCDDAT10 PA11/LCDDAT11 PA12/LCDDAT12 K8 2 2 2 2 2 PA11/LCDDAT11 PA13/LCDDAT13 F2 G6 PA12/LCDDAT12 PA13/LCDDAT13 PA14/LCDDAT14 PA15/LCDDAT15 E1 H5 PA14/LCDDAT14 PA15/LCDDAT15 PA16/LCDDAT16/ISI_D0 PA17/LCDDAT17/ISI_D1 PA18/LCDDAT18/TWD2/ISI_D2 PA19/LCDDAT19/TWCK2/ISI_D3 PA20/LCDDAT20/PWMH0 PA21/LCDDAT21/PWML0/ISI_D5 PA22/LCDDAT22/PWMH1 PA23/LCDDAT23/PWML1/ISI_D7 PA24/LCDPWM PA25/LCDDISP H3 PA16/LCDDAT16/ISI_D0 H6 H4 PA19/LCDDAT19/TWCK2/ISI_D3 PA20/LCDDAT20/PWMH0 J6 PA21/LCDDAT21/PWML0/ISI_D5 G2 J5 PA22/LCDDAT22/PWMH1 PA23/LCDDAT23/PWML1/ISI_D7 F1 J4 2 2 2 2 2 2 2 2 2 2 PA17/LCDDAT17/ISI_D1 PA18/LCDDAT18/TWD2/ISI_D2 H7 H2 2 2 2 2 2 2 2 PA24/LCDPWM PA25/LCDDISP 2 2 2 PA26/LCDVSYNC J3 G1 PA27/LCDHSYNC 2 2 PA29/LCDDEN PA30/TWD0/URXD1/ISI_VSYNC 2 PA30/TWD0/URXD1/ISI_VSYNC K4 H1 PA31/TWCK0/UTXD1/SI_HSYNC K3 PA31/TWCK0/UTXD1/SI_HSYNC 2 K5 PD0/MCI0_CDA 2 P1 PD1/MCI0_DA0 K6 R1 PD2/MCI0_DA1 PD3/MCI0_DA2 2 2 2 PA28/LCDPCK PA29/LCDDEN U3-F 2 G3 PA26/LCDVSYNC PA27/LCDHSYNC 1 1 PA3/LCDDAT3 D2 F4 top/bot PA28/LCDPCK 2 2 SAMA5D3x PD0/MCI0_CDA PD1/MCI0_DA0 PD2/MCI0_DA1 PD3/MCI0_DA2 PD4/MCI0_DA3 PD5/MCI0_DA4/TIOA0/PWMH2 PD6/MCI0_DA5/TIOB0/PWML2 PD7/MCI0_DA6/TCLK0/PWMH3 PD13/SPI0_NPCS0 PD14/SCK0/SPI0_NPCS1/CANRX0 PD15/CTS0/SPI0_NPCS2/CANTX0 PD16/RTS0/SPI0_NPCS3/PWMFI3 PD17/RXD0 PD18/TXD0 PD19/ADTRG PD20/AD0 PD21/AD1 PD22/AD2 PD23/AD3 PD24/AD4 PD25/AD5 PD26/AD6 PD27/AD7 PD28/AD8 PD29/AD9 PD30/AD10 PD31/AD11 U2 K9 M5 K10 N4 2 2 2 2 2 PD4/MCI0_DA3 PD5/MCI0_DA4/TIOA0/PWMH2 PD6/MCI0_DA5/TIOB0/PWML2 PD7/MCI0_DA6/TCLK0/PWMH3 PD8/MCI0_DA7//PWML3 2 top/bot R63 R64 0402 0402 22R 22R PD10/SPI0_MISO PD11/SPI0_MOSI 2;6 2;6 PD13/SPI0_CS0 2;6 2 2 2 2 L9 N3 L10 N5 M6 PD14/SCK0/SPI0_NPCS1/CANRX0 PD15/CTS0/SPI0_NPCS2/CANTX0 PD16/RTS0/SPI0_NPCS3/PWMFI3 PD17/RXD0 PD18/TXD0 T1 N2 M3 M2 L3 PD19/ADTRG PD20/AD0 PD21/AD1 PD22/AD2 PD23/AD3 M1 N1 L1 L2 K1 K2 J1 J2 PD24/AD4 PD25/AD5 PD26/AD6 PD27/AD7 PD28/AD8 PD29/AD9 PD30/AD10 PD31/AD11 PD9/MCI0_CK 2 top/bot PD12/SPI0_SPCK top/bot PC15/MCI2_CK/PCK2/LCDDAT21 3 3 PD8/MCI0_DA7//PWML3 PD9/MCI0_CK PD10/SPI0_MISO PD11/SPI0_MOSI PD12/SPI0_SPCK L7 P2 L8 R2 K7 2;6 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 U3-E SAMA5D3x D8 A4 E8 A3 A2 F8 B3 G8 B4 F7 A1 D7 C6 E7 B2 F6 B1 E6 C3 D6 C4 D5 C2 G9 C1 H10 H9 D4 H8 G5 D3 E4 PC0/ETX0/TIOA3 PC1/ETX1/TIOB3 PC2/ERX0/TCLK3 PC3/ERX1/TIOA4 PC4/ETXEN/TIOB4 PC5/ECRSDV/TCLK4 PC6/ERXER/TIOA5 PC7/EREFCK/TIOB5 PC8/EMDC/TCLK5 PC9/EMDIO PC10/MCI2_CDA//LCDDAT20 PC11/MCI2_DA0//LCDDAT19 PC12/MCI2_DA1/TIOA1/LCDDAT18 PC13/MCI2_DA2/TIOB1/LCDDAT17 PC14/MCI2_DA3/TCLK1/LCDDAT16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 PC16/TK0 PC17/TF0 PC18/TD0 PC19/RK0 PC20/RF0 PC21/RD0 PC22/SPI1_MISO PC23/SPI1_MOSI 2 2 2 2 2 2 2 2 PC25/SPI1_NPCS0 PC26/SPI1_NPCS1/TWD1/ISI_D11 PC27/SPI1_NPCS2/TWCK1/ISI_D10 PC28/SPI1_NPCS3/PWMFI0/ISI_D9 PC29/URXD0/PWMFI2/ISI_D8 PC30/UTXD0//ISI_PCK PC31/FIQ/PWMFI1 2 2 2 2 2 2 2 2 5 5 PC0/ETX0/TIOA3 PC1/ETX1/TIOB3 PC2/ERX0/TCLK3 PC3/ERX1/TIOA4 PC4/ETXEN/TIOB4 PC5/ECRSDV/TCLK4 PC6/ERXER/TIOA5 PC7/EREFCK/TIOB5 PC8/EMDC/TCLK5 PC9/EMDIO PC10/MCI2_CDA//LCDDAT20 PC11/MCI2_DA0//LCDDAT19 PC12/MCI2_DA1/TIOA1/LCDDAT18 PC13/MCI2_DA2/TIOB1/LCDDAT17 PC14/MCI2_DA3/TCLK1/LCDDAT16 PC15/MCI2_CK/PCK2/LCDDAT21 PC16/TK0 PC17/TF0 PC18/TD0 PC19/RK0 PC20/RF0 PC21/RD0 PC22/SPI1_MISO PC23/SPI1_MOSI PC24/SPI1_SPCK PC25/SPI1_NPCS0 PC26/SPI1_NPCS1/TWD1/ISI_D11 PC27/SPI1_NPCS2/TWCK1/ISI_D10 PC28/SPI1_NPCS3/PWMFI0/ISI_D9 PC29/URXD0/PWMFI2/ISI_D8 PC30/UTXD0//ISI_PCK PC31/FIQ/PWMFI1 top/bot PC24/SPI1_SPCK 2 FILE SAMA5D3x-CM BUS INTERFACE SAMA5D3x-CM v2.0f.scm SHEET NO SIZE REV DROWN PROJECT TITLE SHEET TITLE DESCRIPTION FILE 20.9.2012 ISSUED 9 OF 9 development tool www.ronetix.at D DATE 6 C 6 A4 B A 5. Main Board (MB) 5.1 Main Board Overview The SAMA5D3 series main board (MB) hosts any of the SAMA5D31/33/34/35/36 CPU module boards (CM). The main board features all necessary peripheral devices and interfaces for processor evaluation. Figure 5-1. Main Board Top View SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 53 Figure 5-2. Annotated MB Layout SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 54 5.1.1 Equipment List The SAMA5D3 series MB is a full-featured motherboard. It can be used with all available SAMA5D3 series CM boards. 5.1.2 Technical Specifications Table 5-1. MB Technical Specifications Characteristic Specifications Supported Module All SAMA5D3 series computer modules Expansion Slots One 200-pin SODIMM socket Mass Storage Interface Two high-speed memory card hosts 1 x SD card slot (can also read MMC cards) 1 x micro SD card slot 3 x 20 pin header 1 x 20 + 1 x 15 pin header LCD connector I/O 1 x 10 pin header ISI connector (Image Sensor) One 1-Wire EEPROM DS28EC20 One power LED 1 x Gigabit Ethernet 1 x 10/100 MHz Ethernet 2 x USB High-speed 2.0 Host Communication 1 x USB High-speed 2.0 Host/Device 1 x USARTs, 1 x DBGU 2 x CAN connectors 1 x 10-pin header ZigBee connector 1 x Smart DAA (Softmodem interface) Sound Wolfson's 8904 Mic in, Headphone out signals Video 1 x HDMI LCD LCD TFT Controller with overlay, alpha-blending, rotation, scaling and color space conversion ISI ITU-R BT. 601/656 Image Sensor Interface 1 x On-board SAM-ICE™ Debug 1 x Bridge USB/UART DBGU CMOS Battery On-board Lithium Battery for CMOS backup System power: +5V DC +/-5% Power Backup: +1.65V to 3.6V DC RoHS status Compliant CE and FCC Part 15 status Compliant Dimensions 165 * 135 * 20 mm Note: Some of the features mentioned in the above feature summary table are optional. Check the article number of your module and compare it to the option information list on Table 3-1 “Evaluation Kit Features” of this user guide to determine which options are available with your particular module. SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 55 5.1.3 Devices List of the MB board peripherals: 5.1.4  Two EMAC PHY  One audio CODEC  Two high-speed MCI card interfaces  Two CAN transceivers  One RS232 port with level translator features USART1  One Smart DAA port  Two USB host ports  One USB host/device port  On-board power regulation  LCD/ISI extension interface  HDMI interface  ZigBee® interface  One-wire device Board Interface Connection  Main power supply (J4)  200 positions socket (as defined in SODIMM 200), 0.6mm pitch (J12)  USB A Host/Device, support USB host/device using a micro AB connector (J20)  USB B Host, support USB host using a type A connector (J19, upper)  USB C Host, support USB host using a type A connector (J19, lower)  USB-to-serial bridge on DBGU, and JTAG-OB functionality (J14)  USART1 (RX, TX, RTS, CTS) connected to a 9-way male RS232 connector (J8)  JTAG, 20-pin IDC connector (J9)  MicroSD connector (J6)  SD/MMC connector (J7)  Gigabit Ethernet ETH0 (J17)  Ethernet ETH1 (J24)  Headphone (J15), line (J13)  Image sensor connector (J11)  HDMI connector (J25)  Expansion connector with all LCD controller signals for DM board connection (QTouch, TFT LCD display with touchscreen and backlight (J21, J22))  DAA connecter RJ11 6P4C type (J16)  CAN bus connectors RJ12 6P6C type (J18, J27)  ZigBee connector (J10)  Battery socket (J5)  Three expansion connectors with PIO signals (J1, J2, J3)  Test points; various test points are located throughout the board SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 56 Figure 5-3. MB Architecture VCC 5V Jack MIC1 MCI0 CAN0 & 1 COM1 or DBGU RS232 On Board JTAG Bridge USB/DBGU ZIGBEE RJ12 4 bits 4 bits interface interface 8 bits 8 bits interface interface oooooo oooooo MCI1 MCI1 Audio In RJ11 Micro Audio Out RJ12 HeadPh OnB JTAG OnB JTAG USB/DBGU USB/DBGU USART USART RS232 RS232 CONEXANT CONEXANT Micro input Can0 Can0 Can1 Can1 MCI0 MCI0 USART1 USART1 Audio output ZIGBEE ZIGBEE MUX System System Power Power Modem DBGU SAM3U SAM3U Modem Modem Codec Codec Connector SoDIMM200 Ethernet Ethernet RMII ETH1 RMII ETH1 Ethernet Ethernet RGMII ETH0 RGMII ETH0 USB USB Host Host RJ45 ISI ISI LCD Part 1 LCD Part 1 Host Host Device Device LCD Part 2 LCD Part 2 PIO PIO LCD interface LCD interface RJ45 oooooooo oooooooo Ethernet RMII 1-Wire 1-Wire Ethernet RGMII USB Host * 2 USB H/Device ISI oooooooo oooooooo HDMI LCD oooooooooooooooo oooooooooooooooo LCD oooooooooooooo oooooooooooooo PIO SAMA5D3x-MB SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 57 5.2 Function Blocks 5.2.1 Processor The SAMA5D3 series MB board may be used with any of the SAMA5D31/D33/D34/D35/SAMA5D36 CPU modules. Figure 5-4. SODIMM Interface on MB VDDIOP0 R83 4.7k JP9 for BMS Config: When Open,BMS=1: Boot on embeded ROM When Close,BMS=0: Boot on External memory 5V JP9 BMS 2 1 SIP2 12,13 ONE_WIRE PE25 VDDIOM 6,13 7 PC23 PC21 7,9 7,9 10 10 10 10 10 4 PC18 PC16 PC8 PC6 PC4 PC2 PC0 PWR_EN PE23 PE24 PE25 PE26 SPI1_MOSI RD PC25 PC23 PC21 TD TK E1_MDC E1_RXER E1_TXEN E1_RX0 E1_TX0 PC18 PC16 PC8 PC6 PC4 PC2 PC0 PE27 PC10 9,13 9,13 13 13 9 PC12 PC14 PC27 PC29 PC31 9,13 9,13 PA0 PA2 9,13 9,13 9,13 9,13 9,13 9,13 13 13 PA5 PA7 PA9 PA11 PA12 PA14 PA16 PA18 13 13 13 9,13 9,13 7,9,13 PA21 PA23 PA25 PA27 PA28 PA30 PB_USER1 LCDD22 LCDD20 PE27 PC10 TWCK1 LCDD18 LCDD16 ISI_D10 ISI_D8 RESET_HDMI PC12 PC14 PC27 PC29 PC31 VDDIOP0 LCDD0 LCDD2 ISI_D0 ISI_D2 ISI_D5 ISI_D7 ISI_VSYNC LCDD5 LCDD7 LCDD9 LCDD11 LCDD12 LCDD14 LCDDISP LCDHSYNC LCDPCK TWD0 VDDANA 7 11 11 13 13 13 5 7 6 PD30 PD28 PD26 PD24 PD22 PD20 PD18 PD16 PD14 PD12 PD10 R50 R6 PA0 PA2 PA5 PA7 PA9 PA11 PA12 PA14 PA16 PA18 PA21 PA23 PA25 PA27 PA28 PA30 PCK0 PD30 OVCUR_USB EN5V_HDB# AD4_LR AD2_YP AD0_XP MCI1_CD INT_AUDIO CANRX0 PD28 PD26 PD24 PD22 PD20 PD18 PD16 PD14 22R DNP 22R DNP 5 5 5 5 5 PD8 PD6 PD5 PD3 PD1 MCI0_D7 MCI0_D5 MCI0_D4 MCI0_D2 MCI0_D0 5 6,13 5 5 5 5 PB10 PB14 PB19 PB21 PB23 PB24 PWR_MCI0 CANRX1 MCI1_CDA MCI1_DA1 MCI1_DA3 MCI1_CK PD8 PD6 PD5 PD3 PD1 VDDIOP1 11 11 USBA_DP USBA_DM 11 11 USBB_DP USBB_DM 11 11 10 10 10 10 10 10 10 10 10 10 USBC_DP USBC_DM ETH0_GND ETH0_TX1+ ETH0_TX1ETH0_RX1+ ETH0_RX1ETH0_GND ETH0_TX2+ ETH0_TX2ETH0_RX2+ ETH0_RX2- 10 10 ETH0_LED2 ETH0_LED1 PB10 PB14 PB19 PB21 PB23 PB24 VCC5V_2 VCC5V_4 VBAT PE29 PE30 PE31 GND13 VDDIOM_2 PC24 PC22 PC20 PC19 PC17 PC9 PC7 GND14 PC5 PC3 PC1 Enable_1 VCC5V_1 VCC5V_3 GND1 PE23 PE24 PE25 PE26 VDDIOM_1 PC25 PC23 PC21 GND2 PC18 PC16 PC8 PC6 PC4 PC2 PC0 Enable_0 3V3 9,12,13 9,13 5V J12 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 ZB_RSTN ZB_IRQ1 ZB_IRQ0 PE29 PE30 PE31 VCC3V3_1 VCC3V3_3 Enable_2 NC1 PE27 PC10 GND3 PC12 PC14 PC27 PC29 PC31 VDDIOP0_1 PA0 PA2 GND4 PA5 PA7 PA9 PA11 PA12 PA14 PA16 PA18 GND5 PA21 PA23 PA25 PA27 PA28 PA30 VDDANA_1 PD30 GND6 PD28 PD26 PD24 PD22 PD20 PD18 PD16 PD14 GND7 PD12 PD10 PD8 PD6 PD5 PD3 PD1 VDDIOP1_1 GND8 PB10 PB14 PB19 PB21 PB23 PB24 GND23 USBA_DP USBA_DM GND10 USBB_DP USBB_DM GND11 USBC_DP USBC_DM GND_ETH1 ETH0_TX1+ ETH0_TX1ETH0_RX1+ ETH0_RX1GND_ETH2 ETH0_TX2+ ETH0_TX2ETH0_RX2+ ETH0_RX2GND12 LED2 LED1 VBAT PE29 PE30 PE31 4,12 6,13 6,10,13 6,9,13 PC24 PC22 PC20 PC19 PC17 PC9 PC7 6,13 6,13 7 7 7,9 10 10 VDDIOM PC24 PC22 PC20 PC19 PC17 PC9 PC7 SPI1_SPCK SPI1_MISO RF RK TF E1_MDIO E1_TXCK PC5 PC3 PC1 E1_CRSDV E1_RX1 E1_TX1 PC5 10 PC3 10 PC1 10 CS_BOOT_DISABLE 12 3V3 KEY 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 INT_ETH1 HDMI_INT VCC3V3_2 VCC3V3_4 Enable_3 ADVREF PE28 PC11 PC13 PC15 PC26 PC28 GND15 PC30 VDDIOP0_2 PA1 PA3 PA4 PA6 PA8 PA10 GND16 PA13 PA15 PA17 PA19 PA20 PA22 PA24 PA26 GND17 PA29 PA31 VDDANA_2 PD31 PD29 PD27 PD25 PD23 GND18 PD21 PD19 PD17 PD15 PD13 PD11 PD9 PD7 GND19 PD4 PD2 PD0 VDDIOP1_2 NC2 PB12 PB15 PB20 PB22 GND20 PB25 PB27 PB29 PB31 PB30 PB26 PB28 GND9 DIBP DIBN GND21 JTAGSEL WKUP SHDN BMS nRST nTRST TDI TCK TMS TDO RTCK GND22 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 PE28 PC11 PC13 PC15 PC26 PC28 ZB_SLPTR LCDD23 LCDD19 LCDD17 LCDD21 ISI_D11 TWD1 SPI1_NPCS3 ISI_D9 ISI_MCK PC30 PA1 PA3 PA4 PA6 PA8 PA10 PA13 PA15 PA17 PA19 PA20 PA22 PA24 PA26 PA29 PA31 PD31 PD29 PD27 PD25 PD23 PD21 PD19 PD17 PD15 ADVREF PE28 PC11 PC13 PC15 PC26 PC28 PC30 13 VDDIOP0 LCDD1 LCDD3 LCDD4 LCDD6 LCDD8 LCDD10 LCDD13 LCDD15 LCDPWM LCDVSYNC LCDDEN TWCK0 VDDANA VBUS_SENSE EN5V_HDC# EN5V_HDA# AD3_YM ISI_PCK ISI_D1 ISI_D3 ISI_D4 ISI_D6 ISI_HSYNC PCK1(HDMI) AD1_XM MCI0_CD CANTX0 DNP R120 DNP R51 PD9 PD7 MCI0_CK MCI0_D6 PD4 PD2 PD0 MCI0_D3 MCI0_D1 MCI0_CDA VDDIOP1 PB12 PB15 PB20 PB22 PWR_MCI1 CANTX1 MCI1_DA0 MCI1_DA2 PB25 PB27 PB29 PB31 PB30 PB26 PB28 RTS1 TXD1 DTXD DRXD CTS1 RXD1 22R 22R PD13 PD11 PA1 PA3 PA4 PA6 PA8 PA10 9,13 9,13 9,13 9,13 9,13 9,13 PA13 PA15 PA17 PA19 PA20 PA22 PA24 PA26 9,13 9,13 13 13 13 13 13 9,13 PA29 PA31 9,13 7,9,13 PD31 PD29 PD27 PD25 PD23 9 11 11 11 13 PD21 PD19 PD17 PD15 13 13 5 6 PD9 PD7 5 5 PD4 PD2 PD0 5 5 5 PB12 PB15 PB20 PB22 5 6,13 5 5 PB27 PB29 PB31 PB30 PB26 PB28 6 6 6,14 6,14 6 6 DIBP DIBN BMS 12 6,9,13 9,13 9,13 9,13 13 6,13 8 8 WAKE UP 12 SHDN 4 NRST NTRST TDI TCK TMS TDO RTCK 10,12,14 14 14 14 14 14 14 1612618-1 SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 58 5.2.2 Power Supplies The SAMA5D3 series MB is supplied with a simple external 5 VCC power supply. The MB features one adjustable lowdropout regulator (LDO). It accepts DC in 5V power and outputs a regulated +3.3V to most other circuits on the board through four 3.3V rails. 5.2.2.1 Supply Group Configuration The LDO is enabled through a dual FET scheme. The processor can assert SHDN (which is a VDDBU powered I/O) to shut down the LDO to enter backup mode. The regulators on the CM board are also shut down by the action of the SHDN signal. If the 3V battery is mounted on J5, both the CM and the MB can be woken up by action on the BP2 button, which drives the WKUP signal that is also a VDDBU powered I/O. Figure 5-5. MB Power Management 1 3V3 D1 J4 2 1 3 2 DC POWER JACK 5V/2A Input BAT54CLT1G 1 B CB 2 3 PSG CG1 CG2 CG3 4 5 6 C3 100n JP4 5V MN2 BNX002-01 3 1 J5 + C2 33u 2 SIP2 C1 100n VBAT 3,12 2 MN1 ZEN056V230A16LS 5V_INPUT 1 3 C4 100n 3V3 VOUT = 0.8V x (Rtop + Rbottom)/Rbottom 5V MN3 RT9018A 5V C120 1u 1 2 3 4 POWER_EN 1 2 R4 100k C6 10u 6 5 4 2 3 C7 1u GND ADJ VOUT NC 10n R2 47k L1 220ohm at 100MHz 1 2 VDDISI 13 R3 8 7 6 5 470R R5 15k C8 1u C9 10u D2 Red 1 Q1 Si1563EDH PGOOD EN VIN VDD C5 2 PWR_EN# C57 R1 100k 3 1 PWR_EN EP PWR_EN 3 9 Q6 IRLML2402 3V3 3V3 R25 10k JP5 2 100n SIP2 FORCE POWER ON 1 C10 15p R7 10k SHDN R8 10k C22 1u Place C22 near MN3.pin2 5V TP3 TP1 3V3 TP4 TP2 VDDIOP0 TP5 VDDIOP1 TP6 VDDIOM TP7 VDDANA TP8 SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 59 5.2.3 Debug JTAG/ICE and DBGU The MB includes a built-in SEGGER J-Link-on-Board device. The functionality is implemented with an ATSAM3U4C microcontroller in an LQFP100 package. The ATSAM3U4C provides the functions of JTAG and a bridge USB/Serial DBGU port. Two LEDs D13 and D14 that are mounted on the main board signal the status of the J-Link-on-Board device. The J-Link-OB-ATSAM3U4C was designed in order to provide an efficient, on-board alternative to the general J-Link. J-Link-OB-ATSAM3U4C supports the following target interfaces:  JTAG  DBGU An optional 20-pin header is provided on the board to allow for the JTAG connection. In order to use this functionality, RR6 and RR7 must be removed and JP15 jumper must be in place. Figure 5-6. MB JTAG-OB VCC_3V3_DEBUG R66 42 TCK_3U R131 0R R128 VCC RESET TMS NC2 GND1 TDI TCK NC1 GND2 TDO TRESIN TRESOUT TC2050-IDC RXDaux TXDaux RX_3U TX_3U TDIIN R44 R45 DTXD DRXD 0R 0R 0R R62 0R NRST_3U TDI_3U TDO_3U TCKOUT TMSOUT TDIOUT TDOIN TCKIN ENSPI TCKOUT 2 JP16 2 JP15 CDC Enabled,close to disable 1 1 LED1_3U LED2_3U RTCKIN VCC_3V3_DEBUG JTAG Enabled,close to disable VCC_3V3_DEBUG 2 D13 1 Red R69 1k 2 D14 1 Green R70 1k 3V3 R186 MN18 1 2 C94 10u C98 100n VDDIOP0 0R DNP VBUS_DEBUG VDDOUT_3U VDDOUT_3U 0R R64 3,6 3,6 PB31 PB30 3 VDDOUT_3U R65 TMSIN EARTH_USB2 VCC_3V3_DEBUG 10 9 8 7 6 4.7k T3 T4 4.7k 100n J23 1 2 3 4 5 R130 0R C92 R63 R129 DNP VDDCORE_1 VDDCORE_2 VDDCORE_3 VDDCORE_4 VDDCORE_5 87 83 9 34 59 TVS DNP 45 46 DNP VDDIO_1 VDDIO_2 VDDIO_3 VDDIO_4 VDDBU GNDBU D11 9 L24 TVS 220ohm at 100MHz 2 1 88 60 36 22 DHSDM DFSDM DFSDP DHSDP VDDPLL GNDPLL FWUP 77 80 81 76 VDDUTMI GNDUTMI 39R 39R 73 72 100k XIN XOUT 79 82 R43 75 74 VDDIN VDDOUT XOUT_3U VDDANA GNDANA 12MHz 4.7k 90 91 92 7 8 97 98 99 100 71 70 93 94 95 69 16 15 68 67 66 65 64 63 62 58 XIN32 XOUT32 XIN_3U R68 R67 DHSDP VBG Y4 4 DHSDM D12 6 3 VCC_3V3_DEBUG 1 2 3 4 5 11 C121 15p 1 8 7 J14 105017-0001 DHS EARTH_USB2 2 78 50 49 C117 10p C119 15p 10 6.8k/1% SAM3U_LQFP100 TEST JTAGSEL 53 52 VBUS_DEBUG NRST NRSTB 44 48 0R DNP 1 3 VCC_3V3_DEBUG 57 47 TRSTIN TRSTOUT R61 GND1 GND2 GND3 R54 10n AD12BVREF ADVREF 26 27 28 29 30 31 32 33 37 38 39 40 41 10 11 12 13 14 17 18 19 20 5 21 23 24 25 96 84 85 6 86 TMS_3U 35 61 89 NRST_3U C116 PA0/PGMNCMD PA1/PGMRDY PA2/PGMNOE PA3/PGMNVALID PA4/PGMM0 PA5/PGMM1 PA6/PGMM2 PA7/PGMM3 PA8/PGMD0 PA9/PGMD1 PA10/PGMD2 PA11/PGMD3 PA12/PGMD4 PA13/PGMD5 PA14/PGMD6 PA15/PGMD7 PA16/PGMD8 PA17/PGMD9 PA18/PGMD10 PA19/PGMD11 PA20/PGMD12 PA21/PGMD13 PA22/PGMD12 PA23/PGMD15 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 ERASE 4 2 VCC_3V3_DEBUG R145 47k TDI TDO/TRACESWO TCK/SWCLK TMS/SWDIO ERASE_3U 43 T1 VCC_3V3_DEBUG PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 MN17 51 54 56 55 TDI_3U TDO_3U TCK_3U TMS_3U VCC_3V3_DEBUG 0R/0805 ENSPI 5V C47 2.2u VIN VOUT 5 R185 0R C95 10u GND EN BYP C96 100n 4 SPX3819 500mA capability VCC_3V3_DEBUG VCC_3V3_DEBUG R179 150R TRSTIN C152 C153 C131 C146 C154 C155 C156 C157 C158 C159 C160 100n 100n 100n 4.7u 100n 100n 100n 100n 100n 100n 100n TDIOUT R180 1 2 3 4 8 0R 7 6 5 NTRST TDI TMS TCK VDDANA VDDIN VDDUTMI VDDIO VDDIO ADVREF TMSOUT R181 150R TMSIN TCKOUT R182 VDDIOP0 R106 R107 R109 100k 100k 100k 100k DNP DNP DNP DNP VDDIOP0 J9 DNP 2 4 6 8 10 12 14 16 18 20 150R TDIIN VDDBU R79 RR6 TRSTOUT 150R 1 3 5 7 9 11 13 15 17 19 DNP R113 0R R110 0R DNP R112 BR20-H 0R DNP NTRST TDI TMS TCK RTCK TDO NRST NTRST TDI TMS TCK RTCK TDO NRST 3 3 3 3 3 3 10,12,3 R111 0R DNP TCKIN VDDOUT_3U RR7 1 2 3 4 RTCKIN C161 C147 C162 C163 C164 C165 C166 C167 100n 4.7u 100n 100n 100n 100n 100n 100n VDDOUT VDDPLL VDDCORE 8 0R 7 RTCK 6 TDO 5 NRST ICE INTERFACE TDOIN TRESOUT R183 150R SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 60 5.2.3.1 Disabling J-Link-OB-ATSAM3U4C Jumper JP15 disables the J-Link-OB-ATSAM3U4C JTAG functionality. When the jumper is installed, it grounds Pin 25 of the ATSAM3U4C that is normally pulled high. This signals to the microcontroller it must not provide JTAG support.  Jumper JP15 not installed: J-Link-OB-ATSAM3U4C is enabled and fully functional  Jumper JP15 installed: JTAG functionality is disabled Jumper J15 disables only J-Link functionality. The debug serial port (DBGU) that is emulated through a communication device class (CDC) of the same USB connector remains operational. The built-in JTAG controller does not have to be explicitly disabled to use an external JTAG controller through the 20-pin JTAG port. The internal J-Link-OB connects to a target only after it receives a first command; otherwise, it remains disabled. 5.2.3.2 Hardware UART via CDC In addition to J-Link-OB functionality, the ATSAM3U4C microcontroller LAO provides a bridge to a debug serial port (DBGU) of the processor on a CM board. The port is made accessible over the same USB connection used by JTAG by implementing communication device class (CDC), which allows terminal communication with the target device. This feature is enabled only if the microcontroller Pin 24 is not grounded. The pin is normally pulled high and controlled by jumper JP16. 5.2.4  Jumper JP16 not installed: the device is enabled  Jumper JP16 installed: the CDC device is disabled USART The USART1 is used as a user serial communication port. This USART provides an RS-232 interface with transceiver TXD, RXD lines and hardware flow control CTS/RTS lines. The device uses a DB-9 male connector. The software must drive the appropriate PIO pins to enable the USART function. Figure 5-7. USART1 Com Port VDDIOP1 MN4 3 VDDIOP1 USART1 R22 R23 R24 4.7u 100n 23 C15 100n 1 C18 100n 21 19 47k 47k 47k PB27 PB29 PB31 PB26 PB28 PB30 RTS1 TXD1 DTXD R27 R28 R132 0R 0R 0R 5 7 8 9 DNP CTS1 RXD1 DRXD R30 R31 R133 0R 0R 0R DNP 10 11 12 VCC C1+ GND C1- V+ C2+ V- C2- SD C3+ EN T1IN T2IN T3IN R1OUT R2OUT R3OUT C3T1OUT T2OUT T3OUT R1IN R2IN R3IN ADM3312EARU 6 C16 100n C17 100n C19 100n J8 20 2 4 24 22 RTSC1 TXDC1 18 17 16 15 14 13 1 6 2 7 3 8 4 9 5 R29 0R CTSC1 RXDC1 11 C14 10 C13 L5 220ohm at 100MHz 1 2 EARTH_RS232 SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 61 5.2.5 USB Ports The SAMA5D3 series MB features three USB communication ports: Port A High-speed (EHCI) and full-speed (OHCI) host multiplexed with USB Device High-speed micro AB connector, J20 Port B High-speed (EHCI) and full-speed (OHCI) host Standard type A connector, J19 upper port Port C Full-speed (OHCI) only host Standard type A connector, J19 lower port All three USB host ports are equipped with 500 mA high-side power switch for self-powered and bus-powered applications. The USB device port feature VBUS insert detection function through the resistor ladder R138 and R139. Refer to the embedded MPU product datasheet for detailed programming information, available on www.atmel.com. Figure 5-8. USB Port A 3V3 L14 MN15 2 8 5V + C106 220ohm at 100MHz C107 100n 33u 7 C108 100n L15 1 6 2 5 220ohm at 100MHz C109 100n OUTA ENA IN FLGA FLGB GNG OUTB ENB R163 47k 1 2 EN_PWRLCD 3 OVCUR_USB 4 EN5V_HDA PD28 JP17 AIC1526-1GS R137 47k MN21 6 1Y 8 7 10 11 PD29 1 LCD_DETECT# 5 C99 100n VCC 2A 3 PD25 GND 2 13 3 SN74LVC2GU04 USBA_DM 3 USBA_DP 3 USB A HOST/DEVICE INTERFACE 47k 9 R140 1A 4 2Y 3 3V3 (IDUSBA) 3V3 6 (VBUS_SENSE) R139 82k 1 2 3 4 5 DHS EARTH_USB 47589-0001 47k C111 15p J20 OPEN:Enable LCD for D31,D33,D34 CLOSE:Disable LCD for D35 SIP2 3V3 C75 10u R138 13 1 1 5V_LCD 2 13 EARTH_USB Figure 5-9. USB Ports B and C USBB_DP 3 USBB_DM 3 L12 MN19 MN14 1 2 8 5V C102 100n 220ohm at 100MHz + C103 33u L13 1 C105 100n J19 + C104 7 C101 100n 6 2 220ohm at 100MHz 5 OUTA ENA IN FLGA GNG FLGB OUTB ENB 1 2 EN5V_HDB OVCUR_USB PD28 6 1Y PD28 4 2Y 3 4 5 3V3 EN5V_HDC AIC1526-1GS C97 100n 33u 1A 1 PD26 3 2A 3 PD27 3 GND 2 3 VCC SN74LVC2GU04 Dual USB A A1 A2 A3 A4 L21 220ohm at 100MHz 1 2 B1 B2 B3 B4 fi fl EARTH_USB 1 2 USBC_DM 3 USBC_DP 3 USB HOST B&C INTERFACE 3 4 EARTH_USB SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 62 5.2.6 Ethernet 10/100 (EMAC) Port The main board contains a MICREL PHY device (KSZ8051) handling Ethernet connectivity at 10/100 Mbps. The device supports MII and RMII interface modes. There are two independent PHY devices placed on CM and MB boards that connect to two separate RJ-45 connectors and that contain built-in magnetics and status LEDs. The LEDs are driven by PHY devices to indicate activity, link and speed status for the respective Ethernet ports. ETH0 Port ETH0 J17 3 3 3 3 3 3 3 ETH0_GND R175 ETH0_RX2+ ETH0_RX2- ETH0_GND ETH0_TX2+ ETH0_TX2- ETH0_GND ETH0_RX1+ ETH0_RX1- ETH0_GND ETH0_TX1+ ETH0_TX1- 0R ETH0_GND L23 220ohm at 100MHz 1 2 TRD4+ 7 TRCT4 9 TRD4- 3 TRD3+ 1 TRCT3 2 TRD3- 4 TRD2+ 6 TRCT2 5 TRD2- 11 TRD1+ C128 100n 12 TRCT1 10 TRD1- C125 100n C126 100n C127 100n T4/A 1:1 T3/A 7 TRP4- 8 T3/B TRP3+ 4 TRP3- 5 TRP2+ 3 TRP2- 6 TRP1+ 1 TRP1- 2 75 OHM 1:1 T2/A T2/B 75 OHM 1:1 T1/A T1/B 75 OHM 3 ETH0_LED2 13 3 ETH0_LED1 15 GREEN LED 17 GREEN LED EARTH_ETH0 ETH0_GND TRP4+ 75 OHM 1:1 YELLOW LED J0G-0003NL T4/B EARTH_ETH0 1NF,2KV (SHIELD) 14 3 3 8 16 10Base-T/100Base-TX/1000BASE-T 18 19 Figure 5-10. VDDIOP1 R165 R168 470R 470R SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 63 ETH1 Port ETH1 VDDIOP0 C122 100n 10Base-T/100Base-TX DNP L20 220ohm at 100MHz 2 1 C100 10u 10V R136 EARTH_ETH1 1 2 3 4 8 7 6 5 E1_RX1 E1_RX0 E1_CRSDV E1_RXER 1 2 3 4 8 7 6 5 25 24 23 13 14 15 16 18 20 29 28 22R RR19 1 2 3 4 R60 R59 VDDIOP0 8 7 6 5 EARTH_ETH1 RR21 10k TXM 3 VDDA_3V3 C31 10u C32 100n 17 RXP 5 R177 KSZ8051RNL VDD_1V2 1 2 TD- TX- 2 3 RD+ RX+ 3 RX- 6 5 CT DNP 6 RDC39 C118 100n 2.2u R171 49.9R DNP C124 100n GND PADDLE NC1 NC2 NC3 REXT 0R 4 2 1 33 22 26 27 10 C129 100n R172 49.9R DNP 75 7 NC GND_ETH1 R173 6.49k/1% 3,12,14 NRST 4 5 75 7 8 J00-0061NL VDDIO C38 100n 32 75 C123 100n DNP VDDIOP0 XI 8 ETH1_XO 9 ETH1_XI EARTH_ETH1 GND_ETH1 RR22 10k LED0/NWAYEN LED1/SPEED RESET 30 31 C91 22p 2 C34 10u 75 1nF 8 1 4 At the De-Assertion of Reset: PHY ADD[2:0]:001 CONFIG[2:0]:001,Mode:RMII Duplex Mode:Half Duplex Isolate Mode:Disable Speed Mode:100Mbps Nway Auto-Negotiation:Enable 16 TX+ E1_AVDDT XO VDDIOP0 J24 4 CT DNP VDDIOP0 1 2 3 4 VDDIOP0 0R 6 1 2 3 4 RR20 10k E1_AVDDT L2 220ohm at 100MHz 1 2 1 TD+ 7 R176 RXM MDC MDIO INTRP/NAND 8 7 6 5 8 7 6 5 VDDIOP0 TXP TXD1 TXD0 TXEN PHYAD0 PHYAD1 RXD1/PHYAD2 RXD0/DUPLEX CRS_DV/CONFIG2 RXER/ISO CONFIG1 CONFIG0 1k 1k 12 11 21 1 2 3 4 E1_MDC E1_MDIO INT_ETH1 REF_CLK/B-CAST_OFF 8 7 6 5 E1_TXCK E1_TX1 E1_TX0 E1_TXEN 22R RR18 PC8 PC9 PE30 GND_ETH1 R162 49.9R DNP MN20 19 PC3 PC2 PC5 PC6 R170 49.9R DNP GND_ETH1 22R RR17 PC7 PC1 PC0 PC4 0R 15 Figure 5-11. C88 22p Y2 3 2 D9 1 Yellow R134 470R 2 D8 1 Green R135 470R KSZ8041NL:R162,R170,R171,R172,R176,R177,C122,C123 a KSZ8051NL:R162,R170,R171,R172,R176,R177,C122,C123 a re needed. re not needed. 25MHz SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 64 5.2.7 Audio The MB includes a WM8904 CODEC that provides route to handle audio in the digital domain. The interface includes audio jacks for line input (J13) and headphone line output (J15). It also connects to an electret microphone, which is conveniently installed on the main board. This interface can be used to play and record audio. The WM8904 chip has left and right channel line inputs, a microphone input and an on-board microphone, as well as a left and right headphone output. The line in and headphones can be connected through two 2.5 mm J13 and J15 audio jacks. A stereo microphone input (or a second left/right line input) and left/right line outputs are connected to a 5-pin header (J26). The header is not installed normally. The SAMA5D3 series processor is configured in IIS slave mode to interface with the WM8904 CODEC. Figure 5-12. Audio Interface 3V3 3V3 L27 220ohm at 100MHz 1 2 C140 C141 4.7u 100n AUDIO_GND L26 220ohm at 100MHz 1 2 AUD_1V8 C46 C144 100n 3 DNP DNP C62 470p R84 20R C76 1u AUDIO_GND C143 4.7u 21 AUDIO_GND C136 4.7u 20 5 7 4 6 DCVDD CPVDD 19 23 AVDD MCLK BCLK/GPIO4 LRCLK ADCDAT DACDAT LINEOUTR LINEOUTL LINEOUTFB R86 2K2 L3 220ohm at 100MHz 1 2 R87 2K2 C28 3 2 R226 R234 1.5k 1.5k IRQ/GPIO1 0R 0R R227 R230 R231 R228 R229 R232 R233 28 29 30 31 32 33R 0R DNP 0R 0R 0R 0R 0R PCK0 TK RK RF TF RD TD INT_AUDIO 1 IN1L/DMICDAT1 CPCA VMIDC CPCB CPVOUTP MICBIAS CPGND IN2R IN2L WM8904 8 C45 C44 2.2u 3 C42 470p AUDIO_GND C43 470p AUDIO_GND R80 47k DNP R81 47k DNP 3,9 3,9 3 3 3,9 3 3,9 PD16 3 C41 2.2u R178 0R AUDIO_GND AUDIO_GND 1 1u 3 C30 4.7u AUD_1V8 MN7 AUDIO_GND 2 4 STEREO_3.5mm J13 PD30 PC16 PC19 PC20 PC17 PC21 PC18 12 1u AUDIO_GND C29 13,3,9 13,3,9 10 11 3V3 L4 220ohm at 100MHz 1 2 PA30 PA31 2.2u 2 1 TWD0 TWCK0 IN1R/DMICDAT2 CPVOUTN AUDIO_GND LINE IN SDA SCLK 2K2 24 26 R123 9 R126 25 27 AUDIO_GND 1 2 MP6027P AUDIO_GND 18 16 17 R122 C135 100n HPOUTFB DGND PAD OUT GND MIC1 R85 20R 100n 100n DNP J26 DNP MD1x5 DNP 5 4 3 2 1 MIC AGND MIC1 AUDIO_GND AUDIO_GND 20R C89 20R C90 HPOUTL 5 33 C61 470p R118 R119 C145 100n HPOUTR DBVDD 13 VDDIOP0 AUD_1V8 MICVDD MN10 15 L7 220ohm at 100MHz 1 2 14 4 STEREO_3.5mm J15 AUDIO_GND AUDIO_GND 2 1 2.2u C139 100n 22 5 L6 220ohm at 100MHz 1 2 C142 100n AVDD1V8 AVDD1V8 C138 10u HEADPHONE C137 10u C37 100n C36 2.2u VIN VOUT 5 GND EN BYP SPX5205M5-L-1-8 C33 4 4.7u C35 100n 150mA capability AUDIO_GND SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 65 5.2.8 HDMI Transmitter Interface The Main Board (MB) is equipped with an HDMI transmitter interface. The SiI9022/9024 HDMI Tx provides a complete solution for transmitting HDMI compliant digital audio/video. Specialized audio/video processing is available within the transmitter to easily and cost-effectively add HDMI capability to consumer electronics devices. The user must use an HDMI cable to connect to a monitor. This cable is not provided with the SAMA5D3 series-EK. A standard HDMI cable can be used. Important: HDMI Interface HDMI Spec. +4.8V < PVDD5 < +5.3V 5V R272 R273 C87 RB160M-60 RR27 22R RR28 22R RR29 22R R42 LCDPCK 3,7 PD30 PCK0 33R DNP 32 31 30 29 28 27 25 24 23 20 19 18 17 16 15 14 13 11 10 9 8 7 6 4 BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 BLUE6 BLUE7 GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 GREEN6 GREEN7 RED0 RED1 RED2 RED3 RED4 RED5 RED6 RED7 Close to SiI902x 22 CLK_HDMI 35 34 33 51 45 44 VSYNC_HDMI HSYNC_HDMI DE_HDMI RST# 41 40 39 37 R285 R266 Type A connector 100n 0R 38 T2 G2 G4 HPD_SiI 36 TSPDIF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 HPD 0R 48 49 54 52 71 50 R108 DDCSDA DDCSCL R71 DDCSDA DDCSCL 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 1k DNP 22R 8 7 6 5 22R 10k 0R 33R 0R R104 2K2 R90 4.7k R88 4.7k TXC+ TXCTX0+ TX0TX1+ TX1TX2+ TX2EXT_SWING 59 58 TX_C+ TX_C- 62 61 TX_0+ TX_0- 65 64 TX_1+ TX_1- 68 67 TX_2+ TX_2- D17 D15 R164 47k D18 TVS TVS 0R L38 DNP TXC- TX_C- 4 3 TXC- TX_C+ 1 2 TXC+ TVS R72 NCMS20C900 0R R73 TX_0- TXC+ TX0TX0+ TX1- 0R DNP L39 NCMS20C900 4 3 TX0- TX1+ TX2TX2+ 56 EXT_SW R265 4.3K/1% TX_0+ 1 2 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 TX0+ HDM19SW-4-1R-H R74 Close to Chip 0R J25 1V2 L18 AVCC_1 AVCC_2 AGND_1 AGND_2 IO_SEL CLK IOVCC18_1 IOVCC18_2 IOVCC18_3 VSYNC HSYNC DE RESETN SCLK LRCLK 60 66 69 1 AVCC12 C49 57 63 1n R41 C50 1n C51 C52 1n 1n C48 100n C53 100n C54 100n 2 EBMS321611A520 C82 10u 3 21 46 TX_1- 4 TX_1+ 1 R75 0R L40 DNP L19 1 MCLK SPDIF SiI9022ACUN CVCC12_1 CVCC12_2 CVCC12_3 CVCC12_4 CVCC12_5 CVCC12_6 CGND TX1- 2 IOVCC3V3 TX1+ R76 NCMS20C900 0R R77 0R 2 EBMS321611A520 C55 100n C56 100n C58 100n C81 10u TX_2TX_2+ DNP L41 NCMS20C900 4 3 TX21 R78 I2S0 I2S1 I2S2 I2S3 3 3V3 1k IO_SEL: LOW=3.3V ,HIGH=1.8V ePAD VDDQ TMODE RR26 22R PC16 PC17 PC18 PA26 PA27 PA29 PC31 PVDD5 1V2 5 12 26 42 47 53 CVCC12 C59 100n 43 C60 100n C77 100n C83 10u C78 100n C79 100n C80 100n 2 TX2+ 0R To keep TMDS pair impedance maintain at 100 ohm , pls share common choke pad with shunted resistor L22 EBMS321611A520 1 2 TX2+ TX2TX1+ TX1- 6 7 8 9 10 MN12 RClamp0514M 5 LINE4 NC2 4 NC4 LINE3 3 GND VCC 2 LINE2 NC1 1 NC3 LINE1 6 7 8 9 10 MN13 RClamp0514M 5 LINE4 NC2 4 NC4 LINE3 3 GND VCC 2 LINE2 NC1 1 NC3 LINE1 TX2+ TX2TX1+ TX1- 73 70 55 RR25 22R 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 3,7 3,7 3,7 13,3 13,3 13,3 3 D7 1812L160/12 HPD INT RR24 22R R260 1 LCDVSYNC RR30 2 LCDHSYNC 22R 3 4 LCDDEN RESET_HDMI R264 R184 3V3 R282 BCLK R270 LRCLK R284 DAT PA28 2 4.7k MN9 13,3 1 R105 2K2 CEC_A CEC_D R89 3V3 LCDDAT0 LCDDAT1 LCDDAT2 LCDDAT3 LCDDAT4 LCDDAT5 LCDDAT6 LCDDAT7 LCDDAT8 LCDDAT9 LCDDAT10 LCDDAT11 LCDDAT12 LCDDAT13 LCDDAT14 LCDDAT15 LCDDAT16 LCDDAT17 LCDDAT18 LCDDAT19 LCDDAT20 LCDDAT21 LCDDAT22 LCDDAT23 F1 3V3 DNP LOW:72h(Defult) 13,3 PA0 13,3 PA1 13,3 PA2 13,3 PA3 13,3 PA4 13,3 PA5 13,3 PA6 13,3 PA7 13,3 PA8 13,3 PA9 13,3 PA10 13,3 PA11 13,3 PA12 13,3 PA13 13,3 PA14 13,3 PA15 13,3 PC14 13,3 PC13 13,3 PC12 13,3 PC11 13,3 PC10 13,3 PC15 12,13,3 PE27 13,3,6 PE28 2K2 3V3 0R 0R 72 TWD0 TWCK0 R91 1 2 13,3,7 PA30 13,3,7 PA31 HDMI_INT SCL SDA PC29 CI2CA 13,3 G1 G3 Figure 5-13. Do not plug in the HDMI connector to a display with the evaluation kit powered on. Be certain that the EK board is not powered, plug in the cable to the display and then power on the SAMA5D3 series EK board. TX0+ TX03V3 1V2 MN8 1 2 C84 100n C85 10u 3 VIN VOUT 5 GND EN BYP TXC+ TXC- 4 TX0+ TX0TXC+ TXC- C86 10u RT9013-12PB SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 66 5.2.9 1-Wire EEPROM The MB also features a 1-wire device as a “software identification label” to store information such as chip type, manufacture name, production date, etc. Figure 5-14. 1-Wire on MB 3V3 ONE WIRE EEPROM DNP R144 1.5k MN16 ONE_WIRE PE25 2 3 I/O GND 1 4 5 6 NC1 NC2 NC3 NC4 DS28EC20P 5.2.10 CAN Bus The MB offers two CPU-controlled Controller Area Network (CAN) interfaces with transceivers available through connectors J18 and J27. Figure 5-15. CAN on MB JP7 CAN INTERFACE R21 CANTX0 PD15 10k R20 VDDIOP1 R40 0R 10k CANRX0 PD14 8 1 5 4 CANH CANL EN VCC R GND 120R 7 6 C21 10u 1 3,13 PB15 CANTX1 VDDIOP1 3,13 PB14 CANRX1 R33 R35 0R 10k R37 1 5 0R 4 D EN R R34 CANH CANL VCC GND SN65HVD234DR 120R 7 6 VDDIOP0 3 J27 2 SIP2 RS CAN0 MJM0606GE06-H C20 100n JP8 8 1 2 3 4 5 6 2 MN6 10k 3V3 5V VDDIOP0 3 SN65HVD234DR R32 J18 2 SIP2 RS D R19 1 MN5 3V3 5V 1 2 3 4 5 6 CAN1 MJM0606GE06-H 2 C23 100n C24 10u SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 67 5.2.11 Smart DAA The SAMA5D3 series MB features a Smart DAA chip to drive an analog telephone line on RJ11 6P4C port (J16). Figure 5-16. Smart DAA L8 220ohm at 100MHz 6.81M TEST 4 1 2 J16 MMBD3004S-7-F 2 R166 2 R93 AVDD EIC 11 C67 16 RXI 6.81M C68 3 14 LAN0066-50 DIBP EIF 10 R99 100R Q2 C69 10n MMBAT42 DAA_GND 1 9 3 C72 150pF TXF DVDD 1 Q3 7 1 13 EP GPIO R95 280R R96 280R R97 280R 1% 1206 1% 1206 1% 1206 R98 280R 1% 1206 Q5 1 1 MMBAT42 DVDD C73 100n 8 2 TXO VC 150pF EIO 3 C71 2 47n 2 4 MJM0606GE06-H 2 3 1 RJ11 TB3100M-13-F 470p Q4 MMBAT42 MMBAT42 2 0R 17 R167 C64 237K C70 47pF DIBP 1 1 2 3 4 5 6 D4 100V DAA_GND 6 DIBN 0805 470p 100n R94 DAA_GND 3 L9 220ohm at 100MHz DAA_GND DAA_GND TX1 0R 5 C63 3 DIBN 2 C66 100n TAC 2 C65 100n 0R can be replaced by bead to improve EMI PWR MMBD3004S-7-F 2 3 15 D5 1 1 2 RAC 1 1 D3 12 3 0805 R92 MN11 R100 3.01R CX20548-11Z R101 3.01R 1% 1% R102 110R DAA_GND C74 100n R103 9R1 1% 1206 DAA_GND R94,C68 should be placed near Pin6(RXI), and should be no vias on the RXI Net. DAA_GND SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 68 5.2.12 SD/MMC Interface SD/MMC is a standard Secure Digital/MultiMedia Card interface. The MB has two high-speed Multimedia Card Interfaces (MCI).  The first interface is used as an 8-bit interface (MCI0), connected to an SD/MMC card slot.  The second interface is used as a 4-bit interface (MCI1), connected to a MicroSD card slot. Each power line is on by default and is connected to a MOSFET controlled by a PIO to switch on or off the SD card power. Note: Figure 5-17. The power is connected to VCC, which is 3.3V. SD/MMC Interface VDD_MCI0 VDD_MCI0 VDDIOP1 RR3 10k JP6 MCI0 8 7 6 5 R15 R16 R17 R18 R26 R36 R38 R39 C40 2 R49 10k SIP2 C12 68k 68k 68k 68k 68k 68k 68k 68k 10u 100n 1 2 3 4 1 (MCI0_WP) (MCI0_CD) RR4 (MCI0_DA1) (MCI0_DA0) PD9 PD0 PD4 PD3 J7 (MCI0_CK) 1 2 3 4 8 7 6 27R 5 (MCI0_CDA) (MCI0_DA3) (MCI0_DA2) 1 RR5 2 3 4 8 27R 7 6 5 (MCI0_DA4) (MCI0_DA5) (MCI0_DA6) (MCI0_DA7) 1 2 3 4 R58 0R DNP 13 12 11 10 1 PB10 3 PB12 3 7SDMM-B0-2211 RR42 PD5 PD6 PD7 PD8 VDDIOP1 16 15 14 8 7 6 5 4 3 2 1 9 VDD_MCI0 27R 8 7 6 5 3 PD2 PD1 2 PD17 RR4,RR5,RR42 near SODIMM place Q8 IRLML6402 R47 4.7k SD/MMCPlus CARD INTERFACE - MCI0 VDDIOP1 VDD_MCI1 MCI1 R10 R11 R12 R13 R9 10k R14 10k VDDIOP1 68k 68k 68k 68k PD18 (MCI1_CD) Micro SD J6 3 PB24 3 3 3 PB19 PB23 PB22 (MCI1_CK) (MCI1_CDA) (MCI1_DA3) (MCI1_DA2) 1 2 3 4 RR2 27R 8 7 6 5 10 8 7 6 5 4 3 2 1 8 7 6 5 27R C93 10u C11 100n R121 0R DNP SW2 11 12 13 14 1 VDD_MCI1 3 PB21 PB20 RR1 1 2 3 4 SW1 3 3 (MCI1_DA1) (MCI1_DA0) 2 3 9 PJS008-2110-0 Q9 IRLML6402 R48 4.7k RR1,RR2 near SODIMM place SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 69 5.2.13 ZigBee The MB has a 10-pin male connector for the Atmel RZ600 ZigBee module. Not populated (DNP) 0 Ohm resistors have been implemented in series with the PIO lines that are used elsewhere in the design This ensures that in case of a conflict in the user application, the lines can be disconnected individually. Figure 5-18. ZigBee Interface ZIGBEE INTERFACE ZB_RSTN ZB_IRQ1 SPI1_NPCS3 SPI1_MISO PE29 PE30 PC28 PC22 R52 R56 R55 R82 DNP DNP DNP DNP J10 0R 0R 0R 0R DNP DNP 2 4 6 8 10 1 3 5 7 9 R53 R57 0R 0R BD10-H C25 15p C26 2.2n ZB_IRQ0 ZB_SLPTR SPI1_MOSI SPI1_SPCK 1 2 JP10 C27 DNP DNP 2.2u 3V3 5.2.14 LED Indicators The main board has one red LED (D2) that is on when the board is powered. There are two additional LEDs on the main board that are associated with on-board JTAG port. See Section 5.2.3 “Debug JTAG/ICE and DBGU”. 5.2.15 Pushbutton Switches 5.2.15.1  One reset, board reset (BP1)  One wake-up, pushbutton to bring the processor out of low-power mode (BP2)  One user momentary pushbutton  One boot memory Chip Select (CS), disabling the pushbutton (refer to Section 4.2.4.1 “Boot Configuration”). Reset When pressed and released, this pushbutton causes a power-on reset of the SAMA5D3 series EK (MB, CM and DM boards). SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 70 5.2.15.2 CS_BOOT Button The CS_BOOT can be used to prevent the system from booting out of external memories (NANDFlash, SPI Flash). The purpose is mainly to execute the SAM-BA part of the ROM code. Two methods can be used: Figure 5-19. 1. Press the CS_BOOT and power-cycle the board. 2. Press the CS_BOOT and then press the NRST button. Pushbutton 3V3 PUSH BUTTON VBAT R142 1.5k R141 100k PB1 NRST NRST 3,10,14 PB2 WAKE UP WAKE UP 3 PB3 PB_USER1 PB_USER1 PE27 3,9,13 PB4 CS_BOOT R46 0R CS_BOOT_DISABLE 3 5.2.16 Analog Reference The 3V voltage reference is based on an LM4040 (Precision Micropower Shunt Voltage Reference). This ADVREF level can be set as 3V or 3.3V via the jumper JP14. Analog Reference VDDANA 5V 1 ANALOG Reference 3V R143 1.5k JP14 2 ADVREF C112 100n 3 Figure 5-20. 3V C113 2.2u D6 LM4040BIM3-3.0+T SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 71 5.2.17 Expansion Ports Three 40-pin headers (J1, J2, J3) are provided on the board to allow for the PIO connection of various expansion cards that could be developed by the users or other sources. Due to multiplexing, different signals can be provided on each pin. I/O Expansion VDDIOP0 5V VDDIOP0 JP1 JP2 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 VDDIOP0 2 2 J2 MD2X20-H PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 VDDIOP0 VDDIOP0 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 1 3 J1 MD2X20-H 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 5V JP3 1 3 1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 VDDIOP1 5V 3 2 Figure 5-21. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 J3 MD2X20-H PB10 PB12 PB14 PB15 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PB31 PE23 PE24 PE25 PE26 PE29 PE30 PE31 PD10 PD11 PD12 PD13 PD14 PD15 PD19 PD31 VDDIOM VDDIOM Two connectors (J21, J22) are provided on-board to interface the optional LCD and touchscreen display module (DM) board. SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 72 Figure 5-22. LCD Expansion 3V3 3,6 13,3 R147 R146 PE31 PC27 3,9 3,9 3,9 3,9 3,9 3,9 ZB_IRQ0 TWCK1(SPI1_NPCS2) 0R 0R LCDDAT1 LCDDAT3 LCDDAT5 LCDDAT7 LCDDAT9 LCDDAT11 1 8 7 RR11 2 6 22R 3 4 5 1 RR43A 8 2 RR43B 7 PA1 PA3 PA5 PA7 PA9 PA11 LCD J21 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 ZB_IRQ1 TWD1(SPI1_NPCS1) LCDDAT15 LCDDAT13 LCDDAT14 LCDDAT12 LCDDAT0 LCDDAT2 LCDDAT4 LCDDAT6 LCDDAT8 LCDDAT10 R148 0R R149 0R 1 8 7 RR13 2 6 22R 3 4 5 1 8 7 RR12 2 6 22R 3 4 5 RR43C 3 6 RR43D 4 5 PE30 PC26 PA15 PA13 PA14 PA12 PA0 PA2 PA4 PA6 PA8 PA10 10,3,6 13,3 3,9 3,9 3,9 3,9 3,9 3,9 3,9 3,9 3,9 3,9 ESW-115-33-L-D 5V_LCD J22 11 5V_LCD 3,9 3,9 3,9 12,3,9 PC14 PC12 PC10 PE27 3 3,9 3,9 PA25 PA26 PA29 3 3 3 PD20 PD22 PD24 3,6 3,6 11 3,6 1 RR16 2 22R 3 4 8 7 6 5 LCDDAT16 LCDDAT18 LCDDAT20 LCDDAT22 1 RR14 2 22R 3 4 R150 R152 R154 8 7 6 5 LCDDISP LCDVSYNC LCDDEN 0R 0R 0R R156 R158 R160 R169 0R 0R 0R 0R PC22 PC24 EN_PWRLCD PB14 AD0_XP AD2_YP AD4_LR SPI1_MISO SPI1_SPCK EN_PWRLCD 3 PD19 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 ESW-120-33-L-D DNP R127 0R LCD/TSC LCDDAT17 LCDDAT19 LCDDAT21 LCDDAT23 1 RR23 2 22R 3 4 8 7 6 5 LCDPWM LCDHSYNC LCDPCK 1 RR15 2 22R 3 4 R151 R153 R155 8 7 6 5 AD1_XM AD3_YM ONE_WIRE SPI1_MOSI SPI1_NPCS3 PA27 R157 R159 R161 R174 PC13 PC11 PC15 PE28 3,9 3,9 3,9 3,6,9 PA24 PA27 PA28 3 13,3,9 3,9 0R 0R 0R PD21 PD23 PE25 0R 0R 0R 0R PC23 3,6 PC28 13,3,6 LCD_DETECT# 11 3,6 PB15 3 3 12,3 13,3,9 All I/Os of the SAMA5D3 series Image Sensor Interface (ISI) are routed to connectors J11. Figure 5-23. ISI Expansion VDDIOP0 4 3,6,9 3 VDDISI ZB_SLPTR TWCK1 PE28 PC27 VDDIOP0 3 3 3 3 3,6 3 PA17 PA19 PA21 PA23 PC28 PC26 R124 1.5k ISI_D1 ISI_D3 ISI_D5 ISI_D7 ISI_D9 ISI_D11 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 J11 TSW-115-07-L-D 2 4 ZB_RSTN 6 TWD1 8 10 ISI_MCK 12 ISI_VSYNC 14 ISI_HSYNC 16 ISI_PCK 18 ISI_D0 20 ISI_D2 22 ISI_D4 24 ISI_D6 26 ISI_D8 28 ISI_D10 30 ISI R125 1.5k PE29 3,6 PC15 PA30 PA31 PC30 PA16 PA18 PA20 PA22 PC29 PC27 3,9 3,7,9 3,7,9 3 3 3 3 3 3 3 PC26 SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 3 73 5.3 Configuration Table 5-2 describes the PIO usage, the jumpers, the test points and the solder drops of a SAMA5D3 series EK board. Table 5-2. Jumpers and Solderdrops Reference Default JP1 1-2 VDDIOP0 or 5V selection for J1 JP2 1-2 VDDIOP0 or 5V selection for J2 JP3 1-2 VDDIOP0 or 5V selection for J3 JP4 CLOSE Backup supply on/off JP5 CLOSE Force power on function JP6 CLOSE MCI0 write protect select JP7 CLOSE CAN0 diff termination select JP8 CLOSE CAN1 diff termination select JP9 OPEN Default boot on embedded ROM, close boot on external memory JP10 OPEN ZigBee power on/off select JP11 — JP12 — JP13 — JP14 1-2 JP15 OPEN JTAG enable JP16 OPEN CDC enable OPEN Enable LCD for D31, D33, D34 CLOSE Disable LCD for D35 JP17 JP18 Table 5-3. Page 3 1-2 Function ADVREF input selection SAM3U powered by main 3V3 Default Not Populated Parts Reference Function R6,R51,R50,R120 Optional PD10, PD11, PD12, PD13 from MB R58 Optional for MCI0 power supply mode R121 Optional for MCI1 power supply mode R52,R53,R55,R56,R57,R82,JP10 Optional ZigBee R132,R133 Debug or USART1 option C89,C90,R118,R119,J26 Optional Audio Line out, MIC in R80,R81 Optional MIC level setting R230 Optional audio TK L38,L39,L40,L41 Optional HDMI EMI filter R89 HDMI chip I2C address setting R266 Optional for I2S PCLK R42 Optional for LCD PCLK 5 6 7 9 SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 74 Table 5-3. Page Default Not Populated Parts Reference Function 10 R162,R170,R171,R172,R176,R17 7,C122,C123 Optional for KSZ8041NL 12 R144 Optional pull up for DS28EC20P 13 R127 Optional for ADC trigger R79,R106,R107,R109,R113,R110, R112,R111,J9 Optional JTAG R54 SAM3U JTAG selection R63 5V option D11,D12 USB ESD protect option R186 Main 3V3 optional for VCC_3V3_DEBUG 14 SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 75 5.4 PIO Usage and Interface Connectors Details 5.4.1 Power Supply Figure 5-24. Power Supply Connector J4 Table 5-4. Pin 1 Power Supply Connector J4 Signal Description Mnemonic Signal Description Center +5V 2 GND 3 Floating SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 76 5.4.2 JTAG/ICE Connector Figure 5-25. JTAG J9 Table 5-5. Pin JTAG/ICE Connector J9 Signal Descriptions Mnemonic Signal Description 1 VTref 3.3V power This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators, and to control the output logic levels to the target. It is normally fed from VDD on the target board and must not have a series resistor. 2 Vsupply 3.3V power This pin is not connected in SAM-ICE. It is reserved for compatibility with other equipment. Connect to VDD or leave open in target system. 3 nTRST Target Reset - Active-low output signal that resets the target. JTAG Reset. Output from SAM-ICE to the Reset signal on the target JTAG port. Typically connected to nTRST on the target CPU. This pin is normally pulled High on the target to avoid unintentional resets when there is no connection. 4 GND Common ground 5 TDI Test Data Input - Serial data output line, sampled on the rising edge of the TCK signal. JTAG data input of target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TDI on target CPU. 6 GND Common ground 7 TMS Test Mode Select. JTAG mode set input of target CPU. This pin should be pulled up on the target. Typically connected to TMS on target CPU. Output signal that sequences the target's JTAG state machine, sampled on the rising edge of the TCK signal. 8 GND Common ground 9 TCK Test Clock - Output timing signal, for synchronizing test logic and control register access. JTAG clock signal to target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TCK on target CPU. 10 GND Common ground 11 RTCK - Input Return Test Clock signal from the target. Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, a returned and retimed TCK can be used to dynamically control the TCK rate. SAM-ICE supports adaptive clocking which waits for TCK changes to be echoed correctly before making further changes. Connect to RTCK if available, otherwise to GND. 12 GND Common ground 13 TDO JTAG Test Data Output Serial data input from the target. JTAG data output from target CPU. Typically connected to TDO on target CPU. 14 GND Common ground 15 nSRST RESET Active-low reset signal. Target CPU reset signal. SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 77 Table 5-5. 5.4.3 JTAG/ICE Connector J9 Signal Descriptions Pin Mnemonic Signal Description 16 GND Common ground 17 RFU This pin is not connected in SAM-ICE. 18 GND Common ground 19 RFU This pin is not connected in SAM-ICE. 20 GND Common ground USB Type A Dual Port Figure 5-26. USB Type A Dual Port J19 Table 5-6. USB Type A Dual Port J19 Signal Descriptions Pin Mnemonic A1 Vbus - USB_A 5V power A2 DM - USB_A Data minus A3 DP - USB_A Data plus A4 GND Common ground B1 Vbus - USB_A 5V power B2 DM - USB_A Data minus B3 DP - USB_A Data plus B4 GND Common ground Mechanical pins PIO Signal Description Shield SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 78 5.4.4 USB MicroAB Figure 5-27. USB Host/Device MicroAB Connector J20 Table 5-7. Pin 5.4.5 USB Host/Device Micro AB Connector J20 Signal Descriptions Mnemonic PIO Signal Description 1 Vbus 5V power 2 DM Data minus 3 DP Data plus 4 ID On the Go identification 5 GND Common ground JTAG OB USB MicroAB Figure 5-28. USB JTAG OB MicroAB connector J14 Table 5-8. Pin USB JTAG OB MicroAB connector J14 Signal Descriptions Mnemonic PIO Signal description 1 Vbus 5V power 2 DM Data minus 3 DP Data plus 4 ID On the Go Identification 5 GND Common ground SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 79 5.4.6 HDMI Connector Figure 5-29. HDMI Female Type A Connector J25 Table 5-9. HDMI Type A Female Connector J25 LCD Pin Num LCD TMDS Data 2+ 1 2 TMDS Data 2 Shield TMDS Data 2- 3 4 TMDS Data 1+ TMDS Data 1 Shield 5 6 TMDS Data 1- TMDS Data 0+ 7 8 TMDS Data 0 Shield TMDS Data 0- 9 10 TMDS Clock + TMDS Clock Shield 11 12 TMDS Clock - NC 13 14 NC SCL 15 16 SDA GND 17 18 +5V Hot Plus Detect 19 SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 80 5.4.7 RS232 Connector with RTS/CTS Handshake Support Figure 5-30. USART1 Connector J8 Table 5-10. Pin USART Connector J8 Signal Descriptions Mnemonic PIO Signal Description 1, 4, 6, 9 No connection 2 RXD (Received Data) PB28 RS232 serial data output signal 3 TXD (Transmitted Data) PB29 RS232 serial data input signal 5 GND 7 RTS (Request To Send) PB27 Active-positive RS232 input signal 8 CTS (Clear To Send) PB26 Active-positive RS232 output signal Mechanical pins 5.4.8 Common ground Shield DAA RJ11 Socket (6P4C) Figure 5-31. DAA RJ11 Socket J16 SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 81 Table 5-11. Pin DAA RJ11 Socket J16 Signal Descriptions Mnemonic 1, 2, 5, 6 5.4.9 Signal Description No connection 3 RAC RING side of ordinary telephone line 4 TAC TIP side of ordinary telephone line CAN RJ12 Socket (6P6C) Figure 5-32. CAN RJ12 Socket J18, J27 Table 5-12. Pin CAN RJ12 Socket Signal Descriptions Mnemonic Signal Description 1 3V3 Power pin 2 5V Power pin 4 CANL CAN bus differential pair 5 CANH CAN bus differential pair GND Common ground 3, 6 SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 82 5.4.10 SD/MMC Plus MCI0 Figure 5-33. SD Socket J7 Table 5-13. Pin MicroSD Socket J7 Signal Descriptions Mnemonic PIO Signal Description 1 DAT3 PD4 Data bit 2 CMD PD0 Command line 3 VSS Command line 4 VCC Supply voltage 3.3V 5 CLK PD9 Clock / command line 6 CD PD17 Card detect 7 DAT0 PD1 Data bit 8 DAT1 PD2 Data bit 9 DAT2 PD3 Data bit 10 DAT4 PD5 Data bit 11 DAT5 PD6 Data bit 12 DAT6 PD7 Data bit 13 DAT7 PD8 Data bit 14 WP JP6 Protect 15 VSS Common ground 16 VSS Common ground SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 83 5.4.11 MicroSD MCI1 Figure 5-34. MicroSD Socket J6 Table 5-14. Pin MicroSD Socket J6 Signal Descriptions Mnemonic PIO Signal Description 1 DAT2 PB22 Data bit 2 2 CD/DAT3 PB23 Card detect / data bit 3 3 CMD PB19 Command line 4 VCC 5 CLK 6 VSS 7 DAT0 PB20 Data bit 0 8 DAT1 PB21 Data bit 1 9 SW1 10 CARD DETECT Supply voltage 3.3V PB24 Clock / command line Common ground Not used, grounded PD18 Card detect SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 84 5.4.12 Gigabit Ethernet ETH0 RJ45 Socket J17 Figure 5-35. Gigabit Ethernet RJ45 Socket J17 5.4.13 Ethernet ETH1 RJ45 Socket J24 Figure 5-36. 5.4.14 Ethernet RJ45 Socket J24 ZigBee Socket J10 Figure 5-37. ZigBee Socket J10 Table 5-15. ZigBee Socket J10 Signal Descriptions Function Signal Name Port Pin Pin Port Signal Name Function Option on Misc. Port Set by OR or Solder Shunts EEPROM for MAC address, cap array settings and serial number Reset /RST 1 2 Misc. TST: test mode activation CLKM: RF chip clock output Interrupt Request IRQ 3 4 SLP_TR SLP_TR SPI chip select /SEL 5 6 MOSI SPI MOSI SPI MISO MISO 7 8 SCLK SPI CLK Power Supply GND 9 10 VCC VCC GND VCC Voltage range: 1.8V to 5.5V, regulated to 3.3V SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 85 5.4.15 LCD Socket J21 Figure 5-38. LCD Socket J21 Table 5-16. LCD Socket J21 HE10 Female LCD 2*15p LCD Pin Number LCD VDD3V3 1 2 GND VDD3V3 3 4 GND ZB_IRQ0 5 6 ZB_IRQ1 TWCK1 7 8 TWD1 GND 9 10 LCDDAT15 GND 11 12 LCDDAT13 GND 13 14 LCDDAT14 GND 15 16 LCDDAT12 GND 17 18 LCDDAT0 LCDDAT1 19 20 LCDDAT2 LCDDAT3 21 22 LCDDAT4 LCDDAT5 23 24 LCDDAT6 LCDDAT7 25 26 LCDDAT8 LCDDAT9 27 28 LCDDAT10 LCDDAT11 29 30 GND SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 86 5.4.16 LCD/TSC Socket J22 Figure 5-39. LCD/TSC Socket J22 Table 5-17. LCD/TSC Socket J22 HE10 Female LCD/TSC/QT 2*20p LCD Pin Number LCD 5V 5V_LCD 1 2 GND GND 5V 5V_LCD 3 4 GND GND LCDDAT16 5 6 LCDDAT17 LCDDAT18 7 8 LCDDAT19 LCDDAT20 9 10 LCDDAT21 LCDDAT22 11 12 LCDDAT23 13 14 LCDDISP 15 16 LCDPWM LCDCSYNC 17 18 LCDHSYNC LCDDEN 19 20 LCDPCK GND GND GND GND GND GND 21 22 GND GND AD0_XP TSC 23 24 TSC AD1_XM AD2_YP TSC 25 26 TSC AD3_YM AD4_LR TSC 27 28 GND1 GND 29 30 SPI1_MISO 31 32 SPI1_MOSI SPI1_SPCK 33 34 SPI1_NPCS3 EN_PWRLCD 35 36 LCD_DETECT PB14 37 38 PB15 GND 39 40 GND GND ONE_WIRE GND GND LCD_DETECT# GND SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 87 5.4.17 ISI Socket J11 Figure 5-40. ISI Socket J11 Table 5-18. ISI Socket J11 HE10 Female ISI 2*15p ISI Pin Number ISI VDDISI 1 2 GND VDDISI 3 4 GND ZB_SLPTR 5 6 ZB_RST TWCK1 7 8 TWD1 GND 9 10 ISI_MCK GND 11 12 ISI_VSYNC GND 13 14 ISDI_HSYNC GND 15 16 ISI_PCK GND 17 18 ISI_D0 ISI_D1 19 20 ISI_D2 ISI_D3 21 22 ISI_D4 ISI_D5 23 24 ISI_D6 ISI_D7 25 26 ISI_D8 ISI_D9 27 28 ISI_D10 ISI_D11 29 30 GND SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 88 5.4.18 PIO Usage Table 5-19. PIO A Pin Assignment and Signal Description Power Rail Signal Signal Signal Signal SAMA5-CM SAMA5-MB VDDIOP0 PA0 LCDDAT0 PIO PU – LCDDAT0 VDDIOP0 PA1 LCDDAT1 PIO PU – LCDDAT1 VDDIOP0 PA2 LCDDAT2 PIO PU – LCDDAT2 VDDIOP0 PA3 LCDDAT3 PIO PU – LCDDAT3 VDDIOP0 PA4 LCDDAT4 PIO PU – LCDDAT4 VDDIOP0 PA5 LCDDAT5 PIO PU – LCDDAT5 VDDIOP0 PA6 LCDDAT6 PIO PU – LCDDAT6 VDDIOP0 PA7 LCDDAT7 PIO PU – LCDDAT7 VDDIOP0 PA8 LCDDAT8 PIO PU – LCDDAT8 VDDIOP0 PA9 LCDDAT9 PIO PU – LCDDAT9 VDDIOP0 PA10 LCDDAT10 PIO PU – LCDDAT10 VDDIOP0 PA11 LCDDAT11 PIO PU – LCDDAT11 VDDIOP0 PA12 LCDDAT12 PIO PU – LCDDAT12 VDDIOP0 PA13 LCDDAT13 PIO PU – LCDDAT13 VDDIOP0 PA14 LCDDAT14 PIO PU – LCDDAT14 VDDIOP0 PA15 LCDDAT15 PIO PU – LCDDAT15 VDDIOP0 PA16 LCDDAT16 ISI_D0 PIO – ISI_D0 VDDIOP0 PA17 LCDDAT17 ISI_D1 PIO – ISI_D1 VDDIOP0 PA18 LCDDAT18 TWD2 ISI_D2 – ISI_D2 VDDIOP0 PA19 LCDDAT19 TWCK2 ISI_D3 – ISI_D3 VDDIOP0 PA20 LCDDAT20 PWMH0 ISI_D4 – ISI_D4 VDDIOP0 PA21 LCDDAT21 PWML0 ISI_D5 – ISI_D5 VDDIOP0 PA22 LCDDAT22 PWMH1 ISI_D6 – ISI_D6 VDDIOP0 PA23 LCDDAT23 PWML1 ISI_D7 – ISI_D7 VDDIOP0 PA24 LCDPWM PIO PU – LCDPWM VDDIOP0 PA25 LCDDISP PIO PU – LCDDISP VDDIOP0 PA26 LCDVSYNC PIO PU – LCDVSYNC VDDIOP0 PA27 LCDHSYNC PIO PU – LCDHSYNC VDDIOP0 PA28 LCDPCK PIO PU – LCDPCK VDDIOP0 PA29 LCDDEN PIO PU – LCDDEN VDDIOP0 PA30 TWD0 URXD1 ISI_VSYNC – ISI_VSYNC VDDIOP0 PA31 TWCK0 UTXD1 ISI_HSYNC – ISI_HSYNC SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 89 Table 5-20. PIO B Pin Assignment and Signal Description Power Rail Signal Signal Signal Signal SAMA5-CM VDDIOP1 PB0 GTX0 PWMH0 PIO GETH CM – VDDIOP1 PB1 GTX1 PWML0 PIO GETH CM – VDDIOP1 PB2 GTX2 TK1 PIO GETH CM – VDDIOP1 PB3 GTX3 TF1 PIO GETH CM – VDDIOP1 PB4 GRX0 PWMH1 PIO GETH CM – VDDIOP1 PB5 GRX1 PWML1 PIO GETH CM – VDDIOP1 PB6 GRX2 TD1 PIO GETH CM – VDDIOP1 PB7 GRX3 RK1 PIO GETH CM – VDDIOP1 PB8 GTXCK PWMH2 PIO GETH CM – VDDIOP1 PB9 GTXEN PWML2 PIO GETH CM – VDDIOP1 PB10 GTXER RF1 PIO VDDIOP1 PB11 GRXCK RD1 PIO VDDIOP1 PB12 GRXDV PWMH3 PIO VDDIOP1 PB13 GRXER PWML3 PIO VDDIOP1 PB14 GCRS CANRX1 PIO – CANRX1 VDDIOP1 PB15 GCOL CANTX1 PIO – CANTX1 VDDIOP1 PB16 GMDC PIO PU GETH CM – VDDIOP1 PB17 GMDIO PIO PU GETH CM – VDDIOP1 PB18 G125CK PIO PU GETH CM – VDDIOP1 PB19 MCI1_CDA GTX4 PIO – MCI1_CDA VDDIOP1 PB20 MCI1_DA0 GTX5 PIO – MCI1_DA0 VDDIOP1 PB21 MCI1_DA1 GTX6 PIO – MCI1_DA1 VDDIOP1 PB22 MCI1_DA2 GTX7 PIO – MCI1_DA2 VDDIOP1 PB23 MCI1_DA3 GRX4 PIO – MCI1_DA3 VDDIOP1 PB24 MCI1_CK GRX5 PIO – MCI1_CK VDDIOP1 PB25 SCK1 GRX6 PIO VDDIOP1 PB26 CTS1 GRX7 PIO – CTS1 VDDIOP1 PB27 RTS1 PWMH1 PIO – RTS1 VDDIOP1 PB28 RXD1 PIO PU – RXD1 VDDIOP1 PB29 TXD1 PIO PU – TXD1 VDDIOP0 PB30 DRXD PIO PU – DRXD (DBGU) VDDIOP0 PB31 DTXD PIO PU – DTXD (DBGU) – SAMA5-MB PWR_MCI0 GETH CM – GETH CM – PWR_MCI1 RX_DV (KSZ9021) INT_GETH0 – SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 90 Table 5-21. PIO C Pin Assignment and Signal Description Power Rail Signal Signal Signal Signal SAMA5-MB VDDIOP0 PC0 ETX0 TIOA3 PIO ETX0 – VDDIOP0 PC1 ETX1 TIOB3 PIO ETX1 – VDDIOP0 PC2 ERX0 TCLK3 PIO ERX0 – VDDIOP0 PC3 ERX1 TIOA4 PIO ERX1 – VDDIOP0 PC4 ETXEN TIOB4 PIO ETXEN – VDDIOP0 PC5 ECRSDV TCLK4 PIO ECRSDV – VDDIOP0 PC6 ERXER TIOA5 PIO ERXER – VDDIOP0 PC7 EREFCK TIOB5 PIO EREFCK – VDDIOP0 PC8 EMDC TCLK5 PIO EMDC – VDDIOP0 PC9 EMDIO PIO PU EMDIO – VDDIOP0 PC10 MCI2_CDA LCDDAT20 PIO LCDDAT20 – VDDIOP0 PC11 MCI2_DA0 LCDDAT19 PIO LCDDAT19 – VDDIOP0 PC12 MCI2_DA1 TIOA1 LCDDAT18 LCDDAT18 – VDDIOP0 PC13 MCI2_DA2 TIOB1 LCDDAT17 LCDDAT17 – VDDIOP0 PC14 MCI2_DA3 TCLK1 LCDDAT16 LCDDAT16 – VDDIOP0 PC15 MCI2_CK PCK2 LCDDAT21 LCDDAT21 VDDIOP0 PC16 TK0 PIO PU TK0 Audio – VDDIOP0 PC17 TF0 PIO PU TF0 Audio – VDDIOP0 PC18 TD0 PIO PU TD0 Audio – VDDIOP0 PC19 RK0 PIO PU RK0 Audio – VDDIOP0 PC20 RF0 PIO PU RF0 Audio – VDDIOP0 PC21 RD0 PIO PU RD0 Audio – VDDIOP0 PC22 SPI1_MISO PIO PU SPI1_MISO SPI LCD VDDIOP0 PC23 SPI1_MOSI PIO PU SPI1_MOSI SPI LCD VDDIOP0 PC24 SPI1_SPCK PIO PU SPI1_SPCK SPI LCD VDDIOP0 PC25 SPI1_NPCS0 PIO PU SPI1_NPCS0 VDDIOP0 PC26 SPI1_NPCS1 TWD1 ISI_D11 ISI_D11 TWI LCD VDDIOP0 PC27 SPI1_NPCS2 TWCK1 ISI_D10 ISI_D10 TWI LCD VDDIOP0 PC28 SPI1_NPCS3 PWMFI0 ISI_D9 ISI_D9 SPI LCD VDDIOP0 PC29 URXD0 PWMFI2 ISI_D8 ISI_D8 HDMI_INT VDDIOP0 PC30 UTXD0 ISI_PCK PIO ISI_PCK VDDIOP0 PC31 FIQ PWMFI1 PIO ISI_MCK – – – Reset_HDMI SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 91 Table 5-22. PIO D Pin Assignment and Signal Description Power Rail Signal Signal Signal Signal SAMA5-MB VDDIOP1 PD0 MCI0_CDA PIO PU – MCI0_CDA VDDIOP1 PD1 MCI0_DA0 PIO PU – MCI0_DA0 VDDIOP1 PD2 MCI0_DA1 PIO PU – MCI0_DA1 VDDIOP1 PD3 MCI0_DA2 PIO PU – MCI0_DA2 VDDIOP1 PD4 MCI0_DA3 PIO PU – MCI0_DA3 VDDIOP1 PD5 MCI0_DA4 TIOA0 PWMH2 – MCI0_DA4 VDDIOP1 PD6 MCI0_DA5 TIOB0 PWML2 – MCI0_DA5 VDDIOP1 PD7 MCI0_DA6 TCLK0 PWMH3 – MCI0_DA6 VDDIOP1 PD8 MCI0_DA7 PWML3 PIO – MCI0_DA7 VDDIOP1 PD9 MCI0_CK PIO PU – MCI0_CK VDDIOP1 PD10 SPI0_MISO PIO PU CM_SerFlash – VDDIOP1 PD11 SPI0_MOSI PIO PU CM_SerFlash – VDDIOP1 PD12 SPI0_SPCK PIO PU CM_SerFlash – VDDIOP1 PD13 SPI0_NPCS0 PIO PU CM_SerFlash – VDDIOP1 PD14 SCK0 SPI0_NPCS1 CANRX0 – CANRX0 VDDIOP1 PD15 CTS0 SPI0_NPCS2 CANTX0 – CANTX0 VDDIOP1 PD16 RTS0 SPI0_NPCS3 PWMFI3 VDDIOP1 PD17 RXD0 PIO PU – MCI0_CD VDDIOP1 PD18 TXD0 PIO PU – MCI1_CD VDDIOP1 PD19 ADTRG PIO PU – ADTRG (HSYNC) VDDANA PD20 AD0 PIO PU – LCD TSC VDDANA PD21 AD1 PIO PU – LCD TSC VDDANA PD22 AD2 PIO PU – LCD TSC VDDANA PD23 AD3 PIO PU – LCD TSC VDDANA PD24 AD4 PIO PU – LCD TSC VDDANA PD25 AD5 PIO PU – EN5V_USBA VDDANA PD26 AD6 PIO PU – EN5V_USBB VDDANA PD27 AD7 PIO PU – EN5V_USBC VDDANA PD28 AD8 PIO PU – OVCUR_USB VDDANA PD29 AD9 PIO PU – VBUS_SENSE VDDANA PD30 AD10 PCK0 PIO VDDANA PD31 AD11 PCK1 PIO INT_AUDIO MCLK_AUDIO – – MCLK_HDMI ISI_MCK SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 92 Table 5-23. PIO E Pin Assignment and Signal Description Power Rail Signal Signal Signal VDDIOM PE0 A0/NBS0 I VDDIOM PE1 A1 I VDDIOM PE2 A2 VDDIOM PE3 VDDIOM SAMA5-CM SAMA5-MB – – NOR – – I NOR – – A3 I NOR – – PE4 A4 I NOR – – VDDIOM PE5 A5 I NOR – – VDDIOM PE6 A6 I NOR – – VDDIOM PE7 A7 I NOR – – VDDIOM PE8 A8 I NOR – – VDDIOM PE9 A9 I NOR – – VDDIOM PE10 A10 I NOR – – VDDIOM PE11 A11 I NOR – – VDDIOM PE12 A12 I NOR – – VDDIOM PE13 A13 I NOR – – VDDIOM PE14 A14 I NOR – – VDDIOM PE15 A15 SCK3 NOR – – VDDIOM PE16 A16 CTS3 NOR – – VDDIOM PE17 A17 RTS3 NOR – – VDDIOM PE18 A18 RXD3 NOR – – VDDIOM PE19 A19 TXD3 NOR – – VDDIOM PE20 A20 SCK2 NOR – – VDDIOM PE21 A21/NANDALE I NOR / NAND – – VDDIOM PE22 A22/NANDCLE I NOR / NAND – – VDDIOM PE23 A23 CTS2 NOR – – VDDIOM PE24 A24 RTS2 Power LED ISI_RST – VDDIOM PE25 A25 RXD2 1-Wire / User LED 1-Wire – VDDIOM PE26 NCS0 TXD2 CS NOR VDDIOM PE27 NCS1 TIOA2 – PB_USER1 LCDDAT22 VDDIOM PE28 NCS2 TIOB2 – ZB_SLPTR LCDDAT23 VDDIOM PE29 NWR1/NBS1 TCLK2 – ZB_RST VDDIOM PE30 NWAIT I – ZB_IRQ1 INT_ETH1 VDDIOM PE31 IRQ PWML1 – ZB_IRQ0 HDMI_INT – – – SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 93 5.4.19 IO Expansion Port J1 Figure 5-41. IO Expansion Socket J1 Table 5-24. IO Expansion Socket J1 HE10 Male 2*20 Signal Descriptions Signal Pin Number Signal VDDIOP0 / 5V 1 2 VDDIOP0 / 5V GND 3 4 GND PA0 5 6 PA16 PA1 7 8 PA17 PA2 9 10 PA18 PA3 11 12 PA19 PA4 13 14 PA20 PA5 15 16 PA21 PA6 17 18 PA22 PA7 19 20 PA23 PA8 21 22 PA24 PA9 23 24 PA25 PA10 25 26 PA26 PA11 27 28 PA27 PA12 29 30 PA28 PA13 31 32 PA29 PA14 33 34 PA30 PA15 35 36 PA31 GND 37 38 GND VDDIOP0 39 40 VDDIOP0 SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 94 5.4.20 IO Expansion Port J2 Figure 5-42. IO Expansion Socket J2 Table 5-25. Expansion Socket J2 HE10 Male 2*20 Signal Descriptions Signal Pin Number Signal VDDIOP0 / 5V 1 2 VDDIOP0 / 5V GND 3 4 GND PC0 5 6 PC16 PC1 7 8 PC17 PC2 9 10 PC18 PC3 11 12 PC19 PC4 13 14 PC20 PC5 15 16 PC21 PC6 17 18 PC22 PC7 19 20 PC23 PC8 21 22 PC24 PC9 23 24 PC25 PC10 25 26 PC26 PC11 27 28 PC27 PC12 29 30 PC28 PC13 31 32 PC29 PC14 33 34 PC30 PC15 35 36 PC31 GND 37 38 GND VDDIOP0 39 40 VDDIOP0 SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 95 5.4.21 IO Expansion Port J3 Figure 5-43. IO Expansion Socket J3 Table 5-26. Expansion Socket J3 HE10 Male 2*20 Signal Descriptions Signal Pin Number Signal VDDIOP0 / 5V 1 2 VDDIOP0 / 5V GND 3 4 GND PB10 5 6 PB31 PB12 7 8 PE23 PB14 9 10 PE24 PB15 11 12 PE25 PB19 13 14 PE26 PB20 15 16 PE29 PB21 17 18 PE30 PB22 19 20 PE31 PB23 21 22 PD10 PB24 23 24 PD11 PB25 25 26 PD12 PB26 27 28 PD13 PB27 29 30 PD14 PB28 31 32 PD15 PB29 33 34 PD19 PB30 35 36 PD31 GND 37 38 GND VDDIOP0 39 40 VDDIOP0 SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 96 5.4.22 SODIMM Card Edge Socket The SAMA5D3 series-EK implements a SODIMM200 standard connector for to interface to the CM board. Note this is not an industry standard pinout and is unlikely to be compatible with off-the-shelf SODIMM. Figure 5-44. SODIMM200 Socket CON1 SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 97 Table 5-27. PIOC SODIMM200 CON1 Signal Descriptions PIOB PIOA SODIMM 200 Front Side A B PIOA PIOB PIOC Back Side – – VCC 5V 1 2 VCC 5V – – – – VCC 5V 3 4 VCC 5V – – – – GND 5 6 VBAT – – – – CTS2 PE23 7 8 PE29 NWR1/NBS1 TCLK2 – – – RTS2 PE24 9 10 PE30 NWAIT – – – – RXD2 PE25 11 12 PE31 IRQ PWML1 – – – TXD2 PE26 13 14 – GND – – – VDDIOM 15 16 – – SPI1_NPCS0 PC25 17 18 PC24 – – SPI1_MOSI PC23 19 20 – – RD0 PC21 21 – – GND – – TD0 – – – – – – SPI1_SPCK – – PC22 SPI1_MISO – – 22 PC20 RF0 – – 23 24 PC19 RK0 – – PC18 25 26 PC17 TF0 – – TK0 PC16 27 28 PC9 EMDIO PIO – TCLK5 EMDC PC8 29 30 PC7 EREFCK TIOB5 – – TIOA5 ERXER PC6 31 32 GND – – TIOB4 ETXEN PC4 33 34 PC5 ECRSDV TCLK4 – – TCLK3 ERX0 PC2 35 36 PC3 ERX1 TIOA4 – – TIOA3 ETX0 PC0 37 38 PC1 ETX1 TIOB3 – Enable_0 39 40 Enable_1 CS Boot Disable – – Power Enable VDDIOM – – KEY – – VCC 3V3 41 42 VCC 3V3 – – – – VCC 3V3 43 44 VCC 3V3 – – – – NC 45 46 NC – – – – NC 47 48 ADVREF – – LCDDAT22 – – Enable_2 – Enable_3 TIOA2 NCS1 PE27 49 50 PE28 NCS2 TIOB2 LCDDAT23 LCDDAT20 MCI2_CDA PC10 51 52 PC11 MCI2_DA0 LCDDAT19 PIO 53 54 PC13 MCI2_DA2 TIOB1 LCDDAT17 PCK2 LCDDAT21 – – GND LCDDAT18 TIOA1 MCI2_DA1 PC12 55 56 PC15 MCI2_CK LCDDAT16 TCLK1 MCI2_DA3 PC14 57 58 PC26 SPI1_NPCS1 SPI1_NPCS2 PC27 59 60 PC28 SPI1_NPCS3 ISI_D10 – ISI_D8 PWMFI2 URXD0 PC29 61 62 – – PWMFI1 FIQ PC31 63 64 PC30 65 66 67 68 VDDIOP0 – – LCDDAT0 PA0 – PWMFI0 ISI_D9 – GND UTXD0 ISI_D11 ISI_PCK – – VDDIOP0 PA1 LCDDAT1 – SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 – 98 Table 5-27. PIOC SODIMM200 CON1 Signal Descriptions PIOB PIOA – – LCDDAT2 – – GND – – LCDDAT5 – – – SODIMM 200 PIOA PIOB PIOC 69 70 PA3 LCDDAT3 – – 71 72 PA4 LCDDAT4 – – PA5 73 74 PA6 LCDDAT6 – – LCDDAT7 PA7 75 76 PA8 LCDDAT8 – – – LCDDAT9 PA9 77 78 PA10 LCDDAT10 – – – – LCDDAT11 PA11 79 80 GND – – – – LCDDAT12 PA12 81 82 PA13 LCDDAT13 – – – – LCDDAT14 PA14 83 84 PA15 LCDDAT15 – – PA2 – – – ISI_D0 LCDDAT16 PA16 85 86 PA17 LCDDAT17 ISI_D1 ISI_D2 TWD2 LCDDAT18 PA18 87 88 PA19 LCDDAT19 TWCK2 ISI_D3 89 90 PA20 LCDDAT20 PWMH0 ISI_D4 PWMH1 ISI_D6 – – ISI_D5 PWML0 LCDDAT21 PA21 91 92 PA22 LCDDAT22 ISI_D7 PWML1 LCDDAT23 PA23 93 94 PA24 LCDPWM – – – – LCDDISP PA25 95 96 PA26 LCDVSYNC – – – – LCDHSYNC PA27 97 98 GND – – – – LCDPCK PA28 99 100 PA29 LCDDEN – – TWD0 PA30 101 102 PA31 TWCK0 103 104 105 106 PD31 AD11 107 108 PD29 AD9 – – ISI_VSYNC – GND URXD1 VDDANA – PCK0 AD10 PD30 – UTXD1 ISI_HSYNC VDDANA – PCK1 – – GND – – AD8 PD28 109 110 PD27 AD7 – – – – AD6 PD26 111 112 PD25 AD5 – – – – AD4 PD24 113 114 PD23 AD3 – – – – AD2 PD22 115 116 GND – – – – AD0 PD20 117 118 PD21 AD1 – – – – TXD0 PD18 119 120 PD19 ADTRG – – PWMFI3 SPI0_NPCS3 RTS0 PD16 121 122 PD17 RXD0 PIO CANRX0 SPI0_NPCS1 SCK0 PD14 123 124 PD15 CTS0 SPI0_NPCS2 – – GND 125 126 PD13 SPI0_NPCS0 – – – – SPI0_SPCK PD12 127 128 PD11 SPI0_MOSI – – – – SPI0_MISO PD10 129 130 PD9 MCI0_CK – – PD7 MCI0_DA6 – PIO PWML3 MCI0_DA7 PD8 131 132 PWML2 TIOB0 MCI0_DA5 PD6 133 134 PWMH2 TIOA0 MCI0_DA4 PD5 135 136 – TCLK0 CANTX0 PWMH3 GND – – PD4 MCI0_DA3 – – – – MCI0_DA2 PD3 137 138 PD2 MCI0_DA1 – – – – MCI0_DA0 PD1 139 140 PD0 MCI0_CDA – – 141 142 VDDIOP1 VDDIOP1 SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 99 Table 5-27. PIOC SODIMM200 CON1 Signal Descriptions PIOB – PIOA – SODIMM 200 – GND PIOA PIOB PIOC 143 144 PB13 GRXER PWML3 – – RF1 GTXER PB10 145 146 PB12 GRXDV PWMH3 – – CANRX1 GCRS PB14 147 148 PB15 GCOL CANTX1 – – GTX4 MCI1_CDA PB19 149 150 PB20 MCI1_DA0 GTX5 – – GTX6 MCI1_DA1 PB21 151 152 PB22 MCI1_DA2 GTX7 – – GRX4 MCI1_DA3 PB23 153 154 – – GRX5 MCI1_CK PB24 155 156 PB25 SCK1 GRX6 – – – – GND – GND – 157 158 PB27 RTS1 PWMH1 – PIO – – USB A USBA_DP – 159 160 PB29 TXD1 – USB A USBA_DM – 161 162 PB31 DTXD – – GND – 163 164 PB30 DRXD – – – – – USB B USBB_DP – 165 166 PB26 CTS1 GRX7 – – USB B USBB_DM – 167 168 PB28 RXD1 PIO – GND – 169 170 – – – GND – – – USB C USBC_DP – 171 172 DIB DIBP – – – USB C USBC_DM – 173 174 DIB DIBN – – GND_ETH – 175 176 – GND – – – – – GIGA_ETH ETH0_TX1+ – 177 178 – JTAGSEL SYSC – – GIGA_ETH ETH0_TX1- – 179 180 – WKUP SYSC – – GIGA_ETH ETH0_RX1+ – 181 182 – SHDN SYSC – – GIGA_ETH ETH0_RX1- – 183 184 – BMS RSTJTAG – GND_ETH – 185 186 – nRST SYSC – – – – GIGA_ETH ETH0_TX2+ – 187 188 – nTRST RSTJTAG – – GIGA_ETH ETH0_TX2- – 189 190 – TDI RSTJTAG – – GIGA_ETH ETH0_RX2+ – 191 192 – TCK RSTJTAG – – GIGA_ETH ETH0_RX2- – 193 194 – TMS RSTJTAG – – – GND – 195 196 – TDO RSTJTAG – – – LED2 – 197 198 – RTCK RSTJTAG – – – LED1 – 199 200 – GND – SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 – 100 5.5 Main Board Schematics This section contains the following schematics:  Block diagram  General information  SODIMM  Power supply  HSMCI  CAN & ZigBee & USART1  Audio  Smart DAA  HDMI  ETH  USB interface  Miscellaneous  LCD and ISI  On-board JTAG interface SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 101 5 4 3 2 1 5V Sheet 4 POWER SUPPLY Sheet 4 Battery 3V3 INPUT Sheet 12 ANALOG 3V USBA D VBAT USBB HOST & DEVICE HOST ANALOG Reference 3V RJ11 USBC D SmartDAA HOST Sheet 8 Sheet 11 USB A,B,C SmartDAA ICE USB_B PORT SAM3U DBGU USER INTERFACE C O N N E C T O R C ICE HE10 ICE HE 14 Sheet 14 C Sheet 12 HE 14 LCD INTERFACE ONE WIRE EEPROM ISI Sheet 13 HDMI INTERFACE PIO A,...E PIO A,...E HDMI Type A S O D I M M Sheet 9 PIO A PIO CONNECTOR PIO C PIO CONNECTOR 10/100/1000 ETH0 PIO CONNECTOR PIO B&D&E 10/100 FAST EHT1 RJ 45 RJ 45 Sheet 10 Sheet 10 ZIGBEE INTERFACE AUDIO OUT MIC1 MIC2 USRAT1 Sheet 7 B CARD READER CARD READER MMC SD SDIO Sheet 6 MMC SD SDIO B RS232 HE10 CAN1 RJ12 CAN0 Sheet 5 Sheet 3 A A C B A REV SAMA5D3x-MB MODIF. Derek Derek Derek 30-Sep-12 30-Mar-12 11-Nov-11 DES. DATE X.X X.X X.X DATE REV. SHEET 1/1 SCALE C BLOCK Diagram This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 3 2 1 XX-XXX-XX XX-XXX-XX XX-XXX-XX VER. 1 14 5 4 3 REVISION HISTORY REV DATA 1 SAMA5D3x config SCHEMATICS CONVENTIONS NOTE SAMA5D33 SAMA5D31 A 2 2011.11 ORIGINAL RELEASED B 2012.03 SECOND RELEASED C 2012.10 THIRD RELEASED SAMA5D34 (1) Resistance Unit: "K" is "Kohm", "R" is "Ohm SAMA5D35 CAN0 (2) "DNP" means the component is not populated by default CAN1 GMAC EMAC HSMCI2 D PAGE 3 4 5 6 USART0 USART1 REFERENCE DEFAULT JP1 1-2 VDDIOP0 or 5V selection for J1 FUNCTION JP2 1-2 VDDIOP0 or 5V selection for J2 JP3 1-2 VDDIOP1 or 5V selection for J3 4 TP1, TP2 GND JP9 OPEN Default boot on embedded ROM,Close boot on external memory 4 TP3 5V JP4 CLOSE Backup supply on/off 4 TP4 3V3 JP5 CLOSE Force power on function 4 TP5 VDDIOP0 JP6 CLOSE MCI0 write protect select 4 TP6 VDDIOP1 JP7 CLOSE CAN0 diff termination select 4 TP7 VDDIOM JP8 CLOSE CAN1 diff termination select 4 TP8 VDDANA Zigbee Power on/off select JP10 OPEN 12 JP14 1-2 ADVREF input selection 14 JP15 OPEN JTAG Enabled,close to disable 14 JP16 OPEN CDC Enabled,close to disable 11 JP17 OPEN Enable LCD for D31,D33,D34 CLOSE Disable LCD for D35 TC1 PAGE Block Diagram 2 Describe 3 SODIMM 4 POWER SUPPLY 5 HSMCI 6 CAN & ZIGBEE &USART1 7 AUDIO 8 SmartDAA 9 HDMI 10 ETH 11 USB Interface 12 Miscellaneous 13 LCD&ISI 14 Segger-SAM3U REFERENCE REFERENCE FUNCTION FUNCTION 3 R6,R51,R50,R120 Optional PD10,PD11,PD12,PD13 from MB 5 R58 Optional for MCI0 Power supply mode R121 Optional for MCI1 Power supply mode 6 7 DESCRIPTION 1 PAGE DEFAULT NO POPULATE PARTS TABLE OF CONTENTS PAGE TEST POINT ISI C B D LCDC JUMPER and SOLDERDROP 9 R52, R53,R55,R56,R57,R82,JP10 Optional Zigbee R132,R133 Debug or USART1 option C89,C90,R118,R119,J26 Optional Audio Line out,mic in R80,R81 Optional MIC level setting R230 Optional audio TK L38,L39,L40,L41 Optional HDMI EMI filter R89 HDMI chip I2C address setting R266 Optional for I2S PCLK R42 Optional for LCD PCLK 10 R162,R170,R171,R172,R176,R177,C122,C123, Optional for KSZ8041NL 12 R144 Optional pull up for DS28EC20P R127 Optional for ADC triger 13 14 C R79, R106,R107,R109,R113,R110,R112,R111,J9 Optional JTAG R54 SAM3U JTAG selection R63 5V Option D11,D12 USB ESD protect option R186 Main 3V3 Optional for VCC_3V3_DEBUG B PIO MUXING PIOA A USAGE PIOA USAGE PIOB USAGE PIOB USAGE PA0 LCDD0 PA16 ISI_D0 PB0 PA1 LCDD1 PA17 ISI_D1 PB1 PA2 LCDD2 PA18 ISI_D2 PB2 PB18 PA3 LCDD3 PA19 ISI_D3 PB3 PB19 MCI1_CDA PA4 LCDD4 PA20 ISI_D4 PB4 PB20 PA5 LCDD5 PA21 ISI_D5 PB5 PA6 LCDD6 PA22 ISI_D6 PA7 LCDD7 PA23 ISI_D7 PA8 LCDD8 PA24 PA9 LCDD9 PA10 PIOC USAGE PIOC USAGE PIOD USAGE PIOD USAGE PIOE USAGE PIOE USAGE PC0 E1_TX0 PC16 TK0 PD0 MCI0_CDA PD16 INT_AUDIO PE0 PE16 PC1 E1_TX1 PC17 TF0 PD1 MCI0_DA0 PD17 MCI0_CD PE1 PE17 PC2 E1_RX0 PC18 TD0 PD2 MCI0_DA1 PD18 MCI1_CD PE2 PE18 PC3 E1_RX1 PC19 RK0 PD3 MCI0_DA2 PD19 ADTRG PE3 PE19 MCI1_DA0 PC4 E1_TXEN PC20 RF0 PD4 MCI0_DA3 PD20 AD0_XP PE4 PE20 PB21 MCI1_DA1 PC5 E1_CRSDV PC21 RD0 PD5 MCI0_DA4 PD21 AD1_XM PE5 PE21 PB6 PB22 MCI1_DA2 PC6 E1_RXER PC22 SPI1_MISO PD6 MCI0_DA5 PD22 AD2_YP PE6 PE22 PB7 PB23 MCI1_DA3 PC7 E1_TXCK PC23 SPI1_MOSI PD7 MCI0_DA6 PD23 AD3_YM PE7 PE23 LCDPW M PB8 PB24 MCI1_CK PC8 E1_MDC PC24 SPI1_SPCK PD8 MCI0_DA7 PD24 AD4_LR PE8 PE24 ISI_RST PA25 LCDDISP PB9 PB25 PC9 E1_MDIO PC25 SPI1_NPCS0 PD9 MCI0_CK PD25 EN5V_HDA PE9 PE25 ONE_WIRE LCDD10 PA26 LCDVSYNC PB10 PA11 LCDD11 PA27 LCDHSYNC PB11 PA12 LCDD12 PA28 LCDPCK PB12 PA13 LCDD13 PA29 LCDDEN PB13 PA14 LCDD14 PA30 TW D0 ISI_VSYNC PB14 PA15 LCDD15 PA31 TW CK0 ISI_HSYNC PB15 PB16 PB17 PB26 CTS1 PC10 LCDD20 PC26 TWD1 ISI_D11 PD10 PD26 EN5V_HDB PE10 PE26 PB27 RTS1 PC11 LCDD19 PC27 TWCK1 ISI_D10 PD11 PD27 EN5V_HDC PE11 PE27 PB_USER1 LCDD22 PB28 RXD1 PC12 LCDD18 PC28 SPI1_NPCS3 ISI_D9 PD12 PD28 OVCUR_USB PE12 PE28 ZB_SLPTR LCDD23 PB29 TXD1 PC13 LCDD17 PC29 HDMI_INT ISI_D8 PD13 PD29 VBUS_SENSE PE13 PE29 ZB_RST CANRX1 PB30 DRXD PC14 LCDD16 PC30 ISI_PCK PD14 CANRX0 PD30 PCK0(Audio,HDMI) PE14 PE30 ZB_IRQ1 CANTX1 PB31 DTXD PC15 LCDD21 PC31 PD15 CANTX0 PD31 PCK1(ISI_MCK) PE15 PE31 ZB_IRQ0 PW R_MCI0 PW R_MCI1 RESET_HDMI C B A REV SAMA5D3x-MB SCALE Derek Derek Derek MODIF. DES. 1/1 This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 4 3 2 30-Sep-12 30-Mar-12 11-Nov-11 DATE X.X X.X X.X 1 XX-XXX-XX XX-XXX-XX XX-XXX-XX VER. DATE REV. SHEET C Describe 5 A INT_ETH1 2 14 5 4 3 2 1 VDDIOP0 VDDIOP0 SIP2 1 2 13 12,13 PE23 PE24 PE25 PE26 ISI_RST ONE_WIRE PE24 PE25 VDDIOM D 13,6 7 PC23 PC21 7,9 7,9 10 10 10 10 10 4 PC18 PC16 PC8 PC6 PC4 PC2 PC0 PWR_EN SPI1_MOSI RD PC25 PC23 PC21 TD TK E1_MDC E1_RXER E1_TXEN E1_RX0 E1_TX0 PC18 PC16 PC8 PC6 PC4 PC2 PC0 VCC5V_1 VCC5V_3 GND1 PE23 PE24 PE25 PE26 VDDIOM_1 PC25 PC23 PC21 GND2 PC18 PC16 PC8 PC6 PC4 PC2 PC0 Enable_0 3V3 12,13,9 13,9 PE27 PC10 13,9 13,9 13 13,9 9 PC12 PC14 PC27 PC29 PC31 13,9 13,9 PA0 PA2 13,9 13,9 13,9 13,9 13,9 13,9 13 13 PA5 PA7 PA9 PA11 PA12 PA14 PA16 PA18 13 13 13 13,9 13,9 13,7,9 PA21 PA23 PA25 PA27 PA28 PA30 PB_USER1 TWCK1 HDMI_INT LCDD22 LCDD20 PE27 PC10 LCDD18 LCDD16 ISI_D10 ISI_D8 RESET_HDMI PC12 PC14 PC27 PC29 PC31 VDDIOP0 C LCDD0 LCDD2 PA0 PA2 LCDD5 LCDD7 LCDD9 LCDD11 LCDD12 LCDD14 PA5 PA7 PA9 PA11 PA12 PA14 PA16 PA18 ISI_D0 ISI_D2 ISI_D5 ISI_D7 ISI_VSYNC LCDDISP LCDHSYNC LCDPCK TWD0 VDDANA 7,9 PD30 11 11 13 13 13 5 7 6 PD28 PD26 PD24 PD22 PD20 PD18 PD16 PD14 PD12 R50 PD10 R6 B 5 5 5 5 5 PD8 PD6 PD5 PD3 PD1 PA21 PA23 PA25 PA27 PA28 PA30 PCK0 PD30 OVCUR_USB EN5V_HDB AD4_LR AD2_YP AD0_XP MCI1_CD INT_AUDIO CANRX0 PD28 PD26 PD24 PD22 PD20 PD18 PD16 PD14 22R DNP 22R DNP MCI0_D7 MCI0_D5 MCI0_D4 MCI0_D2 MCI0_D0 PD8 PD6 PD5 PD3 PD1 VDDIOP1 5 13,6 5 5 5 5 A PB10 PB14 PB19 PB21 PB23 PB24 11 11 USBA_DP USBA_DM 11 11 USBB_DP USBB_DM 11 11 10,3 10 10 10 10 10,3 10 10 10 10 10 10 USBC_DP USBC_DM ETH0_GND ETH0_TX1+ ETH0_TX1ETH0_RX1+ ETH0_RX1ETH0_GND ETH0_TX2+ ETH0_TX2ETH0_RX2+ ETH0_RX2ETH0_LED2 ETH0_LED1 PWR_MCI0 CANRX1 MCI1_CDA MCI1_DA1 MCI1_DA3 MCI1_CK PB10 PB14 PB19 PB21 PB23 PB24 1 VCC5V_2 VCC5V_4 VBAT PE29 PE30 PE31 GND13 VDDIOM_2 PC24 PC22 PC20 PC19 PC17 PC9 PC7 GND14 PC5 PC3 PC1 Enable_1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PE29 PE30 PE31 VCC3V3_1 VCC3V3_3 Enable_2 NC1 PE27 PC10 GND3 PC12 PC14 PC27 PC29 PC31 VDDIOP0_1 PA0 PA2 GND4 PA5 PA7 PA9 PA11 PA12 PA14 PA16 PA18 GND5 PA21 PA23 PA25 PA27 PA28 PA30 VDDANA_1 PD30 GND6 PD28 PD26 PD24 PD22 PD20 PD18 PD16 PD14 GND7 PD12 PD10 PD8 PD6 PD5 PD3 PD1 VDDIOP1_1 GND8 PB10 PB14 PB19 PB21 PB23 PB24 GND23 USBA_DP USBA_DM GND10 USBB_DP USBB_DM GND11 USBC_DP USBC_DM GND_ETH1 ETH0_TX1+ ETH0_TX1ETH0_RX1+ ETH0_RX1GND_ETH2 ETH0_TX2+ ETH0_TX2ETH0_RX2+ ETH0_RX2GND12 LED2 LED1 ZB_RSTN ZB_IRQ1 ZB_IRQ0 INT_ETH1 VBAT PE29 PE30 PE31 12,4 13,6 10,13,6 13,6 PC24 PC22 PC20 PC19 PC17 PC9 PC7 13,6 13,6 7 7 7,9 10 10 J1 MD2X20-H SPI1_SPCK SPI1_MISO RF RK TF E1_MDIO E1_TXCK PC5 PC3 PC1 E1_CRSDV E1_RX1 E1_TX1 10 PC5 10 PC3 PC1 10 CS_BOOT_DISABLE 12 3V3 VCC3V3_2 VCC3V3_4 Enable_3 ADVREF PE28 PC11 PC13 PC15 PC26 PC28 GND15 PC30 VDDIOP0_2 PA1 PA3 PA4 PA6 PA8 PA10 GND16 PA13 PA15 PA17 PA19 PA20 PA22 PA24 PA26 GND17 PA29 PA31 VDDANA_2 PD31 PD29 PD27 PD25 PD23 GND18 PD21 PD19 PD17 PD15 PD13 PD11 PD9 PD7 GND19 PD4 PD2 PD0 VDDIOP1_2 NC2 PB12 PB15 PB20 PB22 GND20 PB25 PB27 PB29 PB31 PB30 PB26 PB28 GND9 DIBP DIBN GND21 JTAGSEL W KUP SHDN BMS nRST nTRST TDI TCK TMS TDO RTCK GND22 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 VDDIOM PC24 PC22 PC20 PC19 PC17 PC9 PC7 KEY 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 3 2 5V J12 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 VDDIOP0 VDDIOP0 VDDIOP0 PE28 PC11 PC13 PC15 PC26 PC28 LCDD23 ZB_SLPTR LCDD19 LCDD17 LCDD21 TWD1 ISI_D11 SPI1_NPCS3 ISI_D9 PC30 ISI_PCK ADVREF PE28 PC11 PC13 PC15 PC26 PC28 12 13,6,9 13,9 13,9 13,9 13 13,6 PC30 13 LCDD1 LCDD3 LCDD4 LCDD6 LCDD8 LCDD10 PA13 PA15 PA17 PA19 PA20 PA22 PA24 PA26 LCDD13 LCDD15 PA29 PA31 LCDDEN TWCK0 ISI_D1 ISI_D3 ISI_D4 ISI_D6 LCDPWM LCDVSYNC PA1 PA3 PA4 PA6 PA8 PA10 13,9 13,9 13,9 13,9 13,9 13,9 PA13 PA15 PA17 PA19 PA20 PA22 PA24 PA26 13,9 13,9 13 13 13 13 13 13,9 PA29 PA31 13,9 13,7,9 PD31 PD29 PD27 PD25 PD23 PCK1(ISI_MCK) VBUS_SENSE EN5V_HDC EN5V_HDA AD3_YM PD31 PD29 PD27 PD25 PD23 13 11 11 11 13 PD21 PD19 PD17 PD15 AD1_XM PD21 PD19 PD17 PD15 13 13 5 6 PD9 PD7 5 5 PD4 PD2 PD0 5 5 5 PB12 PB15 PB20 PB22 5 13,6 5 5 PB27 PB29 PB31 PB30 PB26 PB28 6 6 14,6 14,6 6 6 ISI_HSYNC VDDANA MCI0_CD CANTX0 DNP R120 DNP R51 PD9 PD7 MCI0_CK MCI0_D6 PD4 PD2 PD0 MCI0_D3 MCI0_D1 MCI0_CDA VDDIOP1 PB12 PB15 PB20 PB22 PWR_MCI1 CANTX1 MCI1_DA0 MCI1_DA2 PB25 PB27 PB29 PB31 PB30 PB26 PB28 RTS1 TXD1 DTXD DRXD CTS1 RXD1 22R PD13 22R PD11 5V JP2 1 3 J2 MD2X20-H VDDIOP0 PA1 PA3 PA4 PA6 PA8 PA10 D 2 JP9 BMS 5V 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 VDDIOP0 C VDDIOP0 VDDIOP1 5V JP3 1 3 2 R83 4.7k 5V JP1 JP9 for BMS Config: When Open,BMS=1: Boot on embeded ROM When Close,BMS=0: Boot on External memory DIBP DIBN 8 8 J3 MD2X20-H 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 PB10 PB12 PB14 PB15 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 B PB31 PE23 PE24 PE25 PE26 PE29 PE30 PE31 PD10 PD11 PD12 PD13 PD14 PD15 PD19 PD31 VDDIOM VDDIOM WAKE UP 12 SHDN 4 BMS NRST NTRST TDI TCK TMS TDO RTCK 10,12,14 14 14 14 14 14 14 A 1612618-1 C B A REV SAMA5D3x-MB Derek 30-Sep-12 Derek 30-Mar-12 Derek 11-Nov-11 MODIF. SCALE DES. 1/1 DATE X.X X.X X.X DATE REV. SHEET C SODIMM XX-XXX-XX XX-XXX-XX XX-XXX-XX VER. 3 14 T his agreem ent is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 3 2 1 5 4 3 2 1 1 3V3 J4 D 1 3 2 1 B 2 3 PSG CG1 CG2 CG3 C3 100n DC POWER JACK 5V/2A Input CB D1 5V MN2 BNX002-01 JP4 3 1 BAT54CLT1G 2 VBAT 2 D SIP2 J5 4 5 6 12,3 + C2 33u C1 100n 2 MN1 ZEN056V230A16LS 3 5V_INPUT 1 C4 100n 3V3 3V3 R25 10k 3V3 VOUT = 0.8V x (Rtop + Rbottom)/Rbottom PWR_EN 5V 1 1 2 3 4 POWER_EN 2 R4 100k C6 10u PWR_EN# GND ADJ VOUT NC 10n R2 47k 8 7 6 5 C VDDISI 13 R3 470R R5 15k 4 C8 1u C9 10u D2 Red 1 5 C7 1u PGOOD EN VIN VDD C5 L1 220ohm at 100MHz 1 2 2 Q1 6 Si1563EDH C57 MN3 RT9018B-18GSP 5V C120 1u B R1 100k 3 1 PWR_EN EP Q6 IRLML2402 3 9 C B JP5 2 100n SIP2 FORCE POWER ON TP1 1 C10 2 3 TP2 15p R7 10k 3 R8 10k C22 1u Place C22 near MN3.pin2 5V TP3 3V3 TP4 VDDIOP0 TP5 VDDIOP1 TP6 VDDIOM TP7 VDDANA TP8 SHDN ADHESIVE FEET Z6 A Bumpon Z7 Bumpon Z17 C B A Bumpon REV Z8 Bumpon SAMA5D3x-MB Z9 Derek Derek Derek MODIF. SCALE DES. 30-Sep-12 30-Mar-12 11-Nov-11 DATE 1/1 POWER SUPPLY Bumpon This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 3 2 1 X.X X.X X.X XX-XXX-XX A XX-XXX-XX XX-XXX-XX VER. DATE REV. SHEET C 4 14 5 4 3 VDD_MCI0 2 1 VDD_MCI0 VDDIOP1 RR3 10k JP6 8 7 6 5 1 MCI0 R15 R16 R17 R18 R26 R36 R38 R39 2 C40 R49 10k SIP2 C12 10u 100n 1 2 3 4 68k 68k 68k 68k 68k 68k 68k 68k D PD17 3 3 PD2 PD1 3 PD9 3 3 3 PD0 PD4 PD3 D (MCI0_WP) (MCI0_CD) RR4 (MCI0_CK) 8 7 6 27R 5 (MCI0_CDA) (MCI0_DA3) (MCI0_DA2) 1 RR5 2 3 4 8 27R 7 6 5 C 13 12 11 10 R58 0R DNP 1 PB10 3 VDD_MCI0 27R 8 7 6 5 3 1 2 3 4 (MCI0_DA4) (MCI0_DA5) (MCI0_DA6) (MCI0_DA7) PD5 PD6 PD7 PD8 8 7 6 5 4 3 2 1 9 7SDMM-B0-2211 RR42 3 3 3 3 VDDIOP1 16 15 14 J7 1 2 3 4 (MCI0_DA1) (MCI0_DA0) 2 3 RR4,RR5,RR42 near SODIMM place Q8 IRLML6402 R47 4.7k C SD/MMCPlus CARD INTERFACE - MCI0 VDDIOP1 VDD_MCI1 MCI1 R10 R11 R12 R13 R9 10k R14 10k VDDIOP1 68k 68k 68k 68k PB21 PB20 3 PB24 3 3 3 PB19 PB23 PB22 (MCI1_DA1) (MCI1_DA0) (MCI1_CK) (MCI1_CDA) (MCI1_DA3) (MCI1_DA2) RR1 1 2 3 4 1 2 3 4 RR2 J6 10 8 SW2 7 6 5 4 3 2 1 27R 8 7 6 5 8 7 6 5 27R Micro SD R121 0R DNP 11 12 13 14 C93 10u 9 C11 100n B 2 3 3 (MCI1_CD) 1 PB12 3 VDD_MCI1 3 B PD18 SW1 3 Q9 IRLML6402 R48 4.7k PJS008-2110-0 RR1,RR2 near SODIMM place A A C B A REV SAMA5D3x-MB Derek 30-Sep-12 Derek 30-Mar-12 Derek 11-Nov-11 MODIF. SCALE DES. DATE 1/1 This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 4 3 2 1 XX-XXX-XX XX-XXX-XX XX-XXX-XX VER. DATE REV. SHEET C HSMCI 5 X.X X.X X.X 5 14 5 4 3 CAN INTERFACE CANTX0 PD15 R20 D 3 5 10k 4 CANRX0 PD14 EN VCC R GND 120R VDDIOP0 3 2 C20 100n JP8 13,3 PB15 VDDIOP1 13,3 8 0R 1 R35 CANRX1 PB14 10k R33 10k R37 4 0R EN VCC R GND J27 1 2 3 4 5 6 3V3 5V 120R 7 6 CANH CANL D 5 R34 2 SIP2 RS D C21 10u 1 MN6 R32 CAN0 MJM0606GE06-H SN65HVD234DR CANTX1 1 2 3 4 5 6 3V3 5V 7 6 CANH CANL D 1 J18 2 SIP2 RS 1 0R R40 VDDIOP1 8 10k R19 1 MN5 R21 3 2 JP7 VDDIOP0 3 2 CAN1 MJM0606GE06-H SN65HVD234DR C23 C C24 10u 100n C VDDIOP1 USART1 MN4 3 4.7u VDDIOP1 VCC 100n 23 R22 R23 R24 C15 100n 1 C18 100n 21 GND 19 47k 47k 47k B 3 3 14,3 PB27 PB29 PB31 3 3 14,3 PB26 PB28 PB30 RTS1 TXD1 R27 R28 R132 DTXD 5 R30 R31 R133 DRXD 10 11 12 0R 0R 0R V+ C2+ V- C2- SD C3+ C3- T1IN T2IN T3IN DNP CTS1 RXD1 C1- EN 7 8 9 0R 0R 0R C1+ T1OUT T2OUT T3OUT R1OUT R2OUT R3OUT R1IN R2IN R3IN 6 C16 100n C17 100n C19 100n 20 2 J8 1 6 2 7 3 8 4 9 5 4 24 22 18 17 16 15 14 13 RTSC1 TXDC1 R29 0R CTSC1 RXDC1 ADM3312EARU DNP 11 C14 10 C13 B L5 220ohm at 100MHz 1 2 EARTH_RS232 ZIGBEE INTERFACE DNP DNP DNP DNP 13,3 10,13,3 13,3 13,3 A PE29 PE30 PC28 PC22 ZB_RSTN ZB_IRQ1 SPI1_NPCS3 SPI1_MISO R52 R56 R55 R82 DNP DNP J10 0R 0R 0R 0R 1 3 5 7 9 2 4 6 8 10 R53 R57 0R 0R 2 BD10-H C25 15p ZB_IRQ0 ZB_SLPTR SPI1_MOSI SPI1_SPCK 1 JP10 C27 DNP DNP 2.2u C26 2.2n PE31 PE28 PC23 PC24 13,3 13,3,9 13,3 13,3 A 3V3 C B A REV SAMA5D3x-MB Derek 30-Sep-12 Derek 30-Mar-12 Derek 11-Nov-11 MODIF. SCALE DES. DATE 1/1 This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 4 3 2 1 XX-XXX-XX XX-XXX-XX XX-XXX-XX VER. DATE REV. SHEET C CAN & ZIGBEE & USART1 5 X.X X.X X.X 6 14 5 4 3 2 1 3V3 3V3 L27 220ohm at 100MHz 1 2 C140 C141 4.7u 100n C137 10u C142 100n D D AUDIO_GND AUD_1V8 L26 220ohm at 100MHz 1 2 3 C76 27 1u AUDIO_GND C143 4.7u 21 AUDIO_GND C136 4.7u 20 5 R86 2K2 R87 2K2 7 DCVDD 4 19 23 6 CPVDD 3 2 R226 R234 R227 R230 R231 R228 R229 R232 R233 HPOUTFB MCLK BCLK/GPIO4 LRCLK ADCDAT DACDAT LINEOUTR LINEOUTL LINEOUTFB 1.5k 1.5k IRQ/GPIO1 28 29 30 31 32 0R 0R TWD0 TWCK0 33R PCK0 0RDNP TK 0R RK 0R RF 0R TF 0R RD 0R TD 1 PA30 PA31 13,3,9 13,3,9 PD30 PC16 PC19 PC20 PC17 PC21 PC18 3,9 3,9 3 3 3,9 3 3,9 INT_AUDIO PD16 C 3 IN1R/DMICDAT2 IN1L/DMICDAT1 CPCA VMIDC CPCB CPVOUTP MICBIAS IN2R IN2L WM8904 CPGND 24 26 L3 220ohm at 100MHz 1 2 LINE IN SDA SCLK 2K2 AUDIO_GND B 25 R123 CPVOUTN 8 C45 2.2u 10 11 12 C44 2.2u C41 2.2u 9 R126 18 16 17 R122 C135 100n DGND PAD MP6027P AUDIO_GND AUDIO_GND 1 2 OUT GND MIC1 AUDIO_GND R85 20R 100n 100n DNP J26 DNP MD1x5 DNP 5 4 3 2 1 MIC 5 33 AUDIO_GND 20R C89 20R C90 DNP DNP C62 470p R84 20R MIC1 R118 R119 AGND C61 470p C145 100n 22 4 STEREO_3.5mm J15 C144 100n HPOUTL DBVDD 13 HPOUTR MICVDD 15 L7 220ohm at 100MHz 1 2 VDDIOP0 AUD_1V8 MN10 14 C AUDIO_GND AUDIO_GND 2 1 2.2u C139 100n AVDD 5 L6 220ohm at 100MHz 1 2 AVDD1V8 C46 C138 10u HEADPHONE AVDD1V8 B C28 1u C29 1u 2 1 4 STEREO_3.5mm J13 L4 220ohm at 100MHz 1 2 3 C42 470p C43 470p AUDIO_GND R80 47k DNP R81 47k DNP R178 AUDIO_GND AUDIO_GND 0R AUDIO_GND 3V3 AUDIO_GND AUDIO_GND 1 2 A 3 C30 4.7u AUD_1V8 MN7 AUDIO_GND C37 100n C36 2.2u VIN VOUT 5 GND 4 EN BYP SPX5205M5-L-1-8 150mA capability C33 4.7u A C35 100n Derek Derek Derek C B A REV SAMA5D3x-MB SCALE MODIF. 30-Sep-12 30-Mar-12 11-Nov-11 DES. DATE 1/1 This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 4 3 2 1 XX-XXX-XX XX-XXX-XX XX-XXX-XX VER. DATE REV. SHEET C AUDIO 5 X.X X.X X.X 7 14 5 4 3 2 1 D D L8 220ohm at 100MHz D3 TEST RAC MMBD3004S-7-F 2 4 1 5 D5 MMBD3004S-7-F 1 2 DIBN R166 TX1 2 0R EIC 11 C67 DAA_GND 16 RXI 150pF 3 EIF TXO 150pF TXF DVDD 1 17 3 1 C69 10n MMBAT42 DAA_GND 9 8 Q3 7 1 1 1 13 EP VC GPIO Q2 1 100R MMBAT42 DVDD C73 100n R99 3 EIO DIBP C72 10 R95 280R 1% 1206 R96 280R 1% 1206 R97 280R 1% 1206 R98 280R 1% 1206 2 14 LAN0066-50 C71 2 C 3 DIBP 4 MJM0606GE06-H 470p Q4 MMBAT42 Q5 MMBAT42 2 3 1 0R 2 237K C70 47pF R167 1 RJ11 TB3100M-13-F 100V DAA_GND C68 47n 6 DIBN 6.81M C64 100n R94 DAA_GND 3 0805 D4 470p 3 3 R93 AVDD L9 220ohm at 100MHz DAA_GND 2 0R can be replaced by bead to improve EMI C 2 C66 100n TAC 2 C65 100n PWR 3 15 J16 1 2 3 4 5 6 C63 2 12 2 1 1 6.81M 3 R92 MN11 0805 CX20548-11Z R102 110R R100 3.01R 1% R101 3.01R 1% DAA_GND C74 100n B B R103 9R1 1% 1206 DAA_GND R94,C68 should be placed near Pin6(RXI), and should be no vias on the RXI Net. DAA_GND A A C B A REV SAMA5D3x-MB SCALE Derek 30-Sep-12 Derek 30-Mar-12 Derek 11-Nov-11 MODIF. DES. 1/1 DATE X.X X.X X.X XX-XXX-XX XX-XXX-XX XX-XXX-XX VER. DATE REV. SHEET C SmartDAA T his agreem ent is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 3 2 1 8 14 5 4 3 2 1 5V TWD0 TWCK0 R91 R272 R273 PVDD5 C87 RB160M-60 RR27 22R RR28 22R RR29 22R R42 PA28 LCDPCK PA26 PA27 PA29 PC31 LCDVSYNC RR30 2 LCDHSYNC 22R 3 4 LCDDEN RESET_HDMI R264 BCLK LRCLK DAT 3V3 R260 1 R184 R282 R270 R284 22R 8 7 6 5 22R 10k 0R 33R 0R 32 BLUE0 31 BLUE1 30 BLUE2 29 BLUE3 28 BLUE4 27 BLUE5 25 BLUE6 24 BLUE7 23 GREEN0 20 GREEN1 19 GREEN2 18 GREEN3 17 GREEN4 16 GREEN5 15 GREEN6 14 GREEN7 13 RED0 11 RED1 10 RED2 9 RED3 8 RED4 7 RED5 6 RED6 4 RED7 Close to SiI902x CLK_HDMI 22 VSYNC_HDMI HSYNC_HDMI DE_HDMI RST# 35 34 33 51 45 44 41 40 39 37 R285 B PCK0 R266 DNP 0R 38 33R T2 36 TSPDIF 48 49 71 50 1 2 72 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 HPD 0R R71 DDCSDA DDCSCL 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 1k DNP R108 TXC+ TXCTX0+ TX0TX1+ TX1TX2+ TX2EXT_SWING 59 58 TX_C+ TX_C- 62 61 TX_0+ TX_0- 65 64 TX_1+ TX_1- 68 67 TX_2+ TX_2- D15 D17 D18 TVS TVS TVS TXC- 4 3 TXC- TX_C+ 1 2 TXC+ TX_C- R164 47k 0R L38 DNP R72 R73 TX_0- TXC+ TX0- NCMS20C900 0R TX0+ TX1- 0R TX1+ TX2- DNP L39 NCMS20C900 4 3 TX0- TX2+ 56 EXT_SW R265 4.3K/1% TX_0+ 1 2 D 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 TX0+ HDM19SW-4-1R-H R74 Close to Chip G1 G3 RR26 22R Type A connector 100n DDCSDA DDCSCL 0R J25 C 1V2 L18 AVCC_1 AVCC_2 AGND_1 AGND_2 IO_SEL CLK IOVCC18_1 IOVCC18_2 IOVCC18_3 VSYNC HSYNC DE RESETN SCLK LRCLK 60 66 57 63 69 I2S0 I2S1 I2S2 I2S3 MCLK SPDIF R41 CGND C53 C49 C50 C51 C52 C48 1n 1n 1n 1n 100n 100n C54 100n 2 EBMS321611A520 C82 10u 3V3 1k 3 21 46 L19 1 IOVCC3V3 R75 0R L40 TX_1- 4 DNP 3 TX1- TX_1+ 1 2 TX1+ R76 NCMS20C900 0R R77 0R 2 EBMS321611A520 C55 100n C56 100n C58 100n C81 10u DNP L41 NCMS20C900 3 TX2TX_2- 4 TX_2+ 5 12 26 42 47 53 C59 100n C60 100n 43 R78 1V2 L22 EBMS321611A520 1 2 CVCC12 C77 100n C83 10u C78 100n C79 100n C80 100n 1 2 TX2+ 0R To keep TMDS pair impedance maintain at 100 ohm , pls share common choke pad with shunted resistor TX2+ TX2TX1+ TX1- 6 7 8 9 10 MN12 RClamp0514M 5 LINE4 NC2 4 NC4 LINE3 3 GND VCC 2 LINE2 NC1 1 NC3 LINE1 6 7 8 9 10 MN13 RClamp0514M 5 LINE4 NC2 4 NC4 LINE3 3 GND VCC 2 LINE2 NC1 1 NC3 LINE1 B TX2+ TX2TX1+ TX1- 73 70 55 SiI9022ACUN CVCC12_1 CVCC12_2 CVCC12_3 CVCC12_4 CVCC12_5 CVCC12_6 1 AVCC12 IO_SEL: LOW=3.3V ,HIGH=1.8V ePAD VDDQ TMODE RR25 22R 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 SCL SDA RR24 22R R104 2K2 G2 G4 HPD_SiI R88 4.7k CI2CA LCDDAT0 LCDDAT1 LCDDAT2 LCDDAT3 LCDDAT4 LCDDAT5 LCDDAT6 LCDDAT7 LCDDAT8 LCDDAT9 LCDDAT10 LCDDAT11 LCDDAT12 LCDDAT13 LCDDAT14 LCDDAT15 LCDDAT16 LCDDAT17 LCDDAT18 LCDDAT19 LCDDAT20 LCDDAT21 LCDDAT22 LCDDAT23 13,3 13,3 13,3 3 PD30 D7 R90 4.7k 13,3 3,7 2 4.7k MN9 PC16 PC17 PC18 F1 R105 2K2 LOW:72h(Defult) 3,7 3,7 3,7 1 DNP R89 3V3 C 3V3 3V3 0R 0R D 13,3 PA0 13,3 PA1 13,3 PA2 13,3 PA3 13,3 PA4 13,3 PA5 13,3 PA6 13,3 PA7 13,3 PA8 13,3 PA9 13,3 PA10 13,3 PA11 13,3 PA12 13,3 PA13 13,3 PA14 13,3 PA15 13,3 PC14 13,3 PC13 13,3 PC12 13,3 PC11 13,3 PC10 13,3 PC15 12,13,3 PE27 13,3,6 PE28 2K2 1812L160/12 54 52 13,3,7 PA30 13,3,7 PA31 HDMI_INT HPD INT PC29 CEC_A CEC_D 13,3 HDMI Spec. +4.8V < PVDD5 < +5.3V TX0+ TX03V3 2 C84 100n 1V2 MN8 1 3 C85 10u VIN VOUT GND EN BYP TXC+ TXC- 5 4 TX0+ TX0TXC+ TXC- C86 10u RT9013-12PB A A C B A REV SAMA5D3x-MB SCALE Derek 30-Sep-12 Derek 30-Mar-12 Derek 11-Nov-11 MODIF. DES. 1/1 DATE X.X X.X X.X XX-XXX-XX XX-XXX-XX XX-XXX-XX VER. DATE REV. SHEET C HDMI T his agreem ent is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 3 2 1 9 14 4 3 2 1 ETH1 VDDIOP0 C122 100n DNP L20 220ohm at 100MHz 1 2 C100 10u 10V R136 0R R170 49.9R DNP EARTH_ETH1 3 3 3 3 PC3 PC2 PC5 PC6 1 2 3 4 E1_TXCK E1_TX1 E1_TX0 E1_TXEN 8 7 6 5 1 E1_RX1 2 E1_RX0 E1_CRSDV 3 4 E1_RXER 22R RR19 25 24 23 13 14 15 16 18 20 29 28 8 7 6 5 22R RR18 3 3 13,3,6 PC8 PC9 PE30 E1_MDC E1_MDIO INT_ETH1 1 2 3 4 VDDIOP0 R60 R59 C31 10u VDD_1V2 KSZ8051RNL 5 GND PADDLE NC1 NC2 NC3 REXT VDDA_3V3 0R 15 TX- 2 3 RD+ RX+ 3 RX- 6 5 CT DNP 4 6 RD- 2 C39 C118 100n 2.2u R171 49.9R DNP C124 100n C32 100n 1 33 22 26 27 10 C129 100n 75 R172 49.9R DNP 75 17 C34 10u 12,14,3 VDDIO XI C38 100n LED0/NWAYEN LED1/SPEED 32 NRST 4 5 GND_ETH1 1nF 75 8 R173 6.49k/1% 7 C123 100n DNP VDDIOP0 8 ETH1_XO 9 ETH1_XI 8 GND_ETH1 EARTH_ETH1 RR22 10k C VDDIOP0 30 31 C91 22p RESET 2 At the De-Assertion of Reset: PHY ADD[2:0]:001 CONFIG[2:0]:001,Mode:RMII Duplex Mode:Half Duplex Isolate Mode:Disable Speed Mode:100Mbps Nway Auto-Negotiation:Enable 75 7 NC J00-0061NL XO VDDIOP0 2 TD- 1 2 3 4 VDDIOP0 1 4 CT DNP 6 R177 1 2 3 4 RR21 10k 0R TX+ E1_AVDDT RXP 8 7 6 5 8 7 6 5 C E1_AVDDT L2 220ohm at 100MHz 3 1 2 MDC MDIO INTRP/NAND D 1 TD+ 7 R176 TXM RXM 12 11 21 1 2 3 4 RR20 10k TXP TXD1 TXD0 TXEN PHYAD0 PHYAD1 RXD1/PHYAD2 RXD0/DUPLEX CRS_DV/CONFIG2 RXER/ISO CONFIG1 CONFIG0 1k 1k 8 7 6 5 VDDIOP0 J24 REF_CLK/B-CAST_OFF 8 7 6 5 PC7 PC1 PC0 PC4 EARTH_ETH1 MN20 19 3 3 3 3 R162 49.9R DNP GND_ETH1 22R RR17 D 10Base-T/100Base-TX GND_ETH1 16 5 4 1 C88 22p 2 D9 1 Yellow R134 470R 2 D8 1 Green R135 470R KSZ8041NL:R162,R170,R171,R172,R176,R177,C122,C123 are needed. KSZ8051NL:R162,R170,R171,R172,R176,R177,C122,C123 are not needed. Y2 3 25MHz J17 3 3 ETH0_RX2+ ETH0_RX2- ETH0_GND 8 TRD4+ C125 100n 7 TRCT4 9 TRD4- T4/A T4/B TRP4+ 7 TRP4- 8 TRP3+ 4 TRP3- 5 TRP2+ 3 TRP2- 6 TRP1+ 1 TRP1- 2 75 OHM B B 1:1 3 3 ETH0_TX2+ ETH0_TX2- ETH0_GND 3 TRD3+ C126 100n 1 TRCT3 2 TRD3- T3/A T3/B 75 OHM 1:1 3 3 ETH0_RX1+ ETH0_RX1- ETH0_GND 4 TRD2+ C127 100n 6 TRCT2 5 TRD2- T2/A T2/B ETH0 75 OHM 10Base-T/100Base-TX/1000BASE-T 1:1 ETH0_GND 3 R175 ETH0_GND 0R 3 ETH0_LED2 3 ETH0_LED1 TRD1+ C128 100n 12 TRCT1 10 TRD1- T1/A T1/B 75 OHM 13 1:1 YELLOW LED 15 GREEN LED 17 GREEN LED A 1NF,2KV L23 220ohm at 100MHz 1 2 J0G-0003NL (SHIELD) 14 A 11 16 ETH0_TX1+ ETH0_TX1- 18 19 3 3 REV EARTH_ETH0 ETH0_GND EARTH_ETH0 R165 R168 Derek 30-Sep-12 Derek 30-Mar-12 Derek 11-Nov-11 C B A VDDIOP1 470R 470R SAMA5D3x-MB SCALE MODIF. DES. 1/1 ETH DATE X.X X.X X.X XX-XXX-XX XX-XXX-XX XX-XXX-XX VER. DATE REV. SHEET C 10 14 T his agreem ent is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 3 2 1 5 4 3 2 1 USB HOST B&C INTERFACE USBB_DP 3 USBB_DM 3 L12 MN19 MN14 D 1 2 8 5V C102 100n 220ohm at 100MHz 7 + C103 33u C101 100n L13 1 C105 100n J19 + C104 33u 6 5 2 OUTA ENA IN FLGA GNG FLGB OUTB ENB 1 2 D EN5V_HDB OVCUR_USB PD28 PD28 1A 1 PD26 3 4 2Y 2A 3 PD27 3 3 3 4 5 3V3 EN5V_HDC AIC1526-1GS 220ohm at 100MHz 6 1Y GND VCC 2 SN74LVC2GU04 C97 100n Dual USB A A1 A2 A3 A4 L21 220ohm at 100MHz 1 2 B1 B2 B3 B4 A B 1 2 USBC_DM 3 USBC_DP 3 3 4 C C EARTH_USB EARTH_USB 3V3 USB A HOST/DEVICE INTERFACE L14 MN15 2 8 5V + C106 220ohm at 100MHz C108 33u 100n L15 C107 100n 1 C109 100n 2 220ohm at 100MHz 7 6 5 OUTA ENA IN FLGA GNG FLGB OUTB ENB R163 47k 1 2 EN_PWRLCD 3 OVCUR_USB 4 EN5V_HDA PD28 JP17 AIC1526-1GS B R137 47k MN21 8 7 R138 10 SHD EARTH_USB 47589-0001 11 1 2 3 4 5 (VBUS_SENSE) PD29 3 3V3 R139 82k (IDUSBA) R140 6 1Y 1A 1 LCD_DETECT# 4 2Y 2A 3 PD25 5 C99 100n VCC GND 13 3 2 SN74LVC2GU04 USBA_DM 3 USBA_DP 3 A C B A 47k 9 3V3 6 A VBUS DM DP ID GND 47k C111 15p J20 OPEN:Enable LCD for D31,D33,D34 CLOSE:Disable LCD for D35 SIP2 3V3 C75 10u B REV SAMA5D3x-MB SCALE Derek Derek Derek MODIF. 30-Sep-12 30-Mar-12 11-Nov-11 DES. DATE 1/1 USB INTERFACE EARTH_USB This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 13 1 5V_LCD 2 13 1 3 2 1 X.X X.X X.X XX-XXX-XX XX-XXX-XX XX-XXX-XX VER. DATE REV. SHEET C 11 14 5 4 3 2 PUSH BUTTON 1 ANALOG Reference 3V 3V3 3,4 VBAT VDDANA 5V D D R142 1.5k PB1 1 R141 100k R143 1.5k JP14 NRST NRST 10,14,3 3 2 ADVREF PB2 WAKE UP C112 100n 3 3V 3 WAKE UP PB3 PB_USER1 PB_USER1 PE27 C113 2.2u 13,3,9 D6 LM4040BIM3-3.0+T PB4 CS_BOOT C R46 0R CS_BOOT_DISABLE 3V3 ONE WIRE EEPROM B C 3 B DNP R144 1.5k MN16 13,3 2 ONE_WIRE PE25 3 I/O GND NC1 NC2 NC3 NC4 1 4 5 6 DS28EC20P C B A A REV SAMA5D3x-MB Derek Derek Derek MODIF. SCALE DES. 30-Sep-12 30-Mar-12 11-Nov-11 DATE 1/1 Miscellaneous This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 3 2 1 X.X X.X X.X XX-XXX-XX XX-XXX-XX XX-XXX-XX VER. DATE REV. SHEET C 12 14 A 5 4 3 3V3 3,6 13,3 R147 R146 PE31 PC27 0R 0R D 3,9 3,9 3,9 3,9 3,9 3,9 1 8 7 RR11 2 6 22R 3 4 5 1 RR43A 8 2 RR43B 7 PA1 PA3 PA5 PA7 PA9 PA11 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 1 LCD J21 1 3 5 ZB_IRQ0 TWCK1(SPI1_NPCS2) 7 9 11 13 15 17 19 LCDDAT1 21 LCDDAT3 23 LCDDAT5 25 LCDDAT7 27 LCDDAT9 29 LCDDAT11 2 R148 0R ZB_IRQ1 0R TWD1(SPI1_NPCS1) R149 1 8 LCDDAT15 7 RR13 2 LCDDAT13 6 22R 3 LCDDAT14 4 5 LCDDAT12 1 8 LCDDAT0 7 RR12 2 LCDDAT2 6 22R 3 LCDDAT4 4 5 LCDDAT6 RR43C 3 LCDDAT8 6 RR43D 4 LCDDAT10 5 PE30 PC26 PA15 PA13 PA14 PA12 PA0 PA2 PA4 PA6 PA8 PA10 10,3,6 13,3 3,9 3,9 3,9 3,9 3,9 3,9 3,9 3,9 3,9 3,9 D ESW-115-33-L-D 5V_LCD J22 11 5V_LCD C 3,9 3,9 3,9 12,3,9 PC14 PC12 PC10 PE27 3 3,9 3,9 PA25 PA26 PA29 3 3 3 3,6 3,6 11 3,6 PD20 PD22 PD24 PC22 PC24 EN_PWRLCD PB14 1 RR16 2 22R 3 4 8 7 6 5 LCDDAT16 LCDDAT18 LCDDAT20 LCDDAT22 1 RR14 2 22R 3 4 R150 R152 R154 8 7 6 5 0R 0R 0R LCDDISP LCDVSYNC LCDDEN R156 R158 R160 R169 0R 0R 0R 0R SPI1_MISO SPI1_SPCK EN_PWRLCD AD0_XP AD2_YP AD4_LR B 3 4 VDDIOP0 A PD19 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 ISI_RST TWCK1 3 3 3 3 13,3,6 13,3 PA17 PA19 PA21 PA23 PC28 PC26 R124 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 ESW-120-33-L-D DNP R127 0R VDDISI 3 PE24 13,3 PC27 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 1.5k ISI_D1 ISI_D3 ISI_D5 ISI_D7 ISI_D9 ISI_D11 LCD/TSC LCDDAT17 LCDDAT19 LCDDAT21 LCDDAT23 1 RR23 2 22R 3 4 8 7 6 5 LCDPWM LCDHSYNC LCDPCK 1 RR15 2 22R 3 4 R151 R153 R155 8 7 6 5 0R 0R 0R R157 R159 R161 R174 0R 0R 0R 0R AD1_XM AD3_YM ONE_WIRE SPI1_MOSI SPI1_NPCS3 C PC13 PC11 PC15 PE28 3,9 3,9 3,9 3,6,9 PA24 PA27 PA28 3 13,3,9 3,9 PD21 PD23 PE25 3 3 12,3 PC23 3,6 PC28 13,3,6 LCD_DETECT# 11 3,6 PB15 B PA27 VDDIOP0 13,3,9 J11 TSW-115-07-L-D 2 4 6 ZB_RSTN 8 TWD1 10 PCK1(ISI_MCK) 12 ISI_VSYNC 14 ISI_HSYNC 16 ISI_PCK 18 ISI_D0 20 ISI_D2 22 ISI_D4 24 ISI_D6 26 ISI_D8 28 ISI_D10 30 ISI R125 1.5k PE29 3,6 PD31 PA30 PA31 PC30 PA16 PA18 PA20 PA22 PC29 PC27 3 3,7,9 3,7,9 3 3 3 3 3 3,9 13,3 PC26 13,3 C B A REV SAMA5D3x-MB Derek Derek Derek MODIF. SCALE DES. 30-Sep-12 30-Mar-12 11-Nov-11 DATE 1/1 LCD & ISI This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 3 2 1 X.X X.X X.X XX-XXX-XX XX-XXX-XX XX-XXX-XX VER. DATE REV. SHEET C 13 14 A 5 3 4 2 1 VCC_3V3_DEBUG R66 VCC_3V3_DEBUG B VDDCORE_1 VDDCORE_2 VDDCORE_3 VDDCORE_4 VDDCORE_5 87 83 9 34 59 VDDIO_1 VDDIO_2 VDDIO_3 VDDIO_4 4.7k R128 C92 100n NRST_3U 0R TDI_3U R62 0R D TC2050-IDC T3 RXDaux T4 TXDaux RX_3U TX_3U TDIIN 0R R64 TDO_3U R130 R63 R129 4.7k 0R TRESIN TRESOUT R44 R45 DTXD DRXD 0R 0R PB31 PB30 3,6 3,6 TMSIN TCKOUT TMSOUT TDIOUT TDOIN TCKIN ENSPI TCKOUT 2 JP16 1 2 1 JP15 2 D13 LED1_3U LED2_3U 2 D14 RTCKIN C CDC Enabled,close to disable JTAG Enabled,close to disable 1 Red R69 1k 1 Green R70 1k VCC_3V3_DEBUG 3V3 VCC_3V3_DEBUG JP18 2 VBUS_DEBUG 2 3 C94 10u C47 2.2u C98 100n VDDIOP0 C95 10u MN18 1 VDDOUT_3U VDDOUT_3U EARTH_USB2 88 60 36 22 TVS DNP 1 3 DNP VDDBU GNDBU D11 VDDPLL GNDPLL DHSDM DFSDM DFSDP DHSDP 73 72 39R 39R FWUP VDDOUT_3U R68 R67 42 77 80 81 76 VDDUTMI GNDUTMI 100k 79 82 XOUT_3U XIN XOUT VDDIN VDDOUT 12MHz 75 74 45 46 9 L24 TVS 220ohm at 100MHz 1 2 XIN32 XOUT32 XIN_3U DHSDM DHSDP VBG Y4 4 R43 VCC_3V3_DEBUG 1 2 3 4 5 78 50 49 10p SAM3U_LQFP100 TEST JTAGSEL VDDANA GNDANA C121 15p D12 6 3 2 1 8 7 J14 105017-0001 SHD EARTH_USB2 11 6.8k/1% C117 C119 15p 10 0RDNP 53 52 VCC_3V3_DEBUG VBUS_DEBUG NRST NRSTB 44 48 R131 R65 1 R54 VCC_3V3_DEBUG 10n AD12BVREF ADVREF 57 47 TCK_3U TRSTIN TRSTOUT 10 9 8 7 6 VCC RESET TMS NC2 GND1 TDI TCK NC1 GND2 TDO VIN VOUT 5 3 NRST_3U C116 R145 47k ERASE 4 2 VCC_3V3_DEBUG PA0/PGMNCMD PA1/PGMRDY PA2/PGMNOE PA3/PGMNVALID PA4/PGMM0 PA5/PGMM1 PA6/PGMM2 PA7/PGMM3 PA8/PGMD0 PA9/PGMD1 PA10/PGMD2 PA11/PGMD3 PA12/PGMD4 PA13/PGMD5 PA14/PGMD6 PA15/PGMD7 PA16/PGMD8 PA17/PGMD9 PA18/PGMD10 PA19/PGMD11 PA20/PGMD12 PA21/PGMD13 PA22/PGMD12 PA23/PGMD15 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 26 27 28 29 30 31 32 33 37 38 39 40 41 10 11 12 13 14 17 18 19 20 5 21 23 24 25 96 84 85 6 86 J23 1 2 3 4 5 4.7k ERASE_3U43 T1 C TDI TDO/TRACESWO TCK/SWCLK TMS/SWDIO 0R GND1 GND2 GND3 51 54 56 55 TMS_3U R61 35 61 89 D TDI_3U TDO_3U TCK_3U TMS_3U DNP 90 91 92 7 8 97 98 99 100 71 70 93 94 95 69 16 15 68 67 66 65 64 63 62 58 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 MN17 VCC_3V3_DEBUG 0R/0805 ENSPI 5V C96 100n GND EN BYP 4 SPX3819 500mA capability B VCC_3V3_DEBUG VCC_3V3_DEBUG R179 150R TRSTIN C152 C153 C131 C146 C154 C155 C156 C157 C158 C159 C160 100n 100n 100n 4.7u 100n 100n 100n 100n 100n 100n 100n TDIOUT R180 150R R181 150R 1 2 3 4 8 0R 7 6 5 NTRST TDI TMS TCK VDDANA VDDIN VDDUTMI VDDIO VDDIO ADVREF TMSOUT TMSIN TCKOUT R182 VDDIOP0 R106 R107 R109 100k 100k 100k 100k DNP DNP DNP DNP VDDIOP0 J9 DNP 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 TDIIN VDDBU R79 RR6 TRSTOUT 150R DNP R113 R110 DNP R112 DNP 0R 0R 0R NTRST TDI TMS TCK RTCK TDO NRST NTRST TDI TMS TCK RTCK TDO NRST 3 3 3 3 3 3 10,12,3 R111 0R DNP BR20-H TCKIN RR7 VDDOUT_3U RTCKIN C161 C147 C162 C163 C164 C165 C166 C167 100n 4.7u 100n 100n 100n 100n 100n 100n 8 0R 7 RTCK 6 TDO 5 NRST 1 2 3 4 A ICE INTERFACE A C B A TDOIN REV VDDOUT VDDPLL TRESOUT VDDCORE R183 150R SAMA5D3x-MB Derek 30-Sep-12 X.X Derek 30-Mar-12 X.X Derek 11-Nov-11 X.X MODIF. SCALE DES. DATE 1/1 Segger-SAM3U TRESIN This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5 4 3 2 1 VER. XX-XXX-XX XX-XXX-XX XX-XXX-XX DATE REV. SHEET C 14 14 6. Optional Display Module (DM) Board 6.1 DM Board Overview The DM board integrates a 5.0” TFT LCD module with touchscreen, as well as four QTouch pads. Figure 6-1. 6.1.1 DM Board Equipment List The DM board components are: 6.1.2 6.1.2.1  One 5.0” TFT LCD module  LCD back light driver  3.3V regulator  QTouch device  1-wire device Function Blocks 3.3V Regulator The 5-0_WVGA_R_AEA-DM Board features its own LDO for local power regulation. It accepts DC 5V power from 500 mA high-side power switch on EK and outputs a regulated +3.3V to most other circuits on the board. Figure 6-2. DM Power Supply 5V_INTER 2 3 SELCONFIG C12 10u C13 100n 3V3_LCD MN3 1 C15 2.2u VIN VOUT 5 C10 10u GND EN BYP 4 C11 100n SPX3819 500mA capability SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 116 6.1.3 TFT LCD with Touch Panel The 5-0_WVGA_R_AEA-DM features an LCD controller. The 5” 800x480 LCD provides the DM with a low-power LCD display feature, backlight unit and a touch panel, similar to that used on commercial PDAs. Graphics and text can be displayed on the dot matrix panel with up to 16 million colors by supplying 24-bit data signals (8bit x RGB by default) or 16-bit data signals (5+6+5bit x RGB in option). This allows the user to develop graphical user interfaces for a wide variety of applications. Warning: Figure 6-3. Never connect/disconnect the LCD display from the board while the power supply is on. This can damage both boards. LCD with Touch Panel M1 5'' LCD, 800(H)¡ÁRGB¡Á480(V) Conductors on TOP SIDE FOXLINK PIN 45 PIN 1 FL500WVR00-A0T LED2+ LED2LED1+ LED1GND6 X1 Y1 X2 Y2 GND5 GND4 DE VSYNC HSYNC STB DOTCLK GND3 B7 B6 B5 B4 B3 B2 B1 B0 G7 G6 G5 G4 G3 G2 G1 G0 R7 R6 R5 R4 R3 R2 R1 R0 VCC2 VCC1 GND2 GND1 J1 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 R1 R2 R3 R4 VLED+ VLED- X_RIGHT Y_LOW X_LEFT Y_UP 0R 0R 0R 0R AD2_YP AD1_XM AD3_YM AD0_XP C4 C1 C2 C3 10n DNP 10n DNP 10n DNP 10n DNP R64 220K DNP LCDDEN LCDVSYNC LCDHSYNC R7 27R LCDDISP LCDPCK BLUE7 BLUE6 BLUE5 BLUE4 BLUE3 BLUE2 BLUE1 BLUE0 GREEN7 GREEN6 GREEN5 GREEN4 GREEN3 GREEN2 GREEN1 GREEN0 RED7 RED6 RED5 RED4 RED3 RED2 RED1 RED0 BLUE[0..7] BLUE3 R10 R8 R11 R9 R12 R13 R14 R15 R16 R17 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R BLUE2 BLUE1 BLUE0 R18 R20 R21 0R 0R 0R GREEN2 G5 R24 R25 G4 R26 R27 G3 R28 R29 G2 R30 R32 G1 R34 R33 G0 R35 R36 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R GREEN1 GREEN0 R38 R37 0R 0R RED3 R4 R42 R43 R3 R44 R46 R2 R47 R48 R1 R49 R50 R0 R51 R52 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R RED2 RED1 RED0 R53 R54 R55 0R 0R 0R B4 BLUE7 B3 BLUE6 B2 BLUE5 B1 BLUE4 B0 LCDDAT4 DNP LCDDAT7 DNP LCDDAT3 LCDDAT6 DNP LCDDAT2 LCDDAT5 DNP LCDDAT1 LCDDAT4 DNP LCDDAT0 LCDDAT3 GREEN[0..7] LCDDAT2 LCDDAT1 LCDDAT0 3V3_LCD C5 100n C6 10u RED[0..7] GREEN7 GREEN6 GREEN5 GREEN4 GREEN3 RED7 RED6 RED5 RED4 DNP LCDDAT10 LCDDAT15 DNP LCDDAT9 LCDDAT14 DNP LCDDAT8 LCDDAT13 DNP LCDDAT7 LCDDAT12 LCDDAT6 DNP LCDDAT11 DNP LCDDAT5 LCDDAT10 LCDDAT9 LCDDAT8 DNP LCDDAT15 LCDDAT23 DNP LCDDAT14 LCDDAT22 DNP LCDDAT13 LCDDAT21 DNP LCDDAT12 LCDDAT20 LCDDAT11 DNP LCDDAT19 LCDDAT18 LCDDAT17 LCDDAT16 SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 117 6.1.4 Backlight The backlight voltage is generated from a CP2122ST/CP2123ST boost converter. It is powered directly by the 5V DC from the EK board. The backlight level is controlled by a PWM signal generated from the SAMA5D3 series processor. Figure 6-4. DM Back Light Control L1 22uH 880mA 5V_INTER 5V/217mA 24.5V/40mA D1 RB160M-60 60V/1A C7 10u 10V VLED+ C9 2.2u 50V MN1 5 VIN SW GND SHDN# FB 4 LCDPWM 1 2 3 CP2122ST 300mV VLED- R40 10k R41 7R5 2 x 7 LEDs Back Light 2*20mA, 24.5V 6.1.5 QTouch The 5-0_WVGA_R_AEA-DM board carries a QTouch device driven through a TWI interface. It manages four capacitive touch buttons directly printed on the PCB. There is dual footprint for the QTouch device. SOIC is the default mounted one. Figure 6-5. DM QTouch 3V3_LCD MN5 C16 3V3_LCD 3V3_LCD C14 R63 R56 R57 R58 DNP DNP 100n 11 8 VSS KEY0 KEY1 KEY2 KEY3 KEY4 KEY5 14 13 12 11 10 9 8 R65 R66 R67 R68 4.7k 4.7k 4.7k 4.7k QT1070_SOIC Thermal KEY6 KEY5 KEY4 KEY3 KEY2 KEY1 KEY0 21 QT1070 DNP NC5 NC4 NC3 NC2 NC1 NC0 VSS 6 7 10 18 19 20 SCL SDA CHANGE RESET VDD MODE(VSS) SDA RESET CHANGE SCL KEY6 VDD 15 12 14 13 MODE(VSS) 10k 4.7k 4.7k 4.7k TWCK0 TWD0 CHANGE# RESET# 9 MN4 6.1.6 1 2 3 TWD0 RESET# 4 CHANGE# 5 6 TWCK0 7 100n 16 17 1 2 3 4 5 KEY4 KEY3 KEY2 KEY1 R59 R60 R61 R62 4.7k 4.7k 4.7k 4.7k DNP DNP DNP DNP KEY K4 KEY K3 KEY K2 KEY K1 1-Wire The 5-0_WVGA_R_AEA-DM board also uses a 1-wire device as a “soft label” to store the information such as chip type, manufacture name, production date, etc. Figure 6-6. DM 1-Wire 3V3_LCD R45 4.7k ONE_WIRE MN2 1 2 3 4 NC1 NC2 DATA GND NC6 NC5 NC4 NC3 8 7 6 5 DS2433S SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 118 A B C D M1 FOXLINK SW GND FB 5 C10 10u R41 7R5 300mV C9 2.2u 50V VLED- VLED+ ONE_WIRE 1 2 3 4 3V3_LCD 3V3_LCD C6 10u BLUE7 BLUE6 BLUE5 BLUE4 BLUE3 BLUE2 BLUE1 BLUE0 GREEN7 GREEN6 GREEN5 GREEN4 GREEN3 GREEN2 GREEN1 GREEN0 RED7 RED6 RED5 RED4 RED3 RED2 RED1 RED0 LCDPCK MN2 NC6 NC5 NC4 NC3 8 7 6 5 RED[0..7] GREEN[0..7] BLUE[0..7] R1 R2 R3 R4 C13 100n 5 C15 2.2u 3 2 1 BYP 4 SPX3819 500mA capability EN GND VIN MN3 C11 100n 3V3_LCD R45 4.7k 4 DS2433S NC1 NC2 DATA GND BLUE2 BLUE1 BLUE0 BLUE3 BLUE4 BLUE5 BLUE6 BLUE7 R7 10n DNP C1 RED7 GREEN1 GREEN0 GREEN2 GREEN3 GREEN4 GREEN5 GREEN6 GREEN7 10n DNP C4 0R 0R 0R 0R RED2 RED1 RED0 RED3 RED4 RED5 VOUT 1 2 3 24.5V/40mA C5 100n X_RIGHT Y_LOW X_LEFT Y_UP LCDDEN LCDVSYNC LCDHSYNC VLED+ VLED- 2*20mA, 24.5V WϮϭϮϮŽƌ WϮϭϮϯ^d CP2123ST VIN OVP SHDN# MN1 RB160M-60 60V/1A D1 J1 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 RED6 6 5 4 L1 22uH 880mA PIN 1 LED2+ LED2LED1+ LED1GND6 X1 Y1 X2 Y2 GND5 GND4 DE VSYNC HSYNC STB DOTCLK GND3 B7 B6 B5 B4 B3 B2 B1 B0 G7 G6 G5 G4 G3 G2 G1 G0 R7 R6 R5 R4 R3 R2 R1 R0 VCC2 VCC1 GND2 GND1 2 x 7 LEDs Back Light 200k 5V_INTER R40 10k C12 10u SELCONFIG VLED+ R69 LCDPWM C7 10u 10V 5V/217mA 5V_INTER KD50G22-45TT-A5 5'' LCD, 800(H)×RGB×480(V) PIN 45 Conductors on TOP SIDE 4 10n DNP C3 R18 R20 R21 R0 R1 R2 R3 R4 R53 R54 R55 R42 R43 R44 R46 R47 R48 R49 R50 R51 R52 R38 R37 G5 R24 R25 G4 R26 R27 G3 R28 R29 G2 R30 R32 G1 R34 R33 G0 R35 R36 B0 B1 B2 B3 R10 R8 R11 R9 R12 R13 R14 R15 R16 R17 27R B4 10n DNP C2 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R 0R R64 13K DNP DNP DNP DNP DNP DNP DNP DNP DNP DNP DNP DNP DNP DNP DNP DNP 3 LCDDAT18 LCDDAT17 LCDDAT16 LCDDAT19 LCDDAT20 LCDDAT21 LCDDAT22 LCDDAT23 LCDDAT9 LCDDAT8 LCDDAT10 LCDDAT11 LCDDAT12 LCDDAT13 LCDDAT14 LCDDAT15 LCDDAT2 LCDDAT1 LCDDAT0 LCDDAT3 LCDDAT4 LCDDAT5 LCDDAT6 LCDDAT7 LCDDISP AD2_YP AD1_XM AD3_YM AD0_XP 3 LCDDAT11 LCDDAT12 LCDDAT13 LCDDAT14 LCDDAT15 LCDDAT5 LCDDAT6 LCDDAT7 LCDDAT8 LCDDAT9 LCDDAT10 LCDDAT0 LCDDAT1 LCDDAT2 LCDDAT3 LCDDAT4 0R 0R CHANGE# 10k 4.7k 4.7k 4.7k TWCK0 TWD0 CHANGE# RESET# R63 R56 R57 R58 DNP DNP 0R 6 7 10 18 19 20 15 12 14 13 AD0_XP AD2_YP AD4_LR 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 2 J3 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 NC5 NC4 NC3 NC2 NC1 NC0 QT1070 DNP SCL SDA CHANGE RESET 2 0R 16 17 1 2 3 4 5 KEY4 KEY3 KEY2 KEY1 R59 R60 R61 R62 C16 LCD_DETECT R23 AD1_XM AD3_YM R19 LCDPWM LCDHSYNC LCDPCK LCDDAT17 LCDDAT19 LCDDAT21 LCDDAT23 TWD0 LCDDAT15 LCDDAT13 LCDDAT14 LCDDAT12 LCDDAT0 LCDDAT2 LCDDAT4 LCDDAT6 LCDDAT8 LCDDAT10 KEY6 KEY5 KEY4 KEY3 KEY2 KEY1 KEY0 100n 3V3_LCD C14 TSM-120-01-L-DV-A MN4 LCDDISP LCDVSYNC LCDDEN J2 TSM-115-01-L-DV-A 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 5V_INTER ZB_IRQ0 TWCK0 1 3 5 7 9 11 13 15 17 LCDDAT1 19 LCDDAT3 21 LCDDAT5 23 LCDDAT7 25 LCDDAT9 27 LCDDAT11 29 DNP DNP 3V3 LCDDAT16 LCDDAT18 LCDDAT20 LCDDAT22 3V3_LCD SELCONFIG R22 R5 R6 3V3_LCD 9 VDD 5 VSS 8 MODE(VSS) 11 Thermal 21 4.7k 4.7k 4.7k 4.7k 1 2 3 4 5 6 7 VSS KEY0 KEY1 KEY2 KEY3 KEY4 KEY5 14 13 12 11 10 9 8 B A 1/1 MODIF. SCALE REV R66 R65 R67 R68 DES. DATE Derek 26-Sep-12 Derek 30-Mar-12 4.7k 4.7k 4.7k 4.7k 1 This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings. 5.0_WVGA_R_AEA_DM 5.0_WVGA_R_AEA_DM QT1070_SOIC VDD MODE(VSS) SDA RESET CHANGE SCL KEY6 MN5 DNP DNP DNP DNP TWD0 RESET# CHANGE# TWCK0 100n 3V3_LCD 0R ONE_WIRE 1 SHEET 1 1 B DATE XX-XXX-XX XX-XXX-XX REV. VER. X.X X.X KEY K1 KEY K2 KEY K3 KEY K4 A B C D 6.2 Schematics SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 119 7. Troubleshooting and Recommendations 7.1 Errata 7.1.1 Impedance Mismatch on Revision C of the SAMA5D3x Main Board There is an impedance mismatch on the revision C of the SAMA5D3x main board, impacting the clock signal of the Ethernet PHY chip (MN20, KSZ8051RNL).This leads to a non-optimal data transmission on the ETH1 channel (J24), with timeouts and retrials occurring from time to time. Resolution: Figure 7-1. Add a line termination on signal PC7.Connect PC7 to ground through a 200 Ohm resistor in series with a 100pF ceramic capacitor. The connection point must be done at Pin 19 of Connector J2. Figure 7-1 shows how and where to apply the fix. Fixing An Impedance Mismatch on the Revision C of the SAMA5D3x Main Board SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 120 8. Revision History Table 8-1. Document Revision History Change Request Ref. Comments Changed document layout, including section numbering. Changed Embest to Embest/Flextronics throughout document. 9364 In “Introduction” and“Contents”: Added SAMA5D36, SAMA5D36-EK and SAMA5D36-CM to lists of available references and to information for display modules (DM). Also throughout document. 9364 In Table 1-1 “Evaluation Kit Specifications”, removed information on temperature and relative humidity. Added information on CE and FCC compliancy. Added SAMA5D36-EK. 9363 In Table 4-1 “CM Board Implementation”, updated boards available from manufacturers. 9360 In Table 4-2 “CPU Module Specifications”, removed ‘optional’ from details on NOR in Memory row. 9363 In Section 4.2.3 “Configuration Items”, removed “Dual ON/OFF switch for NAND Flash” and replaced with “One jumper for”. In Table 4-3 “Boot Options”, in row BMS OPEN: Added “...followed by:” after “ROM Boot” and added SAM-BA after TWI in column Type. In column Note, changed “Default boot on embedded ROM” to “Default boot is from embedded ROM”. In row BMS CLOSE, changed “Boot on external NOR Flash memory” to “Boot from external NOR Flash memory”. Section 4.2.4.1 “Boot Configuration”: Revised throughout. Section 4.3.3 “Reset Circuitry”: Changed information on JTAG reset. 11180B Section 4.3.6 “Serial Peripheral Interface Controller (SPI)”: Revised throughout. Section 4.3.9 “Indicators”: Removed specific information on red and blue LEDs. Added information on control by GPIO lines. Added Section 4.4.2 “CPU Module Revision E Schematics”. 9364 9363 Table 5-1 “MB Technical Specifications”, Mass Storage Interface: Updated information on all types of cards supported. - Added information on RoHS and CE and FCC compliancy. - Removed temperature range information. Section 5.2.3 “Debug JTAG/ICE and DBGU”: Modified details of ATSAM3U4C. 9360 Section 5.2.3.1 “Disabling J-Link-OB-ATSAM3U4C”: Revised throughout. Section 5.2.3.2 “Hardware UART via CDC”: Revised throughout. Section 5.2.4 “USART”: Revised throughout. Section 5.2.6 “Ethernet 10/100 (EMAC) Port”: Revised throughout. Section 5.2.10 “CAN Bus”: Removed mention of two ports for connector J27. Section 5.2.14 “LED Indicators”: Revised throughout. Section 5.2.15 “Pushbutton Switches”: Changed fourth bullet. Added Section 7.1 “Errata” with Section 7.1.1 “Impedance Mismatch on Revision C of the SAMA5D3x Main Board”. 11180A 8803 First issue SAMA5D3x-EK User Guide [USER GUIDE] 11180B–ATARM–29-Oct-13 121 Atmel Corporation 1600 Technology Drive Atmel Asia Limited Unit 01-5 & 16, 19F Atmel Munich GmbH Business Campus Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg San Jose, CA 95110 BEA Tower, Millennium City 5 Parkring 4 1-6-4 Osaki, Shinagawa-ku USA 418 Kwun Tong Road D-85748 Garching b. Munich Tokyo 141-0032 Tel: (+1) (408) 441-0311 Kwun Tong, Kowloon GERMANY JAPAN Fax: (+1) (408) 487-2600 HONG KONG Tel: (+49) 89-31970-0 Tel: (+81) (3) 6417-0300 www.atmel.com Tel: (+852) 2245-6100 Fax: (+49) 89-3194621 Fax: (+81) (3) 6417-0370 Fax: (+852) 2722-1369 © 2013 Atmel Corporation. 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