SAM DA1
32-bit ARM-Based Microcontrollers
Introduction
®
®
The SAM DA1 is a series of low-power microcontrollers using the 32-bit ARM Cortex -M0+ processor,
and ranging from 32- to 64-pins with up to 64KB Flash, 8KB of SRAM and up to 2KB Read-While-Write
(RWW) Flash section. The SAM DA1 operate at a maximum frequency of 48MHz and reach 2.46
®
CoreMark /MHz. They are designed for simple and intuitive migration with identical peripheral modules,
hex compatible code, identical linear address map and pin compatible migration paths between all
devices in the product series. All devices include intelligent and flexible peripherals, Event System for
inter-peripheral signaling, and support for capacitive touch button, slider and wheel user interfaces.
Features
•
•
•
•
•
Processor
– ARM Cortex-M0+ CPU running at up to 48MHz
• Single-cycle hardware multiplier
• Micro Trace Buffer (MTB)
Memories
– 16/32/64KB in-system self-programmable Flash
– 0.5/1/2KB Read-While-Write (RWW) Flash section
– 4/4/8KB SRAM memory
System
– Power-on reset (POR) and brown-out detection (BOD)
– Internal and external clock options with 48MHz Digital Frequency Locked Loop (DFLL48M)
and 48MHz to 96MHz Fractional Digital Phase Locked Loop (FDPLL96M)
– External Interrupt Controller (EIC)
– 16 external interrupts
– One non-maskable interrupt
– Two-pin Serial Wire Debug (SWD) programming, test and debugging interface
Low Power
– Idle and standby sleep modes
– SleepWalking peripherals
Peripherals
– 12-channel Direct Memory Access Controller (DMAC)
– 12-channel Event System
– Up to five 16-bit Timer/Counters (TC), configurable as either:
• One 16-bit TC with two compare/capture channels
• One 8-bit TC with two compare/capture channels
• One 32-bit TC with two compare/capture channels, by using two TCs
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SAM DA1
–
–
–
–
–
–
–
–
–
–
–
•
•
•
•
Three 24-bit Timer/Counters for Control (TCC), with extended functions:
• Up to four compare channels with optional complementary output
• Generation of synchronized pulse width modulation (PWM) pattern across port pins
• Deterministic fault protection, fast decay and configurable dead-time between
complementary output
• Dithering that increase resolution with up to 5 bit and reduce quantization error
32-bit Real Time Counter (RTC) with clock/calendar function
Watchdog Timer (WDT)
CRC-32 generator
One full-speed (12Mbps) Universal Serial Bus (USB) 2.0 interface controller
• Device 2.0 and reduced-host low speed and full speed
• Flexible end-point configuration and management with dedicated DMA channels
• On-chip transceivers including pull-ups and serial resistors
• Crystal-less operation in device mode
Up to six Serial Communication Interfaces (SERCOM), each configurable to operate as either:
• USART with full-duplex and single-wire half-duplex configuration
• I2C up to 3.4MHz
• SPI
One two-channel Inter-IC Sound (I2S) interface
One 12-bit, 350ksps Analog-to-Digital Converter (ADC) with up to 20 channels
• Differential and single-ended input
• 1/2x to 16x programmable gain stage
• Automatic offset and gain error compensation
• Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution
10-bit, 350ksps Digital-to-Analog Converter (DAC)
Two Analog Comparators (AC) with window compare function
Peripheral Touch Controller (PTC)
• 256-Channel capacitive touch and proximity sensing
I/O
– Up to 52 programmable I/O pins
Packages
– 64-pin TQFP
– 48-pin TQFP, QFN
– 32-pin TQFP, QFN
Operating Voltage
– 2.7V - 3.63V
Temperature range
– -40°C to +105°C
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40001895A-page 2
Table of Contents
Introduction......................................................................................................................1
Features.......................................................................................................................... 1
1. Description............................................................................................................... 11
2. Configuration Summary...........................................................................................12
3. Ordering Information................................................................................................14
3.1.
3.2.
3.3.
Device Variant A.........................................................................................................................14
Device Variant B.........................................................................................................................15
Device Identification................................................................................................................... 17
4. Block Diagram......................................................................................................... 18
5. Pinout...................................................................................................................... 20
5.1.
5.2.
5.3.
SAM DA1J - TQFP64................................................................................................................. 20
SAM DA1G - QFN48 / TQFP48................................................................................................. 21
SAM DA1E - QFN32 / TQFP32..................................................................................................22
6. Signal Descriptions List........................................................................................... 23
7. I/O Multiplexing and Considerations........................................................................25
7.1.
7.2.
Multiplexed Signals.................................................................................................................... 25
Other Functions..........................................................................................................................27
8. Power Supply and Start-Up Considerations............................................................ 30
8.1.
8.2.
8.3.
8.4.
Power Domain Overview............................................................................................................30
Power Supply Considerations.................................................................................................... 30
Power-Up................................................................................................................................... 32
Power-On Reset and Brown-Out Detector................................................................................. 32
9. Product Mapping..................................................................................................... 34
10. Automotive Quality Grade....................................................................................... 35
11. Data Retention.........................................................................................................36
12. Memories.................................................................................................................37
12.1. Embedded Memories................................................................................................................. 37
12.2. Physical Memory Map................................................................................................................ 37
12.3. NVM Calibration and Auxiliary Space........................................................................................ 38
13. Processor And Architecture.....................................................................................41
13.1. Cortex M0+ Processor............................................................................................................... 41
13.2. Nested Vector Interrupt Controller..............................................................................................42
13.3. Micro Trace Buffer...................................................................................................................... 44
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SAM DA1
13.4. High-Speed Bus System............................................................................................................ 45
13.5. AHB-APB Bridge........................................................................................................................ 47
13.6. PAC - Peripheral Access Controller........................................................................................... 48
14. Peripherals Configuration Summary........................................................................60
15. DSU - Device Service Unit...................................................................................... 62
15.1. Overview.................................................................................................................................... 62
15.2. Features..................................................................................................................................... 62
15.3. Block Diagram............................................................................................................................ 63
15.4. Signal Description...................................................................................................................... 63
15.5. Product Dependencies............................................................................................................... 63
15.6. Debug Operation........................................................................................................................ 64
15.7. Chip Erase..................................................................................................................................66
15.8. Programming..............................................................................................................................66
15.9. Intellectual Property Protection.................................................................................................. 67
15.10. Device Identification................................................................................................................... 68
15.11. Functional Description................................................................................................................69
15.12. Register Summary..................................................................................................................... 75
15.13. Register Description...................................................................................................................77
16. Clock System...........................................................................................................99
16.1.
16.2.
16.3.
16.4.
16.5.
16.6.
16.7.
16.8.
Clock Distribution....................................................................................................................... 99
Synchronous and Asynchronous Clocks..................................................................................100
Register Synchronization......................................................................................................... 100
Enabling a Peripheral............................................................................................................... 105
Disabling a Peripheral.............................................................................................................. 105
On-demand, Clock Requests................................................................................................... 105
Power Consumption vs. Speed................................................................................................ 106
Clocks after Reset.................................................................................................................... 106
17. GCLK - Generic Clock Controller.......................................................................... 107
17.1.
17.2.
17.3.
17.4.
17.5.
17.6.
17.7.
17.8.
Overview.................................................................................................................................. 107
Features................................................................................................................................... 107
Block Diagram.......................................................................................................................... 107
Signal Description.................................................................................................................... 108
Product Dependencies............................................................................................................. 108
Functional Description..............................................................................................................109
Register Summary....................................................................................................................114
Register Description................................................................................................................. 115
18. PM – Power Manager............................................................................................126
18.1.
18.2.
18.3.
18.4.
18.5.
18.6.
18.7.
Overview.................................................................................................................................. 126
Features................................................................................................................................... 126
Block Diagram.......................................................................................................................... 127
Signal Description.................................................................................................................... 127
Product Dependencies............................................................................................................. 127
Functional Description..............................................................................................................129
Register Summary....................................................................................................................136
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SAM DA1
18.8. Register Description................................................................................................................. 136
19. SYSCTRL – System Controller............................................................................. 150
19.1.
19.2.
19.3.
19.4.
19.5.
19.6.
19.7.
19.8.
Overview.................................................................................................................................. 150
Features................................................................................................................................... 150
Block Diagram.......................................................................................................................... 152
Signal Description.................................................................................................................... 152
Product Dependencies............................................................................................................. 152
Functional Description..............................................................................................................154
Register Summary....................................................................................................................170
Register Description................................................................................................................. 172
20. WDT – Watchdog Timer........................................................................................ 207
20.1.
20.2.
20.3.
20.4.
20.5.
20.6.
20.7.
20.8.
Overview.................................................................................................................................. 207
Features................................................................................................................................... 207
Block Diagram.......................................................................................................................... 208
Signal Description.................................................................................................................... 208
Product Dependencies............................................................................................................. 208
Functional Description..............................................................................................................209
Register Summary....................................................................................................................214
Register Description................................................................................................................. 214
21. RTC – Real-Time Counter..................................................................................... 220
21.1.
21.2.
21.3.
21.4.
21.5.
21.6.
21.7.
21.8.
Overview.................................................................................................................................. 220
Features................................................................................................................................... 220
Block Diagram.......................................................................................................................... 221
Signal Description.................................................................................................................... 221
Product Dependencies............................................................................................................. 221
Functional Description..............................................................................................................223
Register Summary....................................................................................................................228
Register Description................................................................................................................. 231
22. DMAC – Direct Memory Access Controller........................................................... 255
22.1. Overview.................................................................................................................................. 255
22.2. Features................................................................................................................................... 255
22.3. Block Diagram.......................................................................................................................... 257
22.4. Signal Description.................................................................................................................... 257
22.5. Product Dependencies............................................................................................................. 257
22.6. Functional Description..............................................................................................................258
22.7. Register Summary....................................................................................................................278
22.8. Register Description................................................................................................................. 279
22.9. Register Summary - SRAM...................................................................................................... 304
22.10. Register Description - SRAM................................................................................................... 304
23. EIC – External Interrupt Controller.........................................................................311
23.1.
23.2.
23.3.
23.4.
Overview...................................................................................................................................311
Features................................................................................................................................... 311
Block Diagram.......................................................................................................................... 311
Signal Description.................................................................................................................... 312
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SAM DA1
23.5.
23.6.
23.7.
23.8.
Product Dependencies............................................................................................................. 312
Functional Description..............................................................................................................313
Register Summary....................................................................................................................317
Register Description................................................................................................................. 318
24. NVMCTRL – Non-Volatile Memory Controller....................................................... 327
24.1.
24.2.
24.3.
24.4.
24.5.
24.6.
24.7.
24.8.
Overview.................................................................................................................................. 327
Features................................................................................................................................... 327
Block Diagram.......................................................................................................................... 327
Signal Description.................................................................................................................... 328
Product Dependencies............................................................................................................. 328
Functional Description..............................................................................................................329
Register Summary....................................................................................................................336
Register Description................................................................................................................. 336
25. PORT - I/O Pin Controller......................................................................................346
25.1.
25.2.
25.3.
25.4.
25.5.
25.6.
25.7.
25.8.
Overview.................................................................................................................................. 346
Features................................................................................................................................... 346
Block Diagram.......................................................................................................................... 347
Signal Description.................................................................................................................... 347
Product Dependencies............................................................................................................. 347
Functional Description..............................................................................................................349
Register Summary....................................................................................................................354
Register Description................................................................................................................. 356
26. EVSYS – Event System........................................................................................ 372
26.1.
26.2.
26.3.
26.4.
26.5.
26.6.
26.7.
26.8.
Overview.................................................................................................................................. 372
Features................................................................................................................................... 372
Block Diagram.......................................................................................................................... 372
Signal Description.................................................................................................................... 373
Product Dependencies............................................................................................................. 373
Functional Description..............................................................................................................374
Register Summary....................................................................................................................379
Register Description................................................................................................................. 379
27. SERCOM – Serial Communication Interface.........................................................391
27.1.
27.2.
27.3.
27.4.
27.5.
27.6.
Overview.................................................................................................................................. 391
Features................................................................................................................................... 391
Block Diagram.......................................................................................................................... 392
Signal Description.................................................................................................................... 392
Product Dependencies............................................................................................................. 392
Functional Description..............................................................................................................394
28. SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiver
and Transmitter......................................................................................................400
28.1. Overview.................................................................................................................................. 400
28.2. USART Features...................................................................................................................... 400
28.3. Block Diagram.......................................................................................................................... 401
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SAM DA1
28.4.
28.5.
28.6.
28.7.
28.8.
Signal Description.................................................................................................................... 401
Product Dependencies............................................................................................................. 401
Functional Description..............................................................................................................403
Register Summary....................................................................................................................415
Register Description................................................................................................................. 415
29. SERCOM SPI – SERCOM Serial Peripheral Interface..........................................432
29.1.
29.2.
29.3.
29.4.
29.5.
29.6.
29.7.
29.8.
Overview.................................................................................................................................. 432
Features................................................................................................................................... 432
Block Diagram.......................................................................................................................... 433
Signal Description.................................................................................................................... 433
Product Dependencies............................................................................................................. 433
Functional Description..............................................................................................................435
Register Summary....................................................................................................................444
Register Description................................................................................................................. 445
30. SERCOM I2C – SERCOM Inter-Integrated Circuit................................................ 458
30.1. Overview.................................................................................................................................. 458
30.2. Features................................................................................................................................... 458
30.3. Block Diagram.......................................................................................................................... 459
30.4. Signal Description.................................................................................................................... 459
30.5. Product Dependencies............................................................................................................. 459
30.6. Functional Description..............................................................................................................461
30.7. Register Summary - I2C Slave.................................................................................................479
30.8. Register Description - I2C Slave...............................................................................................479
30.9. Register Summary - I2C Master...............................................................................................493
30.10. Register Description - I2C Master............................................................................................ 494
31. I2S - Inter-IC Sound Controller.............................................................................. 510
31.1.
31.2.
31.3.
31.4.
31.5.
31.6.
31.7.
31.8.
31.9.
Overview.................................................................................................................................. 510
Features................................................................................................................................... 510
Block Diagram.......................................................................................................................... 511
Signal Description.................................................................................................................... 512
Product Dependencies............................................................................................................. 512
Functional Description..............................................................................................................514
I2S Application Examples......................................................................................................... 525
Register Summary....................................................................................................................528
Register Description................................................................................................................. 529
32. TC – Timer/Counter............................................................................................... 542
32.1.
32.2.
32.3.
32.4.
32.5.
32.6.
32.7.
32.8.
Overview.................................................................................................................................. 542
Features................................................................................................................................... 542
Block Diagram.......................................................................................................................... 543
Signal Description.................................................................................................................... 543
Product Dependencies............................................................................................................. 544
Functional Description..............................................................................................................545
Register Summary....................................................................................................................557
Register Description................................................................................................................. 559
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SAM DA1
33. TCC – Timer/Counter for Control Applications...................................................... 575
33.1.
33.2.
33.3.
33.4.
33.5.
33.6.
33.7.
33.8.
Overview.................................................................................................................................. 575
Features................................................................................................................................... 575
Block Diagram.......................................................................................................................... 576
Signal Description.................................................................................................................... 576
Product Dependencies............................................................................................................. 577
Functional Description..............................................................................................................578
Register Summary....................................................................................................................611
Register Description................................................................................................................. 613
34. USB – Universal Serial Bus...................................................................................650
34.1.
34.2.
34.3.
34.4.
34.5.
34.6.
34.7.
34.8.
Overview.................................................................................................................................. 650
Features................................................................................................................................... 650
USB Block Diagram..................................................................................................................651
Signal Description.................................................................................................................... 651
Product Dependencies............................................................................................................. 651
Functional Description..............................................................................................................653
Register Summary....................................................................................................................671
Register Description................................................................................................................. 675
35. ADC – Analog-to-Digital Converter........................................................................727
35.1.
35.2.
35.3.
35.4.
35.5.
35.6.
35.7.
35.8.
Overview.................................................................................................................................. 727
Features................................................................................................................................... 727
Block Diagram.......................................................................................................................... 728
Signal Description.................................................................................................................... 728
Product Dependencies............................................................................................................. 729
Functional Description..............................................................................................................730
Register Summary....................................................................................................................739
Register Description................................................................................................................. 740
36. AC – Analog Comparators.....................................................................................757
36.1.
36.2.
36.3.
36.4.
36.5.
36.6.
36.7.
36.8.
Overview.................................................................................................................................. 757
Features................................................................................................................................... 757
Block Diagram.......................................................................................................................... 758
Signal Description.................................................................................................................... 758
Product Dependencies............................................................................................................. 758
Functional Description..............................................................................................................760
Register Summary....................................................................................................................770
Register Description................................................................................................................. 770
37. DAC – Digital-to-Analog Converter........................................................................781
37.1.
37.2.
37.3.
37.4.
37.5.
37.6.
37.7.
Overview.................................................................................................................................. 781
Features................................................................................................................................... 781
Block Diagram.......................................................................................................................... 781
Signal Description.................................................................................................................... 781
Product Dependencies............................................................................................................. 781
Functional Description..............................................................................................................783
Register Summary....................................................................................................................787
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SAM DA1
37.8. Register Description................................................................................................................. 787
38. PTC - Peripheral Touch Controller.........................................................................795
38.1.
38.2.
38.3.
38.4.
38.5.
38.6.
Overview.................................................................................................................................. 795
Features................................................................................................................................... 795
Block Diagram.......................................................................................................................... 796
Signal Description.................................................................................................................... 796
Product Dependencies............................................................................................................. 796
Functional Description..............................................................................................................798
39. Electrical Characteristics....................................................................................... 800
39.1. Disclaimer.................................................................................................................................800
39.2. Absolute Maximum Ratings......................................................................................................800
39.3. Supply Characteristics..............................................................................................................800
39.4. Maximum Clock Frequencies................................................................................................... 801
39.5. Power Consumption................................................................................................................. 803
39.6. Peripheral Power Consumption................................................................................................805
39.7. I/O Pin Characteristics..............................................................................................................808
39.8. Injection Current....................................................................................................................... 812
39.9. Analog Characteristics............................................................................................................. 813
39.10. NVM Characteristics................................................................................................................ 822
39.11. Oscillators Characteristics........................................................................................................822
39.12. PTC Typical Characteristics..................................................................................................... 831
39.13. USB Characteristics................................................................................................................. 833
39.14. Timing Characteristics..............................................................................................................834
40. Packaging Information...........................................................................................841
40.1. Thermal Considerations........................................................................................................... 841
40.2. Package Drawings................................................................................................................... 842
40.3. Soldering Profile....................................................................................................................... 848
41. Schematic Checklist.............................................................................................. 849
41.1.
41.2.
41.3.
41.4.
41.5.
41.6.
41.7.
41.8.
Introduction...............................................................................................................................849
Power Supply........................................................................................................................... 849
External Analog Reference Connections................................................................................. 850
External Reset Circuit...............................................................................................................851
Clocks and Crystal Oscillators..................................................................................................852
Unused or Unconnected Pins...................................................................................................856
Programming and Debug Ports................................................................................................856
USB Interface........................................................................................................................... 859
42. Errata.....................................................................................................................861
42.1. Die Revision E..........................................................................................................................861
42.2. Die Revision F.......................................................................................................................... 866
43. Conventions...........................................................................................................870
43.1. Numerical Notation...................................................................................................................870
43.2. Memory Size and Type.............................................................................................................870
43.3. Frequency and Time.................................................................................................................870
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SAM DA1
43.4. Registers and Bits.................................................................................................................... 871
44. Acronyms and Abbreviations.................................................................................872
45. Datasheet Revision History................................................................................... 875
45.1. Revision B - 03/2017................................................................................................................ 875
45.2. Revision A - 04/2016................................................................................................................ 876
The Microchip Web Site.............................................................................................. 877
Customer Change Notification Service........................................................................877
Customer Support....................................................................................................... 877
Product Identification System...................................................................................... 878
Microchip Devices Code Protection Feature............................................................... 878
Legal Notice.................................................................................................................879
Trademarks................................................................................................................. 879
Quality Management System Certified by DNV...........................................................880
Worldwide Sales and Service......................................................................................881
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Datasheet Complete
40001895A-page 10
SAM DA1
1.
Description
®
®
The SAM DA1 is a series of low-power microcontrollers using the 32-bit ARM Cortex -M0+ processor,
and ranging from 32- to 64-pins with up to 64KB Flash, 8KB of SRAM and up to 2KB Read-While-Write
(RWW) Flash section. The SAM DA1 operate at a maximum frequency of 48MHz and reach 2.46
CoreMark/MHz. They are designed for simple and intuitive migration with identical peripheral modules,
hex compatible code, identical linear address map and pin compatible migration paths between all
devices in the product series. All devices include intelligent and flexible peripherals, Event System for
inter-peripheral signaling, and support for capacitive touch button, slider and wheel user interfaces.
The SAM DA1 provide the following features: In-system programmable Flash, 12-channel direct memory
access (DMA) controller, 12-channel Event System, programmable interrupt controller, up to 52
programmable I/O pins, 32-bit real-time clock and calendar, up to five 16-bit Timer/Counters (TC) and
three 24-bit Timer/Counters for Control (TCC), where each TC can be configured to perform frequency
and waveform generation, accurate program execution timing or input capture with time and frequency
measurement of digital signals. The TCs can operate in 8- or 16-bit mode, selected TCs can be cascaded
to form a 32-bit TC, and three timer/counters have extended functions optimized for motor, lighting and
other control applications. The series provide one full-speed USB 2.0 embedded host and device
interface; up to six Serial Communication Modules (SERCOM) that each can be configured to act as an
USART, UART, SPI, I2C up to 3.4MHz, SMBus, PMBus, and LIN slave; two-channel I2S interface; up to
twenty-channel 350ksps 12-bit ADC with programmable gain and optional oversampling and decimation
supporting up to 16-bit resolution, one 10-bit 350ksps DAC, two analog comparators with window mode,
Peripheral Touch Controller supporting up to 256 buttons, sliders, wheels and proximity sensing;
programmable Watchdog Timer, brown-out detector and power-on reset and two-pin Serial Wire Debug
(SWD) program and debug interface.
All devices have accurate and low-power external and internal oscillators. All oscillators can be used as a
source for the system clock. Different clock domains can be independently configured to run at different
frequencies, enabling power saving by running each peripheral at its optimal clock frequency, and thus
maintaining a high CPU frequency while reducing power consumption.
The SAM DA1 have two software-selectable sleep modes, idle and standby. In idle mode the CPU is
stopped while all other functions can be kept running. In standby all clocks and functions are stopped
expect those selected to continue running. The device supports SleepWalking. This feature allows the
peripheral to wake up from sleep based on predefined conditions, and thus allows the CPU to wake up
only when needed, e.g. when a threshold is crossed or a result is ready. The Event System supports
synchronous and asynchronous events, allowing peripherals to receive, react to and send events even in
standby mode.
The Flash program memory can be reprogrammed in-system through the SWD interface. The same
interface can be used for non-intrusive on-chip debug of application code. A boot loader running in the
device can use any communication interface to download and upgrade the application program in the
Flash memory.
The SAM DA1 microcontrollers are supported with a full suite of program and system development tools,
including C compilers, macro assemblers, program debugger/simulators, programmers and evaluation
kits.
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SAM DA1
2.
Configuration Summary
SAM DA1J
SAM DA1G
SAM DA1E
Pins
64
48
32
General Purpose I/O-pins
(GPIOs)
52
38
26
Flash
64/32/16KB
64/32/16KB
64/32/16KB
RWW Flash section
2KB/1KB/512B
2KB/1KB/512B
2KB/1KB/512B
SRAM
8/4/4KB
8/4/4KB
8/4/4KB
Timer Counter (TC)
instances
5
3
3
Waveform output channels 2
per TC instance
2
2
Timer Counter for Control
(TCC) instances
3
3
Waveform output channels 8/4/2
per TCC
8/4/2
6/4/2
DMA channels
12
12
12
USB interface
1
1
1
Serial Communication
Interface (SERCOM)
instances
6
6
4
Inter-IC Sound (I2S)
interface
1
1
1
Analog-to-Digital Converter 20
(ADC) channels
14
10
Analog Comparators (AC)
2
2
2
Digital-to-Analog Converter 1
(DAC) channels
1
1
Real-Time Counter (RTC)
Yes
Yes
Yes
RTC alarms
1
1
1
RTC compare values
One 32-bit value or
One 32-bit value or
One 32-bit value or
two 16-bit values
two 16-bit values
two 16-bit values
16
16
16
12x10
10x6
External Interrupt lines
3
Peripheral Touch Controller 16x16
(PTC) X and Y lines
Maximum CPU frequency
48MHz
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Datasheet Complete
40001895A-page 12
SAM DA1
Packages
Oscillators
SAM DA1J
SAM DA1G
SAM DA1E
TQFP
QFN
QFN
TQFP
TQFP
32.768kHz crystal oscillator (XOSC32K)
0.4-32MHz crystal oscillator (XOSC)
32.768kHz internal oscillator (OSC32K)
32KHz ultra-low-power internal oscillator (OSCULP32K)
8MHz high-accuracy internal oscillator (OSC8M)
48MHz Digital Frequency Locked Loop (DFLL48M)
96MHz Fractional Digital Phased Locked Loop (FDPLL96M)
Event System channels
12
12
12
SW Debug Interface
Yes
Yes
Yes
Watchdog Timer (WDT)
Yes
Yes
Yes
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SAM DA1
3.
Ordering Information
SAM D A1 E 14 A - A B T
Product Family
Package Carrier
SAM D = Baseline Cortex-M0+ MCU
T = Tape and Reel
Product Series
A1 = Automotive basic feature set + DMA,
Adv Timers, USB, I2S, PTC
Package Grade
Pin Count
B = -40 C - 105 C Matte Sn Plating (only DA1)
O
E = 32 Pins
G = 48 Pins
J = 64 Pins
O
Package Type
Flash Memory Density
A = TQFP
M = QFN Wettable Flanks
16 = 64KB
15 = 32KB
14 = 16KB
Device Variant
A = Silicon revision E (Initial revision)
B = Silicon revision F
3.1
Device Variant A
3.1.1
SAM DA1E
Ordering
Code
SRAM
(Bytes)
Package
Carrier Type Temp.Grade PTC, USB,
I2S
ATSAMDA1E 16K
14A-ABT(1)
4K
TQFP32
Tape and
Reel
-40°C to
+105°C
Yes
ATSAMDA1E 16K
14A-MBT(1)
4K
QFN32
Tape and
Reel
-40°C to
+105°C
Yes
ATSAMDA1E 32K
15A-ABT(1)
4K
TQFP32
Tape and
Reel
-40°C to
+105°C
Yes
ATSAMDA1E 32K
15A-MBT(1)
4K
QFN32
Tape and
Reel
-40°C to
+105°C
Yes
ATSAMDA1E 64K
16A-ABT(1)
8K
TQFP32
Tape and
Reel
-40°C to
+105°C
Yes
ATSAMDA1E 64K
16A-MBT(1)
8K
QFN32
Tape and
Reel
-40°C to
+105°C
Yes
1.
Flash
(Bytes)
Contact your local sales representative for availability.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 14
SAM DA1
3.1.2
SAM DA1G
Ordering
Code
SRAM
(Bytes)
Package
Carrier Type Temp.Grade PTC, USB,
I2S
ATSAMDA1 16K
G14A-ABT(1)
4K
TQFP48
Tape and
Reel
-40°C to
+105°C
Yes
ATSAMDA1 16K
G14A-MBT(1)
4K
QFN48
Tape and
Reel
-40°C to
+105°C
Yes
ATSAMDA1 32K
G15A-ABT(1)
4K
TQFP48
Tape and
Reel
-40°C to
+105°C
Yes
ATSAMDA1 32K
G15A-MBT(1)
4K
QFN48
Tape and
Reel
-40°C to
+105°C
Yes
ATSAMDA1 64K
G16A-ABT(1)
8K
TQFP48
Tape and
Reel
-40°C to
+105°C
Yes
ATSAMDA1 64K
G16A-MBT(1)
8K
QFN48
Tape and
Reel
-40°C to
+105°C
Yes
1.
3.1.3
Flash
(Bytes)
Contact your local sales representative for availability.
SAM DA1J
Ordering
Code
SRAM
(Bytes)
Package
Carrier Type Temp.Grade PTC, USB,
I2S
ATSAMDA1J 16K
14A-ABT(1)
4K
TQFP64
Tape and
Reel
-40°C to
+105°C
Yes
ATSAMDA1J 32K
15A-ABT(1)
4K
TQFP64
Tape and
Reel
-40°C to
+105°C
Yes
ATSAMDA1J 64K
16A-ABT(1)
8K
TQFP64
Tape and
Reel
-40°C to
+105°C
Yes
1.
Flash
(Bytes)
Contact your local sales representative for availability.
3.2
Device Variant B
3.2.1
SAM DA1E
Ordering
Code
Flash
(Bytes)
SRAM
(Bytes)
Package
Carrier Type Temp.Grade PTC, USB,
I2S
ATSAMDA1E 16K
14B-ABT(1)
4K
TQFP32
Tape and
Reel
-40°C to
+105°C
Yes
ATSAMDA1E 16K
14B-MBT(1)
4K
QFN32
Tape and
Reel
-40°C to
+105°C
Yes
ATSAMDA1E 32K
15B-ABT(1)
4K
TQFP32
Tape and
Reel
-40°C to
+105°C
Yes
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 15
SAM DA1
Ordering
Code
SRAM
(Bytes)
Package
Carrier Type Temp.Grade PTC, USB,
I2S
ATSAMDA1E 32K
15B-MBT(1)
4K
QFN32
Tape and
Reel
-40°C to
+105°C
Yes
ATSAMDA1E 64K
16B-ABT(1)
8K
TQFP32
Tape and
Reel
-40°C to
+105°C
Yes
ATSAMDA1E 64K
16B-MBT(1)
8K
QFN32
Tape and
Reel
-40°C to
+105°C
Yes
1.
3.2.2
Contact your local sales representative for availability.
SAM DA1G
Ordering
Code
SRAM
(Bytes)
Package
Carrier Type Temp.Grade PTC, USB,
I2S
ATSAMDA1 16K
G14B-ABT(1)
4K
TQFP48
Tape and
Reel
-40°C to
+105°C
Yes
ATSAMDA1 16K
G14B-MBT(1)
4K
QFN48
Tape and
Reel
-40°C to
+105°C
Yes
ATSAMDA1 32K
G15B-ABT(1)
4K
TQFP48
Tape and
Reel
-40°C to
+105°C
Yes
ATSAMDA1 32K
G15B-MBT(1)
4K
QFN48
Tape and
Reel
-40°C to
+105°C
Yes
ATSAMDA1 64K
G16B-ABT(1)
8K
TQFP48
Tape and
Reel
-40°C to
+105°C
Yes
ATSAMDA1 64K
G16B-MBT(1)
8K
QFN48
Tape and
Reel
-40°C to
+105°C
Yes
1.
3.2.3
Flash
(Bytes)
Flash
(Bytes)
Contact your local sales representative for availability.
SAM DA1J
Ordering
Code
SRAM
(Bytes)
Package
Carrier Type Temp.Grade PTC, USB,
I2S
ATSAMDA1J 16K
14B-ABT(1)
4K
TQFP64
Tape and
Reel
-40°C to
+105°C
Yes
ATSAMDA1J 32K
15B-ABT(1)
4K
TQFP64
Tape and
Reel
-40°C to
+105°C
Yes
ATSAMDA1J 64K
16B-ABT(1)
8K
TQFP64
Tape and
Reel
-40°C to
+105°C
Yes
1.
Flash
(Bytes)
Contact your local sales representative for availability.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 16
SAM DA1
3.3
Device Identification
The DSU - Device Service Unit peripheral provides the Device Selection bits in the Device Identification
register (DID.DEVSEL) in order to identify the device by software. The SAM DA1 variants have a reset
value of DID=0x1001drxx, with the LSB identifying the die number ('d'), the die revision ('r') and the
device selection ('xx').
Table 3-1. SAM DA1 Device Identification Values
Device Variant
DID.DEVSEL
Device ID (DID)
Reserved
0x00 - 0x28
SAMDA1J16A
0x29
0x10011429
SAMDA1J15A
0x2A
0x1001142A
SAMDA1J14A
0x2B
0x1001142B
SAMDA1G16A
0x2C
0x1001142C
SAMDA1G15A
0x2D
0x1001142D
SAMDA1G14A
0x2E
0x1001142D
SAMDA1E16A
0x2F
0x1001142F
SAMDA1E15A
0x30
0x10011430
SAMDA1E14A
0x31
0x10011431
Reserved
0x32 - 0x63
SAMDA1J16B
0x64
0x10011564
SAMDA1J15B
0x65
0x10011565
SAMDA1J14B
0x66
0x10011566
SAMDA1G16B
0x67
0x10011567
SAMDA1G15B
0x68
0x10011568
SAMDA1G14B
0x69
0x10011569
SAMDA1E16B
0x6A
0x1001156A
SAMDA1E15B
0x6B
0x1001156B
SAMDA1E14B
0x6C
0x1001156C
Reserved
0x6D - 0xFF
Note: The device variant (last letter of the ordering number) is independent of the die revision
(DSU.DID.REVISION): The device variant denotes functional differences, whereas the die revision marks
evolution of the die. The device variant denotes functional differences, whereas the die revision marks
evolution of the die.
Related Links
DID
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 17
SAM DA1
Block Diagram
64/32/16KB NVM
SERIAL
WIRE
SWDIO
DEVICE
SERVICE
UNIT
M
8/4/4KB
RAM
2KB/1KB/512B
RWW Flash Section
NVM
CONTROLLER
Cache
M
SRAM
CONTROLLER
S
S
M
HIGH SPEED
BUS MATRIX
PERIPHERAL
ACCESS CONTROLLER
S
AHB-APB
BRIDGE B
S
USB FS
DEVICE
MINI-HOST
S
AHB-APB
BRIDGE A
DMA
66xxSERCOM
SERCOM
VREF
OSC32K
XOSC32K
DMA
OSC8M
5 x TIMER / COUNTER
8 x Timer Counter
XOSC
FDPLL96M
POWER MANAGER
CLOCK
CONTROLLER
RESET
CONTROLLER
SLEEP
CONTROLLER
EVENT SYSTEM
DMA
RESETN
PAD0
PAD1
PAD2
PAD3
OSCULP32K
DFLL48M
XIN
XOUT
DM
SOF 1KHZ
PERIPHERAL
ACCESS CONTROLLER
SYSTEM CONTROLLER
XIN32
XOUT32
DP
AHB-APB
BRIDGE C
PERIPHERAL
ACCESS CONTROLLER
BOD33
DMA
3x TIMER / COUNTER
FOR CONTROL
WO0
WO1
WO0
WO1
PORT
SWCLK
CORTEX-M0+
PROCESSOR
Fmax 48 MHz
MICRO
TRACE BUFFER
IOBUS
PORT
4.
(2)
WOn
AIN[19..0]
DMA
20-CHANNEL
12-bit ADC 350KSPS
VREFA
VREFB
CMP[1..0]
GCLK_IO[7..0]
2 ANALOG
COMPARATORS
GENERIC CLOCK
CONTROLLER
REAL TIME
COUNTER
DMA
EXTINT[15..0]
NMI
VOUT
10-bit DAC
WATCHDOG
TIMER
EXTERNAL INTERRUPT
CONTROLLER
PERIPHERAL
TOUCH
CONTROLLER
DMA
INTER-IC
SOUND
CONTROLLER
1.
AIN[3..0]
VREFA
X[15..0]
Y[15..0]
MCK[1..0]
SCK[1..0]
SD[1..0]
FS[1..0]
Some products have different number of SERCOM instances, Timer/Counter instances, PTC
signals and ADC signals. Refer to the Configuration Summary for details.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 18
SAM DA1
2.
The three TCC instances have different configurations, including the number of Waveform Output
(WO) lines. Refer to the TCC Configuration for details.
Related Links
Configuration Summary
TCC Configurations
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 19
SAM DA1
Pinout
5.1
SAM DA1J - TQFP64
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PB03
PB02
PB01
PB00
PB31
PB30
PA31
PA30
VDDIN
VDDCORE
GND
PA28
RESET
PA27
PB23
PB22
5.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VDDIO
GND
PA25
PA24
PA23
PA22
PA21
PA20
PB17
PB16
PA19
PA18
PA17
PA16
VDDIO
GND
PA08
PA09
PA10
PA11
VDDIO
GND
PB10
PB11
PB12
PB13
PB14
PB15
PA12
PA13
PA14
PA15
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PA00
PA01
PA02
PA03
PB04
PB05
GNDANA
VDDANA
PB06
PB07
PB08
PB09
PA04
PA05
PA06
PA07
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 20
SAM DA1
48
47
46
45
44
43
42
41
40
39
38
37
PB03
PB02
PA31
PA30
VDDIN
VDDCORE
GND
PA28
RESET
PA27
PB23
PB22
SAM DA1G - QFN48 / TQFP48
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
VDDIO
GND
PA25
PA24
PA23
PA22
PA21
PA20
PA19
PA18
PA17
PA16
13
14
15
16
17
18
19
20
21
22
23
24
PA00
PA01
PA02
PA03
GNDANA
VDDANA
PB08
PB09
PA04
PA05
PA06
PA07
PA08
PA09
PA10
PA11
VDDIO
GND
PB10
PB11
PA12
PA13
PA14
PA15
5.2
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 21
SAM DA1
32
31
30
29
28
27
26
25
PA31
PA30
VDDIN
VDDCORE
GND
PA28
RESET
PA27
SAM DA1E - QFN32 / TQFP32
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
PA25
PA24
PA23
PA22
PA19
PA18
PA17
PA16
9
10
11
12
13
14
15
16
PA00
PA01
PA02
PA03
PA04
PA05
PA06
PA07
VDDANA
GND
PA08
PA09
PA10
PA11
PA14
PA15
5.3
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 22
SAM DA1
6.
Signal Descriptions List
The following table gives details on signal names classified by peripheral.
Signal Name Function
Type
Active Level
Analog Comparators - AC
AIN[3:0]
AC Analog Inputs
Analog
CMP[:0]
AC Comparator Outputs
Digital
Analog Digital Converter - ADC
AIN[19:0]
ADC Analog Inputs
Analog
VREFA
ADC Voltage External Reference A
Analog
VREFB
ADC Voltage External Reference B
Analog
Digital Analog Converter - DAC
VOUT
DAC Voltage output
Analog
VREFA
DAC Voltage External Reference
Analog
External Interrupt Controller
EXTINT[15:0] External Interrupts
Input
NMI
Input
External Non-Maskable Interrupt
Generic Clock Generator - GCLK
GCLK_IO[7:0] Generic Clock (source clock or generic clock generator
output)
I/O
Inter-IC Sound Controller - I2S
MCK[1:0]
Master Clock
I/O
SCK[1:0]
Serial Clock
I/O
FS[1:0]
I2S Word Select or TDM Frame Sync
I/O
SD[1:0]
Serial Data Input or Output
I/O
Power Manager - PM
RESETN
Reset
Input
Low
Serial Communication Interface - SERCOMx
PAD[3:0]
SERCOM I/O Pads
I/O
System Control - SYSCTRL
XIN
Crystal Input
Analog/ Digital
XIN32
32kHz Crystal Input
Analog/ Digital
XOUT
Crystal Output
Analog
XOUT32
32kHz Crystal Output
Analog
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 23
SAM DA1
Signal Name Function
Type
Active Level
Timer Counter - TCx
WO[1:0]
Waveform Outputs
Output
Timer Counter - TCCx
WO[1:0]
Waveform Outputs
Output
Peripheral Touch Controller - PTC
X[15:0]
PTC Input
Analog
Y[15:0]
PTC Input
Analog
General Purpose I/O - PORT
PA25 - PA00
Parallel I/O Controller I/O Port A
I/O
PA28 - PA27
Parallel I/O Controller I/O Port A
I/O
PA31 - PA30
Parallel I/O Controller I/O Port A
I/O
PB17 - PB00
Parallel I/O Controller I/O Port B
I/O
PB23 - PB22
Parallel I/O Controller I/O Port B
I/O
PB31 - PB30
Parallel I/O Controller I/O Port B
I/O
Universal Serial Bus - USB
DP
DP for USB
I/O
DM
DM for USB
I/O
SOF 1kHz
USB Start of Frame
I/O
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 24
SAM DA1
7.
I/O Multiplexing and Considerations
7.1
Multiplexed Signals
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be
assigned to one of the peripheral functions A, B, C, D, E, F, G or H. To enable a peripheral function on a
pin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin
(PINCFGn.PMUXEN, n = 0-31) in the PORT must be written to one. The selection of peripheral function
A to H is done by writing to the Peripheral Multiplexing Odd and Even bits in the Peripheral Multiplexing
register (PMUXn.PMUXE/O) in the PORT.
This table describes the peripheral signals multiplexed to the PORT I/O pins.
Table 7-1. PORT Function Multiplexing
Pin
SAMDA1E
SAMDA1G
I/O Pin
Supply
SAMDA1J
B(1)(2)
A
EIC
REF
ADC
AC
PTC
DAC
C
D
E
F
G
H
SERCOM(1)(2)
SERCOM-ALT
TC(3)
TCC
COM
AC/
/TCC
1
1
1
PA00
VDDANA
EXTINT[0]
SERCOM1/
PAD[0]
TCC2/WO[0]
2
2
2
PA01
VDDANA
EXTINT[1]
SERCOM1/
PAD[1]
TCC2/WO[1]
3
3
3
PA02
VDDANA
EXTINT[2]
4
4
4
PA03
VDDANA
EXTINT[3]
5
PB04
VDDANA
6
PB05
VDDANA
9
PB06
10
7
AIN[0]
Y[0]
AIN[1]
Y[1]
EXTINT[4]
AIN[12]
Y[10]
EXTINT[5]
AIN[13]
Y[11]
VDDANA
EXTINT[6]
AIN[14]
Y[12]
PB07
VDDANA
EXTINT[7]
AIN[15]
Y[13]
11
PB08
VDDANA
EXTINT[8]
AIN[2]
Y[14]
SERCOM4/
PAD[0]
TC4/WO[0]
8
12
PB09
VDDANA
EXTINT[9]
AIN[3]
Y[15]
SERCOM4/
PAD[1]
TC4/WO[1]
5
9
13
PA04
VDDANA
EXTINT[4]
6
10
14
PA05
VDDANA
7
11
15
PA06
8
12
16
11
13
12
ADC/
VREFA
DAC/
VREFA
VOUT
AIN[4]
AIN[0]
Y[2]
SERCOM0/
PAD[0]
TCC0/WO[0]
EXTINT[5]
AIN[5]
AIN[1]
Y[3]
SERCOM0/
PAD[1]
TCC0/WO[1]
VDDANA
EXTINT[6]
AIN[6]
AIN[2]
Y[4]
SERCOM0/
PAD[2]
TCC1/WO[0]
PA07
VDDANA
EXTINT[7]
AIN[7]
AIN[3]
Y[5]
SERCOM0/
PAD[3]
TCC1/WO[1]
17
PA08
VDDIO
NMI
AIN[16]
X[0]
SERCOM0/
PAD[0]
SERCOM2/
PAD[0]
TCC0/WO[0]
TCC1/
WO[2]
I2S/SD[1]
14
18
PA09
VDDIO
EXTINT[9]
AIN[17]
X[1]
SERCOM0/
PAD[1]
SERCOM2/
PAD[1]
TCC0/WO[1]
TCC1/
WO[3]
I2S/
MCK[0]
13
15
19
PA10
VDDIO
EXTINT[10]
AIN[18]
X[2]
SERCOM0/
PAD[2]
SERCOM2/
PAD[2]
TCC1/WO[0]
TCC0/
WO[2]
I2S/
SCK[0]
GCLK_IO[4]
14
16
20
PA11
VDDIO
EXTINT[11]
AIN[19]
X[3]
SERCOM0/
PAD[3]
SERCOM2/
PAD[3]
TCC1/WO[1]
TCC0/
WO[3]
I2S/FS[0]
GCLK_IO[5]
19
23
PB10
VDDIO
EXTINT[10]
SERCOM4/
PAD[2]
TC5/WO[0]
TCC0/
WO[4]
I2S/
MCK[1]
GCLK_IO[4]
20
24
PB11
VDDIO
EXTINT[11]
SERCOM4/
PAD[3]
TC5/WO[1]
TCC0/
WO[5]
I2S/
SCK[1]
GCLK_IO[5]
25
PB12
VDDIO
EXTINT[12]
X[12]
SERCOM4/
PAD[0]
TC4/WO[0]
TCC0/
WO[6]
I2S/FS[1]
GCLK_IO[6]
26
PB13
VDDIO
EXTINT[13]
X[13]
SERCOM4/
PAD[1]
TC4/WO[1]
TCC0/
WO[7]
27
PB14
VDDIO
EXTINT[14]
X[14]
SERCOM4/
PAD[2]
TC5/WO[0]
© 2017 Microchip Technology Inc.
ADC/
VREFB
GCLK
Datasheet Complete
I2S/SD[0]
GCLK_IO[7]
GCLK_IO[0]
40001895A-page 25
SAM DA1
Pin
SAMDA1E
SAMDA1G
I/O Pin
Supply
SAMDA1J
B(1)(2)
A
EIC
REF
ADC
C
AC
PTC
D
E
F
G
SERCOM-ALT
TC(3)
TCC
COM
AC/
/TCC
GCLK
TC5/WO[1]
GCLK_IO[1]
PB15
VDDIO
EXTINT[15]
21
29
PA12
VDDIO
EXTINT[12]
SERCOM2/
PAD[0]
SERCOM4/
PAD[0]
TCC2/WO[0]
TCC0/
WO[6]
AC/CMP[0]
22
30
PA13
VDDIO
EXTINT[13]
SERCOM2/
PAD[1]
SERCOM4/
PAD[1]
TCC2/WO[1]
TCC0/
WO[7]
AC/CMP[1]
15
23
31
PA14
VDDIO
EXTINT[14]
SERCOM2/
PAD[2]
SERCOM4/
PAD[2]
TC3/WO[0]
TCC0/
WO[4]
GCLK_IO[0]
16
24
32
PA15
VDDIO
EXTINT[15]
SERCOM2/
PAD[3]
SERCOM4/
PAD[3]
TC3/WO[1]
TCC0/
WO[5]
GCLK_IO[1]
17
25
35
PA16
VDDIO
EXTINT[0]
X[4]
SERCOM1/
PAD[0]
SERCOM3/
PAD[0]
TCC2/WO[0]
TCC0/
WO[6]
GCLK_IO[2]
18
26
36
PA17
VDDIO
EXTINT[1]
X[5]
SERCOM1/
PAD[1]
SERCOM3/
PAD[1]
TCC2/WO[1]
TCC0/
WO[7]
GCLK_IO[3]
19
27
37
PA18
VDDIO
EXTINT[2]
X[6]
SERCOM1/
PAD[2]
SERCOM3/
PAD[2]
TC3/WO[0]
TCC0/
WO[2]
AC/CMP[0]
20
28
38
PA19
VDDIO
EXTINT[3]
X[7]
SERCOM1/
PAD[3]
SERCOM3/
PAD[3]
TC3/WO[1]
TCC0/
WO[3]
I2S/SD[0]
AC/CMP[1]
39
PB16
VDDIO
EXTINT[0]
SERCOM5/
PAD[0]
TC6/WO[0]
TCC0/
WO[4]
I2S/SD[1]
GCLK_IO[2]
40
PB17
VDDIO
EXTINT[1]
SERCOM5/
PAD[1]
TC6/WO[1]
TCC0/
WO[5]
I2S/
MCK[0]
GCLK_IO[3]
29
41
PA20
VDDIO
EXTINT[4]
X[8]
SERCOM5/
PAD[2]
SERCOM3/
PAD[2]
TC7/WO[0]
TCC0/
WO[6]
I2S/
SCK[0]
GCLK_IO[4]
30
42
PA21
VDDIO
EXTINT[5]
X[9]
SERCOM5/
PAD[3]
SERCOM3/
PAD[3]
TC7/WO[1]
TCC0/
WO[7]
I2S/FS[0]
GCLK_IO[5]
21
31
43
PA22
VDDIO
EXTINT[6]
X[10]
SERCOM3/
PAD[0]
SERCOM5/
PAD[0]
TC4/WO[0]
TCC0/
WO[4]
22
32
44
PA23
VDDIO
EXTINT[7]
X[11]
SERCOM3/
PAD[1]
SERCOM5/
PAD[1]
TC4/WO[1]
TCC0/
WO[5]
USB/SOF
1kHz
23
33
45
PA24(5)
VDDIO
EXTINT[12]
SERCOM3/
PAD[2]
SERCOM5/
PAD[2]
TC5/WO[0]
TCC1/
WO[2]
USB/DM
24
34
46
PA25(5)
VDDIO
EXTINT[13]
SERCOM3/
PAD[3]
SERCOM5/
PAD[3]
TC5/WO[1]
TCC1/
WO[3]
USB/DP
37
49
PB22
VDDIO
EXTINT[6]
SERCOM5/
PAD[2]
TC7/WO[0]
GCLK_IO[0]
38
50
PB23
VDDIO
EXTINT[7]
SERCOM5/
PAD[3]
TC7/WO[1]
GCLK_IO[1]
25
39
51
PA27
VDDIO
EXTINT[15]
27
41
53
PA28
VDDIO
EXTINT[8]
31
45
57
PA30
VDDIO
EXTINT[10]
SERCOM1/
PAD[2]
TCC1/WO[0]
SWCLK
32
46
58
PA31
VDDIO
EXTINT[11]
SERCOM1/
PAD[3]
TCC1/WO[1]
SWDIO(4)
59
PB30
VDDIO
EXTINT[14]
SERCOM5/
PAD[0]
TCC0/WO[0]
TCC1/
WO[2]
60
PB31
VDDIO
EXTINT[15]
SERCOM5/
PAD[1]
TCC0/WO[1]
TCC1/
WO[3]
61
PB00
VDDANA
EXTINT[0]
AIN[8]
Y[6]
SERCOM5/
PAD[2]
TC7/WO[0]
62
PB01
VDDANA
EXTINT[1]
AIN[9]
Y[7]
SERCOM5/
PAD[3]
TC7/WO[1]
47
63
PB02
VDDANA
EXTINT[2]
AIN[10]
Y[8]
SERCOM5/
PAD[0]
TC6/WO[0]
48
64
PB03
VDDANA
EXTINT[3]
AIN[11]
Y[9]
SERCOM5/
PAD[1]
TC6/WO[1]
2.
SERCOM4/
PAD[3]
H
28
1.
X[15]
DAC
SERCOM(1)(2)
GCLK_IO[6]
GCLK_IO[7]
GCLK_IO[0]
GCLK_IO[0]
GCLK_IO[0]
All analog pin functions are on peripheral function B. Peripheral function B must be selected to
disable the digital control of the pin.
Only some pins can be used in SERCOM I2C mode.
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SAM DA1
3.
4.
5.
Note that not all TC6 and TC7 waveform outputs are available on SAM DA1E and G devices but
may still be used for internal counting/timing applications.
This function is only activated in the presence of a debugger.
If the PA24 and PA25 pins are not connected, it is recommended to enable a pull-up on PA24 and
PA25 through input GPIO mode. The aim is to avoid an eventually extract power consumption
( MASK)
return 1;
return 0;
Dithering on Period
Writing DITHERCY in PER will lead to an average PWM period configured by the following formulas.
DITH4 mode:
��������� =
DITHERCY
1
+ PER
16
�GCLK_TCC
Note: If DITH4 mode is enabled, the last 4 significant bits from PER/CCx or COUNT register correspond
to the DITHERCY value, rest of the bits corresponds to PER/CCx or COUNT value.
DITH5 mode:
��������� =
DITHERCY
1
+ PER
32
�GCLK_TCC
��������� =
DITHERCY
1
+ PER
64
�GCLK_TCC
DITH6 mode:
Dithering on Pulse Width
Writing DITHERCY in CCx will lead to an average PWM pulse width configured by the following formula.
DITH4 mode:
������������ℎ =
DITHERCY
1
+ CCx
16
�GCLK_TCC
������������ℎ =
DITHERCY
1
+ CCx
32
�GCLK_TCC
������������ℎ =
DITHERCY
1
+ CCx
64
�GCLK_TCC
DITH5 mode:
DITH6 mode:
Note: The PWM period will remain static in this case.
33.6.3.4 Ramp Operations
Three ramp operation modes are supported. All of them require the timer/counter running in single-slope
PWM generation. The ramp mode is selected by writing to the Ramp Mode bits in the Waveform Control
register (WAVE.RAMP).
RAMP1 Operation
This is the default PWM operation, described in Single-Slope PWM Generation.
RAMP2 Operation
These operation modes are dedicated for power factor correction (PFC), Half-Bridge and Push-Pull
SMPS topologies, where two consecutive timer/counter cycles are interleaved, see Figure 33-18. In cycle
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SAM DA1
A, odd channel output is disabled, and in cycle B, even channel output is disabled. The ramp index
changes after each update, but can be software modified using the Ramp index command bits in Control
B Set register (CTRLBSET.IDXCMD).
Standard RAMP2 (RAMP2) Operation
Ramp A and B periods are controlled by the PER register value. The PER value can be different on each
ramp by the Circular Period buffer option in the Wave register (WAVE.CIPEREN=1). This mode uses a
two-channel TCC to generate two output signals, or one output signal with another CC channel enabled
in capture mode.
Figure 33-18. RAMP2 Standard Operation
Ramp
A
B
A
B
Retrigger
on
FaultA
TOP(B)
TOP(A)
CC0
TOP(B)
CIPEREN = 1
CC1
CC1
COUNT
"clear" update
"match"
CC0
ZERO
WO[0]
POL0 = 1
WO[1]
Keep on FaultB
POL1 = 1
FaultA input
FaultB input
Alternate RAMP2 (RAMP2A) Operation
Alternate RAMP2 operation is similar to RAMP2, but CC0 controls both WO[0] and WO[1] waveforms
when the corresponding circular buffer option is enabled (CIPEREN=1). The waveform polarity is the
same on both outputs. Channel 1 can be used in capture mode.
Figure 33-19. RAMP2 Alternate Operation
Ramp
A
B
A
TOP(B)
TOP(A)
B
Retrigger
on
FaultA
CC0(B)
COUNT
CC0(A)
"clear" update
"match"
TOP(B)
CIPEREN = 1
CC0(B)
CICCEN0 = 1
CC0(A)
ZERO
WO[0]
Keep on FaultB
WO[1]
POL0 = 1
FaultA input
FaultB input
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SAM DA1
33.6.3.5 Recoverable Faults
Recoverable faults can restart or halt the timer/counter. Two faults, called Fault A and Fault B, can trigger
recoverable fault actions on the compare channels CC0 and CC1 of the TCC. The compare channels'
outputs can be clamped to inactive state either as long as the fault condition is present, or from the first
valid fault condition detection on until the end of the timer/counter cycle.
Fault Inputs
The first two channel input events (TCCxMC0 and TCCxMC1) can be used as Fault A and Fault B inputs,
respectively. Event system channels connected to these fault inputs must be configured as
asynchronous. The TCC must work in a PWM mode.
Fault Filtering
There are three filters available for each input Fault A and Fault B. They are configured by the
corresponding Recoverable Fault n Configuration registers (FCTRLA and FCTRLB). The three filters can
either be used independently or in any combination.
Input
Filtering
By default, the event detection is asynchronous. When the event occurs, the fault system
will immediately and asynchronously perform the selected fault action on the compare
channel output, also in device power modes where the clock is not available. To avoid false
fault detection on external events (e.g. due to a glitch on an I/O port) a digital filter can be
enabled and configured by the Fault B Filter Value bits in the Fault n Configuration registers
(FCTRLn.FILTERVAL). If the event width is less than FILTERVAL (in clock cycles), the
event will be discarded. A valid event will be delayed by FILTERVAL clock cycles.
Fault
Blanking
This ignores any fault input for a certain time just after a selected waveform output edge.
This can be used to prevent false fault triggering due to signal bouncing, as shown in the
figure below. Blanking can be enabled by writing an edge triggering configuration to the
Fault n Blanking Mode bits in the Recoverable Fault n Configuration register
(FCTRLn.BLANK). The desired duration of the blanking must be written to the Fault n
Blanking Time bits (FCTRLn.BLANKVAL).
The blanking time tbis calculated by
�� =
1 + BLANKVAL
�GCLK_TCCx_PRESC
Here, fGCLK_TCCx_PRESC is the frequency of the prescaled peripheral clock frequency
fGCLK_TCCx.
The maximum blanking time (FCTRLn.BLANKVAL=
255) at fGCLK_TCCx=96MHz is 2.67µs (no prescaler) or 170µs (prescaling). For
fGCLK_TCCx=1MHz, the maximum blanking time is either 170µs (no prescaling) or 10.9ms
(prescaling enabled).
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SAM DA1
Figure 33-20. Fault Blanking in RAMP1 Operation with Inverted Polarity
"clear" update
"match"
TOP
"Fault input enabled"
- "Fault input disabled"
CC0
x
"Fault discarded"
COUNT
ZERO
CMP0
FCTRLA.BLANKVAL = 0
FCTRLA.BLANKVAL > 0
FaultA Blanking
FCTRLA.BLANKVAL > 0
-
-
x
xxx
FaultA Input
WO[0]
Fault
Qualification
This is enabled by writing a '1' to the Fault n Qualification bit in the Recoverable Fault
n Configuration register (FCTRLn.QUAL). When the recoverable fault qualification is
enabled (FCTRLn.QUAL=1), the fault input is disabled all the time the corresponding
channel output has an inactive level, as shown in the figures below.
Figure 33-21. Fault Qualification in RAMP1 Operation
MAX
"clear" update
TOP
"match"
CC0
COUNT
"Fault input enabled"
- "Fault input disabled"
CC1
x
"Fault discarded"
ZERO
Fault A Input Qual
-
-
-
-
-
x x x
x x x x x x
Fault Input A
Fault B Input Qual
-
-
-
x x x
-
x x x x x
-
x x x x x x x
-
x x x x
Fault Input B
Figure 33-22. Fault Qualification in RAMP2 Operation with Inverted Polarity
Cycle
"clear" update
MAX
"match"
TOP
"Fault input enabled"
COUNT
CC0
- "Fault input disabled"
x
CC1
"Fault discarded"
ZERO
Fault A Input Qual
-
-
x
x
-
x
x
x
x
x
x
x
x
x
x
Fault Input A
-
Fault B Input Qual
x
x
x
x
x
-
x
x
x
x
x
x
x
x
x
-
x
Fault Input B
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SAM DA1
Fault Actions
Different fault actions can be configured individually for Fault A and Fault B. Most fault actions are not
mutually exclusive; hence two or more actions can be enabled at the same time to achieve a result that is
a combination of fault actions.
Keep
Action
This is enabled by writing the Fault n Keeper bit in the Recoverable Fault n Configuration
register (FCTRLn.KEEP) to '1'. When enabled, the corresponding channel output will be
clamped to zero as long as the fault condition is present. The clamp will be released on the
start of the first cycle after the fault condition is no longer present, see next Figure.
Figure 33-23. Waveform Generation with Fault Qualification and Keep Action
MAX
"clear" update
TOP
"match"
"Fault input enabled"
CC0
COUNT
- "Fault input disabled"
x
"Fault discarded"
ZERO
Fault A Input Qual
-
-
-
-
x
-
x
x
x
Fault Input A
WO[0]
Restart
Action
KEEP
KEEP
This is enabled by writing the Fault n Restart bit in Recoverable Fault n Configuration register
(FCTRLn.RESTART) to '1'. When enabled, the timer/counter will be restarted as soon as the
corresponding fault condition is present. The ongoing cycle is stopped and the timer/counter
starts a new cycle, see Figure 33-24. In Ramp 1 mode, when the new cycle starts, the
compare outputs will be clamped to inactive level as long as the fault condition is present.
Note: For RAMP2 operation, when a new timer/counter cycle starts the cycle index will
change automatically, see Figure 33-25. Fault A and Fault B are qualified only during the
cycle A and cycle B respectively: Fault A is disabled during cycle B, and Fault B is disabled
during cycle A.
Figure 33-24. Waveform Generation in RAMP1 mode with Restart Action
MAX
"clear" update
"match"
TOP
COUNT
CC0
CC1
ZERO
Restart
Restart
Fault Input A
WO[0]
WO[1]
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SAM DA1
Figure 33-25. Waveform Generation in RAMP2 mode with Restart Action
Cycle
CCx=ZERO
CCx=TOP
"clear" update
"match"
MAX
TOP
COUNT
CC0/CC1
ZERO
No fault A action
in cycle B
Restart
Fault Input A
WO[0]
WO[1]
Capture
Action
Several capture actions can be selected by writing the Fault n Capture Action bits in the
Fault n Control register (FCTRLn.CAPTURE). When one of the capture operations is
selected, the counter value is captured when the fault occurs. These capture operations are
available:
•
CAPT - the equivalent to a standard capture operation, for further details refer to
Capture Operations
•
CAPTMIN - gets the minimum time stamped value: on each new local minimum
captured value, an event or interrupt is issued.
•
CAPTMAX - gets the maximum time stamped value: on each new local maximum
captured value, an event or interrupt (IT) is issued, see Figure 33-26.
•
LOCMIN - notifies by event or interrupt when a local minimum captured value is
detected.
•
LOCMAX - notifies by event or interrupt when a local maximum captured value is
detected.
•
DERIV0 - notifies by event or interrupt when a local extreme captured value is
detected, see Figure 33-27.
CCx Content:
In CAPTMIN and CAPTMAX operations, CCx keeps the respective extremum captured
values, see Figure 33-26. In LOCMIN, LOCMAX or DERIV0 operation, CCx follows the
counter value at fault time, see Figure 33-27.
Before enabling CAPTMIN or CAPTMAX mode of capture, the user must initialize the
corresponding CCx register value to a value different from zero (for CAPTMIN) top (for
CAPTMAX). If the CCx register initial value is zero (for CAPTMIN) top (for CAPTMAX), no
captures will be performed using the corresponding channel.
MCx Behaviour:
In LOCMIN and LOCMAX operation, capture is performed on each capture event. The MCx
interrupt flag is set only when the captured value is upper or equal (for LOCMIN) or lower or
equal (for LOCMAX) to the previous captured value. So interrupt flag is set when a new
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SAM DA1
relative local Minimum (for CAPTMIN) or Maximum (for CAPTMAX) value has been
detected. DERIV0 is equivalent to an OR function of (LOCMIN, LOCMAX).
In CAPT operation, capture is performed on each capture event. The MCx interrupt flag is
set on each new capture.
In CAPTMIN and CAPTMAX operation, capture is performed only when on capture event
time, the counter value is lower (for CAPTMIN) or upper (for CAPMAX) than the last
captured value. The MCx interrupt flag is set only when on capture event time, the counter
value is upper or equal (for CAPTMIN) or lower or equal (for CAPTMAX) to the value
captured on the previous event. So interrupt flag is set when a new absolute local Minimum
(for CAPTMIN) or Maximum (for CAPTMAX) value has been detected.
Interrupt Generation
In CAPT mode, an interrupt is generated on each filtered Fault n and each dedicated CCx
channel capture counter value. In other modes, an interrupt is only generated on an extreme
captured value.
Figure 33-26. Capture Action “CAPTMAX”
TOP
COUNT
"clear" update
"match"
CC0
ZERO
FaultA Input
CC0 Event/
Interrupt
Figure 33-27. Capture Action “DERIV0”
TOP
COUNT
"update"
"match"
CC0
ZERO
FaultA Input
CC0 Event/
Interrupt
Hardware
This is configured by writing 0x1 to the Fault n Halt mode bits in the Recoverable Fault n
Halt Action Configuration register (FCTRLn.HALT). When enabled, the timer/counter is halted and the
cycle is extended as long as the corresponding fault is present.
The next figure ('Waveform Generation with Halt and Restart Actions') shows an example
where both restart action and hardware halt action are enabled for Fault A. The compare
channel 0 output is clamped to inactive level as long as the timer/counter is halted. The
timer/counter resumes the counting operation as soon as the fault condition is no longer
present. As the restart action is enabled in this example, the timer/counter is restarted
after the fault condition is no longer present.
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SAM DA1
The figure after that ('Waveform Generation with Fault Qualification, Halt, and Restart
Actions') shows a similar example, but with additionally enabled fault qualification. Here,
counting is resumed after the fault condition is no longer present.
Note that in RAMP2 and RAMP2A operations, when a new timer/counter cycle starts, the
cycle index will automatically change.
Figure 33-28. Waveform Generation with Halt and Restart Actions
MAX
"clear" update
"match"
TOP
COUNT
CC0
HALT
ZERO
Restart
Restart
Fault Input A
WO[0]
Figure 33-29. Waveform Generation with Fault Qualification, Halt, and Restart
Actions
MAX
"update"
"match"
TOP
COUNT
CC0
HALT
ZERO
Resume
Fault A Input Qual
-
-
-
-
x
x
-
x
Fault Input A
WO[0]
Software
Halt Action
KEEP
This is configured by writing 0x2 to the Fault n Halt mode bits in the Recoverable Fault n
configuration register (FCTRLn.HALT). Software halt action is similar to hardware halt
action, but in order to restart the timer/counter, the corresponding fault condition must not
be present anymore, and the corresponding FAULT n bit in the STATUS register must be
cleared by software.
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SAM DA1
Figure 33-30. Waveform Generation with Software Halt, Fault Qualification, Keep and Restart
Actions
MAX
"update"
"match"
TOP
COUNT
CC0
HALT
ZERO
Restart
Fault A Input Qual
-
-
Restart
-
x
-
x
Fault Input A
Software Clear
WO[0]
KEEP
NO
KEEP
33.6.3.6 Non-Recoverable Faults
The non-recoverable fault action will force all the compare outputs to a pre-defined level programmed into
the Driver Control register (DRVCTRL.NRE and DRVCTRL.NRV). The non-recoverable fault input (EV0
and EV1) actions are enabled in Event Control register (EVCTRL.EVACT0 and EVCTRL.EVACT1).
To avoid false fault detection on external events (e.g. a glitch on an I/O port) a digital filter can be enabled
using Non-Recoverable Fault Input x Filter Value bits in the Driver Control register
(DRVCTRL.FILTERVALn). Therefore, the event detection is synchronous, and event action is delayed by
the selected digital filter value clock cycles.
When the Fault Detection on Debug Break Detection bit in Debug Control register (DGBCTRL.FDDBD) is
written to '1', a non-recoverable Debug Faults State and an interrupt (DFS) is generated when the system
goes in debug operation.
33.6.3.7 Waveform Extension
Figure 33-31 shows a schematic diagram of actions of the four optional units that follow the recoverable
fault stage on a port pin pair: Output Matrix (OTMX), Dead-Time Insertion (DTI), SWAP and Pattern
Generation. The DTI and SWAP units can be seen as a four port pair slices:
•
Slice 0 DTI0 / SWAP0 acting on port pins (WO[0], WO[WO_NUM/2 +0])
•
Slice 1 DTI1 / SWAP1 acting on port pins (WO[1], WO[WO_NUM/2 +1])
And more generally:
•
Slice n DTIx / SWAPx acting on port pins (WO[x], WO[WO_NUM/2 +x])
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SAM DA1
Figure 33-31. Waveform Extension Stage Details
WEX
OTMX
PORTS
DTI
SWAP
OTMX[x+WO_NUM/2]
PATTERN
PGV[x+WO_NUM/2]
P[x+WO_NUM/2]
LS
OTMX
DTIx
PGO[x+WO_NUM/2]
DTIxEN
INV[x+WO_NUM/2]
SWAPx
PGO[x]
HS
INV[x]
P[x]
OTMX[x]
PGV[x]
The output matrix (OTMX) unit distributes compare channels, according to the selectable configurations
in Table 33-4.
Table 33-4. Output Matrix Channel Pin Routing Configuration
Value
OTMX[x]
0x0
CC3
CC2
CC1
CC0
CC3
CC2
CC1
CC0
0x1
CC1
CC0
CC1
CC0
CC1
CC0
CC1
CC0
0x2
CC0
CC0
CC0
CC0
CC0
CC0
CC0
CC0
0x3
CC1
CC1
CC1
CC1
CC1
CC1
CC1
CC0
Notes on Table 33-4:
•
Configuration 0x0 is the default configuration. The channel location is the default one, and channels
are distributed on outputs modulo the number of channels. Channel 0 is routed to the Output matrix
output OTMX[0], and Channel 1 to OTMX[1]. If there are more outputs than channels, then channel
0 is duplicated to the Output matrix output OTMX[CC_NUM], channel 1 to OTMX[CC_NUM+1] and
so on.
•
Configuration 0x1 distributes the channels on output modulo half the number of channels. This
assigns twice the number of output locations to the lower channels than the default configuration.
This can be used, for example, to control the four transistors of a full bridge using only two compare
channels.
Using pattern generation, some of these four outputs can be overwritten by a constant level,
enabling flexible drive of a full bridge in all quadrant configurations.
•
Configuration 0x2 distributes compare channel 0 (CC0) to all port pins. With pattern generation, this
configuration can control a stepper motor.
•
Configuration 0x3 distributes the compare channel CC0 to the first output, and the channel CC1 to
all other outputs. Together with pattern generation and the fault extension, this configuration can
control up to seven LED strings, with a boost stage.
Table
33-5. Example: four compare channels on four outputs
•
Value
OTMX[3]
OTMX[2]
OTMX[1]
OTMX[0]
0x0
CC3
CC2
CC1
CC0
0x1
CC1
CC0
CC1
CC0
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SAM DA1
Value
OTMX[3]
OTMX[2]
OTMX[1]
OTMX[0]
0x2
CC0
CC0
CC0
CC0
0x3
CC1
CC1
CC1
CC0
The dead-time insertion (DTI) unit generates OFF time with the non-inverted low side (LS) and inverted
high side (HS) of the wave generator output forced at low level. This OFF time is called dead time. Deadtime insertion ensures that the LS and HS will never switch simultaneously.
The DTI stage consists of four equal dead-time insertion generators; one for each of the first four
compare channels. Figure 33-32 shows the block diagram of one DTI generator. The four channels have
a common register which controls the dead time, which is independent of high side and low side setting.
Figure 33-32. Dead-Time Generator Block Diagram
DTHS
DTLS
Dead Time Generator
LOAD
EN
Counter
=0
D
OTMX output
"DTLS"
Q
(To PORT)
"DTHS"
Edge Detect
(To PORT)
As shown in Figure 33-33, the 8-bit dead-time counter is decremented by one for each peripheral clock
cycle until it reaches zero. A non-zero counter value will force both the low side and high side outputs into
their OFF state. When the output matrix (OTMX) output changes, the dead-time counter is reloaded
according to the edge of the input. When the output changes from low to high (positive edge) it initiates a
counter reload of the DTLS register. When the output changes from high to low (negative edge) it reloads
the DTHS register.
Figure 33-33. Dead-Time Generator Timing Diagram
"dti_cnt"
T
tP
tDTILS
t DTIHS
"OTMX output"
"DTLS"
"DTHS"
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 604
SAM DA1
The pattern generator unit produces a synchronized bit pattern across the port pins it is connected to.
The pattern generation features are primarily intended for handling the commutation sequence in
brushless DC motors (BLDC), stepper motors, and full bridge control. See also Figure 33-34.
Figure 33-34. Pattern Generator Block Diagram
COUNT
UPDATE
BV
PGEB[7:0]
EN
BV
PGE[7:0]
PGVB[7:0]
EN
SWAP output
PGV[7:0]
WOx[7:0]
As with other double-buffered timer/counter registers, the register update is synchronized to the UPDATE
condition set by the timer/counter waveform generation operation. If synchronization is not required by
the application, the software can simply access directly the PATT.PGE, PATT.PGV bits registers.
33.6.4
DMA, Interrupts, and Events
Table 33-6. Module Requests for TCC
Condition
Interrupt
request
Event
output
Overflow / Underflow
Yes
Yes
Channel Compare
Match or Capture
Yes
Yes
Retrigger
Yes
Yes
Count
Yes
Yes
Capture Overflow Error
Yes
Debug Fault State
Yes
Recoverable Faults
Yes
Event
input
Yes(2)
DMA
request
DMA request is
cleared
Yes(1)
On DMA acknowledge
Yes(3)
For circular buffering:
on DMA acknowledge
For capture channel:
when CCx register is
read
Non-Recoverable Faults Yes
TCCx Event 0 input
Yes(4)
TCCx Event 1 input
Yes(5)
© 2017 Microchip Technology Inc.
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SAM DA1
Notes:
1. DMA request set on overflow, underflow or re-trigger conditions.
2. Can perform capture or generate recoverable fault on an event input.
3. In capture or circular modes.
4. On event input, either action can be executed:
– re-trigger counter
– control counter direction
– stop the counter
– decrement the counter
– perform period and pulse width capture
– generate non-recoverable fault
5. On event input, either action can be executed:
– re-trigger counter
–
–
–
–
–
increment or decrement counter depending on direction
start the counter
increment or decrement counter based on direction
increment counter regardless of direction
generate non-recoverable fault
33.6.4.1 DMA Operation
The TCC can generate the following DMA requests:
Counter
overflow
(OVF)
If the Ones-shot Trigger mode in the control A register (CTRLA.DMAOS) is written to '0',
the TCC generates a DMA request on each cycle when an update condition (overflow,
underflow or re-trigger) is detected.
When an update condition (overflow, underflow or re-trigger) is detected while
CTRLA.DMAOS=1, the TCC generates a DMA trigger on the cycle following the DMA
One-Shot Command written to the Control B register (CTRLBSET.CMD=DMAOS).
In both cases, the request is cleared by hardware on DMA acknowledge.
Channel
A DMA request is set only on a compare match if CTRLA.DMAOS=0. The request is
Match (MCx) cleared by hardware on DMA acknowledge.
When CTRLA.DMAOS=1, the DMA requests are not generated.
Channel
Capture
(MCx)
For a capture channel, the request is set when valid data is present in the CCx register,
and cleared once the CCx register is read.
In this operation mode, the CTRLA.DMAOS bit value is ignored.
DMA Operation with Circular Buffer
When circular buffer operation is enabled, the buffer registers must be written in a correct order and
synchronized to the update times of the timer. The DMA triggers of the TCC provide a way to ensure a
safe and correct update of circular buffers.
Note: Circular buffer are intended to be used with RAMP2, RAMP2A and DSBOTH operation only.
DMA Operation with Circular Buffer in RAMP and RAMP2A Mode
When a CCx channel is selected as a circular buffer, the related DMA request is not set on a compare
match detection, but on start of ramp B.
© 2017 Microchip Technology Inc.
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SAM DA1
If at least one circular buffer is enabled, the DMA overflow request is conditioned to the start of ramp A
with an effective DMA transfer on previous ramp B (DMA acknowledge).
The update of all circular buffer values for ramp A can be done through a DMA channel triggered on a MC
trigger. The update of all circular buffer values for ramp B, can be done through a second DMA channel
triggered by the overflow DMA request.
Figure 33-35. DMA Triggers in RAMP and RAMP2 Operation Mode and Circular Buffer Enabled
Ramp
Cycle
A
B
A
B
A
B
N-1
N-2
N
"update"
COUNT
ZERO
STATUS.IDX
DMA_CCx_req
DMA Channel i
Update ramp A
DMA_OVF_req
DMA Channel j
Update ramp B
DMA Operation with Circular Buffer in DSBOTH Mode
When a CC channel is selected as a circular buffer, the related DMA request is not set on a compare
match detection, but on start of down-counting phase.
If at least one circular buffer is enabled, the DMA overflow request is conditioned to the start of upcounting phase with an effective DMA transfer on previous down-counting phase (DMA acknowledge).
When up-counting, all circular buffer values can be updated through a DMA channel triggered by MC
trigger. When down-counting, all circular buffer values can be updated through a second DMA channel,
triggered by the OVF DMA request.
Figure 33-36. DMA Triggers in DSBOTH Operation Mode and Circular Buffer Enabled
Cycle
N-2
N
N-1
New Parameter Set
Old Parameter Set
"update"
COUNT
ZERO
CTRLB.DIR
DMA_CCx_req
DMA Channel i
Update Rising
DMA_OVF_req
DMA Channel j
Update Rising
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 607
SAM DA1
33.6.4.2 Interrupts
The TCC has the following interrupt sources:
•
•
•
•
•
•
•
•
Overflow/Underflow (OVF)
Retrigger (TRG)
Count (CNT) - refer also to description of EVCTRL.CNTSEL.
Capture Overflow Error (ERR)
Debug Fault State (DFS)
Recoverable Faults (FAULTn)
Non-recoverable Faults (FAULTx)
Compare Match or Capture Channels (MCx)
These interrupts are asynchronous wake-up sources. See Sleep Mode Entry and Exit Table in PM/Sleep
Mode Controller section for details.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status
and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be
individually enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set (INTENSET)
register, and disabled by writing a '1' to the corresponding bit in the Interrupt Enable Clear (INTENCLR)
register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is
enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or
the TCC is reset. See INTFLAG for details on how to clear interrupt flags. The TCC has one common
interrupt request line for all the interrupt sources. The user must read the INTFLAG register to determine
which interrupt condition is present.
Note: Interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested Vector
Interrupt Controller for details.
Related Links
Nested Vector Interrupt Controller
Sleep Mode Controller
IDLE Mode
STANDBY Mode
33.6.4.3 Events
The TCC can generate the following output events:
•
Overflow/Underflow (OVF)
•
Trigger (TRG)
•
Counter (CNT) For further details, refer to EVCTRL.CNTSEL description.
•
Compare Match or Capture on compare/capture channels: MCx
Writing a '1' ('0') to an Event Output bit in the Event Control Register (EVCTRL.xxEO) enables (disables)
the corresponding output event. Refer also to EVSYS – Event System.
The TCC can take the following actions on a channel input event (MCx):
•
Capture event
•
Generate a recoverable or non-recoverable fault
The TCC can take the following actions on counter Event 1 (TCCx EV1):
•
Counter re-trigger
•
Counter direction control
•
Stop the counter
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SAM DA1
•
•
•
Decrement the counter on event
Period and pulse width capture
Non-recoverable fault
The TCC can take the following actions on counter Event 0 (TCCx EV0):
•
Counter re-trigger
•
Count on event (increment or decrement, depending on counter direction)
•
Counter start - start counting on the event rising edge. Further events will not restart the counter;
the counter will keep on counting using prescaled GCLK_TCCx, until it reaches TOP or ZERO,
depending on the direction.
•
Counter increment on event. This will increment the counter, irrespective of the counter direction.
•
Count during active state of an asynchronous event (increment or decrement, depending on
counter direction). In this case, the counter will be incremented or decremented on each cycle of
the prescaled clock, as long as the event is active.
•
Non-recoverable fault
The counter Event Actions are available in the Event Control registers (EVCTRL.EVACT0 and
EVCTRL.EVACT1). For further details, refer to EVCTRL.
Writing a '1' ('0') to an Event Input bit in the Event Control register (EVCTRL.MCEIx or EVCTRL.TCEIx)
enables (disables) the corresponding action on input event.
Note: When several events are connected to the TCC, the enabled action will apply for each of the
incoming events. Refer to EVSYS – Event System for details on how to configure the event system.
Related Links
EVSYS – Event System
33.6.5
Sleep Mode Operation
The TCC can be configured to operate in any sleep mode. To be able to run in standby the RUNSTDBY
bit in the Control A register (CTRLA.RUNSTDBY) must be '1'. The MODULE can in any sleep mode wake
up the device using interrupts or perform actions through the Event System.
33.6.6
Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers
need to be synchronized when written or read.
The following bits are synchronized when written:
•
Software Reset and Enable bits in Control A register (CTRLA.SWRST and CTRLA.ENABLE)
The following registers are synchronized when written:
•
•
•
•
•
•
•
Control B Clear and Control B Set registers (CTRLBCLR and CTRLBSET)
Status register (STATUS)
Pattern and Pattern Buffer registers (PATT and PATTB)
Waveform register (WAVE)
Count Value register (COUNT)
Period Value and Period Buffer Value registers (PER and PERB)
Compare/Capture Channel x and Channel x Compare/Capture Buffer Value registers (CCx and
CCBx)
The following registers are synchronized when read:
© 2017 Microchip Technology Inc.
Datasheet Complete
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SAM DA1
•
•
•
•
•
•
Control B Clear and Control B Set registers (CTRLBCLR and CTRLBSET)
Count Value register (COUNT): synchronization is done on demand through READSYNC command
(CTRLBSET.CMD)
Pattern and Pattern Buffer registers (PATT and PATTB)
Waveform register (WAVE)
Period Value and Period Buffer Value registers (PER and PERB)
Compare/Capture Channel x and Channel x Compare/Capture Buffer Value registers (CCx and
CCBx)
Required write-synchronization is denoted by the "Write-Synchronized" property in the register
description.
Required read-synchronization is denoted by the "Read-Synchronized" property in the register
description.
Related Links
Register Synchronization
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 610
SAM DA1
33.7
Offset
Register Summary
Name
0x00
0x01
0x02
Bit Pos.
7:0
CTRLA
0x03
RESOLUTION[1:0]
15:8
ALOCK
ENABLE
PRESCYNC[1:0]
RUNSTDBY
SWRST
PRESCALER[2:0]
23:16
31:24
CPTEN3
CPTEN2
CPTEN1
CPTEN0
0x04
CTRLBCLR
7:0
CMD[2:0]
IDXCMD[1:0]
ONESHOT
LUPD
DIR
0x05
CTRLBSET
7:0
CMD[2:0]
IDXCMD[1:0]
ONESHOT
LUPD
DIR
CTRLB
ENABLE
SWRST
0x06
...
Reserved
0x07
0x08
0x09
0x0A
7:0
SYNCBUSY
0x0B
7:0
15:8
FCTRLA
31:24
0x10
7:0
FCTRLB
0x13
STATUS
CC3
CC2
CC1
CC0
CCB3
CCB2
CCB1
CCB0
PERB
WAVEB
PATTB
QUAL
KEEP
RESTART
BLANK[1:0]
CAPTURE[2:0]
BLANK[1:0]
QUAL
KEEP
CAPTURE[2:0]
7:0
WEXCTRL
CHSEL[1:0]
OTMX[1:0]
DTIENx
23:16
DTLS[7:0]
31:24
DTHS[7:0]
0x18
7:0
0x19
DRVCTRL
0x1B
HALT[1:0]
FILTERVAL[3:0]
0x17
0x1A
SRC[1:0]
BLANKVAL[7:0]
31:24
15:8
HALT[1:0]
FILTERVAL[3:0]
RESTART
15:8
0x15
SRC[1:0]
CHSEL[1:0]
BLANKVAL[7:0]
23:16
0x14
0x16
COUNT
23:16
0x0F
0x11
PATT
31:24
0x0D
0x12
WAVE
15:8
23:16
0x0C
0x0E
PER
NREx
NREx
NREx
NREx
NREx
DTIENx
DTIENx
DTIENx
NREx
NREx
NREx
15:8
NRVx
NRVx
NRVx
NRVx
NRVx
NRVx
NRVx
NRVx
23:16
INVENx
INVENx
INVENx
INVENx
INVENx
INVENx
INVENx
INVENx
31:24
FILTERVAL1[3:0]
FILTERVAL0[3:0]
0x1C
...
Reserved
0x1D
0x1E
DBGCTRL
0x1F
Reserved
0x20
0x21
7:0
FDDBD
7:0
CNTEO
TRGEO
OVFEO
MCEIx
MCEIx
MCEIx
0x23
31:24
MCEOx
MCEOx
MCEOx
MCEOx
0x24
7:0
ERR
CNT
TRG
OVF
0x25
15:8
MCx
MCx
MCx
MCx
ERR
CNT
TRG
OVF
0x26
INTENCLR
0x27
0x28
0x29
FAULTx
TCEIx
FAULTx
TCINVx
EVACT0[2:0]
MCEIx
EVCTRL
TCEIx
EVACT1[2:0]
23:16
0x22
15:8
CNTSEL[1:0]
DBGRUN
FAULTB
TCINVx
FAULTA
23:16
DFS
31:24
INTENSET
7:0
15:8
FAULTx
© 2017 Microchip Technology Inc.
FAULTx
FAULTB
FAULTA
Datasheet Complete
DFS
40001895A-page 611
SAM DA1
Offset
Name
Bit Pos.
0x2A
23:16
0x2B
31:24
0x2C
7:0
0x2D
0x2E
INTFLAG
0x2F
15:8
FAULTx
FAULTx
FAULTB
7:0
PERBV
WAVEBV
PATTBV
FAULTx
FAULTx
FAULTB
STATUS
31:24
0x34
7:0
COUNT
0x37
0x39
ERR
CNT
TRG
OVF
MCx
MCx
MCx
IDX
STOP
FAULT1IN
FAULT0IN
FAULTBIN
FAULTAIN
CCBVx
CCBVx
CCBVx
CCBVx
CMPx
CMPx
CMPx
CMPx
FAULTA
DFS
DFS
FAULTA
23:16
0x33
0x38
MCx
31:24
15:8
0x36
MCx
MCx
0x31
0x35
MCx
23:16
0x30
0x32
MCx
COUNT[7:0]
15:8
COUNT[15:8]
23:16
COUNT[23:16]
31:24
PATT
7:0
PGE0[7:0]
15:8
PGV0[7:0]
0x3A
...
Reserved
0x3B
0x3C
0x3D
0x3E
7:0
WAVE
0x3F
CIPEREN
RAMP[1:0]
WAVEGEN[2:0]
15:8
CICCEN3
CICCEN2
CICCEN1
23:16
POL3
POL2
POL1
POL0
31:24
SWAP3
SWAP2
SWAP1
SWAP0
0x40
7:0
0x41
15:8
PER[9:2]
23:16
PER[17:10]
0x42
PER
0x43
31:24
0x44
7:0
0x45
0x46
CC0
0x47
PER[1:0]
DITHER[5:0]
CC[1:0]
DITHER[5:0]
15:8
CC[9:2]
23:16
CC[17:10]
31:24
0x48
7:0
0x49
15:8
CC[9:2]
23:16
CC[17:10]
0x4A
CC1
0x4B
31:24
0x4C
7:0
0x4D
0x4E
CC2
0x4F
CC[1:0]
DITHER[5:0]
CC[1:0]
DITHER[5:0]
15:8
CC[9:2]
23:16
CC[17:10]
31:24
0x50
7:0
0x51
15:8
CC[9:2]
23:16
CC[17:10]
0x52
CICCEN0
CC3
0x53
CC[1:0]
DITHER[5:0]
31:24
0x54
...
Reserved
0x63
0x64
PATTB
7:0
© 2017 Microchip Technology Inc.
PGEB0[7:0]
Datasheet Complete
40001895A-page 612
SAM DA1
Offset
Name
0x65
Bit Pos.
15:8
PGVB0[7:0]
0x66
...
Reserved
0x67
0x68
7:0
0x69
15:8
CICCENB3
CICCENB2
CICCENB1
CICCENB0
23:16
POLB3
POLB2
POLB1
POLB0
SWAPB 3
SWAPB 2
SWAPB 1
SWAPB 0
0x6A
WAVEB
0x6B
31:24
0x6C
7:0
0x6D
0x6E
PERB
0x6F
CIPERENB
RAMPB[1:0]
WAVEGENB[2:0]
PERB[1:0]
DITHERB[5:0]
15:8
PERB[9:2]
23:16
PERB[17:10]
31:24
0x70
7:0
0x71
15:8
CCB[9:2]
23:16
CCB[17:10]
0x72
CCB0
0x73
31:24
0x74
7:0
0x75
0x76
CCB1
0x77
CCB[1:0]
DITHERB[5:0]
CCB[1:0]
DITHERB[5:0]
15:8
CCB[9:2]
23:16
CCB[17:10]
31:24
0x78
7:0
0x79
15:8
CCB[9:2]
23:16
CCB[17:10]
0x7A
CCB2
0x7B
31:24
0x7C
7:0
0x7D
0x7E
CCB3
0x7F
33.8
CCB[1:0]
DITHERB[5:0]
CCB[1:0]
DITHERB[5:0]
15:8
CCB[9:2]
23:16
CCB[17:10]
31:24
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,
the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the
"Read-Synchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled.
Enable-protection is denoted by the "Enable-Protected" property in each individual register description.
33.8.1
Control A
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Datasheet Complete
40001895A-page 613
SAM DA1
Name: CTRLA
Offset: 0x00 [ID-00002e48]
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected, Write-Synchronized (ENABLE, SWRST)
Bit
31
30
29
28
Access
Reset
Bit
27
26
25
24
CPTEN3
CPTEN2
CPTEN1
CPTEN0
R/W
R/W
R/W
R/W
0
0
0
0
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Access
Reset
Bit
ALOCK
Access
Reset
Bit
7
PRESCYNC[1:0]
RUNSTDBY
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
6
5
4
3
2
RESOLUTION[1:0]
Access
Reset
PRESCALER[2:0]
R/W
1
0
ENABLE
SWRST
R/W
R/W
R/W
R/W
0
0
0
0
Bits 24, 25, 26, 27 – CPTEN0, CPTEN1, CPTEN2, CPTEN3: Capture Channel x Enable
These bits are used to select the capture or compare operation on channel x.
Writing a '1' to CPTENx enables capture on channel x.
Writing a '0' to CPTENx disables capture on channel x.
Bit 14 – ALOCK: Auto Lock
This bit is not synchronized.
Value
0
1
Description
The Lock Update bit in the Control B register (CTRLB.LUPD) is not affected by overflow/
underflow, and re-trigger events
CTRLB.LUPD is set to '1' on each overflow/underflow or re-trigger event.
Bits 13:12 – PRESCYNC[1:0]: Prescaler and Counter Synchronization
These bits select if on re-trigger event, the Counter is cleared or reloaded on either the next GCLK_TCCx
clock, or on the next prescaled GCLK_TCCx clock. It is also possible to reset the prescaler on re-trigger
event.
These bits are not synchronized.
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Datasheet Complete
40001895A-page 614
SAM DA1
Value
Name
Description
Counter Reloaded
Prescaler
0x0
GCLK
Reload or reset Counter on next
GCLK
-
0x1
PRESC
Reload or reset Counter on next
prescaler clock
-
0x2
RESYNC
Reload or reset Counter on next
GCLK
Reset prescaler counter
0x3
Reserved
Bit 11 – RUNSTDBY: Run in Standby
This bit is used to keep the TCC running in standby mode.
This bit is not synchronized.
Value
0
1
Description
The TCC is halted in standby.
The TCC continues to run in standby.
Bits 10:8 – PRESCALER[2:0]: Prescaler
These bits select the Counter prescaler factor.
These bits are not synchronized.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Name
DIV1
DIV2
DIV4
DIV8
DIV16
DIV64
DIV256
DIV1024
Description
Prescaler: GCLK_TCC
Prescaler: GCLK_TCC/2
Prescaler: GCLK_TCC/4
Prescaler: GCLK_TCC/8
Prescaler: GCLK_TCC/16
Prescaler: GCLK_TCC/64
Prescaler: GCLK_TCC/256
Prescaler: GCLK_TCC/1024
Bits 6:5 – RESOLUTION[1:0]: Dithering Resolution
These bits increase the TCC resolution by enabling the dithering options.
These bits are not synchronized.
Table 33-7. Dithering
Value
Name
Description
0x0
NONE
The dithering is disabled.
0x1
DITH4
Dithering is done every 16 PWM frames.
PER[3:0] and CCx[3:0] contain dithering pattern
selection.
0x2
© 2017 Microchip Technology Inc.
DITH5
Dithering is done every 32 PWM frames.
Datasheet Complete
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SAM DA1
Value
Name
Description
PER[4:0] and CCx[4:0] contain dithering pattern
selection.
0x3
DITH6
Dithering is done every 64 PWM frames.
PER[5:0] and CCx[5:0] contain dithering pattern
selection.
Bit 1 – ENABLE: Enable
Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/
disabled. The value written to CTRLA.ENABLE will read back immediately and the ENABLE bit in the
SYNCBUSY register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the
operation is complete.
Value
0
1
Description
The peripheral is disabled.
The peripheral is enabled.
Bit 0 – SWRST: Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the TCC (except DBGCTRL) to their initial state, and the TCC
will be disabled.
Writing a '1' to CTRLA.SWRST will always take precedence; all other writes in the same write-operation
will be discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete.
CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.
Value
0
1
33.8.2
Description
There is no reset operation ongoing.
The reset operation is ongoing.
Control B Clear
This register allows the user to change this register without doing a read-modify-write operation. Changes
in this register will also be reflected in the Control B Set (CTRLBSET) register.
Name: CTRLBCLR
Offset: 0x04 [ID-00002e48]
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized
© 2017 Microchip Technology Inc.
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40001895A-page 616
SAM DA1
Bit
7
6
5
4
CMD[2:0]
Access
Reset
3
IDXCMD[1:0]
2
1
0
ONESHOT
LUPD
DIR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 7:5 – CMD[2:0]: TCC Command
These bits can be used for software control of re-triggering and stop commands of the TCC. When a
command has been executed, the CMD bit field will read back zero. The commands are executed on the
next prescaled GCLK_TCC clock cycle.
Writing zero to this bit group has no effect.
Writing a '1' to any of these bits will clear the pending command.
Value
0x0
0x1
0x2
0x3
0x4
Name
NONE
RETRIGGER
STOP
UPDATE
READSYNC
Description
No action
Clear start, restart or retrigger
Force stop
Force update of double buffered registers
Force COUNT read synchronization
Bits 4:3 – IDXCMD[1:0]: Ramp Index Command
These bits can be used to force cycle A and cycle B changes in RAMP2 and RAMP2A operation. On
timer/counter update condition, the command is executed, the IDX flag in STATUS register is updated
and the IDXCMD command is cleared.
Writing zero to these bits has no effect.
Writing a '1' to any of these bits will clear the pending command.
Value
0x0
0x1
0x2
0x3
Name
DISABLE
SET
CLEAR
HOLD
Description
DISABLE Command disabled: IDX toggles between cycles A and B
Set IDX: cycle B will be forced in the next cycle
Clear IDX: cycle A will be forced in next cycle
Hold IDX: the next cycle will be the same as the current cycle.
Bit 2 – ONESHOT: One-Shot
This bit controls one-shot operation of the TCC. When one-shot operation is enabled, the TCC will stop
counting on the next overflow/underflow condition or on a stop command.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will disable the one-shot operation.
Value
0
1
Description
The TCC will update the counter value on overflow/underflow condition and continue
operation.
The TCC will stop counting on the next underflow/overflow condition.
Bit 1 – LUPD: Lock Update
This bit controls the update operation of the TCC buffered registers.
When CTRLB.LUPD is set, no any update of the registers with value of its buffered register is performed
on hardware UPDATE condition. Locking the update ensures that all buffer registers are valid before an
© 2017 Microchip Technology Inc.
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40001895A-page 617
SAM DA1
hardware update is performed. After all the buffer registers are loaded correctly, the buffered registers
can be unlocked.
This bit has no effect when input capture operation is enabled.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will enable updating.
Value
0
1
Description
The CCBx, PERB, PGVB, PGOB, and SWAPBx buffer registers values are copied into the
corresponding CCx, PER, PGV, PGO and SWAPx registers on hardware update condition.
The CCBx, PERB, PGVB, PGOB, and SWAPBx buffer registers values are not copied into
the corresponding CCx, PER, PGV, PGO and SWAPx registers on hardware update
condition.
Bit 0 – DIR: Counter Direction
This bit is used to change the direction of the counter.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will clear the bit and make the counter count up.
Value
0
1
33.8.3
Description
The timer/counter is counting up (incrementing).
The timer/counter is counting down (decrementing).
Control B Set
This register allows the user to change this register without doing a read-modify-write operation. Changes
in this register will also be reflected in the Control B Set (CTRLBCLR) register.
Name: CTRLBSET
Offset: 0x05 [ID-00002e48]
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized
Bit
7
6
5
4
CMD[2:0]
Access
Reset
3
IDXCMD[1:0]
2
1
0
ONESHOT
LUPD
DIR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 7:5 – CMD[2:0]: TCC Command
These bits can be used for software control of re-triggering and stop commands of the TCC. When a
command has been executed, the CMD bit field will be read back as zero. The commands are executed
on the next prescaled GCLK_TCC clock cycle.
Writing zero to this bit group has no effect
Writing a valid value to this bit group will set the associated command.
Value
0x0
0x1
0x2
Name
NONE
RETRIGGER
STOP
© 2017 Microchip Technology Inc.
Description
No action
Force start, restart or retrigger
Force stop
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40001895A-page 618
SAM DA1
Value
0x3
0x4
Name
UPDATE
READSYNC
Description
Force update of double buffered registers
Force a read synchronization of COUNT
Bits 4:3 – IDXCMD[1:0]: Ramp Index Command
These bits can be used to force cycle A and cycle B changes in RAMP2 and RAMP2A operation. On
timer/counter update condition, the command is executed, the IDX flag in STATUS register is updated
and the IDXCMD command is cleared.
Writing a zero to these bits has no effect.
Writing a valid value to these bits will set a command.
Value
0x0
0x1
0x2
0x3
Name
DISABLE
SET
CLEAR
HOLD
Description
Command disabled: IDX toggles between cycles A and B
Set IDX: cycle B will be forced in the next cycle
Clear IDX: cycle A will be forced in next cycle
Hold IDX: the next cycle will be the same as the current cycle.
Bit 2 – ONESHOT: One-Shot
This bit controls one-shot operation of the TCC. When in one-shot operation, the TCC will stop counting
on the next overflow/underflow condition or a stop command.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will enable the one-shot operation.
Value
0
1
Description
The TCC will count continuously.
The TCC will stop counting on the next underflow/overflow condition.
Bit 1 – LUPD: Lock Update
This bit controls the update operation of the TCC buffered registers.
When CTRLB.LUPD is set, no any update of the registers with value of its buffered register is performed
on hardware UPDATE condition. Locking the update ensures that all buffer registers are valid before an
hardware update is performed. After all the buffer registers are loaded correctly, the buffered registers
can be unlocked.
This bit has no effect when input capture operation is enabled.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will lock updating.
Value
0
1
Description
The CCBx, PERB, PGVB, PGOB, and SWAPBx buffer registers values are copied into the
corresponding CCx, PER, PGV, PGO and SWAPx registers on hardware update condition.
The CCBx, PERB, PGVB, PGOB, and SWAPBx buffer registers values are not copied into
CCx, PER, PGV, PGO and SWAPx registers on hardware update condition.
Bit 0 – DIR: Counter Direction
This bit is used to change the direction of the counter.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will clear the bit and make the counter count up.
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40001895A-page 619
SAM DA1
Value
0
1
33.8.4
Description
The timer/counter is counting up (incrementing).
The timer/counter is counting down (decrementing).
Synchronization Busy
Name: SYNCBUSY
Offset: 0x08 [ID-00002e48]
Reset: 0x00000000
Property:
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
22
21
20
19
18
17
16
CCB3
CCB2
CCB1
CCB0
PERB
WAVEB
PATTB
Access
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
14
13
12
Bit
23
11
10
9
8
CC3
CC2
CC1
CC0
Access
R
R
R
R
Reset
0
0
0
0
Bit
15
7
6
5
4
3
2
1
0
PER
WAVE
PATT
COUNT
STATUS
CTRLB
ENABLE
SWRST
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bits 19, 20, 21, 22 – CCB: Compare/Capture Buffer Channel x Synchronization Busy
This bit is cleared when the synchronization of Compare/Capture Buffer Channel x register between the
clock domains is complete.
This bit is set when the synchronization of Compare/Capture Buffer Channel x register between clock
domains is started.
CCBx bit is available only for existing Compare/Capture Channels. For details on CC channels number,
refer to each TCC feature list.
Bit 18 – PERB: PER Buffer Synchronization Busy
This bit is cleared when the synchronization of PERB register between the clock domains is complete.
This bit is set when the synchronization of PERB register between clock domains is started.
Bit 17 – WAVEB: WAVE Buffer Synchronization Busy
This bit is cleared when the synchronization of WAVEB register between the clock domains is complete.
This bit is set when the synchronization of WAVEB register between clock domains is started.
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SAM DA1
Bit 16 – PATTB: PATT Buffer Synchronization Busy
This bit is cleared when the synchronization of PATTB register between the clock domains is complete.
This bit is set when the synchronization of PATTB register between clock domains is started.
Bits 8, 9, 10, 11 – CC: Compare/Capture Channel x Synchronization Busy
This bit is cleared when the synchronization of Compare/Capture Channel x register between the clock
domains is complete.
This bit is set when the synchronization of Compare/Capture Channel x register between clock domains
is started.
CCx bit is available only for existing Compare/Capture Channels. For details on CC channels number,
refer to each TCC feature list.
This bit is set when the synchronization of CCx register between clock domains is started.
Bit 7 – PER: PER Synchronization Busy
This bit is cleared when the synchronization of PER register between the clock domains is complete.
This bit is set when the synchronization of PER register between clock domains is started.
Bit 6 – WAVE: WAVE Synchronization Busy
This bit is cleared when the synchronization of WAVE register between the clock domains is complete.
This bit is set when the synchronization of WAVE register between clock domains is started.
Bit 5 – PATT: PATT Synchronization Busy
This bit is cleared when the synchronization of PATTERN register between the clock domains is
complete.
This bit is set when the synchronization of PATTERN register between clock domains is started.
Bit 4 – COUNT: COUNT Synchronization Busy
This bit is cleared when the synchronization of COUNT register between the clock domains is complete.
This bit is set when the synchronization of COUNT register between clock domains is started.
Bit 3 – STATUS: STATUS Synchronization Busy
This bit is cleared when the synchronization of STATUS register between the clock domains is complete.
This bit is set when the synchronization of STATUS register between clock domains is started.
Bit 2 – CTRLB: CTRLB Synchronization Busy
This bit is cleared when the synchronization of CTRLB register between the clock domains is complete.
This bit is set when the synchronization of CTRLB register between clock domains is started.
Bit 1 – ENABLE: ENABLE Synchronization Busy
This bit is cleared when the synchronization of ENABLE bit between the clock domains is complete.
This bit is set when the synchronization of ENABLE bit between clock domains is started.
Bit 0 – SWRST: SWRST Synchronization Busy
This bit is cleared when the synchronization of SWRST bit between the clock domains is complete.
This bit is set when the synchronization of SWRST bit between clock domains is started.
© 2017 Microchip Technology Inc.
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40001895A-page 621
SAM DA1
33.8.5
Fault Control A and B
Name: FCTRLA, FCTRLB
Offset: 0x0C + n*0x04 [n=0..1]
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
Bit
31
30
29
28
27
26
25
24
FILTERVAL[3:0]
Access
Reset
Bit
23
22
21
20
R/W
R/W
R/W
R/W
0
0
0
0
19
18
17
16
BLANKVAL[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
CAPTURE[2:0]
Access
Reset
Bit
7
8
HALT[1:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
6
5
4
3
2
1
0
RESTART
Access
CHSEL[1:0]
QUAL
KEEP
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Reset
BLANK[1:0]
SRC[1:0]
Bits 27:24 – FILTERVAL[3:0]: Recoverable Fault n Filter Value
These bits define the filter value applied on MCEx (x=0,1) event input line. The value must be set to zero
when MCEx event is used as synchronous event.
Bits 23:16 – BLANKVAL[7:0]: Recoverable Fault n Blanking Value
These bits determine the duration of the blanking of the fault input source. Activation and edge selection
of the blank filtering are done by the BLANK bits (FCTRLn.BLANK).
When enabled, the fault input source is internally disabled for BLANKVAL* prescaled GCLK_TCC periods
after the detection of the waveform edge.
Bits 14:12 – CAPTURE[2:0]: Recoverable Fault n Capture Action
These bits select the capture and Fault n interrupt/event conditions.
Table 33-8. Fault n Capture Action
Value
0x0
0x1
Name
Description
DISABLE Capture on valid recoverable Fault n is disabled
CAPT
On rising edge of a valid recoverable Fault n, capture counter value on channel
selected by CHSEL[1:0].
INTFLAG.FAULTn flag rises on each new captured value.
© 2017 Microchip Technology Inc.
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40001895A-page 622
SAM DA1
Value
0x2
Name
Description
CAPTMIN On rising edge of a valid recoverable Fault n, capture counter value on channel
selected by CHSEL[1:0], if COUNT value is lower than the last stored capture value
(CC).
INTFLAG.FAULTn flag rises on each local minimum detection.
0x3
CAPTMAX On rising edge of a valid recoverable Fault n, capture counter value on channel
selected by CHSEL[1:0], if COUNT value is higher than the last stored capture value
(CC).
INTFLAG.FAULTn flag rises on each local maximun detection.
0x4
LOCMIN
On rising edge of a valid recoverable Fault n, capture counter value on channel
selected by CHSEL[1:0].
INTFLAG.FAULTn flag rises on each local minimum value detection.
0x5
LOCMAX On rising edge of a valid recoverable Fault n, capture counter value on channel
selected by CHSEL[1:0].
INTFLAG.FAULTn flag rises on each local maximun detection.
0x6
DERIV0
On rising edge of a valid recoverable Fault n, capture counter value on channel
selected by CHSEL[1:0].
INTFLAG.FAULTn flag rises on each local maximun or minimum detection.
Bits 11:10 – CHSEL[1:0]: Recoverable Fault n Capture Channel
These bits select the channel for capture operation triggered by recoverable Fault n.
Value
0x0
0x1
0x2
0x3
Name
CC0
CC1
CC2
CC3
Description
Capture value stored into CC0
Capture value stored into CC1
Capture value stored into CC2
Capture value stored into CC3
Bits 9:8 – HALT[1:0]: Recoverable Fault n Halt Operation
These bits select the halt action for recoverable Fault n.
Value
0x0
0x1
0x2
0x3
Name
DISABLE
HW
SW
NR
Description
Halt action disabled
Hardware halt action
Software halt action
Non-recoverable fault
Bit 7 – RESTART: Recoverable Fault n Restart
Setting this bit enables restart action for Fault n.
Value
0
1
Description
Fault n restart action is disabled.
Fault n restart action is enabled.
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40001895A-page 623
SAM DA1
Bits 6:5 – BLANK[1:0]: Recoverable Fault n Blanking Operation
These bits, select the blanking start point for recoverable Fault n.
Value
0x0
0x1
0x2
0x3
Name
START
RISE
FALL
BOTH
Description
Blanking applied from start of the Ramp period
Blanking applied from rising edge of the waveform output
Blanking applied from falling edge of the waveform output
Blanking applied from each toggle of the waveform output
Bit 4 – QUAL: Recoverable Fault n Qualification
Setting this bit enables the recoverable Fault n input qualification.
Value
0
1
Description
The recoverable Fault n input is not disabled on CMPx value condition.
The recoverable Fault n input is disabled when output signal is at inactive level (CMPx == 0).
Bit 3 – KEEP: Recoverable Fault n Keep
Setting this bit enables the Fault n keep action.
Value
0
1
Description
The Fault n state is released as soon as the recoverable Fault n is released.
The Fault n state is released at the end of TCC cycle.
Bits 1:0 – SRC[1:0]: Recoverable Fault n Source
These bits select the TCC event input for recoverable Fault n.
Event system channel connected to MCEx event input, must be configured to route the event
asynchronously, when used as a recoverable Fault n input.
Value
0x0
0x1
0x2
0x3
33.8.6
Name
DISABLE
ENABLE
INVERT
ALTFAULT
Description
Fault input disabled
MCEx (x=0,1) event input
Inverted MCEx (x=0,1) event input
Alternate fault (A or B) state at the end of the previous period.
Waveform Extension Control
Name: WEXCTRL
Offset: 0x14 [ID-00002e48]
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
© 2017 Microchip Technology Inc.
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40001895A-page 624
SAM DA1
Bit
31
30
29
28
27
26
25
24
DTHS[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DTLS[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
Access
Reset
Bit
7
6
5
4
11
10
9
8
DTIENx
DTIENx
DTIENx
DTIENx
R/W
R/W
R/W
R/W
0
0
0
0
3
2
1
0
OTMX[1:0]
Access
Reset
R/W
R/W
0
0
Bits 31:24 – DTHS[7:0]: Dead-Time High Side Outputs Value
This register holds the number of GCLK_TCC clock cycles for the dead-time high side.
Bits 23:16 – DTLS[7:0]: Dead-time Low Side Outputs Value
This register holds the number of GCLK_TCC clock cycles for the dead-time low side.
Bits 11,10,9,8 – DTIENx : Dead-time Insertion Generator x Enable
Setting any of these bits enables the dead-time insertion generator for the corresponding output matrix.
This will override the output matrix [x] and [x+WO_NUM/2], with the low side and high side waveform
respectively.
Value
0
1
Description
No dead-time insertion override.
Dead time insertion override on signal outputs[x] and [x+WO_NUM/2], from matrix outputs[x]
signal.
Bits 1:0 – OTMX[1:0]: Output Matrix
These bits define the matrix routing of the TCC waveform generation outputs to the port pins, according
to Table 33-4.
33.8.7
Driver Control
Name: DRVCTRL
Offset: 0x18 [ID-00002e48]
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
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40001895A-page 625
SAM DA1
Bit
31
30
29
28
27
FILTERVAL1[3:0]
Access
Reset
Bit
Access
Reset
Bit
Access
26
25
24
FILTERVAL0[3:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
INVENx
INVENx
INVENx
INVENx
INVENx
INVENx
INVENx
INVENx
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
NRVx
NRVx
NRVx
NRVx
NRVx
NRVx
NRVx
NRVx
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
NREx
NREx
NREx
NREx
NREx
NREx
NREx
NREx
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Access
Reset
Bits 31:28 – FILTERVAL1[3:0]: Non-Recoverable Fault Input 1 Filter Value
These bits define the filter value applied on TCE1 event input line. When the TCE1 event input line is
configured as a synchronous event, this value must be 0x0.
Bits 27:24 – FILTERVAL0[3:0]: Non-Recoverable Fault Input 0 Filter Value
These bits define the filter value applied on TCE0 event input line. When the TCE0 event input line is
configured as a synchronous event, this value must be 0x0.
Bits 23,22,21,20,19,18,17,16 – INVENx: Waveform Output x Inversion
These bits are used to select inversion on the output of channel x.
Writing a '1' to INVENx inverts output from WO[x].
Writing a '0' to INVENx disables inversion of output from WO[x].
Bits 15,14,13,12,11,10,9,8 – NRVx: NRVx Non-Recoverable State x Output Value
These bits define the value of the enabled override outputs, under non-recoverable fault condition.
Bits 7,6,5,4,3,2,1,0 – NREx: Non-Recoverable State x Output Enable
These bits enable the override of individual outputs by NRVx value, under non-recoverable fault
condition.
Value
0
1
33.8.8
Description
Non-recoverable fault tri-state the output.
Non-recoverable faults set the output to NRVx level.
Debug control
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SAM DA1
Name: DBGCTRL
Offset: 0x1E [ID-00002e48]
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
Access
Reset
2
1
0
FDDBD
DBGRUN
R/W
R/W
0
0
Bit 2 – FDDBD: Fault Detection on Debug Break Detection
This bit is not affected by software reset and should not be changed by software while the TCC is
enabled.
By default this bit is zero, and the on-chip debug (OCD) fault protection is disabled. When this bit is
written to ‘1’, OCD break request from the OCD system will trigger non-recoverable fault. When this bit is
set, OCD fault protection is enabled and OCD break request from the OCD system will trigger a nonrecoverable fault.
Value
0
1
Description
No faults are generated when TCC is halted in debug mode.
A non recoverable fault is generated and FAULTD flag is set when TCC is halted in debug
mode.
Bit 0 – DBGRUN: Debug Running State
This bit is not affected by software reset and should not be changed by software while the TCC is
enabled.
Value
0
1
33.8.9
Description
The TCC is halted when the device is halted in debug mode.
The TCC continues normal operation when the device is halted in debug mode.
Event Control
Name: EVCTRL
Offset: 0x20 [ID-00002e48]
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected
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40001895A-page 627
SAM DA1
Bit
31
30
29
28
Access
Reset
Bit
23
22
21
20
Access
Reset
Bit
Access
27
26
25
24
MCEOx
MCEOx
MCEOx
MCEOx
R/W
R/W
R/W
R/W
0
0
0
0
19
18
17
16
MCEIx
MCEIx
MCEIx
MCEIx
R/W
R/W
R/W
R/W
0
0
0
0
15
14
13
12
10
9
8
TCEIx
TCEIx
TCINVx
TCINVx
11
CNTEO
TRGEO
OVFEO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
CNTSEL[1:0]
Access
Reset
EVACT1[2:0]
EVACT0[2:0]
Bits 27,26,25,24 – MCEOx: Match or Capture Channel x Event Output Enable
These bits control if the Match/capture event on channel x is enabled and will be generated for every
match or capture.
Value
0
1
Description
Match/capture x event is disabled and will not be generated.
Match/capture x event is enabled and will be generated for every compare/capture on
channel x.
Bits 19,18,17,16 – MCEIx: Match or Capture Channel x Event Input Enable
These bits indicate if the Match/capture x incoming event is enabled
These bits are used to enable match or capture input events to the CCx channel of TCC.
Value
0
1
Description
Incoming events are disabled.
Incoming events are enabled.
Bits 15,14 – TCEIx: Timer/Counter Event Input x Enable
This bit is used to enable input event x to the TCC.
Value
0
1
Description
Incoming event x is disabled.
Incoming event x is enabled.
Bits 13,12 – TCINVx: Timer/Counter Event x Invert Enable
This bit inverts the event x input.
Value
0
1
Description
Input event source x is not inverted.
Input event source x is inverted.
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SAM DA1
Bit 10 – CNTEO: Timer/Counter Event Output Enable
This bit is used to enable the counter cycle event. When enabled, an event will be generated on begin or
end of counter cycle depending of CNTSEL[1:0] settings.
Value
0
1
Description
Counter cycle output event is disabled and will not be generated.
Counter cycle output event is enabled and will be generated depend of CNTSEL[1:0] value.
Bit 9 – TRGEO: Retrigger Event Output Enable
This bit is used to enable the counter retrigger event. When enabled, an event will be generated when the
counter retriggers operation.
Value
0
1
Description
Counter retrigger event is disabled and will not be generated.
Counter retrigger event is enabled and will be generated for every counter retrigger.
Bit 8 – OVFEO: Overflow/Underflow Event Output Enable
This bit is used to enable the overflow/underflow event. When enabled an event will be generated when
the counter reaches the TOP or the ZERO value.
Value
0
1
Description
Overflow/underflow counter event is disabled and will not be generated.
Overflow/underflow counter event is enabled and will be generated for every counter
overflow/underflow.
Bits 7:6 – CNTSEL[1:0]: Timer/Counter Interrupt and Event Output Selection
These bits define on which part of the counter cycle the counter event output is generated.
Value
0x0
0x1
0x2
0x3
Name
BEGIN
END
BETWEEN
BOUNDARY
Description
An interrupt/event is generated at begin of each counter cycle
An interrupt/event is generated at end of each counter cycle
An interrupt/event is generated between each counter cycle.
An interrupt/event is generated at begin of first counter cycle, and end of last
counter cycle.
Bits 5:3 – EVACT1[2:0]: Timer/Counter Event Input 1 Action
These bits define the action the TCC will perform on TCE1 event input.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Name
OFF
RETRIGGER
DIR (asynch)
STOP
DEC
PPW
PWP
FAULT
Description
Event action disabled.
Start restart or re-trigger TC on event
Direction control
Stop TC on event
Decrement TC on event
Period captured into CC0 Pulse Width on CC1
Period captured into CC1 Pulse Width on CC0
Non-recoverable Fault
Bits 2:0 – EVACT0[2:0]: Timer/Counter Event Input 0 Action
These bits define the action the TCC will perform on TCE0 event input 0.
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SAM DA1
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Name
OFF
RETRIGGER
COUNTEV
START
INC
COUNT (async)
FAULT
Description
Event action disabled.
Start restart or re-trigger TC on event
Count on event.
Start TC on event
Increment TC on EVENT
Count on active state of asynchronous event
Reserved
Non-recoverable Fault
33.8.10 Interrupt Enable Clear
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Name: INTENCLR
Offset: 0x24 [ID-00002e48]
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
MCx
MCx
MCx
MCx
R/W
R/W
R/W
R/W
0
0
0
0
10
9
8
Access
Reset
Bit
Access
Reset
Bit
15
14
13
12
11
FAULTx
FAULTx
FAULTB
FAULTA
DFS
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
Bit
7
6
5
4
Access
Access
Reset
3
2
1
0
ERR
CNT
TRG
OVF
R/W
R/W
R/W
R/W
0
0
0
0
Bits 19,18,17,16 – MCx: Match or Capture Channel x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the corresponding Match or Capture Channel x Interrupt Disable/Enable
bit, which disables the Match or Capture Channel x interrupt.
Value
0
1
Description
The Match or Capture Channel x interrupt is disabled.
The Match or Capture Channel x interrupt is enabled.
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SAM DA1
Bits 15,14 – FAULTx: Non-Recoverable Fault x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Non-Recoverable Fault x Interrupt Disable/Enable bit, which disables
the Non-Recoverable Fault x interrupt.
Value
0
1
Description
The Non-Recoverable Fault x interrupt is disabled.
The Non-Recoverable Fault x interrupt is enabled.
Bit 13 – FAULTB: Recoverable Fault B Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Recoverable Fault B Interrupt Disable/Enable bit, which disables the
Recoverable Fault B interrupt.
Value
0
1
Description
The Recoverable Fault B interrupt is disabled.
The Recoverable Fault B interrupt is enabled.
Bit 12 – FAULTA: Recoverable Fault A Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Recoverable Fault A Interrupt Disable/Enable bit, which disables the
Recoverable Fault A interrupt.
Value
0
1
Description
The Recoverable Fault A interrupt is disabled.
The Recoverable Fault A interrupt is enabled.
Bit 11 – DFS: Non-Recoverable Debug Fault Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Debug Fault State Interrupt Disable/Enable bit, which disables the
Debug Fault State interrupt.
Value
0
1
Description
The Debug Fault State interrupt is disabled.
The Debug Fault State interrupt is enabled.
Bit 3 – ERR: Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Error Interrupt Disable/Enable bit, which disables the Compare
interrupt.
Value
0
1
Description
The Error interrupt is disabled.
The Error interrupt is enabled.
Bit 2 – CNT: Counter Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Counter Interrupt Disable/Enable bit, which disables the Counter
interrupt.
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SAM DA1
Value
0
1
Description
The Counter interrupt is disabled.
The Counter interrupt is enabled.
Bit 1 – TRG: Retrigger Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Retrigger Interrupt Disable/Enable bit, which disables the Retrigger
interrupt.
Value
0
1
Description
The Retrigger interrupt is disabled.
The Retrigger interrupt is enabled.
Bit 0 – OVF: Overflow Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Overflow Interrupt Disable/Enable bit, which disables the Overflow
interrupt request.
Value
0
1
Description
The Overflow interrupt is disabled.
The Overflow interrupt is enabled.
33.8.11 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name: INTENSET
Offset: 0x28 [ID-00002e48]
Reset: 0x00000000
Property: PAC Write-Protection
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SAM DA1
Bit
31
30
29
28
23
22
21
20
27
26
25
24
Access
Reset
Bit
Access
19
18
17
16
MCx
MCx
MCx
MCx
R/W
R/W
R/W
R/W
0
0
0
0
10
9
8
Reset
Bit
Access
15
14
13
12
11
FAULTx
FAULTx
FAULTB
FAULTA
DFS
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ERR
CNT
TRG
OVF
R/W
R/W
R/W
R/W
0
0
0
0
Access
Reset
Bits 19,18,17,16 – MCx: Match or Capture Channel x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the corresponding Match or Capture Channel x Interrupt Disable/Enable bit,
which enables the Match or Capture Channel x interrupt.
Value
0
1
Description
The Match or Capture Channel x interrupt is disabled.
The Match or Capture Channel x interrupt is enabled.
Bits 15,14 – FAULTx: Non-Recoverable Fault x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Non-Recoverable Fault x Interrupt Disable/Enable bit, which enables the
Non-Recoverable Fault x interrupt.
Value
0
1
Description
The Non-Recoverable Fault x interrupt is disabled.
The Non-Recoverable Fault x interrupt is enabled.
Bit 13 – FAULTB: Recoverable Fault B Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Recoverable Fault B Interrupt Disable/Enable bit, which enables the
Recoverable Fault B interrupt.
Value
0
1
Description
The Recoverable Fault B interrupt is disabled.
The Recoverable Fault B interrupt is enabled.
Bit 12 – FAULTA: Recoverable Fault A Interrupt Enable
Writing a '0' to this bit has no effect.
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SAM DA1
Writing a '1' to this bit will set the Recoverable Fault A Interrupt Disable/Enable bit, which enables the
Recoverable Fault A interrupt.
Value
0
1
Description
The Recoverable Fault A interrupt is disabled.
The Recoverable Fault A interrupt is enabled.
Bit 11 – DFS: Non-Recoverable Debug Fault Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Debug Fault State Interrupt Disable/Enable bit, which enables the
Debug Fault State interrupt.
Value
0
1
Description
The Debug Fault State interrupt is disabled.
The Debug Fault State interrupt is enabled.
Bit 3 – ERR: Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Error Interrupt Disable/Enable bit, which enables the Compare interrupt.
Value
0
1
Description
The Error interrupt is disabled.
The Error interrupt is enabled.
Bit 2 – CNT: Counter Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Retrigger Interrupt Disable/Enable bit, which enables the Counter
interrupt.
Value
0
1
Description
The Counter interrupt is disabled.
The Counter interrupt is enabled.
Bit 1 – TRG: Retrigger Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Retrigger Interrupt Disable/Enable bit, which enables the Retrigger
interrupt.
Value
0
1
Description
The Retrigger interrupt is disabled.
The Retrigger interrupt is enabled.
Bit 0 – OVF: Overflow Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Overflow Interrupt Disable/Enable bit, which enables the Overflow
interrupt request.
Value
0
1
Description
The Overflow interrupt is disabled.
The Overflow interrupt is enabled.
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SAM DA1
33.8.12 Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x2C [ID-00002e48]
Reset: 0x00000000
Property:
Bit
31
30
29
28
23
22
21
20
27
26
25
24
Access
Reset
Bit
Access
Reset
Bit
Access
19
18
17
16
MCx
MCx
MCx
MCx
R/W
R/W
R/W
R/W
0
0
0
0
10
9
8
15
14
13
12
11
FAULTx
FAULTx
FAULTB
FAULTA
DFS
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ERR
CNT
TRG
OVF
R/W
R/W
R/W
R/W
0
0
0
0
Access
Reset
Bits 19,18,17,16 – MCx: Match or Capture Channel x Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a match with the compare condition or once
CCx register contain a valid capture value.
Writing a '0' to one of these bits has no effect.
Writing a '1' to one of these bits will clear the corresponding Match or Capture Channel x interrupt flag
In Capture operation, this flag is automatically cleared when CCx register is read.
Bits 15,14 – FAULTx: Non-Recoverable Fault x Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a Non-Recoverable Fault x occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Non-Recoverable Fault x interrupt flag.
Bit 13 – FAULTB: Recoverable Fault B Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a Recoverable Fault B occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Recoverable Fault B interrupt flag.
Bit 12 – FAULTA: Recoverable Fault A Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a Recoverable Fault B occurs.
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SAM DA1
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Recoverable Fault B interrupt flag.
Bit 11 – DFS: Non-Recoverable Debug Fault State Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after an Debug Fault State occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Debug Fault State interrupt flag.
Bit 3 – ERR: Error Interrupt Flag
This flag is set if a new capture occurs on a channel when the corresponding Match or Capture Channel x
interrupt flag is one. In which case there is nowhere to store the new capture.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the error interrupt flag.
Bit 2 – CNT: Counter Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a counter event occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the CNT interrupt flag.
Bit 1 – TRG: Retrigger Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a counter retrigger occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the re-trigger interrupt flag.
Bit 0 – OVF: Overflow Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after an overflow condition occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Overflow interrupt flag.
33.8.13 Status
Name: STATUS
Offset: 0x30 [ID-00002e48]
Reset: 0x00000001
Property:
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SAM DA1
Bit
27
26
25
24
CMPx
CMPx
CMPx
CMPx
Access
R
R
R
R
Reset
0
0
0
0
Bit
31
23
30
22
29
21
28
20
Access
Reset
Bit
Access
19
18
17
16
CCBVx
CCBVx
CCBVx
CCBVx
R/W
R/W
R/W
R/W
0
0
0
0
15
14
13
12
11
10
9
8
FAULTx
FAULTx
FAULTB
FAULTA
FAULT1IN
FAULT0IN
FAULTBIN
FAULTAIN
R/W
R/W
R/W
R/W
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PERBV
WAVEBV
PATTBV
DFS
IDX
STOP
R/W
R/W
R/W
R/W
R
R
0
0
0
0
0
1
Access
Reset
Bits 27,26,25,24 – CMPx: Channel x Compare Value
This bit reflects the channel x output compare value.
Value
0
1
Description
Channel compare output value is 0.
Channel compare output value is 1.
Bits 19,18,17,16 – CCBVx: Channel x Compare or Capture Buffer Valid
For a compare channel, this bit is set when a new value is written to the corresponding CCBx register.
The bit is cleared either by writing a '1' to the corresponding location when CTRLB.LUPD is set, or
automatically on an UPDATE condition.
For a capture channel, the bit is set when a valid capture value is stored in the CCBx register. The bit is
automatically cleared when the CCx register is read.
Bits 15,14 – FAULTx: Non-recoverable Fault x State
This bit is set by hardware as soon as non-recoverable Fault x condition occurs.
This bit is cleared by writing a one to this bit and when the corresponding FAULTxIN status bit is low.
Once this bit is clear, the timer/counter will restart from the last COUNT value. To restart the timer/counter
from BOTTOM, the timer/counter restart command must be executed before clearing the corresponding
STATEx bit. For further details on timer/counter commands, refer to available commands description
(CTRLBSET.CMD).
Bit 13 – FAULTB: Recoverable Fault B State
This bit is set by hardware as soon as recoverable Fault B condition occurs.
This bit can be clear by hardware when Fault B action is resumed, or by writing a '1' to this bit when the
corresponding FAULTBIN bit is low. If software halt command is enabled (FAULTB.HALT=SW), clearing
this bit will release the timer/counter.
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SAM DA1
Bit 12 – FAULTA: Recoverable Fault A State
This bit is set by hardware as soon as recoverable Fault A condition occurs.
This bit can be clear by hardware when Fault A action is resumed, or by writing a '1' to this bit when the
corresponding FAULTAIN bit is low. If software halt command is enabled (FAULTA.HALT=SW), clearing
this bit will release the timer/counter.
Bit 11 – FAULT1IN: Non-Recoverable Fault 1 Input
This bit is set while an active Non-Recoverable Fault 1 input is present.
Bit 10 – FAULT0IN: Non-Recoverable Fault 0 Input
This bit is set while an active Non-Recoverable Fault 0 input is present.
Bit 9 – FAULTBIN: Recoverable Fault B Input
This bit is set while an active Recoverable Fault B input is present.
Bit 8 – FAULTAIN: Recoverable Fault A Input
This bit is set while an active Recoverable Fault A input is present.
Bit 7 – PERBV: Period Buffer Valid
This bit is set when a new value is written to the PERB register. This bit is automatically cleared by
hardware on UPDATE condition when CTRLB.LUPD is set, or by writing a '1' to this bit.
Bit 6 – WAVEBV: Waveform Control Buffer Valid
This bit is set when a new value is written to the WAVEB register. This bit is automatically cleared by
hardware on UPDATE condition when CTRLB.LUPD is set, or by writing a '1' to this bit.
Bit 5 – PATTBV: Pattern Generator Value Buffer Valid
This bit is set when a new value is written to the PATTB register. This bit is automatically cleared by
hardware on UPDATE condition when CTRLB.LUPD is set, or by writing a '1' to this bit.
Bit 3 – DFS: Debug Fault State
This bit is set by hardware in debug mode when DDBGCTRL.FDDBD bit is set. The bit is cleared by
writing a '1' to this bit and when the TCC is not in debug mode.
When the bit is set, the counter is halted and the waveforms state depend on DRVCTRL.NRE and
DRVCTRL.NRV registers.
Bit 1 – IDX: Ramp Index
In RAMP2 and RAMP2A operation, the bit is cleared during the cycle A and set during the cycle B. In
RAMP1 operation, the bit always reads zero. For details on ramp operations, refer to Ramp Operations.
Bit 0 – STOP: Stop
This bit is set when the TCC is disabled either on a STOP command or on an UPDATE condition when
One-Shot operation mode is enabled (CTRLBSET.ONESHOT=1).
This bit is clear on the next incoming counter increment or decrement.
Value
0
1
Description
Counter is running.
Counter is stopped.
© 2017 Microchip Technology Inc.
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SAM DA1
33.8.14 Counter Value
Note: Prior to any read access, this register must be synchronized by user by writing the according TCC
Command value to the Control B Set register (CTRLBSET.CMD=READSYNC).
Name: COUNT
Offset: 0x34 [ID-00002e48]
Reset: 0x00000000
Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
COUNT[23:16]
Access
COUNT[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
COUNT[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 23:0 – COUNT[23:0]: Counter Value
These bits hold the value of the counter register.
Note: When the TCC is configured as 16-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the MSB of the register, [23:m]. m is dependent on the Resolution bit in the
Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [23:m]
0x0 - NONE
23:0 (depicted)
0x1 - DITH4
23:4
0x2 - DITH5
23:5
0x3 - DITH6
23:6
33.8.15 Pattern
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SAM DA1
Name: PATT
Offset: 0x38 [ID-00002e48]
Reset: 0x0000
Property: Write-Synchronized
Bit
15
14
13
12
11
10
9
8
PGV0[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PGE0[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 8:15, 16:23, 24:31, 32:39, 40:47, 48:55, 56:63, 64:71 – PGV: Pattern Generation Output Value
This register holds the values of pattern for each waveform output.
Bits 0:7, 8:15, 16:23, 24:31, 32:39, 40:47, 48:55, 56:63 – PGE: Pattern Generation Output Enable
This register holds the enable status of pattern generation for each waveform output. A bit written to '1'
will override the corresponding SWAP output with the corresponding PGVn value.
33.8.16 Waveform
Name: WAVE
Offset: 0x3C [ID-00002e48]
Reset: 0x00000000
Property: Write-Synchronized
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SAM DA1
Bit
31
30
29
28
Access
Reset
Bit
23
22
21
20
Access
Reset
Bit
15
14
13
12
Access
Reset
Bit
7
6
5
CIPEREN
Access
Reset
4
27
26
25
24
SWAP3
SWAP2
SWAP1
SWAP0
R/W
R/W
R/W
R/W
0
0
0
0
19
18
17
16
POL3
POL2
POL1
POL0
R/W
R/W
R/W
R/W
0
0
0
0
11
10
9
8
CICCEN3
CICCEN2
CICCEN1
CICCEN0
R/W
R/W
R/W
R/W
0
0
0
0
3
2
1
0
RAMP[1:0]
WAVEGEN[2:0]
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bits 24, 25, 26, 27 – SWAP: Swap DTI Output Pair x
Setting these bits enables output swap of DTI outputs [x] and [x+WO_NUM/2]. Note the DTIxEN settings
will not affect the swap operation.
Bits 16, 17, 18, 19 – POL: Channel Polarity x
Setting these bits enables the output polarity in single-slope and dual-slope PWM operations.
Value
0
1
0
1
Name
(single-slope PWM waveform
generation)
(single-slope PWM waveform
generation)
(dual-slope PWM waveform
generation)
(dual-slope PWM waveform
generation)
Description
Compare output is initialized to ~DIR and set to DIR when
TCC counter matches CCx value
Compare output is initialized to DIR and set to ~DIR when
TCC counter matches CCx value.
Compare output is set to ~DIR when TCC counter matches
CCx value
Compare output is set to DIR when TCC counter matches
CCx value.
Bits 8, 9, 10, 11 – CICCEN: Circular CC Enable x
Setting this bits enables the compare circular buffer option on channel. When the bit is set, CCx register
value is copied-back into the CCx register on UPDATE condition.
Bit 7 – CIPEREN: Circular Period Enable
Setting this bits enable the period circular buffer option. When the bit is set, the PER register value is
copied-back into the PERB register on UPDATE condition.
Bits 5:4 – RAMP[1:0]: Ramp Operation
These bits select Ramp operation (RAMP). These bits are not synchronized.
Value
0x0
0x1
Name
RAMP1
RAMP2A
© 2017 Microchip Technology Inc.
Description
RAMP1 operation
Alternative RAMP2 operation
Datasheet Complete
40001895A-page 641
SAM DA1
Value
0x2
0x3
Name
RAMP2
-
Description
RAMP2 operation
Reserved
Bits 2:0 – WAVEGEN[2:0]: Waveform Generation Operation
These bits select the waveform generation operation. The settings impact the top value and control if
frequency or PWM waveform generation should be used. These bits are not synchronized.
Value
Name
Description
Operation
Top
Update
Waveform Output
On Match
Waveform Output
On Update
OVFIF/Event
Up Down
0x0
NFRQ
Normal Frequency
PER
TOP/Zero
Toggle
Stable
TOP
Zero
0x1
MFRQ
Match Frequency
CC0
TOP/Zero
Toggle
Stable
TOP
Zero
0x2
NPWM
Normal PWM
PER
TOP/Zero
Set
Clear
TOP
Zero
0x3
Reserved
–
–
–
–
–
–
–
0x4
DSCRITICAL
Dual-slope PWM
PER
Zero
~DIR
Stable
–
Zero
0x5
DSBOTTOM
Dual-slope PWM
PER
Zero
~DIR
Stable
–
Zero
0x6
DSBOTH
Dual-slope PWM
PER
TOP & Zero
~DIR
Stable
TOP
Zero
0x7
DSTOP
Dual-slope PWM
PER
Zero
~DIR
Stable
TOP
–
33.8.17 Period Value
Name: PER
Offset: 0x40 [ID-00002e48]
Reset: 0xFFFFFFFF
Property: Write-Synchronized
© 2017 Microchip Technology Inc.
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SAM DA1
Bit
31
30
29
28
23
22
21
20
27
26
25
24
19
18
17
16
Access
Reset
Bit
PER[17:10]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
1
1
1
1
1
1
1
Bit
15
14
13
12
11
10
9
8
PER[9:2]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
1
1
1
1
1
1
1
Bit
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
PER[1:0]
Access
Reset
DITHER[5:0]
Bits 23:6 – PER[17:0]: Period Value
These bits hold the value of the period buffer register.
Note: When the TCC is configured as 16-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the MSB of the register, [23:m]. m is dependent on the Resolution bit in the
Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [23:m]
0x0 - NONE
23:0
0x1 - DITH4
23:4
0x2 - DITH5
23:5
0x3 - DITH6
23:6 (depicted)
Bits 5:0 – DITHER[5:0]: Dithering Cycle Number
These bits hold the number of extra cycles that are added on the PWM pulse period every 64 PWM
frames.
Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution
bits in the Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [n:0]
0x0 - NONE
-
0x1 - DITH4
3:0
0x2 - DITH5
4:0
0x3 - DITH6
5:0 (depicted)
© 2017 Microchip Technology Inc.
Datasheet Complete
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SAM DA1
33.8.18 Compare/Capture Channel x
The CCx register represents the 16-, 24- bit value, CCx. The register has two functions, depending of the
mode of operation.
For capture operation, this register represents the second buffer level and access point for the CPU and
DMA.
For compare operation, this register is continuously compared to the counter value. Normally, the output
form the comparator is then used for generating waveforms.
CCx register is updated with the buffer value from their corresponding CCBx register when an UPDATE
condition occurs.
In addition, in match frequency operation, the CC0 register controls the counter period.
Name: CC
Offset: 0x44 + n*0x04 [n=0..3]
Reset: 0x00000000
Property: Write-Synchronized, Read-Synchronized
Bit
31
30
29
28
23
22
21
20
27
26
25
24
19
18
17
16
Access
Reset
Bit
CC[17:10]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
CC[9:2]
Access
CC[1:0]
Access
Reset
DITHER[5:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 23:6 – CC[17:0]: Channel x Compare/Capture Value
These bits hold the value of the Channel x compare/capture register.
Note: When the TCC is configured as 16-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the m MSB of the register, [23:m]. m is dependent on the Resolution bit in
the Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [23:m]
0x0 - NONE
23:0
0x1 - DITH4
23:4
© 2017 Microchip Technology Inc.
Datasheet Complete
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SAM DA1
CTRLA.RESOLUTION
Bits [23:m]
0x2 - DITH5
23:5
0x3 - DITH6
23:6 (depicted)
Bits 5:0 – DITHER[5:0]: Dithering Cycle Number
These bits hold the number of extra cycles that are added on the PWM pulse width every 64 PWM
frames.
Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution
bits in the Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [n:0]
0x0 - NONE
-
0x1 - DITH4
3:0
0x2 - DITH5
4:0
0x3 - DITH6
5:0 (depicted)
33.8.19 Pattern Buffer
Name: PATTB
Offset: 0x64
Reset: 0x0000
Property: Write-Synchronized, Read-Synchronized
Bit
15
14
13
12
11
10
9
8
PGVB0[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PGEB0[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 8:15, 16:23, 24:31, 32:39, 40:47, 48:55, 56:63, 64:71 – PGVB: Pattern Generation Output Value
Buffer
This register is the buffer for the PGV register. If double buffering is used, valid content in this register is
copied to the PGV register on an UPDATE condition.
Bits 0:7, 8:15, 16:23, 24:31, 32:39, 40:47, 48:55, 56:63 – PGEB: Pattern Generation Output Enable
Buffer
This register is the buffer of the PGE register. If double buffering is used, valid content in this register is
copied into the PGE register at an UPDATE condition.
33.8.20 Waveform Buffer
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 645
SAM DA1
Name: WAVEB
Offset: 0x68 [ID-00002e48]
Reset: 0x00000000
Property: Write-Synchronized, Read-Synchronized
Bit
31
30
29
28
Access
Reset
Bit
23
22
21
20
Access
Reset
Bit
15
14
13
12
Access
Reset
Bit
7
6
5
CIPERENB
Access
Reset
4
27
26
25
24
SWAPB 3
SWAPB 2
SWAPB 1
SWAPB 0
R/W
R/W
R/W
R/W
0
0
0
0
19
18
17
16
POLB3
POLB2
POLB1
POLB0
R/W
R/W
R/W
R/W
0
0
0
0
11
10
9
8
CICCENB3
CICCENB2
CICCENB1
CICCENB0
R/W
R/W
R/W
R/W
0
0
0
0
3
2
1
0
RAMPB[1:0]
WAVEGENB[2:0]
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bits 24, 25, 26, 27 – SWAPB : Swap DTI output pair x Buffer
These register bits are the buffer bits for the SWAP register bits. If double buffering is used, valid content
in these bits is copied to the corresponding SWAPx bits on an UPDATE condition.
Bits 16, 17, 18, 19 – POLB: Channel Polarity x Buffer
These register bits are the buffer bits for POLx register bits. If double buffering is used, valid content in
these bits is copied to the corresponding POBx bits on an UPDATE condition.
Bits 8, 9, 10, 11 – CICCENB: Circular CCx Buffer Enable
These register bits are the buffer bits for CICCENx register bits. If double buffering is used, valid content
in these bits is copied to the corresponding CICCENx bits on a UPDATE condition.
Bit 7 – CIPERENB: Circular Period Enable Buffer
This register bit is the buffer bit for CIPEREN register bit. If double buffering is used, valid content in this
bit is copied to the corresponding CIPEREN bit on a UPDATE condition.
Bits 5:4 – RAMPB[1:0]: Ramp Operation Buffer
These register bits are the buffer bits for RAMP register bits. If double buffering is used, valid content in
these bits is copied to the corresponding RAMP bits on a UPDATE condition.
Bits 2:0 – WAVEGENB[2:0]: Waveform Generation Operation Buffer
These register bits are the buffer bits for WAVEGEN register bits. If double buffering is used, valid content
in these bits is copied to the corresponding WAVEGEN bits on a UPDATE condition.
33.8.21 Period Buffer Value
© 2017 Microchip Technology Inc.
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40001895A-page 646
SAM DA1
Name: PERB
Offset: 0x6C [ID-00002e48]
Reset: 0xFFFFFFFF
Property: Write-Synchronized, Read-Synchronized
Bit
31
30
29
28
23
22
21
20
27
26
25
24
19
18
17
16
Access
Reset
Bit
PERB[17:10]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
1
1
1
1
1
1
1
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
1
1
1
1
1
1
1
Bit
7
6
5
4
3
2
1
0
PERB[9:2]
Access
PERB[1:0]
Access
Reset
DITHERB[5:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
1
1
1
Bits 23:6 – PERB[17:0]: Period Buffer Value
These bits hold the value of the period buffer register. The value is copied to PER register on UPDATE
condition.
Note: When the TCC is configured as 16-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the MSB of the register, [23:m]. m is dependent on the Resolution bit in the
Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [23:m]
0x0 - NONE
23:0
0x1 - DITH4
23:4
0x2 - DITH5
23:5
0x3 - DITH6
23:6 (depicted)
Bits 5:0 – DITHERB[5:0]: Dithering Buffer Cycle Number
These bits represent the PER.DITHER bits buffer. When the double buffering is enabled, the value of this
bit field is copied to the PER.DITHER bits on an UPDATE condition.
Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution
bits in the Control A register (CTRLA.RESOLUTION):
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 647
SAM DA1
CTRLA.RESOLUTION
Bits [n:0]
0x0 - NONE
-
0x1 - DITH4
3:0
0x2 - DITH5
4:0
0x3 - DITH6
5:0 (depicted)
33.8.22 Channel x Compare/Capture Buffer Value
CCBx is copied into CCx at TCC update time
Name: CCB
Offset: 0x70 + n*0x04 [n=0..3]
Reset: 0x00000000
Property: Write-Synchronized, Read-Synchronized
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
Access
Reset
Bit
CCB[17:10]
Access
CCB[9:2]
Access
CCB[1:0]
Access
Reset
DITHERB[5:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 23:6 – CCB[17:0]: Channel x Compare/Capture Buffer Value
These bits hold the value of the Channel x Compare/Capture Buffer Value register. The register serves as
the buffer for the associated compare or capture registers (CCx). Accessing this register using the CPU
or DMA will affect the corresponding CCBVx status bit.
Note: When the TCC is configured as 16-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the MSB of the register, [23:m]. m is dependent on the Resolution bit in the
Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [23:m]
0x0 - NONE
23:0
0x1 - DITH4
23:4
© 2017 Microchip Technology Inc.
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SAM DA1
CTRLA.RESOLUTION
Bits [23:m]
0x2 - DITH5
23:5
0x3 - DITH6
23:6 (depicted)
Bits 5:0 – DITHERB[5:0]: Dithering Buffer Cycle Number
These bits represent the CCx.DITHER bits buffer. When the double buffering is enable, DITHERBUF bits
value is copied to the CCx.DITHER bits on an UPDATE condition.
Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution
bits in the Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [n:0]
0x0 - NONE
-
0x1 - DITH4
3:0
0x2 - DITH5
4:0
0x3 - DITH6
5:0 (depicted)
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 649
SAM DA1
34.
USB – Universal Serial Bus
34.1
Overview
The Universal Serial Bus interface (USB) module complies with the Universal Serial Bus (USB) 2.1
specification supporting both device and embedded host modes.
The USB device mode supports 8 endpoint addresses. All endpoint addresses have one input and one
output endpoint, for a total of 16 endpoints. Each endpoint is fully configurable in any of the four transfer
types: control, interrupt, bulk or isochronous. The USB host mode supports up to 8 pipes. The maximum
data payload size is selectable up to 1023 bytes.
Internal SRAM is used to keep the configuration and data buffer for each endpoint. The memory locations
used for the endpoint configurations and data buffers is fully configurable. The amount of memory
allocated is dynamic according to the number of endpoints in use, and the configuration of these. The
USB module has a built-in Direct Memory Access (DMA) and will read/write data from/to the system RAM
when a USB transaction takes place. No CPU or DMA Controller resources are required.
To maximize throughput, an endpoint can be configured for ping-pong operation. When this is done the
input and output endpoint with the same address are used in the same direction. The CPU or DMA
Controller can then read/write one data buffer while the USB module writes/reads from the other buffer.
This gives double buffered communication.
Multi-packet transfer enables a data payload exceeding the maximum packet size of an endpoint to be
transferred as multiple packets without any software intervention. This reduces the number of interrupts
and software intervention needed for USB transfers.
For low power operation the USB module can put the microcontroller in any sleep mode when the USB
bus is idle and a suspend condition is given. Upon bus resume, the USB module can wake the
microcontroller from any sleep mode.
34.2
Features
•
•
•
•
•
•
Compatible with the USB 2.1 specification
USB Embedded Host and Device mode
Supports full (12Mbit/s) and low (1.5Mbit/s) speed communication
Supports Link Power Management (LPM-L1) protocol
On-chip transceivers with built-in pull-ups and pull-downs
On-Chip USB serial resistors
•
•
1kHz SOF clock available on external pin
Device mode
– Supports 8 IN endpoints and 8 OUT endpoints
– No endpoint size limitations
– Built-in DMA with multi-packet and dual bank for all endpoints
– Supports feedback endpoint
– Supports crystal less clock
Host mode
– Supports 8 physical pipes
– No pipe size limitations
•
© 2017 Microchip Technology Inc.
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40001895A-page 650
SAM DA1
–
–
–
–
34.3
Supports multiplexed virtual pipe on one physical pipe to allow an unlimited USB tree
Built-in DMA with multi-packet support and dual bank for all pipes
Supports feedback endpoint
Supports the USB 2.0 Phase-locked SOFs feature
USB Block Diagram
Figure 34-1. High-speed Implementation: USB Block Diagram
LS/FS Implementation: USB Block Diagram
USB
SRAM Controller
AHB Slave
APB
dedicated bus
device-wide bus
AHB Master
User
Interface
DP
USB interrupts
NVIC
SOF 1kHz
GCLK_USB
GCLK
System clock domain
34.4
DM
USB 2.0
Core
USB clock domain
Signal Description
Pin Name
Pin Description
Type
DM
Data -: Differential Data Line - Port
Input/Output
DP
Data +: Differential Data Line + Port
Input/Output
SOF 1kHZ
SOF Output
Output
Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal
can be mapped on several pins.
Related Links
I/O Multiplexing and Considerations
34.5
Product Dependencies
In order to use this peripheral module, other parts of the system must be configured correctly, as
described below.
© 2017 Microchip Technology Inc.
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SAM DA1
34.5.1
I/O Lines
The USB pins may be multiplexed with the I/O lines Controller. The user must first configure the I/O
Controller to assign the USB pins to their peripheral functions.
A 1kHz SOF clock is available on an external pin. The user must first configure the I/O Controller to
assign the 1kHz SOF clock to the peripheral function. The SOF clock is available for device and host
mode.
34.5.2
Power Management
This peripheral can continue to operate in any sleep mode where its source clock is running. The
interrupts can wake up the device from sleep modes. Events connected to the event system can trigger
other operations in the system without exiting sleep modes.
Related Links
PM – Power Manager
34.5.3
Clocks
The USB bus clock (CLK_USB_AHB) can be enabled and disabled in the Power Manager, and the
default state of CLK_USB_AHB can be found in the Peripheral Clock Masking.
A generic clock (GCLK_USB) is required to clock the USB. This clock must be configured and enabled in
the Generic Clock Controller before using the USB. Refer to GCLK - Generic Clock Controller for further
details.
This generic clock is asynchronous to the bus clock (CLK_USB_AHB). Due to this asynchronicity, writes
to certain registers will require synchronization between the clock domains. Refer to GCLK
Synchronization for further details.
The USB module requires a GCLK_USB of 48 MHz ± 0.25% clock for low speed and full speed operation.
To follow the USB data rate at 12Mbit/s in full-speed mode, the CLK_USB_AHB clock should be at
minimum 8MHz.
Clock recovery is achieved by a digital phase-locked loop in the USB module, which complies with the
USB jitter specifications. If crystal-less operation is used in USB device mode, refer to USB Clock
Recovery Module.
Related Links
GCLK - Generic Clock Controller
USB Clock Recovery Mode
Peripheral Clock Masking
Synchronization
34.5.4
DMA
The USB has a built-in Direct Memory Access (DMA) and will read/write data to/from the system RAM
when a USB transaction takes place. No CPU or DMA Controller resources are required.
34.5.5
Interrupts
The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this
peripheral, the Interrupt Controller (NVIC) must be configured first. Refer to Nested Vector Interrupt
Controller for details.
Related Links
Nested Vector Interrupt Controller
© 2017 Microchip Technology Inc.
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40001895A-page 652
SAM DA1
34.5.6
Events
Not applicable.
34.5.7
Debug Operation
When the CPU is halted in debug mode the USB peripheral continues normal operation. If the USB
peripheral is configured in a way that requires it to be periodically serviced by the CPU through interrupts
or similar, improper operation or data loss may result during debugging.
34.5.8
Register Access Protection
Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC),
except for the following:
•
•
•
•
Device Interrupt Flag (INTFLAG) register
Endpoint Interrupt Flag (EPINTFLAG) register
Host Interrupt Flag (INTFLAG) register
Pipe Interrupt Flag (PINTFLAG) register
Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register
description.
When the CPU is halted in debug mode, all write-protection is automatically disabled. Write-protection
does not apply for accesses through an external debugger.
34.5.9
Analog Connections
Not applicable.
34.5.10 Calibration
The output drivers for the DP/DM USB line interface can be fine tuned with calibration values from
production tests. The calibration values must be loaded from the NVM Software Calibration Area into the
USB Pad Calibration register (PADCAL) by software, before enabling the USB, to achieve the specified
accuracy. Refer to NVM Software Calibration Area Mapping for further details.
For details on Pad Calibration, refer to Pad Calibration (PADCAL) register.
Related Links
NVM Software Calibration Area Mapping
34.6
Functional Description
34.6.1
USB General Operation
34.6.1.1 Initialization
After a hardware reset, the USB is disabled. The user should first enable the USB (CTRLA.ENABLE) in
either device mode or host mode (CTRLA.MODE).
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Figure 34-2. General States
HW RESET | CTRLA.SWRST
Any state
Idle
CTRLA.ENABLE = 1
CTRLA.MODE
=0
CTRLA.ENABLE = 0
CTRLA.ENABLE = 1
CTRLA.MODE
=1
CTRLA.ENABLE = 0
Device
Host
After a hardware reset, the USB is in the idle state. In this state:
•
•
•
•
The module is disabled. The USB Enable bit in the Control A register (CTRLA.ENABLE) is reset.
The module clock is stopped in order to minimize power consumption.
The USB pad is in suspend mode.
The internal states and registers of the device and host are reset.
Before using the USB, the Pad Calibration register (PADCAL) must be loaded with production calibration
values from the NVM Software Calibration Area.
The USB is enabled by writing a '1' to CTRLA.ENABLE. The USB is disabled by writing a '0' to
CTRLA.ENABLE.
The USB is reset by writing a '1' to the Software Reset bit in CTRLA (CTRLA.SWRST). All registers in the
USB will be reset to their initial state, and the USB will be disabled. Refer to the CTRLA register for
details.
The user can configure pads and speed before enabling the USB by writing to the Operating Mode bit in
the Control A register (CTRLA.MODE) and the Speed Configuration field in the Control B register
(CTRLB.SPDCONF). These values are taken into account once the USB has been enabled by writing a
'1' to CTRLA.ENABLE.
After writing a '1' to CTRLA.ENABLE, the USB enters device mode or host mode (according to
CTRLA.MODE).
The USB can be disabled at any time by writing a '0' to CTRLA.ENABLE.
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Refer to USB Device Operations for the basic operation of the device mode.
Refer to Host Operations for the basic operation of the host mode.
Related Links
NVM Software Calibration Area Mapping
34.6.2
USB Device Operations
This section gives an overview of the USB module device operation during normal transactions. For more
details on general USB and USB protocol, refer to the Universal Serial Bus specification revision 2.1.
34.6.2.1 Initialization
To attach the USB device to start the USB communications from the USB host, a zero should be written
to the Detach bit in the Device Control B register (CTRLB.DETACH). To detach the device from the USB
host, a one must be written to the CTRLB.DETACH.
After the device is attached, the host will request the USB device descriptor using the default device
address zero. On successful transmission, it will send a USB reset. After that, it sends an address to be
configured for the device. All further transactions will be directed to this device address. This address
should be configured in the Device Address field in the Device Address register (DADD.DADD) and the
Address Enable bit in DADD (DADD.ADDEN) should be written to one to accept communications directed
to this address. DADD.ADDEN is automatically cleared on receiving a USB reset.
34.6.2.2 Endpoint Configuration
Endpoint data can be placed anywhere in the device RAM. The USB controller accesses these endpoints
directly through the AHB master (built-in DMA) with the help of the endpoint descriptors. The base
address of the endpoint descriptors needs to be written in the Descriptor Address register (DESCADD) by
the user. Refer also to the Endpoint Descriptor structure in Endpoint Descriptor Structure.
Before using an endpoint, the user should configure the direction and type of the endpoint in Type of
Endpoint field in the Device Endpoint Configuration register (EPCFG.EPTYPE0/1). The endpoint
descriptor registers should be initialized to known values before using the endpoint, so that the USB
controller does not read random values from the RAM.
The Endpoint Size field in the Packet Size register (PCKSIZE.SIZE) should be configured as per the size
reported to the host for that endpoint. The Address of Data Buffer register (ADDR) should be set to the
data buffer used for endpoint transfers.
The RAM Access Interrupt bit in Device Interrupt Flag register (INTFLAG.RAMACER) is set when a RAM
access underflow error occurs during IN data stage.
When an endpoint is disabled, the following registers are cleared for that endpoint:
•
Device Endpoint Interrupt Enable Clear/Set (EPINTENCLR/SET) register
•
•
•
Device Endpoint Interrupt Flag (EPINTFLAG) register
Transmit Stall 0 bit in the Endpoint Status register (EPSTATUS.STALLRQ0)
Transmit Stall 1 bit in the Endpoint Status register (EPSTATUS.STALLRQ1)
34.6.2.3 Multi-Packet Transfers
Multi-packet transfer enables a data payload exceeding the endpoint maximum transfer size to be
transferred as multiple packets without software intervention. This reduces the number of interrupts and
software intervention required to manage higher level USB transfers. Multi-packet transfer is identical to
the IN and OUT transactions described below unless otherwise noted in this section.
The application software provides the size and address of the RAM buffer to be proceeded by the USB
module for a specific endpoint, and the USB module will split the buffer in the required USB data transfers
without any software intervention.
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Figure 34-3. Multi-Packet Feature - Reduction of CPU Overhead
Data Payload
Without Multi-packet support
Transfer Complete Interrupt
&
Data Processing
Maximum Endpoint size
With Multi-packet support
34.6.2.4 USB Reset
The USB bus reset is initiated by a connected host and managed by hardware.
During USB reset the following registers are cleared:
•
•
Device Endpoint Configuration (EPCFG) register - except for Endpoint 0
Device Frame Number (FNUM) register
•
•
•
•
•
•
•
Device Address (DADD) register
Device Endpoint Interrupt Enable Clear/Set (EPINTENCLR/SET) register
Device Endpoint Interrupt Flag (EPINTFLAG) register
Transmit Stall 0 bit in the Endpoint Status register (EPSTATUS.STALLRQ0)
Transmit Stall 1 bit in the Endpoint Status register (EPSTATUS.STALLRQ1)
Endpoint Interrupt Summary (EPINTSMRY) register
Upstream resume bit in the Control B register (CTRLB.UPRSM)
At the end of the reset process, the End of Reset bit is set in the Interrupt Flag register
(INTFLAG.EORST).
34.6.2.5 Start-of-Frame
When a Start-of-Frame (SOF) token is detected, the frame number from the token is stored in the Frame
Number field in the Device Frame Number register (FNUM.FNUM), and the Start-of-Frame interrupt bit in
the Device Interrupt Flag register (INTFLAG.SOF) is set. If there is a CRC or bit-stuff error, the Frame
Number Error status flag (FNUM.FNCERR) in the FNUM register is set.
34.6.2.6 Management of SETUP Transactions
When a SETUP token is detected and the device address of the token packet does not match
DADD.DADD, the packet is discarded and the USB module returns to idle and waits for the next token
packet.
When the address matches, the USB module checks if the endpoint is enabled in EPCFG. If the
addressed endpoint is disabled, the packet is discarded and the USB module returns to idle and waits for
the next token packet.
When the endpoint is enabled, the USB module then checks on the EPCFG of the addressed endpoint. If
the EPCFG.EPTYPE0 is not set to control, the USB module returns to idle and waits for the next token
packet.
When the EPCFG.EPTYPE0 matches, the USB module then fetches the Data Buffer Address (ADDR)
from the addressed endpoint's descriptor and waits for a DATA0 packet. If a PID error or any other PID
than DATA0 is detected, the USB module returns to idle and waits for the next token packet.
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When the data PID matches and if the Received Setup Complete interrupt bit in the Device Endpoint
Interrupt Flag register (EPINTFLAG.RXSTP) is equal to zero, ignoring the Bank 0 Ready bit in the Device
Endpoint Status register (EPSTATUS.BK0RDY), the incoming data is written to the data buffer pointed to
by the Data Buffer Address (ADDR). If the number of received data bytes exceeds the endpoint's
maximum data payload size as specified by the PCKSIZE.SIZE, the remainders of the received data
bytes are discarded. The packet will still be checked for bit-stuff and CRC errors. Software must never
report a endpoint size to the host that is greater than the value configured in PCKSIZE.SIZE. If a bit-stuff
or CRC error is detected in the packet, the USB module returns to idle and waits for the next token
packet.
If data is successfully received, an ACK handshake is returned to the host, and the number of received
data bytes, excluding the CRC, is written to the Byte Count (PCKSIZE.BYTE_COUNT). If the number of
received data bytes is the maximum data payload specified by PCKSIZE.SIZE, no CRC data is written to
the data buffer. If the number of received data bytes is the maximum data payload specified by
PCKSIZE.SIZE minus one, only the first CRC data is written to the data buffer. If the number of received
data is equal or less than the data payload specified by PCKSIZE.SIZE minus two, both CRC data bytes
are written to the data buffer.
Finally the EPSTATUS is updated. Data Toggle OUT bit (EPSTATUS.DTGLOUT), the Data Toggle IN bit
(EPSTATUS.DTGLIN), the current bank bit (EPSTATUS.CURRBK) and the Bank Ready 0 bit
(EPSTATUS.BK0RDY) are set. Bank Ready 1 bit (EPSTATUS.BK1RDY) and the Stall Bank 0/1 bit
(EPSTATUS.STALLQR0/1) are cleared on receiving the SETUP request. The RXSTP bit is set and
triggers an interrupt if the Received Setup Interrupt Enable bit is set in Endpoint Interrupt Enable Set/
Clear register (EPINTENSET/CLR.RXSTP).
34.6.2.7 Management of OUT Transactions
Figure 34-4. OUT Transfer: Data Packet Host to USB Device
Memory Map
HOST
I/O Register
USB I/O Registers
BULK OUT
EPT 2
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
BULK OUT
EPT 3
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
D
A
T
A
1
BULK OUT
EPT 1
D
A
T
A
0
D
A
T
A
0
D
A
T
A
1
Internal RAM
USB Module
USB Endpoints
Descriptor Table
D
A
T
A
0
DESCADD
ENDPOINT 1 DATA
ENDPOINT 3 DATA
DP
DM
USB Buffers
time
ENDPOINT 2 DATA
When an OUT token is detected, and the device address of the token packet does not match
DADD.DADD, the packet is discarded and the USB module returns to idle and waits for the next token
packet.
If the address matches, the USB module checks if the endpoint number received is enabled in the
EPCFG of the addressed endpoint. If the addressed endpoint is disabled, the packet is discarded and the
USB module returns to idle and waits for the next token packet.
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When the endpoint is enabled, the USB module then checks the Endpoint Configuration register
(EPCFG) of the addressed output endpoint. If the type of the endpoint (EPCFG.EPTYPE0) is not set to
OUT, the USB module returns to idle and waits for the next token packet.
The USB module then fetches the Data Buffer Address (ADDR) from the addressed endpoint's descriptor,
and waits for a DATA0 or DATA1 packet. If a PID error or any other PID than DATA0 or DATA1 is
detected, the USB module returns to idle and waits for the next token packet.
If EPSTATUS.STALLRQ0 in EPSTATUS is set, the incoming data is discarded. If the endpoint is not
isochronous, a STALL handshake is returned to the host and the Transmit Stall Bank 0 interrupt bit in
EPINTFLAG (EPINTFLAG.STALL0) is set.
For isochronous endpoints, data from both a DATA0 and DATA1 packet will be accepted. For other
endpoint types the PID is checked against EPSTATUS.DTGLOUT. If a PID mismatch occurs, the
incoming data is discarded, and an ACK handshake is returned to the host.
If EPSTATUS.BK0RDY is set, the incoming data is discarded, the bit Transmit Fail 0 interrupt bit in
EPINTFLAG (EPINTFLAG.TRFAIL0) and the status bit STATUS_BK.ERRORFLOW are set. If the
endpoint is not isochronous, a NAK handshake is returned to the host.
The incoming data is written to the data buffer pointed to by the Data Buffer Address (ADDR). If the
number of received data bytes exceeds the maximum data payload specified as PCKSIZE.SIZE, the
remainders of the received data bytes are discarded. The packet will still be checked for bit-stuff and CRC
errors. If a bit-stuff or CRC error is detected in the packet, the USB module returns to idle and waits for
the next token packet.
If the endpoint is isochronous and a bit-stuff or CRC error in the incoming data, the number of received
data bytes, excluding CRC, is written to PCKSIZE.BYTE_COUNT. Finally the EPINTFLAG.TRFAIL0 and
CRC Error bit in the Device Bank Status register (STATUS_BK.CRCERR) is set for the addressed
endpoint.
If data was successfully received, an ACK handshake is returned to the host if the endpoint is not
isochronous, and the number of received data bytes, excluding CRC, is written to
PCKSIZE.BYTE_COUNT. If the number of received data bytes is the maximum data payload specified by
PCKSIZE.SIZE no CRC data bytes are written to the data buffer. If the number of received data bytes is
the maximum data payload specified by PCKSIZE.SIZE minus one, only the first CRC data byte is written
to the data buffer If the number of received data is equal or less than the data payload specified by
PCKSIZE.SIZE minus two, both CRC data bytes are written to the data buffer.
Finally in EPSTATUS for the addressed output endpoint, EPSTATUS.BK0RDY is set and
EPSTATUS.DTGLOUT is toggled if the endpoint is not isochronous. The flag Transmit Complete 0
interrupt bit in EPINTFLAG (EPINTFLAG.TRCPT0) is set for the addressed endpoint.
34.6.2.8 Multi-Packet Transfers for OUT Endpoint
The number of data bytes received is stored in endpoint PCKSIZE.BYTE_COUNT as for normal
operation. Since PCKSIZE.BYTE_COUNT is updated after each transaction, it must be set to zero when
setting up a new transfer. The total number of bytes to be received must be written to
PCKSIZE.MULTI_PACKET_SIZE. This value must be a multiple of PCKSIZE.SIZE, otherwise excess
data may be written to SRAM locations used by other parts of the application.
EPSTATUS.DTGLOUT management for non-isochronous packets and EPINTFLAG.BK1RDY/BK0RDY
management are as for normal operation.
If a maximum payload size packet is received, PCKSIZE.BYTE_COUNT will be incremented by
PCKSIZE.SIZE after the transaction has completed, and EPSTATUS.DTGLOUT will be toggled if the
endpoint is not isochronous. If the updated PCKSIZE.BYTE_COUNT is equal to
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PCKSIZE.MULTI_PACKET_SIZE (i.e. the last transaction), EPSTATUS.BK1RDY/BK0RDY, and
EPINTFLAG.TRCPT0/TRCPT1 will be set.
34.6.2.9 Management of IN Transactions
Figure 34-5. IN Transfer: Data Packet USB Device to Host After Request from Host
Memory Map
I/O Register
HOST
CPU
USB I/O Registers
Internal RAM
EPT 2
D
A
T
A
0
D
A
T
A
1
EPT 3
D
A
T
A
0
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
D
A
T
A
1
USB Module
EPT 1
D
A
T
A
0
D
A
T
A
0
D
A
T
A
1
DP
DM
ENDPOINT 2 DATA
DESCADD
USB Endpoints
Descriptor Table
D
A
T
A
0
ENDPOINT 3 DATA
USB Buffers
EPT 2
I
N
T
O
K
E
N
I
N
EPT 3 T
O
K
E
N
I
N
EPT 1 T
O
K
E
N
ENDPOINT 1 DATA
time
When an IN token is detected, and if the device address of the token packet does not match
DADD.DADD, the packet is discarded and the USB module returns to idle and waits for the next token
packet.
When the address matches, the USB module checks if the endpoint received is enabled in the EPCFG of
the addressed endpoint and if not, the packet is discarded and the USB module returns to idle and waits
for the next token packet.
When the endpoint is enabled, the USB module then checks on the EPCFG of the addressed input
endpoint. If the EPCFG.EPTYPE1 is not set to IN, the USB module returns to idle and waits for the next
token packet.
If EPSTATUS.STALLRQ1 in EPSTATUS is set, and the endpoint is not isochronous, a STALL handshake
is returned to the host and EPINTFLAG.STALL1 is set.
If EPSTATUS.BK1RDY is cleared, the flag EPINTFLAG.TRFAIL1 is set. If the endpoint is not
isochronous, a NAK handshake is returned to the host.
The USB module then fetches the Data Buffer Address (ADDR) from the addressed endpoint's descriptor.
The data pointed to by the Data Buffer Address (ADDR) is sent to the host in a DATA0 packet if the
endpoint is isochronous. For non-isochronous endpoints a DATA0 or DATA1 packet is sent depending on
the state of EPSTATUS.DTGLIN. When the number of data bytes specified in endpoint
PCKSIZE.BYTE_COUNT is sent, the CRC is appended and sent to the host.
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For isochronous endpoints, EPSTATUS.BK1RDY is cleared and EPINTFLAG.TRCPT1 is set.
For all non-isochronous endpoints the USB module waits for an ACK handshake from the host. If an ACK
handshake is not received within 16 bit times, the USB module returns to idle and waits for the next token
packet. If an ACK handshake is successfully received EPSTATUS.BK1RDY is cleared,
EPINTFLAG.TRCPT1 is set and EPSTATUS.DTGLIN is toggled.
34.6.2.10 Multi-Packet Transfers for IN Endpoint
The total number of data bytes to be sent is written to PCKSIZE.BYTE_COUNT as for normal operation.
The Multi-packet size register (PCKSIZE.MULTI_PACKET_SIZE) is used to store the number of bytes
that are sent, and must be written to zero when setting up a new transfer.
When an IN token is received, PCKSIZE.BYTE_COUNT and PCKSIZE.MULTI_PACKET_SIZE are
fetched. If PCKSIZE.BYTE_COUNT minus PCKSIZE.MULTI_PACKET_SIZE is less than the endpoint
PCKSIZE.SIZE, endpoint BYTE_COUNT minus endpoint PCKSIZE.MULTI_PACKET_SIZE bytes are
transmitted, otherwise PCKSIZE.SIZE number of bytes are transmitted. If endpoint
PCKSIZE.BYTE_COUNT is a multiple of PCKSIZE.SIZE, the last packet sent will be zero-length if the
AUTOZLP bit is set.
If a maximum payload size packet was sent (i.e. not the last transaction), MULTI_PACKET_SIZE will be
incremented by the PCKSIZE.SIZE. If the endpoint is not isochronous the EPSTATUS.DTLGIN bit will be
toggled when the transaction has completed. If a short packet was sent (i.e. the last transaction),
MULTI_PACKET_SIZE is incremented by the data payload. EPSTATUS.BK0/1RDY will be cleared and
EPINTFLAG.TRCPT0/1 will be set.
34.6.2.11 Ping-Pong Operation
When an endpoint is configured for ping-pong operation, it uses both the input and output data buffers
(banks) for a given endpoint in a single direction. The direction is selected by enabling one of the IN or
OUT direction in EPCFG.EPTYPE0/1 and configuring the opposite direction in EPCFG.EPTYPE1/0 as
Dual Bank.
When ping-pong operation is enabled for an endpoint, the endpoint in the opposite direction must be
configured as dual bank. The data buffer, data address pointer and byte counter from the enabled
endpoint are used as Bank 0, while the matching registers from the disabled endpoint are used as Bank
1.
Figure 34-6. Ping-Pong Overview
Endpoint
single bank
Without Ping Pong
t
Endpoint
dual bank
Bank0
With Ping Pong
t
Bank1
USB data packet
Available time for data processing by CPU
to avoid NACK
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The Bank Select flag in EPSTATUS.CURBK indicates which bank data will be used in the next
transaction, and is updated after each transaction. According to EPSTATUS.CURBK,
EPINTFLAG.TRCPT0 or EPINTFLAG.TRFAIL0 or EPINTFLAG.TRCPT1 or EPINTFLAG.TRFAIL1 in
EPINTFLAG and Data Buffer 0/1 ready (EPSTATUS.BK0RDY and EPSTATUS.BK1RDY) are set. The
EPSTATUS.DTGLOUT and EPSTATUS.DTGLIN are updated for the enabled endpoint direction only.
34.6.2.12 Feedback Operation
Feedback endpoints are endpoints with same the address but in different directions. This is usually used
in explicit feedback mechanism in USB Audio, where a feedback endpoint is associated to one or more
isochronous data endpoints to which it provides feedback service. The feedback endpoint always has the
opposite direction from the data endpoint.
The feedback endpoint always has the opposite direction from the data endpoint(s). The feedback
endpoint has the same endpoint number as the first (lower) data endpoint. A feedback endpoint can be
created by configuring an endpoint with different endpoint size (PCKSIZE.SIZE) and different endpoint
type (EPCFG.EPTYPE0/1) for the IN and OUT direction.
Example Configuration for Feedback Operation:
•
Endpoint n / IN: EPCFG.EPTYPE1 = Interrupt IN, PCKSIZE.SIZE = 64.
•
Endpoint n / OUT: EPCFG.EPTYPE0= Isochronous OUT, PCKSIZE.SIZE = 512.
34.6.2.13 Suspend State and Pad Behavior
The following figure, Pad Behavior, illustrates the behavior of the USB pad in device mode.
Figure 34-7. Pad Behavior
Idle
CTRLA.ENABLE = 1
|
CTRLB.DETACH = 0
| INTFLAG.SUSPEND = 0
CTRLA.ENABLE = 0
|
CTRLB.DETACH = 1
| INTFLAG.SUSPEND = 1
Active
In Idle state, the pad is in low power consumption mode.
In Active state, the pad is active.
The following figure, Pad Events, illustrates the pad events leading to a PAD state change.
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Figure 34-8. Pad Events
Suspend detected
Cleared on Wakeup
Wakeup detected
Active
Cleared by software to acknowledge the interrupt
Idle
Active
The Suspend Interrupt bit in the Device Interrupt Flag register (INTFLAG.SUSPEND) is set when a USB
Suspend state has been detected on the USB bus. The USB pad is then automatically put in the Idle
state. The detection of a non-idle state sets the Wake Up Interrupt bit in INTFLAG(INTFLAG.WAKEUP)
and wakes the USB pad.
The pad goes to the Idle state if the USB module is disabled or if CTRLB.DETACH is written to one. It
returns to the Active state when CTRLA.ENABLE is written to one and CTRLB.DETACH is written to zero.
34.6.2.14 Remote Wakeup
The remote wakeup request (also known as upstream resume) is the only request the device may send
on its own initiative. This should be preceded by a DEVICE_REMOTE_WAKEUP request from the host.
First, the USB must have detected a “Suspend” state on the bus, i.e. the remote wakeup request can only
be sent after INTFLAG.SUSPEND has been set.
The user may then write a one to the Remote Wakeup bit in CTRLB(CTRLB.UPRSM) to send an
Upstream Resume to the host initiating the wakeup. This will automatically be done by the controller after
5 ms of inactivity on the USB bus.
When the controller sends the Upstream Resume INTFLAG.WAKEUP is set and INTFLAG.SUSPEND is
cleared.
The CTRLB.UPRSM is cleared at the end of the transmitting Upstream Resume.
In case of a rebroadcast resume initiated by the host, the End of Resume bit in
INTFLAG(INTFLAG.EORSM) flag is set when the rebroadcast resume is completed.
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In the case where the CTRLB.UPRSM bit is set while a host initiated downstream resume is already
started, the CTRLB.UPRSM is cleared and the upstream resume request is ignored.
34.6.2.15 Link Power Management L1 (LPM-L1) Suspend State Entry and Exit as Device
The LPM Handshake bit in CTRLB.LPMHDSK should be configured to accept the LPM transaction.
When a LPM transaction is received on any enabled endpoint n and a handshake has been sent in
response by the controller according to CTRLB.LPMHDSK, the Device Link Power Manager (EXTREG)
register is updated in the bank 0 of the addressed endpoint's descriptor. It contains information such as
the Best Effort Service Latency (BESL), the Remote Wake bit (bRemoteWake), and the Link State
parameter (bLinkState). Usually, the LPM transaction uses only the endpoint number 0.
If the LPM transaction was positively acknowledged (ACK handshake), USB sets the Link Power
Management Interrupt bit in INTFLAG(INTFLAG.LPMSUSP) bit which indicates that the USB transceiver
is suspended, reducing power consumption. This suspend occurs 9 microseconds after the LPM
transaction according to the specification.
To further reduce consumption, it is recommended to stop the USB clock while the device is suspended.
The MCU can also enter in one of the available sleep modes if the wakeup time latency of the selected
sleep mode complies with the host latency constraint (see the BESL parameter in EXTREG register).
Recovering from this LPM-L1 suspend state is exactly the same as the Suspend state (see Section
Suspend State and Pad Behavior) except that the remote wakeup duration initiated by USB is shorter to
comply with the Link Power Management specification.
If the LPM transaction is responded with a NYET, the Link Power Management Not Yet Interrupt Flag
INTFLAG(INTFLAG.LPMNYET) is set. This generates an interrupt if the Link Power Management Not Yet
Interrupt Enable bit in INTENCLR/SET (INTENCLR/SET.LPMNYET) is set.
If the LPM transaction is responded with a STALL or no handshake, no flag is set, and the transaction is
ignored.
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34.6.2.16 USB Device Interrupt
Figure 34-9. Device Interrupt
EPINTFLAG7.STALL
EPINTENSET7.STALL0/STALL1
EPINTFLAG7.TRFAIL1
EPINTENSET7.TRFAIL1
EPINTFLAG7.TRFAIL0
EPINTSMRY
EPINTENSET7.TRFAIL0
ENDPOINT7
EPINTFLAG7.RXSTP
EPINT7
EPINTENSET7.RXSTP
EPINT6
EPINTFLAG7.TRCPT1
EPINTENSET7.TRCPT1
EPINTFLAG7.TRCPT0
EPINTENSET7.TRCPT0
USB EndPoint
Interrupt
EPINTFLAG0.STALL
EPINTENSET0.STALL0/STALL1
EPINTFLAG0.TRFAIL1
EPINTENSET0.TRFAIL1
EPINTFLAG0.TRFAIL0
EPINTENSET0.TRFAIL0
EPINTFLAG0.RXSTP
ENDPOINT0
EPINT1
EPINT0
EPINTENSET0.RXSTP
EPINTFLAG0.TRCPT1
EPINTENSET0.TRCPT1
EPINTFLAG0.TRCPT0
USB
Interrupt
EPINTENSET0.TRCPT0
INTFLAG.LPMSUSP
INTENSET.LPMSUSP
INTFLAG.LPMNYET
INTENSET.DDISC
INTFLAG.RAMACER
INTENSET.RAMACER
INTFLAG.UPRSM
INTFLAG
INTENSET.UPRSM
INTFLAG.EORSM
USB Device Interrupt
INTENSET.EORSM
INTFLAG.WAKEUP
*
INTENSET.WAKEUP
INTFLAG.EORST
INTENSET.EORST
INTFLAG.SOF
INTENSET.SOF
INTFLAGA.MSOF
INTENSET.MSOF
INTFLAG.SUSPEND
INTENSET.SUSPEND
* Asynchronous interrupt
The WAKEUP is an asynchronous interrupt and can be used to wake-up the device from any sleep mode.
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34.6.3
Host Operations
This section gives an overview of the USB module Host operation during normal transactions. For more
details on general USB and USB protocol, refer to Universal Serial Bus Specification revision 2.1.
34.6.3.1 Device Detection and Disconnection
Prior to device detection the software must set the VBUS is OK bit in CTRLB (CTRLB.VBUSOK) register
when the VBUS is available. This notifies the USB host that USB operations can be started. When the bit
CTRLB.VBUSOK is zero and even if the USB HOST is configured and enabled, host operation is halted.
Setting the bit CTRLB.VBUSOK will allow host operation when the USB is configured.
The Device detection is managed by the software using the Line State field in the Host Status
(STATUS.LINESTATE) register. The device connection is detected by the host controller when DP or DM
is pulled high, depending of the speed of the device.
The device disconnection is detected by the host controller when both DP and DM are pulled down using
the STATUS.LINESTATE registers.
The Device Connection Interrupt bit in INTFLAG (INTFLAG.DCONN) is set if a device connection is
detected.
The Device Disconnection Interrupt bit in INTFLAG (INTFLAG.DDISC) is set if a device disconnection is
detected.
34.6.3.2 Host Terminology
In host mode, the term pipe is used instead of endpoint. A host pipe corresponds to a device endpoint,
refer to "Universal Serial Bus Specification revision 2.1." for more information.
34.6.3.3 USB Reset
The USB sends a USB reset signal when the user writes a one to the USB Reset bit in CTRLB
(CTRLB.BUSRESET). When the USB reset has been sent, the USB Reset Sent Interrupt bit in the
INTFLAG (INTFLAG.RST) is set and all pipes will be disabled.
If the bus was previously in a suspended state (Start of Frame Generation Enable bit in CTRLB
(CTRLB.SOFE) is zero) the USB will switch it to the Resume state, causing the bus to asynchronously set
the Host Wakeup Interrupt flag (INTFLAG.WAKEUP). The CTRLB.SOFE bit will be set in order to
generate SOFs immediately after the USB reset.
During USB reset the following registers are cleared:
•
•
•
•
•
•
•
All Host Pipe Configuration register (PCFG)
Host Frame Number register (FNUM)
Interval for the Bulk-Out/Ping transaction register (BINTERVAL)
Host Start-of-Frame Control register (HSOFC)
Pipe Interrupt Enable Clear/Set register (PINTENCLR/SET)
Pipe Interrupt Flag register (PINTFLAG)
Pipe Freeze bit in Pipe Status register (PSTATUS.FREEZE)
After the reset the user should check the Speed Status field in the Status register (STATUS.SPEED) to
find out the current speed according to the capability of the peripheral.
34.6.3.4 Pipe Configuration
Pipe data can be placed anywhere in the RAM. The USB controller accesses these pipes directly through
the AHB master (built-in DMA) with the help of the pipe descriptors. The base address of the pipe
descriptors needs to be written in the Descriptor Address register (DESCADD) by the user. Refer also to
Pipe Descriptor Structure.
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SAM DA1
Before using a pipe, the user should configure the direction and type of the pipe in Type of Pipe field in
the Host Pipe Configuration register (PCFG.PTYPE). The pipe descriptor registers should be initialized to
known values before using the pipe, so that the USB controller does not read the random values from the
RAM.
The Pipe Size field in the Packet Size register (PCKSIZE.SIZE) should be configured as per the size
reported by the device for the endpoint associated with this pipe. The Address of Data Buffer register
(ADDR) should be set to the data buffer used for pipe transfers.
The Pipe Bank bit in PCFG (PCFG.BK) should be set to one if dual banking is desired. Dual bank is not
supported for Control pipes.
The Ram Access Interrupt bit in Host Interrupt Flag register (INTFLAG.RAMACER) is set when a RAM
access underflow error occurs during an OUT stage.
When a pipe is disabled, the following registers are cleared for that pipe:
•
Interval for the Bulk-Out/Ping transaction register (BINTERVAL)
•
•
•
Pipe Interrupt Enable Clear/Set register (PINTENCLR/SET)
Pipe Interrupt Flag register (PINTFLAG)
Pipe Freeze bit in Pipe Status register (PSTATUS.FREEZE)
34.6.3.5 Pipe Activation
A disabled pipe is inactive, and will be reset along with its context registers (pipe registers for the pipe n).
Pipes are enabled by writing Type of the Pipe in PCFG (PCFG.PTYPE) to a value different than 0x0
(disabled).
When a pipe is enabled, the Pipe Freeze bit in Pipe Status register (PSTATUS.FREEZE) is set. This allow
the user to complete the configuration of the pipe, without starting a USB transfer.
When starting an enumeration, the user retrieves the device descriptor by sending an
GET_DESCRIPTOR USB request. This descriptor contains the maximal packet size of the device default
control endpoint (bMaxPacketSize0) which the user should use to reconfigure the size of the default
control pipe.
34.6.3.6 Pipe Address Setup
Once the device has answered the first host requests with the default device address 0, the host assigns
a new address to the device. The host controller has to send a USB reset to the device and a
SET_ADDRESS(addr) SETUP request with the new address to be used by the device. Once this SETUP
transaction is complete, the user writes the new address to the Pipe Device Address field in the Host
Control Pipe register (CTRL_PIPE.PDADDR) in Pipe descriptor. All following requests by this pipe will be
performed using this new address.
34.6.3.7 Suspend and Wakeup
Setting CTRLB.SOFE to zero when in host mode will cause the USB to cease sending Start-of-Frames
on the USB bus and enter the Suspend state. The USB device will enter the Suspend state 3ms later.
Before entering suspend by writing CTRLB.SOFE to zero, the user must freeze the active pipes by
setting their PSTATUS.FREEZE bit. Any current on-going pipe will complete its transaction, and then all
pipes will be inactive. The user should wait at least 1 complete frame before entering the suspend mode
to avoid any data loss.
The device can awaken the host by sending an Upstream Resume (Remote Wakeup feature). When the
host detects a non-idle state on the USB bus, it sets the INTFLAG.WAKEUP. If the non-idle bus state
corresponds to an Upstream Resume (K state), the Upstream Resume Received Interrupt bit in INTFLAG
(INTFLAG.UPRSM) is set and the user must generate a Downstream Resume within 1 ms and for at
© 2017 Microchip Technology Inc.
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SAM DA1
least 20 ms. It is required to first write a one to the Send USB Resume bit in CTRLB (CTRLB.RESUME)
to respond to the upstream resume with a downstream resume. Alternatively, the host can resume from a
suspend state by sending a Downstream Resume on the USB bus (CTRLB.RESUME set to 1). In both
cases, when the downstream resume is completed, the CTRLB.SOFE bit is automatically set and the
host enters again the active state.
34.6.3.8 Phase-locked SOFs
To support the Synchronous Endpoints capability, the period of the emitted Start-of-Frame is maintained
while the USB connection is not in the active state. This does not apply for the disconnected/connected/
reset states. It applies for active/idle/suspend/resume states. The period of Start-of-Frame will be 1ms
when the USB connection is in active state and an integer number of milli-seconds across idle/suspend/
resume states.
To ensure the Synchronous Endpoints capability, the GCLK_USB clock must be kept running. If the
GCLK_USB is interrupted, the period of the emitted Start-of-Frame will be erratic.
34.6.3.9 Management of Control Pipes
A control transaction is composed of three stages:
•
•
•
SETUP
Data (IN or OUT)
Status (IN or OUT)
The user has to change the pipe token according to each stage using the Pipe Token field in PCFG
(PCFG.PTOKEN).
For control pipes only, the token is assigned a specific initial data toggle sequence:
•
•
•
SETUP: Data0
IN: Data1
OUT: Data1
34.6.3.10 Management of IN Pipes
IN packets are sent by the USB device controller upon IN request reception from the host. All the
received data from the device to the host will be stored in the bank provided the bank is empty. The pipe
and its descriptor in RAM must be configured.
The host indicates it is able to receive data from the device by clearing the Bank 0/1 Ready bit in
PSTATUS (PSTATUS.BK0/1RDY), which means that the memory for the bank is available for new USB
transfer.
The USB will perform IN requests as long as the pipe is not frozen by the user.
The generation of IN requests starts when the pipe is unfrozen (PSTATUS.PFREEZE is set to zero).
When the current bank is full, the Transmit Complete 0/1 bit in PINTFLAG (PINTFLAG.TRCPT0/1) will be
set and trigger an interrupt if enabled and the PSTATUS.BK0/1RDY bit will be set.
PINTFLAG.TRCPT0/1 must be cleared by software to acknowledge the interrupt. This is done by writing
a one to the PINTFLAG.TRCPT0/1 of the addressed pipe.
The user reads the PCKSIZE.BYTE_COUNT to know how many bytes should be read.
To free the bank the user must read the IN data from the address ADDR in the pipe descriptor and clear
the PKSTATUS.BK0/1RDY bit. When the IN pipe is composed of multiple banks, a successful IN
transaction will switch to the next bank. Another IN request will be performed by the host as long as the
PSTATUS.BK0/1RDY bit for that bank is set. The PINTFLAG.TRCPT0/1 and PSTATUS.BK0/1RDY will be
updated accordingly.
© 2017 Microchip Technology Inc.
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SAM DA1
The user can follow the current bank looking at Current Bank bit in PSTATUS (PSTATUS.CURBK) and by
looking at Data Toggle for IN pipe bit in PSTATUS (PSTATUS.DTGLIN).
When the pipe is configured as single bank (Pipe Bank bit in PCFG (PCFG.BK) is 0), only
PINTFLAG.TRCPT0 and PSTATUS.BK0 are used. When the pipe is configured as dual bank (PCFG.BK
is 1), both PINTFLAG.TRCPT0/1 and PSTATUS.BK0/1 are used.
34.6.3.11 Management of OUT Pipes
OUT packets are sent by the host. All the data stored in the bank will be sent to the device provided the
bank is filled. The pipe and its descriptor in RAM must be configured.
The host can send data to the device by writing to the data bank 0 in single bank or the data bank 0/1 in
dual bank.
The generation of OUT packet starts when the pipe is unfrozen (PSTATUS.PFREEZE is zero).
The user writes the OUT data to the data buffer pointer by ADDR in the pipe descriptor and allows the
USB to send the data by writing a one to the PSTATUS.BK0/1RDY. This will also cause a switch to the
next bank if the OUT pipe is part of a dual bank configuration.
PINTFLAGn.TRCPT0/1 must be cleared before setting PSTATUS.BK0/1RDY to avoid missing an
PINTFLAGn.TRCPT0/1 event.
34.6.3.12 Alternate Pipe
The user has the possibility to run sequentially several logical pipes on the same physical pipe. It allows
addressing of any device endpoint of any attached device on the bus.
Before switching pipe, the user should save the pipe context (Pipe registers and descriptor for pipe n).
After switching pipe, the user should restore the pipe context (Pipe registers and descriptor for pipe n)
and in particular PCFG, and PSTATUS.
34.6.3.13 Data Flow Error
This error exists only for isochronous and interrupt pipes for both IN and OUT directions. It sets the
Transmit Fail bit in PINTFLAG (PINTFLAG.TRFAIL), which triggers an interrupt if the Transmit Fail bit in
PINTENCLR/SET(PINTENCLR/SET.TRFAIL) is set. The user must check the Pipe Interrupt Summary
register (PINTSMRY) to find out the pipe which triggered the interrupt. Then the user must check the
origin of the interrupt’s bank by looking at the Pipe Bank Status register (STATUS_BK) for each bank. If
the Error Flow bit in the STATUS_BK (STATUS_BK.ERRORFLOW) is set then the user is able to
determine the origin of the data flow error. As the user knows that the endpoint is an IN or OUT the error
flow can be deduced as OUT underflow or as an IN overflow.
An underflow can occur during an OUT stage if the host attempts to send data from an empty bank. If a
new transaction is successful, the relevant bank descriptor STATUS_BK.ERRORFLOW will be cleared.
An overflow can occur during an IN stage if the device tries to send a packet while the bank is full.
Typically this occurs when a CPU is not fast enough. The packet data is not written to the bank and is
lost. If a new transaction is successful, the relevant bank descriptor STATUS_BK.ERRORFLOW will be
cleared.
34.6.3.14 CRC Error
This error exists only for isochronous IN pipes. It sets the PINTFLAG.TRFAIL, which triggers an interrupt
if PINTENCLR/SET.TRFAIL is set. The user must check the PINTSMRY to find out the pipe which
triggered the interrupt. Then the user must check the origin of the interrupt’s bank by looking at the bank
descriptor STATUS_BK for each bank and if the CRC Error bit in STATUS_BK (STATUS_BK.CRCERR) is
set then the user is able to determine the origin of the CRC error. A CRC error can occur during the IN
stage if the USB detects a corrupted packet. The IN packet will remain stored in the bank and
PINTFLAG.TRCPT0/1 will be set.
© 2017 Microchip Technology Inc.
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SAM DA1
34.6.3.15 PERR Error
This error exists for all pipes. It sets the PINTFLAG.PERR Interrupt, which triggers an interrupt if
PINTFLAG.PERR is set. The user must check the PINTSMRY register to find out the pipe which can
cause an interrupt.
A PERR error occurs if one of the error field in the STATUS_PIPE register in the Host pipe descriptor is
set and the Error Count field in STATUS_PIPE (STATUS_PIPE.ERCNT) exceeds the maximum allowed
number of Pipe error(s) as defined in Pipe Error Max Number field in CTRL_PIPE
(CTRL_PIPE.PERMAX). Refer to section STATUS_PIPE register.
If one of the error field in the STATUS_PIPE register from the Host Pipe Descriptor is set and the
STATUS_PIPE.ERCNT is less than the CTRL_PIPE.PERMAX, the STATUS_PIPE.ERCNT is
incremented.
34.6.3.16 Link Power Management L1 (LPM-L1) Suspend State Entry and Exit as Host.
An EXTENDED LPM transaction can be transmitted by any enabled pipe. The PCFGn.PTYPE should be
set to EXTENDED. Other fields as PCFG.PTOKEN, PCFG.BK and PCKSIZE.SIZE are irrelevant in this
configuration. The user should also set the EXTREG.VARIABLE in the descriptor as described in
EXTREG register.
When the pipe is configured and enabled, an EXTENDED TOKEN followed by a LPM TOKEN are
transmitted. The device responds with a valid HANDSHAKE, corrupted HANDSHAKE or no
HANDSHAKE (TIME-OUT).
If the valid HANDSHAKE is an ACK, the host will immediately proceed to L1 SLEEP and the
PINTFLAG.TRCT0 is set. The minimum duration of the L1 SLEEP state will be the
TL1RetryAndResidency as defined in the reference document "ENGINEERING CHANGE NOTICE, USB
2.0 Link Power Management Addendum". When entering the L1 SLEEP state, the CTRLB.SOFE is
cleared, avoiding Start-of-Frame generation.
If the valid HANDSHAKE is a NYET PINTFLAG.TRFAIL is set.
If the valid HANDSHAKE is a STALL the PINTFLAG.STALL is set.
If there is no HANDSHAKE or corrupted HANDSHAKE, the EXTENDED/LPM pair of TOKENS will be
transmitted again until reaching the maximum number of retries as defined by the CTRL_PIPE.PERMAX
in the pipe descriptor.
If the last retry returns no valid HANDSHAKE, the PINTFLAGn.PERR is set, and the STATUS_BK is
updated in the pipe descriptor.
All LPM transactions, should they end up with a ACK, a NYET, a STALL or a PERR, will set the
PSTATUS.PFREEZE bit, freezing the pipe before a succeeding operation. The user should unfreeze the
pipe to start a new LPM transaction.
To exit the L1 STATE, the user initiate a DOWNSTREAM RESUME by setting the bit CTRLB.RESUME or
a L1 RESUME by setting the Send L1 Resume bit in CTRLB (CTRLB.L1RESUME). In the case of a L1
RESUME, the K STATE duration is given by the BESL bit field in the EXTREG.VARIABLE field. See
EXTREG.
When the host is in the L1 SLEEP state after a successful LPM transmitted, the device can initiate an
UPSTREAM RESUME. This will set the Upstream Resume Interrupt bit in INTFLAG (INTFLAG.UPRSM).
The host should proceed then to a L1 RESUME as described above.
After resuming from the L1 SLEEP state, the bit CTRLB.SOFE is set, allowing Start-of-Frame generation.
© 2017 Microchip Technology Inc.
Datasheet Complete
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SAM DA1
34.6.3.17 Host Interrupt
Figure 34-10. Host Interrupt
PINTFLAG7.STALL
PINTENSET.STALL
PINTFLAG7.PERR
PINTENSET.PERR
PINTFLAG7.TRFAIL
PINTENSET.TRFAIL
PIPE7
PINTFLAG7.TXSTP
PINTSMRY
PINT7
PINTENSET.TXSTP
PINT6
PINTFLAG7.TRCPT1
PINTENSET.TRCPT1
PINTFLAG7.TRCPT0
PINTENSET.TRCPT0
USB PIPE
Interrupt
PINTFLAG0.STALL
PINTENSET.STALL
PINTFLAG0.PERR
PINTENSET.PERR
PINTFLAG0.TRFAIL
PINTENSET.TRFAIL
PINTFLAG0.TXSTP
PIPE0
PINT1
PINT0
PINTENSET.TXSTP
PINTFLAG0.TRCPT1
PINTENSET.TRCPT1
PINTFLAG0.TRCPT0
USB
Interrupt
PINTENSET.TRCPT0
INTFLAG.DDISC *
INTENSET.DDISC
INTFLAG.DCONN *
INTENSET.DCONN
INTFLAG.RAMACER
INTFLAGA
INTENSET.RAMACER
INTFLAG.UPRSM
USB Host Interrupt
INTENSET.UPRSM
INTFLAG.DNRSM
INTENSET.DNRSM
INTFLAG.WAKEUP *
INTENSET.WAKEUP
INTFLAG.RST
INTENSET.RST
INTFLAG.HSOF
INTENSET.HSOF
* Asynchronous interrupt
The WAKEUP is an asynchronous interrupt and can be used to wake-up the device from any sleep mode.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 670
SAM DA1
34.7
Register Summary
The register mapping depends on the Operating Mode field in the Control A register (CTRLA.MODE).
The register summary is detailed below.
34.7.1
Common Device Summary
Offset
Name
Bit Pos.
0x00
CTRLA
7:0
0x01
Reserved
0x02
SYNCBUSY
7:0
0x03
QOSCTRL
7:0
0x0D
FSMSTATUS
7:0
0x24
0x25
0x26
DESCADD
0x27
0x28
0x29
34.7.2
PADCAL
MODE
RUNSTBY
DQOS[1:0]
ENABLE
SWRST
ENABLE
SWRST
CQOS[1:0]
FSMSTATE[6:0]
7:0
DESCADD[7:0]
15:8
DESCADD[15:8]
23:16
DESCADD[23:16]
31:24
DESCADD[31:24]
7:0
TRANSN[1:0]
15:8
TRANSP[4:0]
TRIM[2:0]
TRANSN[4:2]
Device Summary
Table 34-1. General Device Registers
Offset
Name
0x04
Reserved
0x05
Reserved
0x06
Reserved
0x07
Reserved
0x08
0x09
CTRLB
0x0A
DADD
0x0B
Reserved
0x0C
STATUS
0x0E
Reserved
0x0F
Reserved
0x10
0x11
0x12
0x14
0x15
FNUM
INTENCLR
Reserved
0x17
Reserved
0x19
INTENSET
0x1A
Reserved
0x1B
Reserved
0x1C
0x1D
7:0
NREPLY
15:8
ADDEN
7:0
SPDCONF[1:0]
UPRSM
LPMHDSK[1:0]
GNAK
DETACH
DADD[6:0]
LINESTATE[1:0]
7:0
SPEED[1:0]
FNUM[4:0]
15:8
FNCERR
7:0
RAMACER
FNUM[10:5]
Reserved
0x16
0x18
Bit Pos.
INTFLAG
UPRSM
EORSM
WAKEUP
EORST
SOF
15:8
7:0
LPMSUSP
RAMACER
UPRSM
EORSM
WAKEUP
EORST
SOF
15:8
7:0
SUSPEND
SUSPEND
LPMSUSP
RAMACER
UPRSM
EORSM
WAKEUP
EORST
15:8
© 2017 Microchip Technology Inc.
SOF
LPMNYET
SUSPEND
LPMSUSP
Datasheet Complete
LPMNYET
LPMNYET
40001895A-page 671
SAM DA1
Offset
Name
0x1E
Reserved
0x1F
Reserved
0x20
0x21
EPINTSMRY
0x22
Reserved
0x23
Reserved
Bit Pos.
7:0
EPINT[7:0]
15:8
EPINT[15:8]
Table 34-2. Device Endpoint Register n
Offset
Name
Bit Pos.
0x1m0
EPCFGn
7:0
0x1m1
Reserved
0x1m2
Reserved
EPTYPE1[1:0]
EPTYPE0[1:0]
0x1m3
Reserved
0x1m4
EPSTATUSCLRn
7:0
BK1RDY
BK0RDY
STALLRQ1
STALLRQ0
CURBK
DTGLIN
DTGLOUT
0x1m5
EPSTATUSSETn
7:0
BK1RDY
BK0RDY
STALLRQ1
STALLRQ0
CURBK
DTGLIN
DTGLOUT
0x1m6
EPSTATUSn
7:0
BK1RDY
BK0RDY
STALLRQ1
STALLRQ0
CURBK
DTGLIN
DTGLOUT
0x1m7
EPINTFLAGn
7:0
STALL1
STALL0
RXSTP
TRFAIL1
TRFAIL0
TRCPT1
TRCPT0
0x1m8
EPINTENCLRn
7:0
STALL1
STALL0
RXSTP
TRFAIL1
TRFAIL0
TRCPT1
TRCPT0
0x1m9
EPINTENSETn
7:0
STALL1
STALL0
RXSTP
TRFAIL1
TRFAIL0
TRCPT1
TRCPT0
0x1mA
Reserved
0x1mB
Reserved
Table 34-3. Device Endpoint n Descriptor Bank 0
Offset
Name
Bit Pos.
0x n0 +
index
0x00
7:0
ADD[7:0]
0x01
15:8
ADD[15:8]
23:16
ADD[23:16]
0x02
ADDR
0x03
31:24
ADD[31:24]
0x04
7:0
BYTE_COUNT[7:0]
0x05
0x06
PCKSIZE
15:8
0x07
31:24
0x08
7:0
0x09
EXTREG
MULTI_PACKET_SIZE[1:0]
BYTE_COUNT[13:8]
23:16
MULTI_PACKET_SIZE[9:2]
AUTO_ZLP
15:8
0x0A
STATUS_BK
7:0
0x0B
Reserved
7:0
0x0C
Reserved
7:0
0x0D
Reserved
7:0
0x0E
Reserved
7:0
0x0F
Reserved
7:0
© 2017 Microchip Technology Inc.
SIZE[2:0]
MULTI_PACKET_SIZE[13:10]
VARIABLE[3:0]
SUBPID[3:0]
VARIABLE[10:4]
ERRORFLOW
Datasheet Complete
CRCERR
40001895A-page 672
SAM DA1
Table 34-4. Device Endpoint n Descriptor Bank 1
Offset
Name
Bit Pos.
0x n0 +
0x10 +
index
0x00
0x01
0x02
7:0
ADDR
ADD[7:0]
15:8
ADD[15:8]
23:16
ADD[23:16]
0x03
31:24
ADD[31:24]
0x04
7:0
BYTE_COUNT[7:0]
0x05
0x06
PCKSIZE
0x07
0x08
15:8
BYTE_COUNT[13:8]
23:16
31:24
Reserved
7:0
0x09
Reserved
15:8
0x0A
STATUS_BK
7:0
0x0B
Reserved
7:0
0x0C
Reserved
7:0
0x0D
Reserved
7:0
0x0E
Reserved
7:0
0x0F
Reserved
7:0
34.7.3
MULTI_PACKET_SIZE[1:0]
MULTI_PACKET_SIZE[9:2]
AUTO_ZLP
SIZE[2:0]
MULTI_PACKET_SIZE[13:10]
ERRORFLOW
CRCERR
Host Summary
Table 34-5. General Host Registers
Offset
Name
0x04
Reserved
0x05
Reserved
0x06
Reserved
0x07
Reserved
0x08
0x09
CTRLB
0x0A
HSOFC
0x0B
Reserved
0x0C
STATUS
0x0E
Reserved
0x0F
Reserved
0x10
0x11
0x12
0x14
0x15
FNUM
FLENHIGH
INTENCLR
0x16
Reserved
0x17
Reserved
0x18
0x19
0x1A
INTENSET
Bit Pos.
7:0
TSTK
TSTJ
SPDCONF[1:0]
15:8
7:0
7:0
L1RESUME
FLENCE
LINESTATE[1:0]
SOFE
SPEED[1:0]
FNUM[4:0]
15:8
FNUM[10:5]
7:0
FLENHIGH[7:0]
RAMACER
UPRSM
DNRSM
WAKEUP
RST
HSOF
15:8
7:0
BUSRESET
FLENC[3:0]
7:0
7:0
RESUME
VBUSOK
RAMACER
UPRSM
DNRSM
WAKEUP
15:8
RST
DDISC
DCONN
DDISC
DCONN
HSOF
Reserved
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40001895A-page 673
SAM DA1
Offset
Name
0x1B
Reserved
0x1C
0x1D
INTFLAG
0x1E
Reserved
0x1F
Reserved
0x20
0x21
0x22
PINTSMRY
Bit Pos.
7:0
RAMACER
UPRSM
DNRSM
WAKEUP
RST
HSOF
15:8
DDISC
7:0
PINT[7:0]
15:8
PINT[15:8]
DCONN
Reserved
0x23
Table 34-6. Host Pipe Register n
Offset
Name
Bit Pos.
0x1m0
PCFGn
7:0
0x1m1
Reserved
PTYPE[2:0]
BK
PTOKEN[1:0]
0x1m2
Reserved
0x1m3
BINTERVAL
7:0
0x1m4
PSTATUSCLRn
7:0
BK1RDY
BK0RDY
PFREEZE
CURBK
DTGL
0x1m5
PSTATUSETn
7:0
BK1RDY
BK0RDY
PFREEZE
CURBK
DTGL
0x1m6
PSTATUSn
7:0
BK1RDY
BK0RDY
PFREEZE
CURBK
DTGL
BINTERVAL[7:0]
0x1m7
PINTFLAGn
7:0
STALL
TXSTP
PERR
TRFAIL
TRCPT1
TRCPT0
0x1m8
PINTENCLRn
7:0
STALL
TXSTP
PERR
TRFAIL
TRCPT1
TRCPT0
0x1m9
PINTENSETn
7:0
STALL
TXSTP
PERR
TRFAIL
TRCPT1
TRCPT0
0x1mA
Reserved
0x1mB
Reserved
Table 34-7. Host Pipe n Descriptor Bank 0
Offset
Name
Bit Pos.
0x n0 +
index
0x00
7:0
ADD[7:0]
0x01
15:8
ADD[15:8]
23:16
ADD[23:16]
31:24
ADD[31:24]
0x02
ADDR
0x03
0x04
7:0
0x05
15:8
0x06
PCKSIZE
31:24
0x08
7:0
0x0A
EXTREG
STATUS_BK
0x0B
0x0C
0x0D
0x0E
0x0F
BYTE_COUNT[13:8]
23:16
0x07
0x09
BYTE_COUNT[7:0]
MULTI_PACKET_SIZE[1:0]
MULTI_PACKET_SIZE[9:2]
AUTO_ZLP
SIZE[2:0]
MULTI_PACKET_SIZE[13:10]
VARIABLE[3:0]
SUBPID[3:0]
15:8
VARIABLE[10:4]
7:0
ERRORFLOW
CRCERR
15:8
CTRL_PIPE
STATUS_PIPE
7:0
15:8
7:0
PDADDR[6:0]
PEPMAX[3:0]
ERCNT[2:0]
PEPNUM[3:0]
CRC16ER
TOUTER
PIDER
DAPIDER
DTGLER
15:8
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SAM DA1
Table 34-8. Host Pipe n Descriptor Bank 1
Offset
Name
Bit Pos.
0x n0
+0x10
+index
0x00
0x01
0x02
7:0
ADDR
ADD[7:0]
15:8
ADD[15:8]
23:16
ADD[23:16]
0x03
31:24
ADD[31:24]
0x04
7:0
BYTE_COUNT[7:0]
0x05
0x06
PCKSIZE
15:8
31:24
0x08
7:0
0x09
0x0B
MULTI_PACKET_SIZE[13:10]
ERRORFLOW
CRCERR
DAPIDER
DTGLER
15:8
7:0
15:8
34.8
SIZE[2:0]
7:0
0x0D
0x0F
MULTI_PACKET_SIZE[9:2]
AUTO_ZLP
15:8
STATUS_BK
0x0C
0x0E
BYTE_COUNT[13:8]
23:16
0x07
0x0A
MULTI_PACKET_SIZE[1:0
STATUS_PIPE
7:0
ERCNT[2:0]
CRC16ER
TOUTER
PIDER
15:8
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition,
the 8-bit quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the
"Read-Synchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled.
Enable-protection is denoted by the "Enable-Protected" property in each individual register description.
Refer to the Register Access Protection, PAC - Peripheral Access Controller and GCLK Synchronization
for details.
Related Links
PAC - Peripheral Access Controller
34.8.1
Communication Device Host Registers
34.8.1.1 Control A
Name: CTRLA
Offset: 0x00 [ID-0000306e]
Reset: 0x00
Property: PAC Write-Protection, Write-Synchronised
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SAM DA1
Bit
Access
Reset
2
1
0
MODE
7
6
5
4
3
RUNSTDBY
ENABLE
SWRST
R/W
R/W
R/W
R/W
0
0
0
0
Bit 7 – MODE: Operating Mode
This bit defines the operating mode of the USB.
Value
0
1
Description
USB Device mode
USB Host mode
Bit 2 – RUNSTDBY: Run in Standby Mode
This bit is Enable-Protected.
Value
0
1
Description
USB clock is stopped in standby mode.
USB clock is running in standby mode
Bit 1 – ENABLE: Enable
Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/
disabled. The value written to CTRLA.ENABLE will read back immediately and the Synchronization status
enable bit in the Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE
will be cleared when the operation is complete.
This bit is Write-Synchronized.
Value
0
1
Description
The peripheral is disabled or being disabled.
The peripheral is enabled or being enabled.
Bit 0 – SWRST: Software Reset
Writing a zero to this bit has no effect.
Writing a '1' to this bit resets all registers in the USB, to their initial state, and the USB will be disabled.
Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same
write-operation will be discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete.
CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.
This bit is Write-Synchronized.
Value
0
1
Description
There is no reset operation ongoing.
The reset operation is ongoing.
34.8.1.2 Synchronization Busy
Name: SYNCBUSY
Offset: 0x02 [ID-0000306e]
Reset: 0x00
Property:
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SAM DA1
Bit
7
6
5
4
3
2
1
0
ENABLE
SWRST
Access
R
R
Reset
0
0
Bit 1 – ENABLE: Synchronization Enable status bit
This bit is cleared when the synchronization of ENABLE register between the clock domains is complete.
This bit is set when the synchronization of ENABLE register between clock domains is started.
Bit 0 – SWRST: Synchronization Software Reset status bit
This bit is cleared when the synchronization of SWRST register between the clock domains is complete.
This bit is set when the synchronization of SWRST register between clock domains is started.
34.8.1.3 QOS Control
Name: QOSCTRL
Offset: 0x03 [ID-0000306e]
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
1
R/W
R/W
DQOS[1:0]
Access
R/W
0
CQOS[1:0]
R/W
Reset
Bits 3:2 – DQOS[1:0]: Data Quality of Service
These bits define the memory priority access during the endpoint or pipe read/write data operation. Refer
to SRAM Quality of Service.
Bits 1:0 – CQOS[1:0]: Configuration Quality of Service
These bits define the memory priority access during the endpoint or pipe read/write configuration
operation. Refer to SRAM Quality of Service.
34.8.1.4 Finite State Machine Status
Name: FSMSTATUS
Offset: 0x0D [ID-0000306e]
Reset: 0xXXXX
Property: Read only
Bit
7
6
5
4
3
2
1
0
FSMSTATE[6:0]
Access
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
1
Bits 6:0 – FSMSTATE[6:0]: Fine State Machine Status
These bits indicate the state of the finite state machine of the USB controller.
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Value
0x01
0x02
0x04
0x08
0x10
0x20
0x40
Others
Name
OFF (L3)
ON (L0)
SUSPEND (L2)
SLEEP (L1)
DNRESUME
UPRESUME
RESET
Description
Corresponds to the powered-off, disconnected, and disabled state.
Corresponds to the Idle and Active states.
Down Stream Resume.
Up Stream Resume.
USB lines Reset.
Reserved
34.8.1.5 Descriptor Address
Name: DESCADD
Offset: 0x24 [ID-0000306e]
Reset: 0x00000000
Property: PAC Write-Protection
Bit
31
30
29
28
27
26
25
24
DESCADD[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
DESCADD[23:16]
Access
DESCADD[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
DESCADD[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:0 – DESCADD[31:0]: Descriptor Address Value
These bits define the base address of the main USB descriptor in RAM. The two least significant bits
must be written to zero.
34.8.1.6 Pad Calibration
The Pad Calibration values must be loaded from the NVM Software Calibration Area into the USB Pad
Calibration register by software, before enabling the USB, to achieve the specified accuracy.
Refer to NVM Software Calibration Area Mapping for further details.
Refer to for further details.
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SAM DA1
Name: PADCAL
Offset: 0x28 [ID-0000306e]
Reset: 0x0000
Property: PAC Write-Protection
Bit
15
14
13
12
11
10
TRIM[2:0]
Access
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
6
5
4
2
1
0
7
3
TRANSN[1:0]
Access
Reset
8
R/W
Reset
Bit
9
TRANSN[4:2]
TRANSP[4:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
9
8
Bits 14:12 – TRIM[2:0]: Trim bits for DP/DM
These bits calibrate the matching of rise/fall of DP/DM.
Bits 10:6 – TRANSN[4:0]: Trimmable Output Driver Impedance N
These bits calibrate the NMOS output impedance of DP/DM drivers.
Bits 4:0 – TRANSP[4:0]: Trimmable Output Driver Impedance P
These bits calibrate the PMOS output impedance of DP/DM drivers.
34.8.2
Device Registers - Common
34.8.2.1 Control B
Name: CTRLB
Offset: 0x08 [ID-0000306e]
Reset: 0x0000
Property: PAC Write-Protection
Bit
15
14
13
12
11
10
LPMHDSK[1:0]
Access
Reset
Bit
7
6
5
4
NREPLY
GNAK
R/W
R/W
R/W
0
0
0
3
2
SPDCONF[1:0]
1
0
UPRSM
DETACH
Access
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
Bits 11:10 – LPMHDSK[1:0]: Link Power Management Handshake
These bits select the Link Power Management Handshake configuration.
Value
0x0
0x1
0x2
Description
No handshake. LPM is not supported.
ACK
NYET
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SAM DA1
Value
0x3
Description
Reserved
Bit 9 – GNAK: Global NAK
This bit configures the operating mode of the NAK.
This bit is not synchronized.
Value
0
1
Description
The handshake packet reports the status of the USB transaction
A NAK handshake is answered for each USB transaction regardless of the current endpoint
memory bank status
Bit 4 – NREPLY: No reply excepted SETUP Token
This bit is cleared by hardware when receiving a SETUP packet.
This bit has no effect for any other endpoint but endpoint 0.
Value
0
1
Description
Disable the “NO_REPLY” feature: Any transaction to endpoint 0 will be handled according to
the USB2.0 standard.
Enable the “NO_REPLY” feature: Any transaction to endpoint 0 will be ignored except
SETUP.
Bits 3:2 – SPDCONF[1:0]: Speed Configuration
These bits select the speed configuration.
Value
0x0
0x1
0x2
0x3
Description
FS: Full-speed
LS: Low-speed
Reserved
Reserved
Bit 1 – UPRSM: Upstream Resume
This bit is cleared when the USB receives a USB reset or once the upstream resume has been sent.
Value
0
1
Description
Writing a zero to this bit has no effect.
Writing a one to this bit will generate an upstream resume to the host for a remote wakeup.
Bit 0 – DETACH: Detach
Value
0
1
Description
The device is attached to the USB bus so that communications may occur.
It is the default value at reset. The internal device pull-ups are disabled, removing the device
from the USB bus.
34.8.2.2 Device Address
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SAM DA1
Name: DADD
Offset: 0x0A [ID-0000306e]
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
ADDEN
Access
Reset
2
1
0
DADD[6:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 7 – ADDEN: Device Address Enable
This bit is cleared when a USB reset is received.
Value
0
Description
Writing a zero will deactivate the DADD field (USB device address) and return the device to
default address 0.
Writing a one will activate the DADD field (USB device address).
1
Bits 6:0 – DADD[6:0]: Device Address
These bits define the device address. The DADD register is reset when a USB reset is received.
34.8.2.3 Status
Name: STATUS
Offset: 0x0C [ID-0000306e]
Reset: 0x40
Property:
Bit
7
6
5
4
3
LINESTATE[1:0]
2
1
0
SPEED[1:0]
Access
R
R
R/W
R/W
Reset
0
1
0
1
Bits 7:6 – LINESTATE[1:0]: USB Line State Status
These bits define the current line state DP/DM.
LINESTATE[1:0]
USB Line Status
0x0
SE0/RESET
0x1
FS-J or LS-K State
0x2
FS-K or LS-J State
Bits 3:2 – SPEED[1:0]: Speed Status
These bits define the current speed used of the device
.
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SAM DA1
SPEED[1:0]
SPEED STATUS
0x0
Low-speed mode
0x1
Full-speed mode
0x2
Reserved
0x3
Reserved
34.8.2.4 Device Frame Number
Name: FNUM
Offset: 0x10 [ID-0000306e]
Reset: 0x0000
Property: Read only
Bit
15
14
13
12
11
FNCERR
Access
10
9
8
FNUM[10:5]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
FNUM[4:0]
Access
Reset
MFNUM[2:0]
Bit 15 – FNCERR: Frame Number CRC Error
This bit is cleared upon receiving a USB reset.
This bit is set when a corrupted frame number (or micro-frame number) is received.
This bit and the SOF (or MSOF) interrupt bit are updated at the same time.
Bits 13:3 – FNUM[10:0]: Frame Number
These bits are cleared upon receiving a USB reset.
These bits are updated with the frame number information as provided from the last SOF packet even if a
corrupted SOF is received.
Bits 2:0 – MFNUM[2:0]: Micro Frame Number
These bits are cleared upon receiving a USB reset or at the beginning of each Start-of-Frame (SOF
interrupt).
These bits are updated with the micro-frame number information as provided from the last MSOF packet
even if a corrupted MSOF is received.
34.8.2.5 Device Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
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SAM DA1
Name: INTENCLR
Offset: 0x14 [ID-0000306e]
Reset: 0x0000
Property: PAC Write-Protection
Bit
15
14
13
12
11
10
Access
Reset
Bit
Access
Reset
9
8
LPMSUSP
LPMNYET
R/W
R/W
0
0
7
6
5
4
3
2
RAMACER
UPRSM
EORSM
WAKEUP
EORST
SOF
1
SUSPEND
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Bit 9 – LPMSUSP: Link Power Management Suspend Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Link Power Management Suspend Interrupt Enable bit and disable
the corresponding interrupt request.
Value
0
1
Description
The Link Power Management Suspend interrupt is disabled.
The Link Power Management Suspend interrupt is enabled and an interrupt request will be
generated when the Link Power Management Suspend interrupt Flag is set.
Bit 8 – LPMNYET: Link Power Management Not Yet Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Link Power Management Not Yet interrupt Enable bit and disable the
corresponding interrupt request.
Value
0
1
Description
The Link Power Management Not Yet interrupt is disabled.
The Link Power Management Not Yet interrupt is enabled and an interrupt request will be
generated when the Link Power Management Not Yet interrupt Flag is set.
Bit 7 – RAMACER: RAM Access Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the RAM Access interrupt Enable bit and disable the corresponding
interrupt request.
Value
0
1
Description
The RAM Access interrupt is disabled.
The RAM Access interrupt is enabled and an interrupt request will be generated when the
RAM Access interrupt Flag is set.
Bit 6 – UPRSM: Upstream Resume Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Upstream Resume interrupt Enable bit and disable the
corresponding interrupt request.
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SAM DA1
Value
0
1
Description
The Upstream Resume interrupt is disabled.
The Upstream Resume interrupt is enabled and an interrupt request will be generated when
the Upstream Resume interrupt Flag is set.
Bit 5 – EORSM: End Of Resume Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the End Of Resume interrupt Enable bit and disable the corresponding
interrupt request.
Value
0
1
Description
The End Of Resume interrupt is disabled.
The End Of Resume interrupt is enabled and an interrupt request will be generated when the
End Of Resume interrupt Flag is set.
Bit 4 – WAKEUP: Wake-Up Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Wake Up interrupt Enable bit and disable the corresponding interrupt
request.
Value
0
1
Description
The Wake Up interrupt is disabled.
The Wake Up interrupt is enabled and an interrupt request will be generated when the Wake
Up interrupt Flag is set.
Bit 3 – EORST: End of Reset Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the End of Reset interrupt Enable bit and disable the corresponding
interrupt request.
Value
0
1
Description
The End of Reset interrupt is disabled.
The End of Reset interrupt is enabled and an interrupt request will be generated when the
End of Reset interrupt Flag is set.
Bit 2 – SOF: Start-of-Frame Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Start-of-Frame interrupt Enable bit and disable the corresponding
interrupt request.
Value
0
1
Description
The Start-of-Frame interrupt is disabled.
The Start-of-Frame interrupt is enabled and an interrupt request will be generated when the
Start-of-Frame interrupt Flag is set.
Bit 0 – SUSPEND: Suspend Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Suspend Interrupt Enable bit and disable the corresponding interrupt
request.
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SAM DA1
Value
0
1
Description
The Suspend interrupt is disabled.
The Suspend interrupt is enabled and an interrupt request will be generated when the
Suspend interrupt Flag is set.
34.8.2.6 Device Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name: INTENSET
Offset: 0x18 [ID-0000306e]
Reset: 0x0000
Property: PAC Write-Protection
Bit
15
14
13
12
11
10
Access
Reset
Bit
Access
Reset
9
8
LPMSUSP
LPMNYET
R/W
R/W
0
0
7
6
5
4
3
2
RAMACER
UPRSM
EORSM
WAKEUP
EORST
SOF
1
SUSPEND
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Bit 9 – LPMSUSP: Link Power Management Suspend Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Link Power Management Suspend Enable bit and enable the
corresponding interrupt request.
Value
0
1
Description
The Link Power Management Suspend interrupt is disabled.
The Link Power Management Suspend interrupt is enabled.
Bit 8 – LPMNYET: Link Power Management Not Yet Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Link Power Management Not Yet interrupt bit and enable the
corresponding interrupt request.
Value
0
1
Description
The Link Power Management Not Yet interrupt is disabled.
The Link Power Management Not Yet interrupt is enabled.
Bit 7 – RAMACER: RAM Access Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the RAM Access Enable bit and enable the corresponding interrupt
request.
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SAM DA1
Value
0
1
Description
The RAM Access interrupt is disabled.
The RAM Access interrupt is enabled.
Bit 6 – UPRSM: Upstream Resume Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Upstream Resume Enable bit and enable the corresponding interrupt
request.
Value
0
1
Description
The Upstream Resume interrupt is disabled.
The Upstream Resume interrupt is enabled.
Bit 5 – EORSM: End Of Resume Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the End Of Resume interrupt Enable bit and enable the corresponding
interrupt request.
Value
0
1
Description
The End Of Resume interrupt is disabled.
The End Of Resume interrupt is enabled.
Bit 4 – WAKEUP: Wake-Up Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Wake Up interrupt Enable bit and enable the corresponding interrupt
request.
Value
0
1
Description
The Wake Up interrupt is disabled.
The Wake Up interrupt is enabled.
Bit 3 – EORST: End of Reset Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the End of Reset interrupt Enable bit and enable the corresponding
interrupt request.
Value
0
1
Description
The End of Reset interrupt is disabled.
The End of Reset interrupt is enabled.
Bit 2 – SOF: Start-of-Frame Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Start-of-Frame interrupt Enable bit and enable the corresponding
interrupt request.
Value
0
1
Description
The Start-of-Frame interrupt is disabled.
The Start-of-Frame interrupt is enabled.
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SAM DA1
Bit 0 – SUSPEND: Suspend Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Suspend interrupt Enable bit and enable the corresponding interrupt
request.
Value
0
1
Description
The Suspend interrupt is disabled.
The Suspend interrupt is enabled.
34.8.2.7 Device Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x01C [ID-0000306e]
Reset: 0x0000
Property:
Bit
15
14
13
12
11
10
Access
Reset
Bit
Access
Reset
9
8
LPMSUSP
LPMNYET
R/W
R/W
0
0
1
0
7
6
5
4
3
2
RAMACER
UPRSM
EORSM
WAKEUP
EORST
SOF
SUSPEND
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Bit 9 – LPMSUSP: Link Power Management Suspend Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB module acknowledge a Link Power Management Transaction (ACK
handshake) and has entered the Suspended state and will generate an interrupt if INTENCLR/
SET.LPMSUSP is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the LPMSUSP Interrupt Flag.
Bit 8 – LPMNYET: Link Power Management Not Yet Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB module acknowledges a Link Power Management Transaction (handshake
is NYET) and will generate an interrupt if INTENCLR/SET.LPMNYET is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the LPMNYET Interrupt Flag.
Bit 7 – RAMACER: RAM Access Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a RAM access underflow error occurs during IN data stage. This bit will generate an
interrupt if INTENCLR/SET.RAMACER is one.
Writing a zero to this bit has no effect.
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Bit 6 – UPRSM: Upstream Resume Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB sends a resume signal called “Upstream Resume” and will generate an
interrupt if INTENCLR/SET.UPRSM is one.
Writing a zero to this bit has no effect.
Bit 5 – EORSM: End Of Resume Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB detects a valid “End of Resume” signal initiated by the host and will
generate an interrupt if INTENCLR/SET.EORSM is one.
Writing a zero to this bit has no effect.
Bit 4 – WAKEUP: Wake Up Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB is reactivated by a filtered non-idle signal from the lines and will generate
an interrupt if INTENCLR/SET.WAKEUP is one.
Writing a zero to this bit has no effect.
Bit 3 – EORST: End of Reset Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a USB “End of Reset” has been detected and will generate an interrupt if
INTENCLR/SET.EORST is one.
Writing a zero to this bit has no effect.
Bit 2 – SOF: Start-of-Frame Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a USB “Start-of-Frame” has been detected (every 1 ms) and will generate an
interrupt if INTENCLR/SET.SOF is one.
The FNUM is updated. In High Speed mode, the MFNUM register is cleared.
Writing a zero to this bit has no effect.
Bit 0 – SUSPEND: Suspend Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a USB “Suspend” idle state has been detected for 3 frame periods (J state for 3 ms)
and will generate an interrupt if INTENCLR/SET.SUSPEND is one.
Writing a zero to this bit has no effect.
34.8.2.8 Endpoint Interrupt Summary
Name: EPINTSMRY
Offset: 0x20 [ID-0000306e]
Reset: 0x0000
Property:
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Bit
15
14
13
12
11
10
9
8
EPINT[15:8]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
EPINT[7:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bits 15:0 – EPINT[15:0]: EndPoint Interrupt
The flag EPINT[n] is set when an interrupt is triggered by the EndPoint n. See EPINTFLAGn register in
the device EndPoint section.
This bit will be cleared when no interrupts are pending for EndPoint n.
34.8.3
Device Registers - Endpoint
34.8.3.1 Device Endpoint Configuration register n
Name: EPCFGn
Offset: 0x100 + (n x 0x20) [ID-0000306e]
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
EPTYPE1[2:0]
Access
Reset
1
0
EPTYPE0[2:0]
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bits 6:4 – EPTYPE1[2:0]: Endpoint Type for IN direction
These bits contains the endpoint type for IN direction.
Upon receiving a USB reset EPCFGn.EPTYPE1 is cleared except for endpoint 0 which is unchanged.
Value
0x0
0x1
0x2
0x3
0x4
0x5
Description
Bank1 is disabled.
Bank1 is enabled and configured as Control IN.
Bank1 is enabled and configured as Isochronous IN.
Bank1 is enabled and configured as Bulk IN.
Bank1 is enabled and configured as Interrupt IN.
Bank1 is enabled and configured as Dual-Bank OUT
0x6-0x7
(Endpoint type is the same as the one defined in EPTYPE0)
Reserved
Bits 2:0 – EPTYPE0[2:0]: Endpoint Type for OUT direction
These bits contains the endpoint type for OUT direction.
Upon receiving a USB reset EPCFGn.EPTYPE0 is cleared except for endpoint 0 which is unchanged.
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Value
0x0
0x1
0x2
0x3
0x4
0x5
Description
Bank0 is disabled.
Bank0 is enabled and configured as Control SETUP / Control OUT.
Bank0 is enabled and configured as Isochronous OUT.
Bank0 is enabled and configured as Bulk OUT.
Bank0 is enabled and configured as Interrupt OUT.
Bank0 is enabled and configured as Dual Bank IN
0x6-0x7
(Endpoint type is the same as the one defined in EPTYPE1)
Reserved
34.8.3.2 EndPoint Status Clear n
Name: EPSTATUSCLRn
Offset: 0x104 + (n * 0x20) [ID-0000306e]
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
BK1RDY
BK0RDY
STALLRQ1
STALLRQ0
CURBK
DTGLIN
DTGLOUT
Access
W
W
W
W
W
W
W
Reset
0
0
0
0
0
0
0
Bit 7 – BK1RDY: Bank 1 Ready Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.BK1RDY bit.
Bit 6 – BK0RDY: Bank 0 Ready Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.BK0RDY bit.
Bit 5 – STALLRQ1: STALL bank 1 Request Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.STALLRQ1 bit.
Bit 4 – STALLRQ0: STALL bank 0 Request Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.STALLRQ0 bit.
Bit 2 – CURBK: Current Bank Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.CURBK bit.
Bit 1 – DTGLIN: Data Toggle IN Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.DTGLIN bit.
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Bit 0 – DTGLOUT: Data Toggle OUT Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the EPSTATUS.DTGLOUT bit.
34.8.3.3 EndPoint Status Set n
Name: EPSTATUSSETn
Offset: 0x105 + (n x 0x20) [ID-0000306e]
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
BK1RDY
BK0RDY
STALLRQ1
STALLRQ0
CURBK
DTGLIN
DTGLOUT
Access
W
W
W
W
W
W
W
Reset
0
0
0
0
0
0
0
Bit 7 – BK1RDY: Bank 1 Ready Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.BK1RDY bit.
Bit 6 – BK0RDY: Bank 0 Ready Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.BK0RDY bit.
Bit 5 – STALLRQ1: STALL Request bank 1 Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.STALLRQ1 bit.
Bit 4 – STALLRQ0: STALL Request bank 0 Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.STALLRQ0 bit.
Bit 2 – CURBK: Current Bank Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.CURBK bit.
Bit 1 – DTGLIN: Data Toggle IN Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.DTGLIN bit.
Bit 0 – DTGLOUT: Data Toggle OUT Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set the EPSTATUS.DTGLOUT bit.
34.8.3.4 EndPoint Status n
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Name: EPSTATUSn
Offset: 0x106 + (n x 0x20) [ID-0000306e]
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
2
1
0
BK1RDY
BK0RDY
5
STALLRQ
4
3
CURBK
DTGLIN
DTGLOUT
Access
R
R
R
R
R
R
Reset
0
0
2
0
0
0
Bit 7 – BK1RDY: Bank 1 is ready
For Control/OUT direction Endpoints, the bank is empty.
Writing a one to the bit EPSTATUSCLR.BK1RDY will clear this bit.
Writing a one to the bit EPSTATUSSET.BK1RDY will set this bit.
Value
0
1
Description
The bank number 1 is not ready : For IN direction Endpoints, the bank is not yet filled in.
The bank number 1 is ready: For IN direction Endpoints, the bank is filled in. For
Control/OUT direction Endpoints, the bank is full.
Bit 6 – BK0RDY: Bank 0 is ready
Writing a one to the bit EPSTATUSCLR.BK0RDY will clear this bit.
Writing a one to the bit EPSTATUSSET.BK0RDY will set this bit.
Value
0
1
Description
The bank number 0 is not ready : For IN direction Endpoints, the bank is not yet filled in. For
Control/OUT direction Endpoints, the bank is empty.
The bank number 0 is ready: For IN direction Endpoints, the bank is filled in. For
Control/OUT direction Endpoints, the bank is full.
Bit 4 – STALLRQ: STALL bank x request
Writing a zero to the bit EPSTATUSCLR.STALLRQ will clear this bit.
Writing a one to the bit EPSTATUSSET.STALLRQ will set this bit.
This bit is cleared by hardware when receiving a SETUP packet.
Value
0
1
Description
Disable STALLRQx feature.
Enable STALLRQx feature: a STALL handshake will be sent to the host in regards to bank x.
Bit 2 – CURBK: Current Bank
Writing a zero to the bit EPSTATUSCLR.CURBK will clear this bit.
Writing a one to the bit EPSTATUSSET.CURBK will set this bit.
Value
0
1
Description
The bank0 is the bank that will be used in the next single/multi USB packet.
The bank1 is the bank that will be used in the next single/multi USB packet.
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Bit 1 – DTGLIN: Data Toggle IN Sequence
Writing a zero to the bit EPSTATUSCLR.DTGLINCLR will clear this bit.
Writing a one to the bit EPSTATUSSET.DTGLINSET will set this bit.
Value
0
1
Description
The PID of the next expected IN transaction will be zero: data 0.
The PID of the next expected IN transaction will be one: data 1.
Bit 0 – DTGLOUT: Data Toggle OUT Sequence
Writing a zero to the bit EPSTATUSCLR.DTGLOUTCLR will clear this bit.
Writing a one to the bit EPSTATUSSET.DTGLOUTSET will set this bit.
Value
0
1
Description
The PID of the next expected OUT transaction will be zero: data 0.
The PID of the next expected OUR transaction will be one: data 1.
34.8.3.5 Device EndPoint Interrupt Flag n
Name: EPINTFLAGn
Offset: 0x107 + (n x 0x20) [ID-0000306e]
Reset: 0x00
Property:
Bit
7
6
Access
Reset
5
4
3
2
1
0
STALL
RXSTP
TRFAIL
TRCPT
R/W
R/W
R/W
R/W
2
0
2
2
Bit 5 – STALL: Transmit Stall x Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Transmit Stall occurs and will generate an interrupt if EPINTENCLR/SET.STALL is
one.
EPINTFLAG.STALL is set for a single bank OUT endpoint or double bank IN/OUT endpoint when current
bank is "0".
Writing a zero to this bit has no effect.
Writing a one to this bit clears the STALL Interrupt Flag.
Bit 4 – RXSTP: Received Setup Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Received Setup occurs and will generate an interrupt if EPINTENCLR/SET.RXSTP
is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the RXSTP Interrupt Flag.
Bit 2 – TRFAIL: Transfer Fail x Interrupt Flag
This flag is cleared by writing a one to the flag.
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This flag is set when a transfer fail occurs and will generate an interrupt if EPINTENCLR/SET.TRFAIL is
one.
EPINTFLAG.TRFAIL is set for a single bank OUT endpoint or double bank IN/OUT endpoint when current
bank is "0".
Writing a zero to this bit has no effect.
Writing a one to this bit clears the TRFAIL Interrupt Flag.
Bit 0 – TRCPT: Transfer Complete x interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Transfer complete occurs and will generate an interrupt if EPINTENCLR/
SET.TRCPT is one. EPINTFLAG.TRCPT is set for a single bank OUT endpoint or double bank IN/OUT
endpoint when current bank is "0".
Writing a zero to this bit has no effect.
Writing a one to this bit clears the TRCPT0 Interrupt Flag.
34.8.3.6 Device EndPoint Interrupt Enable n
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Endpoint Interrupt Enable Set (EPINTENSET) register.
Name: EPINTENCLRn
Offset: 0x108 + (n x 0x20) [ID-0000306e]
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
Access
Reset
5
4
STALL
RXSTP
3
TRFAIL
2
1
TRCPT
0
R/W
R/W
R/W
R/W
2
0
2
2
Bit 5 – STALL: Transmit STALL x Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transmit Stall x Interrupt Enable bit and disable the corresponding
interrupt request.
Value
0
1
Description
The Transmit Stall x interrupt is disabled.
The Transmit Stall x interrupt is enabled and an interrupt request will be generated when the
Transmit Stall x Interrupt Flag is set.
Bit 4 – RXSTP: Received Setup Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Received Setup Interrupt Enable bit and disable the corresponding
interrupt request.
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SAM DA1
Value
0
1
Description
The Received Setup interrupt is disabled.
The Received Setup interrupt is enabled and an interrupt request will be generated when the
Received Setup Interrupt Flag is set.
Bit 2 – TRFAIL: Transfer Fail x Interrupt Enable
The user should look into the descriptor table status located in ram to be informed about the error
condition : ERRORFLOW, CRC.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Fail x Interrupt Enable bit and disable the corresponding
interrupt request.
Value
0
1
Description
The Transfer Fail bank x interrupt is disabled.
The Transfer Fail bank x interrupt is enabled and an interrupt request will be generated when
the Transfer Fail x Interrupt Flag is set.
Bit 0 – TRCPT: Transfer Complete x interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Complete x interrupt Enable bit and disable the
corresponding interrupt request.
Value
0
1
Description
The Transfer Complete bank x interrupt is disabled.
The Transfer Complete bank x interrupt is enabled and an interrupt request will be generated
when the Transfer Complete x Interrupt Flag is set.
34.8.3.7 Device Interrupt EndPoint Set n
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Endpoint Interrupt Enable Set (EPINTENCLR) register. This
register is cleared by USB reset or when EPEN[n] is zero.
Name: EPINTENSETn
Offset: 0x109 + (n x 0x20) [ID-0000306e]
Reset: 0x0000
Property: PAC Write-Protection
Bit
7
6
Access
Reset
5
4
3
2
1
0
STALL
RXSTP
TRFAIL
TRCPT
R/W
R/W
R/W
R/W
2
0
2
2
Bit 5 – STALL: Transmit Stall x Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transmit bank x Stall interrupt.
Value
0
1
Description
The Transmit Stall x interrupt is disabled.
The Transmit Stall x interrupt is enabled.
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SAM DA1
Bit 4 – RXSTP: Received Setup Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Received Setup interrupt.
Value
0
1
Description
The Received Setup interrupt is disabled.
The Received Setup interrupt is enabled.
Bit 2 – TRFAIL: Transfer Fail bank x Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Fail interrupt.
Value
0
1
Description
The Transfer Fail interrupt is disabled.
The Transfer Fail interrupt is enabled.
Bit 0 – TRCPT: Transfer Complete bank x interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Complete x interrupt.
0.2.4 Device Registers - Endpoint RAM
Value
0
1
Description
The Transfer Complete bank x interrupt is disabled.
The Transfer Complete bank x interrupt is enabled.
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34.8.4
Device Registers - Endpoint RAM
34.8.4.1 Endpoint Descriptor Structure
Data Buffers
EPn BK1
EPn BK0
Endpoint
descriptors
Reserved
Bank1
Reserved
PCKSIZE
ADDR
(2 x 0xn0) + 0x10
Reserved
STATUS_BK
Bank0
EXTREG
PCKSIZE
ADDR
2 x 0xn0
Reserved
+0x01B
+0x01A
+0x018
+0x014
+0x010
+0x00B
+0x00A
+0x008
+0x004
+0x000
STATUS_BK
Descriptor E0
Bank1
Reserved
PCKSIZE
ADDR
Bank0
Reserved
STATUS_BK
EXTREG
PCKSIZE
ADDR
Growing Memory Addresses
Descriptor En
STATUS_BK
DESCADD
34.8.4.2 Address of Data Buffer
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Name: ADDR
Offset: 0x00 & 0x10 [ID-0000306e]
Reset: 0xxxxxxxx
Property: NA
Bit
31
30
29
28
27
26
25
24
ADDR[31:24]
Access
Reset
Bit
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
x
x
x
x
x
x
x
23
22
21
20
19
18
17
16
ADDR[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
x
x
x
x
x
x
x
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
x
x
x
x
x
x
x
x
Bit
7
6
5
4
3
2
1
0
Reset
Bit
ADDR[15:8]
Access
ADDR[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
x
x
x
x
x
x
x
Bits 31:0 – ADDR[31:0]: Data Pointer Address Value
These bits define the data pointer address as an absolute word address in RAM. The two least significant
bits must be zero to ensure the start address is 32-bit aligned.
34.8.4.3 Packet Size
Name: PCKSIZE
Offset: 0x04 & 0x14 [ID-0000306e]
Reset: 0xxxxxxxxx
Property: NA
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Bit
31
30
AUTO_ZLP
Access
Reset
Bit
29
28
27
SIZE[2:0]
26
25
24
MULTI_PACKET_SIZE[13:10]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
0
0
x
0
0
0
0
23
22
21
20
19
18
17
16
MULTI_PACKET_SIZE[9:2]
Access
Reset
Bit
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
MULTI_PACKET_SIZE[1:0]
Access
BYTE_COUNT[13:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
x
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
x
BYTE_COUNT[7:0]
Access
Reset
Bit 31 – AUTO_ZLP: Automatic Zero Length Packet
This bit defines the automatic Zero Length Packet mode of the endpoint.
When enabled, the USB module will manage the ZLP handshake by hardware. This bit is for IN endpoints
only. When disabled the handshake should be managed by firmware.
Value
0
1
Description
Automatic Zero Length Packet is disabled.
Automatic Zero Length Packet is enabled.
Bits 30:28 – SIZE[2:0]: Endpoint size
These bits contains the maximum packet size of the endpoint.
Value
Description
0x0
8 Byte
0x1
16 Byte
0x2
32 Byte
0x3
64 Byte
0x4
128 Byte(1)
0x5
256 Byte(1)
0x6
512 Byte(1)
0x7
1023 Byte(1)
(1) for Isochronous endpoints only.
Bits 27:14 – MULTI_PACKET_SIZE[13:0]: Multiple Packet Size
These bits define the 14-bit value that is used for multi-packet transfers.
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For IN endpoints, MULTI_PACKET_SIZE holds the total number of bytes sent. MULTI_PACKET_SIZE
should be written to zero when setting up a new transfer.
For OUT endpoints, MULTI_PACKET_SIZE holds the total data size for the complete transfer. This value
must be a multiple of the maximum packet size.
Bits 13:0 – BYTE_COUNT[13:0]: Byte Count
These bits define the 14-bit value that is used for the byte count.
For IN endpoints, BYTE_COUNT holds the number of bytes to be sent in the next IN transaction.
For OUT endpoint or SETUP endpoints, BYTE_COUNT holds the number of bytes received upon the last
OUT or SETUP transaction.
34.8.4.4 Extended Register
Name: EXTREG
Offset: 0x08 [ID-0000306e]
Reset: 0xxxxxxxx
Property: NA
Bit
15
14
13
12
11
10
9
8
VARIABLE[10:4]
Access
Reset
Bit
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
6
5
4
3
2
1
0
VARIABLE[3:0]
Access
Reset
SUBPID[3:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
x
0
0
0
x
Bits 14:4 – VARIABLE[10:0]: Variable field send with extended token
These bits define the VARIABLE field of a received extended token. These bits are updated when the
USB has answered by an handshake token ACK to a LPM transaction. See Section 2.1.1 Protocol
Extension Token in the reference document “ENGINEERING CHANGE NOTICE, USB 2.0 Link Power
Management Addendum”.
To support the USB2.0 Link Power Management addition the VARIABLE field should be read as
described below.
VARIABLES
Description
VARIABLE[3:0]
bLinkState (1)
VARIABLE[7:4]
BESL (2)
VARIABLE[8]
bRemoteWake (1)
VARIABLE[10:9]
Reserved
1.
For a definition of LPM Token bRemoteWake and bLinkState fields, refer to "Table 2-3 in the
reference document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management
Addendum".
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2.
For a definition of LPM Token BESL field, refer to "Table 2-3 in the reference document
ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum" and "Table XX1 in Errata for ECN USB 2.0 Link Power Management.
Bits 3:0 – SUBPID[3:0]: SUBPID field send with extended token
These bits define the SUBPID field of a received extended token. These bits are updated when the USB
has answered by an handshake token ACK to a LPM transaction. See Section 2.1.1 Protocol Extension
Token in the reference document “ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management
Addendum”.
34.8.4.5 Device Status Bank
Name: STATUS_BK
Offset: 0x0A & 0x1A [ID-0000306e]
Reset: 0xxxxxxxx
Property: NA
Bit
7
6
5
4
3
Access
Reset
2
1
0
ERRORFLOW
CRCERR
R/W
R/W
x
x
Bit 1 – ERRORFLOW: Error Flow Status
This bit defines the Error Flow Status.
This bit is set when a Error Flow has been detected during transfer from/towards this bank.
For OUT transfer, a NAK handshake has been sent.
For Isochronous OUT transfer, an overrun condition has occurred.
For IN transfer, this bit is not valid. EPSTATUS.TRFAIL0 and EPSTATUS.TRFAIL1 should reflect the flow
errors.
Value
0
1
Description
No Error Flow detected.
A Error Flow has been detected.
Bit 0 – CRCERR: CRC Error
This bit defines the CRC Error Status.
This bit is set when a CRC error has been detected in an isochronous OUT endpoint bank.
0.2.5 Host Registers - Common
Value
0
1
34.8.5
Description
No CRC Error.
CRC Error detected.
Host Registers - Common
34.8.5.1 Control B
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Name: CTRLB
Offset: 0x08 [ID-0000306e]
Reset: 0x0000
Property: PAC Write-Protection
Bit
15
14
13
12
Access
Reset
Bit
7
6
5
4
11
10
9
8
L1RESUME
VBUSOK
BUSRESET
SOFE
R/W
R/W
R/W
R/W
0
0
0
0
3
2
1
0
SPDCONF[1:0]
Access
Reset
RESUME
R/W
R/W
R/W
0
0
0
Bit 11 – L1RESUME: Send USB L1 Resume
Writing 0 to this bit has no effect.
1: Generates a USB L1 Resume on the USB bus. This bit should only be set when the Start-of-Frame
generation is enabled (SOFE bit set). The duration of the USB L1 Resume is defined by the
EXTREG.VARIABLE[7:4] bits field also known as BESL (See LPM ECN).See also EXTREG Register.
This bit is cleared when the USB L1 Resume has been sent or when a USB reset is requested.
Bit 10 – VBUSOK: VBUS is OK
This notifies the USB HOST that USB operations can be started. When this bit is zero and even if the
USB HOST is configured and enabled, HOST operation is halted. Setting this bit will allow HOST
operation when the USB is configured and enabled.
Value
0
1
Description
The USB module is notified that the VBUS on the USB line is not powered.
The USB module is notified that the VBUS on the USB line is powered.
Bit 9 – BUSRESET: Send USB Reset
Value
0
1
Description
Reset generation is disabled. It is written to zero when the USB reset is completed or when a
device disconnection is detected. Writing zero has no effect.
Generates a USB Reset on the USB bus.
Bit 8 – SOFE: Start-of-Frame Generation Enable
Value
0
1
Description
The SOF generation is disabled and the USB bus is in suspend state.
Generates SOF on the USB bus in full speed and keep it alive in low speed mode. This bit is
automatically set at the end of a USB reset (INTFLAG.RST) or at the end of a downstream
resume (INTFLAG.DNRSM) or at the end of L1 resume.
Bits 3:2 – SPDCONF[1:0]: Speed Configuration for Host
These bits select the host speed configuration as shown below
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Value
0x0
0x1
0x2
0x3
Description
Low and Full Speed capable
Reserved
Reserved
Reserved
Bit 1 – RESUME: Send USB Resume
Writing 0 to this bit has no effect.
1: Generates a USB Resume on the USB bus.
This bit is cleared when the USB Resume has been sent or when a USB reset is requested.
34.8.5.2 Host Start-of-Frame Control
During a very short period just before transmitting a Start-of-Frame, this register is locked. Thus, after
writing, it is recommended to check the register value, and write this register again if necessary. This
register is cleared upon a USB reset.
Name: HSOFC
Offset: 0x0A [ID-0000306e]
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
FLENCE
Access
Reset
1
0
FLENC[3:0]
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Bit 7 – FLENCE: Frame Length Control Enable
When this bit is '1', the time between Start-of-Frames can be tuned by up to +/-0.06% using FLENC[3:0].
Note: In Low Speed mode, FLENCE must be '0'.
Value
0
1
Description
Start-of-Frame is generated every 1ms.
Start-of-Frame generation depends on the signed value of FLENC[3:0].
USB Start-of-Frame period equals 1ms + (FLENC[3:0]/12000)ms
Bits 3:0 – FLENC[3:0]: Frame Length Control
These bits define the signed value of the 4-bit FLENC that is added to the Internal Frame Length when
FLENCE is '1'. The internal Frame length is the top value of the frame counter when FLENCE is zero.
34.8.5.3 Status
Name: STATUS
Offset: 0x0C [ID-0000306e]
Reset: 0x00
Property: Read only
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Bit
7
6
5
4
3
2
LINESTATE[1:0]
1
0
10
9
8
SPEED[1:0]
Access
R
R
R/W
R/W
Reset
0
0
0
0
Bits 7:6 – LINESTATE[1:0]: USB Line State Status
These bits define the current line state DP/DM.
LINESTATE[1:0]
USB Line Status
0x0
SE0/RESET
0x1
FS-J or LS-K State
0x2
FS-K or LS-J State
Bits 3:2 – SPEED[1:0]: Speed Status
These bits define the current speed used by the host.
SPEED[1:0]
Speed Status
0x0
Full-speed mode
0x1
Low-speed mode
0x2
Reserved
0x3
Reserved
34.8.5.4 Host Frame Number
Name: FNUM
Offset: 0x10 [ID-0000306e]
Reset: 0x0000
Property: PAC Write-Protection
Bit
15
14
13
12
11
FNUM[10:5]
Access
Reset
Bit
7
6
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
5
4
3
2
1
0
FNUM[4:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Bits 13:3 – FNUM[10:0]: Frame Number
These bits contains the current SOF number.
These bits can be written by software to initialize a new frame number value. In this case, at the next
SOF, the FNUM field takes its new value.
As the FNUM register lies across two consecutive byte addresses, writing byte-wise (8-bits) to the FNUM
register may produce incorrect frame number generation. It is recommended to write FNUM register
word-wise (32-bits) or half-word-wise (16-bits).
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34.8.5.5 Host Frame Length
Name: FLENHIGH
Offset: 0x12 [ID-0000306e]
Reset: 0x00
Property: Read-Only
Bit
7
6
5
4
Access
R
R
R
R
Reset
0
0
0
0
3
2
1
0
R
R
R
R
0
0
0
0
FLENHIGH[7:0]
Bits 7:0 – FLENHIGH[7:0]: Frame Length
These bits contains the 8 high-order bits of the internal frame counter.
Table 34-9. Counter Description vs. Speed
Host Register
Description
STATUS.SPEED
Full Speed
With a USB clock running at 12MHz, counter length is 12000 to ensure a SOF
generation every 1 ms.
34.8.5.6 Host Interrupt Enable Register Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Name: INTENCLR
Offset: 0x14 [ID-0000306e]
Reset: 0x0000
Property: PAC Write-Protection
Bit
15
14
13
12
11
10
Access
Reset
Bit
Access
Reset
7
6
5
4
3
2
RAMACER
UPRSM
DNRSM
WAKEUP
RST
HSOF
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
9
8
DDISC
DCONN
R/W
R/W
0
0
1
0
Bit 9 – DDISC: Device Disconnection Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Device Disconnection interrupt Enable bit and disable the
corresponding interrupt request.
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Value
0
1
Description
The Device Disconnection interrupt is disabled.
The Device Disconnection interrupt is enabled and an interrupt request will be generated
when the Device Disconnection interrupt Flag is set.
Bit 8 – DCONN: Device Connection Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Device Connection interrupt Enable bit and disable the
corresponding interrupt request.
Value
0
1
Description
The Device Connection interrupt is disabled.
The Device Connection interrupt is enabled and an interrupt request will be generated when
the Device Connection interrupt Flag is set.
Bit 7 – RAMACER: RAM Access Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the RAM Access interrupt Enable bit and disable the corresponding
interrupt request.
Value
0
1
Description
The RAM Access interrupt is disabled.
The RAM Access interrupt is enabled and an interrupt request will be generated when the
RAM Access interrupt Flag is set.
Bit 6 – UPRSM: Upstream Resume from Device Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Upstream Resume interrupt Enable bit and disable the
corresponding interrupt request.
Value
0
1
Description
The Upstream Resume interrupt is disabled.
The Upstream Resume interrupt is enabled and an interrupt request will be generated when
the Upstream Resume interrupt Flag is set.
Bit 5 – DNRSM: Down Resume Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Down Resume interrupt Enable bit and disable the corresponding
interrupt request.
Value
0
1
Description
The Down Resume interrupt is disabled.
The Down Resume interrupt is enabled and an interrupt request will be generated when the
Down Resume interrupt Flag is set.
Bit 4 – WAKEUP: Wake Up Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Wake Up interrupt Enable bit and disable the corresponding interrupt
request.
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Value
0
1
Description
The Wake Up interrupt is disabled.
The Wake Up interrupt is enabled and an interrupt request will be generated when the Wake
Up interrupt Flag is set.
Bit 3 – RST: BUS Reset Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Bus Reset interrupt Enable bit and disable the corresponding
interrupt request.
Value
0
1
Description
The Bus Reset interrupt is disabled.
The Bus Reset interrupt is enabled and an interrupt request will be generated when the Bus
Reset interrupt Flag is set.
Bit 2 – HSOF: Host Start-of-Frame Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Host Start-of-Frame interrupt Enable bit and disable the
corresponding interrupt request.
Value
0
1
Description
The Host Start-of-Frame interrupt is disabled.
The Host Start-of-Frame interrupt is enabled and an interrupt request will be generated when
the Host Start-of-Frame interrupt Flag is set.
34.8.5.7 Host Interrupt Enable Register Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name: INTENSET
Offset: 0x18 [ID-0000306e]
Reset: 0x0000
Property: PAC Write-Protection
Bit
15
14
13
12
11
10
Access
Reset
Bit
Access
Reset
7
6
5
4
3
2
RAMACER
UPRSM
DNRSM
WAKEUP
RST
HSOF
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
9
8
DDISC
DCONN
R/W
R/W
0
0
1
0
Bit 9 – DDISC: Device Disconnection Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Device Disconnection interrupt bit and enable the DDSIC interrupt.
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Value
0
1
Description
The Device Disconnection interrupt is disabled.
The Device Disconnection interrupt is enabled.
Bit 8 – DCONN: Device Connection Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Device Connection interrupt bit and enable the DCONN interrupt.
Value
0
1
Description
The Device Connection interrupt is disabled.
The Device Connection interrupt is enabled.
Bit 7 – RAMACER: RAM Access Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the RAM Access interrupt bit and enable the RAMACER interrupt.
Value
0
1
Description
The RAM Access interrupt is disabled.
The RAM Access interrupt is enabled.
Bit 6 – UPRSM: Upstream Resume from the device Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Upstream Resume interrupt bit and enable the UPRSM interrupt.
Value
0
1
Description
The Upstream Resume interrupt is disabled.
The Upstream Resume interrupt is enabled.
Bit 5 – DNRSM: Down Resume Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Down Resume interrupt Enable bit and enable the DNRSM interrupt.
Value
0
1
Description
The Down Resume interrupt is disabled.
The Down Resume interrupt is enabled.
Bit 4 – WAKEUP: Wake Up Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Wake Up interrupt Enable bit and enable the WAKEUP interrupt
request.
Value
0
1
Description
The WakeUp interrupt is disabled.
The WakeUp interrupt is enabled.
Bit 3 – RST: Bus Reset Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Bus Reset interrupt Enable bit and enable the Bus RST interrupt.
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Value
0
1
Description
The Bus Reset interrupt is disabled.
The Bus Reset interrupt is enabled.
Bit 2 – HSOF: Host Start-of-Frame Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Host Start-of-Frame interrupt Enable bit and enable the HSOF
interrupt.
Value
0
1
Description
The Host Start-of-Frame interrupt is disabled.
The Host Start-of-Frame interrupt is enabled.
34.8.5.8 Host Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x1C [ID-0000306e]
Reset: 0x0000
Property:
Bit
15
14
13
12
11
10
Access
Reset
Bit
Access
Reset
7
6
5
4
3
2
RAMACER
UPRSM
DNRSM
WAKEUP
RST
HSOF
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
9
8
DDISC
DCONN
R/W
R/W
0
0
1
0
Bit 9 – DDISC: Device Disconnection Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the device has been removed from the USB Bus and will generate an interrupt if
INTENCLR/SET.DDISC is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DDISC Interrupt Flag.
Bit 8 – DCONN: Device Connection Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a new device has been connected to the USB BUS and will generate an interrupt if
INTENCLR/SET.DCONN is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DCONN Interrupt Flag.
Bit 7 – RAMACER: RAM Access Interrupt Flag
This flag is cleared by writing a one to the flag.
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This flag is set when a RAM access error occurs during an OUT stage and will generate an interrupt if
INTENCLR/SET.RAMACER is one.
Writing a zero to this bit has no effect.
Bit 6 – UPRSM: Upstream Resume from the Device Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB has received an Upstream Resume signal from the Device and will
generate an interrupt if INTENCLR/SET.UPRSM is one.
Writing a zero to this bit has no effect.
Bit 5 – DNRSM: Down Resume Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB has sent a Down Resume and will generate an interrupt if INTENCLR/
SET.DRSM is one.
Writing a zero to this bit has no effect.
Bit 4 – WAKEUP: Wake Up Interrupt Flag
This flag is cleared by writing a one.
This flag is set when:
l The host controller is in suspend mode (SOFE is zero) and an upstream resume from the device is
detected.
l The host controller is in suspend mode (SOFE is zero) and an device disconnection is detected.
l The host controller is in operational state (VBUSOK is one) and an device connection is detected.
In all cases it will generate an interrupt if INTENCLR/SET.WAKEUP is one.
Writing a zero to this bit has no effect.
Bit 3 – RST: Bus Reset Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Bus “Reset” has been sent to the Device and will generate an interrupt if
INTENCLR/SET.RST is one.
Writing a zero to this bit has no effect.
Bit 2 – HSOF: Host Start-of-Frame Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a USB “Host Start-of-Frame” in Full Speed/High Speed or a keep-alive in Low
Speed has been sent (every 1 ms) and will generate an interrupt if INTENCLR/SET.HSOF is one.
The value of the FNUM register is updated.
Writing a zero to this bit has no effect.
34.8.5.9 Pipe Interrupt Summary
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Name: PINTSMRY
Offset: 0x20 [ID-0000306e]
Reset: 0x0000
Property: Read-only
Bit
15
14
13
12
11
10
9
8
PINT[15:8]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PINT[7:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bits 15:0 – PINT[15:0]
The flag PINT[n] is set when an interrupt is triggered by the pipe n. See PINTFLAG register in the Host
Pipe Register section.
This bit will be cleared when there are no interrupts pending for Pipe n.
Writing to this bit has no effect.
34.8.6
Host Registers - Pipe
34.8.6.1 Host Pipe n Configuration
Name: PCFGn
Offset: 0x100 + (n x 0x20) [ID-0000306e]
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
PTYPE[2:0]
Access
Reset
1
BK
0
PTOKEN[1:0]
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bits 5:3 – PTYPE[2:0]: Type of the Pipe
These bits contains the pipe type.
PTYPE[2:0]
Description
0x0
Pipe is disabled
0x1
Pipe is enabled and configured as CONTROL
0x2
Pipe is enabled and configured as ISO
0x3
Pipe is enabled and configured as BULK
0x4
Pipe is enabled and configured as INTERRUPT
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PTYPE[2:0]
Description
0x5
Pipe is enabled and configured as EXTENDED
0x06-0x7
Reserved
These bits are cleared upon sending a USB reset.
Bit 2 – BK: Pipe Bank
This bit selects the number of banks for the pipe.
For control endpoints writing a zero to this bit is required as only Bank0 is used for Setup/In/Out
transactions.
This bit is cleared when a USB reset is sent.
BK(1)
Description
0x0
Single-bank endpoint
0x1
Dual-bank endpoint
1.
Bank field is ignored when PTYPE is configured as EXTENDED.
Value
0
1
Description
A single bank is used for the pipe.
A dual bank is used for the pipe.
Bits 1:0 – PTOKEN[1:0]: Pipe Token
These bits contains the pipe token.
PTOKEN[1:0](1)
Description
0x0
SETUP(2)
0x1
IN
0x2
OUT
0x3
Reserved
1.
2.
PTOKEN field is ignored when PTYPE is configured as EXTENDED.
Available only when PTYPE is configured as CONTROL
Theses bits are cleared upon sending a USB reset.
34.8.6.2 Interval for the Bulk-Out/Ping Transaction
Name: BINTERVAL
Offset: 0x103 + (n x 0x20) [ID-0000306e]
Reset: 0x00
Property: PAC Write-Protection
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Bit
7
6
5
4
3
2
1
0
BINTERVAL[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 7:0 – BINTERVAL[7:0]: BINTERVAL
These bits contains the Ping/Bulk-out period.
These bits are cleared when a USB reset is sent or when PEN[n] is zero.
BINTERVAL Description
=0
Multiple consecutive OUT token is sent in the same frame until it is acked by the
peripheral
>0
One OUT token is sent every BINTERVAL frame until it is acked by the peripheral
Depending from the type of pipe the desired period is defined as:
PTYPE
Description
Interrupt
1 ms to 255 ms
Isochronous
2^(Binterval) * 1 ms
Bulk or control
1 ms to 255 ms
EXT LPM
bInterval ignored. Always 1 ms when a NYET is received.
34.8.6.3 Pipe Status Clear n
Name: PSTATUSCLR
Offset: 0x104 + (n x 0x20) [ID-0000306e]
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
BK1RDY
BK0RDY
PFREEZE
CURBK
DTGL
Access
W
W
W
W
W
Reset
0
0
0
0
0
Bit 7 – BK1RDY: Bank 1 Ready Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear PSTATUS.BK1RDY bit.
Bit 6 – BK0RDY: Bank 0 Ready Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear PSTATUS.BK0RDY bit.
Bit 4 – PFREEZE: Pipe Freeze Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear PSTATUS.PFREEZE bit.
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Bit 2 – CURBK: Current Bank Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear PSTATUS.CURBK bit.
Bit 0 – DTGL: Data Toggle Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear PSTATUS.DTGL bit.
34.8.6.4 Pipe Status Set Register n
Name: PSTATUSSET
Offset: 0x105 + (n x 0x20) [ID-0000306e]
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
5
4
3
2
1
0
BK1RDY
BK0RDY
PFREEZE
CURBK
DTGL
Access
W
W
W
W
W
Reset
0
0
0
0
0
Bit 7 – BK1RDY: Bank 1 Ready Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set the bit PSTATUS.BK1RDY.
Bit 6 – BK0RDY: Bank 0 Ready Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set the bit PSTATUS.BK0RDY.
Bit 4 – PFREEZE: Pipe Freeze Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set PSTATUS.PFREEZE bit.
Bit 2 – CURBK: Current Bank Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set PSTATUS.CURBK bit.
Bit 0 – DTGL: Data Toggle Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set PSTATUS.DTGL bit.
34.8.6.5 Pipe Status Register n
Name: PSTATUS
Offset: 0x106 + (n x 0x20) [ID-0000306e]
Reset: 0x00
Property: PAC Write-Protection
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Bit
7
6
BK1RDY
BK0RDY
5
PFREEZE
4
3
CURBK
2
1
DTGL
0
Access
R
R
R
R
R
Reset
0
0
0
0
0
Bit 7 – BK1RDY: Bank 1 is ready
Writing a one to the bit EPSTATUSCLR.BK1RDY will clear this bit.
Writing a one to the bit EPSTATUSSET.BK1RDY will set this bit.
This bank is not used for Control pipe.
Value
0
1
Description
The bank number 1 is not ready: For IN the bank is empty. For Control/OUT the bank is not
yet fill in.
The bank number 1 is ready: For IN the bank is filled full. For Control/OUT the bank is filled
in.
Bit 6 – BK0RDY: Bank 0 is ready
Writing a one to the bit EPSTATUSCLR.BK0RDY will clear this bit.
Writing a one to the bit EPSTATUSSET.BK0RDY will set this bit.
This bank is the only one used for Control pipe.
Value
0
1
Description
The bank number 0 is not ready: For IN the bank is not empty. For Control/OUT the bank is
not yet fill in.
The bank number 0 is ready: For IN the bank is filled full. For Control/OUT the bank is filled
in.
Bit 4 – PFREEZE: Pipe Freeze
Writing a one to the bit EPSTATUSCLR.PFREEZE will clear this bit.
Writing a one to the bit EPSTATUSSET.PFREEZE will set this bit.
This bit is also set by the hardware:
•
When a STALL handshake has been received.
•
After a PIPE has been enabled (rising of bit PEN.N).
•
When an LPM transaction has completed whatever handshake is returned or the transaction was
timed-out.
•
When a pipe transfer was completed with a pipe error. See PINTFLAG register.
When PFREEZE bit is set while a transaction is in progress on the USB bus, this transaction will be
properly completed. PFREEZE bit will be read as “1” only when the ongoing transaction will have been
completed.
Value
0
1
Description
The Pipe operates in normal operation.
The Pipe is frozen and no additional requests will be sent to the device on this pipe address.
Bit 2 – CURBK: Current Bank
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SAM DA1
Value
0
1
Description
The bank0 is the bank that will be used in the next single/multi USB packet.
The bank1 is the bank that will be used in the next single/multi USB packet.
Bit 0 – DTGL: Data Toggle Sequence
Writing a one to the bit EPSTATUSCLR.DTGL will clear this bit.
Writing a one to the bit EPSTATUSSET.DTGL will set this bit.
This bit is toggled automatically by hardware after a data transaction.
This bit will reflect the data toggle in regards of the token type (IN/OUT/SETUP).
Value
0
1
Description
The PID of the next expected transaction will be zero: data 0.
The PID of the next expected transaction will be one: data 1.
34.8.6.6 Host Pipe Interrupt Flag Register
Name: PINTFLAG
Offset: 0x107 + (n x 0x20) [ID-0000306e]
Reset: 0x00
Property:
Bit
7
6
Access
Reset
5
4
3
2
1
0
STALL
TXSTP
PERR
TRFAIL
TRCPT
R/W
R/W
R/W
R/W
R/W
0
0
0
0
2
Bit 5 – STALL: STALL Received Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a stall occurs and will generate an interrupt if PINTENCLR/SET.STALL is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the STALL Interrupt Flag.
Bit 4 – TXSTP: Transmitted Setup Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Transfer Complete occurs and will generate an interrupt if PINTENCLR/
SET.TXSTP is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the TXSTP Interrupt Flag.
Bit 3 – PERR: Pipe Error Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a pipe error occurs and will generate an interrupt if PINTENCLR/SET.PERR is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the PERR Interrupt Flag.
© 2017 Microchip Technology Inc.
Datasheet Complete
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SAM DA1
Bit 2 – TRFAIL: Transfer Fail Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Transfer Fail occurs and will generate an interrupt if PINTENCLR/SET.TRFAIL is
one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the TRFAIL Interrupt Flag.
Bit 0 – TRCPT: Transfer Complete x interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Transfer complete occurs and will generate an interrupt if PINTENCLR/
SET.TRCPT is one. PINTFLAG.TRCPT is set for a single bank IN/OUT pipe or a double bank IN/OUT
pipe when current bank is 0.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the TRCPT Interrupt Flag.
34.8.6.7 Host Pipe Interrupt Clear Register
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Pipe Interrupt Enable Set (PINTENSET) register.
This register is cleared by USB reset or when PEN[n] is zero.
Name: PINTENCLR
Offset: 0x108 + (n x 0x20) [ID-0000306e]
Reset: 0x00
Property: PAC Write-Protection
Bit
7
6
Access
Reset
5
4
3
2
1
0
STALL
TXSTP
PERR
TRFAIL
TRCPT
R/W
R/W
R/W
R/W
R/W
0
0
0
0
2
Bit 5 – STALL: Received Stall Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Received Stall interrupt Enable bit and disable the corresponding
interrupt request.
Value
0
1
Description
The received Stall interrupt is disabled.
The received Stall interrupt is enabled and an interrupt request will be generated when the
received Stall interrupt Flag is set.
Bit 4 – TXSTP: Transmitted Setup Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transmitted Setup interrupt Enable bit and disable the corresponding
interrupt request.
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SAM DA1
Value
0
1
Description
The Transmitted Setup interrupt is disabled.
The Transmitted Setup interrupt is enabled and an interrupt request will be generated when
the Transmitted Setup interrupt Flag is set.
Bit 3 – PERR: Pipe Error Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Pipe Error interrupt Enable bit and disable the corresponding
interrupt request.
Value
0
1
Description
The Pipe Error interrupt is disabled.
The Pipe Error interrupt is enabled and an interrupt request will be generated when the Pipe
Error interrupt Flag is set.
Bit 2 – TRFAIL: Transfer Fail Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Fail interrupt Enable bit and disable the corresponding
interrupt request.
Value
0
1
Description
The Transfer Fail interrupt is disabled.
The Transfer Fail interrupt is enabled and an interrupt request will be generated when the
Transfer Fail interrupt Flag is set.
Bit 0 – TRCPT: Transfer Complete Bank x interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Complete interrupt Enable bit x and disable the
corresponding interrupt request.
Value
0
1
Description
The Transfer Complete Bank x interrupt is disabled.
The Transfer Complete Bank x interrupt is enabled and an interrupt request will be
generated when the Transfer Complete interrupt x Flag is set.
34.8.6.8 Host Interrupt Pipe Set Register
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes
in this register will also be reflected in the Pipe Interrupt Enable Set (PINTENCLR) register.
This register is cleared by USB reset or when PEN[n] is zero.
Name: PINTENSET
Offset: 0x109 + (n x 0x20) [ID-0000306e]
Reset: 0x00
Property: PAC Write-Protection
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 718
SAM DA1
Bit
7
6
Access
Reset
5
4
3
2
STALL
TXSTP
PERR
TRFAIL
1
TRCPT
0
R/W
R/W
R/W
R/W
R/W
0
0
0
0
2
Bit 5 – STALL: Stall Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Stall interrupt.
Value
0
1
Description
The Stall interrupt is disabled.
The Stall interrupt is enabled.
Bit 4 – TXSTP: Transmitted Setup Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transmitted Setup interrupt.
Value
0
1
Description
The Transmitted Setup interrupt is disabled.
The Transmitted Setup interrupt is enabled.
Bit 3 – PERR: Pipe Error Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Pipe Error interrupt.
Value
0
1
Description
The Pipe Error interrupt is disabled.
The Pipe Error interrupt is enabled.
Bit 2 – TRFAIL: Transfer Fail Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Fail interrupt.
Value
0
1
Description
The Transfer Fail interrupt is disabled.
The Transfer Fail interrupt is enabled.
Bit 0 – TRCPT: Transfer Complete x interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Complete interrupt Enable bit x.
0.2.7 Host Registers - Pipe RAM
Value
0
1
Description
The Transfer Complete x interrupt is disabled.
The Transfer Complete x interrupt is enabled.
© 2017 Microchip Technology Inc.
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40001895A-page 719
SAM DA1
34.8.7
Host Registers - Pipe RAM
34.8.7.1 Pipe Descriptor Structure
Data Buffers
Pn BK1
Pn BK0
Pipe descriptors
Reserved
STATUS _PIPE
Bank1
CTRL_BK
Reserved
Descriptor Pn
Reserved
PCKSIZE
ADDR
(2 x 0xn0) + 0x10
Reserved
STATUS _PIPE
Bank0
CTRL_PIPE
STATUS_BK
EXTREG
PCKSIZE
Reserved
STATUS _PIPE
Bank1
CTRL_BK
Reserved
Descriptor P0
Reserved
PCKSIZE
ADDR
Reserved
STATUS _PIPE
Bank0
CTRL_PIPE
STATUS_BK
EXTREG
PCKSIZE
ADDR
2 x 0xn0
+0x01F
+0x01E
+0x01C
+0x01A
+0x018
+0x014
+0x010
+0x00F
+0x00E
+0x00C
+0x00A
+0x008
+0x004
+0x000
Growing Memory Addresses
ADDR
DESCADD
34.8.7.2 Address of the Data Buffer
© 2017 Microchip Technology Inc.
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SAM DA1
Name: ADDR
Offset: 0x00 & 0x10 [ID-0000306e]
Reset: 0xxxxxxxx
Property: NA
Bit
31
30
29
28
27
26
25
24
ADDR[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
ADDR[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ADDR[15:8]
Access
ADDR[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
x
Bits 31:0 – ADDR[31:0]: Data Pointer Address Value
These bits define the data pointer address as an absolute double word address in RAM. The two least
significant bits must be zero to ensure the descriptor is 32-bit aligned.
34.8.7.3 Packet Size
Name: PCKSIZE
Offset: 0x04 & 0x14 [ID-0000306e]
Reset: 0xxxxxxxx
Property: NA
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 721
SAM DA1
Bit
31
30
AUTO_ZLP
Access
Reset
Bit
29
28
27
SIZE[2:0]
26
25
24
MULTI_PACKET_SIZE[13:10]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
x
0
0
x
0
0
0
0
23
22
21
20
19
18
17
16
MULTI_PACKET_SIZE[9:2]
Access
Reset
Bit
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
MULTI_PACKET_SIZE[1:0]
Access
BYTE_COUNT[5:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
x
0
0
0
0
0
x
Bit
7
6
5
4
3
2
1
0
Access
Reset
Bit 31 – AUTO_ZLP: Automatic Zero Length Packet
This bit defines the automatic Zero Length Packet mode of the pipe.
When enabled, the USB module will manage the ZLP handshake by hardware. This bit is for OUT pipes
only. When disabled the handshake should be managed by firmware.
Value
0
1
Description
Automatic Zero Length Packet is disabled.
Automatic Zero Length Packet is enabled.
Bits 30:28 – SIZE[2:0]: Pipe size
These bits contains the size of the pipe.
Theses bits are cleared upon sending a USB reset.
SIZE[2:0]
Description
0x0
8 Byte
0x1
16 Byte
0x2
32 Byte
0x3
64 Byte
0x4
128 Byte(1)
0x5
256 Byte(1)
0x6
512 Byte(1)
0x7
1024 Byte in HS mode(1)
1023 Byte in FS mode(1)
1. For Isochronous pipe only.
© 2017 Microchip Technology Inc.
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40001895A-page 722
SAM DA1
Bits 27:14 – MULTI_PACKET_SIZE[13:0]: Multi Packet IN or OUT size
These bits define the 14-bit value that is used for multi-packet transfers.
For IN pipes, MULTI_PACKET_SIZE holds the total number of bytes sent. MULTI_PACKET_SIZE should
be written to zero when setting up a new transfer.
For OUT pipes, MULTI_PACKET_SIZE holds the total data size for the complete transfer. This value must
be a multiple of the maximum packet size.
Bits 13:8 – BYTE_COUNT[5:0]: Byte Count
These bits define the 14-bit value that contains number of bytes sent in the last OUT or SETUP
transaction for an OUT pipe, or of the number of bytes to be received in the next IN transaction for an
input pipe.
34.8.7.4 Extended Register
Name: EXTREG
Offset: 0x08 [ID-0000306e]
Reset: 0xxxxxxxx
Property: NA
Bit
15
14
13
12
11
10
9
8
VARIABLE[10:4]
Access
Reset
Bit
7
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
6
5
4
3
2
1
0
VARIABLE[3:0]
Access
Reset
SUBPID[3:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
x
0
0
0
x
Bits 14:4 – VARIABLE[10:0]: Variable field send with extended token
These bits define the VARIABLE field sent with extended token. See “Section 2.1.1 Protocol Extension
Token in the reference document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management
Addendum.”
To support the USB2.0 Link Power Management addition the VARIABLE field should be set as described
below.
VARIABLE
Description
VARIABLE[3:0]
bLinkState(1)
VARIABLE[7:4]
BESL (See LPM ECN)(2)
VARIABLE[8]
bRemoteWake(1)
VARIABLE[10:9]
Reserved
(1) for a definition of LPM Token bRemoteWake and bLinkState fields, refer to "Table 2-3 in the reference
document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum"
(2) for a definition of LPM Token BESL field, refer to "Table 2-3 in the reference document ENGINEERING
CHANGE NOTICE, USB 2.0 Link Power Management Addendum" and "Table X-X1 in Errata for ECN USB 2.0
Link Power Management.
© 2017 Microchip Technology Inc.
Datasheet Complete
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SAM DA1
Bits 3:0 – SUBPID[3:0]: SUBPID field send with extended token
These bits define the SUBPID field sent with extended token. See “Section 2.1.1 Protocol Extension
Token in the reference document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management
Addendum”.
To support the USB2.0 Link Power Management addition the SUBPID field should be set as described in
“Table 2.2 SubPID Types in the reference document ENGINEERING CHANGE NOTICE, USB 2.0 Link
Power Management Addendum”.
34.8.7.5 Host Status Bank
Name: STATUS_BK
Offset: 0x0A & 0x1A [ID-0000306e]
Reset: 0xxxxxxxx
Property: NA
Bit
7
6
5
4
3
2
Access
Reset
1
0
ERRORFLOW
CRCERR
R/W
R/W
x
x
Bit 1 – ERRORFLOW: Error Flow Status
This bit defines the Error Flow Status.
This bit is set when a Error Flow has been detected during transfer from/towards this bank.
For IN transfer, a NAK handshake has been received. For OUT transfer, a NAK handshake has been
received. For Isochronous IN transfer, an overrun condition has occurred. For Isochronous OUT transfer,
an underflow condition has occurred.
Value
0
1
Description
No Error Flow detected.
A Error Flow has been detected.
Bit 0 – CRCERR: CRC Error
This bit defines the CRC Error Status.
This bit is set when a CRC error has been detected in an isochronous IN endpoint bank.
Value
0
1
Description
No CRC Error.
CRC Error detected.
34.8.7.6 Host Control Pipe
Name: CTRL_PIPE
Offset: 0x0C [ID-0000306e]
Reset: 0xXXXX
Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized
© 2017 Microchip Technology Inc.
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40001895A-page 724
SAM DA1
Bit
15
14
13
12
11
10
PERMAX[3:0]
Access
9
8
PEPNUM[3:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
x
0
0
0
x
Bit
7
6
5
4
3
2
1
0
PDADDR[6:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
x
Bits 15:12 – PERMAX[3:0]: Pipe Error Max Number
These bits define the maximum number of error for this Pipe before freezing the pipe automatically.
Bits 11:8 – PEPNUM[3:0]: Pipe EndPoint Number
These bits define the number of endpoint for this Pipe.
Bits 6:0 – PDADDR[6:0]: Pipe Device Address
These bits define the Device Address for this pipe.
34.8.7.7 Host Status Pipe
Name: STATUS_PIPE
Offset: 0x0E & 0x1E [ID-0000306e]
Reset: 0xxxxxxxx
Property: PAC Write-Protection, Write-Synchronized, Read-Synchronized
Bit
15
14
13
6
5
12
11
10
9
8
Access
Reset
Bit
7
ERCNT[2:0]
Access
Reset
4
3
2
1
0
CRC16ER
TOUTER
PIDER
DAPIDER
DTGLER
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
x
x
x
x
x
x
Bits 7:5 – ERCNT[2:0]: Pipe Error Counter
These bits define the number of errors detected on the pipe.
Bit 4 – CRC16ER: CRC16 ERROR
This bit defines the CRC16 Error Status.
This bit is set when a CRC 16 error has been detected during a IN transactions.
Value
0
1
Description
No CRC 16 Error detected.
A CRC 16 error has been detected.
Bit 3 – TOUTER: TIME OUT ERROR
This bit defines the Time Out Error Status.
This bit is set when a Time Out error has been detected during a USB transaction.
© 2017 Microchip Technology Inc.
Datasheet Complete
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SAM DA1
Value
0
1
Description
No Time Out Error detected.
A Time Out error has been detected.
Bit 2 – PIDER: PID ERROR
This bit defines the PID Error Status.
This bit is set when a PID error has been detected during a USB transaction.
Value
0
1
Description
No PID Error detected.
A PID error has been detected.
Bit 1 – DAPIDER: Data PID ERROR
This bit defines the PID Error Status.
This bit is set when a Data PID error has been detected during a USB transaction.
Value
0
1
Description
No Data PID Error detected.
A Data PID error has been detected.
Bit 0 – DTGLER: Data Toggle Error
This bit defines the Data Toggle Error Status.
This bit is set when a Data Toggle Error has been detected.
Value
0
1
Description
No Data Toggle Error.
Data Toggle Error detected.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 726
SAM DA1
35.
ADC – Analog-to-Digital Converter
35.1
Overview
The Analog-to-Digital Converter (ADC) converts analog signals to digital values. The ADC has 12-bit
resolution, and is capable of converting up to 350ksps. The input selection is flexible, and both differential
and single-ended measurements can be performed. An optional gain stage is available to increase the
dynamic range. In addition, several internal signal inputs are available. The ADC can provide both signed
and unsigned results.
ADC measurements can be started by either application software or an incoming event from another
peripheral in the device. ADC measurements can be started with predictable timing, and without software
intervention.
Both internal and external reference voltages can be used.
An integrated temperature sensor is available for use with the ADC. The bandgap voltage as well as the
scaled I/O and core voltages can also be measured by the ADC.
The ADC has a compare function for accurate monitoring of user-defined thresholds, with minimum
software intervention required.
The ADC may be configured for 8-, 10- or 12-bit results, reducing the conversion time. ADC conversion
results are provided left- or right-adjusted, which eases calculation when the result is represented as a
signed value. It is possible to use DMA to move ADC results directly to memory or peripherals when
conversions are done.
35.2
Features
•
•
•
•
•
•
•
•
•
8-, 10- or 12-bit resolution
Up to 350,000 samples per second (350ksps)
Differential and single-ended inputs
– Up to 32 analog input
– 25 positive and 10 negative, including internal and external
Five internal inputs
– Bandgap
– Temperature sensor
– DAC
– Scaled core supply
– Scaled I/O supply
1/2x to 16x gain
Single, continuous and pin-scan conversion options
Windowing monitor with selectable channel
Conversion range:
– Vref [1v to VDDANA - 0.6V]
– ADCx * GAIN [0V to -Vref ]
Built-in internal reference and external reference options
– Four bits for reference selection
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 727
SAM DA1
•
•
•
•
•
35.3
Event-triggered conversion for accurate timing (one event input)
Optional DMA transfer of conversion result
Hardware gain and offset compensation
Averaging and oversampling with decimation to support, up to 16-bit result
Selectable sampling time
Block Diagram
Figure 35-1. ADC Block Diagram
CTRLA
WINCTRL
AVGCTRL
WINLT
SAMPCTRL
WINUT
EVCTRL
OFFSETCORR
SWTRIG
GAINCORR
INPUTCTRL
ADC0
...
ADCn
INT.SIG
ADC
POST
PROCESSING
RESULT
ADC0
...
ADCn
INT.SIG
INT1V
CTRLB
INTVCC
VREFA
VREFB
PRESCALER
REFCTRL
35.4
Signal Description
Signal Name
Type
Description
VREFA
Analog input
External reference voltage A
VREFB
Analog input
External reference voltage B
ADC[19..0](1)
Analog input
Analog input channels
Note: Refer to Configuration Summary for details on exact number of analog input channels.
Note: Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral.
One signal can be mapped on several pins.
Related Links
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 728
SAM DA1
I/O Multiplexing and Considerations
35.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
35.5.1
I/O Lines
Using the ADC's I/O lines requires the I/O pins to be configured using the port configuration (PORT).
Related Links
PORT - I/O Pin Controller
35.5.2
Power Management
The ADC will continue to operate in any sleep mode where the selected source clock is running. The
ADC’s interrupts can be used to wake up the device from sleep modes. Events connected to the event
system can trigger other operations in the system without exiting sleep modes.
Related Links
PM – Power Manager
35.5.3
Clocks
The ADC bus clock (CLK_APB_ADCx) can be enabled in the Main Clock, which also defines the default
state.
The ADC requires a generic clock (GCLK_ADC). This clock must be configured and enabled in the
Generic Clock Controller (GCLK) before using the ADC.
A generic clock is asynchronous to the bus clock. Due to this asynchronicity, writes to certain registers will
require synchronization between the clock domains. Refer to Synchronization for further details.
Related Links
Peripheral Clock Masking
GCLK - Generic Clock Controller
35.5.4
DMA
The DMA request line is connected to the DMA Controller (DMAC). Using the ADC DMA requests
requires the DMA Controller to be configured first.
Related Links
DMAC – Direct Memory Access Controller
35.5.5
Interrupts
The interrupt request line is connected to the interrupt controller. Using the ADC interrupt requires the
interrupt controller to be configured first.
Related Links
Nested Vector Interrupt Controller
35.5.6
Events
The events are connected to the Event System.
Related Links
EVSYS – Event System
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 729
SAM DA1
35.5.7
Debug Operation
When the CPU is halted in debug mode the ADC will halt normal operation. The ADC can be forced to
continue operation during debugging.
35.5.8
Register Access Protection
All registers with write-access are optionally write-protected by the peripheral access controller (PAC),
except the following register:
•
Interrupt Flag Status and Clear (INTFLAG) register
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC WriteProtection" property in each individual register description.
PAC write-protection does not apply to accesses through an external debugger.
Related Links
PAC - Peripheral Access Controller
35.5.9
Analog Connections
I/O-pins AIN0 to AIN19 as well as the VREFA/VREFB reference voltage pin are analog inputs to the ADC.
35.5.10 Calibration
The BIAS and LINEARITY calibration values from the production test must be loaded from the NVM
Software Calibration Area into the ADC Calibration register (CALIB) by software to achieve specified
accuracy.
Related Links
NVM Software Calibration Area Mapping
35.6
Functional Description
35.6.1
Principle of Operation
By default, the ADC provides results with 12-bit resolution. 8-bit or 10-bit results can be selected in order
to reduce the conversion time.
The ADC has an oversampling with decimation option that can extend the resolution to 16 bits. The input
values can be either internal (e.g., internal temperature sensor) or external (connected I/O pins). The user
can also configure whether the conversion should be single-ended or differential.
35.6.2
Basic Operation
35.6.2.1 Initialization
Before enabling the ADC, the asynchronous clock source must be selected and enabled, and the ADC
reference must be configured. The first conversion after the reference is changed must not be used. All
other configuration registers must be stable during the conversion. The source for GCLK_ADC is selected
and enabled in the System Controller (SYSCTRL). Refer to SYSCTRL – System Controller for more
details.
When GCLK_ADC is enabled, the ADC can be enabled by writing a one to the Enable bit in the Control
Register A (CTRLA.ENABLE).
Related Links
SYSCTRL – System Controller
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 730
SAM DA1
35.6.2.2 Enabling, Disabling and Reset
The ADC is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The
ADC is disabled by writing CTRLA.ENABLE=0. The ADC is reset by writing a '1' to the Software Reset bit
in the Control A register (CTRLA.SWRST). All registers in the ADC, except DBGCTRL, will be reset to
their initial state, and the ADC will be disabled.
The ADC must be disabled before it is reset.
35.6.2.3 Operation
In the most basic configuration, the ADC samples values from the configured internal or external sources
(INPUTCTRL register). The rate of the conversion depends on the combination of the GCLK_ADCx
frequency and the clock prescaler.
To convert analog values to digital values, the ADC needs to be initialized first, as described in
Initialization. Data conversion can be started either manually by setting the Start bit in the Software
Trigger register (SWTRIG.START=1), or automatically by configuring an automatic trigger to initiate the
conversions. A free-running mode can be used to continuously convert an input channel. When using
free-running mode the first conversion must be started, while subsequent conversions will start
automatically at the end of previous conversions.
The automatic trigger can be configured to trigger on many different conditions.
The result of the conversion is stored in the Result register (RESULT) overwriting the result from the
previous conversion.
To avoid data loss if more than one channel is enabled, the conversion result must be read as soon as it
is available (INTFLAG.RESRDY). Failing to do so will result in an overrun error condition, indicated by the
OVERRUN bit in the Interrupt Flag Status and Clear register (INTFLAG.OVERRUN). When the RESRDY
interrupt flag is set, the new result has been synchronized to the RESULT register.
To enable one of the available interrupts sources, the corresponding bit in the Interrupt Enable Set
register (INTENSET) must be written to '1'.
35.6.3
Prescaler
The ADC is clocked by GCLK_ADC. There is also a prescaler in the ADC to enable conversion at lower
clock rates.
Refer to CTRLB for details on prescaler settings.
© 2017 Microchip Technology Inc.
Datasheet Complete
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SAM DA1
Figure 35-2. ADC Prescaler
DIV512
DIV256
DIV128
DIV64
DIV32
DIV8
DIV16
9-BIT PRESCALER
DIV4
GCLK_ADC
CTRLB.PRESCALER[2:0]
CLK_ADC
The propagation delay of an ADC measurement depends on the selected mode and is given by:
•
Single-shot mode:
•
PropagationDelay =
Free-running mode:
1+
PropagationDelay =
Table 35-1. Delay Gain
Resolution
2
+ DelayGain
�CLK+ − ADC
Resolution
2
+ DelayGain
�CLK+ − ADC
Delay Gain (in CLK_ADC Period)
INTPUTCTRL.GAIN[3:0] Free-running mode
Name
35.6.4
Single shot mode
Differential
Mode
Single-Ended Differential
Mode
mode
Single-Ended
mode
1X
0x0
0
0
0
1
2X
0x1
0
1
0.5
1.5
4X
0x2
1
1
1
2
8X
0x3
1
2
1.5
2.5
16X
0x4
2
2
2
3
Reserved 0x5 ... 0xE
Reserved
Reserved
Reserved
Reserved
DIV2
0
1
0.5
1.5
0xF
ADC Resolution
The ADC supports 8-bit, 10-bit or 12-bit resolution. Resolution can be changed by writing the Resolution
bit group in the Control B register (CTRLB.RESSEL). By default, the ADC resolution is set to 12 bits.
35.6.5
Differential and Single-Ended Conversions
The ADC has two conversion options: differential and single-ended:
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 732
SAM DA1
•
If the positive input may go below the negative input, the differential mode should be used in order
to get correct results.
If the positive input is always positive, the single-ended conversion should be used in order to
have full 12-bit resolution in the conversion.
•
The negative input must be connected to ground. This ground could be the internal GND, IOGND or an
external ground connected to a pin. Refer to the Control B (CTRLB) register for selection details.
If the positive input may go below the negative input, creating some negative results, the differential mode
should be used in order to get correct results. The differential mode is enabled by setting DIFFMODE bit
in the Control B register (CTRLB.DIFFMODE). Both conversion types could be run in single mode or in
free-running mode. When the free-running mode is selected, an ADC input will continuously sample the
input and performs a new conversion. The INTFLAG.RESRDY bit will be set at the end of each
conversion.
Related Links
CTRLB
35.6.5.1 Conversion Timing
The following figure shows the ADC timing for one single conversion. A conversion starts after the
software or event start are synchronized with the GCLK_ADC clock. The input channel is sampled in the
first half CLK_ADC period.
Figure 35-3. ADC Timing for One Conversion in Differential Mode without Gain
1
2
3
4
5
6
7
8
CLK_ ADC
START
SAMPLE
INT
Converting Bit
MS B
10
9
8
7
6
5
4
3
2
1
LS B
The sampling time can be increased by using the Sampling Time Length bit group in the Sampling Time
Control register (SAMPCTRL.SAMPLEN). As example, the next figure is showing the timing conversion.
Figure 35-4. ADC Timing for One Conversion in Differential Mode without Gain, but with Increased
Sampling Time
1
2
3
4
5
6
7
8
9
10
11
CLK_ ADC
START
SAMPLE
INT
Converting Bit
© 2017 Microchip Technology Inc.
MS B
10
9
8
7
6
Datasheet Complete
5
4
3
2
1
LS B
40001895A-page 733
SAM DA1
Figure 35-5. ADC Timing for Free Running in Differential Mode without Gain
2
1
3
4
5
6
7
9
8
10
11
12
13
6
4
2
0
14
15
16
8
6
CLK_ ADC
START
SAMPLE
INT
Converting Bit
11
10
9
8
7
6
5
4
3
2
1
0
11
10
9
8
7
5
3
1
11
10
9
7
5
Figure 35-6. ADC Timing for One Conversion in Single-Ended Mode without Gain
1
2
3
4
5
6
7
8
9
10
11
CLK_ADC
START
SAMPLE
AMPLIFY
INT
Converting Bit
MS B
10
9
8
7
6
5
4
3
2
1
LS B
Figure 35-7. ADC Timing for Free Running in Single-Ended Mode without Gain
2
1
3
4
5
6
7
9
8
10
11
12
13
14
9
7
5
3
1
15
16
CLK_ADC
START
SAMPLE
AMPLIFY
INT
Converting Bit
35.6.6
11
10
9
8
7
6
5
4
3
2
1
0
11
10
8
6
4
2
0
11
10
Accumulation
The result from multiple consecutive conversions can be accumulated. The number of samples to be
accumulated is specified by the Number of Samples to be Collected field in the Average Control register
(AVGCTRL.SAMPLENUM). When accumulating more than 16 samples, the result will be too large to
match the 16-bit RESULT register size. To avoid overflow, the result is right shifted automatically to fit
within the available register size. The number of automatic right shifts is specified in the table below.
Note: To perform the accumulation of two or more samples, the Conversion Result Resolution field in
the Control B register (CTRLB.RESSEL) must be set.
Table 35-2. Accumulation
Number of
Accumulated
Samples
AVGCTRL.
SAMPLENUM
Intermediate
Number of
Result Precision Automatic
Right Shifts
Final Result
Precision
Automatic
Division
Factor
1
0x0
12 bits
0
12 bits
0
2
0x1
13 bits
0
13 bits
0
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SAM DA1
35.6.7
Number of
Accumulated
Samples
AVGCTRL.
SAMPLENUM
Intermediate
Number of
Result Precision Automatic
Right Shifts
Final Result
Precision
Automatic
Division
Factor
4
0x2
14 bits
0
14 bits
0
8
0x3
15 bits
0
15 bits
0
16
0x4
16 bits
0
16 bits
0
32
0x5
17 bits
1
16 bits
2
64
0x6
18 bits
2
16 bits
4
128
0x7
19 bits
3
16 bits
8
256
0x8
20 bits
4
16 bits
16
512
0x9
21 bits
5
16 bits
32
1024
0xA
22 bits
6
16 bits
64
Reserved
0xB - 0xF
12 bits
12 bits
0
Averaging
Averaging is a feature that increases the sample accuracy, at the cost of a reduced sampling rate. This
feature is suitable when operating in noisy conditions.
Averaging is done by accumulating m samples, as described in Accumulation, and dividing the result by
m. The averaged result is available in the RESULT register. The number of samples to be accumulated is
specified by writing to AVGCTRL.SAMPLENUM.
The division is obtained by a combination of the automatic right shift described above, and an additional
right shift that must be specified by writing to the Adjusting Result/Division Coefficient field in AVGCTRL
(AVGCTRL.ADJRES).
Note: To perform the averaging of two or more samples, the Conversion Result Resolution field in the
Control B register (CTRLB.RESSEL) must be set to '1'.
Averaging AVGCTRL.SAMPLENUM samples will reduce the un-averaged sampling rate by a factor
1
.
AVGCTRL.SAMPLENUM
When the averaged result is available, the INTFLAG.RESRDY bit will be set.
Table 35-3. Averaging
Number of
Accumulated
Samples
AVGCTRL.
SAMPLENUM
Intermediate
Result
Precision
Number of
Automatic
Right Shifts
Division
Factor
AVGCTRL.ADJRES Total
Number
of Right
Shifts
Final Result
Precision
Automatic
Division
Factor
1
0x0
12 bits
0
1
0x0
12 bits
0
2
0x1
13
0
2
0x1
1
12 bits
0
4
0x2
14
0
4
0x2
2
12 bits
0
8
0x3
15
0
8
0x3
3
12 bits
0
16
0x4
16
0
16
0x4
4
12 bits
0
32
0x5
17
1
16
0x4
5
12 bits
2
64
0x6
18
2
16
0x4
6
12 bits
4
© 2017 Microchip Technology Inc.
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SAM DA1
35.6.8
Number of
Accumulated
Samples
AVGCTRL.
SAMPLENUM
Intermediate
Result
Precision
Number of
Automatic
Right Shifts
Division
Factor
AVGCTRL.ADJRES Total
Number
of Right
Shifts
Final Result
Precision
Automatic
Division
Factor
128
0x7
19
3
16
0x4
7
12 bits
8
256
0x8
20
4
16
0x4
8
12 bits
16
512
0x9
21
5
16
0x4
9
12 bits
32
1024
0xA
22
6
16
0x4
10
12 bits
64
Reserved
0xB-0xF
12 bits
0
0x0
Oversampling and Decimation
By using oversampling and decimation, the ADC resolution can be increased from 12 bits up to 16 bits,
for the cost of reduced effective sampling rate.
To increase the resolution by n bits, 4n samples must be accumulated. The result must then be rightshifted by n bits. This right-shift is a combination of the automatic right-shift and the value written to
AVGCTRL.ADJRES. To obtain the correct resolution, the ADJRES must be configured as described in the
table below. This method will result in n bit extra LSB resolution.
Table 35-4. Configuration Required for Oversampling and Decimation
Result
Number of
Resolution Samples to
Average
35.6.9
AVGCTRL.SAMPLENUM[3:0]
Number of
Automatic
Right Shifts
AVGCTRL.ADJRES[2:0]
13 bits
41 = 4
0x2
0
0x1
14 bits
42 = 16
0x4
0
0x2
15 bits
43 = 64
0x6
2
0x1
16 bits
44 = 256
0x8
4
0x0
Window Monitor
The window monitor feature allows the conversion result in the RESULT register to be compared to
predefined threshold values. The window mode is selected by setting the Window Monitor Mode bits in
the Window Monitor Control register (WINCTRL.WINMODE[2:0]). Threshold values must be written in the
Window Monitor Lower Threshold register (WINLT) and Window Monitor Upper Threshold register
(WINUT).
If differential input is selected, the WINLT and WINUT are evaluated as signed values. Otherwise they are
evaluated as unsigned values. The significant WINLT and WINUT bits are given by the precision selected
in the Conversion Result Resolution bit group in the Control B register (CTRLB.RESSEL). This means
that e.g. in 8-bit mode, only the eight lower bits will be considered. In addition, in differential mode, the
eighth bit will be considered as the sign bit, even if the ninth bit is zero.
The INTFLAG.WINMON interrupt flag will be set if the conversion result matches the window monitor
condition.
35.6.10 Offset and Gain Correction
Inherent gain and offset errors affect the absolute accuracy of the ADC.
The offset error is defined as the deviation of the actual ADC transfer function from an ideal straight line
at zero input voltage. The offset error cancellation is handled by the Offset Correction register
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SAM DA1
(OFFSETCORR). The offset correction value is subtracted from the converted data before writing the
Result register (RESULT).
The gain error is defined as the deviation of the last output step’s midpoint from the ideal straight line,
after compensating for offset error. The gain error cancellation is handled by the Gain Correction register
(GAINCORR).
To correct these two errors, the Digital Correction Logic Enabled bit in the Control B register
(CTRLB.CORREN) must be set to ''.
Offset and gain error compensation results are both calculated according to:
Result = Conversion value+ − OFFSETCORR ⋅ GAINCORR
The correction will introduce a latency of 13 CLK_ADC clock cycles. In free running mode this latency is
introduced on the first conversion only, since its duration is always less than the propagation delay. In
single conversion mode this latency is introduced for each conversion.
Figure 35-8. ADC Timing Correction Enabled
START
CONV0
CONV1
CONV2
CORR0
CORR1
CONV3
CORR2
CORR3
35.6.11 DMA Operation
The ADC generates the following DMA request:
•
Result Conversion Ready (RESRDY): the request is set when a conversion result is available and
cleared when the RESULT register is read. When the averaging operation is enabled, the DMA
request is set when the averaging is completed and result is available.
35.6.12 Interrupts
The ADC has the following interrupt sources:
•
Result Conversion Ready: RESRDY
•
Window Monitor: WINMON
•
Overrun: OVERRUN
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status
and Clear (INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be
individually enabled by writing a one to the corresponding bit in the Interrupt Enable Set (INTENSET)
register, and disabled by writing a one to the corresponding bit in the Interrupt Enable Clear (INTENCLR)
register. An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is
enabled. The interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled, or
the ADC is reset. An interrupt flag is cleared by writing a one to the corresponding bit in the INTFLAG
register. Each peripheral can have one interrupt request line per interrupt source or one common interrupt
request line for all the interrupt sources. This is device dependent.
© 2017 Microchip Technology Inc.
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SAM DA1
Refer to Nested Vector Interrupt Controller for details. The user must read the INTFLAG register to
determine which interrupt condition is present.
Related Links
Nested Vector Interrupt Controller
35.6.13 Events
The ADC can generate the following output events:
•
Result Ready (RESRDY): Generated when the conversion is complete and the result is available.
•
Window Monitor (WINMON): Generated when the window monitor condition match.
Setting an Event Output bit in the Event Control Register (EVCTRL.xxEO=1) enables the corresponding
output event. Clearing this bit disables the corresponding output event. Refer to the Event System
chapter for details on configuring the event system.
The peripheral can take the following actions on an input event:
•
Start conversion (START): Start a conversion.
•
Conversion flush (FLUSH): Flush the conversion.
Setting an Event Input bit in the Event Control register (EVCTRL.xxEI=1) enables the corresponding
action on input event. Clearing this bit disables the corresponding action on input event.
Note: If several events are connected to the ADC, the enabled action will be taken on any of the
incoming events. The events must be correctly routed in the Event System.
Related Links
EVSYS – Event System
35.6.14 Sleep Mode Operation
The Run in Standby bit in the Control A register (CTRLA.RUNSTDBY) controls the behavior of the ADC
during standby sleep mode. When CTRLA.RUNSTDBY=0, the ADC is disabled during sleep, but
maintains its current configuration. When CTRLA.RUNSTDBY=1, the ADC continues to operate during
sleep. Note that when CTRLA.RUNSTDBY=0, the analog blocks are powered off for the lowest power
consumption. This necessitates a start-up time delay when the system returns from sleep.
When CTRLA.RUNSTDBY=1, any enabled ADC interrupt source can wake up the CPU. While the CPU
is sleeping, ADC conversion can only be triggered by events.
35.6.15 Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers
need to be synchronized when written or read.
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status
register (STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
The Synchronization Ready interrupt can be used to signal when synchronization is complete.
If an operation that requires synchronization is executed while STATUS.SYNCBUSY=1, the bus will be
stalled. All operations will complete successfully, but the CPU will be stalled and interrupts will be pending
as long as the bus is stalled.
The following bits are synchronized when written:
•
•
Software Reset bit in the Control A register (CTRLA.SWRST)
Enable bit in the Control A register (CTRLA.ENABLE)
The following registers are synchronized when written:
© 2017 Microchip Technology Inc.
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SAM DA1
•
•
•
•
•
Control B (CTRLB)
Software Trigger (SWTRIG)
Window Monitor Control (WINCTRL)
Input Control (INPUTCTRL)
Window Upper/Lower Threshold (WINUT/WINLT)
Required write-synchronization is denoted by the "Write-Synchronized" property in the register
description.
The following registers are synchronized when read:
•
•
Software Trigger (SWTRIG)
Input Control (INPUTCTRL)
Required read-synchronization is denoted by the "Read-Synchronized" property in the register
description.
Related Links
Register Synchronization
35.7
Offset
Register Summary
Name
Bit
Pos.
0x00
CTRLA
7:0
0x01
REFCTRL
7:0
0x02
AVGCTRL
7:0
0x03
SAMPCTRL
7:0
0x04
0x05
0x06
CTRLB
RUNSTDBY
REFCOMP
ENABLE
SWRST
REFSEL[3:0]
ADJRES[2:0]
SAMPLENUM[3:0]
SAMPLEN[5:0]
7:0
RESSEL[1:0]
CORREN
FREERUN
LEFTADJ
15:8
PRESCALER[2:0]
7:0
WINMODE[2:0]
7:0
START
DIFFMODE
Reserved
0x07
Reserved
0x08
WINCTRL
0x09
...
Reserved
0x0B
0x0C
SWTRIG
FLUSH
0x0D
...
Reserved
0x0F
0x10
7:0
MUXPOS[4:0]
0x11
15:8
MUXNEG[4:0]
0x12
INPUTCTRL
0x13
0x14
23:16
INPUTOFFSET[3:0]
INPUTSCAN[3:0]
31:24
EVCTRL
GAIN[3:0]
7:0
WINMONEO RESRDYEO
SYNCEI
STARTEI
0x15
Reserved
0x16
INTENCLR
7:0
SYNCRDY
WINMON
OVERRUN
RESRDY
0x17
INTENSET
7:0
SYNCRDY
WINMON
OVERRUN
RESRDY
0x18
INTFLAG
7:0
SYNCRDY
WINMON
OVERRUN
RESRDY
0x19
STATUS
7:0
SYNCBUSY
© 2017 Microchip Technology Inc.
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SAM DA1
Offset
Name
Bit
Pos.
0x1A
RESULT
0x1B
0x1C
WINLT
0x1D
0x1E
Reserved
0x1F
Reserved
0x20
WINUT
0x21
0x22
Reserved
0x23
Reserved
0x24
GAINCORR
0x25
0x26
OFFSETCORR
0x27
0x28
CALIB
0x29
0x2A
DBGCTRL
35.8
7:0
RESULT[7:0]
15:8
RESULT[15:8]
7:0
WINLT[7:0]
15:8
WINLT[15:8]
7:0
WINUT[7:0]
15:8
WINUT[15:8]
7:0
GAINCORR[7:0]
15:8
GAINCORR[11:8]
7:0
OFFSETCORR[7:0]
15:8
OFFSETCORR[11:8]
7:0
LINEARITY_CAL[7:0]
15:8
BIAS_CAL[2:0]
7:0
DBGRUN
Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the
8-bit quarters and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be
accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection
is denoted by the Write-Protected property in each individual register description.
Some registers require synchronization when read and/or written. Synchronization is denoted by the
Write-Synchronized or the Read-Synchronized property in each individual register description.
Some registers are enable-protected, meaning they can be written only when the ADC is disabled.
Enable-protection is denoted by the Enable-Protected property in each individual register description.
35.8.1
Control A
Name: CTRLA
Offset: 0x00 [ID-00002049]
Reset: 0x00
Property: Write-Protected
Bit
7
6
5
4
3
Access
Reset
2
1
0
RUNSTDBY
ENABLE
SWRST
R/W
R/W
R/W
0
0
0
Bit 2 – RUNSTDBY: Run in Standby
This bit indicates whether the ADC will continue running in standby sleep mode or not:
© 2017 Microchip Technology Inc.
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SAM DA1
Value
0
1
Description
The ADC is halted during standby sleep mode.
The ADC continues normal operation during standby sleep mode.
Bit 1 – ENABLE: Enable
Due to synchronization, there is a delay from writing CTRLA.ENABLE until the peripheral is enabled/
disabled. The value written to CTRL.ENABLE will read back immediately and the Synchronization Busy
bit in the Status register (STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when
the operation is complete.
Value
0
1
Description
The ADC is disabled.
The ADC is enabled.
Bit 0 – SWRST: Software Reset
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the ADC, except DBGCTRL, to their initial state, and the
ADC will be disabled.
Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same
write-operation will be discarded.
Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete.
CTRLA.SWRST and STATUS.SYNCBUSY will both be cleared when the reset is complete.
Value
0
1
35.8.2
Description
There is no reset operation ongoing.
The reset operation is ongoing.
Reference Control
Name: REFCTRL
Offset: 0x01 [ID-00002049]
Reset: 0x00
Property: Write-Protected
Bit
7
6
5
4
3
2
REFCOMP
Access
Reset
1
0
REFSEL[3:0]
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Bit 7 – REFCOMP: Reference Buffer Offset Compensation Enable
The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation.
This will decrease the input impedance and thus increase the start-up time of the reference.
Value
0
1
Description
Reference buffer offset compensation is disabled.
Reference buffer offset compensation is enabled.
Bits 3:0 – REFSEL[3:0]: Reference Selection
These bits select the reference for the ADC.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 741
SAM DA1
Table 35-5. Reference Selection
REFSEL[3:0]
Name
Description
0x0
INT1V
1.0V voltage reference
0x1
INTVCC0
1/1.48 VDDANA
0x2
INTVCC1
1/2 VDDANA (only for VDDANA > 2.0V)
0x3
VREFA
External reference
0x4
VREFB
External reference
0x5-0xF
35.8.3
Reserved
Average Control
Name: AVGCTRL
Offset: 0x02 [ID-00002049]
Reset: 0x00
Property: Write-Protected
Bit
7
6
5
4
3
ADJRES[2:0]
Access
Reset
2
1
0
SAMPLENUM[3:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
Bits 6:4 – ADJRES[2:0]: Adjusting Result / Division Coefficient
These bits define the division coefficient in 2n steps.
Bits 3:0 – SAMPLENUM[3:0]: Number of Samples to be Collected
These bits define how many samples should be added together.The result will be available in the Result
register (RESULT). Note: if the result width increases, CTRLB.RESSEL must be changed.
SAMPLENUM[3:0]
Name
Description
0x0
1
1 sample
0x1
2
2 samples
0x2
4
4 samples
0x3
8
8 samples
0x4
16
16 samples
0x5
32
32 samples
0x6
64
64 samples
0x7
128
128 samples
0x8
256
256 samples
0x9
512
512 samples
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40001895A-page 742
SAM DA1
SAMPLENUM[3:0]
Name
Description
0xA
1024
1024 samples
0xB-0xF
35.8.4
Reserved
Sampling Time Control
Name: SAMPCTRL
Offset: 0x03 [ID-00002049]
Reset: 0x00
Property: Write-Protected
Bit
7
6
5
4
3
2
1
0
SAMPLEN[5:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bits 5:0 – SAMPLEN[5:0]: Sampling Time Length
These bits control the ADC sampling time in number of half CLK_ADC cycles, depending of the prescaler
value, thus controlling the ADC input impedance. Sampling time is set according to the equation:
Sampling time = SAMPLEN+1 ⋅
35.8.5
Control B
CLKADC
2
Name: CTRLB
Offset: 0x04 [ID-00002049]
Reset: 0x0000
Property: Write-Protected, Write-Synchronized
Bit
15
14
13
12
11
10
9
8
PRESCALER[2:0]
Access
Reset
Bit
7
6
5
4
RESSEL[1:0]
Access
Reset
R/W
R/W
R/W
0
0
0
3
2
1
0
CORREN
FREERUN
LEFTADJ
DIFFMODE
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bits 10:8 – PRESCALER[2:0]: Prescaler Configuration
These bits define the ADC clock relative to the peripheral clock.
PRESCALER[2:0]
Name
Description
0x0
DIV4
Peripheral clock divided by 4
0x1
DIV8
Peripheral clock divided by 8
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SAM DA1
PRESCALER[2:0]
Name
Description
0x2
DIV16
Peripheral clock divided by 16
0x3
DIV32
Peripheral clock divided by 32
0x4
DIV64
Peripheral clock divided by 64
0x5
DIV128
Peripheral clock divided by 128
0x6
DIV256
Peripheral clock divided by 256
0x7
DIV512
Peripheral clock divided by 512
Bits 5:4 – RESSEL[1:0]: Conversion Result Resolution
These bits define whether the ADC completes the conversion at 12-, 10- or 8-bit result resolution.
RESSEL[1:0]
Name
Description
0x0
12BIT
12-bit result
0x1
16BIT
For averaging mode output
0x2
10BIT
10-bit result
0x3
8BIT
8-bit result
Bit 3 – CORREN: Digital Correction Logic Enabled
Value
0
1
Description
Disable the digital result correction.
Enable the digital result correction. The ADC conversion result in the RESULT register is
then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL
registers. Conversion time will be increased by X cycles according to the value in the Offset
Correction Value bit group in the Offset Correction register.
Bit 2 – FREERUN: Free Running Mode
Value
0
1
Description
The ADC run is single conversion mode.
The ADC is in free running mode and a new conversion will be initiated when a previous
conversion completes.
Bit 1 – LEFTADJ: Left-Adjusted Result
Value
0
1
Description
The ADC conversion result is right-adjusted in the RESULT register.
The ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12bit result will be present in the upper part of the result register. Writing this bit to zero
(default) will right-adjust the value in the RESULT register.
Bit 0 – DIFFMODE: Differential Mode
Value
0
1
Description
The ADC is running in singled-ended mode.
The ADC is running in differential mode. In this mode, the voltage difference between the
MUXPOS and MUXNEG inputs will be converted by the ADC.
© 2017 Microchip Technology Inc.
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SAM DA1
35.8.6
Window Monitor Control
Name: WINCTRL
Offset: 0x08 [ID-00002049]
Reset: 0x00
Property: Write-Protected, Write-Synchronized
Bit
7
6
5
4
3
2
1
0
WINMODE[2:0]
Access
R/W
R/W
R/W
0
0
0
Reset
Bits 2:0 – WINMODE[2:0]: Window Monitor Mode
These bits enable and define the window monitor mode.
WINMODE[2:0]
Name
Description
0x0
DISABLE
No window mode (default)
0x1
MODE1
Mode 1: RESULT > WINLT
0x2
MODE2
Mode 2: RESULT < WINUT
0x3
MODE3
Mode 3: WINLT < RESULT < WINUT
0x4
MODE4
Mode 4: !(WINLT < RESULT < WINUT)
0x5-0x7
35.8.7
Reserved
Software Trigger
Name: SWTRIG
Offset: 0x0C [ID-00002049]
Reset: 0x00
Property: Write-Protected, Write-Synchronized
Bit
7
6
5
4
3
Access
Reset
2
1
0
START
FLUSH
R/W
R/W
0
0
Bit 1 – START: ADC Start Conversion
Writing this bit to zero will have no effect.
Value
0
1
Description
The ADC will not start a conversion.
The ADC will start a conversion. The bit is cleared by hardware when the conversion has
started. Setting this bit when it is already set has no effect.
Bit 0 – FLUSH: ADC Conversion Flush
After the flush, the ADC will resume where it left off; i.e., if a conversion was pending, the ADC will start a
new conversion.
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SAM DA1
Writing this bit to zero will have no effect.
Value
0
1
Description
No flush action.
"Writing a '1' to this bit will flush the ADC pipeline. A flush will restart the ADC clock on the
next peripheral clock edge, and all conversions in progress will be aborted and lost. This bit
will be cleared after the ADC has been flushed.
After the flush, the ADC will resume where it left off; i.e., if a conversion was pending, the
ADC will start a new conversion.
35.8.8
Input Control
Name: INPUTCTRL
Offset: 0x10 [ID-00002049]
Reset: 0x00000000
Property: Write-Protected, Write-Synchronized
Bit
31
30
29
28
27
26
25
24
GAIN[3:0]
Access
R/W
R/W
R/W
R/W
0
0
0
0
20
19
18
17
16
Reset
Bit
23
22
21
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
INPUTOFFSET[3:0]
Access
INPUTSCAN[3:0]
MUXNEG[4:0]
Access
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
4
3
2
1
0
Reset
Bit
7
6
5
MUXPOS[4:0]
Access
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Reset
Bits 27:24 – GAIN[3:0]: Gain Factor Selection
These bits set the gain factor of the ADC gain stage.
GAIN[3:0]
Name
Description
0x0
1X
1x
0x1
2X
2x
0x2
4X
4x
0x3
8X
8x
0x4
16X
16x
© 2017 Microchip Technology Inc.
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SAM DA1
GAIN[3:0]
Name
Description
0x5-0xE
Reserved
0xF
DIV2
1/2x
Bits 23:20 – INPUTOFFSET[3:0]: Positive Mux Setting Offset
The pin scan is enabled when INPUTSCAN != 0. Writing these bits to a value other than zero causes the
first conversion triggered to be converted using a positive input equal to MUXPOS + INPUTOFFSET.
Setting this register to zero causes the first conversion to use a positive input equal to MUXPOS.
After a conversion, the INPUTOFFSET register will be incremented by one, causing the next conversion
to be done with the positive input equal to MUXPOS + INPUTOFFSET. The sum of MUXPOS and
INPUTOFFSET gives the input that is actually converted.
Bits 19:16 – INPUTSCAN[3:0]: Number of Input Channels Included in Scan
This register gives the number of input sources included in the pin scan. The number of input sources
included is INPUTSCAN + 1. The input channels included are in the range from MUXPOS +
INPUTOFFSET to MUXPOS + INPUTOFFSET + INPUTSCAN.
The range of the scan mode must not exceed the number of input channels available on the device.
Bits 12:8 – MUXNEG[4:0]: Negative Mux Input Selection
These bits define the Mux selection for the negative ADC input. selections.
Value
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08-0x1
7
0x18
0x19
0x1A-0x1
F
Name
PIN0
PIN1
PIN2
PIN3
PIN4
PIN5
PIN6
PIN7
Reserved
Description
ADC AIN0 pin
ADC AIN1 pin
ADC AIN2 pin
ADC AIN3 pin
ADC AIN4 pin
ADC AIN5 pin
ADC AIN6 pin
ADC AIN7 pin
GND
IOGND
Reserved
Internal ground
I/O ground
Note: 1. Only available in SAM R21G.
Bits 4:0 – MUXPOS[4:0]: Positive Mux Input Selection
These bits define the Mux selection for the positive ADC input. The following table shows the possible
input selections. If the internal bandgap voltage or temperature sensor input channel is selected, then the
Sampling Time Length bit group in the SamplingControl register must be written.
MUXPOS[4:0]
Group configuration
Description
0x00
PIN0
ADC AIN0 pin
0x01
PIN1
ADC AIN1 pin
0x02
PIN2
ADC AIN2 pin
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SAM DA1
MUXPOS[4:0]
Group configuration
Description
0x03
PIN3
ADC AIN3 pin
0x04
PIN4
ADC AIN4 pin
0x05
PIN5
ADC AIN5 pin
0x06
PIN6
ADC AIN6 pin
0x07
PIN7
ADC AIN7 pin
0x08
PIN8
ADC AIN8 pin
0x09
PIN9
ADC AIN9 pin
0x0A
PIN10
ADC AIN10 pin
0x0B
PIN11
ADC AIN11 pin
0x0C
PIN12
ADC AIN12 pin
0x0D
PIN13
ADC AIN13 pin
0x0E
PIN14
ADC AIN14 pin
0x0F
PIN15
ADC AIN15 pin
0x10
PIN16
ADC AIN16 pin
0x11
PIN17
ADC AIN17 pin
0x12
PIN18
ADC AIN18 pin
0x13
PIN19
ADC AIN19 pin
0x14-0x17
Reserved
0x18
TEMP
Temperature reference
0x19
BANDGAP
Bandgap voltage
0x1A
SCALEDCOREVCC
1/4 scaled core supply
0x1B
SCALEDIOVCC
1/4 scaled I/O supply
0x1C
DAC
DAC output
0x1D-0x1F
35.8.9
Reserved
Event Control
Name: EVCTRL
Offset: 0x14 [ID-00002049]
Reset: 0x00
Property: Write-Protected
© 2017 Microchip Technology Inc.
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SAM DA1
Bit
7
6
5
4
1
0
WINMONEO
RESRDYEO
SYNCEI
STARTEI
R/W
R/W
R/W
R/W
0
0
0
0
Access
Reset
3
2
Bit 5 – WINMONEO: Window Monitor Event Out
This bit indicates whether the Window Monitor event output is enabled or not and an output event will be
generated when the window monitor detects something.
Value
0
1
Description
Window Monitor event output is disabled and an event will not be generated.
Window Monitor event output is enabled and an event will be generated.
Bit 4 – RESRDYEO: Result Ready Event Out
This bit indicates whether the Result Ready event output is enabled or not and an output event will be
generated when the conversion result is available.
Value
0
1
Description
Result Ready event output is disabled and an event will not be generated.
Result Ready event output is enabled and an event will be generated.
Bit 1 – SYNCEI: Synchronization Event In
Value
0
1
Description
A flush and new conversion will not be triggered on any incoming event.
A flush and new conversion will be triggered on any incoming event.
Bit 0 – STARTEI: Start Conversion Event In
Value
0
1
Description
A new conversion will not be triggered on any incoming event.
A new conversion will be triggered on any incoming event.
35.8.10 Interrupt Enable Clear
Name: INTENCLR
Offset: 0x16 [ID-00002049]
Reset: 0x00
Property: Write-Protected
Bit
7
6
Access
Reset
5
4
3
2
1
0
SYNCRDY
WINMON
OVERRUN
RESRDY
R/W
R/W
R/W
R/W
0
0
0
0
Bit 3 – SYNCRDY: Synchronization Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and the corresponding
interrupt request.
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SAM DA1
Value
0
1
Description
The Synchronization Ready interrupt is disabled.
The Synchronization Ready interrupt is enabled, and an interrupt request will be generated
when the Synchronization Ready interrupt flag is set.
Bit 2 – WINMON: Window Monitor Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Window Monitor Interrupt Enable bit and the corresponding interrupt
request.
Value
0
1
Description
The window monitor interrupt is disabled.
The window monitor interrupt is enabled, and an interrupt request will be generated when the
Window Monitor interrupt flag is set.
Bit 1 – OVERRUN: Overrun Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overrun Interrupt Enable bit and the corresponding interrupt request.
Value
0
1
Description
The Overrun interrupt is disabled.
The Overrun interrupt is enabled, and an interrupt request will be generated when the
Overrun interrupt flag is set.
Bit 0 – RESRDY: Result Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Result Ready Interrupt Enable bit and the corresponding interrupt
request.
Value
0
1
Description
The Result Ready interrupt is disabled.
The Result Ready interrupt is enabled, and an interrupt request will be generated when the
Result Ready interrupt flag is set.
35.8.11 Interrupt Enable Set
Name: INTENSET
Offset: 0x17 [ID-00002049]
Reset: 0x00
Property: Write-Protected
Bit
7
6
Access
Reset
5
4
3
2
1
0
SYNCRDY
WINMON
OVERRUN
RESRDY
R/W
R/W
R/W
R/W
0
0
0
0
Bit 3 – SYNCRDY: Synchronization Ready Interrupt Enable
Writing a zero to this bit has no effect.
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SAM DA1
Writing a one to this bit will set the Synchronization Ready Interrupt Enable bit, which enables the
Synchronization Ready interrupt.
Value
0
1
Description
The Synchronization Ready interrupt is disabled.
The Synchronization Ready interrupt is enabled.
Bit 2 – WINMON: Window Monitor Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Window Monitor Interrupt bit and enable the Window Monitor interrupt.
Value
0
1
Description
The Window Monitor interrupt is disabled.
The Window Monitor interrupt is enabled.
Bit 1 – OVERRUN: Overrun Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overrun Interrupt bit and enable the Overrun interrupt.
Value
0
1
Description
The Overrun interrupt is disabled.
The Overrun interrupt is enabled.
Bit 0 – RESRDY: Result Ready Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Result Ready Interrupt bit and enable the Result Ready interrupt.
Value
0
1
Description
The Result Ready interrupt is disabled.
The Result Ready interrupt is enabled.
35.8.12 Interrupt Flag Status and Clear
Name: INTFLAG
Offset: 0x18 [ID-00002049]
Reset: 0x00
Property:
Bit
7
6
5
4
Access
Reset
3
2
1
0
SYNCRDY
WINMON
OVERRUN
RESRDY
R/W
R/W
R/W
R/W
0
0
0
0
Bit 3 – SYNCRDY: Synchronization Ready
This flag is cleared by writing a one to the flag.
This flag is set on a one-to-zero transition of the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY), except when caused by an enable or software reset, and will generate an
interrupt request if INTENCLR/SET.SYNCRDY is one.
Writing a zero to this bit has no effect.
© 2017 Microchip Technology Inc.
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SAM DA1
Writing a one to this bit clears the Synchronization Ready interrupt flag.
Bit 2 – WINMON: Window Monitor
This flag is cleared by writing a one to the flag or by reading the RESULT register.
This flag is set on the next GCLK_ADC cycle after a match with the window monitor condition, and an
interrupt request will be generated if INTENCLR/SET.WINMON is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Window Monitor interrupt flag.
Bit 1 – OVERRUN: Overrun
This flag is cleared by writing a one to the flag.
This flag is set if RESULT is written before the previous value has been read by CPU, and an interrupt
request will be generated if INTENCLR/SET.OVERRUN is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Overrun interrupt flag.
Bit 0 – RESRDY: Result Ready
This flag is cleared by writing a one to the flag or by reading the RESULT register.
This flag is set when the conversion result is available, and an interrupt will be generated if INTENCLR/
SET.RESRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Result Ready interrupt flag.
35.8.13 Status
Name: STATUS
Offset: 0x19 [ID-00002049]
Reset: 0x00
Property:
Bit
7
6
5
4
3
2
1
0
SYNCBUSY
Access
R
Reset
0
Bit 7 – SYNCBUSY: Synchronization Busy
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
35.8.14 Result
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SAM DA1
Name: RESULT
Offset: 0x1A [ID-00002049]
Reset: 0x0000
Property: Read-Synchronized
Bit
15
14
13
12
11
10
9
8
RESULT[15:8]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RESULT[7:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bits 15:0 – RESULT[15:0]: Result Conversion Value
These bits will hold up to a 16-bit ADC result, depending on the configuration.
In single conversion mode without averaging, the ADC conversion will produce a 12-bit result, which can
be left- or right-shifted, depending on the setting of CTRLB.LEFTADJ.
If the result is left-adjusted (CTRLB.LEFTADJ), the high byte of the result will be in bit position [15:8],
while the remaining 4 bits of the result will be placed in bit locations [7:4]. This can be used only if an 8-bit
result is required; i.e., one can read only the high byte of the entire 16-bit register.
If the result is not left-adjusted (CTRLB.LEFTADJ) and no oversampling is used, the result will be
available in bit locations [11:0], and the result is then 12 bits long.
If oversampling is used, the result will be located in bit locations [15:0], depending on the settings of the
Average Control register (AVGCTRL).
35.8.15 Window Monitor Lower Threshold
Name: WINLT
Offset: 0x1C [ID-00002049]
Reset: 0x0000
Property: Write-Protected, Write-Synchronized
Bit
15
14
13
12
11
10
9
8
WINLT[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
WINLT[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 15:0 – WINLT[15:0]: Window Lower Threshold
If the window monitor is enabled, these bits define the lower threshold value.
© 2017 Microchip Technology Inc.
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SAM DA1
35.8.16 Window Monitor Upper Threshold
Name: WINUT
Offset: 0x20 [ID-00002049]
Reset: 0x0000
Property: Write-Protected, Write-Synchronized
Bit
15
14
13
12
11
10
9
8
WINUT[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
WINUT[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
9
8
Bits 15:0 – WINUT[15:0]: Window Upper Threshold
If the window monitor is enabled, these bits define the upper threshold value.
35.8.17 Gain Correction
Name: GAINCORR
Offset: 0x24 [ID-00002049]
Reset: 0x0000
Property: Write-Protected
Bit
15
14
13
12
11
10
R/W
R/W
R/W
R/W
0
0
0
0
3
2
1
0
GAINCORR[11:8]
Access
Reset
Bit
7
6
5
4
GAINCORR[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 11:0 – GAINCORR[11:0]: Gain Correction Value
If the CTRLB.CORREN bit is one, these bits define how the ADC conversion result is compensated for
gain error before being written to the result register. The gain-correction is a fractional value, a 1-bit
integer plusan 11-bit fraction, and therefore 1/2 2.7V, IOL maxI
VOL
-
0.1 × VDD
0.2 ×
VDD
Output high-level
voltage
VDD > 2.7V, IOH maxII
VOH
0.8 ×
VDD
0.9 × VDD
-
VDD = 2.7V-3V,
PORT.PINCFG.DRVSTR=0
-
-
1
VDD = 3V-3.63V,
PORT.PINCFG.DRVSTR=0
-
-
2.5
-
-
3
VDD = 3V-3.63V,
PORT.PINCFG.DRVSTR=1
-
-
10
VDD = 2.7V-3V,
PORT.PINCFG.DRVSTR=0
-
-
0.70
VDD = 3V-3.63V,
PORT.PINCFG.DRVSTR=0
-
-
2
-
-
2
VDD = 3V-3.63V,
PORT.PINCFG.DRVSTR=1
-
-
7
PORT.PINCFG.DRVSTR = 0load = 5pF,
VDD = 3.3V
-
-
15
Output low-level
current
Output high-level
current
Rise time(1)
Fall
time(1)
IOL
VDD = 2.7V-3V,
PORT.PINCFG.DRVSTR=1
mA
IOH
VDD = 2.7V-3V,
PORT.PINCFG.DRVSTR=1
PORT.PINCFG.DRVSTR = 1load = 20pF,
VDD = 3.3V
PORT.PINCFG.DRVSTR = 0load = 5pF,
VDD = 3.3V
PORT.PINCFG.DRVSTR = 1load = 20pF,
VDD = 3.3V
Input leakage current Pull-up resistors disabled
Unit
tRISE
ns
-
-
15
-
-
15
tFALL
ILEAK
ns
-
-
15
–1
±0.015
1
μA
Note: These values are based on simulation. These values are not covered by test limits in production
or characterization.
39.7.2
I2C Pins
Refer to the SERCOM I2C Pins section to get the list of I2C pins.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 809
SAM DA1
Table 39-12. I2C Pins Characteristics in I2C Configuration
Parameter
Condition
Symbol
Min.
Typ.
Max.
Unit
RPULL
20
40
60
kΩ
Pull-up - Pull-down resistance
Input low-level voltage
VDD = 2.7V-3.63V
VIL
-
-
0.3 × VDD
Input high-level voltage
VDD = 2.7V-3.63V
VIH
0.55 × VDD
-
-
VHYS
0.08 × VDD
-
-
-
-
0.4
-
-
0.2 × VDD
20
-
-
6
-
-
-
-
3.4
MHz
Hysteresis of Schmitt trigger inputs
VDD > 2.0V,
IOL = 3mA
Output low-level voltage
V
VOL
VDD ≤ 2.0V
,
IOL = 2mA
VOL = 0.4V
Standard, Fast and HS Modes
Output low-level current
VOL = 0.4V
Fast Mode +
3
IOL
VOL = 0.6V
SCL clock frequency
fSCL
mA
I2C pins timing characteristics can be found in the SERCOM in I2C Mode Timing section.
Table 39-13. I2C Pins Characteristics in I/O Configuration
Parameter
Conditions
Pull-up - Pull-down resistance
Symbol
Min.
Typ.
Max.
Unit
RPULL
20
40
60
kΩ
Input low-level voltage
VDD = 2.7V-3.63V
VIL
-
-
0.3 × VDD
Input high-level voltage
VDD = 2.7V-3.63V
VIH
0.55 × VDD
-
-
Output low-level voltage
VDD > 2.7V, IOL max
VOL
-
Output high-level voltage
VDD > 2.7V, IOH max
VOH
0.8*VDD
0.9 × VDD
-
-
-
1
-
-
2.5
-
-
3
0.1 × VDD 0.2 × VDD
V
VDD = 2.7V-3V,
PORT.PINCFG.
DRVSTR=0
VDD = 3V-3.63V,
Output low-level current
PORT.PINCFG.
DRVSTR=0
IOL
mA
VDD = 2.7V-3V,
PORT.PINCFG.
DRVSTR=1
VDD = 3V-3.63V,
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SAM DA1
Parameter
Conditions
Symbol
Min.
Typ.
Max.
-
-
10
-
-
0.70
-
-
2
-
-
2
-
-
7
PORT.PINCFG.
DRVSTR=1
Unit
VDD = 2.7V-3V,
PORT.PINCFG.
DRVSTR=0
VDD = 3V-3.63V,
Output high-level current
PORT.PINCFG.
DRVSTR=0
IOH
VDD = 2.7V-3V,
PORT.PINCFG.
DRVSTR=1
VDD = 3V-3.63V,
PORT.PINCFG.
DRVSTR=1
load = 20pF,
VDD = 3.3V
Rise time
15
PORT.PINCFG.
DRVSTR=1
tRISE
ns
load = 5pF, VDD = 3.3V
15
PORT.PINCFG.
DRVSTR=0
load = 20pF,
VDD = 3.3V
15
PORT.PINCFG.
DRVSTR=1
Fall time
tFALL
ns
load = 5pF, VDD = 3.3V
15
PORT.PINCFG.
DRVSTR=0
Input leakage current
Pull-up resistors disabled
ILEAK
-1
0.015
1
μA
Related Links
SERCOM I2C Pins
SERCOM in I2C Mode Timing
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SAM DA1
39.7.3 USB Pins
Table 39-14. USB Pins Characteristics in I/O Configuration
Parameter
Conditions
Pull-up - Pull-down resistance
Symbol
Min.
Typ.
Max.
Unit
RPULL
20
40
60
kΩ
Input low-level voltage
VDD = 2.7V-3.63V
VIL
-
-
0.29 × VDD
Input high-level voltage
VDD = 2.7V-3.63V
VIH
0.55 × VDD
-
-
Output low-level voltage
VDD > 2.7V, IOL max
VOL
-
0.1 × VDD
0.2 × VDD
Output high-level voltage
VDD > 2.7V, IOH max
VOH
0.8 × VDD
0.9 × VDD
-
-
-
3
-
-
9
-
-
2
-
-
7
Output low-level current
Output high-level current
Rise time
VDD = 2.7V-3V
IOL
VDD = 3V-3.63V
VDD = 2.7V-3V
IOH
VDD = 3V-3.63V
load = 5pF, VDD = 3.3V
load = 20pF, VDD = 3.3V
load = 5pF, VDD = 3.3V
Fall time
load = 20pF, VDD = 3.3V
Input leakage current
Pull-up resistors disabled
tRISE
V
mA
15
ns
tFALL
ILEAK
15
–1
±0.015
1
39.7.4
XOSC Pin
XOSC pins behave as normal pins when used as normal I/Os. Refer to table “Normal I/O Pins
Characteristics”.
39.7.5
XOSC32 Pin
XOSC32 pins behave as normal pins when used as normal I/Os. Refer to table “Normal I/O Pins
Characteristics”.
39.7.6
External Reset Pin
Reset pin has the same electrical characteristics as normal I/O pins. Refer to table “Normal I/O Pins
Characteristics”.
39.8
Injection Current
μA
Stresses beyond those listed in the table below may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or other conditions beyond those
indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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SAM DA1
Table 39-15. Injection Current(1)
Symbol
Description
min
max
Unit
Iinj1 (2)
IO pin injection current
-1
+1
mA
Iinj2 (3)
IO pin injection current
-15
+15
mA
Iinjtotal
Sum of IO pins injection current
-45
+45
mA
1.
2.
Injecting current may have an effect on the accuracy of Analog blocks
Conditions for Vpin: Vpin < GND-0.6V or 3.6V VREF/4 -0.05 × VDDANA – 0.1V
If |VIN| < VREF/4
VCM_IN < 1.2 × VDDANA – 0.75V
4.
5.
VCM_IN > 0.2 × VDDANA – 0.1V
The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the VDDIO power supply.
The ADC performance of these pins will not be the same as all the other ADC channels on pins
powered from the VDDANA power supply.
The gain accuracy represents the gain error expressed in percent.
Gain accuracy (%) = (Gain Error in V × 100) / (2 × Vref/GAIN)
Table 39-24. Single-Ended Mode
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
Effective Number of Bits
With gain compensation
ENOB
-
9.6
10.1
Bits
Total Unadjusted Error
1x gain
TUE
3
11
74
LSB
Integral Non-Linearity
1x gain
INL
1
4
11
LSB
Differential Non-Linearity
1x gain
DNL
-
±0.5
±0.95
LSB
Gain Error
Ext. Ref. 1x
-
±0.9
±10
mV
Ext. Ref. 0.5x
-
±0.2
±0.5
%
Ext. Ref. 2x to 16X
-
±0.15
±0.3
%
Offset Error
Ext. Ref. 1x
-
±3
±40
mV
Spurious Free Dynamic Range
SFDR
63
68
70.1
dB
Signal-to-Noise and Distortion
1x Gain
FCLK_ADC = 2.1MHz
SINAD
55
60.1
62.5
dB
Signal-to-Noise Ratio
FIN = 40kHz
SNR
54
61
64
dB
Total Harmonic Distortion
AIN = 95%FSR
THD
–70
–68
–65
dB
Noise RMS
T = 25°C
-
1
5
mV
Gain Accuracy(4)
Note:
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SAM DA1
1.
2.
3.
4.
Maximum numbers are based on characterization and not tested in production, and for 5% to 95%
of the input voltage range.
Respect the input common mode voltage through the following equations (where VCM_IN is the
Input channel common mode voltage) for all VIN:
VCM_IN < 0.7 × VDDANA + VREF/4 – 0.75V
VCM_IN > VREF/4 – 0.3 × VDDANA – 0.1V
The ADC channels on pins PA08, PA09, PA10, PA11 are powered from the VDDIO power supply.
The ADC performance of these pins will not be the same as all the other ADC channels on pins
powered from the VDDANA power supply.
The gain accuracy represents the gain error expressed in percent.
Gain accuracy (%) = (Gain Error in V × 100) / (Vref/GAIN)
39.9.4.1 Performance with the Averaging Digital Feature
Averaging is a feature which increases the sample accuracy. ADC automatically computes an average
value of multiple consecutive conversions. The numbers of samples to be averaged is specified by the
Number-of-Samples-to-be-collected bit group in the Average Control register
(AVGCTRL.SAMPLENUM[3:0]) and the averaged output is available in the Result register (RESULT).
Table 39-25. Averaging Feature
Average
Number
Conditions
SNR (dB) SINAD (dB) SFDR (dB)
1
8
In differential mode, 1x gain,
VDDANA = 3.0V, VREF = 1.0V, 350kSps at 25°C
32
128
ENOB
(bits)
66.0
65.0
72.8
10.5
67.6
65.8
75.1
10.62
69.7
67.1
75.3
10.85
70.4
67.5
75.5
10.91
39.9.4.2 Performance with the hardware offset and gain correction
Inherent gain and offset errors affect the absolute accuracy of the ADC. The offset error cancellation is
handled by the Offset Correction register (OFFSETCORR) and the gain error cancellation, by the Gain
Correction register (GAINCORR). The offset and gain correction value is subtracted from the converted
data before writing the Result register (RESULT).
Table 39-26. Offset and Gain Correction Feature
Gain
Factor
Offset Error
(mV)
Gain Error
(mV)
Total Unadjusted
Error (LSB)
0.25
1.0
2.4
0.20
0.10
1.5
0.15
–0.15
2.7
8x
–0.05
0.05
3.2
16x
0.10
–0.05
6.1
Conditions
0.5x
1x
2x
In differential mode, 1x gain, VDDANA = 3.0V, VREF
= 1.0V, 350kSps at 25°C
39.9.4.3 Inputs and Sample and Hold Acquisition Times
The analog voltage source must be able to charge the sample and hold (S/H) capacitor in the ADC in
order to achieve maximum accuracy. Seen externally the ADC input consists of a resistor (�SAMPLE) and a
capacitor (�SAMPLE). In addition, the source resistance (�SOURCE) must be taken into account when
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SAM DA1
calculating the required sample and hold time. The next figure shows the ADC input channel equivalent
circuit.
Figure 39-5. ADC Input
VDDANA/2
Analog Input
AINx
CSAMPLE
RSOURCE
RSAMPLE
VIN
To achieve n bits of accuracy, the �SAMPLE capacitor must be charged at least to a voltage of
�CSAMPLE ≥ �
IN
�+1
× 1 + − 2−
The minimum sampling time �SAMPLEHOLD for a given �SOURCEcan be found using this formula:
�SAMPLEHOLD ≥ �SAMPLE + �
SOURCE
× �SAMPLE × � + 1 × ln 2
for a 12 bits accuracy: �SAMPLEHOLD ≥ �SAMPLE + �
SOURCE
where
39.9.5
�SAMPLEHOLD =
× �SAMPLE × 9.02
1
2 × �ADC
Digital to Analog Converter (DAC) Characteristics
Table 39-27. Operating Conditions(1)
Symbol
Parameter
VDDANA
AVREF
IDD
Min.
Typ.
Max.
Unit
Analog supply voltage
2.7
-
3.63
V
External reference voltage
1.0
-
VDDANA – 0.6
V
Internal reference voltage 1
-
1
-
V
Internal reference voltage 2
-
VDDANA
-
V
Linear output voltage range
0.05
-
VDDANA – 0.05
V
Minimum resistive load
5
-
-
kΩ
Maximum capacitance load
-
-
100
pF
-
175
256
μA
DC supply current(2)
1.
2.
Conditions
Voltage pump disabled
These values are based on specifications otherwise noted.
These values are based on characterization. These values are not covered by test limits in
production.
© 2017 Microchip Technology Inc.
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SAM DA1
Table 39-28. Clock and Timing(1)
Parameter
Conditions
Conversion rate
Cload = 100pF
Rload > 5kΩ
Startup time
1.
Min.
Typ.
Max.
Unit
Normal mode
-
-
350
For ΔDATA = ±1
-
-
1000
VDDNA > 2.6V
-
-
2.85
μs
VDDNA < 2.6V
-
-
10
μs
ksps
These values are based on simulation. These values are not covered by test limits in production or
characterization.
Table 39-29. Accuracy Characteristics(1)
Symbol
Parameter
RES
Conditions
Min.
Typ.
Max.
Unit
-
-
10
Bits
VDD = 1.6V
±0.2
±0.5
±1
VDD = 3.6V
±0.2
±0.4
±1.2
VDD = 1.6V
±0.2
±0.6
±1.2
VDD = 3.6V
±0.2
±0.5
±1.3
VDD = 1.6V
±0.4
±0.7
±2
VDD = 3.6V
±0.4
±0.8
±6
VDD = 1.6V
±0.1
±0.3
±0.8
VDD = 3.6V
±0.1
±0.3
±0.8
VDD = 1.6V
±0.1
±0.2
±0.5
VDD = 3.6V
±0.1
±0.2
±1
VDD = 1.6V
±0.3
±0.6
±3
VDD = 3.6V
±0.3
±0.8
±7
VREF = Ext. VREF
-
±4
±16
mV
VREF = VDDANA
-
±12
±60
mV
VREF = INT1V
-
±1
±22
mV
VREF = Ext. VREF
-
±1
±13
mV
VREF = VDDANA
-
±2.5
±21
mV
VREF = INT1V
-
±1.5
±20
mV
Input resolution
VREF = Ext 1.0V
INL
Integral non-linearity
VREF = VDDANA
VREF = INT1V
VREF = Ext 1.0V
DNL
Differential non-linearity
VREF = VDDANA
VREF = INT1V
Gain error
Offset error
1.
LSB
LSB
All values measured using a conversion rate of 350ksps.
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SAM DA1
39.9.6 Analog Comparator Characteristics
Table 39-30. Electrical and Timing
Parameter
Conditions
Min.
Typ.
Max.
Positive input voltage range
0
-
VDDANA
Negative input voltage range
0
-
VDDANA
Hysteresis = 0, Fast mode
–26
0
26
mV
Hysteresis = 0, Low power mode
–28
0
28
mV
Hysteresis = 1, Fast mode
8
50
102
mV
Hysteresis = 1, Low power mode
14
50
75
mV
Changes for VACM = VDDANA/2
100mV overdrive, Fast mode
90
180
ns
Changes for VACM = VDDANA/2
100mV overdrive, Low power mode
302
534
ns
1
2
μs
-
14
23
μs
–1.4
0.201
1.4
LSB
–0.9
0.022
0.9
LSB
–0.2
0.056
0.92
LSB
–0.89 0.079
0.89
LSB
Offset
Hysteresis
Propagation delay
Symbol
Enable to ready delay
Fast mode
Startup time
Enable to ready delay
Low power mode
VSCALE
Offset Error (1)(2)
Gain Error (1)(2)
1.
2.
3.
V
tSTARTUP
INL(3)
DNL(3)
Unit
According to the standard equation V(X) = VLSB × (X + 1); VLSB = VDDANA/64
Data computed with the Best Fit method
Data computed using histogram
39.9.7 Internal 1.1V Bandgap Reference Characteristics
Table 39-31. Bandgap and Internal 1.1V Reference Characteristics
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
1.07
1.1
1.12
V
1.08
1.1
1.11
V
After
calibration at
T= 25°C,
Internal 1.1V
Bandgap
reference
over [–40,
+105]°C,
INT1V
VDD = 3.3V
Over voltage
at 25°C
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SAM DA1
39.10
NVM Characteristics
Table 39-32. Maximum Operating Frequency
VDD range
NVM Wait States
Maximum Operating Frequency
Unit
0
24
MHz
1
48
MHz
2.7V to 3.63V
Note that on this flash technology, a max number of 8 consecutive write is allowed per row. Once this
number is reached, a row erase is mandatory.
Table 39-33. Flash Endurance and Data Retention
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
Retention after up to 25k
Average ambient 55°C
RetNVM25k
10
50
-
Years
Retention after up to 2.5k
Average ambient 55°C
RetNVM2.5k
20
100
-
Years
Retention after up to 100
Average ambient 55°C
RetNVM100
25
>100
-
Years
Cycling Endurance(1)
–40°C < Ta < 105°C
CycNVM
25k
150k
-
Cycles
An endurance cycle is a write and an erase operation.
Table 39-34. EEPROM Emulation(1) Endurance and Data Retention
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
Retention after up to 100k
Average ambient 55°C
RetEEPROM100k
10
50
-
Years
Retention after up to 10k
Average ambient 55°C
RetEEPROM10k
20
100
-
Years
Cycling Endurance(2)
–40°C < Ta
< 105°C
CycEEPROM
100k
600k
-
Cycles
The EEPROM emulation is a software emulation described in the App note AT03265. An endurance cycle
is a write and an erase operation.
Table 39-35. NVM Characteristics
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
Page programming time
-
tFPP
-
-
2.5
ms
Row erase time
-
tFRE
-
-
6
ms
DSU chip erase time (CHIP_ERASE)
-
tFCE
-
-
240
ms
39.11
Oscillators Characteristics
39.11.1 Crystal Oscillator (XOSC) Characteristics
39.11.1.1 Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN.
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SAM DA1
Table 39-36. Digital Clock Characteristics
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
XIN clock frequency
Digital mode
Fxin
-
-
32
MHz
XIN clock duty cycle
Digital mode
DCxin
-
-
-
%
39.11.1.2 XOSC Characteristics
The following table describes the characteristics for the oscillator when a crystal is connected between
XIN and XOUT. The user must choose a crystal oscillator where the crystal load capacitance CL is within
the range given in the table. The exact value of CL can be found in the crystal datasheet. The
capacitance of the external capacitors (CLEXT) can then be computed as follows:
CLEXT = 2 CL − CSTRAY − CSHUNT
where CSTRAY is the capacitance of the pins and PCB, CSHUNT is the shunt capacitance of the crystal.
Table 39-37. Crystal Oscillator Characteristics
Parameter
Conditions
Crystal oscillator frequency
Symbol Min. Typ. Max. Unit
fOUT
0.4
-
32
-
-
5.6K
-
-
330
-
-
240
MHz
f = 0.455 MHz,
CL = 100pF
XOSC.GAIN = 0
f = 2MHz,
CL = 20pF
XOSC.GAIN = 0
f = 4MHz,
Crystal Equivalent Series Resistance
CL = 20pF
XOSC.GAIN = 1
Safety Factor = 3
The AGC does not have any noticeable impact on
these measurements.
f = 8 MHz,
ESR
CL = 20pF
Ω
-
-
105
-
-
60
-
-
55
XOSC.GAIN = 2
f = 16 MHz,
CL = 20pF
XOSC.GAIN = 3
f = 32MHz,
CL = 18pF
XOSC.GAIN = 4
Parasitic capacitor load
CXIN
-
5.9
-
pF
Parasitic capacitor load
CXOUT
-
3.2
-
pF
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SAM DA1
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
-
15.6K
51.0K
-
6.3K
20.1K
-
6.2K
20.3K
-
7.7K
21.2K
-
6.0K
14.2K
f = 2MHz,
CL = 20pF,
XOSC.GAIN = 0,
ESR = 600Ω
f = 4MHz,
CL = 20pF,
XOSC.GAIN = 1,
ESR = 100Ω
f = 8 MHz,
CL = 20pF,
Startup time
tSTARTUP
XOSC.GAIN = 2,
cycles
ESR = 35Ω
f = 16 MHz,
CL = 20pF,
XOSC.GAIN = 3,
ESR = 25Ω
f = 32MHz,
CL = 18pF,
XOSC.GAIN = 4,
ESR = 40Ω
Parameter
Conditions
Symbol
Min.
Typ.
Max.
-
89
190
Unit
f = 2MHz,
CL = 20pF,
XOSC.GAIN = 0,
AGC off
Current Consumption
f = 2MHz,
μA
CL = 20pF,
XOSC.GAIN = 0,
-
82
187
-
140
256
AGC on
f = 4MHz,
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SAM DA1
Parameter
Conditions
Symbol
Min.
Typ.
Max.
-
102
219
-
243
380
-
166
299
-
493
685
-
293
480
-
1343
1975
-
555
776
Unit
CL = 20pF,
XOSC.GAIN = 1,
AGC off
f = 4MHz,
CL = 20pF,
XOSC.GAIN = 1,
AGC on
f = 8MHz,
CL = 20pF,
XOSC.GAIN = 2,
AGC off
f = 8MHz,
CL = 20pF,
XOSC.GAIN = 2,
AGC on
f = 16MHz,
CL = 20pF,
XOSC.GAIN = 3,
AGC off
f = 16MHz,
Current Consumption
CL = 20pF,
XOSC.GAIN = 3,
μA
AGC on
f = 32MHz,
CL = 18pF,
XOSC.GAIN = 4,
AGC off
f = 32MHz,
CL = 18pF,
XOSC.GAIN = 4,
AGC on
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 825
SAM DA1
Figure 39-6. Oscillator Connection
Xin
C LEXT
Crystal
LM
C SHUNT
RM
C STRAY
CM
Xout
C LEXT
39.11.2 External 32 kHz Crystal Oscillator (XOSC32K) Characteristics
39.11.2.1 Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32
pin.
Table 39-38. Digital Clock Characteristics
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
XIN32 clock frequency
fCPXIN32
-
32.768
-
kHz
XIN32 clock duty cycle
DCxin
-
50
-
%
39.11.2.2 XOSC32K Characteristics
The Figure 39-6 and the equation in XOSC Characteristics also applies to the 32 kHz oscillator
connection. The user must choose a crystal oscillator where the crystal load capacitance CL is within the
range given in the table. The exact value of CL can be found in the crystal datasheet.
Table 39-39. 32kHz Crystal Oscillator Characteristics
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
fOUT
-
32768
-
Hz
tSTARTUP
-
28K
30K
cycles
Crystal load capacitance
CL
-
-
12.5
pF
Crystal shunt capacitance
CSHUNT
-
0.1
-
pF
Parasitic capacitor load
CXIN32
-
3.2
-
pF
Parasitic capacitor load
CXOUT32
-
3.7
-
pF
Crystal oscillator frequency
Startup time
© 2017 Microchip Technology Inc.
ESRXTAL = 39.9 kΩ,
CL = 12.5 pF
Datasheet Complete
40001895A-page 826
SAM DA1
Parameter
Conditions
Current consumption
Symbol
Min.
Typ.
Max.
Unit
IXOSC32K
-
1.22
2.2
μA
ESR
-
-
100
kΩ
Crystal equivalent series resistance
f = 32.768kHz
CL=12.5pF
Safety Factor = 3
39.11.3 Digital Frequency Locked Loop (DFLL48M) Characteristics
Table 39-40. DFLL48M Characteristics - Open Loop Mode
Parameter
Conditions
Symbol Min. Typ. Max. Unit
DFLLVAL.COARSE = DFLL48M COARSE CAL
Output frequency
DFLLVAL.FINE = 512
fOUT
44.75
48
49
MHz
fOUT
43.75
48
49
MHz
fOUT
45.5
48
49
MHz
IDFLL
-
403
453
μA
tSTARTUP
-
8.6
11.5
μs
over [–10, +105]C, over [2.7, 3.6]V
DFLLVAL.COARSE = DFLL48M COARSE CAL
Output frequency
DFLLVAL.FINE = 512
over [–40, +105]C, over [2.7, 3.6]V
DFLLVAL.COARSE = DFLL48M COARSE CAL
Output frequency
DFLLVAL.FINE = 512
at 25°C, over [2.7, 3.6]V
Power consumption on VDDIN
DFLLVAL.COARSE = DFLL48M COARSE CAL
DFLLVAL.FINE = 512
DFLLVAL.COARSE = DFLL48M COARSE CAL
Startup time
DFLLVAL.FINE = 512
fOUT within 90 % of final value
Table 39-41. DFLL48M Characteristics - Closed Loop Mode(1)
Parameter
Average Output frequency
Conditions
Symbol
fREF = XTAL, 32.768kHz, 100ppm
DFLLMUL = 1464
Reference frequency
Min.
Typ.
Max.
Unit
fCloseOUT 47.963 47.972 47.981 MHz
fREF
0.732
32.768
33
kHz
Cycle to Cycle jitter
fREF = XTAL, 32.768kHz, 100ppm
DFLLMUL = 1464
Jitter
-
-
0.42
ns
Power consumption on VDDIN
fREF = XTAL, 32.768kHz, 100ppm
IDFLL
-
403
453
μA
tLOCK
-
350
1500
μs
Lock time
fREF = XTAL, 32.768kHz, 100ppm
DFFLMUL = 1464
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 827
SAM DA1
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
DFLLVAL.COARSE = DFLL48M
COARSE CAL
DFLLVAL.FINE = 512
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.CCDIS = 1
DFLLMUL.FSTEP = 10
Note:
1. All parts are tested in production to be able to use the DFLL as main CPU clock whether in DFLL
closed loop mode with an external OSC reference or the internal OSC8M.
2. To ensure that the device stays within the maximum allowed clock frequency, any reference clock
for DFLL in close loop must be within a 2% error accuracy.
39.11.4 32.768kHz Internal oscillator (OSC32K) Characteristics
Table 39-42. 32kHz RC Oscillator Characteristics
Parameter
Conditions
Symbol
Min.
Typ.
Max.
26.214
32.768
39.321
32.113
32.768
33.423
31.457
32.768
34.079
Unit
Calibrated against a 32.768kHz
reference at 25°C,
over [–40, +105]C,
over [2.7, 3.63]V
Output frequency
Calibrated against a 32.768kHz
reference at 25°C,
fOUT
kHz
at VDD = 3.3V
Calibrated against a 32.768kHz
reference at 25°C,
over [2.7, 3.63]V
Current consumption
IOSC32K
0.67
4.06
μA
Startup time
tSTARTUP
1
2
cycle
Duty Cycle
Duty
50
%
39.11.5 Ultra Low Power Internal 32kHz RC Oscillator (OSCULP32K) Characteristics
Table 39-43. Ultra Low Power Internal 32kHz RC Oscillator Characteristics
Parameter
Conditions
Output frequency
Calibrated against a 32.768kHz
reference
© 2017 Microchip Technology Inc.
Symbol
Min.
Typ.
Max.
Unit
fOUT
24.576
32.768
40.960
kHz
Datasheet Complete
40001895A-page 828
SAM DA1
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Unit
31.457
32.768
34.078
31.293
32.768
34.570
-
50
-
at 25°C,
over
[–40, +105]°C,
over [2.7, 3.63]V
Calibrated against a 32.768kHz
reference
at 25°C,
at VDD = 3.3V
Calibrated against a 32.768kHz
reference
at 25°C,
over [2.7, 3.63]V
Duty Cycle
1.
2.
Duty
%
These values are based on simulation. These values are not covered by test limits in production or
characterization.
This oscillator is always on.
39.11.6 8MHz RC Oscillator (OSC8M) Characteristics
Table 39-44. Internal 8MHz RC Oscillator Characteristics
Parameter
Conditions
Symbol Min. Typ. Max. Unit
Calibrated against a 8MHz reference
at 25°C,
over [–10, +70]C,
7.84
8
8.16
7.80
8
8.20
over [2.7, 3.6]V
Calibrated against a 8MHz reference
at 25°C,
over [–10, +105]°C,
Output frequency
fOUT
over [2.7, 3.6]V
MHz
Calibrated against a 8MHz reference
at 25°C,
over [–40, +105]°C,
7.66
8
8.34
7.88
8
8.12
over [2.7, 3.6]V
Calibrated against a 8MHz reference
at 25°C,
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 829
SAM DA1
Parameter
Conditions
Symbol Min. Typ. Max. Unit
over [2.7, 3.6]V
IDLE2 on OSC32K versus IDLE2 on calibrated OSC8M
Current consumption enabled at 8MHz
(FRANGE=1, PRESC=0)
Startup time
IOSC8M
-
64
96
μA
tSTARTUP
-
2.3
3.9
μs
Duty
-
50
-
%
Duty cycle
39.11.7 Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics
Table 39-45. FDPLL96M Characteristics(1) (Device Variant A / Die revision E)
Parameter
Conditions
Input frequency
Output frequency
Current consumption
fIN = 32kHz, fOUT = 48MHz
fIN = 32kHz, fOUT = 96MHz
Symbol
Min. Typ. Max.
fIN
32
-
2000
KHz
fOUT
48
-
96
MHz
-
500
733
-
900
1235
-
1.3
4
-
3.1
7
-
1.3
4
-
3.6
9
-
1
2
ms
-
25
50
μs
40
50
60
%
IFDPLL96M
fIN = 32kHz, fOUT = 48MHz
Period jitter
fIN = 32kHz, fOUT = 96MHz
fIN = 2MHz, fOUT = 48MHz
Jp
fIN = 2MHz, fOUT = 96MHz
Lock Time
After startup, time to get lock signal.
fIN = 32kHz, fOUT = 96MHz
tLOCK
fIN = 2MHz, fOUT = 96MHz
Duty cycle
1.
Unit
Duty
μA
%
All values have been characterized with FILTSEL[1/0] as default value.
Table 39-46. FDPLL96M Characteristics(1) (Device Variant B / Die revision F)
Parameter
Conditions
Input frequency
Output frequency
Current consumption
fIN = 32kHz, fOUT = 48MHz
fIN = 32kHz, fOUT = 96MHz
Symbol
fIN = 32kHz, fOUT = 96MHz
fIN = 2MHz, fOUT = 48MHz
fIN = 2MHz, fOUT = 96MHz
© 2017 Microchip Technology Inc.
Datasheet Complete
Unit
fIN
32
-
2000
KHz
fOUT
48
-
96
MHz
-
500
-
-
900
-
-
2.1
4.0
-
4.0
11.0
-
2.2
4.0
-
4.7
12.0
IFDPLL96M
fIN = 32kHz, fOUT = 48MHz
Period jitter
Min. Typ. Max.
Jp
μA
%
40001895A-page 830
SAM DA1
Parameter
Conditions
Symbol
After startup, time to get lock signal.
fIN = 32kHz, fOUT = 96MHz
Lock Time
tLOCK
fIN = 2MHz, fOUT = 96MHz
Duty cycle
1.
39.12
Duty
Min. Typ. Max.
Unit
-
1.2
2
ms
-
25
35
μs
40
50
60
%
All values have been characterized with FILTSEL[1/0] as default value.
PTC Typical Characteristics
39.12.1
VCC = 3.3C and fCPU = 48MHz for the following PTC measurements.
/ PTC_GCLK
= 4MHz / FREQ_MODE_NONE
Figure 39-7. 1 Sensor / PTC_GCLK =1Key
4MHz
/ FREQ_MODE_NONE
1
2
4
8
16
32
64
32
64
Sample Averaging
/ PTC_GCLK = 2MHz / FREQ_MODE_HOP
Figure 39-8. 1 Sensor / PTC_GCLK =1Key
2MHz
/ FREQ_MODE_HOP
1
2
4
8
16
Sample Averaging
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 831
SAM DA1
/ PTC_GCLK
= 4MHz / FREQ_MODE_NONE
Figure 39-9. 10 Sensor / PTC_GCLK10Keys
= 4MHz
/ FREQ_MODE_NONE
1
2
4
8
16
32
64
32
64
Sample Averaging
10Keys
/ PTC_GCLK
= 2MHz / FREQ_MODE_HOP
Figure 39-10. 10 Sensor / PTC_GCLK
= 2MHz
/ FREQ_MODE_HOP
1
2
4
8
16
Sample Averaging
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 832
SAM DA1
100 Keys
/ PTC_GCLK
= 4MHz / FREQ_MODE_NONE
Figure 39-11. 100 Sensor / PTC_GCLK
= 4MHz
/ FREQ_MODE_NONE
1
2
4
8
16
32
64
32
64
Sample Averaging
Figure 39-12. 100 Sensor / PTC_GCLK
= 2MHz
/ FREQ_MODE_HOP
100 Keys
/ PTC_GCLK
= 2MHz / FREQ_MODE_HOP
1
2
4
8
16
Sample Averaging
39.13
USB Characteristics
The USB on-chip buffers comply with the Universal Serial Bus (USB) v2.0 standard. All AC parameters
related to these buffers can be found within the USB 2.0 electrical specifications.
The USB interface is USB-IF certified:
- TID 40001583 - Peripheral Silicon > Low/Full Speed > Silicon Building Blocks
- TID 120000272 - Embedded Hosts > Full Speed
Electrical configuration required to be USB compliance:
- The CPU frequency must be higher 8MHz when USB is active (No constraint for USB suspend mode)
- The operating voltages must be 3.3V (Min. 3.0V, Max. 3.6V).
- The GCLK_USB frequency accuracy source must be less than:
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 833
SAM DA1
- In USB device mode, 48MHz +/-0.25%
- In USB host mode, 48MHz +/-0.05%
Table 39-47. GCLK_USB Clock Setup Recommendations
Clock setup
DFLL48M
FDPLL96M
USB Device
USB Host
Open loop
No
No
Closed loop, any internal OSC source
No
No
Closed loop, any external XOSC source
Yes
No
Closed loop, USB SOF source (USB recovery mode)(1)
Yes(2)
N/A
Any internal OSC source (32K, 8M, ... )
No
No
Any external XOSC source (< 1MHz)
Yes
No
Any external XOSC source (> 1MHz)
Yes(3)
Yes
Notes: 1. When using DFLL48M in USB recovery mode, the Fine Step value must be Ah to guarantee a
USB clock at +/-0.25% before 11ms after a resume.
2. Very high signal quality and crystal less. It is the best setup for USB Device mode.
3. FDPLL lock time is short when the clock frequency source is high (> 1MHz). Thus, FDPLL and external
OSC can be stopped during USB suspend mode to reduce consumption and guarantee a USB wake-up
time (See TDRSMDN in USB specification).
39.14
Timing Characteristics
39.14.1 External Reset
Table 39-48. External Reset Characteristics
Symbol
Parameter
Condition
tEXT
Minimum reset pulse width
Min.
Typ.
Max.
Units
10
-
-
ns
39.14.2 SERCOM in SPI Mode Timing
Figure 39-13. SPI Timing Requirements in Master Mode
SS
tSCKR
tMOS
tSCKF
SCK
(CPOL = 0)
tSCKW
SCK
(CPOL = 1)
tSCKW
tMIS
MISO
(Data Input)
tMIH
tSCK
MSB
LSB
tMOH
tMOH
MOSI
(Data Output)
© 2017 Microchip Technology Inc.
MSB
LSB
Datasheet Complete
40001895A-page 834
SAM DA1
Figure 39-14. SPI Timing Requirements in Slave Mode
SS
tSSS
tSCKR
tSCKF
tSSH
SCK
(CPOL = 0)
tSSCKW
SCK
(CPOL = 1)
tSSCKW
tSIS
MOSI
(Data Input)
tSIH
MSB
LSB
tSOSSS
MISO
(Data Output)
tSSCK
tSOS
tSOSSH
MSB
LSB
Table 39-49. SPI Timing Characteristics and Requirements(1)
Symbol Parameter
Conditions
Min.
Typ.
Max. Units
tSCK
SCK period
Master
tSCKW
SCK high/low width
Master
-
0.5*tSCK
-
tSCKR
SCK rise time(2)
Master
-
-
-
tSCKF
SCK fall time(2)
Master
-
-
-
tMIS
MISO setup to SCK
Master
-
21
-
tMIH
MISO hold after SCK
Master
-
13
-
tMOS
MOSI setup SCK
Master
-
tSCK/2 - 3
-
tMOH
MOSI hold after SCK
Master
-
3
-
tSSCK
Slave SCK Period
Slave
1*tCLK_APB
-
-
tSSCKW
SCK high/low width
Slave
0.5*tSSCK
-
-
tSSCKR
SCK rise time(2)
Slave
-
-
-
tSSCKF
SCK fall time(2)
Slave
-
-
-
tSIS
MOSI setup to SCK
Slave
tSSCK/2 - 9
-
-
tSIH
MOSI hold after SCK
Slave
tSSCK/2 - 3
-
-
tSSS
SS setup to SCK
Slave PRELOADEN=1 2*tCLK_APB +
tSOS
-
-
PRELOADEN=0 tSOS+7
-
-
84
ns
tSSH
SS hold after SCK
Slave
tSIH - 4
-
tSOS
MISO setup SCK
Slave
-
tSSCK/2 - 18 -
tSOH
MISO hold after SCK
Slave
-
18
© 2017 Microchip Technology Inc.
Datasheet Complete
-
40001895A-page 835
SAM DA1
Symbol Parameter
Conditions
Min.
Typ.
Max. Units
tSOSS
MISO setup after SS
low
Slave
-
18
-
tSOSH
MISO hold after SS
high
Slave
-
10
-
1.
2.
These values are based on simulation. These values are not covered by test limits in production.
See I/O Pin Characteristics.
39.14.3 SERCOM in I2C Mode Timing
This section describes the requirements for devices connected to the I2C Interface Bus.
Figure 39-15. I2C Interface Bus Timing
tHIGH
tOF
tLOW
tR
tLOW
SCL
tS U;S TA
tHD;S TA
tHD;DAT
tS U;DAT
tS U;S TO
SDA
tBUF
Table 39-50. I2C Interface Timing
Symbol Parameter
tR
tOF
Rise time for both SDA
and SCL
Output fall time from
VIHmin to VILmax
Conditions
Min.
Typ. Max. Units
Standard /
Fast Mode
Cb(2) = 400pF
-
230 350
Fast
Mode +
Cb(2) = 550pF
60
100
High Speed
Mode
Cb(2) = 100pF
30
60
Standard /
Fast Mode
10pF < Cb(2) < 400pF
25
50
Fast
Mode +
10pF < Cb(2) < 550pF
20
30
High Speed
Mode
10pF < Cb(2) < 100pF
10
20
tHD;STA
Hold time (repeated)
START condition
fSCL > 100kHz, Master tLOW-9 -
-
tLOW
Low period of SCL Clock
fSCL > 100kHz
-
© 2017 Microchip Technology Inc.
Datasheet Complete
113
-
ns
40001895A-page 836
SAM DA1
Symbol Parameter
Conditions
Min.
Typ. Max. Units
tBUF
Bus free time between a
STOP and a START
condition
fSCL > 100kHz
tLOW
-
-
tSU;STA
Setup time for a repeated
START condition
fSCL > 100kHz, Master tLOW+7 -
-
tHD;DAT
Data hold time
fSCL > 100kHz, Master 9
-
12
tSU;DAT
Data setup time
fSCL > 100kHz, Master 104
-
-
tSU;STO
Setup time for STOP
condition
fSCL > 100kHz, Master tLOW+9 -
-
tSU;DAT;rx Data setup time (receive
mode)
fSCL > 100kHz, Slave
51
-
56
tHD;DAT;tx Data hold time (send
mode)
fSCL > 100kHz, Slave
71
90
138
1. These values are based on simulation. These values are not covered by test limits in production.
2. Cb = Capacitive load on each bus line. Otherwise noted, value of Cb set to 20pF.
39.14.4 SWD Timing
Figure 39-16. SWD Interface Signals
Read Cycle
From debugger to
SWDIO pin
Stop
Park
Tri State
Thigh
Tos
Data
Data
Parity
Start
Tlow
From debugger to
SWDCLK pin
SWDIO pin to
debugger
Tri State
Acknowledge
Tri State
Write Cycle
From debugger to
SWDIO pin
Stop
Park
Tri State
Tis
Start
Tih
From debugger to
SWDCLK pin
SWDIO pin to
debugger
Tri State
Acknowledge
Data
Data
Parity
Tri State
Table 39-51. SWD Timings(1)
Symbol Parameter
Conditions
Min. Max.
Thigh
SWDCLK High period
10
500000 ns
Tlow
SWDCLK Low period
VVDDIO from 3.0 V to 3.6 V, maximum
external capacitor = 40 pF
10
500000
Tos
SWDIO output skew to
falling edge SWDCLK
-5
5
© 2017 Microchip Technology Inc.
Datasheet Complete
Units
40001895A-page 837
SAM DA1
Symbol Parameter
Conditions
Min. Max.
Tis
Input Setup time required
between SWDIO
4
-
Tih
Input Hold time required
between SWDIO and
rising edge SWDCLK
1
-
Units
Note: 1. These values are based on simulation. These values are not covered by test limits in production
or characterization.
39.14.5 I2S Timing
Figure 39-17. I2S Timing Master Mode
Master mode: SCK, FS and MCK are output
MCK output
tM_SCKOR
SCK output
FS output
tM_SCKOF
tM_FSOH
tM_SDIS
tM_SDIH
tM_SCKO
tM_SDOH
tM_FSOV
tM_SDOV
SD output
LSB right ch.
MSB left ch.
SD input
Figure 39-18. I2S Timing Slave Mode
Slave mode: SCK and FS are input
tS_FSIH
SCK input
tS_SCKI
tS_FSIS
FS input
tS_SDIS
tS_SDOH
tS_SDIH
tS_SDOV
SD output
LSB rignt ch.
MSB left ch.
SD input
Figure 39-19. I2S Timing PDM2 Mode
PDM2 mode
tPDM2RS tPDM2RH
tPDM2LS
tPDM2LH
SCK input
SD input
© 2017 Microchip Technology Inc.
Left
Right
Left
Right
Datasheet Complete
Left
Right
40001895A-page 838
SAM DA1
Table 39-52. I2S Timing Characteristics and Requirements
Name
Description
Mode
VDD=1.8V
VDD=3.3V
Units
Min. Typ. Max. Min. Typ. Max.
tM_MCKOR
I2S MCK rise time(3)
Master mode /
Capacitive load CL =
15 pF
9.2
4.7
ns
tM_MCKOF
I2S MCK fall time(3)
Master mode /
Capacitive load CL =
15 pF
11.6
5.4
ns
dM_MCKO
I2S MCK duty cycle
Master mode
50
%
dM_MCKI
I2S MCK duty cycle
Master mode, pin is
input (1b)
tM_SCKOR
I2S SCK rise time(3)
Master mode /
Capacitive load CL =
15 pF
9
4.6
ns
tM_SCKOF
I2S SCK fall time(3)
Master mode /
Capacitive load CL =
15 pF
9.7
4.6
ns
dM_SCKO
I2S SCK duty cycle
Master mode
50
%
fM_SCKO, 1/
tM_SCKO
I2S SCK frequency
Master mode,
Supposing external
device response
delay is 30ns
7.8
9.2
MHz
fS_SCKI, 1/
tS_SCKI
I2S SCK frequency
Slave mode,
Supposing external
device response
delay is 30ns
12.8
13
MHz
dS_SCKO
I2S SCK duty cycle
Slave mode
tM_FSOV
FS valid time
Master mode
tM_FSOH
FS hold time
Master mode
-0.1
-0.1
ns
tS_FSIS
FS setup time
Slave mode
6
5.3
ns
tS_FSIH
FS hold time
Slave mode
0
0
ns
tM_SDIS
Data input setup time Master mode
36
25.9
ns
tM_SDIH
Data input hold time
-8.2
-8.2
ns
tS_SDIS
Data input setup time Slave mode
9.1
8.3
ns
tS_SDIH
Data input hold time
3.8
3.7
ns
tM_SDOV
Data output valid time Master transmitter
tM_SDOH
Data output hold time Master transmitter
tS_SDOV
Data output valid time Slave transmitter
© 2017 Microchip Technology Inc.
Master mode
Slave mode
47.1
50
47.3
50
47
50
50
47.2
50
50
2.4
-0.1
%
1.9
2.5
Datasheet Complete
%
1.9
-0.1
29.8
ns
ns
ns
19.7
ns
40001895A-page 839
SAM DA1
Name
Description
Mode
VDD=1.8V
VDD=3.3V
Units
Min. Typ. Max. Min. Typ. Max.
tS_SDOH
Data output hold time Slave transmitter
29.1
18.9
ns
tPDM2LS
Data input setup time Master mode PDM2
Left
35.5
25.3
ns
tPDM2LH
Data input hold time
Master mode PDM2
Left
-8.2
-8.2
ns
tPDM2RS
Data input setup time Master mode PDM2
Right
30.6
21.1
ns
tPDM2RH
Data input hold time
-7
-7
ns
1.
2.
3.
Master mode PDM2
Right
All timing characteristics given for 15pF capacitive load.
These values are based on simulations and not covered by test limits in production.
See I/O Pin Characteristics.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 840
SAM DA1
40.
Packaging Information
40.1
Thermal Considerations
40.1.1
Thermal Resistance Data
The following Table summarizes the thermal resistance data depending on the package.
Table 40-1. Thermal Resistance Data
Package Type
θJA
θJC
32-pin TQFP
69.5°C/W
27.1°C/W
48-pin TQFP
66.0°C/W
14.0°C/W
64-pin TQFP
61.8°C/W
13.7°C/W
32-pin QFN
40.5°C/W
16.0°C/W
48-pin QFN
31.9°C/W
11.7°C/W
Related Links
Junction Temperature
40.1.2
Junction Temperature
The average chip-junction temperature, TJ, in °C can be obtained from the following:
1.
2.
TJ = TA + (PD x θJA)
TJ = TA + (PD x (θHEATSINK + θJC))
where:
•
•
•
•
•
θJA = Package thermal resistance, Junction-to-ambient (°C/W), see Thermal Resistance Data
θJC = Package thermal resistance, Junction-to-case thermal resistance (°C/W), see Thermal
Resistance Data
θHEATSINK = Thermal resistance (°C/W) specification of the external cooling device
PD = Device power consumption (W)
TA = Ambient temperature (°C)
From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling
device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be
used to compute the resulting average chip-junction temperature TJ in °C.
Related Links
Thermal Resistance Data
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 841
SAM DA1
40.2
Package Drawings
40.2.1
64 pin TQFP
Table 40-2. Device and Package Maximum Weight
300
mg
Table 40-3. Package Characteristics
Moisture Sensitivity Level
MSL3
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 842
SAM DA1
Table 40-4. Package Reference
40.2.2
JEDEC Drawing Reference
MS-026
JESD97 Classification
E3
48 pin TQFP
Table 40-5. Device and Package Maximum Weight
140
© 2017 Microchip Technology Inc.
mg
Datasheet Complete
40001895A-page 843
SAM DA1
Table 40-6. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 40-7. Package Reference
40.2.3
JEDEC Drawing Reference
MS-026
JESD97 Classification
E3
48 pin QFN
bbb C
Drawings not scaled
R
A1
aaa C A
A
D
ccc C
A
B
A3
A1
C B
1
aaa
PIN 1 Corner
E
C
Top View
Seating Plane
Side View
eee C A B
D2
S
37
36
eee C A B
1
E2
e
25
12
24
nX L
COMMON DIMENSIONS
PIN 1 ID
48
13
nX b
ddd M C A B
Exposed Die
Attach Pad
(Unit of Measure = mm)
Symbol
MIN
NOM
MAX
A
A1
A2
A3
D/E
D2/E2
L
R
S
b
e
0.80
0.00
0.85
0.035
0.65
0.203 REF
7.00 BSC
5.15
0.40
0.125
0.90
0.05
5.05
0.35
0.100
0.20
NOTE
5.25
0.45
0.150
0.04
0.30
0.25
0.5 BSC
Tolerances of Form and Position
aaa
0.100
bbb
0.100
ccc
0.08
ddd
0.100
eee
0.100
n
48
2
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-220, Variation VKKD-2 for proper dimensions, tolerances, datums, etc.
(excepted D2/E2 Min and Nom).
2. Dimensions b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip.
If the terminal has the optical radius on the other end of the terminal, the dimensions should not be measured in that radius area.
Package Drawing Contact:
packagedrawings@atmel.com
© 2017 Microchip Technology Inc.
07/01/16
TITLE
GPC
DRAWING NO.
REV.
48 Leads - 0.50mm Pitch, 7x7x0.9mm Body size
Very Thin Quad Flat Lead Package (VQFN) Sawn Wettable Flanks
ZLH
22
A
Datasheet Complete
40001895A-page 844
SAM DA1
Note: The exposed die attach pad is not connected electrically inside the device.
Table 40-8. Device and Package Maximum Weight
140
mg
Table 40-9. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 40-10. Package Reference
JEDEC Drawing Reference
MO-220
JESD97 Classification
E3
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 845
SAM DA1
40.2.4
32 pin TQFP
Table 40-11. Device and Package Maximum Weight
100
mg
Table 40-12. Package Charateristics
Moisture Sensitivity Level
MSL3
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 846
SAM DA1
Table 40-13. Package Reference
40.2.5
JEDEC Drawing Reference
MS-026
JESD97 Classification
E3
32 pin QFN
Drawings not scaled
bbb C
ccc C
A
A2
aaa C A
A
D
A3
R
B
A1
aaa C B
1
PIN 1 Corner
E
Seating Plane
C
Top View
Side View
eee C A B
D2
S
25
24
eee C A B
1
E2
8
17
16
9
nX b
nX L
ddd M C A B
Bottom View
COMMON DIMENSIONS
PIN 1 ID
32
Exposed Die
Attach Pad
(Unit of Measure = mm)
Symbol
MIN
NOM
MAX
A
A1
A2
A3
D/E
D2/E2
L
R
S
b
e
0.80
0.00
0.85
0.035
0.65
0.203 REF
5.00 BSC
3.6
0.40
0.125
0.90
0.05
3.5
0.35
0.10
0.20
NOTE
3.7
0.45
0.15
0.04
0.30
0.25
0.5 BSC
Tolerances of Form and Position
aaa
0.100
bbb
0.100
ccc
0.08
ddd
0.100
eee
0.100
n
32
2
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-220, Variation VHHD-5 for proper dimensions, tolerances, datums, etc.
(excepted D2/E2 Nom and Max).
2. Dimensions b applies to metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip.
If the terminal has the optical radius on the other end of the terminal, the dimensions should not be measured in that radius area.
Package Drawing Contact:
packagedrawings@atmel.com
06/24/16
TITLE
GPC
DRAWING NO.
REV.
32 Leads - 0.50mm Pitch, 5x5x0.9mm Body size
Very Thin Quad Flat Lead Package (VQFN) Sawn Wettable Flanks
ZBS
21
A
Note: The exposed die attach pad is connected inside the device to GND and GNDANA.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 847
SAM DA1
Table 40-14. Device and Package Maximum Weight
90
mg
Table 40-15. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 40-16. Package Reference
40.3
JEDEC Drawing Reference
MO-220
JESD97 Classification
E3
Soldering Profile
The following table gives the recommended soldering profile from J-STD-20.
Table 40-17.
Profile Feature
Green Package
Average Ramp-up Rate (217°C to peak)
3°C/s max.
Preheat Temperature 175°C ±25°C
150-200°C
Time Maintained Above 217°C
60-150s
Time within 5°C of Actual Peak Temperature
30s
Peak Temperature Range
260°C
Ramp-down Rate
6°C/s max.
Time 25°C to Peak Temperature
8 minutes max.
A maximum of three reflow passes is allowed per component.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 848
SAM DA1
41.
Schematic Checklist
41.1
Introduction
This chapter describes a common checklist which should be used when starting and reviewing the
schematics for a SAM DA1 design. This chapter illustrates a recommended power supply connection,
how to connect external analog references, programmer, debugger, oscillator and crystal.
41.1.1
Operation in Noisy Environment
If the device is operating in an environment with much electromagnetic noise it must be protected from
this noise to ensure reliable operation. In addition to following best practice EMC design guidelines, the
recommendations listed in the schematic checklist sections must be followed. In particular placing
decoupling capacitors very close to the power pins, a RC-filter on the RESET pin, and a pull-up resistor
on the SWCLK pin is critical for reliable operations. It is also relevant to eliminate or attenuate noise in
order to avoid that it reaches supply pins, I/O pins and crystals.
41.2
Power Supply
The SAM DA1 supports a single power supply from 2.7V - 3.63V.
41.2.1
Power Supply Connections
Figure 41-1. Power Supply Schematic
Close to device
(for every pin)
2.7V-3.63V
VDDANA
10µF
100nF
GNDANA
VDDIO
100nF
VDDIN
100nF
VDDCORE
10µF
1µF
GND
Table 41-1. Power Supply Connections, VDDCORE From Internal Regulator
Signal Name Recommended Pin Connection
Description
VDDIO
Digital supply voltage
2.7V - 3.63V
Decoupling/filtering capacitors 100nF(1)(2) and 10μF(1)
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 849
SAM DA1
Signal Name Recommended Pin Connection
Description
Decoupling/filtering inductor 10μH(1)(3)
VDDANA
2.7V - 3.63V
Decoupling/filtering capacitors 100nF(1)(2) and 10μF(1)
Analog supply voltage
Ferrite bead(4) prevents the VDD noise interfering the
VDDANA
VDDCORE
Decoupling/filtering capacitor 1μF(1)(2)
Core supply voltage / external
decoupling pin
GND
Ground
GNDANA
Ground for the analog power
domain
Note:
1. These values are only given as typical examples.
2. Decoupling capacitor should be placed close to the device for each supply pin pair in the signal
group, low ESR caps should be used for better decoupling.
3. An inductor should be added between the external power and the VDD for power filtering.
4. Ferrite bead has better filtering performance than the common inductor at high frequencies. It can
be added between VDD and VDDANA for preventing digital noise from entering the analog power
domain. The bead should provide enough impedance (e.g. 50Ω at 20MHz and 220Ω at 100MHz)
for separating the digital power from the analog power domain. Make sure to select a ferrite bead
designed for filtering applications with a low DC resistance to avoid a large voltage drop across the
ferrite bead.
41.3
External Analog Reference Connections
The following schematic checklist is only necessary if the application is using one or more of the external
analog references. If the internal references are used instead, the following circuits are not necessary.
Figure 41-2. External Analog Reference Schematic With Two References
Close to device
(for every pin)
AREFA
EXTERNAL
REFERENCE 1
4.7µF
100nF
GND
AREFB
EXTERNAL
REFERENCE 2
© 2017 Microchip Technology Inc.
4.7µF
100nF
GND
Datasheet Complete
40001895A-page 850
SAM DA1
Figure 41-3. External Analog Reference Schematic With One Reference
Close to device
(for every pin)
AREFA
EXTERNAL
REFERENCE
4.7µF
100nF
GND
AREFB
100nF
GND
Table 41-2. External Analog Reference Connections
Signal Name
Recommended Pin Connection
Description
AREFx
1.0V to VDDANA - 0.6V for ADC
External reference from AREFx pin on
the analog port
1.0V to VDDANA- 0.6V for DAC
Decoupling/filtering capacitors
100nF(1)(2) and 4.7μF(1)
GND
1.
2.
41.4
Ground
These values are given as a typical example.
Decoupling capacitor should be placed close to the device for each supply pin pair in the signal
group.
External Reset Circuit
The external reset circuit is connected to the RESET pin when the external reset function is used. If the
external reset function has been disabled, the circuit is not necessary. The reset switch can also be
removed, if the manual reset is not necessary. The RESET pin itself has an internal pull-up resistor,
hence it is optional to also add an external pull-up resistor.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 851
SAM DA1
Figure 41-4. External Reset Circuit Example Schematic
VDD
10kΩ
330Ω
RESET
100nF
GND
A pull-up resistor makes sure that the reset does not go low unintended causing a device reset. An
additional resistor has been added in series with the switch to safely discharge the filtering capacitor, i.e.
preventing a current surge when shorting the filtering capacitor which again causes a noise spike that can
have a negative effect on the system.
Table 41-3. Reset Circuit Connections
Signal Name
Recommended Pin Connection
Description
RESET
Reset low level threshold voltage
VDDIO = 1.6V - 2.0V: Below 0.33 * VDDIO
Reset pin
VDDIO = 2.7V - 3.6V: Below 0.36 * VDDIO
Decoupling/filter capacitor 100nF(1)
Pull-up resistor 10kΩ(1)(2)
Resistor in series with the switch 330Ω(1)
1.
2.
41.5
These values are given as a typical example.
The SAM DA1 features an internal pull-up resistor on the RESET pin, hence an external pull-up is
optional.
Clocks and Crystal Oscillators
The SAM DA1 can be run from internal or external clock sources, or a mix of internal and external
sources. An example of usage will be to use the internal 8MHz oscillator as source for the system clock,
and an external 32.768kHz watch crystal as clock source for the Real-Time counter (RTC).
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 852
SAM DA1
41.5.1
External Clock Source
Figure 41-5. External Clock Source Example Schematic
External
Clock
XIN
XOUT/GPIO
NC/GPIO
Table 41-4. External Clock Source Connections
41.5.2
Signal Name
Recommended Pin Connection
Description
XIN
XIN is used as input for an external clock signal
Input for inverting oscillator pin
XOUT/GPIO
Can be left unconnected or used as normal GPIO
Crystal Oscillator
Figure 41-6. Crystal Oscillator Example Schematic
XIN
15pF
XOUT
15pF
The crystal should be located as close to the device as possible. Long signal lines may cause too high
load to operate the crystal, and cause crosstalk to other parts of the system.
Table 41-5. Crystal Oscillator Checklist
Signal Name
Recommended Pin Connection
Description
XIN
Load capacitor 15pF(1)(2)
External crystal between 0.4 to 30MHz
XOUT
Load capacitor 15pF(1)(2)
1.
2.
41.5.3
These values are given only as typical example.
Decoupling capacitor should be placed close to the device for each supply pin pair in the signal
group.
External Real Time Oscillator
The low frequency crystal oscillator is optimized for use with a 32.768kHz watch crystal. When selecting
crystals, load capacitance and crystal’s Equivalent Series Resistance (ESR) must be taken into
consideration. Both values are specified by the crystal vendor.
The SAM DA1 oscillator is optimized for very low power consumption, hence close attention should be
made when selecting crystals, see the table below for maximum ESR recommendations on 9pF and
12.5pF crystals.
The Low-frequency Crystal Oscillator provides an internal load capacitance of typical values available in
Table , 32kHz Crystal Oscillator Characteristics. This internal load capacitance and PCB capacitance can
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 853
SAM DA1
allow to use a Crystal inferior to 12.5pF load capacitance without external capacitors as shown in the
following figure.
Table 41-6. Maximum ESR Recommendation for 32.768kHz Crystal
Crystal CL (pF)
Max ESR [kΩ]
12.5
313
Note: Maximum ESR is typical value based on characterization. These values are not covered by test
limits in production.
Figure 41-7. External Real Time Oscillator without Load Capacitor
XIN32
32.768kHz
XOUT32
However, to improve Crystal accuracy and Safety Factor, it can be recommended by crystal datasheet to
add external capacitors as shown in the next figure.
To find suitable load capacitance for a 32.768kHz crystal, consult the crystal datasheet.
Figure 41-8. External Real Time Oscillator with Load Capacitor
XIN32
22pF
32.768kHz
XOUT32
22pF
Table 41-7. External Real Time Oscillator Checklist
Signal Name
Recommended Pin Connection
Description
XIN32
Load capacitor 22pF(1)(2)
Timer oscillator input
XOUT32
Load capacitor 22pF(1)(2)
Timer oscillator output
1.
2.
These values are given only as typical examples.
Decoupling capacitor should be placed close to the device for each supply pin pair in the signal
group.
Note: In order to minimize the cycle-to-cycle jitter of the external oscillator, keep the neighboring pins as
steady as possible. For neighboring pin details, refer to the Oscillator Pinout section.
Related Links
Oscillator Pinout
41.5.4
Calculating the Correct Crystal Decoupling Capacitor
In order to calculate correct load capacitor for a given crystal one can use the model shown in the next
figure which includes internal capacitors CLn, external parasitic capacitance CELn and external load
capacitance CPn.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 854
SAM DA1
CEL1
CP1
Internal
CL1
XIN
CL2
XOUT
External
Figure 41-9. Crystal Circuit With Internal, External and Parasitic Capacitance
CP2
CEL2
Using this model the total capacitive load for the crystal can be calculated as shown in the equation
below:
�tot =
��1 + ��1 + �EL1 ��2 + ��2 + �EL2
��1 + ��1 + �EL1 + ��2 + ��2 + �EL2
where Ctot is the total load capacitance seen by the crystal, this value should be equal to the load
capacitance value found in the crystal manufacturer datasheet.
The parasitic capacitance CELn can in most applications be disregarded as these are usually very small. If
accounted for the value is dependent on the PCB material and PCB layout.
For some crystal the internal capacitive load provided by the device itself can be enough. To calculate the
total load capacitance in this case. CELn and CPn are both zero, CL1 = CL2 = CL, and the equation reduces
to the following:
�tot =
��
2
The next table shows the device equivalent internal pin capacitance.
Table 41-8. Equivalent Internal Pin Capacitance
Symbol
Value
Description
CXIN32
3.05pF
Equivalent internal pin capacitance
CXOUT32
3.29pF
Equivalent internal pin capacitance
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 855
SAM DA1
41.6
Unused or Unconnected Pins
For unused pins the default state of the pins for the will give the lowest current leakage. There is thus no
need to do any configuration of the unused pins in order to lower the power consumption.
41.7
Programming and Debug Ports
For programming and/or debugging the SAM DA1 the device should be connected using the Serial Wire
Debug, SWD, interface. Currently the SWD interface is supported by several Atmel and third party
programmers and debuggers, like the SAM-ICE, JTAGICE3 or SAM SAM DA1 Xplained Pro (SAM SAM
DA1 evaluation kit) Embedded Debugger.
Refer to the SAM-ICE, JTAGICE3 or SAM SAM DA1 Xplained Pro user guides for details on debugging
and programming connections and options. For connecting to any other programming or debugging tool,
refer to that specific programmer or debugger’s user guide.
The SAM SAM DA1 Xplained Pro evaluation board for the SAM SAM DA1 supports programming and
debugging through the onboard embedded debugger so no external programmer or debugger is needed.
Note that a pull-up resistor on the SWCLK pin is critical for reliable operations. Refer to related link for
more information.
Figure 41-10. SWCLK Circuit Connections
VDD
1kΩ
SWCLK
Table 41-9. SWCLK Circuit Connections
Pin Name
Description
Recommended Pin Connection
SWCLK
Serial wire clock pin
Pull-up resistor 1kΩ
Related Links
Operation in Noisy Environment
41.7.1
Cortex Debug Connector (10-pin)
For debuggers and/or programmers that support the Cortex Debug Connector (10-pin) interface the
signals should be connected as shown in the figure below with details described in the next table.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 856
SAM DA1
Figure 41-11. Cortex Debug Connector (10-pin)
VDD
Cortex Debug Connector
(10-pin)
VTref
GND
1
SWDIO
SWDCLK
GND
NC
NC
NC
NC
nRESET
RESET
SWCLK
SWDIO
GND
Table 41-10. Cortex Debug Connector (10-pin)
Header Signal
Name
Description
Recommended Pin
Connection
SWDCLK
Serial wire clock pin
Pull-up resistor 1kΩ
SWDIO
Serial wire bidirectional data pin
RESET
Target device reset pin, active low
Refer to External Reset Circuit.
41.7.2
VTref
Target voltage sense, should be connected to the
device VDD
GND
Ground
10-pin JTAGICE3 Compatible Serial Wire Debug Interface
The JTAGICE3 debugger and programmer does not support the Cortex Debug Connector (10-pin)
directly, hence a special pinout is needed to directly connect the SAM DA1 to the JTAGICE3, alternatively
one can use the JTAGICE3 squid cable and manually match the signals between the JTAGICE3 and
SAM DA1. The following figure describes how to connect a 10-pin header that support connecting the
JTAGICE3 directly to the SAM DA1 without the need for a squid cable.
To connect the JTAGICE3 programmer and debugger to the SAM DA1, one can either use the JTAGICE3
squid cable, or use a 10-pin connector as shown in the figure below with details given in the next table to
connect to the target using the JTAGICE3 50 mil cable directly.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 857
SAM DA1
Figure 41-12. 10-pin JTAGICE3 Compatible Serial Wire Debug Interface
10-pin JTAGICE3 Compatible
VDD
Serial Wire Debug Header
SWDCLK
1
NC
SWDIO
GND
RESET
VTG
RESET
NC
NC
NC
NC
SWCLK
SWDIO
GND
Table 41-11. 10-pin JTAGICE3 Compatible Serial Wire Debug Interface
41.7.3
Header Signal Name
Description
SWDCLK
Serial wire clock pin
SWDIO
Serial wire bidirectional data pin
RESET
Target device reset pin, active low
VTG
Target voltage sense, should be connected to the device VDD
GND
Ground
20-pin IDC JTAG Connector
For debuggers and/or programmers that support the 20-pin IDC JTAG Connector, e.g. the SAM-ICE, the
signals should be connected as shown in the next figure with details described in the table.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 858
SAM DA1
Figure 41-13. 20-pin IDC JTAG Connector
VDD
20-pin IDC JTAG Connector
VCC
NC
1
NC
GND
NC
GND
SWDIO
GND
SWDCLK
GND
NC
GND
NC
GND*
nRESET
GND*
NC
GND*
NC
GND*
RESET
SWCLK
SWDIO
GND
Table 41-12. 20-pin IDC JTAG Connector
Header Signal Name Description
41.8
SWDCLK
Serial wire clock pin
SWDIO
Serial wire bidirectional data pin
RESET
Target device reset pin, active low
VCC
Target voltage sense, should be connected to the device VDD
GND
Ground
GND*
These pins are reserved for firmware extension purposes. They can be left open
or connected to GND in normal debug environment. They are not essential for
SWD in general.
USB Interface
The USB interface consists of a differential data pair (D+/D-) and a power supply (VBUS, GND). Refer to
the Electrical Characteristics for operating voltages which will allow USB operation.
Table 41-13. USB Interface Checklist
Signal
Name
D+
Recommended Pin Connection
•
•
D-
•
The impedance of the pair should be matched on the PCB to
minimize reflections.
USB differential tracks should be routed with the same
characteristics (length, width, number of vias, etc.)
Signals should be routed as parallel as possible, with a
minimum number of angles and vias
© 2017 Microchip Technology Inc.
Datasheet Complete
Description
USB full speed / low
speed positive data
upstream pin
USB full speed / low
speed negative data
upstream pin
40001895A-page 859
SAM DA1
Figure 41-14. Low Cost USB Interface Example Schematic
USB
Connector
VBUS
D+
DGND
VBUS
USB
Differential
Data Line Pair
USB_D+
USB_D-
Shield
GND (Board)
It is recommended to increase ESD protection on the USB D+, D-, and VBUS lines using dedicated
transient suppressors. These protections should be located as close as possible to the USB connector to
reduce the potential discharge path and reduce discharge propagation within the entire system.
The USB FS cable includes a dedicated shield wire that should be connected to the board with caution.
Special attention should be paid to the connection between the board ground plane and the shield from
the USB connector and the cable.
Tying the shield directly to ground would create a direct path from the ground plane to the shield, turning
the USB cable into an antenna. To limit the USB cable antenna effect, it is recommended to connect the
shield and ground through an RC filter.
Figure 41-15. Protected USB Interface Example Schematic
VBUS
USB Transient
protection
USB
Connector
USB
Differential
Data Line Pair
VBUS
D+
DGND
RC Filter
(GND/Shield
Connection)
© 2017 Microchip Technology Inc.
USB_D-
4.5nF
1MO
Shield
USB_D+
GND (Board)
Datasheet Complete
40001895A-page 860
SAM DA1
42.
Errata
The device variant (last letter of the ordering number) is independent of the die revision
(DSU.DID.REVISION): The device variant denotes functional differences, whereas the die revision marks
evolution of the die.
42.1
Die Revision E
42.1.1
DFLL48M
1 – The DFLL clock must be requested before being configured
otherwise a write access to a DFLL register can freeze the device.
Errata reference: 9905
Fix/Workaround:
Write a zero to the DFLL ONDEMAND bit in the DFLLCTRL register before
configuring the DFLL module.
2 – The DFLL status bits in the PCLKSR register during the USB clock
recovery mode can be wrong after a USB suspend state.
Errata reference: 11938
Fix/Workaround:
Do not monitor the DFLL status bits in the PCLKSR register during the USB
clock recovery mode.
3 – If the DFLL48M reaches the maximum or minimum COARSE or
FINE calibration values during the locking sequence, an out of bounds
interrupt will be generated. These interrupts will be generated even if
the final calibration values at DFLL48M lock are not at maximum or
minimum, and might therefore be false out of bounds interrupts.
Errata reference: 10669
Fix/Workaround:
Check that the lockbits: DFLLLCKC and DFLLLCKF in the SYSCTRL
Interrupt Flag Status and Clear register (INTFLAG) are both set before
enabling the DFLLOOB interrupt.
42.1.2
FDPLL
1 – When changing on-the-fly the FDPLL ratio in DPLLnRATIO register,
STATUS.DPLLnLDRTO will not be set when the ratio update will be
completed.
Errata reference: 15753
Fix/Workaround:
Wait for the interruption flag INTFLAG.DPLLnLDRTO instead.
42.1.3
I2S
1 – I2S RX serializer in LSBIT mode (SERCTRL.BITREV set) only works
when the slot size is 32 bits.
Errata reference: 13320
Fix/Workaround:
In SERCTRL.SERMODE RX, SERCTRL.BITREV LSBIT must be used with
CLKCTRL.SLOTSIZE 32.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 861
SAM DA1
42.1.4
Device
1 – The SYSTICK calibration value is incorrect.
Errata reference: 14155
Fix/Workaround:
The correct SYSTICK calibration value is 0x40000000. This value should not
be used to initialize the Systick RELOAD value register, which should be
initialized instead with a value depending on the main clock frequency and
on the tick period required by the application. For a detailed description of
the SYSTICK module, refer to the official ARM Cortex-M0+ documentation.
2 – Pulldown functionality is not available on GPIO pin PA24 and PA25
Errata reference: 15051
Fix/Workaround:
None
3 – The TCC interrupt flags
INTFLAG.ERR,INTFLAG.DFS,INTFLAG.UFS,INTFLAG.CNT,
INTFLAG.FAULTA,INTFLAG.FAULTB, INTFLAG.FAULT0,
INTFLAG.FAULT1 are not always properly set when using
asynchronous TCC features.
Errata reference: 15179
Fix/Workaround:
Do not use these flags when using asynchronous TCC features.
4 – On pin PA24 and PA25 the pull-up and pull-down configuration is
not disabled automatically when alternative pin function is enabled
except for USB.
Errata reference: 12368
Fix/Workaround:
For pin PA24 and PA25, the GPIO pull-up and pull-down must be disabled
before enabling alternative functions on them.
5 – If APB clock is stopped and GCLK clock is running, APB read
access to read-synchronized registers will freeze the system. The CPU
and the DAP AHB-AP are stalled, as a consequence debug operation is
impossible.
Errata reference: 10416
Fix/Workaround:
Do not make read access to read-synchronized registers when APB clock is
stopped and GCLK is running. To recover from this situation, power cycle the
device or reset the device using the RESETN pin.
6 – In I2C Slave mode, writing the CTRLB register when in the AMATCH
or DRDY interrupt service routines can cause the state machine to
reset.
Errata reference: 13574
Fix/Workaround:
Write CTRLB.ACKACT to 0 using the following sequence:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = 0;
// Re-enable interrupts if applicable.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 862
SAM DA1
Write CTRLB.ACKACT to 1 using the following sequence:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
// Re-enable interrupts if applicable.
Otherwise, only write to CTRLB in the AMATCH or DRDY interrupts if it is to
close out a transaction.
When not closing a transaction, clear the AMATCH interrupt by writing a 1 to
its bit position instead of using CTRLB.CMD. The DRDY interrupt is
automatically cleared by reading/writing to the DATA register in smart mode.
If not in smart mode, DRDY should be cleared by writing a 1 to its bit
position.
Code replacements examples:
Current:
SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
Change to:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
// Re-enable interrupts if applicable.
Current:
SERCOM - CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
Change to:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = 0;
// Re-enable interrupts if applicable.
Current:
/* ACK or NACK address */
SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
Change to:
// CMD=0x3 clears all interrupts, so to keep the result similar,
// PREC is cleared if it was set.
if (SERCOM - INTFLAG.bit.PREC) SERCOM - INTFLAG.reg =
SERCOM_I2CS_INTFLAG_PREC;
SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
7 – If the external XOSC32K is broken, neither the external pin RST nor
the GCLK software reset can reset the GCLK generators using
XOSC32K as source clock.
Errata reference: 12164
Fix/Workaround:
Do a power cycle to reset the GCLK generators after an external XOSC32K
failure.
42.1.5
DSU
1 – The MBIST ""Pause-on-Error"" feature is not functional on this
device.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 863
SAM DA1
Errata reference: 14324
Fix/Workaround:
Do not use the ""Pause-on-Error"" feature.
42.1.6
DMAC
1 – When at least one channel using linked descriptors is already
active, enabling another DMA channel (with or without linked
descriptors) can result in a channel Fetch Error (FERR) or an incorrect
descriptor fetch.
This happens if the channel number of the channel being enabled is
lower than the channel already active.
Errata reference: 15683
Fix/Workaround:
When enabling a DMA channel while other channels using linked descriptors
are already active, the channel number of the new channel enabled must be
greater than the other channel numbers.
2 – If data is written to CRCDATAIN in two consecutive instructions, the
CRC computation may be incorrect.
Errata reference: 13507
Fix/Workaround:
Add a NOP instruction between each write to CRCDATAIN register.
42.1.7
EIC
1 – When the EIC is configured to generate an interrupt on a low level
or rising edge or both edges (CONFIGn.SENSEx) with the filter enabled
(CONFIGn.FILTENx), a spurious flag might appear for the dedicated pin
on the INTFLAG.EXTINT[x] register as soon as the EIC is enabled using
CTRLA ENABLE bit.
Errata reference: 15341
Fix/Workaround:
Clear the INTFLAG bit once the EIC enabled and before enabling the
interrupts.
42.1.8
NVMCTRL
1 – The NVMCTRL.INTFLAG.READY bit is not updated after a
RWWEEER command and will keep holding a 1 value. If a new
RWWEEER command is issued it can be accepted even if the previous
RWWEEER command is ongoing. The ongoing NVM RWWEER will be
aborted, the content of the row under erase will be unpredictable.
Errata reference: 13588
Fix/Workaround:
Perform a dummy write to the page buffer right before issuing a RWWEEER
command. This will make the INTFLAG.READY bit behave as expected.
2 – Default value of MANW in NVM.CTRLB is 0.
This can lead to spurious writes to the NVM if a data write is done
through a pointer with a wrong address corresponding to NVM area.
Errata reference: 13134
Fix/Workaround:
Set MANW in the NVM.CTRLB to 1 at startup
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 864
SAM DA1
3 – When external reset is active it causes a high leakage current on
VDDIO.
Errata reference: 13446
Fix/Workaround:
Minimize the time external reset is active.
42.1.9
SERCOM
1 – In USART autobaud mode, missing stop bits are not recognized as
inconsistent sync (ISF) or framing (FERR) errors.
Errata reference: 13852
Fix/Workaround:
None
2 – If the SERCOM is enabled in SPI mode with SSL detection enabled
(CTRLB.SSDE) and CTRLB.RXEN=1, an erroneous slave select low
interrupt (INTFLAG.SSL) can be generated.
Errata reference: 13369
Fix/Workaround:
Enable the SERCOM first with CTRLB.RXEN=0. In a subsequent write, set
CTRLB.RXEN=1.
42.1.10 TCC
1 – When a capture is done using PWP or PPW mode, CC0 and CC1 are
always fill with the period. It is not possible to get the pulse width.
Errata reference: 14475
Fix/Workaround:
Use the PWP feature on TC instead of TCC
2 – FCTRLX.CAPTURE[CAPTMARK] does not work as described in the
datasheet. CAPTMARK cannot be used to identify captured values
triggered by fault inputs source A or B on the same channel.
Errata reference: 13316
Fix/Workaround:
Use two different channels to timestamp FaultA and FaultB.
3 – Using TCC in dithering mode with external retrigger events can lead
to unexpected stretch of right aligned pulses, or shrink of left aligned
pulses.
Errata reference: 15625
Fix/Workaround:
Do not use retrigger events/actions when TCC is configured in dithering
mode.
4 – Advance capture mode (CAPTMIN CAPTMAX LOCMIN LOCMAX
DERIV0) doesn’t work if an upper channel is not in one of these mode.
Example: when CC[0]=CAPTMIN, CC[1]=CAPTMAX, CC[2]=CAPTEN,
and CC[3]=CAPTEN, CAPTMIN and CAPTMAX won’t work.
Errata reference: 14817
Fix/Workaround:
Basic capture mode must be set in lower channel and advance capture
mode in upper channel.
Example: CC[0]=CAPTEN , CC[1]=CAPTEN , CC[2]=CAPTMIN,
CC[3]=CAPTMAX
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 865
SAM DA1
All capture will be done as expected.
5 – In RAMP 2 mode with Fault keep, qualified and restart:
If a fault occurred at the end of the period during the qualified state, the
switch to the next ramp can have two restarts.
Errata reference: 13262
Fix/Workaround:
Avoid faults few cycles before the end or the beginning of a ramp.
42.2
Die Revision F
42.2.1
DFLL48M
1 – The DFLL clock must be requested before being configured
otherwise a write access to a DFLL register can freeze the device.
Errata reference: 9905
Fix/Workaround:
Write a zero to the DFLL ONDEMAND bit in the DFLLCTRL register before
configuring the DFLL module.
2 – The DFLL status bits in the PCLKSR register during the USB clock
recovery mode can be wrong after a USB suspend state.
Errata reference: 11938
Fix/Workaround:
Do not monitor the DFLL status bits in the PCLKSR register during the USB
clock recovery mode.
3 – If the DFLL48M reaches the maximum or minimum COARSE or
FINE calibration values during the locking sequence, an out of bounds
interrupt will be generated. These interrupts will be generated even if
the final calibration values at DFLL48M lock are not at maximum or
minimum, and might therefore be false out of bounds interrupts.
Errata reference: 10669
Fix/Workaround:
Check that the lockbits: DFLLLCKC and DFLLLCKF in the SYSCTRL
Interrupt Flag Status and Clear register (INTFLAG) are both set before
enabling the DFLLOOB interrupt.
42.2.2
FDPLL
1 – When changing on-the-fly the FDPLL ratio in DPLLnRATIO register,
STATUS.DPLLnLDRTO will not be set when the ratio update will be
completed.
Errata reference: 15753
Fix/Workaround:
Wait for the interruption flag INTFLAG.DPLLnLDRTO instead.
42.2.3
I2S
1 – I2S RX serializer in LSBIT mode (SERCTRL.BITREV set) only works
when the slot size is 32 bits.
Errata reference: 13320
Fix/Workaround:
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 866
SAM DA1
In SERCTRL.SERMODE RX, SERCTRL.BITREV LSBIT must be used with
CLKCTRL.SLOTSIZE 32.
42.2.4
Device
1 – The SYSTICK calibration value is incorrect.
Errata reference: 14155
Fix/Workaround:
The correct SYSTICK calibration value is 0x40000000. This value should not
be used to initialize the Systick RELOAD value register, which should be
initialized instead with a value depending on the main clock frequency and
on the tick period required by the application. For a detailed description of
the SYSTICK module, refer to the official ARM Cortex-M0+ documentation.
2 – On pin PA24 and PA25 the pull-up and pull-down configuration is
not disabled automatically when alternative pin function is enabled
except for USB.
Errata reference: 12368
Fix/Workaround:
For pin PA24 and PA25, the GPIO pull-up and pull-down must be disabled
before enabling alternative functions on them.
3 – If APB clock is stopped and GCLK clock is running, APB read
access to read-synchronized registers will freeze the system. The CPU
and the DAP AHB-AP are stalled, as a consequence debug operation is
impossible.
Errata reference: 10416
Fix/Workaround:
Do not make read access to read-synchronized registers when APB clock is
stopped and GCLK is running. To recover from this situation, power cycle the
device or reset the device using the RESETN pin.
4 – If the external XOSC32K is broken, neither the external pin RST nor
the GCLK software reset can reset the GCLK generators using
XOSC32K as source clock.
Errata reference: 12164
Fix/Workaround:
Do a power cycle to reset the GCLK generators after an external XOSC32K
failure.
42.2.5
DSU
1 – The MBIST ""Pause-on-Error"" feature is not functional on this
device.
Errata reference: 14324
Fix/Workaround:
Do not use the ""Pause-on-Error"" feature.
42.2.6
DMAC
1 – When at least one channel using linked descriptors is already
active, enabling another DMA channel (with or without linked
descriptors) can result in a channel Fetch Error (FERR) or an incorrect
descriptor fetch.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 867
SAM DA1
This happens if the channel number of the channel being enabled is
lower than the channel already active.
Errata reference: 15683
Fix/Workaround:
When enabling a DMA channel while other channels using linked descriptors
are already active, the channel number of the new channel enabled must be
greater than the other channel numbers.
2 – If data is written to CRCDATAIN in two consecutive instructions, the
CRC computation may be incorrect.
Errata reference: 13507
Fix/Workaround:
Add a NOP instruction between each write to CRCDATAIN register.
42.2.7
EIC
1 – When the EIC is configured to generate an interrupt on a low level
or rising edge or both edges (CONFIGn.SENSEx) with the filter enabled
(CONFIGn.FILTENx), a spurious flag might appear for the dedicated pin
on the INTFLAG.EXTINT[x] register as soon as the EIC is enabled using
CTRLA ENABLE bit.
Errata reference: 15341
Fix/Workaround:
Clear the INTFLAG bit once the EIC enabled and before enabling the
interrupts.
42.2.8
NVMCTRL
1 – Default value of MANW in NVM.CTRLB is 0.
This can lead to spurious writes to the NVM if a data write is done
through a pointer with a wrong address corresponding to NVM area.
Errata reference: 13134
Fix/Workaround:
Set MANW in the NVM.CTRLB to 1 at startup
42.2.9
SERCOM
1 – In USART autobaud mode, missing stop bits are not recognized as
inconsistent sync (ISF) or framing (FERR) errors.
Errata reference: 13852
Fix/Workaround:
None
42.2.10 TCC
1 – FCTRLX.CAPTURE[CAPTMARK] does not work as described in the
datasheet. CAPTMARK cannot be used to identify captured values
triggered by fault inputs source A or B on the same channel.
Errata reference: 13316
Fix/Workaround:
Use two different channels to timestamp FaultA and FaultB.
2 – Using TCC in dithering mode with external retrigger events can lead
to unexpected stretch of right aligned pulses, or shrink of left aligned
pulses.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 868
SAM DA1
Errata reference: 15625
Fix/Workaround:
Do not use retrigger events/actions when TCC is configured in dithering
mode.
3 – Advance capture mode (CAPTMIN CAPTMAX LOCMIN LOCMAX
DERIV0) doesn’t work if an upper channel is not in one of these mode.
Example: when CC[0]=CAPTMIN, CC[1]=CAPTMAX, CC[2]=CAPTEN,
and CC[3]=CAPTEN, CAPTMIN and CAPTMAX won’t work.
Errata reference: 14817
Fix/Workaround:
Basic capture mode must be set in lower channel and advance capture
mode in upper channel.
Example: CC[0]=CAPTEN , CC[1]=CAPTEN , CC[2]=CAPTMIN,
CC[3]=CAPTMAX
All capture will be done as expected.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 869
SAM DA1
43.
Conventions
43.1
Numerical Notation
Table 43-1. Numerical Notation
43.2
Symbol
Description
165
Decimal number
0b0101
Binary number (example 0b0101 = 5 decimal)
'0101'
Binary numbers are given without prefix if
unambiguous.
0x3B24
Hexadecimal number
X
Represents an unknown or don't care value
Z
Represents a high-impedance (floating) state for
either a signal or a bus
Memory Size and Type
Table 43-2. Memory Size and Bit Rate
43.3
Symbol
Description
KB (kbyte)
kilobyte (210 = 1024)
MB (Mbyte)
megabyte (220 = 1024*1024)
GB (Gbyte)
gigabyte (230 = 1024*1024*1024)
b
bit (binary '0' or '1')
B
byte (8 bits)
1kbit/s
1,000 bit/s rate (not 1,024 bit/s)
1Mbit/s
1,000,000 bit/s rate
1Gbit/s
1,000,000,000 bit/s rate
word
32 bit
half-word
16 bit
Frequency and Time
Symbol
Description
kHz
1kHz = 103Hz = 1,000Hz
KHz
1KHz = 1,024Hz, 32KHz = 32,768Hz
MHz
106 = 1,000,000Hz
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 870
SAM DA1
43.4
Symbol
Description
GHz
109 = 1,000,000,000Hz
s
second
ms
millisecond
µs
microsecond
ns
nanosecond
Registers and Bits
Table 43-3. Register and Bit Mnemonics
Symbol
Description
R/W
Read/Write accessible register bit. The user can read from and write to this bit.
R
Read-only accessible register bit. The user can only read this bit. Writes will be
ignored.
W
Write-only accessible register bit. The user can only write this bit. Reading this bit will
return an undefined value.
BIT
Bit names are shown in uppercase. (Example ENABLE)
FIELD[n:m]
A set of bits from bit n down to m. (Example: PINA[3:0] = {PINA3, PINA2, PINA1,
PINA0}
Reserved
Reserved bits are unused and reserved for future use. For compatibility with future
devices, always write reserved bits to zero when the register is written. Reserved bits
will always return zero when read.
Reserved bit field values must not be written to a bit field. A reserved value won't be
read from a read-only bit field.
PERIPHERALi If several instances of a peripheral exist, the peripheral name is followed by a number
to indicate the number of the instance in the range 0-n. PERIPHERAL0 denotes one
specific instance.
Reset
Value of a register after a power Reset. This is also the value of registers in a
peripheral after performing a software Reset of the peripheral, except for the Debug
Control registers.
SET/CLR
Registers with SET/CLR suffix allows the user to clear and set bits in a register without
doing a read-modify-write operation. These registers always come in pairs. Writing a
one to a bit in the CLR register will clear the corresponding bit in both registers, while
writing a one to a bit in the SET register will set the corresponding bit in both registers.
Both registers will return the same value when read. If both registers are written
simultaneously, the write to the CLR register will take precedence.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 871
SAM DA1
44.
Acronyms and Abbreviations
The below table contains acronyms and abbreviations used in this document.
Table 44-1. Acronyms and Abbreviations
Abbreviation
Description
AC
Analog Comparator
ADC
Analog-to-Digital Converter
ADDR
Address
AES
Advanced Encryption Standard
AHB
AMBA Advanced High-performance Bus
®
AMBA
Advanced Microcontroller Bus Architecture
APB
AMBA Advanced Peripheral Bus
AREF
Analog reference voltage
BLB
Boot Lock Bit
BOD
Brown-out detector
CAL
Calibration
CC
Compare/Capture
CCL
Configurable Custom Logic
CLK
Clock
CRC
Cyclic Redundancy Check
CTRL
Control
DAC
Digital-to-Analog Converter
DAP
Debug Access Port
DFLL
Digital Frequency Locked Loop
DMAC
DMA (Direct Memory Access) Controller
DSU
Device Service Unit
EEPROM
Electrically Erasable Programmable Read-Only Memory
EIC
External Interrupt Controller
EVSYS
Event System
GCLK
Generic Clock Controller
GND
Ground
GPIO
General Purpose Input/Output
I2C
Inter-Integrated Circuit
IF
Interrupt flag
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 872
SAM DA1
Abbreviation
Description
INT
Interrupt
MBIST
Memory built-in self-test
MEM-AP
Memory Access Port
MTB
Micro Trace Buffer
NMI
Non-maskable interrupt
NVIC
Nested Vector Interrupt Controller
NVM
Non-Volatile Memory
NVMCTRL
Non-Volatile Memory Controller
OSC
Oscillator
PAC
Peripheral Access Controller
PC
Program Counter
PER
Period
PM
Power Manager
POR
Power-on reset
PORT
I/O Pin Controller
PTC
Peripheral Touch Controller
PWM
Pulse Width Modulation
RAM
Random-Access Memory
REF
Reference
RTC
Real-Time Counter
RX
Receiver/Receive
SERCOM
™
Serial Communication Interface
SMBus
System Management Bus
SP
Stack Pointer
SPI
Serial Peripheral Interface
SRAM
Static Random-Access Memory
SUPC
Supply Controller
SWD
Serial Wire Debug
TC
Timer/Counter
TCC
Timer/Counter for Control Applications
TRNG
True Random Number Generator
TX
Transmitter/Transmit
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 873
SAM DA1
Abbreviation
Description
ULP
Ultra-low power
USART
Universal Synchronous and Asynchronous Serial Receiver and Transmitter
USB
Universal Serial Bus
VDD
Common voltage to be applied to VDDIO, VDDIN and VDDANA
VDDIN
Digital supply voltage
VDDIO
Digital supply voltage
VDDANA
Analog supply voltage
VREF
Voltage reference
WDT
Watchdog Timer
XOSC
Crystal Oscillator
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 874
SAM DA1
45.
Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The referring
revision in this section are referring to the document revision.
45.1
Revision B - 03/2017
General
•
Device Variant B (die revision F) added:
– Ordering Information: Device Variant B ordering codes added.
– DSU - Device Service Unit:
• Device Variant A: DID.DEVSEL values updated.
• Device Variant B: DID.DEVSEL values added.
– Electrical Characteristics: Standby current consumption and
FDPLL96M characterization numbers added. Die revision F
characterization data is preliminary.
– Errata: Added errata for die revision F.
I/O Multiplexing and
Considerations
Oscillator Pinout: Note added.
Memories
Phisical Memory Map: Updated the start address of the Internal RWW
section from 0x00010000 to 0x00400000.
DSU - Device Service
Unit
System Services Availability When Accessed Externally: MBIST not
available when device is operated from external address range and device is
protected.
Clock System
Enabling and Disabling a Peripheral: Updated.
PM - Power Manager
APBCMASK register updated.
SYSCTRL - System
Control
Debug Operation: Paragraph upated.
NVMCTRL - Non-Volatile
Memory Controller
•
•
NVM Memory Organization figure: Updated value from "NVM Base
Address + 0x00010000" to "NVM Base Address + 0x00400000".
Region Size table: Updated.
SERCOM USART Asynchronous Operational Range: Updated equation and added error
Universial Synchronous
calculation explained example.
and Asynchronous
Receiver and Transmitter
TC - Timer/Counter
TCC - Timer/Counter for
Control Applications
© 2017 Microchip Technology Inc.
•
•
•
Additional Features: Removed "Time-Stamp Capture" section.
CTRLA.WAVEGEN[1:0]: Name column updated.
EVCTRL:EVACT[2:0] bit description updated: Time stamp capture and
pulse width capture removed.
DBGCTRL.FDDBD bit description updated: Default '0' is OCD fault
protection disabled.
Datasheet Complete
40001895A-page 875
SAM DA1
Electrical Characteristics
•
•
•
•
Errata
45.2
•
Absolute Maximum Ratings: Updated VPIN minimum and maximum
values. (Related to the new Injection Current definition section).
Injection Current: New section added.
Crystal Oscillator Characteristics: "32kHz Crystal Oscillator
Characteristics" updated.
DFLL48M Characteristics: Added table note.
New errata:
– Die revision E: Errata reverence 15625, 15683, 15753 added.
– Die revision F: Errata reverence 15625, 15683, 15753 added.
Revision A - 04/2016
Initial revision.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 876
SAM DA1
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Microchip provides online support via our web site at http://www.microchip.com/. This web site is used as
a means to make files and information easily available to customers. Accessible by using your favorite
Internet browser, the web site contains the following information:
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General Technical Support – Frequently Asked Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant program member listing
Business of Microchip – Product selector and ordering guides, latest Microchip press releases,
listing of seminars and events, listings of Microchip sales offices, distributors and factory
representatives
Customer Change Notification Service
Microchip’s customer notification service helps keep customers current on Microchip products.
Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata
related to a specified product family or development tool of interest.
To register, access the Microchip web site at http://www.microchip.com/. Under “Support”, click on
“Customer Change Notification” and follow the registration instructions.
Customer Support
Users of Microchip products can receive assistance through several channels:
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers should contact their distributor, representative or Field Application Engineer (FAE) for support.
Local sales offices are also available to help customers. A listing of sales offices and locations is included
in the back of this document.
Technical support is available through the web site at: http://www.microchip.com/support
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 877
SAM DA1
Product Identification System
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
SAM D A1 E 14 A - A B T
Product Family
Package Carrier
SAM D = Baseline Cortex-M0+ MCU
T = Tape and Reel
Product Series
A1 = Automotive basic feature set + DMA,
Adv Timers, USB, I2S, PTC
Pin Count
Package Grade
B = -40 C - 105 C Matte Sn Plating (only DA1)
O
O
E = 32 Pins
G = 48 Pins
J = 64 Pins
Package Type
Flash Memory Density
A = TQFP
M = QFN Wettable Flanks
16 = 64KB
15 = 32KB
14 = 16KB
Device Variant
A = Silicon revision E (Initial revision)
B = Silicon revision F
Note:
1. Tape and Reel identifier only appears in the catalog part number description. This identifier is used
for ordering purposes and is not printed on the device package. Check with your Microchip Sales
Office for package availability with the Tape and Reel option.
2. Small form-factor packaging options may be available. Please check http://www.microchip.com/
packaging for small-form factor package availability, or contact your local Sales Office.
Microchip Devices Code Protection Feature
Note the following details of the code protection feature on Microchip devices:
•
•
•
•
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the
market today, when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of
these methods, to our knowledge, require using the Microchip products in a manner outside the
operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is
engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their
code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the
code protection features of our products. Attempts to break Microchip’s code protection feature may be a
violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software
or other copyrighted work, you may have a right to sue for relief under that Act.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 878
SAM DA1
Legal Notice
Information contained in this publication regarding device applications and the like is provided only for
your convenience and may be superseded by updates. It is your responsibility to ensure that your
application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY
OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS
CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE.
Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life
support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend,
indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting
from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual
property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings,
BitCloud, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo,
Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA,
SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight
Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom,
chipKIT, chipKIT logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController,
dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient
Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL
ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their respective companies.
©
2017, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-1491-9
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 879
SAM DA1
Quality Management System Certified by DNV
ISO/TS 16949
Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer
fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California
®
®
and India. The Company’s quality system processes and procedures are for its PIC MCUs and dsPIC
®
DSCs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design and manufacture of development
systems is ISO 9001:2000 certified.
© 2017 Microchip Technology Inc.
Datasheet Complete
40001895A-page 880
Worldwide Sales and Service
AMERICAS
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EUROPE
Corporate Office
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Tel: 86-756-3210040
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Technical Support:
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http://www.microchip.com/
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Tel: 91-80-3090-4444
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© 2017 Microchip Technology Inc.
Datasheet Complete
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