Atmel SAM R21E / SAM R21G
SMART ARM-Based Wireless Microcontroller
DATASHEET
Description
The Atmel® | SMART™ SAM R21 is a series of low-power microcontrollers using the 32-bit ARM®
Cortex®-M0+ processor and an integrated ultra-low power 2.4GHz ISM band transceiver. SAM
R21 devices are available in 32- and 48-pin packages with up to 256KB Flash, 32KB of SRAM
and are operating at a maximum frequency of 48MHz and reach 2.46 Coremark/MHz. They are
designed for simple and intuitive migration with identical peripheral modules, hex compatible
code, identical linear address map and pin compatible migration paths between all devices in the
product series. All devices include intelligent and flexible peripherals, Atmel Event System for
inter-peripheral signaling, and support for capacitive touch button, slider and wheel user
interfaces.
The Atmel SAM R21 devices provide the following features: In-system programmable Flash,
optional 512KB serial Flash,12-channel direct memory access (DMA) controller, 12-channel
Event System, programmable interrupt controller, up to 28 programmable I/O pins, ultra-low
power 2.4GHz ISM band transceiver with a data rate of 250kb/s, 32-bit real-time clock and
calendar, three 16-bit Timer/Counters (TC) and three 16-bit Timer/Counters for Control (TCC),
where each TC can be configured to perform frequency and waveform generation, accurate
program execution timing or input capture with time and frequency measurement of digital
signals. The TCs can operate in 8- or 16-bit mode, selected TCs can be cascaded to form a 32-bit
TC, and the three Timer/Counters for Control have extended functions optimized for motor,
lighting and other control applications. The series provide one full-speed USB 2.0 embedded host
and device interface; up to five Serial Communication Modules (SERCOM) that each can be
configured to act as an USART, UART, SPI, I2C up 3.4MHz and LIN slave; up to eight channel
350ksps 12-bit ADC with programmable gain and optional oversampling and decimation
supporting up to 16-bit resolution, two analog comparators with window mode, Peripheral Touch
Controller supporting up to 48 buttons, sliders, wheels and proximity sensing; programmable
Watchdog Timer, brown-out detector and power-on reset and two-pin Serial Wire Debug (SWD)
program and debug interface.
All devices have accurate and low-power external and internal oscillators. All oscillators can be
used as a source for the system clock. Different clock domains can be independently configured
to run at different frequencies, enabling power saving by running each peripheral at its optimal
clock frequency, and thus maintaining a high CPU frequency while reducing power consumption.
The SAM R21 devices have two software-selectable sleep modes, idle and standby. In idle mode
the CPU is stopped while all other functions can be kept running. In standby all clocks and
functions are stopped expect those selected to continue running. The device supports
SleepWalking, which is the module's ability to wake itself up and wake up its own clock, and
hence perform predefined tasks without waking up the CPU. The CPU can then be only woken on
a need basis, e.g. a threshold is crossed or a result is ready. The Event System supports
synchronous and asynchronous events, allowing peripherals to receive, react to and send events
even in standby mode.
The Flash program memory can be reprogrammed in-system through the SWD interface. The
same interface can be used for non-intrusive on-chip debug of application code. A boot loader
running in the device can use any communication interface to download and upgrade the
application program in the Flash memory.
The SAM R21 devices are supported with a full suite of program and system development tools,
including C compilers, macro assemblers, program debugger/simulators, programmers and
evaluation kits.
Atmel-42223G–SAM-R21_Datasheet–05/2016
SMART
Features
z Processor
z ARM Cortex-M0+ CPU running at up to 48MHz
z Single-cycle hardware multiplier
z Micro Trace Buffer (MTB)
z Memories
z 768(1)/256/128/64KB in-system self-programmable Flash
z 32/16/8KB SRAM
z System
z Power-on reset (POR) and brown-out detection (BOD)
z Internal and external clock options with 48MHz Digital Frequency Locked Loop (DFLL48M) and 48MHz to 96MHz Fractional
Digital Phase Locked Loop (FDPLL96M)
z External Interrupt Controller (EIC)
z Up to 15 external interrupts
z One non-maskable interrupt
z Two-pin Serial Wire Debug (SWD) programming, test and debugging interface
z Low Power
z Idle and standby sleep modes
z SleepWalking peripherals
z Peripherals
z 12-channel Direct Memory Access Controller (DMAC)
z 12-channel Event System
z Integrated Ultra Low Power Transceiver for 2.4GHz ISM Band
z Supported PSDU Data rates: 250kb/s, 500kb/s, 1000kb/s and 2000kb/s(2)
z -99dBm RX Sensitivity; TX Output Power up to +4dBm
z Hardware Assisted MAC (Auto-Acknowledge, Auto-Retry)
z SFD-Detection; Spreading; De-Spreading; Framing; CRC-16 Computation
z Antenna Diversity and TX/RX Control
z 128 Byte TX/RX Frame Buffer
z Integrated 16MHz Crystal Oscillator (external crystal needed)
z PLL synthesizer with 5 MHz and 500 kHz channel spacing for 2.4GHz ISM band
z Hardware Security (AES, True Random Generator)
z Three 16-bit Timer/Counters (TC), configurable as either:
z One 16-bit TC with compare/capture channels
z One 8-bit TC with compare/capture channels
z One 32-bit TC with compare/capture channels, by using two TCs
z Three 16-bit Timer/Counters for Control (TCC), with extended functions:
z Up to four compare channels with optional complementary output
z Generation of synchronized pulse width modulation (PWM) pattern across port pins
z Deterministic fault protection, fast decay and configurable dead-time between complementary output
z Dithering that increase resolution with up to 5 bit and reduce quantization error
z 32-bit Real Time Counter (RTC) with clock/calendar function
z Watchdog Timer (WDT)
z CRC-32 generator
z One full-speed (12Mbps) Universal Serial Bus (USB) 2.0 interface
z Embedded host and device function
z Eight endpoints
z Up to five Serial Communication Interfaces (SERCOM), each configurable to operate as either:
z USART with full-duplex and single-wire half-duplex configuration
z I2C up to 3.4MHz
z SPI
z LIN slave
z One 12-bit, 350ksps Analog-to-Digital Converter (ADC) with up to eight external channels
z Differential and single-ended input
z 1/2x to 16x programmable gain stage
z Automatic offset and gain error compensation
z Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution
z Two Analog Comparators (AC) with window compare function
z Peripheral Touch Controller (PTC)
z 48-channel capacitive touch and proximity sensing
z I/O and Package
z 16/28 programmable I/O pins
z 32-pin and 48-pin QFN
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
2
z Operating Voltage
z 1.8V – 3.6V
z Temperature Range
z -40°C to 85°C Industrial
z -40°C to 125°C Industrial
Notes:
1.
2.
Only applicable for SAM R21E19: 256KB embedded + 512KB serial Flash.
High data rates (500kb/s, 1000kb/s and 2000kb/s) only applicable for T=-40°C to 85°C.
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
3
1.
Configuration Summary
SAM R21G
SAM R21E
Pins
48
32
General Purpose I/O-pins (GPIOs)
28
16
Flash
256/128/64KB
256/128/64KB
SRAM
32/16/8KB
32/16/8KB
Timer Counter (TC) instances
3
3
Waveform output channels per TC instance
2
2
Timer Counter for Control (TCC) instances
3
3
4/4/2
4/4/2
DMA channels
12
12
USB interface
1
1
5+1(1)
4+1(1)
No
No
Analog-to-Digital Converter (ADC) channels
8
4
Analog Comparators (AC)
2
2
Digital-to-Analog Converter (DAC)
channels
No
No
Real-Time Counter (RTC)
Yes
Yes
1
1
1 32-bit value or
2 16-bit values
1 32-bit value or
2 16-bit values
External Interrupt lines
15
14
Peripheral Touch Controller (PTC) X and Y lines
8x6
6x2
Waveform output channels per TCC
Serial Communication Interface (SERCOM) instances
Inter-IC Sound (I2S) interface
RTC alarms
RTC compare values
Maximum CPU frequency
48MHz
Packages
QFN
QFN
32.768kHz crystal oscillator (XOSC32K)
Yes
No
Oscillators
16MHz crystal oscillator for 2.4GHz TRX (XOSCRF)
0.4-32MHz crystal oscillator (XOSC)
32.768kHz internal oscillator (OSC32K)
32kHz ultra-low-power internal oscillator (OSCULP32K)
8MHz high-accuracy internal oscillator (OSC8M)
48MHz Digital Frequency Locked Loop (DFLL48M)
96MHz Fractional Digital Phased Locked Loop (FDPLL96M)
Event System channels
12
12
SW Debug Interface
Yes
Yes
Watchdog Timer (WDT)
Yes
Yes
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
4
Note:
1.
SERCOM4 is internally connected to the AT86RF233.
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
5
2.
Ordering Information
ATSAMR 21 E 16 A - M U T
Product Family
Package Carrier
SAMR = SoC Microcontroller with RF
No character = Tray (Default)
T = Tape and Reel
Product Series
21 = Cortex M0+ CPU, USB
Package Grade
U = -40 - 85°C Matte Sn Plating
F = -40 - 125°C Matte Sn Plating
Pin Count
E = 32 Pins
G = 48 Pins
Package Type
Flash Memory
M = QFN
19 = 256KB + 512KB
18 = 256KB
17 = 128KB
16 = 64KB
Device Variant
A = Default Variant
2.1
SAM R21E
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
ATSAMR21E16A-MF
ATSAMR21E16A-MFT
ATSAMR21E16A-MU
Tray
64K
8K
QFN32
ATSAMR21E16A-MUT
ATSAMR21E17A-MU
128K
16K
QFN32
ATSAMR21E19A-MFT
Note:
1.
Tray
Tray
256K
32K
QFN32
ATSAMR21E18A-MUT
ATSAMR21E19A-MF
Tape & Reel
Tape & Reel
ATSAMR21E18A-MF
ATSAMR21E18A-MU
Tray
Tray
ATSAMR21E17A-MUT
ATSAMR21E18A-MFT
Tape & Reel
Tape & Reel
ATSAMR21E17A-MF
ATSAMR21E17A-MFT
Carrier Type
Tape & Reel
Tray
Tape & Reel
256K + 512K(1)
32K
QFN32
Tray
Tape & Reel
Serial Flash MX25V4006EWSK. For more information, see http://www.macronix.com.
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
6
2.2
SAM R21G
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
ATSAMR21G16A-MF
ATSAMR21G16A-MFT
ATSAMR21G16A-MU
Tray
64K
8K
QFN48
ATSAMR21G16A-MUT
ATSAMR21G17A-MU
128K
16K
QFN48
ATSAMR21G18A-MUT
Tape & Reel
Tray
Tape & Reel
ATSAMR21G18A-MF
ATSAMR21G18A-MU
Tray
Tray
ATSAMR21G17A-MUT
ATSAMR21G18A-MFT
Tape & Reel
Tape & Reel
ATSAMR21G17A-MF
ATSAMR21G17A-MFT
Carrier Type
Tray
256K
32K
QFN48
Tape & Reel
Tray
Tape & Reel
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
7
Block Diagrams
3.1
MCU Block Diagram
SWCLK
CORTEX-M0+
PROCESSOR
Fmax 48 MHz
SERIAL
WIRE
SWDIO
MEMORY
TRACE BUFFER
IOBUS
DEVICE
SERVICE
UNIT
M
256/128/64KB
NVM
32/16/8KB
RAM
NVM
CONTROLLER
Cache
SRAM
CONTROLLER
M
S
S
S
AHB-APB
BRIDGE B
S
AHB-APB
BRIDGE A
DMA
5x
6 SERCOM
x SERCOM
OSCULP32K
OSC32K
XOSC32K
3 x TIMER / COUNTER
8 x Timer Counter
FDPLL96M
POWER MANAGER
CLOCK
CONTROLLER
RESETN
RESET
CONTROLLER
SLEEP
CONTROLLER
GENERIC CLOCK
CONTROLLER
(3)
GCLK_IO[n]
REAL TIME
COUNTER
WATCHDOG
TIMER
EXTINT[15..1]
NMI
DMA
EVENT SYSTEM
XOSC
PAD0
PAD1
PAD2
PAD3
DMA
OSC8M
DFLL48M
XIN
XOUT
DM
SOF 1KHZ
PERIPHERAL
ACCESS CONTROLLER
VREF
(4)
XIN32
XOUT32
DP
AHB-APB
BRIDGE C
SYSTEM CONTROLLER
PORT
USB FS
DEVICE
MINI-HOST
S
PERIPHERAL
ACCESS CONTROLLER
BOD33
DMA
M
HIGH SPEED
BUS MATRIX
PERIPHERAL
ACCESS CONTROLLER
S
3x TIMER / COUNTER
FOR CONTROL
DMA
8-CHANNEL
12-bit ADC 350KSPS
2 ANALOG
COMPARATORS
PERIPHERAL
TOUCH
CONTROLLER
WO0
WO1
PORT
3.
WO0
WO1
(2)
WOn
AIN[n]
(3)
VREFB
AIN[3..0]
X[7..0]
Y[5..0]
EXTERNAL INTERRUPT
CONTROLLER
Notes: 1. Some products have different number of SERCOM instances, Timer/Counter instances, PTC signals and ADC signals. Refer to “Ordering Information” on page 6 for details.
2. The three TCC instances have different configurations, including the number of Waveform Output (WO) lines. Refer
to “Peripherals Configuration Summary” on page 43 for details.
3. Refer to the PORT Function Multiplexing Table 5-1 for details about the available GCLK_IO and ADC signals.
4. Only available for SAM R21G.
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
8
SAM R21 Interconnection
PA08
PA09
GNDANA
RFP
RFP
FECTRL0..1
AVSS
RFN
GNDANA
AVSS
PA12(2)
PA13(2)
PA14
PA15
RFN
2.4 GHz RF
front-end circuit
FECTRL2..5
DIG3
2.4GHz TRX (analog)
DIG4
(1)
DVSS
AVSS
DVDD
DVDD
DVREG
AVREG
TRX (digital)
DEVDD
VDDIO
GNDANA
AVDD
AVDD
EVDD
VDDANA
DIG1
AVSS
Control Logic
DIG2
/SEL
IRQ
PB31
PB00
PAD1
MOSI
PB30
PAD2
MISO
PAD0
GENERIC
CLOCK
PC19
SCLK
PC18
GCLK_IO1(4)
PAD3
CLKM
PC16
PA20
PB15
XOSC
RF
SPI
(Slave)
SLP_TR
PORT
GNDANA
XTAL1
RSTN
SERCOM 4(3)
DIG1..4
EXTINT0
XTAL1
XTAL2
XTAL2
AT86RF233
ADC
AC
EXTERNAL
INTERRUPT
CONTROLLER
RFCTRL
PTC
Notes:
PAD3
XOSC
32K
SAMD21
SCLK
PB23
PAD2
PB22
SO
CS#
SI
PA22
PA12
WP#
GND
PA00
VCC HOLD#
VDDIN
VDDCORE
(1)
PAD1
SERCOM 5
PA23
PORT
PAD0
VREG
GND
3.2
MX25V4006(5)
SAMR21
1. Paddle connected to digital ground DVSS, GND.
2. Only available for SAM R21G.
3. Dedicated SERCOM4 alternate pin function mapping for internally connected AT86RF233.
4. Die revision A uses GCLK_IO5.
5. Only available for SAM R21E19.
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
9
Pinout
4.1
SAM R21G - QFN48
48
47
46
45
44
43
42
41
40
39
38
37
PB03
PB02
PA31
PA30
VDDIN
VDDCORE
GND
PA28
RESET
PA27
PB23
PB22
4.
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
VDDIO
GND
PA25
PA24
PA23
PA22
DVDD
GND
PA19
PA18
PA17
PA16
VDDIO
GND
PA08
PA09
GNDANA
RFP
RFN
GNDANA
PA12
PA13
PA14
PA15
13
14
15
16
17
18
19
20
21
22
23
24
PA00
PA01
XTAL2
XTAL1
GNDANA
VDDANA
AVDD
GNDANA
PA04
PA05
PA06
PA07
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
RESET PIN
Note:
RF PIN
DIGITAL PIN
ANALOG PIN
DIGITAL PIN/
OSCILLATOR
The large center pad underneath the QFN package is made of metal and internally connected to GND.
It should be soldered and connected to the digital ground on the board to ensure good mechanical stability.
It is not recommended to use the exposed paddle as a replacement of the regular GND pin.
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
10
SAM R21E - QFN32
32
31
30
29
28
27
26
25
PA31
PA30
VDDIN
VDDCORE
GND
PA28
RESET
PA27
4.2
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
VDDIO
PA25
PA24
DVDD
PA19
PA18
PA17
PA16
OSCILLATOR
GROUND
PA08
PA09
GNDANA
RFP
RFN
GNDANA
PA14
PA15
9
10
11
12
13
14
15
16
XTAL2
XTAL1
GNDANA
VDDANA
AVDD
GNDANA
PA06
PA07
INPUT SUPPLY
RESET PIN
REGULATED OUTPUT
SUPPLY
Note:
RF PIN
DIGITAL PIN
ANALOG PIN
DIGITAL PIN/
OSCILLATOR
The large center pad underneath the QFN package is made of metal and internally connected to GND.
It should be soldered and connected to the digital ground on the board to ensure good mechanical stability.
It is not recommended to use the exposed paddle as a replacement of the regular GND pin.
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
11
5.
I/O Multiplexing and Considerations
5.1
Multiplexed Signals
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of the
peripheral functions A, B, C, D, E, F, G or H. To enable a peripheral function on a pin, the Peripheral Multiplexer Enable
bit in the Pin Configuration register corresponding to that pin (PINCFGn.PMUXEN, n = 0..31) in the PORT must be
written to one. The selection of peripheral function A to H is done by writing to the Peripheral Multiplexing Odd and Even
bits in the Peripheral Multiplexing register (PMUXn.PMUXE/O) in the PORT.
Table 5-1 describes the peripheral signals multiplexed to the PORT I/O pins.
Table 5-1.
PORT Function Multiplexing
Pin
A
SAMR21 SAMR21
E
G
I/O Pin Supply Type
EIC
B(1)(2)
REF
ADC
C
AC
PTC
D
SERCOM SERCOM(1)(2)
ALT
E
F
G
H
TC
TCC
FECTRL
TCC
SERCOM
COM
AC/
GCLK
SERCOM1/
TCC2/WO[0]
PAD[0]
1
PA00 VDDANA
2
PA01 VDDANA
EXTINT[1]
9
PA04 VDDANA
EXTINT[4]
10
PA05 VDDANA
7
11
8
SERCOM1/
TCC2/WO[1]
PAD[1]
ADC/
VREFB
AIN[4]
AIN[0]
Y[2]
SERCOM0/
TCC0/WO[0]
PAD[0]
EXTINT[5]
AIN[5]
AIN[1]
Y[3]
SERCOM0/
TCC0/WO[1]
PAD[1]
PA06 VDDANA
EXTINT[6]
AIN[6]
AIN[2]
Y[4]
SERCOM0/
TCC1/WO[0]
PAD[2]
12
PA07 VDDANA
EXTINT[7]
AIN[7]
AIN[3]
Y[5]
SERCOM0/
TCC1/WO[1]
PAD[3]
9
15
PA08
VDDIO
I2C
NMI
AIN[16]
X[0]
SERCOM0/ SERCOM2/
TCC0/WO[0] FECTRL[0]
PAD[0]
PAD[0]
10
16
PA09
VDDIO
I2C
EXTINT[9]
AIN[17]
X[1]
SERCOM0/ SERCOM2/
TCC0/WO[1] FECTRL[1]
PAD[1]
PAD[1]
21
PA12
VDDIO
I2C
EXTINT[12]
SERCOM2/
PAD[0]
TCC2/WO[0] FECTRL[2]
AC/
CMP[0]
22
PA13
VDDIO
I2C
EXTINT[13]
SERCOM2/
PAD[1]
TCC2/WO[1] FECTRL[3]
AC/
CMP[1]
15
23
PA14
VDDIO
EXTINT[14]
SERCOM2/
PAD[2]
TC3/WO[0] FECTRL[4]
GCLK_IO[0]
16
24
PA15
VDDIO
EXTINT[15]
SERCOM2/
PAD[3]
TC3/WO[1] FECTRL[5]
GCLK_IO[1]
17
25
PA16
VDDIO
I2C
18
26
PA17
VDDIO
I2C
19
27
PA18
20
28
X[4]
SERCOM1/ SERCOM3/
TCC2/WO[0]
PAD[0]
PAD[0]
TCC0/
WO[0]
GCLK_IO[2]
EXTINT[1]
X[5]
SERCOM1/ SERCOM3/
TCC2/WO[1]
PAD[1]
PAD[1]
TCC0/
WO[1]
GCLK_IO[3]
VDDIO
EXTINT[2]
X[6]
SERCOM1/ SERCOM3/
PAD[2]
PAD[2]
TC3/WO[0]
TCC0/
WO[2]
AC/
CMP[0]
PA19
VDDIO
EXTINT[3]
X[7]
SERCOM1/ SERCOM3/
PAD[3]
PAD[3]
TC3/WO[1]
TCC0/
WO[3]
AC/
CMP[1]
31
PA22
VDDIO
I2C
EXTINT[6]
X[10]
SERCOM3/ SERCOM5/
PAD[0]
PAD[0]
TC4/WO[0]
TCC0/
WO[4]
GCLK_IO[6]
32
PA23
VDDIO
I2C
EXTINT[7]
X[11]
SERCOM3/ SERCOM5/
PAD[1]
PAD[1]
TC4/WO[1]
TCC0/
WO[5]
USB/
GCLK_IO[7]
SOF1kHz
22
33
PA24
VDDIO
EXTINT[12]
SERCOM3/ SERCOM5/
PAD[2]
PAD[2]
TC5/WO[0]
TCC1/
WO[2]
USB_DM
23
34
PA25
VDDIO
EXTINT[13]
SERCOM3/ SERCOM5/
PAD[3]
PAD[3]
TC5/WO[1]
TCC1/
WO[3]
USB_DP
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
12
Table 5-1.
PORT Function Multiplexing (Continued)
Pin
A
SAMR21 SAMR21
E
G
I/O Pin Supply Type
EIC
B(1)(2)
REF
ADC
C
AC
D
SERCOM SERCOM(1)(2)
ALT
PTC
E
F
G
H
TC
TCC
FECTRL
TCC
SERCOM
COM
AC/
GCLK
37
PB22
VDDIO
EXTINT[6]
SERCOM5/
PAD[2]
GCLK_IO[0]
38
PB23
VDDIO
EXTINT[7]
SERCOM5/
PAD[3]
GCLK_IO[1]
25
39
PA27
VDDIO
EXTINT[15]
SERCOM3/
PAD[0]
GCLK_IO[0]
27
41
PA28
VDDIO
EXTINT[8]
SERCOM3/
PAD[1]
GCLK_IO[0]
31
45
PA30
VDDIO
EXTINT[10]
SERCOM1/
TCC1/WO[0]
PAD[2]
SWCLK
32
46
PA31
VDDIO
EXTINT[11]
SERCOM1/
TCC1/WO[1]
PAD[3]
SWDIO(3)
47
PB02 VDDANA
EXTINT[2]
AIN[10]
Y[8]
SERCOM5/
PAD[0]
48
PB03 VDDANA
EXTINT[3]
AIN[11]
Y[9]
SERCOM5/
PAD[1]
Notes:
1.
2.
3.
5.2
GCLK_IO[0]
All analog pin functions are on peripheral function B. Peripheral function B must be selected to disable the digital control of the pin.
Only some pins can be used in SERCOM I2C mode. See the Type column for using a SERCOM pin in I2C mode. Refer to “Electrical Characteristics” on page
1055 for details on the I2C pin characteristics.
This function is only activated in the presence of a debugger.
Internal Multiplexed Signals
PA20, PB00, PB15, PB30, PB31, PC16, PC18 and PC19 are by default controlled by the PORT as a general purpose I/O
and alternatively it can be assigned to one of the peripheral functions A, B, C, D, E, F, G or H. To enable a peripheral
function on a pin, the Peripheral Multiplexer Enable bit in the Pin Configuration register corresponding to that pin
(PINCFGn.PMUXEN, n = 0-31) in the PORT must be written to one. The selection of peripheral function A to H is done
by writing to the Peripheral Multiplexing Odd and Even bits in the Peripheral Multiplexing register (PMUXn.PMUXE/O) in
the PORT.
PA10, PA11, PB16 and PB17 cannot be configured as output ports. These ports are always connected to the RFCTRL
inputs.
A
B
C
D
SERCOM
SERCOMALT
E
F
G
H
TC
FECTRL
TCC
SERCOM
COM
AC/
GCLK
Internal
Signal
I/O Pin
Supply
Type
EIC
DIG3
PA10
VDDIO
Input
EXTINT[10]
DIG4
PA11
VDDIO
Input
EXTINT[11]
SLP_TR
PA20
VDDIO
I/O
IRQ
PB00
VDDANA
I/O
RSTN
PB15
VDDIO
I/O
DIG1
PB16
VDDIO
Input
EXTINT[0]
DIG2
PB17
VDDIO
Input
EXTINT[1]
MOSI
PB30
VDDIO
I/O
SERCOM4/
PAD[2]
SEL
PB31
VDDIO
I/O
SERCOM4/
PAD[1]
REF
ADC
AC
PTC
EXTINT[0]
Atmel | SMART SAM R21 [DATASHEET]
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13
A
Internal
Signal
B
SERCOM
H
TC
FECTRL
TCC
SERCOM
COM
AC/
GCLK
PC16
VDDIO
I/O
GCLK/
IO[1](1)
SCLK
PC18
VDDIO
I/O
SERCOM4/
PAD[3]
MISO
PC19
VDDIO
I/O
SERCOM4/
PAD[0]
5.3.1
Oscillator Pinout
PTC
G
CLKM
Other Functions
AC
F
I/O Pin
5.3
ADC
SERCOMALT
E
Type
1.
REF
D
Supply
Note:
EIC
C
Die revision A uses GCLK/IO[5].
The oscillators are not mapped to the normal PORT functions and their multiplexing are controlled by registers in the
System Controller (SYSCTRL). Refer to “SYSCTRL – System Controller” on page 143 for more information.
Oscillator
Supply
XOSC
VDDIO
XOSC32K
VDDANA
Signal
I/O Pin
XIN
PA14
XOUT
PA15
XIN32
PA00
XOUT32
PA01
The integrated AT86RF233 16 MHz crystal oscillator is directly connected to pins and has no multiplexing functionality.
Oscillator
XOSCRF
5.3.2
Supply
EVDD/VDDANA
Signal
I/O Pin
XTAL1
XTAL1
XTAL2
XTAL2
Serial Wire Debug Interface Pinout
Only the SWCLK pin is mapped to the normal PORT functions. A debugger cold-plugging or hot-plugging detection will
automatically switch the SWDIO port to the SWDIO function. Refer to “DSU – Device Service Unit” on page 45 for more
information.
Signal
Supply
I/O Pin
SWCLK
VDDIO
PA30
SWDIO
VDDIO
PA31
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5.3.3
General Circuit Description
The Atmel AT86RF233 single-chip radio transceiver provides a complete radio transceiver interface between an antenna
and the SAM D21 microcontroller. It comprises the analog radio, digital modulation and demodulation including time and
frequency synchronization, as well as data buffering. A single 128-byte TRX buffer stores receive or transmit data.
Communication between transmitter and receiver is based on direct sequence spread spectrum with different modulation
schemes and spreading codes.
The AT86RF233 block diagram is shown in Figure 5-1.
Figure 5-1. AT86RF233 Block Diagram
ext. PA and Power
Control
DIG3/4
PA
XOSCRF
PLL
AVREG
Configuration Registers
TX Data
TX BBP
/SEL
DVREG
SPI
(Slave)
RFP
Frame
Buffer
FTN, BATMON
MISO
MOSI
SCLK
RFN
LNA
PPF
BPF
Limiter
ADC
RX BBP
AES
IRQ
CLKM
DIG2
AGC
AD
DIG1/2
Analog Domain
/RST
RSSI
Control Logic
SLP_TR
Antenna Diversity
Digital Domain
The number of external components is minimized such that only the antenna, the crystal and decoupling capacitors are
required. The bidirectional differential antenna pins (RFP, RFN) are used for transmission and reception, thus no external
antenna switch is needed. Control of an external power amplifier is supported by two digital control signals (differential
operation).
The received RF signal at SAM R21 pin 13/19 (RFN) and pin 12/18 (RFP) is differentially fed through the low-noise
amplifier (LNA) to the RF filter (PPF) to generate a complex signal, driving the integrated channel filter (BPF). The limiting
amplifier provides sufficient gain to drive the succeeding analog-to-digital converter (ADC) and generates a digital RSSI
signal. The ADC output signal is sampled by the digital base band receiver (RX BBP).
The transmit modulation scheme is offset-QPSK (O-QPSK) with half-sine pulse shaping and 32-length block coding
(spreading) according to [1], [2] and [3]. The modulation signal is generated in the digital transmitter (TX BBP) and
applied to the fractional-N frequency synthesis (PLL), to ensure the coherent phase modulation required for
demodulation of O-QPSK signals. The frequency-modulated signal is fed to the power amplifier (PA).
Two on-chip low-dropout voltage regulators (A|DVREG) provide regulated analog and digital 1.8V supply outputs.
An internal 128-byte RAM for RX and TX (Frame Buffer) buffers the data to be transmitted or the received data.
The configuration of the internal AT86RF233, reading and writing of Frame Buffer is controlled by the SPI interface and
additional control lines.
The AT86RF233 further contains comprehensive hardware-MAC support (Extended Operating Mode) and a security
engine (AES) to improve the overall system power efficiency and timing. The stand-alone 128-bit AES engine can be
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15
accessed in parallel to all PHY operational transactions and states using the SPI interface, except during SLEEP and
DEEP_SLEEP states.
For long-range applications or to improve the reliability of a RF connection the RF performance can further be improved
by using an external RF front-end or Antenna Diversity. Both operation modes are supported by the AT86RF233 with
dedicated control signals DIG1, …, DIG4 which can be activated as alternate pin output functions FECTRL[0..5] by the
integrated microcontroller.
Additional features of the Extended Feature Set, see “AT86RF233 Extended Feature Set” on page 1005, are provided to
simplify the interaction between radio transceiver and microcontroller.
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5.4
Analog and RF Pins
5.4.1
Supply and Ground Pins
5.4.1.1
EVDD, DEVDD
EVDD and DEVDD are analog and digital supply voltage pins of the AT86RF233 radio transceiver.
5.4.1.2
AVDD, DVDD
AVDD and DVDD are outputs of the internal voltage regulators and require bypass capacitors for stable operation. The
voltage regulators are controlled independently by the radio transceivers state machine and are activated depending on
the current radio transceiver state. The voltage regulators can be configured for external supply; for details, refer to
“Voltage Regulators (AVREG, DVREG)” on page 983.
5.4.1.3
AVSS, DVSS
AVSS and DVSS are analog and digital ground pins respectively. The analog and digital power domains should be
separated on the PCB.
5.4.2
RF Pins
5.4.2.1
RFN, RFP
A differential RF port (RFP/RFN) provides common-mode rejection to suppress the switching noise of the internal digital
signal processing blocks. At board-level, the differential RF layout ensures high receiver sensitivity by reducing spurious
emissions originated from other digital ICs such as a microcontroller.
The RF port is designed for a 100Ω differential load. A DC path between the RF pins is allowed; a DC path to ground or
supply voltage is not allowed.
A simplified schematic of the RF front end is shown in Figure 5-2.
Figure 5-2. Simplified RF Front-end Schematic.
3&%
$7 5)
9
0
/1$
5;
3$
7;
&0
)HHGEDFN
5;7;
The RF port DC values depend on the operating state; refer to “AT86RF233 Operating Modes” on page 902. In
TRX_OFF state, when the analog front-end is disabled (see “TRX_OFF – Clock State” on page 904), the RF pins are
pulled to ground, preventing a floating voltage larger than 1.8V which is not allowed for the internal circuitry.
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In transmit mode, a control loop provides a common-mode voltage of 0.9V. Transistor M0 is off, allowing the PA to set
the common-mode voltage. The common-mode capacitance at each pin to ground shall be < 30pF to ensure the stability
of this common-mode feedback loop.
In receive mode, the RF port provides a low-impedance path to ground when transistor M0, (see Figure 5-2) pulls the
inductor center tap to ground. A DC voltage drop of 20mV across the on-chip inductor can be measured at the RF pins.
5.4.3
Crystal Oscillator Pins
5.4.3.1
XTAL1, XTAL2
The pin 2/4 (XTAL1) of SAM R21 is the input of the reference oscillator amplifier (XOSCRF), the pin 1/3 (XTAL2) is the
output. A detailed description of the crystal oscillator setup and the related XTAL1/XTAL2 pin configuration can be found
in “Crystal Oscillator (XOSCRF)” on page 989.
When using an external clock reference signal, XTAL1 shall be used as input pin. For further details, refer to “External
Reference Frequency Setup” on page 990.
5.4.4
Analog Pin Summary
Table 5-2.
Analog Pin Behavior - DC values
Pin
RFP/RFN
Values and Conditions
Description
VDC = 0.9V (BUSY_TX)
DC level at pins RFP/RFN for various transceiver states.
VDC = 20mV (receive states)
AC coupling is required if a circuitry with a DC path to ground
or supply is used. Serial capacitance and capacitance of each
pin to ground must be < 30pF.
VDC = 0mV (otherwise)
XTAL1/XTAL2
DVDD
VDC = 0.9V at both pins
CPAR = 3pF
Parasitic capacitance (CPAR) of the pins must be considered as
additional load capacitance to the crystal.
VDC = 1.8V (all states, except SLEEP
and DEEP_SLEEP)
DC level at pin DVDD for various transceiver states.
VDC = 0mV (DEEP_SLEEP)
Supply pins (voltage regulator output) for the digital 1.8V
voltage domain. The outputs shall be bypassed by 100nF.
VDC = 1.5V (SLEEP)
AVDD
VDC = 1.8V (all states, except P_ON,
SLEEP, DEEP_SLEEP, RESET, and
TRX_OFF)
VDC = 0mV (otherwise)
5.5
DC level at pins XTAL1/XTAL2 for various transceiver states.
DC level at pin AVDD for various transceiver states.
Supply pin (voltage regulator output) for the analog 1.8V
voltage domain. The outputs shall be bypassed by 100nF.
Digital I/O Signals
The AT86RF233 provides a digital microcontroller interface. The interface comprises a slave SPI (/SEL, SCLK, MOSI,
and MISO) and additional control signals (CLKM, IRQ, SLP_TR, /RST, and DIG2). The microcontroller interface is
described in detail in “AT86RF233 Microcontroller Interface” on page 883.
Additional digital output signals DIG1, …, DIG4 are provided to control external blocks, that is for Antenna Diversity RF
switch control or as an RX/TX Indicator, see “Antenna Diversity” on page 1020 and “RX/TX Indicator” on page 1025
respectively.
5.5.1
Driver Strength Settings
The driver strength of all digital output signals (MISO, IRQ, DIG1,..., DIG4 and CLKM) to the microcontroller are fixed.
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5.5.2
Pull-up and Pull-down Configuration
Pulling transistors are internally connected to all digital inputs from the microcontroller in radio transceiver states P_ON
(including reset during P_ON) and DEEP_SLEEP, refer to “P_ON – Power-On after VDD” on page 903 and
“DEEP_SLEEP – Deep Sleep State” on page 904.
Table 5-3 summarizes the pull-up and pull-down configuration.
Table 5-3.
Note:
1.
Pull-Up / Pull-Down Configuration of Digital Input Signals from the Microcontroller
Signal
H = pull-up, L = pull-down
/RST
H
/SEL
H
SCLK
L
MOSI
L
SLP_TR(1))
L
Except SLP_TR pin for DEEP_SLEEP state.
In all other radio transceiver states, including RESET, no pull-up or pull-down transistors are connected to any of the
digital inputs mentioned in Table 5-3.
In all other states, external circuitry should guaranty defined levels at all input pins. Floating input signals may cause
unexpected functionality and increased power consumption, for example in SLEEP state.
If the additional digital output signals DIG1, …, DIG4 are not activated, they are pulled-down to digital ground
(DIG1/DIG2) or analog ground (DIG3/DIG4).
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ADC
VDDIN
GND
VDDIO
Power Domain Overview
VDDCORE
6.1
GNDANA
Power Supply and Start-Up Considerations
VDDANA
6.
VOLTAGE
REGULATOR
PB[31:10]
OSC8M
PA[13:8]
BOD12
XOSC
PA[7:4]
PA[15:14]
AC
PA[31:16]
PB[3:2]
PTC
Digital Logic
(CPU, peripherals)
PA[1:0]
XOSC32K
POR
DFLL48M
OSC32K
OSCULP32K
6.2
Power Supply Considerations
6.2.1
Power Supplies
FDPLL96M
BOD33
The Atmel® SAM R21 has several different power supply pins:
z
VDDIO: Powers I/O lines, OSC8M and XOSC. Voltage is 1.8V to 3.6V.
z
VDDIN: Powers I/O lines, the internal regulator and the stacked 512KB serial Flash. Voltage is 1.8V to 3.6V.
z
VDDANA: Powers I/O lines and the ADC, AC, PTC, OSCULP32K, OSC32K, XOSC32K. Voltage is 1.8V to 3.6V.
z
VDDCORE: Internal regulated voltage output. Powers the core, memories, peripherals, DFLL48M and
FDPLL96M. Voltage is 1.2V.
The same voltage must be applied to both VDDIN, VDDIO and VDDANA. This common voltage is referred to as VDD in
the datasheet.
The ground pins, GND, are common to VDDCORE, VDDIO and VDDIN. The ground pin for VDDANA is GNDANA.
For decoupling recommendations for the different power supplies, refer to the schematic checklist.
Refer to “Schematic Checklist” on page 1112 for details.
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6.2.2
Voltage Regulator
The SAM R21 voltage regulator has two different modes:
6.2.3
z
Normal mode: To be used when the CPU and peripherals are running
z
Low Power (LP) mode: To be used when the regulator draws small static current. It can be used in standby mode
Typical Powering Schematics
The SAM R21 uses a single supply from 1.8V to 3.6V.
The following figure shows the recommended power supply connection.
Figure 6-1. Power Supply Connection
SAM R21
Main Supply
(1.8V — 3.6V)
VDDIO
VDDANA
VDDIN
VDDCORE
GND
DVDD
GNDANA
AVDD
6.2.4
Power-Up Sequence
6.2.4.1
Minimum Rise Rate
The integrated power-on reset (POR) circuitry monitoring the VDDANA power supply requires a minimum rise rate. Refer
to the “Electrical Characteristics” on page 1055 for details.
6.2.4.2
Maximum Rise Rate
The rise rate of the power supply must not exceed the values described in Electrical Characteristics. Refer to the
“Electrical Characteristics” on page 1055 for details.
6.3
Power-Up
This section summarizes the power-up sequence of the SAM R21. The behavior after power-up is controlled by the
Power Manager. Refer to “PM – Power Manager” on page 112 for details.
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6.3.1
Starting of Clocks
After power-up, the device is set to its initial state and kept in reset, until the power has stabilized throughout the device.
Once the power has stabilized, the device will use a 1MHz clock. This clock is derived from the 8MHz Internal Oscillator
(OSC8M), which is divided by eight and used as a clock source for generic clock generator 0. Generic clock generator 0
is the main clock for the Power Manager (PM).
Some synchronous system clocks are active, allowing software execution.
Refer to the “Clock Mask Register” section in “PM – Power Manager” on page 112 for the list of default peripheral clocks
running. Synchronous system clocks that are running are by default not divided and receive a 1MHz clock through
generic clock generator 0. Other generic clocks are disabled except GCLK_WDT, which is used by the Watchdog Timer
(WDT).
6.3.2
I/O Pins
After power-up, the I/O pins are tri-stated.
6.3.3
Fetching of Initial Instructions
After reset has been released, the CPU starts fetching PC and SP values from the reset address, which is 0x00000000.
This address points to the first executable address in the internal flash. The code read from the internal flash is free to
configure the clock system and clock sources. Refer to “PM – Power Manager” on page 112, “GCLK – Generic Clock
Controller” on page 90 and “SYSCTRL – System Controller” on page 143 for details. Refer to the ARM Architecture
Reference Manual for more information on CPU startup (http://www.arm.com).
6.4
Power-On Reset and Brown-Out Detector
The SAM R21 embeds three features to monitor, warn and/or reset the device:
6.4.1
z
POR: Power-on reset on VDDANA
z
BOD33: Brown-out detector on VDDANA
z
BOD12: Voltage Regulator Internal Brown-out detector on VDDCORE. The Voltage Regulator Internal BOD is
calibrated in production and its calibration configuration is stored in the NVM User Row. This configuration should
not be changed if the user row is written to assure the correct behavior of the BOD12.
Power-On Reset on VDDANA
POR monitors VDDANA. It is always activated and monitors voltage at startup and also during all the sleep modes. If
VDDANA goes below the threshold voltage, the entire chip is reset.
6.4.2
Brown-Out Detector on VDDANA
BOD33 monitors VDDANA. Refer to “SYSCTRL – System Controller” on page 143 for details.
6.4.3
Brown-Out Detector on VDDCORE
Once the device has started up, BOD12 monitors the internal VDDCORE.
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7.
Product Mapping
Figure 7-1. Atmel | SMART SAM R21 Product Mapping
Global Memory Space
0x00000000
Code
0x00000000
Internal Flash
Code
0x20000000
AHB-APB Bridge C
0x00400000
0x42000000
Reserved
SRAM
PAC2
0x42000400
0x1FFFFFFF
0x22008000
EVSYS
Undefined
0x40000000
0x42000800
SRAM
SERCOM0
0x42000C00
0x20000000
Peripherals
SERCOM1
Internal SRAM
0x42001000
SERCOM2
0x20008000
0x43000000
0x42001400
SERCOM3
Reserved
0x60000000
AHB-APB
0x42001800
SERCOM4
0x40000000
0x60000200
0x42001C00
AHB-APB
Bridge A
Undefined
SERCOM5
0x42002000
TCC0
0x41000000
AHB-APB
Bridge B
Reserved
(1)
0x42002400
TCC1
0x42002800
0xFFFFFFFF
0x42000000
TCC2
AHB-APB
Bridge C
0x42002C00
TC3
0x42FFFFFF
0x42003000
TC4
0x42003400
AHB-APB Bridge A
0x41002000
0x41004000
0x41004400
0x41004800
0x41005000
0x41006000
PTC
0x42005000
MTB
EIC
Reserved
Reserved
0x42005400
0x41004700
0x40001C00
Reserved
0x42004C00
USB
RTC
0x40001800
AC
0x42004800
DMAC
WDT
0x40001400
ADC
0x42004400
PORT
GCLK
0x40001000
Reserved
0x42004000
NVMCTRL
SYSCTRL
0x40000C00
Reserved
0x42003C00
DSU
PM
0x40000800
0x40FFFFFF
0x42003800
PAC1
PAC0
0x40000400
TC5
AHB-APB Bridge B
0x41000000
0x40000000
Reserved
0x41FFFFFF
RFCTRL
0x42005800
Reserved
Note 1. SERCOM4 is internally connected to the AT86RF233.
0x40FFFFFF
This figure represents the full configuration of the Atmel | SMART SAM R21 with maximum Flash and SRAM capabilities and a full
set of peripherals. Refer to the “Configuration Summary” on page 4 for details.
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8.
Memories
8.1
Embedded Memories
8.2
z
Internal high-speed flash
z
Internal high-speed RAM, single-cycle access at full speed
z
Stacked 512KB serial Flash (SAMR21E19A)
Physical Memory Map
The High-Speed bus is implemented as a bus matrix. All High-Speed bus addresses are fixed, and they are never
remapped in any way, even during boot. The 32-bit physical address space is mapped as follow:
Table 8-1.
SAM R21 physical memory map(1)
Size
Memory
Start address
SAMR21x19
SAMR21x18
SAMR21x17
SAMR21x16
Embedded Flash
0x00000000
256Kbytes
256Kbytes
128Kbytes
64Kbytes
Embedded SRAM
0x20000000
32Kbytes
32Kbytes
16Kbytes
8Kbytes
Peripheral Bridge A
0x40000000
64Kbytes
64Kbytes
64Kbytes
64Kbytes
Peripheral Bridge B
0x41000000
64Kbytes
64Kbytes
64Kbytes
64Kbytes
Peripheral Bridge C
0x42000000
64Kbytes
64Kbytes
64Kbytes
64Kbytes
Note:
1.
Table 8-2.
x = G or E. Refer to “Ordering Information” on page 6 for details.
Flash memory parameters(1)
Device
Flash size
Number of pages
Page size
SAMR21x19(3)
256Kbytes
4096
64 bytes
SAMR21x18
256Kbytes
4096
64 bytes
SAMR21x17
128Kbytes
2046
64 bytes
SAMR21x16
64Kbytes
1024
64 bytes
Note:
1.
x = G or E. Refer to “Ordering Information” on page 6 for details.
2.
The number of pages (NVMP) and page size (PSZ) can be read from the NVM Pages and Page Size bits in
the NVM Parameter register in the NVMCTRL (PARAM.NVMP and PARAM.PSZ, respectively). Refer to
PARAM for details.
3.
The Flash memory parameters refers to the embedded memories: SAMR21x19 shares same embedded
memories as SAMR21x18.
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8.3
NVM Calibration and Auxiliary Space
The device calibration data are stored in different sections of the NVM calibration and auxiliary space presented in Figure
8-1.
Figure 8-1. Calibration and Auxiliary Space
AUX1
0x00806040
800000
Calibration and
auxiliary space
Area 4: Software
calibration area (256bits)
NVM base address +
0x00800000
0x00806020
Area 4 offset add
Area 3: Reserved
(128bits)
NVM base address
+ NVM size
0x00806010
NVM main address
space
0x00806008
Area 2: Device configuration
area (64 bits)
Area 2 offset ad
Area 1: Reserved (64 bits)
0x00806000
000000
Area 3 offset ad
Area 1 address
NVM Base Address
AUX1
0x00806000
AUX1 offset address
0x00804000
AUX0 – NVM User
Row
0x00800000
Automatic calibration
row
AUX0 offset address
Calibration and auxiliary
space address offset
The values from the automatic calibration row are loaded into their respective registers at startup.
8.3.1
NVM User Row Mapping
The NVM User Row contains calibration data that are automatically read at device power on.
The NVM User Row can be read at address 0x804000.
To write the NVM User Row refer to “NVMCTRL – Non-Volatile Memory Controller” on page 350.
Note that when writing to the user row the values do not get loaded by the other modules on the device until a device
reset occurs.
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Table 8-3.
8.3.2
NVM User Row Mapping
Bit Position
Name
Usage
2:0
BOOTPROT
3
Reserved
6:4
EEPROM
7
Reserved
13:8
BOD33 Level
BOD33 Threshold Level at power on. Refer to BOD33 register.
Default value = 7.
14
BOD33 Enable
BOD33 Enable at power on . Refer to BOD33 register. Default value = 1.
16:15
BOD33 Action
BOD33 Action at power on. Refer to BOD33 register. Default value = 1.
24:17
Reserved
25
WDT Enable
WDT Enable at power on. Refer to WDT CTRL register.
Default value = 0.
26
WDT Always-On
WDT Always-On at power on. Refer to WDT CTRL register.
Default value = 0.
30:27
WDT Period
WDT Period at power on. Refer to WDT CONFIG register.
Default value = 0x0B.
34:31
WDT Window
WDT Window mode time-out at power on. Refer to WDT CONFIG register.
Default value = 0x05.
38:35
WDT EWOFFSET
WDT Early Warning Interrupt Time Offset at power on. Refer to WDT
EWCTRL register. Default value = 0x0B.
39
WDT WEN
WDT Timer Window Mode Enable at power on. Refer to WDT CTRL register.
Default value = 0.
40
BOD33 Hysteresis
BOD33 Hysteresis configuration at power on. Refer to BOD33 register.
Default value = 0.
41
Reserved
47:42
Reserved
63:48
LOCK
Used to select one of eight different bootloader sizes. Refer to “NVMCTRL –
Non-Volatile Memory Controller” on page 350. Default value = 7.
Used to select one of eight different EEPROM sizes. Refer to “NVMCTRL –
Non-Volatile Memory Controller” on page 350. Default value = 7.
Voltage Regulator Internal BOD (BOD12) configuration. These bits are written
in production and must not be changed. Default value = 0x70.
Voltage Regulator Internal BOD(BOD12) configuration. This bit is written in
production and must not be changed. Default value = 0.
NVM Region Lock Bits. Refer to “NVMCTRL – Non-Volatile Memory
Controller” on page 350.
Default value = 0xFFFF.
NVM Software Calibration Area Mapping
The NVM Software Calibration Area contains calibration data that are measured and written during production test.
These calibration values should be read by the application software and written back to the corresponding register.
The NVM Software Calibration Area can be read at address 0x806020.
The NVM Software Calibration Area can not be written.
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Table 8-4.
8.3.3
NVM Software Calibration Area Mapping
Bit Position
Name
Description
2:0
Reserved
14:3
Reserved
26:15
Reserved
34:27
ADC LINEARITY
ADC Linearity Calibration. Should be written to CALIB register.
37:35
ADC BIASCAL
ADC Bias Calibration. Should be written to CALIB register.
44:38
OSC32K CAL
OSC32KCalibration. Should be written to OSC32K register.
49:45
USB TRANSN
USB TRANSN calibration value. Should be written to PADCAL register.
54:50
USB TRANSP
USB TRANSP calibration value. Should be written to PADCAL register.
57:55
USB TRIM
USB TRIM calibration value. Should be written to the PADCAL register.
63:58
DFLL48M COARSE CAL
DFLL48M Coarse calibration value. Should be written to DFLLVAL register.
73:64
DFLL48M FINE CAL
DFLL48M Fine calibration value. Should be written to DFLLVAL register.
127:74
Reserved
Serial Number
Each device has a unique 128-bit serial number which is a concatenation of four 32-bit words contained at the following
addresses:
Word 0: 0x0080A00C
Word 1: 0x0080A040
Word 2: 0x0080A044
Word 3: 0x0080A048
The uniqueness of the serial number is guaranteed only when using all 128 bits.
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9.
Processor And Architecture
9.1
Cortex M0+ Processor
The Atmel | SMART SAM R21 implements the ARM® Cortex™-M0+ processor, based on the ARMv6 Architecture and
Thumb®-2 ISA. The Cortex M0+ is 100% instruction set compatible with its predecessor, the Cortex-M0 core, and
upward compatible to Cortex-M3 and M4 cores. The ARM Cortex-M0+ implemented is revision r0p1. For more
information refer to www.arm.com.
9.1.1
Cortex M0+ Configuration
Table 9-1.
Cortex M0+ Configuration
Features
Configurable option
Atmel | SMART SAM R21
configuration
Interrupts
External interrupts 0-32
28
Data endianness
Little-endian or big-endian
Little-endian
SysTick timer
Present or absent
Present
Number of watchpoint comparators
0, 1, 2
2
Number of breakpoint comparators
0, 1, 2, 3, 4
4
Halting debug support
Present or absent
Present
Multiplier
Fast or small
Fast (single cycle)
Single-cycle I/O port
Present or absent
Present
Wake-up interrupt controller
Supported or not supported
Not supported
Vector Table Offset Register
Present or absent
Present
Unprivileged/Privileged support
Present or absent
Absent(1)
Memory Protection Unit
Not present or 8-region
Not present
Reset all registers
Present or absent
Absent
Instruction fetch width
16-bit only or mostly 32-bit
32-bit
Note:
1.
All software run in privileged mode only.
The ARM Cortex-M0+ core has two bus interfaces:
9.1.2
z
Single 32-bit AMBA-3 AHB-Lite system interface that provides connections to peripherals and all system
memory, which includes flash and RAM.
z
Single 32-bit I/O port bus interfacing to the PORT with 1-cycle loads and stores.
Cortex-M0+ Peripherals
z
System Control Space (SCS)
z
z
The processor provides debug through registers in the SCS. Refer to the Cortex-M0+ Technical Reference
Manual for details (www.arm.com).
System Timer (SysTick)
z
The System Timer is a 24-bit timer that extends the functionality of both the processor and the NVIC. Refer
to the Cortex-M0+ Technical Reference Manual for details (www.arm.com).
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z
Nested Vectored Interrupt Controller (NVIC)
z
z
System Control Block (SCB)
z
z
The System Control Block provides system implementation information, and system control. This includes
configuration, control, and reporting of the system exceptions. Refer to the Cortex-M0+ Devices Generic
User Guide for details (www.arm.com).
Micro Trace Buffer (MTB)
z
9.1.3
External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts. Software can set the
priority of each interrupt. The NVIC and the Cortex-M0+ processor core are closely coupled, providing low
latency interrupt processing and efficient processing of late arriving interrupts. Refer to “Nested Vector
Interrupt Controller” on page 29 and the Cortex-M0+ Technical Reference Manual for details
(www.arm.com).
The CoreSight MTB-M0+ (MTB) provides a simple execution trace capability to the Cortex-M0+ processor.
Refer to section “Micro Trace Buffer” on page 31 and the CoreSight MTB-M0+ Technical Reference Manual
for details (www.arm.com).
Cortex-M0+ Address Map
Table 9-2.
Cortex-M0+ Address Map
Address
Peripheral
0xE000E000
System Control Space (SCS)
0xE000E010
System Timer (SysTick)
0xE000E100
Nested Vectored Interrupt Controller (NVIC)
0xE000ED00
System Control Block (SCB)
0x41006000 (see also “Product Mapping” on page 23)
Micro Trace Buffer (MTB)
9.1.4
I/O Interface
9.1.4.1
Overview
Because accesses to the AMBA® AHB-Lite™ and the single cycle I/O interface can be made concurrently, the CortexM0+ processor can fetch the next instructions while accessing the I/Os. This enables single cycle I/O accesses to be
sustained for as long as needed. Refer to “CPU Local Bus” on page 375 for more information.
9.1.4.2
Description
Direct access to PORT registers.
9.2
Nested Vector Interrupt Controller
9.2.1
Overview
The Nested Vectored Interrupt Controller (NVIC) in the SAM R21 supports 32 interrupt lines with four different priority
levels. For more details, refer to the Cortex-M0+ Technical Reference Manual (www.arm.com).
9.2.2
Interrupt Line Mapping
Each of the 28 interrupt lines is connected to one peripheral instance, as shown in the table below. Each peripheral can
have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear (INTFLAG) register. The
interrupt flag is set when the interrupt condition occurs. Each interrupt in the peripheral can be individually enabled by
writing a one to the corresponding bit in the peripheral’s Interrupt Enable Set (INTENSET) register, and disabled by
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writing a one to the corresponding bit in the peripheral’s Interrupt Enable Clear (INTENCLR) register. An interrupt request
is generated from the peripheral when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt
requests for one peripheral are ORed together on system level, generating one interrupt request for each peripheral. An
interrupt request will set the corresponding interrupt pending bit in the NVIC interrupt pending registers
(SETPEND/CLRPEND bits in ISPR/ICPR). For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt
enable register (SETENA/CLRENA bits in ISER/ICER). The NVIC interrupt priority registers IPR0-IPR7 provide a priority
field for each interrupt.
Table 9-3.
Interrupt Line Mapping
Peripheral Source
EIC NMI – External Interrupt Controller
NVIC Line
NMI
PM – Power Manager
0
SYSCTRL – System Control
1
WDT – Watchdog Timer
2
RTC – Real Time Counter
3
EIC – External Interrupt Controller
4
NVMCTRL – Non-Volatile Memory Controller
5
DMAC - Direct Memory Access Controller
6
USB - Universal Serial Bus
7
EVSYS – Event System
8
SERCOM0 – Serial Communication Interface 0
9
SERCOM1 – Serial Communication Interface 1
10
SERCOM2 – Serial Communication Interface 2
11
SERCOM3 – Serial Communication Interface 3
12
SERCOM4 – Serial Communication Interface 4
13
SERCOM5 – Serial Communication Interface 5
14
TCC0 – Timer Counter for Control 0
15
TCC1 – Timer Counter for Control 1
16
TCC2 – Timer Counter for Control 2
17
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Table 9-3.
Interrupt Line Mapping (Continued)
Peripheral Source
TC3 – Timer Counter 3
18
TC4 – Timer Counter 4
19
TC5 – Timer Counter 5
20
Reserved
21
Reserved
22
ADC – Analog-to-Digital Converter
23
AC – Analog Comparator
24
Reserved
25
PTC – Peripheral Touch Controller
26
Reserved
27
9.3
Micro Trace Buffer
9.3.1
Features
9.3.2
NVIC Line
z
Program flow tracing for the Cortex-M0+ processor
z
MTB SRAM can be used for both trace and general purpose storage by the processor
z
The position and size of the trace buffer in SRAM is configurable by software
z
CoreSight compliant
Overview
When enabled, the MTB records changes in program flow, reported by the Cortex-M0+ processor over the execution
trace interface shared between the Cortex-M0+ processor and the CoreSight MTB-M0+. This information is stored as
trace packets in the SRAM by the MTB. An off-chip debugger can extract the trace information using the Debug Access
Port to read the trace information from the SRAM. The debugger can then reconstruct the program flow from this
information.
The MTB simultaneously stores trace information into the SRAM, and gives the processor access to the SRAM. The
MTB ensures that trace write accesses have priority over processor accesses.
The execution trace packet consists of a pair of 32-bit words that the MTB generates when it detects the processor PC
value changes non-sequentially. A non-sequential PC change can occur during branch instructions or during exception
entry. See the CoreSight MTB-M0+ Technical Reference Manual for more details on the MTB execution trace packet
format.
Tracing is enabled when the MASTER.EN bit in the Master Trace Control Register is 1. There are various ways to set the
bit to 1 to start tracing, or to 0 to stop tracing. See the CoreSight Cortex-M0+ Technical Reference Manual for more
details on the Trace start and stop and for a detailed description of the MTB’s MASTER register. The MTB can be
programmed to stop tracing automatically when the memory fills to a specified watermark level or to start or stop tracing
by writing directly to the MASTER.EN bit. If the watermark mechanism is not being used and the trace buffer overflows,
then the buffer wraps around overwriting previous trace packets.
The base address of the MTB registers is 0x41006000; this address is also written in the CoreSight ROM Table. The
offset of each register from the base address is fixed and as defined by the CoreSight MTB-M0+ Technical Reference
Manual. The MTB has 4 programmable registers to control the behavior of the trace features:
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z
POSITION: Contains the trace write pointer and the wrap bit,
z
MASTER: Contains the main trace enable bit and other trace control fields,
z
FLOW: Contains the WATERMARK address and the AUTOSTOP and AUTOHALT control bits,
z
BASE: Indicates where the SRAM is located in the processor memory map. This register is provided to enable
auto discovery of the MTB SRAM location, by a debug agent.
See the CoreSight MTB-M0+ Technical Reference Manual for a detailed description of these registers.
9.4
High-Speed Bus System
9.4.1
Features
High-Speed Bus Matrix has the following features:
z
Symmetric crossbar bus switch implementation
z
Allows concurrent accesses from different masters to different slaves
z
32-bit data bus
z
Operation at a one-to-one clock frequency with the bus masters
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Configuration
Multi-Slave
MASTERS
Table 9-4.
CM0+
0
DSU DSU
1
DMACDSU
Data
2
DMAC Data
DSU
MASTER ID
CM0+
3
DMAC Fetch
AHB-APB Bridge C
2
DMAC WB
AHB-APB Bridge B
1
USB
AHB-APB Bridge A
0
SRAM
MTB
Internal Flash
High-Speed Bus SLAVES
Priviledged SRAM-access
MASTERS
9.4.2
0
1
2
3
4
4
5
5
6
6
SLAVE ID
SRAM PORT ID
MTB
USB
DMAC WB
DMAC Fetch
Bus Matrix Masters
Bus Matrix Masters
Master ID
CM0+ - Cortex M0+ Processor
0
DSU - Device Service Unit
1
DMAC - Direct Memory Access Controller / Data Access
2
Table 9-5.
Bus Matrix Slaves
Bus Matrix Slaves
Slave ID
Internal Flash Memory
0
AHB-APB Bridge A
1
AHB-APB Bridge B
2
AHB-APB Bridge C
3
SRAM Port 4 - CM0+ Access
4
SRAM Port 5 - DMAC Data Access
5
SRAM Port 6 - DSU Access
6
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Table 9-6.
9.4.3
SRAM Port Connection
SRAM Port Connection
Port ID
Connection Type
MTB - Micro Trace Buffer
0
Direct
USB - Universal Serial Bus
1
Direct
DMAC - Direct Memory Access Controller - Write-Back Access
2
Direct
DMAC - Direct Memory Access Controller - Fetch Access
3
Direct
CM0+ - Cortex M0+ Processor
4
Bus Matrix
DMAC - Direct Memory Access Controller - Data Access
5
Bus Matrix
DSU - Device Service Unit
6
Bus Matrix
SRAM Quality of Service
To ensure that masters with latency requirements get sufficient priority when accessing RAM, the different masters can
be configured to have a given priority for different type of access.
The Quality of Service (QoS) level is independently selected for each master accessing the RAM. For any access to the
RAM the RAM also receives the QoS level. The QoS levels and their corresponding bit values for the QoS level
configuration is shown in Table 9-7.
Table 9-7.
Value
Quality of Service
Name
Description
00
DISABLE
Background (no sensitive operation)
01
LOW
Sensitive Bandwidth
10
MEDIUM
Sensitive Latency
11
HIGH
Critical Latency
If a master is configured with QoS level 0x00 or 0x01 there will be minimum one cycle latency for the RAM access.
The priority order for concurrent accesses are decided by two factors. First the QoS level for the master and then a static
priority given by table nn-mm (table: SRAM port connection) where the lowest port ID has the highest static priority.
The MTB has fixed QoS level 3 and the DSU has fixed QoS level 1.
The CPU QoS level can be written/read at address 0x41007110, bits [1:0]. Its reset value is 0x0.
Refer to different master QOSCTRL registers for configuring QoS for the other masters (USB, DMAC).
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9.5
AHB-APB Bridge
The AHB-APB bridge is an AHB slave, providing an interface between the high-speed AHB domain and the low-power
APB domain. It is used to provide access to the programmable control registers of peripherals (see “Product Mapping” on
page 23).
AHB-APB bridge is based on AMBA APB Protocol Specification V2.0 (ref. as APB4) including:
z Wait state support
z Error reporting
z Transaction protection
z Sparse data transfer (byte, half-word and word)
Additional enhancements:
z Address and data cycles merged into a single cycle
z Sparse data transfer also apply to read access
to operate the AHB-APB bridge, the clock (CLK_HPBx_AHB) must be enabled. See “PM – Power Manager” on page 112
for details.
Figure 9-1. APB Write Access.
T0
T1
T2
PCLK
PADDR
T3
T0
T2
T3
T4
T5
PCLK
Addr 1
PADDR
PWRITE
PWRITE
PSEL
PSEL
PENABLE
PENABLE
PWDATA
T1
Data 1
PREADY
PWDATA
Addr 1
Data 1
PREADY
No wait states
Wait states
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Figure 9-2. APB Read Access.
T0
T1
T2
T3
T0
PCLK
PADDR
T2
T3
T4
T5
PCLK
Addr 1
PADDR
PWRITE
PWRITE
PSEL
PSEL
PENABLE
PENABLE
PRDATA
T1
Data 1
PREADY
Addr 1
PRDATA
Data 1
PREADY
No wait states
9.6
PAC – Peripheral Access Controller
9.6.1
Overview
Wait states
There is one PAC associated with each AHB-APB bridge. The PAC can provide write protection for registers of each
peripheral connected on the same bridge.
The PAC peripheral bus clock (CLK_PACx_APB) can be enabled and disabled in the Power Manager. CLK_PAC0_APB
and CLK_PAC1_APB are enabled are reset. CLK_PAC2_APB is disabled at reset. Refer to “PM – Power Manager” on
page 112 for details. The PAC will continue to operate in any sleep mode where the selected clock source is running.
Write-protection does not apply for debugger access. When the debugger makes an access to a peripheral, writeprotection is ignored so that the debugger can update the register.
Write-protect registers allow the user to disable a selected peripheral’s write-protection without doing a read-modify-write
operation. These registers are mapped into two I/O memory locations, one for clearing and one for setting the register
bits. Writing a one to a bit in the Write Protect Clear register (WPCLR) will clear the corresponding bit in both registers
(WPCLR and WPSET) and disable the write-protection for the corresponding peripheral, while writing a one to a bit in the
Write Protect Set (WPSET) register will set the corresponding bit in both registers (WPCLR and WPSET) and enable the
write-protection for the corresponding peripheral. Both registers (WPCLR and WPSET) will return the same value when
read.
If a peripheral is write-protected, and if a write access is performed, data will not be written, and the peripheral will return
an access error (CPU exception).
The PAC also offers a safety feature for correct program execution, with a CPU exception generated on double writeprotection or double unprotection of a peripheral. If a peripheral n is write-protected and a write to one in WPSET[n] is
detected, the PAC returns an error. This can be used to ensure that the application follows the intended program flow by
always following a write-protect with an unprotect, and vice versa. However, in applications where a write-protected
peripheral is used in several contexts, e.g., interrupts, care should be taken so that either the interrupt can not happen
while the main application or other interrupt levels manipulate the write-protection status, or when the interrupt handler
needs to unprotect the peripheral, based on the current protection status, by reading WPSET.
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9.6.2
Register Description
Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters and 16-bit halves of a 32-bit register, and
the 8-bit halves of a 16-bit register can be accessed directly.
Refer to “Product Mapping” on page 23 for PAC locations.
9.6.2.1
PAC0 Register Description
Write Protect Clear
Name:
WPCLR
Offset:
0x00
Reset:
0x00000000
Property:
-
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
EIC
RTC
WDT
GCLK
SYSCTRL
PM
Access
R
R/W
R/W
R/W
R/W
R/W
R/W
R
Reset
0
0
0
0
0
0
0
0
z
Bits 31:7 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 6:1 – EIC, RTC, WDT, GCLK, SYSCTRL, PM: Write Protect Disable
0: Write-protection is disabled.
1: Write-protection is enabled.
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bits for the corresponding peripherals.
z
Bit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
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Write Protect Set
Name:
WPSET
Offset:
0x04
Reset:
0x00000000
Property:
-
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
EIC
RTC
WDT
GCLK
SYSCTRL
PM
Access
R
R/W
R/W
R/W
R/W
R/W
R/W
R
Reset
0
0
0
0
0
0
0
0
z
Bits 31:7 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 6:1 – EIC, RTC, WDT, GCLK, SYSCTRL, PM: Write Protect Enable
0: Write-protection is disabled.
1: Write-protection is enabled.
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write Protect bit for the corresponding peripherals.
z
Bit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
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9.6.2.2
PAC1 Register Description
Write Protect Clear
Name:
WPCLR
Offset:
0x00
Reset:
0x00000002
Property:
-
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
MTB
USB
DMAC
PORT
NVMCTRL
DSU
Access
R
R/W
R/W
R/W
R/W
R/W
R/W
R
Reset
0
0
0
0
0
0
1
0
z
Bits 31:7 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 6:1 – MTB, USB, DMAC, PORT, NVMCTRL, DSU: Write Protect
0: Write-protection is disabled.
1: Write-protection is enabled.
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
z
Bit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
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Write Protect Set
Name:
WPSET
Offset:
0x04
Reset:
0x00000002
Property:
-
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
MTB
USB
DMAC
PORT
NVMCTRL
DSU
Access
R
R/W
R/W
R/W
R/W
R/W
R/W
R
Reset
0
0
0
0
0
0
1
0
z
Bits 31:7 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 6:1 – MTB, USB, DMAC, PORT, NVMCTRL, DSU: Write Protect
0: Write-protection is disabled.
1: Write-protection is enabled.
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write Protect bit for the corresponding peripherals.
z
Bit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
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40
9.6.2.3
PAC2 Register Description
Write Protect Clear
Name:
WPCLR
Offset:
0x00
Reset:
0x00800000
Property:
-
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
AC
ADC
RFCTRL
PTC
Access
R
R
R/W
R
R/W
R
R/W
R/W
Reset
1
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
TC5
TC4
TC3
TCC2
TCC1
TCC0
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
SERCOM5
SERCOM4
SERCOM3
SERCOM2
SERCOM1
SERCOM0
EVSYS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
0
0
0
0
0
0
0
0
Access
Reset
z
Bits 31:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
reset value when this register is written. These bits will always return reset value when read.
z
Bits 21,19,17:16,13:1 – RFCTRL, PTC, AC, ADC, TC5, TC4, TC3, TCC2, TCC1, TCC0, SERCOM5, SERCOM4,
SERCOM3, SERCOM2, SERCOM1, SERCOM0, EVSYS: Write Protect
0: Write-protection is disabled.
1: Write-protection is enabled.
Writing a zero to these bits has no effect.
Writing a one to these bits will clear the Write Protect bit for the corresponding peripherals.
z
Bit 18,15,14,0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
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41
Write Protect Set
Name:
WPSET
Offset:
0x04
Reset:
0x00800000
Property:
-
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
AC
ADC
RFCTRL
PTC
Access
R
R
R/W
R
R/W
R
R/W
R/W
Reset
1
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
TC5
TC4
TC3
TCC2
TCC1
TCC0
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
SERCOM5
SERCOM4
SERCOM3
SERCOM2
SERCOM1
SERCOM0
EVSYS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
0
0
0
0
0
0
0
0
Access
Reset
z
Bits 31:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
reset value when this register is written. These bits will always return reset value when read.
z
Bits 21,19,17:16,13:1 – RFCTRL, PTC, AC, ADC, TC5, TC4, TC3, TCC2, TCC1, TCC0, SERCOM5, SERCOM4,
SERCOM3, SERCOM2, SERCOM1, SERCOM0, EVSYS: Write Protect
0: Write-protection is disabled.
1: Write-protection is enabled.
Writing a zero to these bits has no effect.
Writing a one to these bits will set the Write Protect bit for the corresponding peripherals.
z
Bit 18,15,14,0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
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42
10.
Peripherals Configuration Summary
Table 10-1. Peripherals Configuration Summary
AHB Clock
Peripheral
Name
Base
Address
AHB-APB
Bridge A
0x40000000
PAC0
0x40000000
PM
0x40000400
SYSCTRL
0x40000800
GCLK
0x40000C00
WDT
0x40001000
RTC
IRQ
Line
Index
Enabled
at Reset
0
Y
0
Index
Enabled
at Reset
0
Y
1
Y
Generic Clock
Index
0: DFLL48M
reference
1: FDPLL96M clk
source
2: FDPLL96M
32kHz
PAC
Events
DMA
Index
Prot at
Reset
1
N
Y
2
N
Y
3
N
Y
User
Generator
Index
SleepWalking
2
Y
3
Y
2
4
Y
3
4
N
0x40001400
3
5
Y
4
5
N
1: CMP0/ALARM0
2: CMP1
3: OVF
4-11: PER0-7
Y
EIC
0x40001800
NMI,
4
6
Y
5
6
N
12-27: EXTINT0-15
Y
AHB-APB
Bridge B
0x41000000
PAC1
0x41000000
0
Y
DSU
0x41002000
NVMCTRL
0x41004000
1
APB Clock
1
Y
3
Y
1
Y
1
Y
5
4
Y
2
Y
2
N
[DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
PORT
0x41004400
3
Y
3
N
DMAC
0x41004800
6
5
Y
4
Y
4
N
USB
0x41005000
7
6
Y
5
Y
5
N
6
N
MTB
0x41006000
AHB-APB
Bridge C
0x42000000
PAC2
0x42000000
EVSYS
0x42000400
SERCOM0
2
6
0-3: CH0-3
30-33: CH0-3
Y
Y
0
N
8
1
N
7-18: one per
CHANNEL
1
N
0x42000800
9
2
N
20: CORE
19: SLOW
2
N
1: RX
2: TX
Y
SERCOM1
0x42000C00
10
3
N
21: CORE
19: SLOW
3
N
3: RX
4: TX
Y
SERCOM2
0x42001000
11
4
N
22: CORE
19: SLOW
4
N
5: RX
6: TX
Y
Y
43
Table 10-1. Peripherals Configuration Summary
AHB Clock
Peripheral
Name
Base
Address
IRQ
Line
Index
Enabled
at Reset
APB Clock
Index
Enabled
at Reset
Generic Clock
Index
PAC
Index
Events
Prot at
Reset
User
Generator
DMA
Index
SleepWalking
N
7: RX
8: TX
Y
SERCOM3
0x42001400
12
5
N
23: CORE
19: SLOW
SERCOM4
0x42001800
13
6
N
24: CORE
19: SLOW
6
N
9: RX
10: TX
Y
SERCOM5
0x42001C00
14
7
N
25: CORE
19: SLOW
7
N
11: RX
12: TX
Y
TCC0
0x42002000
15
8
N
26
8
N
4-5: EV0-1
6-9: MC0-3
34: OVF
35: TRG
36: CNT
37-40: MC0-3
13: OVF
14-17: MC0-3
Y
N
10-11: EV0-1
12-13: MC0-1
41: OVF
42: TRG
43: CNT
44-45: MC0-1
18: OVF
19-20: MC0-1
Y
46: OVF
47: TRG
48: CNT
49-50: MC0-1
21: OVF
22-23: MC0-1
Y
TCC1
0x42002400
16
9
N
26
5
9
[DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
TCC2
0x42002800
17
10
N
27
10
N
14-15: EV0-1
16-17: MC0-1
TC3
0x42002C00
18
11
N
27
11
N
18: EV
51: OVF
52-53: MC0-1
24: OVF
25-26: MC0-1
Y
TC4
0x42003000
19
12
N
28
12
N
19: EV
54: OVF
55-56: MCX0-1
27: OVF
28-29: MC0-1
Y
TC5
0x42003400
20
13
N
28
13
N
20: EV
57: OVF
58-59: MC0-1
30: OVF
31-32: MC0-1
Y
ADC
0x42004000
23
16
Y
30
16
N
23: START
24: SYNC
66: RESRDY
67: WINMON
39: RESRDY
Y
AC
0x42004400
24
17
N
31: DIG
32: ANA
17
N
25-26: SOC0-1
68-69: COMP0-1
70: WIN0
PTC
0x42004C00
26
19
N
34
19
N
28: STCONV
72: EOC
73: WCOMP
RFCTRL
0x42005400
21
N
21
N
Y
44
11.
DSU – Device Service Unit
11.1
Overview
The Device Service Unit (DSU) provides a means to detect debugger probes. This enables the ARM Debug Access Port
(DAP) to have control over multiplexed debug pads and CPU reset. The DSU also provides system-level services to
debug adapters in an ARM debug system. It implements a CoreSight Debug ROM that provides device identification as
well as identification of other debug components in the system. Hence, it complies with the ARM Peripheral Identification
specification. The DSU also provides system services to applications that need memory testing, as required for
IEC60730 Class B compliance, for example. The DSU can be accessed simultaneously by a debugger and the CPU, as
it is connected on the High-Speed Bus Matrix. For security reasons, some of the DSU features will be limited or
unavailable when the device is protected by the NVMCTRL security bit (refer to “Security Bit” on page 356).
11.2
Features
z CPU reset extension
z Debugger probe detection (Cold- and Hot-Plugging)
z Chip-Erase command and status
z 32-bit cyclic redundancy check (CRC32) of any memory accessible through the bus matrix
z ARM® CoreSight™ compliant device identification
z Two debug communications channels
z Debug access port security filter
z Onboard memory built-in self-test (MBIST)
11.3
Block Diagram
Figure 11-1. DSU Bock Diagram
DSU
debugger_present
RESET
SWCLK
DEBUGGER PROBE
INTERFACE
cpu_reset_extension
CPU
DAP
AHB-AP
DAP SECURITY FILTER
NVMCTRL
DBG
CORESIGHT ROM
PORT
M
S
CRC-32
SWDIO
MBIST
M
HIGH-SPEED
HIGH-SPEE
BUS
US MATRIX
M
MATR
CHIP ERASE
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11.4
Signal Description
Signal Name
Type
Description
RESET
Digital Input
External reset
SWCLK
Digital Input
SW clock
SWDIO
Digital I/O
SW bidirectional data pin
Refer to “I/O Multiplexing and Considerations” on page 12 for details on the pin mapping for this peripheral.
11.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
11.5.1 I/O Lines
The SWCLK pin is by default assigned to the DSU module to allow debugger probe detection and the condition to stretch
the CPU reset phase. For more information, refer to “Debugger Probe Detection” on page 47. The Hot-Plugging feature
depends on the PORT configuration. If the SWCLK pin function is changed in the PORT or if the PORT_MUX is disabled,
the Hot-Plugging feature is disabled until a power-reset or an external reset.
11.5.2 Power Management
The DSU will continue to operate in any sleep mode where the selected source clock is running.
Refer to “PM – Power Manager” on page 112 for details on the different sleep modes.
11.5.3 Clocks
The DSU bus clocks (CLK_DSU_APB and CLK_DSU_AHB) can be enabled and disabled in the Power Manager. For
more information on the CLK_DSU_APB and CLK_DSU_AHB clock masks, refer to “PM – Power Manager” on page
112.
11.5.4 DMA
Not applicable.
11.5.5 Interrupts
Not applicable.
11.5.6 Events
Not applicable.
11.5.7 Register Access Protection
All registers with write access are optionally write-protected by the Peripheral Access Controller (PAC), except the
following registers:
z
Debug Communication Channel 0 register (DCC0)
z
Debug Communication Channel 1 register (DCC1)
Write-protection is denoted by the Write-Protection property in the register description.
Write-protection does not apply for accesses through an external debugger. Refer to “PAC – Peripheral Access
Controller” on page 36 for details.
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11.5.8 Analog Connections
Not applicable.
11.6
Debug Operation
11.6.1 Principle of Operation
The DSU provides basic services to allow on-chip debug using the ARM Debug Access Port and the ARM processor
debug resources:
z
CPU reset extension
z
Debugger probe detection
For more details on the ARM debug components, refer to the ARM Debug Interface v5Architecture Specification.
11.6.2 CPU Reset Extension
“CPU reset extension” refers to the extension of the reset phase of the CPU core after the external reset is released. This
ensures that the CPU is not executing code at startup while a debugger connects to the system. It is detected on a
RESET release event when SWCLK is low. At startup, SWCLK is internally pulled up to avoid false detection of a
debugger if SWCLK is left unconnected. When the CPU is held in the reset extension phase, the CPU Reset Extension
bit (CRSTEXT) of the Status A register (STATUSA.CRSTEXT) is set. To release the CPU, write a one to
STATUSA.CRSTEXT. STATUSA.CRSTEXT will then be set to zero. Writing a zero to STATUSA.CRSTEXT has no
effect. For security reasons, it is not possible to release the CPU reset extension when the device is protected by the
NVMCTRL security bit (refer to “Security Bit” on page 356). Trying to do so sets the Protection Error bit (PERR) of the
Status A register (STATUSA.PERR).
Figure 11-2. Typical CPU Reset Extension Set and Clear Timing Diagram
SWCLK
RESET
DSU CRSTEXT
Clear
CPU reset
extension
CPU_STATE
reset
running
11.6.3 Debugger Probe Detection
11.6.3.1 Cold-Plugging
Cold-Plugging is the detection of a debugger when the system is in reset. Cold-Plugging is detected when the CPU reset
extension is requested, as described above.
11.6.3.2 Hot-Plugging
Hot-Plugging is the detection of a debugger probe when the system is not in reset. Hot-Plugging is not possible under
reset because the detector is reset when POR or RESET are asserted. Hot-Plugging is active when a SWCLK falling
edge is detected. The SWCLK pad is multiplexed with other functions and the user must ensure that its default function is
assigned to the debug system. If the SWCLK function is changed, the Hot-Plugging feature is disabled until a power-
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reset or external reset occurs. Availability of the Hot-Plugging feature can be read from the Hot-Plugging Enable bit of the
Status B register (STATUSB.HPE).
Figure 11-3. Hot-Plugging Detection Timing Diagram
SWCLK
RESET
CPU_STATE
reset
running
Hot-Plugging
The presence of a debugger probe is detected when either Hot-Plugging or Cold-Plugging is detected. Once detected,
the Debugger Present bit of the Status B register (STATUSB.DBGPRES) is set. For security reasons, Hot-Plugging is not
available when the device is protected by the NVMCTRL security bit (refer to “Security Bit” on page 356).
This detection requires that pads are correctly powered. Thus, at cold startup, this detection cannot be done until POR is
released. If the device is protected, Cold-Plugging is the only way to detect a debugger probe, and so the external reset
timing must be longer than the POR timing. If external reset is deasserted before POR release, the user must retry the
procedure above until it gets connected to the device.
11.7
Chip-Erase
Chip-Erase consists of removing all sensitive information stored in the chip and clearing the NVMCTRL security bit (refer
to “Security Bit” on page 356). Hence, all volatile memories and the flash array (including the EEPROM emulation area)
will be erased. The flash auxiliary rows, including the user row, will not be erased. When the device is protected, the
debugger must reset the device in order to be detected. This ensures that internal registers are reset after the protected
state is removed. The Chip-Erase operation is triggered by writing a one to the Chip-Erase bit in the Control register
(CTRL.CE). This command will be discarded if the DSU is protected by the Peripheral Access Controller (PAC). Once
issued, the module clears volatile memories prior to erasing the flash array. To ensure that the Chip-Erase operation is
completed, check the Done bit of the Status A register (STATUSA.DONE). The Chip-Erase operation depends on clocks
and power management features that can be altered by the CPU. For that reason, it is recommended to issue a ChipErase after a Cold-Plugging procedure to ensure that the device is in a known and safe state.
The recommended sequence is as follows:
1.
2.
11.8
Issue the Cold-Plugging procedure (refer to “Cold-Plugging” on page 47). The device then:
1.
Detects the debugger probe
2.
Holds the CPU in reset
Issue the Chip-Erase command by writing a one to CTRL.CE. The device then:
1.
Clears the system volatile memories
2.
Erases the whole flash array (including the EEPROM emulation area, not including auxiliary rows)
3.
Erases the lock row, removing the NVMCTRL security bit protection
3.
Check for completion by polling STATUSA.DONE (read as one when completed).
4.
Reset the device to let the NVMCTRL update fuses.
Programming
Programming of the flash or RAM memories is available when the device is not protected by the NVMCTRL security bit
(refer to “Security Bit” on page 356).
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11.9
1.
At power up, RESET is driven low by a debugger. The on-chip regulator holds the system in a POR state until the
input supply is above the POR threshold (refer to “Power-On Reset (POR) Characteristics” on page 1069). The
system continues to be held in this static state until the internally regulated supplies have reached a safe operating
state.
2.
The PM starts, clocks are switched to the slow clock (Core Clock, System Clock, Flash Clock and any Bus Clocks
that do not have clock gate control). Internal resets are maintained due to the external reset.
3.
The debugger maintains a low level on SWCLK. Releasing RESET results in a debugger Cold-Plugging
procedure.
4.
The debugger generates a clock signal on the SWCLK pin, the Debug Access Port (DAP) receives a clock.
5.
The CPU remains in reset due to the Cold-Plugging procedure; meanwhile, the rest of the system is released.
6.
A Chip-Erase is issued to ensure that the flash is fully erased prior to programming.
7.
Programming is available through the AHB-AP.
8.
After operation is completed, the chip can be restarted either by asserting RESET, toggling power or writing a one
to the Status A register CPU Reset Phase Extension bit (STATUSA.CRSTEXT). Make sure that the SWCLK pin is
high when releasing RESET to prevent extending the CPU reset.
Intellectual Property Protection
Intellectual property protection consists of restricting access to internal memories from external tools when the device is
protected, and is accomplished by setting the NVMCTRL security bit (refer to “Security Bit” on page 356). This protected
state can be removed by issuing a Chip-Erase (refer to “Chip-Erase” on page 48). When the device is protected,
read/write accesses using the AHB-AP are limited to the DSU address range and DSU commands are restricted.
The DSU implements a security filter that monitors the AHB transactions generated by the ARM AHB-AP inside the DAP.
If the device is protected, then AHB-AP read/write accesses outside the DSU external address range are discarded,
causing an error response that sets the ARM AHB-AP sticky error bits (refer to the ARM Debug Interface v5 Architecture
Specification on http://www.arm.com).
The DSU is intended to be accessed either:
z
Internally from the CPU, without any limitation, even when the device is protected
z
Externally from a debug adapter, with some restrictions when the device is protected
For security reasons, DSU features have limitations when used from a debug adapter. To differentiate external accesses
from internal ones, the first 0x100 bytes of the DSU register map have been replicated at offset 0x100:
z
The first 0x100 bytes form the internal address range
z
The next 0x100 bytes form the external address range
When the device is protected, the DAP can only issue MEM-AP accesses in the DSU address range limited to the 0x1000x2000 offset range.
The DSU operating registers are located in the 0x00-0xFF area and remapped in 0x100-0x1FF to differentiate accesses
coming from a debugger and the CPU. If the device is protected and an access is issued in the region 0x100-0x1FF, it is
subject to security restrictions. For more information, refer to Table 11-1.
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Figure 11-4. APB Memory Mapping
0x0000
DSU operating
registers
0x00FC
0x0100
0x01FD
Internal address range
(cannot be accessed from debug tools when the device is
protected by the NVMCTRL security bit)
Replicated
DSU operating
registers
Empty
External address range
(can be accessed from debug tools with some restrictions)
0x1000
DSU CoreSight
ROM
0x1FFC
Some features not activated by APB transactions are not available when the device is protected:
Table 11-1. Feature Availability Under Protection
Features
Availability When the Device is Protected
CPU reset extension
Yes
Debugger Cold-Plugging
Yes
Debugger Hot-Plugging
No
11.10 Device Identification
Device identification relies on the ARM CoreSight component identification scheme, which allows the chip to be identified
as an ATMEL device implementing a DSU. The DSU contains identification registers to differentiate the device.
11.10.1 CoreSight Identification
A system-level ARM CoreSight ROM table is present in the device to identify the vendor and the chip identification
method. Its address is provided in the MEM-AP BASE register inside the ARM Debug Access Port. The CoreSight ROM
implements a 64-bit conceptual ID composed as follows from the PID0 to PID7 CoreSight ROM Table registers:
Figure 11-5. Conceptual 64-Bit Peripheral ID
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Table 11-2. Conceptual 64-Bit Peripheral ID Bit Descriptions
Field
Size
JEP-106 CC code
4
Atmel continuation code: 0x0
JEP-106 ID code
7
Atmel device ID: 0x1F
4KB count
4
Indicates that the CoreSight component is a ROM: 0x0
PID4
RevAnd
4
Not used; read as 0
PID3
CUSMOD
4
Not used; read as 0
PID3
PARTNUM
12
Contains 0xCD0 to indicate that DSU is present
4
DSU revision (starts at 0x0 and increments by 1 at both major and minor
revisions). Identifies DSU identification method variants. If 0x0, this
indicates that device identification can be completed by reading the
Device Identification register (DID)
REVISION
Description
Location
PID4
PID1+PID2
PID0+PID1
PID3
For more information, refer to the ARM Debug Interface Version 5 Architecture Specification.
11.10.2 DSU Chip Identification Method:
The DSU DID register identifies the device by implementing the following information:
z
Processor identification
z
Product family identification
z
Product series identification
z
Device select
11.11 Functional Description
11.11.1 Principle of Operation
The DSU provides memory services such as CRC32 or MBIST that require almost the same interface. Hence, the
Address, Length and Data registers are shared. They must be configured first; then a command can be issued by writing
the Control register. When a command is ongoing, other commands are discarded until the current operation is
completed. Hence, the user must wait for the STATUSA.DONE bit to be set prior to issuing another one.
11.11.2 Basic Operation
11.11.2.1 Initialization
The module is enabled by enabling its clocks. For more details, refer to “Clocks” on page 46. The DSU registers can be
write-protected. Refer to “PAC – Peripheral Access Controller” on page 36.
11.11.2.2 Operation from a debug adapter
Debug adapters should access the DSU registers in the external address range 0x100 – 0x2000. If the device is
protected by the NVMCTRL security bit (refer to “Security Bit” on page 356), accessing the first 0x100 bytes causes the
system to return an error (refer to “Intellectual Property Protection” on page 49).
11.11.2.3 Operation from the CPU
There are no restrictions when accessing DSU registers from the CPU. However, the user should access DSU registers
in the internal address range (0x0 – 0x100) to avoid external security restrictions (refer to “Intellectual Property
Protection” on page 49).
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11.11.3 32-bit Cyclic Redundancy Check (CRC32)
The DSU unit provides support for calculating a cyclic redundancy check (CRC32) value for a memory area (including
flash and AHB RAM).
When the CRC32 command is issued from:
z
The internal range, the CRC32 can be operated at any memory location
z
The external range, the CRC32 operation is restricted; DATA, ADDR and LENGTH values are forced (see below)
Table 11-3. AMOD Bit Descriptions when Operating CRC32
AMOD[1:0]
Short Name
0
ARRAY
1
EEPROM
2-3
Reserved
External Range Restrictions
CRC32 is restricted to the full flash array area (EEPROM emulation area not included)
DATA forced to 0xFFFFFFFF before calculation (no seed)
CRC32 of the whole EEPROM emulation area
DATA forced to 0xFFFFFFFF before calculation (no seed)
The algorithm employed is the industry standard CRC32 algorithm using the generator polynomial 0xEDB88320
(reversed representation).
11.11.3.1 Starting CRC32 Calculation
CRC32 calculation for a memory range is started after writing the start address into the Address register (ADDR) and the
size of the memory range into the Length register (LENGTH). Both must be word-aligned.
The initial value used for the CRC32 calculation must be written to the Data register. This value will usually be
0xFFFFFFFF, but can be, for example, the result of a previous CRC32 calculation if generating a common CRC32 of
separate memory blocks.
Once completed, the calculated CRC32 value can be read out of the Data register. The read value must be
complemented to match standard CRC32 implementations or kept non-inverted if used as starting point for subsequent
CRC32 calculations.
If the device is in protected state by the NVMCTRL security bit (refer to “Security Bit” on page 356), it is only possible to
calculate the CRC32 of the whole flash array when operated from the external address space. In most cases, this area
will be the entire onboard non-volatile memory. The Address, Length and Data registers will be forced to predefined
values once the CRC32 operation is started, and values written by the user are ignored. This allows the user to verify the
contents of a protected device.
The actual test is started by writing a one in the 32-bit Cyclic Redundancy Check bit of the Control register (CTRL.CRC).
A running CRC32 operation can be canceled by resetting the module (writing a one to CTRL.SWRST).
11.11.3.2 Interpreting the Results
The user should monitor the Status A register. When the operation is completed, STATUSA.DONE is set. Then the Bus
Error bit of the Status A register (STATUSA.BERR) must be read to ensure that no bus error occurred.
11.11.4 Debug Communication Channels
The Debug Communication Channels (DCCO and DCC1) consist of a pair of registers with associated handshake logic,
accessible by both CPU and debugger even if the device is protected by the NVMCTRL security bit (refer to “Security Bit”
on page 356). The registers can be used to exchange data between the CPU and the debugger, during run time as well
as in debug mode. This enables the user to build a custom debug protocol using only these registers. The DCC0 and
DCC1 registers are accessible when the protected state is active. When the device is protected, however, it is not
possible to connect a debugger while the CPU is running (STATUSA.CRSTEXT is not writable and the CPU is held
under reset). Dirty bits in the status registers indicate whether a new value has been written in DCC0 or DCC1. These
bits,DCC0D and DCC1D, are located in the STATUSB registers. They are automatically set on write and cleared on
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read. The DCC0 and DCC1 registers are shared with the onboard memory testing logic (MBIST). Accordingly, DCC0 and
DCC1 must not be used while performing MBIST operations.
11.11.5 Testing of Onboard Memories (MBIST)
The DSU implements a feature for automatic testing of memory also known as MBIST. This is primarily intended for
production test of onboard memories. MBIST cannot be operated from the external address range when the device is
protected by the NVMCTRL security bit (refer to “Security Bit” on page 356). If a MBIST command is issued when the
device is protected, a protection error is reported in the Protection Error bit in the Status A register (STATUSA.PERR).
1.
Algorithm
The algorithm used for testing is a type of March algorithm called "March LR". This algorithm is able to detect a
wide range of memory defects, while still keeping a linear run time. The algorithm is:
1.
Write entire memory to 0, in any order.
2.
Bit for bit read 0, write 1, in descending order.
3.
Bit for bit read 1, write 0, read 0, write 1, in ascending order.
4.
Bit for bit read 1, write 0, in ascending order.
5.
Bit for bit read 0, write 1, read 1, write 0, in ascending order.
6.
Read 0 from entire memory, in ascending order.
The specific implementation used has a run time of O(14n) where n is the number of bits in the RAM. The detected
faults are:
2.
z
Address decoder faults
z
Stuck-at faults
z
Transition faults
z
Coupling faults
z
Linked Coupling faults
z
Stuck-open faults
Starting MBIST
To test a memory, you need to write the start address of the memory to the ADDR.ADDR bit group, and the size of
the memory into the Length register. See “Physical Memory Map” on page 24 to know which memories are available, and which address they are at.
For best test coverage, an entire physical memory block should be tested at once. It is possible to test only a subset of a memory, but the test coverage will then be somewhat lower.
The actual test is started by writing a one to CTRL.MBIST. A running MBIST operation can be canceled by writing
a one to CTRL.SWRST.
3.
Interpreting the Results
The tester should monitor the STATUSA register. When the operation is completed, STATUSA.DONE is set.
There are three different modes:
z
ADDR.AMOD=0: exit-on-error (default)
In this mode, the algorithm terminates either when a fault is detected or on successful completion. In both cases,
STATUSA.DONE is set. If an error was detected, STATUSA.FAIL will be set. User then can read the DATA and
ADDR registers to locate the fault. Refer to “Locating Errors” on page 53.
z
ADDR.AMOD=1: pause-on-error
In this mode, the MBIST algorithm is paused when an error is detected. In such a situation, only STATUSA.FAIL is
asserted. The state machine waits for user to clear STATUSA.FAIL by writing a one in STATUSA.FAIL to resume.
Prior to resuming, user can read the DATA and ADDR registers to locate the fault. Refer to “Locating Errors” on
page 53.
4.
Locating Errors
If the test stops with STATUSA.FAIL set, one or more bits failed the test. The test stops at the first detected error.
The position of the failing bit can be found by reading the following registers:
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z
ADDR: Address of the word containing the failing bit.
z
DATA: contains data to identify which bit failed, and during which phase of the test it failed. The DATA
register will in this case contains the following bit groups:
Table 11-4. DATA bits Description When MBIST Operation Returns An Error
Bit
31
30
29
28
27
26
25
24
Bit
23
22
21
20
19
18
17
16
Bit
15
14
13
12
11
10
9
8
phase
Bit
7
6
5
4
3
2
1
0
bit_index
z
bit_index: contains the bit number of the failing bit
z
phase: indicates which phase of the test failed and the cause of the error. See Table 11-5 on page 54.
Table 11-5. MBIST Operation Phases
Phase
Test Actions
0
Write all bits to zero. This phase cannot fail.
1
Read 0, write 1, increment address
2
Read 1, write 0
3
Read 0, write 1, decrement address
4
Read 1, write 0, decrement address
5
Read 0, write 1
6
Read 1, write 0, decrement address
7
Read all zeros. bit_index is not used
11.11.6 System Services Availability When Accessed Externally
External access: Access performed in the DSU address offset 0x200-0x1FFF range.
Internal access: Access performed in the DSU address offset 0x0-0x100 range.
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Table 11-6. Available Features When Operated From The External Address Range and Device is Protected
Availability From The External Address Range and Device is Protected
Features
Chip-Erase command and status
CRC32
Yes
Yes, only full array or full EEPROM
CoreSight Compliant Device identification
Yes
Debug communication channels
Yes
Testing of onboard memories (MBIST)
Yes
STATUSA.CRSTEXT clearing
No (STATUSA.PERR is set when attempting to do so)
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11.12 Register Summary
Table 11-7. Register Summary
Offset
Name
Bit
Pos.
0x0000
CTRL
7:0
CE
0x0001
STATUSA
7:0
PERR
FAIL
BERR
CRSTEXT
DONE
0x0002
STATUSB
7:0
HPE
DCCD1
DCCD0
DBGPRES
PROT
0x0003
Reserved
MBIST
0x0004
7:0
0x0005
15:8
ADDR[13:6]
23:16
ADDR[21:14]
31:24
ADDR[29:22]
0x0006
ADDR
0x0007
7:0
0x0009
15:8
LENGTH[13:6]
23:16
LENGTH[21:14]
31:24
LENGTH[29:22]
0x000A
0x000B
LENGTH[5:0]
0x000C
7:0
DATA[7:0]
0x000D
15:8
DATA[15:8]
0x000E
DATA
23:16
DATA[23:16]
0x000F
31:24
DATA[31:24]
0x0010
7:0
DATA[7:0]
0x0011
15:8
DATA[15:8]
23:16
DATA[23:16]
0x0013
31:24
DATA[31:24]
0x0014
7:0
DATA[7:0]
0x0012
0x0015
0x0016
DCC0
DCC1
0x0017
15:8
DATA[15:8]
23:16
DATA[23:16]
31:24
DATA[31:24]
0x0018
7:0
0x0019
15:8
0x001A
DID
0x001B
0x001C
...
0x00FF
23:16
31:24
REVISION[3:0]
SERIES[5:0]
FAMILY
PROCESSOR[3:0]
FAMILY[4:1]
External address range:
Replicates the 0x00:0xFF address range,
Gives access to the same resources but with security restrictions when the device is protected.
This address range is the only one accessible externally (using the ARM DAP) when the device is protected.
Reserved
0x1000
0x1001
DEVSEL[7:0]
DIE[3:0]
Reserved
0x0100
...
0x01FF
0x0200
...
0x0FFF
SWRST
ADDR[5:0]
0x0008
LENGTH
CRC
7:0
ENTRY0
15:8
FMT
EPRES
ADDOFF[3:0]
0x1002
23:16
ADDOFF[11:4]
0x1003
31:24
ADDOFF[19:12]
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Offset
Name
0x1004
0x1005
Bit
Pos.
7:0
ENTRY1
15:8
FMT
ADDOFF[3:0]
0x1006
23:16
ADDOFF[11:4]
0x1007
31:24
ADDOFF[19:12]
0x1008
7:0
END[7:0]
0x1009
0x100A
END
0x100B
0x100C
...
0x1FCB
0x1FCE
15:8
END[15:8]
23:16
END[23:16]
31:24
END[31:24]
Reserved
0x1FCC
0x1FCD
7:0
MEMTYPE
23:16
31:24
0x1FD0
7:0
0x1FD1
23:16
Reserved
7:0
0x1FE1
23:16
31:24
0x1FE4
7:0
0x1FE5
15:8
PID1
31:24
0x1FE8
7:0
0x1FE9
JEPU
JEPIDCH[2:0]
31:24
0x1FEC
7:0
15:8
PID3
31:24
0x1FF0
7:0
0x1FF1
REVAND[3:0]
CUSMOD[3:0]
23:16
0x1FEF
0x1FF3
REVISION[3:0]
23:16
0x1FED
0x1FF2
PARTNBH[3:0]
15:8
PID2
0x1FEB
0x1FEE
JEPIDCL[3:0]
23:16
0x1FE7
0x1FEA
PARTNBL[7:0]
15:8
PID0
0x1FE3
0x1FE6
JEPCC[3:0]
31:24
0x1FE0
0x1FE2
FKBC[3:0]
15:8
PID4
0x1FD3
0x1FD4
...
0x1FDF
SMEMP
15:8
0x1FCF
0x1FD2
EPRES
PREAMBLEB0[7:0]
15:8
CID0
23:16
31:24
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Offset
Name
Bit
Pos.
0x1FF4
7:0
0x1FF5
15:8
0x1FF6
CID1
31:24
0x1FF8
7:0
0x1FFA
23:16
31:24
0x1FFC
7:0
0x1FFD
15:8
0x1FFF
PREAMBLEB2[7:0]
15:8
CID2
0x1FFB
0x1FFE
PREAMBLE[3:0]
23:16
0x1FF7
0x1FF9
CCLASS[3:0]
CID3
PREAMBLEB3[7:0]
23:16
31:24
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11.13 Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write protection is denoted by
the Write-Protected property in each individual register description. Refer to “Register Access Protection” on page 46 for
details.
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11.13.1 Control
Name:
CTRL
Offset:
0x0000
Reset:
0x00
Property:
Write-Protected
Bit
7
6
5
4
3
2
CE
MBIST
CRC
1
0
SWRST
Access
R
R
R
W
W
W
R
W
Reset
0
0
0
0
0
0
0
0
z
Bits 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 4 – CE: Chip Erase
Writing a zero to this bit has no effect.
Writing a one to this bit starts the Chip-Erase operation.
z
Bit 3 – MBIST: Memory Built-In Self-Test
Writing a zero to this bit has no effect.
Writing a one to this bit starts the memory BIST algorithm.
z
Bit 2 – CRC: 32-bit Cyclic Redundancy Check
Writing a zero to this bit has no effect.
Writing a one to this bit starts the cyclic redundancy check algorithm.
z
Bit 1 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bit 0 – SWRST: Software Reset
Writing a zero to this bit has no effect.
Writing a one to this bit resets the module.
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11.13.2 Status A
Name:
STATUSA
Offset:
0x0001
Reset:
0x00
Property:
Write-Protected
Bit
7
6
5
4
3
2
1
0
PERR
FAIL
BERR
CRSTEXT
DONE
Access
R
R
R
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
z
Bits 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 4 – PERR: Protection Error
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Protection Error bit.
This bit is set when a command that is not allowed in protected state is issued.
z
Bit 3 – FAIL: Failure
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Failure bit.
This bit is set when a DSU operation failure is detected.
z
Bit 2 – BERR: Bus Error
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Bus Error bit.
This bit is set when a bus error is detected.
z
Bit 1 – CRSTEXT: CPU Reset Phase Extension
Writing a zero to this bit has no effect.
Writing a one to this bit clears the CPU Reset Phase Extension bit.
This bit is set when a debug adapter Cold-Plugging is detected, which extends the CPU reset phase.
z
Bit 0 – DONE: Done
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Done bit.
This bit is set when a DSU operation is completed.
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11.13.3 Status B
Name:
STATUSB
Offset:
0x0002
Reset:
0x1X
Property:
Write-Protected
Bit
7
6
5
4
3
2
1
0
HPE
DCCD1
DCCD0
DBGPRES
PROT
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
1
0
0
X
X
z
Bits 7:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 4 – HPE: Hot-Plugging Enable
Writing a zero to this bit has no effect.
Writing a one to this bit has no effect.
This bit is set when Hot-Plugging is enabled.
This bit is cleared when Hot-Plugging is disabled. This is the case when the SWCLK function is changed. Only a
power-reset or a external reset can set it again.
z
Bits 3:2 – DCCDx [x=1..0]: Debug Communication Channel x Dirty
Writing a zero to this bit has no effect.
Writing a one to this bit has no effect.
This bit is set when DCCx is written.
This bit is cleared when DCCx is read.
z
Bit 1 – DBGPRES: Debugger Present
Writing a zero to this bit has no effect.
Writing a one to this bit has no effect.
This bit is set when a debugger probe is detected.
This bit is never cleared.
z
Bit 0 – PROT: Protected
Writing a zero to this bit has no effect.
Writing a one to this bit has no effect.
This bit is set at powerup when the device is protected.
This bit is never cleared.
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11.13.4 Address
Name:
ADDR
Offset:
0x0004
Reset:
0x00000000
Property:
Write-Protected
Bit
31
30
29
28
27
26
25
24
ADDR[29:22]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
ADDR[21:14]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
ADDR[13:6]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ADDR[5:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R
R
0
0
0
0
0
0
0
0
z
Bits 31:2 – ADDR[29:0]: Address
Initial word start address needed for memory operations.
z
Bits 1:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
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11.13.5 Length
Name:
LENGTH
Offset:
0x0008
Reset:
0x00000000
Property:
Write-Protected
Bit
31
30
29
28
27
26
25
24
LENGTH[29:22]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
LENGTH[21:14]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
LENGTH[13:6]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
LENGTH[5:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R
R
0
0
0
0
0
0
0
0
z
Bits 31:2 – LENGTH[29:0]: Length
Length in words needed for memory operations.
z
Bits 1:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
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11.13.6 Data
Name:
DATA
Offset:
0x000C
Reset:
0x00000000
Property:
Write-Protected
Bit
31
30
29
28
27
26
25
24
DATA[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DATA[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
DATA[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
DATA[7:0]
Access
Reset
z
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:0 – DATA[31:0]: Data
Memory operation initial value or result value.
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
65
11.13.7 Debug Communication Channel n
Name:
DCCn
Offset:
0x0010+n*0x4 [n=0..1]
Reset:
0x00000000
Property:
-
Bit
31
30
29
28
27
26
25
24
DATA[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DATA[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
DATA[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
DATA[7:0]
Access
Reset
z
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:0 – DATA[31:0]: Data
Data register.
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
66
11.13.8 Device Identification
The information in this register is related to the ordering code. Refer to the “Ordering Information” on page 6 for details.
Name:
DID
Offset:
0x0018
Reset:
-
Property:
Write-Protected
Bit
31
30
29
28
27
26
PROCESSOR[3:0]
25
24
FAMILY[4:1]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
FAMILY
SERIES[5:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
DIE[3:0]
REVISION[3:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
DEVSEL[7:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
z
Bits 31:28 – PROCESSOR[3:0]: Processor
The value of this field defines the processor used on the device. For this device, the value of this field is 0x1, corresponding to the ARM Cortex-M0+ processor.
z
Bits 27:23 – FAMILY[4:0]: Product Family
The value of this field corresponds to the Product Family part of the ordering code. For this device, the value of this
field is 0x0, corresponding to the SAM D family of base line microcontrollers.
z
Bit 22 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bits 21:16 – SERIES[5:0]: Product Series
The value of this field corresponds to the Product Series part of the ordering code. For this device, the value of this
field is 0x01, corresponding to a product with the Cortex-M0+ processor with DMA and USB features.
z
Bits 15:12 – DIE[3:0]: Die Identification
Identifies the die in the family.
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
67
z
Bits 11:8 – REVISION[3:0]: Revision
Identifies the die revision number.
z
Bits 7:0 – DEVSEL[7:0]: Device Select
DEVSEL is used to identify a device within a product family and product series. The value corresponds to the
Flash memory density, pin count and device variant parts of the ordering code. Refer to “Ordering Information” on
page 6 for details.
Table 11-8. Device Selection
DEVSEL
Device
Flash
0x00 - 0x17
Pincount
Reserved
0x18
SAMR21E19A
256KB+512KB(1)
32KB
32
0x19
SAMR21G18A
256KB
32KB
48
0x1A
SAMR21G17A
128KB
32KB
48
0x1B
SAMR21G16A
64KB
16KB
48
0x1C
SAMR21E18A
256KB
32KB
32
0x1D
SAMR21E17A
128K
32KB
32
0x1E
SAMR21E16A
64KB
16KB
32
0x1F-0xFF
Note:
RAM
1.
Reserved
Serial Flash MX25V4006EWSK.
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
68
11.13.9 Coresight ROM Table Entry n
Name:
ENTRYn
Offset:
0x1000+n*0x4 [n=0..1]
Reset:
0xXXXXX00X
Property:
Write-Protected
Bit
31
30
29
28
27
26
25
24
ADDOFF[19:12]
Access
R
R
R
R
R
R
R
R
Reset
X
X
X
X
X
X
X
X
Bit
23
22
21
20
19
18
17
16
ADDOFF[11:4]
Access
R
R
R
R
R
R
R
R
Reset
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
ADDOFF[3:0]
Access
R
R
R
R
R
R
R
R
Reset
X
X
X
X
0
0
0
0
Bit
7
6
5
4
3
2
1
0
FMT
EPRES
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
1
X
z
Bits 31:12 – ADDOFF[19:0]: Address Offset
The base address of the component, relative to the base address of this ROM table.
z
Bits 11:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 1 – FMT: Format
Always read as one, indicates a 32-bit ROM table.
z
Bit 0 – EPRES: Entry Present
This bit indicates whether an entry is present at this location in the ROM table.
This bit is set at powerup if the device is not protected indicating that the entry is not present.
This bit is cleared at powerup if the device is not protected indicating that the entry is present.
Atmel | SMART SAM R21 [DATASHEET]
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69
11.13.10Coresight ROM Table End
Name:
END
Offset:
0x1008
Reset:
0x00000000
Property:
-
Bit
31
30
29
28
27
26
25
24
END[31:24]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
END[23:16]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
END[15:8]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
END[7:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
z
Bits 31:0 – END[31:0]: End Marker
Indicates the end of the CoreSight ROM table entries.
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
70
11.13.11Coresight ROM Table Memory Type
Name:
MEMTYPE
Offset:
0x1FCC
Reset:
0x0000000X
Property:
-
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
SMEMP
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
X
z
Bits 31:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 0 – SMEMP: System Memory Present
This bit indicates whether system memory is present on the bus that connects to the ROM table.
This bit is set at powerup if the device is not protected indicating that the system memory is accessible from a
debug adapter.
This bit is cleared at powerup if the device is protected indicating that the system memory is not accessible from a
debug adapter.
Atmel | SMART SAM R21 [DATASHEET]
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71
11.13.12Peripheral Identification 4
Name:
PID4
Offset:
0x1FD0
Reset:
0x00000000
Property:
-
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
FKBC[3:0]
JEPCC[3:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
z
Bits 31:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 7:4 – FKBC[3:0]: 4KB Count
These bits will always return zero when read, indicating that this debug component occupies one 4KB block.
z
Bits 3:0 – JEPCC[3:0]: JEP-106 Continuation Code
These bits will always return zero when read, indicating a Atmel device.
Atmel | SMART SAM R21 [DATASHEET]
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72
11.13.13Peripheral Identification 0
Name:
PID0
Offset:
0x1FE0
Reset:
0x000000D0
Property:
-
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PARTNBL[7:0]
Access
R
R
R
R
R
R
R
R
Reset
1
1
0
1
0
0
0
0
z
Bits 31:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 7:0 – PARTNBL[7:0]: Part Number Low
These bits will always return 0xD0 when read, indicating that this device implements a DSU module instance.
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
73
11.13.14Peripheral Identification 1
Name:
PID1
Offset:
0x1FE4
Reset:
0x000000FC
Property:
-
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
JEPIDCL[3:0]
PARTNBH[3:0]
Access
R
R
R
R
R
R
R
R
Reset
1
1
1
1
1
1
0
0
z
Bits 31:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 7:4 – JEPIDCL[3:0]: Low part of the JEP-106 Identity Code
These bits will always return 0xF when read, indicating a Atmel device (Atmel JEP-106 identity code is 0x1F).
z
Bits 3:0 – PARTNBH[3:0]: Part Number High
These bits will always return 0xC when read, indicating that this device implements a DSU module instance.
Atmel | SMART SAM R21 [DATASHEET]
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74
11.13.15Peripheral Identification 2
Name:
PID2
Offset:
0x1FE8
Reset:
0x00000009
Property:
-
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
REVISION[3:0]
JEPU
JEPIDCH[2:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
1
0
0
1
z
Bits 31:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 7:4 – REVISION[3:0]: Revision Number
Revision of the peripheral. Starts at 0x0 and increments by one at both major and minor revisions.
z
Bit 3 – JEPU: JEP-106 Identity Code is used
This bit will always return one when read, indicating that JEP-106 code is used.
z
Bits 2:0 – JEPIDCH[2:0]: JEP-106 Identity Code High
These bits will always return 0x1 when read, indicating an Atmel device (Atmel JEP-106 identity code is 0x1F).
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
75
11.13.16Peripheral Identification 3
Name:
PID3
Offset:
0x1FEC
Reset:
0x00000000
Property:
-
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
REVAND[3:0]
CUSMOD[3:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
z
Bits 31:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 7:4 – REVAND[3:0]: Revision Number
These bits will always return 0x0 when read.
z
Bits 3:0 – CUSMOD[3:0]: ARM CUSMOD
These bits will always return 0x0 when read.
Atmel | SMART SAM R21 [DATASHEET]
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76
11.13.17Component Identification 0
Name:
CID0
Offset:
0x1FF0
Reset:
0x0000000D
Property:
-
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PREAMBLEB0[7:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
1
1
0
1
z
Bits 31:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 7:0 – PREAMBLEB0[7:0]: Preamble Byte 0
These bits will always return 0xD when read.
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
77
11.13.18Component Identification 1
Name:
CID1
Offset:
0x1FF4
Reset:
0x00000010
Property:
-
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
CCLASS[3:0]
PREAMBLE[3:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
1
0
0
0
0
z
Bits 31:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 7:4 – CCLASS[3:0]: Component Class
These bits will always return 0x1 when read indicating that this ARM CoreSight component is ROM table (refer to
the ARM Debug Interface v5 Architecture Specification at http://www.arm.com).
z
Bits 3:0 – PREAMBLE[3:0]: Preamble
These bits will always return 0x0 when read.
Atmel | SMART SAM R21 [DATASHEET]
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78
11.13.19Component Identification 2
Name:
CID2
Offset:
0x1FF8
Reset:
0x00000005
Property:
-
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PREAMBLEB2[7:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
1
0
1
z
Bits 31:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 7:0 – PREAMBLEB2[7:0]: Preamble Byte 2
These bits will always return 0x05 when read.
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
79
11.13.20Component Identification 3
Name:
CID3
Offset:
0x1FFC
Reset:
0x000000B1
Property:
-
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PREAMBLEB3[7:0]
Access
R
R
R
R
R
R
R
R
Reset
1
0
1
1
0
0
0
1
z
Bits 31:8 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 7:0 – PREAMBLEB3[7:0]: Preamble Byte 3
These bits will always return 0xB1 when read.
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12.
Clock System
This chapter only aims to summarize the clock distribution and terminology in the SAM R21 device. It will not explain
every detail of its configuration. For in-depth documentation, see the referenced module chapters.
12.1
Clock Distribution
Figure 12-1. Clock distribution
PM
SYSCTRL
GCLK
XOSC
GCLK Generator 0
GCLK Multiplexer 0
(DFLL48M Reference)
GCLK Generator 1
GCLK Multiplexer 1
OSCULP32K
OSC32K
GCLK_MAIN
_
N
XOSC32K
Synchronous Clock
Controller
Peripheral 0
Generic
Clocks
OSC8M
GCLK Generator x
DFLL48M
FDPLL96M
GCLK Multiplexer y
Peripheral z
AHB/APB System Clocks
The clock system on the SAM R21 consists of:
z
Clock sources, controlled by SYSCTRL
z
z
z
A Clock source is the base clock signal used in the system. Example clock sources are the internal 8MHz
oscillator (OSC8M), External crystal oscillator (XOSC) and the Digital frequency locked loop (DFLL48M).
Generic Clock Controller (GCLK) which controls the clock distribution system, made up of:
z
Generic Clock generators: A programmable prescaler, that can use any of the system clock sources as its
source clock. The Generic Clock Generator 0, also called GCLK_MAIN, is the clock feeding the Power
Manager used to generate synchronous clocks.
z
Generic Clocks: Typically the clock input of a peripheral on the system. The generic clocks, through the
Generic Clock Multiplexer, can use any of the Generic Clock generators as its clock source. Multiple
instances of a peripheral will typically have a separate generic clock for each instance. The DFLL48M clock
input (when multiplying another clock source) is generic clock 0.
Power Manager (PM)
z
The PM controls synchronous clocks on the system. This includes the CPU, bus clocks (APB, AHB) as well
as the synchronous (to the CPU) user interfaces of the peripherals. It contains clock masks that can turn
on/off the user interface of a peripheral as well as prescalers for the CPU and bus clocks.
Figure 12-2 shows an example where SERCOM0 is clocked by the DFLL48M in open loop mode. The DFLL48M is
enabled, the Generic Clock Generator 1 uses the DFLL48M as its clock source, and the generic clock 20, also called
GCLK_SERCOM0_CORE, that is connected to SERCOM0 uses generator 1 as its source. The SERCOM0 interface,
clocked by CLK_SERCOM0_APB, has been unmasked in the APBC Mask register in the PM.
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Figure 12-2. Example of SERCOM clock
PM
Synchronous Clock
Controller
SYSCTRL
DFLL48M
12.2
CLK_SERCOM0_APB
GCLK
Generic Clock
Generator 1
Generic Clock
Multiplexer 20
GCLK_SERCOM0_CORE
SERCOM 0
Synchronous and Asynchronous Clocks
As the CPU and the peripherals can be clocked from different clock sources, possibly with widely different clock speeds,
some peripheral accesses by the CPU needs to be synchronized between the different clock domains. In these cases the
peripheral includes a SYNCBUSY status flag that can be used to check if a sync operation is in progress. As the nature
of the synchronization might vary between different peripherals, detailed description for each peripheral can be found in
the sub-chapter “synchronization” for each peripheral where this is necessary.
In the datasheet references to synchronous clocks are referring to the CPU and bus clocks, while asynchronous clocks
are clock generated by generic clocks.
12.3
Register Synchronization
There are two different register synchronization schemes implemented on this device: some modules use a common
synchronizer register synchronization scheme, while other modules use a distributed synchronizer register
synchronization scheme.
The modules using a common synchronizer register synchronization scheme are: GCLK, WDT, RTC, EIC, TC, ADC, AC,
DAC.
The modules using a distributed synchronizer register synchronization scheme are: SERCOM USART, SERCOM SPI,
SERCOM I2C, TCC, USB.
12.3.1 Common Synchronizer Register Synchronization
12.3.1.1 Overview
All peripherals are composed of one digital bus interface, which is connected to the APB or AHB bus and clocked using a
corresponding synchronous clock, and one core clock, which is clocked using a generic clock. Access between these
clock domains must be synchronized. As this mechanism is implemented in hardware the synchronization process takes
place even if the different clocks domains are clocked from the same source and on the same frequency. All registers in
the bus interface are accessible without synchronization. All core registers in the generic clock domain must be
synchronized when written. Some core registers must be synchronized when read. Registers that need synchronization
has this denoted in each individual register description. Two properties are used: write-synchronization and readsynchronization.
A common synchronizer is used for all registers in one peripheral, as shown in Figure 12-3. Therefore, only one register
per peripheral can be synchronized at a time.
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Figure 12-3. Synchronization
Asynchronous Domain
(generic clock)
Synchronous Domain
(CLK_APB)
Sync
Non Synced reg
Peripheral bus
INTFLAG
Write-Synced reg
SYNCBUSY
STATUS
READREQ
Synchronizer
Write-Synced reg
R/W-Synced reg
12.3.1.2 Write-Synchronization
The write-synchronization is triggered by a write to any generic clock core register. The Synchronization Busy bit in the
Status register (STATUS.SYNCBUSY) will be set when the write-synchronization starts and cleared when the writesynchronization is complete. Refer to “Synchronization Delay” on page 86 for details on the synchronization delay.
When the write-synchronization is ongoing (STATUS.SYNCBUSY is one), any of the following actions will cause the
peripheral bus to stall until the synchronization is complete:
z
Writing a generic clock core register
z
Reading a read-synchronized core register
z
Reading the register that is being written (and thus triggered the synchronization)
Core registers without read-synchronization will remain static once they have been written and synchronized, and can be
read while the synchronization is ongoing without causing the peripheral bus to stall. APB registers can also be read
while the synchronization is ongoing without causing the peripheral bus to stall.
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12.3.1.3 Read-Synchronization
Reading a read-synchronized core register will cause the peripheral bus to stall immediately until the readsynchronization is complete. STATUS.SYNCBUSY will not be set. Refer to “Synchronization Delay” on page 86 for
details on the synchronization delay. Note that reading a read-synchronized core register while STATUS.SYNCBUSY is
one will cause the peripheral bus to stall twice; first because of the ongoing synchronization, and then again because
reading a read-synchronized core register will cause the peripheral bus to stall immediately.
12.3.1.4 Completion of synchronization
The user can either poll STATUS.SYNCBUSY or use the Synchronisation Ready interrupt (if available) to check when
the synchronization is complete. It is also possible to perform the next read/write operation and wait, as this next
operation will be started once the previous write/read operation is synchronized and/or complete.
12.3.1.5 Read Request
The read request functionality is only available to peripherals that have the Read Request register (READREQ)
implemented. Refer to the register description of individual peripheral chapters for details.
To avoid forcing the peripheral bus to stall when reading read-synchronized core registers, the read request mechanism
can be used.
Basic Read Request
Writing a one to the Read Request bit in the Read Request register (READREQ.RREQ) will request readsynchronization of the register specified in the Address bits in READREQ (READREQ.ADDR) and set
STATUS.SYNCBUSY. When read-synchronization is complete, STATUS.SYNCBUSY is cleared. The readsynchronized value is then available for reading without delay until READREQ.RREQ is written to one again.
The address to use is the offset to the peripheral's base address of the register that should be synchronized.
Continuous Read Request
Writing a one to the Read Continuously bit in READREQ (READREQ.RCONT) will force continuous readsynchronization of the register specified in READREQ.ADDR. The latest value is always available for reading without
stalling the bus, as the synchronization mechanism is continuously synchronizing the given value.
SYNCBUSY is set for the first synchronization, but not for the subsequent synchronizations. If another synchronization is
attempted, i.e. by executing a write-operation of a write-synchronized register, the read request will be stopped, and will
have to be manually restarted.
Note that continuous read-synchronization is paused in sleep modes where the generic clock is not running. This means
that a new read request is required if the value is needed immediately after exiting sleep.
12.3.1.6 Enable Write-Synchronization
Writing to the Enable bit in the Control register (CTRL.ENABLE) will also trigger write-synchronization and set
STATUS.SYNCBUSY. CTRL.ENABLE will read its new value immediately after being written. The Synchronisation
Ready interrupt (if available) cannot be used for Enable write-synchronization.
When the enable write-synchronization is ongoing (STATUS.SYNCBUSY is one), attempt to do any of the following will
cause the peripheral bus to stall until the enable synchronization is complete:
z
Writing a core register
z
Writing an APB register
z
Reading a read-synchronized core register
APB registers can be read while the enable write-synchronization is ongoing without causing the peripheral bus to stall.
12.3.1.7 Software Reset Write-Synchronization
Writing a one to the Software Reset bit in CTRL (CTRL.SWRST) will also trigger write-synchronization and set
STATUS.SYNCBUSY. When writing a one to the CTRL.SWRST bit it will immediately read as one. CTRL.SWRST and
STATUS.SYNCBUSY will be cleared by hardware when the peripheral has been reset. Writing a zero to the
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CTRL.SWRST bit has no effect. The Synchronisation Ready interrupt (if available) cannot be used for Software Reset
write-synchronization.
When the software reset is in progress (STATUS.SYNCBUSY and CTRL.SWRST are one), attempt to do any of the
following will cause the peripheral bus to stall until the Software Reset synchronization and the reset is complete:
z
Writing a core register
z
Writing an APB register
z
Reading a read-synchronized register
APB registers can be read while the software reset is being write-synchronized without causing the peripheral bus to
stall.
12.3.1.8 Synchronization Delay
The synchronization will delay the write or read access duration by a delay D, given by the equation:
5 ⋅ P GCLK + 2 ⋅ P APB < D < 6 ⋅ P GCLK + 3 ⋅ P APB
Where P GCLK is the period of the generic clock and P APB is the period of the peripheral bus clock. A normal peripheral
bus register access duration is 2 ⋅ P APB .
12.3.2 Distributed Synchronizer Register Synchronization
12.3.2.1 Overview
All peripherals are composed of one digital bus interface, which is connected to the APB or AHB bus and clocked using a
corresponding synchronous clock, and one core clock, which is clocked using a generic clock. Access between these
clock domains must be synchronized. As this mechanism is implemented in hardware the synchronization process takes
place even if the different clocks domains are clocked from the same source and on the same frequency. All registers in
the bus interface are accessible without synchronization. All core registers in the generic clock domain must be
synchronized when written. Some core registers must be synchronized when read. Registers that need synchronization
has this denoted in each individual register description.
12.3.2.2 General Write synchronization
Inside the same module, each core register, denoted by the Write-Synchronized property, use its own synchronization
mechanism so that writing to different core registers can be done without waiting for the end of synchronization of
previous core register access.
To write again to the same core register in the same module, user must wait for the end of synchronization or the write
will be discarded.
For each core register, that can be written, a synchronization status bit is associated
Example:
REGA, REGB are 8-bit core registers. REGC is 16-bit core register.
Offset
Register
0x00
REGA
0x01
REGB
0x02
0x03
REGC
Since synchronization is per register, user can write REGA (8-bit access) then immediately write REGB (8-bit access)
without error.
User can write REGC (16-bit access) without affecting REGA or REGB. But if user writes REGC in two consecutives 8-bit
accesses, second write will be discarded and generate an error.
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When user makes a 32-bit access to offset 0x00, all registers are written but REGA, REGB, REGC can be updated at a
different time because of independent write synchronization
12.3.2.3 General read synchronization
Before any read of a core register, the user must check that the related bit in SYNCBUSY register is cleared.
Read access to core register is always immediate but the return value is reliable only if a synchonization of this core
register is not going.
12.3.2.4 Completion of synchronization
The user can either poll SYNCBUSY register or use the Synchronisation Ready interrupt (if available) to check when the
synchronization is complete.
12.3.2.5 Enable Write-Synchronization
Writing to the Enable bit in the Control register (CTRL.ENABLE) will also trigger write-synchronization and set
SYNCBUSY.ENABLE. CTRL.ENABLE will read its new value immediately after being written. The Synchronisation
Ready interrupt (if available) cannot be used for Enable write-synchronization.
12.3.2.6 Software Reset Write-Synchronization
Writing a one to the Software Reset bit in CTRL (CTRL.SWRST) will also trigger write-synchronization and set
SYNCBUSY.SWRST. When writing a one to the CTRL.SWRST bit it will immediately read as one. CTRL.SWRST and
SYNCBUSY.SWRST will be cleared by hardware when the peripheral has been reset. Writing a zero to the
CTRL.SWRST bit has no effect. The Synchronisation Ready interrupt (if available) cannot be used for Software Reset
write-synchronization.
12.3.2.7 Synchronization Delay
The synchronization will delay the write or read access duration by a delay D, given by the equation:
5 ⋅ P GCLK + 2 ⋅ P APB < D < 6 ⋅ P GCLK + 3 ⋅ P APB
Where P GCLK is the period of the generic clock and P APB is the period of the peripheral bus clock. A normal peripheral
bus register access duration is 2 ⋅ P APB .
12.4
Enabling a Peripheral
To enable a peripheral clocked by a generic clock, the following parts of the system needs to be configured:
z
A running clock source.
z
A clock from the Generic Clock Generator must be configured to use one of the running clock sources, and the
generator must be enabled.
z
The generic clock, through the Generic Clock Multiplexer, that connects to the peripheral needs to be configured
with a running clock from the Generic Clock Generator, and the generic clock must be enabled.
z
The user interface of the peripheral needs to be unmasked in the PM. If this is not done the peripheral registers will
read as all 0’s and any writes to the peripheral will be discarded.
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12.5
On-demand, Clock Requests
Figure 12-4. Clock request routing
Clock request
DFLL48M
Generic Clock
Generator
ENABLE
GENEN
RUNSTDBY
RUNSTDBY
Clock request
Generic Clock
Multiplexer
Clock request
Peripheral
CLKEN
ENABLE
RUNSTDBY
ONDEMAND
All the clock sources in the system can be run in an on-demand mode, where the clock source is in a stopped state when
no peripherals are requesting the clock source. Clock requests propagate from the peripheral, via the GCLK, to the clock
source. If one or more peripheral is using a clock source, the clock source will be started/kept running. As soon as the
clock source is no longer needed and no peripheral have an active request the clock source will be stopped until
requested again. For the clock request to reach the clock source, the peripheral, the generic clock and the clock from the
Generic Clock Generator in-between must be enabled. The time taken from a clock request being asserted to the clock
source being ready is dependent on the clock source startup time, clock source frequency as well as the divider used in
the Generic Clock Generator. The total startup time from a clock request to the clock is available for the peripheral is:
Delay_start_max = Clock source startup time + 2 * clock source periods + 2 * divided clock source periods
Delay_start_min = Clock source startup time + 1 * clock source period + 1 * divided clock source period
The delay for shutting down the clock source when there is no longer an active request is:
Delay_stop_min = 1 * divided clock source period + 1 * clock source period
Delay_stop_max = 2 * divided clock source periods + 2 * clock source periods
The On-Demand principle can be disabled individually for each clock source by clearing the ONDEMAND bit located in
each clock source controller. The clock is always running whatever is the clock request. This has the effect to remove the
clock source startup time at the cost of the power consumption.
In standby mode, the clock request mechanism is still working if the modules are configured to run in standby mode
(RUNSTDBY bit).
12.6
Power Consumption vs Speed
Due to the nature of the asynchronous clocking of the peripherals there are some considerations that needs to be taken
if either targeting a low-power or a fast-acting system. If clocking a peripheral with a very low clock, the active power
consumption of the peripheral will be lower. At the same time the synchronization to the synchronous (CPU) clock
domain is dependent on the peripheral clock speed, and will be longer with a slower peripheral clock; giving lower
response time and more time waiting for the synchronization to complete.
12.7
Clocks after Reset
On any reset the synchronous clocks start to their initial state:
z
OSC8M is enabled and divided by 8
z
GCLK_MAIN uses OSC8M as source
z
CPU and BUS clocks are undivided
On a power reset the GCLK starts to their initial state:
z
All generic clock generators disabled except:
z
the generator 0 (GCLK_MAIN) using OSC8M as source, with no division
z
the generator 2 using OSCULP32K as source, with no division
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z
All generic clocks disabled except:
z
the WDT generic clock using the generator 2 as source
On a user reset the GCLK starts to their initial state, except for:
z
generic clocks that are write-locked (WRTLOCK is written to one prior to reset or the WDT generic clock if the
WDT Always-On at power on bit set in the NVM User Row)
z
The generic clock dedicated to the RTC if the RTC generic clock is enabled
On any reset the clock sources are reset to their initial state except the 32KHz clock sources which are reset only by a
power reset.
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13.
GCLK – Generic Clock Controller
13.1
Overview
Several peripherals may require specific clock frequencies to operate correctly. The Generic Clock Controller consists of
number of generic clock generators and generic clock multiplexers that can provide a wide range of clock frequencies.
The generic clock generators can be set to use different external and internal clock sources. The selected clock can be
divided down in the generic clock generator. The outputs from the generic clock generators are used as clock sources for
the generic clock multiplexers, which select one of the sources to generate a generic clock (GCLK_PERIPHERAL), as
shown in Figure 13-2. The number of generic clocks, m, depends on how many peripherals the device has.
13.2
Features
z Provides generic clocks
z Wide frequency range
z Clock source for the generator can be changed on the fly
13.3
Block Diagram
The Generic Clock Controller can be seen in the clocking diagram, which is shown in Figure 13-1 .
Figure 13-1. Device Clocking Diagram
GENERIC CLOCK CONTROLLER
SYSCTRL
Generic Clock Generator
XOSC
OSCULP32K
OSC32K
Generic Clock Multiplexer
XOSC32K
GCLK_PERIPHERAL
OSC8M
DFLL48M
FDPLL96M
Clock
Divider &
Masker
Clock
Gate
PERIPHERALS
GCLK_IO
GCLK_MAIN
PM
The Generic Clock Controller block diagram is shown in Figure 13-2.
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Figure 13-2. Generic Clock Controller Block Diagram(1)
Generic Clock Generator 0
Clock Sources
GCLK_MAIN
GCLKGEN[0]
Clock
Divider &
Masker
GCLK_IO[0]
(I/O input)
Generic Clock Multiplexer 0
GCLK_PERIPHERAL[0]
Clock
Gate
Generic Clock Generator 1
Generic Clock Multiplexer 1
Clock
Divider &
Masker
GCLK_IO[1]
(I/O input)
GCLK_IO[0]
(I/O output)
GCLK_IO[1]
(I/O output)
GCLKGEN[1]
GCLK_PERIPHERAL[1]
Clock
Gate
Generic Clock Generator n
Clock
Divider &
Masker
GCLK_IO[n]
(I/O input)
GCLK_IO[n]
(I/O output)
GCLKGEN[n]
Generic Clock Multiplexer m
Clock
Gate
GCLK_PERIPHERAL[m]
GCLKGEN[n:0]
Note:
13.4
1.
If the GENCTRL.SRC=GCLKIN the GCLK_IO is set as an input.
Signal Description
Table 13-1. Signal Description
Signal Name
GCLK_IO[7:0]
Type
Description
Digital I/O
Source clock when input
Generic clock when output
Refer to “I/O Multiplexing and Considerations” on page 12 for details on the pin mapping for this peripheral. One signal
can be mapped on several pins.
13.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
13.5.1 I/O Lines
Using the Generic Clock Controller’s I/O lines requires the I/O pins to be configured. Refer to “PORT” on page 373 for
details.
13.5.2 Power Management
The Generic Clock Controller can operate in all sleep modes, if required. Refer to Table 14-4 for details on the different
sleep modes.
13.5.3 Clocks
The Generic Clock Controller bus clock (CLK_GCLK_APB) can be enabled and disabled in the Power Manager, and the
default state of CLK_GCLK_APB can be found in the Peripheral Clock Masking section in APBAMASK.
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13.5.4 DMA
Not applicable.
13.5.5 Interrupts
Not applicable.
13.5.6 Events
Not applicable.
13.5.7 Debug Operation
Not applicable.
13.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC).
Write-protection is denoted by the Write-Protection property in the register description.
When the CPU is halted in debug mode or the CPU reset is extended, all write-protection is automatically disabled.
Write-protection does not apply for accesses through an external debugger. Refer to “PAC – Peripheral Access
Controller” on page 36 for details.
13.5.9 Analog Connections
Not applicable.
13.6
Functional Description
13.6.1 Principle of Operation
The GCLK module is comprised of eight generic clock generators sourcing m generic clock multiplexers.
A clock source selected as input to one of the generic clock generators can be used directly, or it can be prescaled in the
generic clock generator before the generator output is used as input to one or more of the generic clock multiplexers.
A generic clock multiplexer provides a generic clock to a peripheral (GCLK_PERIPHERAL). A generic clock can act as
the clock to one or several of peripherals.
13.6.2 Basic Operation
13.6.2.1 Initialization
Before a generic clock is enabled, the clock source of its generic clock generator should be enabled. The generic clock
must be configured as outlined by the following steps:
1.
The generic clock generator division factor must be set by performing a single 32-bit write to the Generic Clock
Generator Division register (GENDIV):
z
The generic clock generator that will be selected as the source of the generic clock must be written to the ID
bit group (GENDIV.ID).
z
The division factor must be written to the DIV bit group (GENDIV.DIV)
Refer to GENDIV register for details.
2.
The generic clock generator must be enabled by performing a single 32-bit write to the Generic Clock Generator
Control register (GENCTRL):
z
The generic clock generator that will be selected as the source of the generic clock must be written to the ID
bit group (GENCTRL.ID)
z
The generic clock generator must be enabled by writing a one to the GENEN bit (GENCTRL.GENEN)
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Refer to GENCTRL register for details.
3.
The generic clock must be configured by performing a single 16-bit write to the Generic Clock Control register
(CLKCTRL):
z
The generic clock that will be configured must be written to the ID bit group (CLKCTRL.ID)
z
The generic clock generator used as the source of the generic clock must be written to the GEN bit group
(CLKCTRL.GEN)
Refer to CLKCTRL register for details.
13.6.2.2 Enabling, Disabling and Resetting
The GCLK module has no enable/disable bit to enable or disable the whole module.
The GCLK is reset by writing a one to the Software Reset bit in the Control register (CTRL.SWRST). All registers in the
GCLK will be reset to their initial state except for generic clocks and associated generators that have their Write Lock bit
written to one. Refer to “Configuration Lock” on page 95 for details.
13.6.2.3 Generic Clock Generator
Each generic clock generator (GCLKGEN) can be set to run from one of eight different clock sources except
GCLKGEN[1] which can be set to run from one of seven sources. GCLKGEN[1] can act as source to the other generic
clock generators but can not act as source to itself.
Each generic clock generator GCLKGEN[x] can be connected to one specific GCLK_IO[x] pin. The GCLK_IO[x] can be
set to act as source to GCLKGEN[x] or GCLK_IO[x] can be set up to output the clock generated by GCLKGEN[x].
The selected source (GCLKGENSRC see Figure 13-3) can optionally be divided. Each generic clock generator can be
independently enabled and disabled.
Each GCLKGEN clock can then be used as a clock source for the generic clock multiplexers. Each generic clock is
allocated to one or several peripherals.
GCLKGEN[0], is used as GCLK_MAIN for the synchronous clock controller inside the Power Manager.
Refer to “PM – Power Manager” on page 112 for details on the synchronous clock generation.
Figure 13-3. Generic Clock Generator
GCLKGENSRC
Clock Sources
0
Clock
Gate
DIVIDER
GCLK_IO[x]
GCLKGEN[x]
1
GENCTRL.GENEN
GENCTRL.DIVSEL
GENCTRL.SRC
GENDIV.DIV
13.6.2.4 Enabling a Generic Clock Generator
A generic clock generator is enabled by writing a one to the Generic Clock Generator Enable bit in the Generic Clock
Generator Control register (GENCTRL.GENEN).
13.6.2.5 Disabling a Generic Clock Generator
A generic clock generator is disabled by writing a zero to GENCTRL.GENEN. When GENCTRL.GENEN is read as zero,
the GCLKGEN clock is disabled and clock gated.
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13.6.2.6 Selecting a Clock Source for the Generic Clock Generator
Each generic clock generator can individually select a clock source by writing to the Source Select bit group in
GENCTRL (GENCTRL.SRC). Changing from one clock source, A, to another clock source, B, can be done on the fly. If
clock source B is not ready, the generic clock generator will continue running with clock source A. As soon as clock
source B is ready, however, the generic clock generator will switch to it. During the switching, the generic clock generator
holds clock requests to clock sources A and B and then releases the clock source A request when the switch is done.
The available clock sources are device dependent (usually the crystal oscillators, RC oscillators, PLL and DFLL clocks).
GCLKGEN[1] can be used as a common source for all the generic clock generators except generic clock generator 1.
13.6.2.7 Changing Clock Frequency
The selected generic clock generator source, GENCLKSRC can optionally be divided by writing a division factor
in the Division Factor bit group in the Generic Clock Generator Division register (GENDIV.DIV). Depending on the value
of the Divide Selection bit in GENCTRL (GENCTRL.DIVSEL), it can be interpreted in two ways by the integer divider.
Note that the number of DIV bits for each generic clock generator is device dependent.
Refer to Table 13-11 for details.
13.6.2.8 Duty Cycle
When dividing a clock with an odd division factor, the duty-cycle will not be 50/50. Writing a one to the Improve Duty
Cycle bit in GENCTRL (GENCTRL.IDC) will result in a 50/50 duty cycle.
13.6.2.9 Generic Clock Output on I/O Pins
Each Generic Clock Generator's output can be directed to a GCLK_IO pin. If the Output Enable bit in GENCTRL
(GENCTRL.OE) is one and the generic clock generator is enabled (GENCTRL.GENEN is one), the generic clock
generator requests its clock source and the GCLKGEN clock is output to a GCLK_IO pin. If GENCTRL.OE is zero,
GCLK_IO is set according to the Output Off Value bit. If the Output Off Value bit in GENCTRL (GENCTRL.OOV) is zero,
the output clock will be low when generic clock generator is turned off. If GENCTRL.OOV is one, the output clock will be
high when generic clock generator is turned off.
In standby mode, if the clock is output (GENCTRL.OE is one), the clock on the GCLK_IO pin is frozen to the OOV value
if the Run In Standby bit in GENCTRL (GENCTRL.RUNSTDBY) is zero. If GENCTRL.RUNSTDBY is one, the GCLKGEN
clock is kept running and output to GCLK_IO.
13.6.3 Generic Clock
Figure 13-4. Generic Clock Multiplexer
GCLKGEN[0]
GCLKGEN[1]
GCLKGEN[2]
GCLKGEN[n]
Clock
Gate
GCLK_PERIPHERAL
CLKCTRL.CLKEN
CLKCTRL.GEN
13.6.3.1 Enabling a Generic Clock
Before a generic clock is enabled, one of the generic clock generators must be selected as the source for the generic
clock by writing to CLKCTRL.GEN. The clock source selection is individually set for each generic clock.
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When a generic clock generator has been selected, the generic clock is enabled by writing a one to the Clock Enable bit
in CLKCTRL (CLKCTRL.CLKEN). The CLKCTRL.CLKEN bit must be synchronized to the generic clock domain.
CLKCTRL.CLKEN will continue to read as its previous state until the synchronization is complete.
13.6.3.2 Disabling a Generic Clock
A generic clock is disabled by writing a zero to CLKCTRL.CLKEN. The SYNCBUSY bit will be cleared when this writesynchronization is complete. CLKCTRL.CLKEN will continue to read as its previous state until the synchronization is
complete. When the generic clock is disabled, the generic clock is clock gated.
13.6.3.3 Selecting a Clock Source for the Generic Clock
When changing a generic clock source by writing to CLKCTRL.GEN, the generic clock must be disabled before being reenabled with the new clock source setting. This prevents glitches during the transition:
1.
Write a zero to CLKCTRL.CLKEN
2.
Wait until CLKCTRL.CLKEN reads as zero
3.
Change the source of the generic clock by writing CLKCTRL.GEN
4.
Re-enable the generic clock by writing a one to CLKCTRL.CLKEN
13.6.3.4 Configuration Lock
The generic clock configuration is locked for further write accesses by writing the Write Lock bit (WRTLOCK) in the
CLKCTRL register. All writes to the CLKCTRL register will be ignored. It can only be unlocked by a power reset.
The generic clock generator sources of a locked generic clock are also locked. The corresponding GENCTRL and
GENDIV are locked, and can be unlocked only by a power reset.
There is one exception concerning the GCLKGEN[0]. As it is used as GCLK_MAIN, it can not be locked. It is reset by any
reset to startup with a known configuration.
The SWRST can not unlock the registers.
13.6.4 Additional Features
13.6.4.1 Indirect Access
The Generic Clock Generator Control and Division registers (GENCTRL and GENDIV) and the Generic Clock Control
register (CLKCTRL) are indirectly addressed as shown in Figure 13-5.
Figure 13-5. GCLK Indirect Access
User Interface
Generic Clock Generator [i]
GENCTRL
GENDIV
CLKCTRL
GENCTRL.ID=i
GENCTRL
GENDIV.ID=i
GENDIV
CLKCTRL.ID=j
Generic Clock[j]
CLKCTRL
Writing these registers is done by setting the corresponding ID bit group.
To read a register, the user must write the ID of the channel, i, in the corresponding register. The value of the register for
the corresponding ID is available in the user interface by a read access.
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For example, the sequence to read the GENCTRL register of generic clock generator i is:
1.
Do an 8-bit write of the i value to GENCTRL.ID
2.
Read GENCTRL
13.6.4.2 Generic Clock Enable after Reset
The Generic Clock Controller must be able to provide a generic clock to some specific peripherals after a reset. That
means that the configuration of the generic clock generators and generic clocks after reset is device-dependent.
Refer to Table 13-9 and Table 13-10 for details on GENCTRL reset.
Refer to Table 13-13 and Table 13-14 for details on GENDIV reset.
Refer to Table 13-5 and Table 13-6 for details on CLKCTRL reset.
13.6.5 Sleep Mode Operation
13.6.5.1 SleepWalking
The GCLK module supports the SleepWalking feature. During a sleep mode where the generic clocks are stopped, a
peripheral that needs its generic clock to execute a process must request it from the Generic Clock Controller.
The Generic Clock Controller will receive this request and then determine which generic clock generator is involved and
which clock source needs to be awakened. It then wakes up the clock source, enables the generic clock generator and
generic clock stages successively and delivers the generic clock to the peripheral.
13.6.5.2 Run in Standby Mode
In standby mode, the GCLK can continuously output the generic clock generator output to GCLK_IO.
Refer to “Generic Clock Output on I/O Pins” on page 94 for details.
13.6.6 Synchronization
Due to the asynchronicity between CLK_GCLK_APB and GCLKGENSRC some registers must be synchronized when
accessed. A register can require:
z
Synchronization when written
z
Synchronization when read
z
Synchronization when written and read
z
No synchronization
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
The following registers need synchronization when written:
z
Generic Clock Generator Control register (GENCTRL)
z
Generic Clock Generator Division register (GENDIV)
z
Control register (CTRL)
Write-synchronization is denoted by the Write-Synchronization property in the register description.
Refer to “Register Synchronization” on page 83 for further details.
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13.7
Register Summary
Table 13-2. Register Summary
Offset
Name
Bit
Pos.
0x0
CTRL
7:0
0x1
STATUS
7:0
0x2
0x3
CLKCTRL
0x4
0x5
0x6
SWRST
SYNCBUSY
7:0
15:8
ID[5:0]
WRTLOCK
GEN[3:0]
CLKEN
ID[3:0]
7:0
GENCTRL
0x7
SRC[4:0]
15:8
23:16
RUNSTDBY
DIVSEL
OE
0x8
7:0
0x9
15:8
DIV[7:0]
23:16
DIV[15:8]
0xA
0xB
OOV
IDC
GENEN
31:24
GENDIV
ID[3:0]
31:24
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13.8
Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by
the Write-protected property in each individual register description. Refer to “Register Access Protection” on page 92 for
details.
Some registers require synchronization when read and/or written. Synchronization is denoted by the Write-Synchronized
or the Read-Synchronized property in each individual register description. Refer to “Synchronization” on page 96 for
details.
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13.8.1 Control
Name:
CTRL
Offset:
0x0
Reset:
0x00
Property:
Write-Protected, Write-Synchronized
Bit
7
6
5
4
3
2
1
0
SWRST
Access
R
R
R
R
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0
z
Bits 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 0 – SWRST: Software Reset
0: There is no reset operation ongoing.
1: There is a reset operation ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the GCLK to their initial state after a power reset, except for generic
clocks and associated generators that have their WRTLOCK bit in CLKCTRL read as one.
Refer to Table 13-9 for details on GENCTRL reset.
Refer to Table 13-13 for details on GENDIV reset.
Refer to Table 13-5 for details on CLKCTRL reset.
Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete. CTRL.SWRST and
STATUS.SYNCBUSY will both be cleared when the reset is complete.
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13.8.2 Status
Name:
STATUS
Offset:
0x1
Reset:
0x00
Property:
-
Bit
7
6
5
4
3
2
1
0
SYNCBUSY
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
z
Bit 7 – SYNCBUSY: Synchronization Busy Status
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
z
Bits 6:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
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13.8.3 Generic Clock Control
This register allows the user to configure one of the generic clocks, as specified in the CLKCTRL.ID bit group. To write to
the CLKCTRL register, do a 16-bit write with all configurations and the ID.
To read the CLKCTRL register, first do an 8-bit write to the CLKCTRL.ID bit group with the ID of the generic clock whose
configuration is to be read, and then read the CLKCTRL register.
Name:
CLKCTRL
Offset:
0x2
Reset:
0x0000
Property:
Write-Protected
Bit
15
14
WRTLOCK
CLKEN
R/W
R/W
R
R
R/W
Reset
0
0
0
0
Bit
7
6
5
4
Access
13
12
11
10
9
8
R/W
R/W
R/W
0
0
0
0
3
2
1
0
GEN[3:0]
ID[5:0]
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
z
Bit 15 – WRTLOCK: Write Lock
When this bit is written, it will lock from further writes the generic clock pointed to by CLKCTRL.ID, the generic
clock generator pointed to in CLKCTRL.GEN and the division factor used in the generic clock generator. It can
only be unlocked by a power reset.
One exception to this is generic clock generator 0, which cannot be locked.
0: The generic clock and the associated generic clock generator and division factor are not locked.
1: The generic clock and the associated generic clock generator and division factor are locked.
z
Bit 14 – CLKEN: Clock Enable
This bit is used to enable and disable a generic clock.
0: The generic clock is disabled.
1: The generic clock is enabled.
z
Bits 13:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 11:8 – GEN[3:0]: Generic Clock Generator
Table 13-3. Generic Clock Generator
GEN[3:0]
Name
Description
0x0
GCLKGEN0
Generic clock generator 0
0x1
GCLKGEN1
Generic clock generator 1
0x2
GCLKGEN2
Generic clock generator 2
0x3
GCLKGEN3
Generic clock generator 3
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Table 13-3. Generic Clock Generator (Continued)
GEN[3:0]
Name
Description
0x4
GCLKGEN4
Generic clock generator 4
0x5
GCLKGEN5
Generic clock generator 5
0x6
GCLKGEN6
Generic clock generator 6
0x7
GCLKGEN7
Generic clock generator 7
0x8
GCLKGEN8
Generic clock generator 8
0x9-0xF
Reserved
z
Bits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 5:0 – ID[5:0]: Generic Clock Selection ID
These bits select the generic clock that will be configured. The value of the ID bit group versus module instance is
shown in Table 13-4.
Table 13-4. Generic Clock Selection ID
Value
Name
Description
0x00
GCLK_DFLL48M_REF
DFLL48M Reference
0x01
GCLK_DPLL
FDPLL96M input clock source for reference
0x02
GCLK_DPLL_32K
FDPLL96M 32kHz clock for FDPLL96M internal lock timer
0x03
GCLK_WDT
WDT
0x04
GCLK_RTC
RTC
0x05
GCLK_EIC
EIC
0x06
GCLK_USB
USB
0x07
GCLK_EVSYS_CHANNEL_0
EVSYS_CHANNEL_0
0x08
GCLK_EVSYS_CHANNEL_1
EVSYS_CHANNEL_1
0x09
GCLK_EVSYS_CHANNEL_2
EVSYS_CHANNEL_2
0x0A
GCLK_EVSYS_CHANNEL_3
EVSYS_CHANNEL_3
0x0B
GCLK_EVSYS_CHANNEL_4
EVSYS_CHANNEL_4
0x0C
GCLK_EVSYS_CHANNEL_5
EVSYS_CHANNEL_5
0x0D
GCLK_EVSYS_CHANNEL_6
EVSYS_CHANNEL_6
0x0E
GCLK_EVSYS_CHANNEL_7
EVSYS_CHANNEL_7
0x0F
GCLK_EVSYS_CHANNEL_8
EVSYS_CHANNEL_8
0x10
GCLK_EVSYS_CHANNEL_9
EVSYS_CHANNEL_9
0x11
GCLK_EVSYS_CHANNEL_10
EVSYS_CHANNEL_10
0x12
GCLK_EVSYS_CHANNEL_11
EVSYS_CHANNEL_11
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Table 13-4. Generic Clock Selection ID (Continued)
Value
Name
Description
0x13
GCLK_SERCOMx_SLOW
SERCOMx_SLOW
0x14
GCLK_SERCOM0_CORE
SERCOM0_CORE
0x15
GCLK_SERCOM1_CORE
SERCOM1_CORE
0x16
GCLK_SERCOM2_CORE
SERCOM2_CORE
0x17
GCLK_SERCOM3_CORE
SERCOM3_CORE
0x18
GCLK_SERCOM4_CORE
SERCOM4_CORE
0x19
GCLK_SERCOM5_CORE
SERCOM5_CORE
0x1A
GCLK_TCC0, GCLK_TCC1
TCC0,TCC1
0x1B
GCLK_TCC2, GCLK_TC3
TCC2,TC3
0x1C
GCLK_TC4, GCLK_TC5
TC4,TC5
0x1D
Reserved
0x1E
GCLK_ADC
ADC
0x1F
GCLK_AC_DIG
AC_DIG
0x20
GCLK_AC_ANA
AC_ANA
0x21
Reserved
0x22
GCLK_PTC
PTCReserved
0x23
Reserved
0x24
Reserved
0x25-0x3F
Reserved
A power reset will reset the CLKCTRL register for all IDs, including the RTC. If the WRTLOCK bit of the corresponding ID is zero and the ID is not the RTC, a user reset will reset the CLKCTRL register for this ID.
After a power reset, the reset value of the CLKCTRL register versus module instance is as shown in Table 13-5.
Table 13-5. CLKCTRL Reset Value after a Power Reset
Module Instance
Reset Value after Power Reset
CLKCTRL.GEN
CLKCTRL.CLKEN
CLKCTRL.WRTLOCK
0x00
0x00
0x00
WDT
0x02
0x01 if WDT Enable bit in NVM
User Row written to one
0x00 if WDT Enable bit in NVM
User Row written to zero
0x01 if WDT Always-On bit in
NVM User Row written to one
0x00 if WDT Always-On bit in
NVM User Row written to zero
Others
0x00
0x00
0x00
RTC
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After a user reset, the reset value of the CLKCTRL register versus module instance is as shown in Table 13-6.
Table 13-6. CLKCTRL Reset Value after a User Reset
Module Instance
Reset Value after a User Reset
CLKCTRL.GEN
CLCTRL.CLKEN
CLKCTRL.WRTLOCK
0x00 if WRTLOCK=0 and
CLKEN=0
No change if WRTLOCK=1
or CLKEN=1
0x00 if WRTLOCK=0 and CLKEN=0
No change if WRTLOCK=1 or CLKEN=1
No change
WDT
0x02 if WRTLOCK=0
No change if WRTLOCK=1
If WRTLOCK=0
0x01 if WDT Enable bit in NVM User
Row written to one
0x00 if WDT Enable bit in NVM User
Row written to zero
If WRTLOCK=1 no change
No change
Others
0x00 if WRTLOCK=0
No change if WRTLOCK=1
0x00 if WRTLOCK=0
No change if WRTLOCK=1
No change
RTC
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13.8.4 Generic Clock Generator Control
This register allows the user to configure one of the generic clock generators, as specified in the GENCTRL.ID bit group.
To write to the GENCTRL register, do a 32-bit write with all configurations and the ID.
To read the GENCTRL register, first do an 8-bit write to the GENCTRL.ID bit group with the ID of the generic clock
generator whose configuration is to be read, and then read the GENCTRL register.
Name:
GENCTRL
Offset:
0x4
Reset:
0x00000000
Property:
Write-Protected, Write-Synchronized
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
RUNSTDBY
DIVSEL
OE
OOV
IDC
GENEN
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
SRC[4:0]
Access
R
R
R
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ID[3:0]
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
z
Bits 31:22 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 21 – RUNSTDBY: Run in Standby
This bit is used to keep the generic clock generator running when it is configured to be output to its dedicated
GCLK_IO pin. If GENCTRL.OE is zero, this bit has no effect and the generic clock generator will only be running if
a peripheral requires the clock.
0: The generic clock generator is stopped in standby and the GCLK_IO pin state (one or zero) will be dependent
on the setting in GENCTRL.OOV.
1: The generic clock generator is kept running and output to its dedicated GCLK_IO pin during standby mode.
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z
Bit 20 – DIVSEL: Divide Selection
This bit is used to decide how the clock source used by the generic clock generator will be divided. If the clock
source should not be divided, the DIVSEL bit must be zero and the GENDIV.DIV value for the corresponding
generic clock generator must be zero or one.
0: The generic clock generator equals the clock source divided by GENDIV.DIV.
1: The generic clock generator equals the clock source divided by 2^(GENDIV.DIV+1).
z
Bit 19 – OE: Output Enable
This bit is used to enable output of the generated clock to GCLK_IO when GCLK_IO is not selected as a source in
the GENCLK.SRC bit group.
0: The generic clock generator is not output.
1: The generic clock generator is output to the corresponding GCLK_IO, unless the corresponding GCLK_IO is
selected as a source in the GENCLK.SRC bit group.
z
Bit 18 – OOV: Output Off Value
This bit is used to control the value of GCLK_IO when GCLK_IO is not selected as a source in the GENCLK.SRC
bit group.
0: The GCLK_IO will be zero when the generic clock generator is turned off or when the OE bit is zero.
1: The GCLK_IO will be one when the generic clock generator is turned off or when the OE bit is zero.
z
Bit 17 – IDC: Improve Duty Cycle
This bit is used to improve the duty cycle of the generic clock generator when odd division factors are used.
0: The generic clock generator duty cycle is not 50/50 for odd division factors.
1: The generic clock generator duty cycle is 50/50.
z
Bit 16 – GENEN: Generic Clock Generator Enable
This bit is used to enable and disable the generic clock generator.
0: The generic clock generator is disabled.
1: The generic clock generator is enabled.
z
Bits 15:13 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 12:8 – SRC[4:0]: Source Select
These bits define the clock source to be used as the source for the generic clock generator, as shown in Table 137.
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Table 13-7. Source Select
Value
Name
Description
0x00
XOSC
XOSC oscillator output
0x01
GCLKIN
Generator input pad
0x02
GCLKGEN1
Generic clock generator 1 output
0x03
OSCULP32K
OSCULP32K oscillator output
0x04
OSC32K
OSC32K oscillator output
0x05
XOSC32K
XOSC32K oscillator output
0x06
OSC8M
OSC8M oscillator output
0x07
DFLL48M
DFLL48M output
0x08
FDPLL96M
FDPLL96M output
0x09-0x1F
Reserved
Reserved for future use
z
Bits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 3:0 – ID[3:0]: Generic Clock Generator Selection
These bits select the generic clock generator that will be configured or read. The value of the ID bit group versus
which generic clock generator is configured is shown in Table 13-8.
Table 13-8. Generic Clock Generator Selection
Value
Name
Description
0x0
GCLKGEN0
Generic clock generator 0
0x1
GCLKGEN1
Generic clock generator 1
0x2
GCLKGEN2
Generic clock generator 2
0x3
GCLKGEN3
Generic clock generator 3
0x4
GCLKGEN4
Generic clock generator 4
0x5
GCLKGEN5
Generic clock generator 5
0x6
GCLKGEN6
Generic clock generator 6
0x7
GCLKGEN7
Generic clock generator 7
0x8
GCLKGEN8
Generic clock generator 8
0x9-0xF
Reserved
A power reset will reset the GENCTRL register for all IDs, including the generic clock generator used by the RTC. If a
generic clock generator ID other than generic clock generator 0 is not a source of a “locked” generic clock or a source of
the RTC generic clock, a user reset will reset the GENCTRL for this ID.
After a power reset, the reset value of the GENCTRL register is as shown in Table 13-9.
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Table 13-9. GENCTRL Reset Value after a Power Reset
GCLK Generator ID
Reset Value after a Power Reset
0x00
0x00010600
0x01
0x00000001
0x02
0x00010302
0x03
0x00000003
0x04
0x00000004
0x05
0x00000005
0x06
0x00000006
0x07
0x00000007
0x08
0x00000008
After a user reset, the reset value of the GENCTRL register is as shown in Table 13-10.
Table 13-10. GENCTRL Reset Value after a User Reset
GCLK Generator ID
Reset Value after a User Reset
0x00
0x00010600
0x01
0x00000001 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x02
0x00010302 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x03
0x00000003 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x04
0x00000004 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x05
0x00000005 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x06
0x00000006 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x07
0x00000007 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x08
0x00000008 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
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13.8.5 Generic Clock Generator Division
This register allows the user to configure one of the generic clock generators, as specified in the GENDIV.ID bit group.
To write to the GENDIV register, do a 32-bit write with all configurations and the ID.
To read the GENDIV register, first do an 8-bit write to the GENDIV.ID bit group with the ID of the generic clock generator
whose configuration is to be read, and then read the GENDIV register.
Name:
GENDIV
Offset:
0x8
Reset:
0x00000000
Property:
-
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DIV[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
DIV[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ID[3:0]
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
z
Bits 31:24 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 23:8 – DIV[15:0]: Division Factor
These bits apply a division on each selected generic clock generator. The number of DIV bits each generator has
can be seen in Table 13-11. Writes to bits above the specified number will be ignored.
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Table 13-11. Division Factor
Generator
Division Factor Bits
Generic clock generator 0
8 division factor bits - DIV[7:0]
Generic clock generator 1
16 division factor bits - DIV[15:0]
Generic clock generators 2
5 division factor bits - DIV[4:0]
Generic clock generators 3 - 8
8 division factor bits - DIV[7:0]
z
Bits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 3:0 – ID[3:0]: Generic Clock Generator Selection
These bits select the generic clock generator on which the division factor will be applied, as shown in Table 13-12.
Table 13-12. Generic Clock Generator Selection
Values
Description
0x0
Generic clock generator 0
0x1
Generic clock generator 1
0x2
Generic clock generator 2
0x3
Generic clock generator 3
0x4
Generic clock generator 4
0x5
Generic clock generator 5
0x6
Generic clock generator 6
0x7
Generic clock generator 7
0x8
Generic clock generator 8
0x9-0xF
Reserved
A power reset will reset the GENDIV register for all IDs, including the generic clock generator used by the RTC. If a
generic clock generator ID other than generic clock generator 0 is not a source of a ‚“locked” generic clock or a source of
the RTC generic clock, a user reset will reset the GENDIV for this ID.
After a power reset, the reset value of the GENDIV register is as shown in Table 13-13.
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Table 13-13. GENDIV Reset value after a Power Reset
GCLK Generator ID
Reset Value after a Power Reset
0x00
0x00000000
0x01
0x00000001
0x02
0x00000002
0x03
0x00000003
0x04
0x00000004
0x05
0x00000005
0x06
0x00000006
0x07
0x00000007
0x08
0x00000008
After a user reset, the reset value of the GENDIV register is as shown in Table 13-14.
Table 13-14. GENDIV Reset Value after a User Reset
GCLK Generator ID
Reset Value after a User Reset
0x00
0x00000000
0x01
0x00000001 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x02
0x00000002 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x03
0x00000003 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x04
0x00000004 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x05
0x00000005 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x06
0x00000006 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x07
0x00000007 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
0x08
0x00000008 if the generator is not used by the RTC and not a source of a 'locked' generic clock
No change if the generator is used by the RTC or used by a GCLK with a WRTLOCK as one
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14.
14.1
PM – Power Manager
Overview
The Power Manager (PM) controls the reset, clock generation and sleep modes of the microcontroller.
Utilizing a main clock chosen from a large number of clock sources from the GCLK, the clock controller provides
synchronous system clocks to the CPU and the modules connected to the AHB and the APBx bus. The synchronous
system clocks are divided into a number of clock domains; one for the CPU and AHB and one for each APBx. Any
synchronous system clock can be changed at run-time during normal operation. The clock domains can run at different
speeds, enabling the user to save power by running peripherals at a relatively low clock frequency, while maintaining
high CPU performance. In addition, the clock can be masked for individual modules, enabling the user to minimize power
consumption.
Before entering the STANDBY sleep mode the user must make sure that a significant amount of clocks and peripherals
are disabled, so that the voltage regulator is not overloaded. This is because during STANDBY sleep mode the internal
voltage regulator will be in low power mode.
Various sleep modes and clock gating are provided in order to fit power consumption requirements. This enables the
microcontroller to stop unused modules to save power. In ACTIVE mode, the CPU is executing application code. When
the device enters a sleep mode, program execution is stopped and some modules and clock domains are automatically
switched off by the PM according to the sleep mode. The application code decides which sleep mode to enter and when.
Interrupts from enabled peripherals and all enabled reset sources can restore the microcontroller from a sleep mode to
ACTIVE mode.
The PM also contains a reset controller, which collects all possible reset sources. It issues a microcontroller reset and
sets the device to its initial state, and allows the reset source to be identified by software.
14.2
Features
z Reset control
Reset the microcontroller and set it to an initial state according to the reset source
Multiple reset sources
z Power reset sources: POR, BOD12, BOD33
z User reset sources: External reset (RESET), Watchdog Timer reset, software reset
z Reset status register for reading the reset source from the application code
z
z
z Clock control
Controls CPU, AHB and APB system clocks
z Multiple clock sources and division factor from GCLK
z Clock prescaler with 1x to 128x division
z Safe run-time clock switching from GCLK
z Module-level clock gating through maskable peripheral clocks
z
z Power management control
z
z
Sleep modes: IDLE, STANDBY
SleepWalking support on GCLK clocks
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14.3
Block Diagram
Figure 14-1. PM Block Diagram
POWER MANAGER
CLK_APB
GCLK
SYNCHRONOUS
CLOCK CONTROLLER
CLK_AHB
PERIPHERALS
CLK_CPU
SLEEP MODE
CONTROLLER
CPU
BOD12
USER RESET
BOD33
POWER RESET
POR
WDT
RESET
CONTROLLER
CPU
RESET
RESET SOURCES
14.4
Signal Description
Signal Name
Type
Description
RESET
Digital input
External reset
Refer to “I/O Multiplexing and Considerations” on page 12 for details on the pin mapping for this peripheral. One signal
can be mapped on several pins.
14.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
14.5.1 I/O Lines
Not applicable.
14.5.2 Power Management
Not applicable.
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14.5.3 Clocks
The PM bus clock (CLK_PM_APB) can be enabled and disabled in the power manager, and the default state of
CLK_PM_APB can be found in Table 14-1. If this clock is disabled in the Power Manager, it can only be re-enabled by a
reset.
A generic clock (GCLK_MAIN) is required to generate the main clock. The clock source for GCLK_MAIN is configured by
default in the Generic Clock Controller, and can be re-configured by the user if needed. Refer to “GCLK – Generic Clock
Controller” on page 90 for details.
14.5.3.1 Main Clock
The main clock (CLK_MAIN) is the common source for the synchronous clocks. This is fed into the common 8-bit
prescaler that is used to generate synchronous clocks to the CPU, AHB and APBx modules.
14.5.3.2 CPU Clock
The CPU clock (CLK_CPU) is routed to the CPU. Halting the CPU clock inhibits the CPU from executing instructions.
14.5.3.3 AHB Clock
The AHB clock (CLK_AHB) is the root clock source used by peripherals requiring an AHB clock. The AHB clock is always
synchronous to the CPU clock and has the same frequency, but may run even when the CPU clock is turned off. A clock
gate is inserted from the common AHB clock to any AHB clock of a peripheral.
14.5.3.4 APBx Clocks
The APBx clock (CLK_APBX) is the root clock source used by modules requiring a clock on the APBx bus. The APBx
clock is always synchronous to the CPU clock, but can be divided by a prescaler, and will run even when the CPU clock
is turned off. A clock gater is inserted from the common APB clock to any APBx clock of a module on APBx bus.
14.5.4 DMA
Not applicable.
14.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the PM interrupt requires the Interrupt Controller
to be configured first. Refer to “Nested Vector Interrupt Controller” on page 29 for details.
14.5.6 Events
Not applicable.
14.5.7 Debug Operation
When the CPU is halted in debug mode, the PM continues normal operation. In sleep mode, the clocks generated from
the PM are kept running to allow the debugger accessing any modules. As a consequence, power measurements are not
possible in debug mode.
14.5.8 Register Access Protection
All registers with write access are optionally write-protected by the Peripheral Access Controller (PAC), except the
following registers:
z
Interrupt Flag register (INTFLAG). Refer to INTFLAG for details
z
Reset Cause register (RCAUSE). Refer to RCAUSE for details
Write-protection is denoted by the Write-Protection property in the register description.
Write-protection does not apply for accesses through an external debugger. Refer to “PAC – Peripheral Access
Controller” on page 36 for details.
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14.5.9 Analog Connections
Not applicable.
14.6
Functional Description
14.6.1 Principle of Operation
14.6.1.1 Synchronous Clocks
The GCLK_MAIN clock from GCLK module provides the source for the main clock, which is the common root for the
synchronous clocks for the CPU and APBx modules. The main clock is divided by an 8-bit prescaler, and each of the
derived clocks can run from any tapping off this prescaler or the undivided main clock, as long as fCPU ≥ fAPBx. The
synchronous clock source can be changed on the fly to respond to varying load in the application. The clocks for each
module in each synchronous clock domain can be individually masked to avoid power consumption in inactive modules.
Depending on the sleep mode, some clock domains can be turned off (see Table 14-4 on page 119).
14.6.1.2 Reset Controller
The Reset Controller collects the various reset sources and generates reset for the device. The device contains a poweron-reset (POR) detector, which keeps the system reset until power is stable. This eliminates the need for external reset
circuitry to guarantee stable operation when powering up the device.
14.6.1.3 Sleep Mode Controller
In ACTIVE mode, all clock domains are active, allowing software execution and peripheral operation. The PM Sleep
Mode Controller allows the user to choose between different sleep modes depending on application requirements, to
save power (see Table 14-4 on page 119).
14.6.2 Basic Operation
14.6.2.1 Initialization
After a power-on reset, the PM is enabled and the Reset Cause (RCAUSE - refer to RCAUSE for details) register
indicates the POR source. The default clock source of the GCLK_MAIN clock is started and calibrated before the CPU
starts running. The GCLK_MAIN clock is selected as the main clock without any division on the prescaler. The device is
in the ACTIVE mode.
By default, only the necessary clocks are enabled (see Table 14-1).
14.6.2.2 Enabling, Disabling and Resetting
The PM module is always enabled and can not be reset.
14.6.2.3 Selecting the Main Clock Source
Refer to “GCLK – Generic Clock Controller” on page 90 for details on how to configure the main clock source.
14.6.2.4 Selecting the Synchronous Clock Division Ratio
The main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks. By default, the
synchronous clocks run on the undivided main clock. The user can select a prescaler division for the CPU clock by
writing the CPU Prescaler Selection bits in the CPU Select register (CPUSEL.CPUDIV), resulting in a CPU clock
frequency determined by this equation:
f main
f CPU = ---------------------CPUDIV
2
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Similarly, the clock for the APBx can be divided by writing their respective registers (APBxSEL.APBxDIV). To ensure
correct operation, frequencies must be selected so that fCPU ≥ fAPBx. Also, frequencies must never exceed the specified
maximum frequency for each clock domain.
Note that the AHB clock is always equal to the CPU clock.
CPUSEL and APBxSEL can be written without halting or disabling peripheral modules. Writing CPUSEL and APBxSEL
allows a new clock setting to be written to all synchronous clocks at the same time. It is possible to keep one or more
clocks unchanged. This way, it is possible to, for example, scale the CPU speed according to the required performance,
while keeping the APBx frequency constant.
Figure 14-2. Synchronous Clock Selection and Prescaler
Sleep Controller
Sleep mode
APBCMASK
Clock
gate
APBCDIV
APBBDIV
Clock
gate
Clock
gate
Clock
gate
CLK_APBB
CLK_PERIPHERAL_APBB_n
CLK_PERIPHERAL_APBB_1
CLK_PERIPHERAL_APBB_0
APBAMASK
Clock
gate
GCLK_MAIN
CLK_PERIPHERAL_APBC_n
CLK_PERIPHERAL_APBC_1
CLK_PERIPHERAL_APBC_0
APBBMASK
Clock
gate
GCLK
Clock
gate
Clock
gate
Clock
gate
CLK_APBC
Clock
gate
Clock
gate
Clock
gate
CLK_PERIPHERAL_APBA_n
CLK_PERIPHERAL_APBA_1
CLK_PERIPHERAL_APBA_0
Clock
gate
Clock
gate
Clock
gate
CLK_PERIPHERAL_AHB_n
CLK_PERIPHERAL_AHB_1
CLK_PERIPHERAL_AHB_0
CLK_APBA
CLK_MAIN
APBADIV
Prescaler
AHBMASK
Clock
gate
CLK_AHB
Clock
gate
CLK_CPU
CPUDIV
14.6.2.5 Clock Ready Flag
There is a slight delay from when CPUSEL and APBxSEL are written until the new clock setting becomes effective.
During this interval, the Clock Ready flag in the Interrupt Flag Status and Clear register (INTFLAG.CKRDY) will read as
zero. If CKRDY in the INTENSET register is written to one, the Power Manager interrupt can be triggered when the new
clock setting is effective. CPUSEL must not be re-written while CKRDY is zero, or the system may become unstable or
hang.
14.6.2.6 Peripheral Clock Masking
It is possible to disable or enable the clock for a peripheral in the AHB or APBx clock domain by writing the corresponding
bit in the Clock Mask register (APBxMASK - refer to APBAMASK for details) to zero or one. Refer to Table 14-1 for the
default state of each of the peripheral clocks.
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Table 14-1. Peripheral Clock Default State
Peripheral Clock
Default State
CLK_PAC0_APB
Enabled
CLK_PM_APB
Enabled
CLK_SYSCTRL_APB
Enabled
CLK_GCLK_APB
Enabled
CLK_WDT_APB
Enabled
CLK_RTC_APB
Enabled
CLK_EIC_APB
Enabled
CLK_PAC1_APB
Enabled
CLK_DSU_APB
Enabled
CLK_NVMCTRL_APB
Enabled
CLK_PORT_APB
Enabled
CLK_HMATRIX_APB
Enabled
CLK_PAC2_APB
Disabled
CLK_SERCOMx_APB
Disabled
CLK_TCx_APB
Disabled
CLK_ADC_APB
Enabled
CLK_AC_APB
Disabled
CLK_PTC_APB
Disabled
CLK_USB_APB
Enabled
CLK_DMAC_APB
Enabled
CLK_TCC_APB
Disabled
CLK_RFCTRL_APB
Disabled
When the APB clock for a module is not provided its registers cannot be read or written. The module can be re-enabled
later by writing the corresponding mask bit to one.
A module may be connected to several clock domains (for instance, AHB and APB), in which case it will have several
mask bits.
Note that clocks should only be switched off if it is certain that the module will not be used. Switching off the clock for the
NVM Controller (NVMCTRL) will cause a problem if the CPU needs to read from the flash memory. Switching off the
clock to the Power Manager (PM), which contains the mask registers, or the corresponding APBx bridge, will make it
impossible to write the mask registers again. In this case, they can only be re-enabled by a system reset.
14.6.2.7 Reset Controller
The latest reset cause is available in RCAUSE, and can be read during the application boot sequence in order to
determine proper action.
There are two groups of reset sources:
z
Power Reset: Resets caused by an electrical issue.
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z
User Reset: Resets caused by the application.
The table below lists the parts of the device that are reset, depending on the reset type.
Table 14-2. Effects of the Different Reset Events
Power Reset
User Reset
POR, BOD12, BOD33
External Reset
WDT Reset,
SysResetReq
RTC
All the 32kHz sources
WDT with ALWAYSON feature
Generic Clock with WRTLOCK
feature
Y
N
N
Debug logic
Y
Y
N
Others
Y
Y
Y
The external reset is generated when pulling the RESET pin low. This pin has an internal pull-up, and does not need to
be driven externally during normal operation.
The POR, BOD12 and BOD33 reset sources are generated by their corresponding module in the System Controller
Interface (SYSCTRL).
The WDT reset is generated by the Watchdog Timer.
The System Reset Request (SysResetReq) is a software reset generated by the CPU when asserting the
SYSRESETREQ bit located in the Reset Control register of the CPU (See the ARM® Cortex® Technical Reference
Manual on http://www.arm.com).
Figure 14-3. Reset Controller
RESET CONTROLLER
BOD12
BOD33
POR
RTC
32kHz clock sources
WDT with ALWAYSON
Generic Clock with
WRTLOCK
Debug Logic
RESET
WDT
Others
CPU
RESET SOURCES
RCAUSE
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14.6.2.8 Sleep Mode Controller
Sleep mode is activated by the Wait For Interrupt instruction (WFI). The Idle bits in the Sleep Mode register
(SLEEP.IDLE) and the SLEEPDEEP bit of the System Control register of the CPU should be used as argument to select
the level of the sleep mode.
There are two main types of sleep mode:
z
IDLE mode: The CPU is stopped. Optionally, some synchronous clock domains are stopped, depending on the
IDLE argument. Regulator operates in normal mode.
z
STANDBY mode: All clock sources are stopped, except those where the RUNSTDBY bit is set. Regulator operates
in low-power mode. Before entering standby mode the user must make sure that a significant amount of clocks
and peripherals are disabled, so that the voltage regulator is not overloaded.
Table 14-3. Sleep Mode Entry and Exit Table
Mode
Level
0
IDLE
1
2
1.
2.
Wake-Up Sources
Synchronous(2) (APB, AHB), asynchronous(1)
SCR.SLEEPDEEP = 0
SLEEP.IDLE=Level
WFI
Synchronous (APB), asynchronous
Asynchronous
SCR.SLEEPDEEP = 1
WFI
STANDBY
Notes:
Mode Entry
Asynchronous
Asynchronous: interrupt generated on generic clock or external clock or external event.
Synchronous: interrupt generated on the APB clock.
Table 14-4. Sleep Mode Overview
Sleep
Mode
CPU
Clock
AHB
Clock
APB
Clock
Oscillators
ONDEMAND = 0
ONDEMAND = 1
RUNSTDBY=0
RUNSTDBY=1
RUNSTDBY=0
RUNSTDBY=1
Main
Clock
Regulator
Mode
RAM
Mode
Idle 0
Stop
Run
Run
Run
Run
Run if
requested
Run if
requested
Run
Normal
Normal
Idle 1
Stop
Stop
Run
Run
Run
Run if
requested
Run if
requested
Run
Normal
Normal
Idle 2
Stop
Stop
Stop
Run
Run
Run if
requested
Run if
requested
Run
Normal
Normal
Standby
Stop
Stop
Stop
Stop
Run
Stop
Run if
requested
Stop
Low
power
Low
power
IDLE Mode
The IDLE modes allow power optimization with the fastest wake-up time.
The CPU is stopped. To further reduce power consumption, the user can disable the clocking of modules and clock
sources by configuring the SLEEP.IDLE bit group. The module will be halted regardless of the bit settings of the mask
registers in the Power Manager (PM.AHBMASK, PM.APBxMASK).
Regulator operates in normal mode.
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z
Entering IDLE mode: The IDLE mode is entered by executing the WFI instruction. Additionally, if the
SLEEPONEXIT bit in the ARM Cortex System Control register (SCR) is set, the IDLE mode will also be entered
when the CPU exits the lowest priority ISR. This mechanism can be useful for applications that only require the
processor to run when an interrupt occurs. Before entering the IDLE mode, the user must configure the IDLE mode
configuration bit group and must write a zero to the SCR.SLEEPDEEP bit.
z
Exiting IDLE mode: The processor wakes the system up when it detects the occurrence of any interrupt that is not
masked in the NVIC Controller with sufficient priority to cause exception entry. The system goes back to the
ACTIVE mode. The CPU and affected modules are restarted.
STANDBY Mode
The STANDBY mode allows achieving very low power consumption.
In this mode, all clocks are stopped except those which are kept running if requested by a running module or have the
ONDEMAND bit set to zero. For example, the RTC can operate in STANDBY mode. In this case, its Generic Clock clock
source will also be enabled.
The regulator and the RAM operate in low-power mode.
A SLEEPONEXIT feature is also available.
z
Entering STANDBY mode: This mode is entered by executing the WFI instruction with the SCR.SLEEPDEEP bit of
the CPU is written to 1.
z
Exiting STANDBY mode: Any peripheral able to generate an asynchronous interrupt can wake up the system. For
example, a module running on a Generic clock can trigger an interrupt. When the enabled asynchronous wake-up
event occurs and the system is woken up, the device will either execute the interrupt service routine or continue
the normal program execution according to the Priority Mask Register (PRIMASK) configuration of the CPU.
14.6.3 SleepWalking
SleepWalking is the capability for a device to temporarily wakeup clocks for peripheral to perform a task without wakingup the CPU in STANDBY sleep mode. At the end of the sleepwalking task, the device can either be waken-up by an
interrupt (from a peripheral involved in SleepWalking) or enter again into STANDBY sleep mode.
In Atmel | SMART SAM R21 devices, SleepWalking is supported only on GCLK clocks by using the on-demand clock
principle of the clock sources. Refer to “On-demand, Clock Requests” on page 88 for more details.
14.6.4 DMA Operation
Not applicable.
14.6.5 Interrupts
The peripheral has the following interrupt sources:
z
Clock Ready flag
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is
cleared, the interrupt is disabled or the peripheral is reset. An interrupt flag is cleared by writing a one to the
corresponding bit in the INTFLAG register. Each peripheral can have one interrupt request line per interrupt source or
one common interrupt request line for all the interrupt sources. Refer to “Nested Vector Interrupt Controller” on page 29
for details. If the peripheral has one common interrupt request line for all the interrupt sources, the user must read the
INTFLAG register to determine which interrupt condition is present.
14.6.6 Events
Not applicable.
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14.6.7 Sleep Mode Operation
In all IDLE sleep modes, the power manager is still running on the selected main clock.
In STANDDBY sleep mode, the power manager is frozen and is able to go back to ACTIVE mode upon any
asynchronous interrupt.
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14.7
Register Summary
Table 14-5. Register Summary
Offset
Name
Bit
Pos.
0x00
CTRL
7:0
0x01
SLEEP
7:0
0x02
...
0x07
Reserved
0x08
CPUSEL
7:0
CPUDIV[2:0]
IDLE[1:0]
0x09
APBASEL
7:0
APBADIV[2:0]
0x0A
APBBSEL
7:0
APBBDIV[2:0]
0x0B
APBCSEL
7:0
APBCDIV[2:0]
0x0C
...
0x13
Reserved
0x14
0x15
0x16
7:0
AHBMASK
0x17
USB
DMAC
NVMCTRL
DSU
HPB2
HPB1
HPB0
EIC
RTC
WDT
GCLK
SYSCTRL
PM
PAC0
USB
DMAC
PORT
NVMCTRL
DSU
PAC1
SERCOM3
SERCOM2
SERCOM1
SERCOM0
EVSYS
PAC2
15:8
TC5
TC4
TC3
TCC2
TCC1
TCC0
23:16
RFCTRL
AC
ADC
15:8
23:16
31:24
0x18
7:0
0x19
15:8
0x1A
APBAMASK
0x1B
23:16
31:24
0x1C
7:0
0x1D
15:8
0x1E
APBBMASK
23:16
0x1F
31:24
0x20
7:0
0x21
0x22
APBCMASK
0x23
SERCOM5
SERCOM4
PTC
31:24
0x24
...
0x33
Reserved
0x34
INTENCLR
7:0
CKRDY
0x35
INTENSET
7:0
CKRDY
0x36
INTFLAG
7:0
CKRDY
0x37
Reserved
0x38
RCAUSE
7:0
SYST
WDT
EXT
BOD33
BOD12
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14.8
Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Exception for APBASEL, APBBSEL and APBCSEL: These registers must only be accessed with 8-bit access.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by
the Write-Protected property in each individual register description. Refer to “Register Access Protection” on page 114
for details.
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14.8.1 Control
Name:
CTRL
Offset:
0x00
Reset:
0x00
Property:
Write-Protected
Bit
7
6
5
4
3
2
1
0
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
z
Bits 7:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
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14.8.2 Sleep Mode
Name:
SLEEP
Offset:
0x01
Reset:
0x00
Property:
Write-Protected
Bit
7
6
5
4
3
2
1
0
IDLE[1:0]
Access
R
R
R
R
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0
z
Bits 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 1:0 – IDLE[1:0]: Idle Mode Configuration
These bits select the Idle mode configuration after a WFI instruction.
Table 14-6. Idle Mode Configuration
IDLE[1:0]
Name
0x0
CPU
The CPU clock domain is stopped
0x1
AHB
The CPU and AHB clock domains are stopped
0x2
APB
The CPU, AHB and APB clock domains are stopped
0x3
Description
Reserved
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14.8.3 CPU Clock Select
Name:
CPUSEL
Offset:
0x08
Reset:
0x00
Property:
Write-Protected
Bit
7
6
5
4
3
2
1
0
CPUDIV[2:0]
Access
R
R
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
z
Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 2:0 – CPUDIV[2:0]: CPU Prescaler Selection
These bits define the division ratio of the main clock prescaler (2n).
Table 14-7. CPU Prescaler Selection
CPUDIV[2:0]
Name
Description
0x0
DIV1
Divide by 1
0x1
DIV2
Divide by 2
0x2
DIV4
Divide by 4
0x3
DIV8
Divide by 8
0x4
DIV16
Divide by 16
0x5
DIV32
Divide by 32
0x6
DIV64
Divide by 64
0x7
DIV128
Divide by 128
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14.8.4 APBA Clock Select
Name:
APBASEL
Offset:
0x09
Reset:
0x00
Property:
Write-Protected
Bit
7
6
5
4
3
2
1
0
APBADIV[2:0]
Access
R
R
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
z
Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 2:0 – APBADIV[2:0]: APBA Prescaler Selection
These bits define the division ratio of the APBA clock prescaler (2n).
Table 14-8. APBA Prescaler Selection
APBADIV[2:0]
Name
Description
0x0
DIV1
Divide by 1
0x1
DIV2
Divide by 2
0x2
DIV4
Divide by 4
0x3
DIV8
Divide by 8
0x4
DIV16
Divide by 16
0x5
DIV32
Divide by 32
0x6
DIV64
Divide by 64
0x7
DIV128
Divide by 128
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14.8.5 APBB Clock Select
Name:
APBBSEL
Offset:
0x0A
Reset:
0x00
Property:
Write-Protected
Bit
7
6
5
4
3
2
1
0
APBBDIV[2:0]
Access
R
R
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
z
Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 2:0 – APBBDIV[2:0]: APBB Prescaler Selection
These bits define the division ratio of the APBB clock prescaler (2n).
Table 14-9. APBB Prescaler Selection
APBBDIV[2:0]
Name
Description
0x0
DIV1
Divide by 1
0x1
DIV2
Divide by 2
0x2
DIV4
Divide by 4
0x3
DIV8
Divide by 8
0x4
DIV16
Divide by 16
0x5
DIV32
Divide by 32
0x6
DIV64
Divide by 64
0x7
DIV128
Divide by 128
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14.8.6 APBC Clock Select
Name:
APBCSEL
Offset:
0x0B
Reset:
0x00
Property:
Write-Protected
Bit
7
6
5
4
3
2
1
0
APBCDIV[2:0]
Access
R
R
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
z
Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 2:0 – APBCDIV[2:0]: APBC Prescaler Selection
These bits define the division ratio of the APBC clock prescaler (2n).
Table 14-10. APBC Prescaler Selection
APBCDIV[2:0]
Name
Description
0x0
DIV1
Divide by 1
0x1
DIV2
Divide by 2
0x2
DIV4
Divide by 4
0x3
DIV8
Divide by 8
0x4
DIV16
Divide by 16
0x5
DIV32
Divide by 32
0x6
DIV64
Divide by 64
0x7
DIV128
Divide by 128
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14.8.7 AHB Mask
Name:
AHBMASK
Offset:
0x14
Reset:
0x0000007F
Property:
Write-Protected
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
USB
DMAC
NVMCTRL
DSU
HPB2
HPB1
HPB0
Access
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
1
1
1
1
1
1
1
z
Bits 31:7 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 6 – USB: USB AHB Clock Mask
0: The AHB clock for the USB is stopped.
1: The AHB clock for the USB is enabled.
z
Bit 5 – DMAC: DMAC AHB Clock Mask
0: The AHB clock for the DMAC is stopped.
1: The AHB clock for the DMAC is enabled.
z
Bit 4 – NVMCTRL: NVMCTRL AHB Clock Mask
0: The AHB clock for the NVMCTRL is stopped.
1: The AHB clock for the NVMCTRL is enabled.
z
Bit 3 – DSU: DSU AHB Clock Mask
0: The AHB clock for the DSU is stopped.
1: The AHB clock for the DSU is enabled.
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z
Bit 2 – HPB2: HPB2 AHB Clock Mask
0: The AHB clock for the HPB2 is stopped.
1: The AHB clock for the HPB2 is enabled.
z
Bit 1 – HPB1: HPB1 AHB Clock Mask
0: The AHB clock for the HPB1 is stopped.
1: The AHB clock for the HPB1 is enabled.
z
Bit 0 – HPB0: HPB0 AHB Clock Mask
0: The AHB clock for the HPB0 is stopped.
1: The AHB clock for the HPB0 is enabled.
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14.8.8 APBA Mask
Name:
APBAMASK
Offset:
0x18
Reset:
0x0000007F
Property:
Write-Protected
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
EIC
RTC
WDT
GCLK
SYSCTRL
PM
PAC0
Access
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
1
1
1
1
1
1
1
z
Bits 31:7 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 6 – EIC: EIC APB Clock Enable
0: The APBA clock for the EIC is stopped.
1: The APBA clock for the EIC is enabled.
z
Bit 5 – RTC: RTC APB Clock Enable
0: The APBA clock for the RTC is stopped.
1: The APBA clock for the RTC is enabled.
z
Bit 4 – WDT: WDT APB Clock Enable
0: The APBA clock for the WDT is stopped.
1: The APBA clock for the WDT is enabled.
z
Bit 3 – GCLK: GCLK APB Clock Enable
0: The APBA clock for the GCLK is stopped.
1: The APBA clock for the GCLK is enabled.
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z
Bit 2 – SYSCTRL: SYSCTRL APB Clock Enable
0: The APBA clock for the SYSCTRL is stopped.
1: The APBA clock for the SYSCTRL is enabled.
z
Bit 1 – PM: PM APB Clock Enable
0: The APBA clock for the PM is stopped.
1: The APBA clock for the PM is enabled.
z
Bit 0 – PAC0: PAC0 APB Clock Enable
0: The APBA clock for the PAC0 is stopped.
1: The APBA clock for the PAC0 is enabled.
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14.8.9 APBB Mask
Name:
APBBMASK
Offset:
0x1C
Reset:
0x0000007F
Property:
Write-Protected
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
USB
DMAC
PORT
NVMCTRL
DSU
PAC1
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
1
1
1
1
1
1
z
Bits 31:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 5 – USB: USB APB Clock Enable
0: The APBB clock for the USB is stopped.
1: The APBB clock for the USB is enabled.
z
Bit 4 – DMAC: DMAC APB Clock Enable
0: The APBB clock for the DMAC is stopped.
1: The APBB clock for the DMAC is enabled.
z
Bit 3 – PORT: PORT APB Clock Enable
0: The APBB clock for the PORT is stopped.
1: The APBB clock for the PORT is enabled.
z
Bit 2 – NVMCTRL: NVMCTRL APB Clock Enable
0: The APBB clock for the NVMCTRL is stopped.
1: The APBB clock for the NVMCTRL is enabled.
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z
Bit 1 – DSU: DSU APB Clock Enable
0: The APBB clock for the DSU is stopped.
1: The APBB clock for the DSU is enabled.
z
Bit 0 – PAC1: PAC1 APB Clock Enable
0: The APBB clock for the PAC1 is stopped.
1: The APBB clock for the PAC1 is enabled.
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14.8.10 APBC Mask
Name:
APBCMASK
Offset:
0x20
Reset:
0x00010000
Property:
Write-Protected
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
AC
ADC
RFCTRL
PTC
Access
R
R
R/W
R
R/W
R
R/W
R/W
Reset
0
0
0
0
0
0
0
1
Bit
15
14
13
12
11
10
9
8
TC5
TC4
TC3
TCC2
TCC1
TCC0
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
SERCOM5
SERCOM4
SERCOM3
SERCOM2
SERCOM1
SERCOM0
EVSYS
PAC2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Access
Reset
z
Bits 31:22 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 21 – RFCTRL: RFCTRL APB Clock Enable
0: The APBC clock for the RFCTRL is stopped.
1: The APBC clock for the RFCTRL is enabled.
z
Bit 20 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bit 19 – PTC: PTC APB Clock Enable
0: The APBC clock for the PTC is stopped.
1: The APBC clock for the PTC is enabled.
z
Bit 18 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
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z
Bit 17 – AC: AC APB Clock Enable
0: The APBC clock for the AC is stopped.
1: The APBC clock for the AC is enabled.
z
Bit 16 – ADC: ADC APB Clock Enable
0: The APBC clock for the ADC is stopped.
1: The APBC clock for the ADC is enabled.
z
Bits 15:14 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 13 – TC5: TC5 APB Clock Enable
0: The APBC clock for the TC5 is stopped.
1: The APBC clock for the TC5 is enabled.
z
Bit 12 – TC4: TC4 APB Clock Enable
0: The APBC clock for the TC4 is stopped.
1: The APBC clock for the TC4 is enabled.
z
Bit 11 – TC3: TC3 APB Clock Enable
0: The APBC clock for the TC3 is stopped.
1: The APBC clock for the TC3 is enabled.
z
Bit 10 – TCC2: TCC2 APB Clock Enable
0: The APBC clock for the TCC2 is stopped.
1: The APBC clock for the TCC2 is enabled.
z
Bit 9 – TCC1: TCC1 APB Clock Enable
0: The APBC clock for the TCC1 is stopped.
1: The APBC clock for the TCC1 is enabled.
z
Bit 8 – TCC0: TCC0 APB Clock Enable
0: The APBC clock for the TCC0 is stopped.
1: The APBC clock for the TCC0 is enabled.
z
Bit 7 – SERCOM5: SERCOM5 APB Clock Enable
0: The APBC clock for the SERCOM5 is stopped.
1: The APBC clock for the SERCOM5 is enabled.
z
Bit 6 – SERCOM4: SERCOM4 APB Clock Enable
0: The APBC clock for the SERCOM4 is stopped.
1: The APBC clock for the SERCOM4 is enabled.
z
Bit 5 – SERCOM3: SERCOM3 APB Clock Enable
0: The APBC clock for the SERCOM3 is stopped.
1: The APBC clock for the SERCOM3 is enabled.
z
Bit 4 – SERCOM2: SERCOM2 APB Clock Enable
0: The APBC clock for the SERCOM2 is stopped.
1: The APBC clock for the SERCOM2 is enabled.
z
Bit 3 – SERCOM1: SERCOM1 APB Clock Enable
0: The APBC clock for the SERCOM1 is stopped.
1: The APBC clock for the SERCOM1 is enabled.
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z
Bit 2 – SERCOM0: SERCOM0 APB Clock Enable
0: The APBC clock for the SERCOM0 is stopped.
1: The APBC clock for the SERCOM0 is enabled.
z
Bit 1 – EVSYS: EVSYS APB Clock Enable
0: The APBC clock for the EVSYS is stopped.
1: The APBC clock for the EVSYS is enabled.
z
Bit 0 – PAC2: PAC2 APB Clock Enable
0: The APBC clock for the PAC2 is stopped.
1: The APBC clock for the PAC2 is enabled.
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14.8.11 Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set (INTENSET) register.
Name:
INTENCLR
Offset:
0x34
Reset:
0x00
Property:
Write-Protected
Bit
7
6
5
4
3
2
1
0
CKRDY
Access
R
R
R
R
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0
z
Bits 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 0 – CKRDY: Clock Ready Interrupt Enable
0: The Clock Ready interrupt is disabled.
1: The Clock Ready interrupt is enabled and will generate an interrupt request when the Clock Ready Interrupt flag
is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Clock Ready Interrupt Enable bit and the corresponding interrupt request.
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14.8.12 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name:
INTENSET
Offset:
0x35
Reset:
0x00
Property:
Write-Protected
Bit
7
6
5
4
3
2
1
0
CKRDY
Access
R
R
R
R
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0
z
Bits 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 0 – CKRDY: Clock Ready Interrupt Enable
0: The Clock Ready interrupt is disabled.
1: The Clock Ready interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Clock Ready Interrupt Enable bit and enable the Clock Ready interrupt.
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14.8.13 Interrupt Flag Status and Clear
Name:
INTFLAG
Offset:
0x36
Reset:
0x00
Property:
-
Bit
7
6
5
4
3
2
1
0
CKRDY
Access
R
R
R
R
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0
z
Bits 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 0 – CKRDY: Clock Ready
This flag is cleared by writing a one to the flag.
This flag is set when the synchronous CPU and APBx clocks have frequencies as indicated in the CPUSEL and
APBxSEL registers, and will generate an interrupt if INTENCLR/SET.CKRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Clock Ready Interrupt flag.
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14.8.14 Reset Cause
Name:
RCAUSE
Offset:
0x38
Reset:
0x01
Property:
-
Bit
7
6
5
4
SYST
WDT
EXT
3
2
1
0
BOD33
BOD12
POR
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
1
z
Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bit 6 – SYST: System Reset Request
This bit is set if a system reset request has been performed. Refer to the Cortex processor documentation for more
details.
z
Bit 5 – WDT: Watchdog Reset
This flag is set if a Watchdog Timer reset occurs.
z
Bit 4 – EXT: External Reset
This flag is set if an external reset occurs.
z
Bit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bit 2 – BOD33: Brown Out 33 Detector Reset
This flag is set if a BOD33 reset occurs.
z
Bit 1 – BOD12: Brown Out 12 Detector Reset
This flag is set if a BOD12 reset occurs.
z
Bit 0 – POR: Power On Reset
This flag is set if a POR occurs.
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15.
15.1
SYSCTRL – System Controller
Overview
The System Controller (SYSCTRL) provides a user interface to the clock sources, brown out detectors, on-chip voltage
regulator and voltage reference of the device.
Through the interface registers, it is possible to enable, disable, calibrate and monitor the SYSCTRL sub-peripherals.
All sub-peripheral statuses are collected in the Power and Clocks Status register (PCLKSR - refer to PCLKSR). They can
additionally trigger interrupts upon status changes via the INTENSET (INTENSET), INTENCLR (INTENCLR) and
INTFLAG (INTFLAG) registers.
Additionally, BOD33 interrupts can be used to wake up the device from standby mode upon a programmed brown-out
detection.
15.2
Features
z 0.4-32MHz Crystal Oscillator (XOSC)
Tunable gain control
Programmable start-up time
z Crystal or external input clock on XIN I/O
z
z
z 32.768kHz Crystal Oscillator (XOSC32K)
Automatic or manual gain control
Programmable start-up time
z Crystal or external input clock on XIN32 I/O
z
z
z 32.768kHz High Accuracy Internal Oscillator (OSC32K)
z
z
Frequency fine tuning
Programmable start-up time
z 32.768kHz Ultra Low Power Internal Oscillator (OSCULP32K)
Ultra low power, always-on oscillator
Frequency fine tuning
z Calibration value loaded from Flash Factory Calibration at reset
z
z
z 8MHz Internal Oscillator (OSC8M)
Fast startup
Output frequency fine tuning
z 4/2/1MHz divided output frequencies available
z Calibration value loaded from Flash Factory Calibration at reset
z
z
z Digital Frequency Locked Loop (DFLL48M)
Internal oscillator with no external components
48MHz output frequency
z Operates standalone as a high-frequency programmable oscillator in open loop mode
z Operates as an accurate frequency multiplier against a known frequency in closed loop mode
z
z
z Fractional Digital Phase Locked Loop (FDPLL96M)
48MHz to 96MHz output clock frequency
32KHz to 2MHz input reference clock frequency range
z Three possible sources for the reference clock
z Adjustable proportional integral controller
z Fractional part used to achieve 1/16th of reference clock step
z
z
z 3.3V Brown-Out Detector (BOD33)
Programmable threshold
Threshold value loaded from Flash User Calibration at startup
z Triggers resets or interrupts
z Operating modes:
z Continuous mode
z
z
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z
z Sampled mode for low power applications (programmable refresh frequency)
Hysteresis
z Internal Voltage Regulator system (VREG)
Operating modes:
z Normal mode
z Low-power mode
z With an internal non-configurable Brown-out detector (BOD12)
z
z Voltage Reference System (VREF)
Bandgap voltage generator with programmable calibration value
Temperature sensor
z Bandgap calibration value loaded from Flash Factory Calibration at startup
z
z
15.3
Block Diagram
Figure 15-1. SYSCTRL Block Diagram
SYSCTRL
XOSC
XOSC32K
OSC32K
OSCILLATORS
CONTROL
OSCULP32K
OSC8M
DFLL48M
FDPLL96M
POWER
MONITOR
CONTROL
BOD33
VOLTAGE
REFERENCE
CONTROL
VOLTAGE
REFERENCE
SYSTEM
STATUS
(PCLKSR register)
INTERRUPTS
GENERATOR
Interrupts
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15.4
Signal Description
Signal Name
Types
XIN
Analog Input
XOUT
Analog Output
XIN32
Analog Input
XOUT32
Analog Output
Description
Multipurpose Crystal Oscillator or external
clock generator input
External Multipurpose Crystal Oscillator
output
32kHz Crystal Oscillator or external clock
generator input
32kHz Crystal Oscillator output
The I/O lines are automatically selected when XOSC or XOSC32K are enabled. Refer to “Oscillator Pinout” on page 14.
15.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
15.5.1 I/O Lines
I/O lines are configured by SYSCTRL when either XOSC or XOSC32K are enabled, and need no user configuration.
15.5.2 Power Management
The SYSCTRL can continue to operate in any sleep mode where the selected source clock is running. The SYSCTRL
interrupts can be used to wake up the device from sleep modes. The events can trigger other operations in the system
without exiting sleep modes. Refer to “PM – Power Manager” on page 112 for details on the different sleep modes.
15.5.3 Clocks
The SYSCTRL gathers controls for all device oscillators and provides clock sources to the Generic Clock Controller
(GCLK). The available clock sources are: XOSC, XOSC32K, OSC32K, OSCULP32K, OSC8M, DFLL48M and
FDPLL96M.
The SYSCTRL bus clock (CLK_SYSCTRL_APB) can be enabled and disabled in the Power Manager, and the default
state of CLK_SYSCTRL_APB can be found in the Peripheral Clock Masking section in the “PM – Power Manager” on
page 112.
The clock used by BOD33in sampled mode is asynchronous to the user interface clock (CLK_SYSCTRL_APB).
Likewise, the DFLL48M control logic uses the DFLL oscillator output, which is also asynchronous to the user interface
clock (CLK_SYSCTRL_APB). Due to this asynchronicity, writes to certain registers will require synchronization between
the clock domains. Refer to “Synchronization” on page 159 for further details.
15.5.4 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the SYSCTRL interrupts requires the Interrupt
Controller to be configured first. Refer to “Nested Vector Interrupt Controller” on page 29 for details.
15.5.5 Debug Operation
When the CPU is halted in debug mode, the SYSCTRL continues normal operation. If the SYSCTRL is configured in a
way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss
may result during debugging.
If a debugger connection is detected by the system, BOD33 reset will be blocked.
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15.5.6 Register Access Protection
All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the
following registers:
z
Interrupt Flag Status and Clear register (INTFLAG - refer to INTFLAG)
Write-protection is denoted by the Write-Protection property in the register description.
When the CPU is halted in debug mode, all write-protection is automatically disabled.
Write-protection does not apply for accesses through an external debugger. Refer to “PAC – Peripheral Access
Controller” on page 36 for details.
15.5.7 Analog Connections
When used, the 32.768kHz crystal must be connected between the XIN32 and XOUT32 pins, and the 0.4-32MHz crystal
must be connected between the XIN and XOUT pins, along with any required load capacitors. For details on
recommended oscillator characteristics and capacitor load, refer to the “Electrical Characteristics” on page 1055 for
details.
15.6
Functional Description
15.6.1 Principle of Operation
XOSC, XOSC32K, OSC32K, OSCULP32K, OSC8M, DFLL48M, FDPLL96M, BOD33, and VREF are configured via
SYSCTRL control registers. Through this interface, the sub-peripherals are enabled, disabled or have their calibration
values updated.
The Power and Clocks Status register gathers different status signals coming from the sub-peripherals controlled by the
SYSCTRL. The status signals can be used to generate system interrupts, and in some cases wake up the system from
standby mode, provided the corresponding interrupt is enabled.
The oscillator must be enabled to run. The oscillator is enabled by writing a one to the ENABLE bit in the respective
oscillator control register, and disabled by writing a zero to the oscillator control register. In idle mode, the default
operation of the oscillator is to run only when requested by a peripheral. In standby mode, the default operation of the
oscillator is to stop. This behavior can be changed by the user, see below for details.
The behavior of the oscillators in the different sleep modes is shown in Table 15-1 on page 146
Table 15-1. Behavior of the Oscillators
Oscillator
Idle 0,
1,
2
Standby
XOSC
Run on request
Stop
XOSC32K
Run on request
Stop
OSC32K
Run on request
Stop
OSCULP32K
Run
Run
OSC8M
Run on request
Stop
DFLL48M
Run on request
Stop
FDPLL96M
Run on request
Stop
To force an oscillator to always run in idle mode, and not only when requested by a peripheral, the oscillator
ONDEMAND bit must be written to zero. The default value of this bit is one, and thus the default operation in idle mode is
to run only when requested by a peripheral.
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To force the oscillator to run in standby mode, the RUNSTDBY bit must be written to one. The oscillator will then run in
standby mode when requested by a peripheral (ONDEMAND is one). To force an oscillator to always run in standby
mode, and not only when requested by a peripheral, the ONDEMAND bit must be written to zero and RUNSTDBY must
be written to one.
Table 15-2 on page 147 shows the behavior in the different sleep modes, depending on the settings of ONDEMAND and
RUNSTDBY.
Table 15-2. Behavior in the different sleep modes
Sleep mode
ONDEMAND
RUNSTDBY
Behavior
Idle
0,
1,
2
0
X
Run
Idle
0,
1,
2
1
X
Run when requested by a peripheral
Standby
0
0
Stop
Standby
0
1
Run
Standby
1
0
Stop
Standby
1
1
Run when requested by a peripheral
Note that this does not apply to the OSCULP32K oscillator, which is always running and cannot be disabled.
15.6.2 External Multipurpose Crystal Oscillator (XOSC) Operation
The XOSC can operate in two different modes:
z
External clock, with an external clock signal connected to the XIN pin
z
Crystal oscillator, with an external 0.4-32MHz crystal
The XOSC can be used as a clock source for generic clock generators, as described in the “GCLK – Generic Clock
Controller” on page 90.
At reset, the XOSC is disabled, and the XIN/XOUT pins can be used as General Purpose I/O (GPIO) pins or by other
peripherals in the system. When XOSC is enabled, the operating mode determines the GPIO usage. When in crystal
oscillator mode, the XIN and XOUT pins are controlled by the SYSCTRL, and GPIO functions are overridden on both
pins. When in external clock mode, only the XIN pin will be overridden and controlled by the SYSCTRL, while the XOUT
pin can still be used as a GPIO pin.
The XOSC is enabled by writing a one to the Enable bit in the External Multipurpose Crystal Oscillator Control register
(XOSC.ENABLE). To enable the XOSC as a crystal oscillator, a one must be written to the XTAL Enable bit
(XOSC.XTALEN). If XOSC.XTALEN is zero, external clock input will be enabled.
When in crystal oscillator mode (XOSC.XTALEN is one), the External Multipurpose Crystal Oscillator Gain (XOSC.GAIN)
must be set to match the external crystal oscillator frequency. If the External Multipurpose Crystal Oscillator Automatic
Amplitude Gain Control (XOSC.AMPGC) is one, the oscillator amplitude will be automatically adjusted, and in most
cases result in a lower power consumption.
The XOSC will behave differently in different sleep modes based on the settings of XOSC.RUNSTDBY,
XOSC.ONDEMAND and XOSC.ENABLE:
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XOSC.RUNSTDBY
XOSC.ONDEMAND
XOSC.ENABLE
Sleep Behavior
-
-
0
Disabled
0
0
1
Always run in IDLE sleep modes.
Disabled in STANDBY sleep mode.
0
1
1
Only run in IDLE sleep modes if
requested by a peripheral. Disabled in
STANDBY sleep mode.
1
0
1
Always run in IDLE and STANDBY sleep
modes.
1
1
1
Only run in IDLE or STANDBY sleep
modes if requested by a peripheral.
After a hard reset, or when waking up from a sleep mode where the XOSC was disabled, the XOSC will need a certain
amount of time to stabilize on the correct frequency. This start-up time can be configured by changing the Oscillator
Start-Up Time bit group (XOSC.STARTUP) in the External Multipurpose Crystal Oscillator Control register. During the
start-up time, the oscillator output is masked to ensure that no unstable clock propagates to the digital logic. The External
Multipurpose Crystal Oscillator Ready bit in the Power and Clock Status register (PCLKSR.XOSCRDY) is set when the
user-selected startup time is over. An interrupt is generated on a zero-to-one transition on PCLKSR.XOSCRDY if the
External Multipurpose Crystal Oscillator Ready bit in the Interrupt Enable Set register (INTENSET.XOSCRDY) is set.
Note:
Do not enter standby mode when an oscillator is in startup:
Wait for the OSCxRDY bit in SYSCTRL.PCLKSR register to be set before going into standby mode.
15.6.3 32kHz External Crystal Oscillator (XOSC32K) Operation
The XOSC32K can operate in two different modes:
z
External clock, with an external clock signal connected to XIN32
z
Crystal oscillator, with an external 32.768kHz crystal connected between XIN32 and XOUT32
The XOSC32K can be used as a source for generic clock generators, as described in the “GCLK – Generic Clock
Controller” on page 90.
At power-on reset (POR) the XOSC32K is disabled, and the XIN32/XOUT32 pins can be used as General Purpose I/O
(GPIO) pins or by other peripherals in the system. When XOSC32K is enabled, the operating mode determines the GPIO
usage. When in crystal oscillator mode, XIN32 and XOUT32 are controlled by the SYSCTRL, and GPIO functions are
overridden on both pins. When in external clock mode, only the XIN32 pin will be overridden and controlled by the
SYSCTRL, while the XOUT32 pin can still be used as a GPIO pin.
The external clock or crystal oscillator is enabled by writing a one to the Enable bit (XOSC32K.ENABLE) in the 32kHz
External Crystal Oscillator Control register. To enable the XOSC32K as a crystal oscillator, a one must be written to the
XTAL Enable bit (XOSC32K.XTALEN). If XOSC32K.XTALEN is zero, external clock input will be enabled.
The oscillator is disabled by writing a zero to the Enable bit (XOSC32K.ENABLE) in the 32kHz External Crystal Oscillator
Control register while keeping the other bits unchanged. Writing to the XOSC32K.ENABLE bit while writing to other bits
may result in unpredictable behavior. The oscillator remains enabled in all sleep modes if it has been enabled
beforehand. The start-up time of the 32kHz External Crystal Oscillator is selected by writing to the Oscillator Start-Up
Time bit group (XOSC32K.STARTUP) in the in the 32kHz External Crystal Oscillator Control register. The SYSCTRL
masks the oscillator output during the start-up time to ensure that no unstable clock propagates to the digital logic. The
32kHz External Crystal Oscillator Ready bit (PCLKSR.XOSC32KRDY) in the Power and Clock Status register is set
when the user-selected startup time is over. An interrupt is generated on a zero-to-one transition of
PCLKSR.XOSC32KRDY if the 32kHz External Crystal Oscillator Ready bit (INTENSET.XOSC32KRDY) in the Interrupt
Enable Set Register is set.
As a crystal oscillator usually requires a very long start-up time (up to one second), the 32kHz External Crystal Oscillator
will keep running across resets, except for power-on reset (POR).
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XOSC32K can provide two clock outputs when connected to a crystal. The XOSC32K has a 32.768kHz output enabled
by writing a one to the 32kHz External Crystal Oscillator 32kHz Output Enable bit (XOSC32K.EN32K) in the 32kHz
External Crystal Oscillator Control register. XOSC32K.EN32K is only usable when XIN32 is connected to a crystal, and
not when an external digital clock is applied on XIN32.
Note:
Do not enter standby mode when an oscillator is in startup:
Wait for the OSCxRDY bit in SYSCTRL.PCLKSR register to be set before going into standby mode.
15.6.4 32kHz Internal Oscillator (OSC32K) Operation
The OSC32K provides a tunable, low-speed and low-power clock source.
The OSC32K can be used as a source for the generic clock generators, as described in the “GCLK – Generic Clock
Controller” on page 90.
The OSC32K is disabled by default. The OSC32K is enabled by writing a one to the 32kHz Internal Oscillator Enable bit
(OSC32K.ENABLE) in the 32kHz Internal Oscillator Control register. It is disabled by writing a zero to OSC32K.ENABLE.
The OSC32K has a 32.768kHz output enabled by writing a one to the 32kHz Internal Oscillator 32kHz Output Enable bit
(OSC32K.EN32K).
The frequency of the OSC32K oscillator is controlled by the value in the 32kHz Internal Oscillator Calibration bits
(OSC32K.CALIB) in the 32kHz Internal Oscillator Control register. The OSC32K.CALIB value must be written by the
user. Flash Factory Calibration values are stored in the NVM Software Calibration Area (refer to “NVM Software
Calibration Area Mapping” on page 26). When writing to the Calibration bits, the user must wait for the
PCLKSR.OSC32KRDY bit to go high before the value is committed to the oscillator.
15.6.5 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Operation
The OSCULP32K provides a tunable, low-speed and ultra-low-power clock source. The OSCULP32K is factorycalibrated under typical voltage and temperature conditions. The OSCULP32K should be preferred to the OSC32K
whenever the power requirements are prevalent over frequency stability and accuracy.
The OSCULP32K can be used as a source for the generic clock generators, as described in the “GCLK – Generic Clock
Controller” on page 90.
The OSCULP32K is enabled by default after a power-on reset (POR) and will always run except during POR. The
OSCULP32K has a 32.768kHz output and a 1.024kHz output that are always running.
The frequency of the OSCULP32K oscillator is controlled by the value in the 32kHz Ultra Low Power Internal Oscillator
Calibration bits (OSCULP32K.CALIB) in the 32kHz Ultra Low Power Internal Oscillator Control register.
OSCULP32K.CALIB is automatically loaded from Flash Factory Calibration during startup, and is used to compensate for
process variation, as described in the “Electrical Characteristics” on page 1055. The calibration value can be overridden
by the user by writing to OSCULP32K.CALIB.
15.6.6 8MHz Internal Oscillator (OSC8M) Operation
OSC8M is an internal oscillator operating in open-loop mode and generating an 8MHz frequency. The OSC8M is factorycalibrated under typical voltage and temperature conditions.
OSC8M is the default clock source that is used after a power-on reset (POR). The OSC8M can be used as a source for
the generic clock generators, as described in the “GCLK – Generic Clock Controller” on page 90.
In order to enable OSC8M, the Oscillator Enable bit in the OSC8M Control register (OSC8M.ENABLE) must be written to
one. OSC8M will not be enabled until OSC8M.ENABLE is set. In order to disable OSC8M, OSC8M.ENABLE must be
written to zero. OSC8M will not be disabled until OSC8M is cleared.
The frequency of the OSC8M oscillator is controlled by the value in the calibration bits (OSC8M.CALIB) in the OSC8M
Control register. CALIB is automatically loaded from Flash Factory Calibration during startup, and is used to compensate
for process variation, as described in the “Electrical Characteristics” on page 1055.
The user can control the oscillation frequency by writing to the Frequency Range (FRANGE) and Calibration (CALIB) bit
groups in the 8MHz RC Oscillator Control register (OSC8M). It is not recommended to update the FRANGE and CALIB
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bits when the OSC8M is enabled. As this is in open-loop mode, the frequency will be voltage, temperature and process
dependent. Refer to the “Electrical Characteristics” on page 1055 for details.
OSC8M is automatically switched off in certain sleep modes to reduce power consumption, as described in the “PM –
Power Manager” on page 112.
15.6.7 Digital Frequency Locked Loop (DFLL48M) Operation
The DFLL48M can operate in both open-loop mode and closed-loop mode. In closed-loop mode, a low-frequency clock
with high accuracy can be used as the reference clock to get high accuracy on the output clock (CLK_DFLL48M).
The DFLL48M can be used as a source for the generic clock generators, as described in the “GCLK – Generic Clock
Controller” on page 90.
15.6.7.1 Basic Operation
Open-Loop Operation
After any reset, the open-loop mode is selected. When operating in open-loop mode, the output frequency of the
DFLL48M will be determined by the values written to the DFLL Coarse Value bit group and the DFLL Fine Value bit
group (DFLLVAL.COARSE and DFLLVAL.FINE) in the DFLL Value register. Using "DFLL48M COARSE CAL" value
from “NVM User Row Mapping” on page 25 in DFLL.COARSE helps to output a frequency close to 48 MHz.
It is possible to change the values of DFLLVAL.COARSE and DFLLVAL.FINE and thereby the output frequency of the
DFLL48M output clock, CLK_DFLL48M, while the DFLL48M is enabled and in use. CLK_DFLL48M is ready to be used
when PCLKSR.DFLLRDY is set after enabling the DFLL48M.
Closed-Loop Operation
In closed-loop operation, the output frequency is continuously regulated against a reference clock. Once the
multiplication factor is set, the oscillator fine tuning is automatically adjusted. The DFLL48M must be correctly configured
before closed-loop operation can be enabled. After enabling the DFLL48M, it must be configured in the following way:
1.
Enable and select a reference clock (CLK_DFLL48M_REF). CLK_DFLL48M_REF is Generic Clock Channel 0
(GCLK_DFLL48M_REF). Refer to “GCLK – Generic Clock Controller” on page 90 for details.
2.
Select the maximum step size allowed in finding the Coarse and Fine values by writing the appropriate values to
the DFLL Coarse Maximum Step and DFLL Fine Maximum Step bit groups (DFLLMUL.CSTEP and DFLLMUL.FSTEP) in the DFLL Multiplier register. A small step size will ensure low overshoot on the output frequency,
but will typically result in longer lock times. A high value might give a large overshoot, but will typically provide
faster locking. DFLLMUL.CSTEP and DFLLMUL.FSTEP should not be higher than 50% of the maximum value of
DFLLVAL.COARSE and DFLLVAL.FINE, respectively.
3.
Select the multiplication factor in the DFLL Multiply Factor bit group (DFLLMUL.MUL) in the DFLL Multiplier register. Care must be taken when choosing DFLLMUL.MUL so that the output frequency does not exceed the
maximum frequency of the DFLL. If the target frequency is below the minimum frequency of the DFLL48M, the output frequency will be equal to the DFLL minimum frequency.
4.
Start the closed loop mode by writing a one to the DFLL Mode Selection bit (DFLLCTRL.MODE) in the DFLL Control register.
The frequency of CLK_DFLL48M (Fclkdfll48m) is given by:
F clkdfll48m = DFLLMUL.MUL × F clkdfll48mref
where Fclkdfll48mref is the frequency of the reference clock (CLK_DFLL48M_REF). DFLLVAL.COARSE and
DFLLVAL.FINE are read-only in closed-loop mode, and are controlled by the frequency tuner to meet user specified
frequency. In closed-loop mode, the value in DFLLVAL.COARSE is used by the frequency tuner as a starting point for
Coarse. Writing DFLLVAL.COARSE to a value close to the final value before entering closed-loop mode will reduce the
time needed to get a lock on Coarse.
Using "DFLL48M COARSE CAL" from “NVM User Row Mapping” on page 25 for DFLL.COARSE will start DFLL with a
frequency close to 48 MHz.
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Following Software sequence should be followed while using the same.
1.
load "DFLL48M COARSE CAL" from “NVM User Row Mapping” on page 25 in DFLL.COARSE register
2.
Set DFLLCTRL.BPLCKC bit
3.
Start DFLL close loop
This procedure will reduce DFLL Lock time to DFLL Fine lock time.
Frequency Locking
The locking of the frequency in closed-loop mode is divided into two stages. In the first, coarse stage, the control logic
quickly finds the correct value for DFLLVAL.COARSE and sets the output frequency to a value close to the correct
frequency. On coarse lock, the DFLL Locked on Coarse Value bit (PCLKSR.DFLLLOCKC) in the Power and Clocks
Status register will be set.
In the second, fine stage, the control logic tunes the value in DFLLVAL.FINE so that the output frequency is very close to
the desired frequency. On fine lock, the DFLL Locked on Fine Value bit (PCLKSR.DFLLLOCKF) in the Power and Clocks
Status register will be set.
Interrupts are generated by both PCLKSR.DFLLLOCKC and PCLKSR.DFLLLOCKF if INTENSET.DFLLOCKC or
INTENSET.DFLLOCKF are written to one.
CLK_DFLL48M is ready to be used when the DFLL Ready bit (PCLKSR.DFLLRDY) in the Power and Clocks Status
register is set, but the accuracy of the output frequency depends on which locks are set. For lock times, refer to the
“Electrical Characteristics” on page 1055.
Frequency Error Measurement
The ratio between CLK_DFLL48M_REF and CLK48M_DFLL is measured automatically when the DFLL48M is in closedloop mode. The difference between this ratio and the value in DFLLMUL.MUL is stored in the DFLL Multiplication Ratio
Difference bit group(DFLLVAL.DIFF) in the DFLL Value register. The relative error on CLK_DFLL48M compared to the
target frequency is calculated as follows:
DIFF
ERROR = -------------MUL
Drift Compensation
If the Stable DFLL Frequency bit (DFLLCTRL.STABLE) in the DFLL Control register is zero, the frequency tuner will
automatically compensate for drift in the CLK_DFLL48M without losing either of the locks. This means that
DFLLVAL.FINE can change after every measurement of CLK_DFLL48M.
The DFLLVAL.FINE value overflows or underflows can occur in close loop mode when the clock source reference drifts
or is unstable. This will set the DFLL Out Of Bounds bit (PCLKSR.DFLLOOB) in the Power and Clocks Status register.
To avoid this error, the reference clock in close loop mode must be stable, an external oscillator is recommended and
internal oscillator forbidden. The better choice is to use an XOSC32K.
Reference Clock Stop Detection
If CLK_DFLL48M_REF stops or is running at a very low frequency (slower than CLK_DFLL48M/(2 * MULMAX)), the DFLL
Reference Clock Stopped bit (PCLKSR.DFLLRCS) in the Power and Clocks Status register will be set. Detecting a
stopped reference clock can take a long time, on the order of 217 CLK_DFLL48M cycles. When the reference clock is
stopped, the DFLL48M will operate as if in open-loop mode. Closed-loop mode operation will automatically resume if the
CLK_DFLL48M_REF is restarted. An interrupt is generated on a zero-to-one transition on PCLKSR.DFLLRCS if the
DFLL Reference Clock Stopped bit (INTENSET.DFLLRCS) in the Interrupt Enable Set register is set.
15.6.7.2 Additional Features
Dealing with Delay in the DFLL in Closed-Loop Mode
The time from selecting a new CLK_DFLL48M frequency until this frequency is output by the DFLL48M can be up to
several microseconds. If the value in DFLLMUL.MUL is small, this can lead to instability in the DFLL48M locking
mechanism, which can prevent the DFLL48M from achieving locks. To avoid this, a chill cycle, during which the
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CLK_DFLL48M frequency is not measured, can be enabled. The chill cycle is enabled by default, but can be disabled by
writing a one to the DFLL Chill Cycle Disable bit (DFLLCTRL.CCDIS) in the DFLL Control register. Enabling chill cycles
might double the lock time.
Another solution to this problem consists of using less strict lock requirements. This is called Quick Lock (QL), which is
also enabled by default, but it can be disabled by writing a one to the Quick Lock Disable bit (DFLLCTRL.QLDIS) in the
DFLL Control register. The Quick Lock might lead to a larger spread in the output frequency than chill cycles, but the
average output frequency is the same.
USB Clock Recovery Mode
USB Clock Recovery mode can be used to create the 48MHz USB clock from the USB Start Of Frame (SOF). The mode
is enabled by writing a one to the USB Clock Recovery Mode bit in DFLL Control register (DFLLCTRL.USBCRM).
The SOF signal from USB device will be used as reference clock (CLK_DFLL_REF), ignoring the selected generic clock
reference. When the USB device is connected, a SOF will be sent every 1ms, thus DFLLMUL.MUL bits should be written
to 0xBB80 to obtain a 48MHz clock. In USB clock recovery mode, the DFLLCTRL.BPLCKC bit state is ignored and the
value stored in the DFLLVAL.COARSE will be used as COARSE final value. The lock procedure will also go
instantaneously to the fine lock search. The COARSE calibration value can be loaded from NVM OTP row by software.
DFLLCTRL.QLDIS bit must be cleared and DFLLCTRL.CCDIS should be set to speed up the lock phase. The
DFLLCTRL.STABLE bit state is ignored to let an auto jitter reduction mechanism working instead.
Wake from Sleep Modes
DFLL48M can optionally reset its lock bits when it is disabled. This is configured by the Lose Lock After Wake bit
(DFLLCTRL.LLAW) in the DFLL Control register. If DFLLCTRL.LLAW is zero, the DFLL48M will be re-enabled and start
running with the same configuration as before being disabled, even if the reference clock is not available. The locks will
not be lost. When the reference clock has restarted, the Fine tracking will quickly compensate for any frequency drift
during sleep if DFLLCTRL.STABLE is zero. If DFLLCTRL.LLAW is one when the DFLL is turned off, the DFLL48M will
lose all its locks, and needs to regain these through the full lock sequence.
Accuracy
There are three main factors that determine the accuracy of Fclkdfll48m. These can be tuned to obtain maximum accuracy
when fine lock is achieved.
z
Fine resolution: The frequency step between two Fine values. This is relatively smaller for high output frequencies.
z
Resolution of the measurement: If the resolution of the measured Fclkdfll48m is low, i.e., the ratio between the
CLK_DFLL48M frequency and the CLK_DFLL48M_REF frequency is small, then the DFLL48M might lock at a
frequency that is lower than the targeted frequency. It is recommended to use a reference clock frequency of
32kHz or lower to avoid this issue for low target frequencies.
z
The accuracy of the reference clock.
15.6.8 FDPLL96M – Fractional Digital Phase-Locked Loop Controller
15.6.8.1 Overview
The FDPLL96M controller allows flexible interface to the core digital function of the Digital Phase Locked Loop (DPLL).
The FDPLL96M integrates a digital filter with a proportional integral controller, a Time-to-Digital Converter (TDC), a test
mode controller, a Digitally Controlled Oscillator (DCO) and a PLL controller. It also provides a fractional multiplier of
frequency N between the input and output frequency.
The CLK_FDPLL96M_REF is the DPLL input clock reference. The selectable sources for the reference clock are
XOSC32K, XOSC and GCLK_DPLL. The path between XOSC and input multiplexer integrates a clock divider.
The selected clock must be configured and enabled before using the FDPLL96M. If the GCLK is selected as reference
clock, it must be configured and enabled in the Generic Clock Controller before using the FDPLL96M. Refer to “GCLK –
Generic Clock Controller” on page 90 for details.If the GCLK_DPLL is selected as the source for the
CLK_FDPLL96M_REF, care must be taken to make sure the source for this GCLK is within the valid frequency range for
the FDPLL96M.
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The XOSC source can be divided inside the FDPLL96M. The user must make sure that the programmable clock divider
and XOSC frequency provides a valid CLK_FDPLL96M_REF clock frequency that meets the FDPLL96M input frequency
range.
The output clock of the FDPLL96M is CLK_FDPLL96M. The state of the CLK_FDPLL96M clock only depends on the
FDPLL96M internal control of the final clock gater CG.
The FDPLL96M requires a 32kHz clock from the GCLK when the FDPLL96M internal lock timer is used. This clock must
be configured and enabled in the Generic Clock Controller before using the FDPLL96M. Refer to “GCLK – Generic Clock
Controller” on page 90 for details.
Table 15-3. Generic Clock Input for FDPLL96M
Generic Clock
FDPLL96M
FDPLL96M 32kHz clock
GCLK_DPLL_32K for internal lock timer
FDPLL96M
GCLK_DPLL for CLK_FDPLL96M_REF
15.6.8.2 Block Diagram
Figure 15-2. FDPLL96M Block Diagram
GCLK_DPLL_32K
XOSC32K
GCLK_DPLL
%JWJEFS
XOSC
CLK_FDPLL96M_REF
TDC
CK
Digital
Filter
DCO
$(
User
Interface
CLK_FDPLL96M
÷N
15.6.8.3 Principle of Operation
The task of the FDPLL96M is to maintain coherence between the input reference clock signal (CLK_FDPLL96M_REF)
and the respective output frequency CK via phase comparison. The FDPLL96M supports three independent sources of
clocks XOSC32K, XOSC and GCLK_DPLL. When the FDPLL96M is enabled, the relationship between the reference
clock (CLK_FDPLL96M_REF) frequency and the output clock (CLK_FDPLL96M) frequency is defined below.
LDRFRAC
f clk_fdpll96m = f clk_fdpll96m_ref × ⎛ LDR + 1 + ----------------------------⎞
⎝
⎠
16
Where LDR is the loop divider ratio integer part, LDRFRAC is the loop divider ratio fractional part, fckrx is the frequency of
the selected reference clock and fck is the frequency of the FDPLL96M output clock. As previously stated a clock divider
exist between XOSC and CLK_FDPLL96M_REF. The frequency between the two clocks is defined below.
1
f clk_fdpll96m_ref = f xosc × ⎛⎝ ----------------------------------⎞⎠
2 × ( DIV + 1 )
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When the FDPLL96M is disabled, the output clock is reset. If the loop divider ratio fractional part
(DPLLRATIO.LDRFRAC) field is reset, the FDPLL96M works in integer mode, otherwise the fractional mode is activated.
It shall be noted that fractional part has a negative impact on the jitter of the FDPLL96M.
Example (integer mode only): assuming fckr = 32kHz and fck = 48MHz, the multiplication ratio is 1500. It means that LDR
shall be set to 1499.
Example (fractional mode): assuming fckr = 32 kHz and fck = 48.006MHz, the multiplication ratio is 1500.1875 (1500 +
3/16). Thus LDR is set to 1499 and LDRFRAC to 3.
15.6.8.4 Initialization, Enabling, Disabling and Resetting
The FDPLL96M is enabled by writing a one to the Enable bit in the DPLL Control A register (DPLLCTRLA.ENABLE). The
FDPLL96M is disabled by writing a zero to DPLLCTRLA.ENABLE. The frequency of the FDPLL96M output clock CK is
stable when the module is enabled and when the DPLL Lock Status bit in the DPLL Status register
(DPLLSTATUS.LOCK) bit is set. When DPLLCTRLB.LTIME is different from 0, a user defined lock time is used to
validate the lock operation. In this case the lock time is constant. If DPLLCTRLB.LTIME is reset, the lock signal is linked
with the status bit of the DPLL, the lock time vary depending on the filter selection and final target frequency.
When DPLLCTRLB.WUF is set, the wake up fast mode is activated. In that mode the clock gating cell is enabled at the
end of the startup time. At that time, the final frequency is not stable as it is still in the acquisition period, but it allows to
save several milliseconds. After first acquisition, DPLLCTRLB.LBYPASS indicates if the Lock signal is discarded from
the control of the clock gater generating the output clock CLK_FDPLL96M.
Table 15-4. CLK_FDPLL96M behavior from startup to first edge detection.
WUF
LTIME
0
0
0
Not Equal To Zero
1
X
CLK_FDPLL96M Behavior
Normal Mode: First Edge when lock is asserted
Lock Timer Timeout mode: First Edge when the timer downcounts to 0.
Wake Up Fast Mode: First Edge when CK is active (startup time)
Table 15-5. CLK_FDPLL96M behavior after First Edge detection.
LBYPASS
CLK_FDPLL96M Behavior
0
Normal Mode: the CLK_FDPLL96M is turned off when lock signal is low.
1
Lock Bypass Mode: the CLK_FDPLL96M is always running, lock is irrelevant.
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Figure 15-3. CK and CLK_FDPLL96M Off Mode to Running Mode
CKRx
ENABLE
CK
CLK_FDPLL96M
LOCK
UTUBSUVQ@UJNF
UMPDL@UJNF
$,45"#-&
Figure 15-4. CK and CLK_FDPLL96M Off Mode to Running Mode when Wake-Up Fast is Activated
CKRx
ENABLE
CK
CLK_FDPLL96M
LOCK
UTUBSUVQ@UJNF
UMPDL@UJNF
$,45"#-&
Figure 15-5. CK and CLK_FDPLL96M Running Mode to Off Mode
CKRx
ENABLE
CK
CLK_FDPLL96M
LOCK
15.6.8.5 Reference Clock Switching
When a software operation requires reference clock switching, the normal operation is to disable the FDPLL96M, modify
the DPLLCTRLB.REFCLK to select the desired reference source and activate the FDPLL96M again.
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15.6.8.6 Loop Divider Ratio updates
The FDPLL96M supports on-the-fly update of the DPLLRATIO register, so it is allowed to modify the loop divider ratio
and the loop divider ratio fractional part when the FDPLL96M is enabled. At that time, the DPLLSTATUS.LOCK bit is
cleared and set again by hardware when the output frequency reached a stable state. The DPLL Lock Fail bit in the
Interrupt Flag Status and Clear register (INTFLAG.DPLLLCK) is set when a falling edge has been detected. The flag is
cleared when the software write a one to the interrupt flag bit location.
Figure 15-6. RATIOCTRL Register Update Operation
CKRx
LDR
LDRFRAC
mult0
mult1
CK
CLK_FDPLL96M
LOCK
LOCKL
15.6.8.7 Digital Filter Selection
The PLL digital filter (PI controller) is automatically adjusted in order to provide a good compromise between stability and
jitter. Nevertheless a software operation can override the filter setting using the DPLLCTRLB.FILTER field. The
DPLLCTRLB.LPEN field can be use to bypass the TDC module.
15.6.9 3.3V Brown-Out Detector Operation
The 3.3V BOD monitors the 3.3V VDDANA supply (BOD33). It supports continuous or sampling modes.
The threshold value action (reset the device or generate an interrupt), the Hysteresis configuration, as well as the
enable/disable settings are loaded from Flash User Calibration at startup, and can be overridden by writing to the
corresponding BOD33 register bit groups.
15.6.9.1 3.3V Brown-Out Detector (BOD33)
The 3.3V Brown-Out Detector (BOD33) monitors the VDDANA supply and compares the voltage with the brown-out
threshold level set in the BOD33 Level bit group (BOD33.LEVEL) in the BOD33 register. The BOD33 can generate either
an interrupt or a reset when VDDANA crosses below the brown-out threshold level. The BOD33 detection status can be
read from the BOD33 Detection bit (PCLKSR.BOD33DET) in the Power and Clocks Status register.
At startup or at power-on reset (POR), the BOD33 register values are loaded from the Flash User Row. Refer to “NVM
User Row Mapping” on page 25 for more details.
15.6.9.2 Continuous Mode
When the BOD33 Mode bit (BOD33.MODE) in the BOD33 register is written to zero and the BOD33 is enabled, the
BOD33 operates in continuous mode. In this mode, the BOD33 is continuously monitoring the VDDANA supply voltage.
Continuous mode is the default mode for BOD33.
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15.6.9.3 Sampling Mode
The sampling mode is a low-power mode where the BOD33 is being repeatedly enabled on a sampling clock’s ticks. The
BOD33 will monitor the supply voltage for a short period of time and then go to a low-power disabled state until the next
sampling clock tick.
Sampling mode is enabled by writing one to BOD33.MODE. The frequency of the clock ticks (Fclksampling) is controlled by
the BOD33 Prescaler Select bit group (BOD33.PSEL) in the BOD33 register.
F clkprescaler
F clksampling = -----------------------------2 ( PSEL + 1 )
The prescaler signal (Fclkprescaler) is a 1kHz clock, output from the32kHz Ultra Low Power Oscillator, OSCULP32K.
As the sampling mode clock is different from the APB clock domain, synchronization among the clocks is necessary.
Figure 15-7 shows a block diagram of the sampling mode. The BOD33Synchronization Ready bits (PCLKSR.B33SRDY)
in the Power and Clocks Status register show the synchronization ready status of the synchronizer. Writing attempts to
the BOD33 register are ignored while PCLKSR.B33SRDY is zero.
Figure 15-7. Sampling Mode Block diagram
USER INTERFACE
REGISTERS
(APB clock domain)
PSEL
CEN
PRESCALER
(clk_prescaler
domain)
SYNCHRONIZER
MODE
CLK_SAMPLING
ENABLE
CLK_APB
CLK_PRESCALER
The BOD33 Clock Enable bit (BOD33.CEN) in the BOD33 register should always be disabled before changing the
prescaler value. To change the prescaler value for the BOD33 during sampling mode, the following steps need to be
taken:
1. Wait until the PCLKSR.B33SRDY bit is set.
2. Write the selected value to the BOD33.PSEL bit group.
15.6.9.4 Hysteresis
The hysteresis functionality can be used in both continuous and sampling mode. Writing a one to the BOD33 Hysteresis
bit (BOD33.HYST) in the BOD33 register will add hysteresis to the BOD33 threshold level.
15.6.10 Voltage Reference System Operation
The Voltage Reference System (VREF) consists of a Bandgap Reference Voltage Generator and a temperature sensor.
The Bandgap Reference Voltage Generator is factory-calibrated under typical voltage and temperature conditions.
At reset, the VREF.CAL register value is loaded from Flash Factory Calibration.
The temperature sensor can be used to get an absolute temperature in the temperature range of CMIN to CMAX
degrees Celsius. The sensor will output a linear voltage proportional to the temperature. The output voltage and
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temperature range are located in the “Electrical Characteristics” on page 1055. To calculate the temperature from a
measured voltage, the following formula can be used:
Δtemperature
C MIN + ( Vmes – Vout MAX ) -----------------------------------Δvoltage
15.6.10.1 User Control of the Voltage Reference System
To enable the temperature sensor, write a one the Temperature Sensor Enable bit (VREF.TSEN) in the VREF register.
The temperature sensor can be redirected to the ADC for conversion. The Bandgap Reference Voltage Generator output
can also be routed to the ADC if the Bandgap Output Enable bit (VREF.BGOUTEN) in the VREF register is set.
The Bandgap Reference Voltage Generator output level is determined by the CALIB bit group (VREF.CALIB) value in the
VREF register.The default calibration value can be overridden by the user by writing to the CALIB bit group.
15.6.11 Internal Voltage Regulator System (VREG)
The embedded Voltage Regulator (VREG) is an internal voltage regulator that supplies the core and digital logic.
The regulator has two operating modes:
z
a normal operating mode: used when the CPU and peripherals are running
z
a low-power operating mode: used when the regulator draws small static current. By default, this mode is used in
standby sleep mode. It is possible to have the voltage regulator operate in normal mode when the chip is in
standby sleep mode: this is done by setting the VREG.RUNSTDBY bit.
The low-power operating mode has two possible configurations in standby sleep mode:
z
a low drive configuration, this is the default setting (the VREG.FORCELDO bit is cleared),
z
a high drive configuration: this setting is required for higher loads in standby sleep mode (case where several
modules are up despite the standby mode). To activate this configuration, the FORCELDO bit
(VREG.FORCELDO) in the VREG register must be set.
The internal voltage regulator system contains an internal brown-out detector(BOD12) on VDDCORE. BOD12 is
calibrated in production and its calibration configuration is stored in the NVM User Row. This configuration must not be
changed to assure the correct behavior of the BOD12. The BOD12 can generate either an interrupt or a reset when
VDDCORE crosses below the preset brown-out level. The BOD12 is always disabled in standby sleep mode.
15.6.12 DMA Operation
Not applicable.
15.6.13 Interrupts
The SYSCTRL has the following interrupt sources:
z
z
z
z
z
z
z
z
z
z
z
z
z
XOSCRDY - Multipurpose Crystal Oscillator Ready: A “0-to-1” transition on the PCLKSR.XOSCRDY bit is detected
XOSC32KRDY - 32kHz Crystal Oscillator Ready: A “0-to-1” transition on the PCLKSR.XOSC32KRDY bit is detected
OSC32KRDY - 32kHz Internal Oscillator Ready: A “0-to-1” transition on the PCLKSR.OSC32KRDY bit is detected
OSC8MRDY - 8MHz Internal Oscillator Ready: A “0-to-1” transition on the PCLKSR.OSC8MRDY bit is detected
DFLLRDY - DFLL48M Ready: A “0-to-1” transition on the PCLKSR.DFLLRDY bit is detected
DFLLOOB - DFLL48M Out Of Boundaries: A “0-to-1” transition on the PCLKSR.DFLLOOB bit is detected
DFLLLOCKF - DFLL48M Fine Lock: A “0-to-1” transition on the PCLKSR.DFLLLOCKF bit is detected
DFLLLOCKC - DFLL48M Coarse Lock: A “0-to-1” transition on the PCLKSR.DFLLLOCKC bit is detected
DFLLRCS - DFLL48M Reference Clock has Stopped: A “0-to-1” transition on the PCLKSR.DFLLRCS bit is detected
BOD33RDY - BOD33 Ready: A “0-to-1” transition on the PCLKSR.BOD33RDY bit is detected
BOD33DET - BOD33 Detection: A “0-to-1” transition on the PCLKSR.BOD33DET bit is detected. This is an
asynchronous interrupt and can be used to wake-up the device from any sleep mode.
B33SRDY - BOD33 Synchronization Ready: A “0-to-1” transition on the PCLKSR.B33SRDY bit is detected
PLL Lock (LOCK): Indicates that the DPLL Lock bit is asserted.
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z
z
PLL Lock Lost (LOCKL): Indicates that a falling edge has been detected on the Lock bit during normal operation mode.
PLL Lock Timer Timeout (LTTO): This interrupt flag indicates that the software defined time DPLLCTRLB.LTIME has
elapsed since the start of the FDPLL96M.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is
cleared, the interrupt is disabled, or the SYSCTRL is reset. See Interrupt Flag Status and Clear (INTFLAG) register for
details on how to clear interrupt flags.
All interrupt requests from the peripheral are ORed together on system level to generate one combined interrupt request
to the NVIC. Refer to “Nested Vector Interrupt Controller” on page 29 for details. The user must read the INTFLAG
register to determine which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to “Nested Vector Interrupt
Controller” on page 29 for details.
15.6.14 Synchronization
Due to the multiple clock domains, values in the DFLL48M control registers need to be synchronized to other clock
domains. The status of this synchronization can be read from the Power and Clocks Status register (PCLKSR). Before
writing to any of the DFLL48M control registers, the user must check that the DFLL Ready bit (PCLKSR.DFLLRDY) in
PCLKSR is set to one. When this bit is set, the DFLL48M can be configured and CLK_DFLL48M is ready to be used. Any
write to any of the DFLL48M control registers while DFLLRDY is zero will be ignored. An interrupt is generated on a zeroto-one transition of DFLLRDY if the DFLLRDY bit (INTENSET.DFLLDY) in the Interrupt Enable Set register is set.
In order to read from any of the DFLL48M configuration registers, the user must request a read synchronization by
writing a one to DFLLSYNC.READREQ. The registers can be read only when PCLKSR.DFLLRDY is set. If
DFLLSYNC.READREQ is not written before a read, a synchronization will be started, and the bus will be halted until the
synchronization is complete. Reading the DFLL48M registers when the DFLL48M is disabled will not halt the bus.
The prescaler counter used to trigger one-shot brown-out detections also operates asynchronously from the peripheral
bus. As a consequence, the prescaler registers require synchronization when written or read. The synchronization
results in a delay from when the initialization of the write or read operation begins until the operation is complete.
The write-synchronization is triggered by a write to the BOD33 control register. The Synchronization Ready bit
(PCLKSR.B33SRDY) in the PCLKSR register will be cleared when the write-synchronization starts and set when the
write-synchronization is complete. When the write-synchronization is ongoing (PCLKSR.B33SRDYis zero), an attempt to
do any of the following will cause the peripheral bus to stall until the synchronization is complete:
z
Writing to the BOD33control register
z
Reading the BOD33 control register that was written
The user can either poll PCLKSR.B33SRDY or use the INTENSET.B33SRDY interrupts to check when the
synchronization is complete. It is also possible to perform the next read/write operation and wait, as this next operation
will be completed after the ongoing read/write operation is synchronized.
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15.7
Register Summary
Table 15-6. Register Summary
Offset
Name
Bit
Pos.
0x00
7:0
DFLLLCKC
0x01
15:8
DPLLLCKR
0x02
INTENCLR
0x03
31:24
7:0
DFLLLCKC
15:8
DPLLLCKR
0x06
INTENSET
0x07
7:0
DFLLLCKC
15:8
DPLLLCKR
INTFLAG
0x0B
31:24
7:0
DFLLLCKC
15:8
DPLLLCKR
0x0D
PCLKSR
0x0F
0x11
XOSC
Reserved
0x13
Reserved
0x15
XOSC32K
0x16
Reserved
0x17
Reserved
0x18
0x19
0x1A
OSC32K
OSCULP32K
0x1D
...
0x1F
Reserved
0x20
OSC8M
0x23
0x24
0x25
DFLLRCS
DPLLLTO
DPLLLCKF
DFLLLCKF
DFLLOOB
DFLLRDY
OSC8MRDY
OSC32KRDY
XOSC32KRDY
XOSCRDY
B33SRDY
BOD33DET
BOD33RDY
DFLLRCS
DPLLLTO
DPLLLCKF
DFLLLCKF
DFLLOOB
DFLLRDY
OSC8MRDY
OSC32KRDY
XOSC32KRDY
XOSCRDY
B33SRDY
BOD33DET
BOD33RDY
DFLLRCS
DPLLLTO
DPLLLCKF
DFLLLCKF
DFLLOOB
DFLLRDY
OSC8MRDY
OSC32KRDY
XOSC32KRDY
XOSCRDY
B33SRDY
BOD33DET
BOD33RDY
DFLLRCS
DPLLLTO
DPLLLCKF
7:0
ONDEMAND
RUNSTDBY
15:8
7:0
XTALEN
STARTUP[3:0]
ONDEMAND
RUNSTDBY
AMPGC
AAMPEN
15:8
EN32K
GAIN[2:0]
XTALEN
WRTLOCK
ONDEMAND
ENABLE
STARTUP[2:0]
RUNSTDBY
EN32K
15:8
ENABLE
WRTLOCK
ENABLE
STARTUP[2:0]
CALIB[6:0]
23:16
31:24
0x1C
0x21
XOSCRDY
BOD33RDY
23:16
7:0
0x1B
0x22
XOSC32KRDY
BOD33DET
31:24
0x12
0x14
OSC32KRDY
B33SRDY
23:16
0x0C
0x10
OSC8MRDY
23:16
0x09
0x0E
DFLLRDY
31:24
0x08
0x0A
DFLLOOB
23:16
0x04
0x05
DFLLLCKF
7:0
WRTLOCK
7:0
ONDEMAND
0x26
Reserved
0x27
Reserved
RUNSTDBY
ENABLE
15:8
PRESC[1:0]
23:16
31:24
DFLLCTRL
CALIB[4:0]
7:0
15:8
CALIB[7:0]
FRANGE[1:0]
ONDEMAND
RUNSTDBY
CALIB[11:8]
USBCRM
LLAW
STABLE
MODE
ENABLE
WAITLOCK
BPLCKC
QLDIS
CCDIS
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Offset
Name
Bit
Pos.
0x28
7:0
0x29
15:8
0x2A
DFLLVAL
0x2B
FINE[7:0]
COARSE[5:0]
FINE[9:8]
23:16
DIFF[7:0]
31:24
DIFF[15:8]
0x2C
7:0
MUL[7:0]
0x2D
15:8
MUL[15:8]
0x2E
DFLLMUL
0x2F
23:16
0x30
DFLLSYNC
0x31
...
0x33
Reserved
7:0
0x34
7:0
0x35
15:8
0x36
BOD33
0x37
0x38
...
0x3B
0x3C
0x3D
VREG
0x3F
Reserved
RUNSTDBY
ACTION[1:0]
HYST
ENABLE
PSEL[3:0]
CEN
MODE
LEVEL[5:0]
7:0
7:0
15:8
VREF
0x43
RUNSTDBY
15:8
0x41
FORCELDO
BGOUTEN
23:16
DPLLCTRLA
0x45
...
0x47
Reserved
0x48
7:0
CALIB[10:8]
ONDEMAND
ENABLE
RUNSTDBY
7:0
0x49
DPLLRATIO
0x4B
TSEN
CALIB[7:0]
31:24
0x44
LDR[7:0]
15:8
LDR[11:8]
23:16
LDRFRAC[3:0]
31:24
0x4C
7:0
0x4D
15:8
DPLLCTRLB
0x4F
0x50
READREQ
23:16
0x40
0x4E
FSTEP[9:8]
Reserved
Reserved
0x4A
CSTEP[5:0]
31:24
0x3E
0x42
FSTEP[7:0]
31:24
23:16
REFCLK[1:0]
WUF
LPEN
LBYPASS
DIV[7:0]
31:24
DPLLSTATUS
7:0
FILTER[1:0]
LTIME[2:0]
DIV[10:8]
DIV
ENABLE
CLKRDY
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15.8
Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by
the Write-Protected property in each individual register description. Refer to “Register Access Protection” on page 146
and the “PAC – Peripheral Access Controller” on page 36 for details.
Some registers require synchronization when read and/or written. Synchronization is denoted by the Synchronized
property in each individual register description. Refer to “Synchronization” on page 159 for details.
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15.8.1 Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set register (INTENSET).
Name:
INTENCLR
Offset:
0x00
Reset:
0x00000000
Property:
Write-Protected
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DPLLLTO
DPLLLCKF
Access
R
R
R
R
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
B33SRDY
BOD33DET
BOD33RDY
DFLLRCS
DPLLLCKR
Access
R/W
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
DFLLLCKC
DFLLLCKF
DFLLOOB
DFLLRDY
OSC8MRDY
OSC32KRDY
XOSC32KRDY
XOSCRDY
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Access
Reset
z
Bits 31:18 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 17 – DPLLLTO: DPLL Lock Timeout Interrupt Enable
0: The DPLL Lock Timeout interrupt is disabled.
1: The DPLL Lock Timeout interrupt is enabled, and an interrupt request will be generated when the DPLL Lock
Timeout Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DPLL Lock Timeout Interrupt Enable bit, which disables the DPLL Lock Timeout interrupt.
z
Bit 16 – DPLLLCKF: DPLL Lock Fall Interrupt Enable
0: The DPLL Lock Fall interrupt is disabled.
1: The DPLL Lock Fall interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Fall
Interrupt flag is set.
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Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DPLL Lock Fall Interrupt Enable bit, which disables the DPLL Lock Fall
interrupt.
z
Bit 15 – DPLLLCKR: DPLL Lock Rise Interrupt Enable
0: The DPLL Lock Rise interrupt is disabled.
1: The DPLL Lock Rise interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Rise
Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DPLL Lock Rise Interrupt Enable bit, which disables the DPLL Lock Rise
interrupt.
z
Bits 14:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 11 – B33SRDY: BOD33 Synchronization Ready Interrupt Enable
0: The BOD33 Synchronization Ready interrupt is disabled.
1: The BOD33 Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the
BOD33 Synchronization Ready Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the BOD33 Synchronization Ready Interrupt Enable bit, which disables the
BOD33 Synchronization Ready interrupt.
z
Bit 10 – BOD33DET: BOD33 Detection Interrupt Enable
0: The BOD33 Detection interrupt is disabled.
1: The BOD33 Detection interrupt is enabled, and an interrupt request will be generated when the BOD33 Detection Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the BOD33 Detection Interrupt Enable bit, which disables the BOD33 Detection
interrupt.
z
Bit 9 – BOD33RDY: BOD33 Ready Interrupt Enable
0: The BOD33 Ready interrupt is disabled.
1: The BOD33 Ready interrupt is enabled, and an interrupt request will be generated when the BOD33 Ready
Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the BOD33 Ready Interrupt Enable bit, which disables the BOD33 Ready
interrupt.
z
Bit 8 – DFLLRCS: DFLL Reference Clock Stopped Interrupt Enable
0: The DFLL Reference Clock Stopped interrupt is disabled.
1: The DFLL Reference Clock Stopped interrupt is enabled, and an interrupt request will be generated when the
DFLL Reference Clock Stopped Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DFLL Reference Clock Stopped Interrupt Enable bit, which disables the DFLL
Reference Clock Stopped interrupt.
z
Bit 7 – DFLLLCKC: DFLL Lock Coarse Interrupt Enable
0: The DFLL Lock Coarse interrupt is disabled.
1: The DFLL Lock Coarse interrupt is enabled, and an interrupt request will be generated when the DFLL Lock
Coarse Interrupt flag is set.
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Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DFLL Lock Coarse Interrupt Enable bit, which disables the DFLL Lock Coarse
interrupt.
z
Bit 6 – DFLLLCKF: DFLL Lock Fine Interrupt Enable
0: The DFLL Lock Fine interrupt is disabled.
1: The DFLL Lock Fine interrupt is enabled, and an interrupt request will be generated when the DFLL Lock Fine
Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DFLL Lock Fine Interrupt Enable bit, which disables the DFLL Lock Fine
interrupt.
z
Bit 5 – DFLLOOB: DFLL Out Of Bounds Interrupt Enable
0: The DFLL Out Of Bounds interrupt is disabled.
1: The DFLL Out Of Bounds interrupt is enabled, and an interrupt request will be generated when the DFLL Out Of
Bounds Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DFLL Out Of Bounds Interrupt Enable bit, which disables the DFLL Out Of
Bounds interrupt.
z
Bit 4 – DFLLRDY: DFLL Ready Interrupt Enable
0: The DFLL Ready interrupt is disabled.
1: The DFLL Ready interrupt is enabled, and an interrupt request will be generated when the DFLL Ready Interrupt
flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the DFLL Ready Interrupt Enable bit, which disables the DFLL Ready interrupt.
z
Bit 3 – OSC8MRDY: OSC8M Ready Interrupt Enable
0: The OSC8M Ready interrupt is disabled.
1: The OSC8M Ready interrupt is enabled, and an interrupt request will be generated when the OSC8M Ready
Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the OSC8M Ready Interrupt Enable bit, which disables the OSC8M Ready
interrupt.
z
Bit 2 – OSC32KRDY: OSC32K Ready Interrupt Enable
0: The OSC32K Ready interrupt is disabled.
1: The OSC32K Ready interrupt is enabled, and an interrupt request will be generated when the OSC32K Ready
Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the OSC32K Ready Interrupt Enable bit, which disables the OSC32K Ready
interrupt.
z
Bit 1 – XOSC32KRDY: XOSC32K Ready Interrupt Enable
0: The XOSC32K Ready interrupt is disabled.
1: The XOSC32K Ready interrupt is enabled, and an interrupt request will be generated when the XOSC32K
Ready Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the XOSC32K Ready Interrupt Enable bit, which disables the XOSC32K Ready
interrupt.
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z
Bit 0 – XOSCRDY: XOSC Ready Interrupt Enable
0: The XOSC Ready interrupt is disabled.
1: The XOSC Ready interrupt is enabled, and an interrupt request will be generated when the XOSC Ready Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the XOSC Ready Interrupt Enable bit, which disables the XOSC Ready interrupt.
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15.8.2 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name:
INTENSET
Offset:
0x04
Reset:
0x00000000
Property:
Write-Protected
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DPLLLTO
DPLLLCKF
Access
R
R
R
R
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
B33SRDY
BOD33DET
BOD33RDY
DFLLRCS
DPLLLCKR
Access
R/W
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
DFLLLCKC
DFLLLCKF
DFLLOOB
DFLLRDY
OSC8MRDY
OSC32KRDY
XOSC32KRDY
XOSCRDY
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Access
Reset
z
Bits 31:18 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 17 – DPLLLTO: DPLL Lock Timeout Interrupt Enable
0: The DPLL Lock Timeout interrupt is disabled.
1: The DPLL Lock Timeout interrupt is enabled, and an interrupt request will be generated when the DPLL Lock
Timeout Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the DPLL Lock Timeout Interrupt Enable bit, which enables the DPLL Lock Timeout
interrupt.
z
Bit 16 – DPLLLCKF: DPLL Lock Fall Interrupt Enable
0: The DPLL Lock Fall interrupt is disabled.
1: The DPLL Lock Fall interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Fall
Interrupt flag is set.
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Writing a zero to this bit has no effect.
Writing a one to this bit will set the DPLL Lock Fall Interrupt Enable bit, which enables the DPLL Lock Fall interrupt.
z
Bit 15 – DPLLLCKR: DPLL Lock Rise Interrupt Enable
0: The DPLL Lock Rise interrupt is disabled.
1: The DPLL Lock Rise interrupt is enabled, and an interrupt request will be generated when the DPLL Lock Rise
Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the DPLL Lock Rise Interrupt Enable bit, which enables the DPLL Lock Rise
interrupt.
z
Bits 14:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 11 – B33SRDY: BOD33 Synchronization Ready Interrupt Enable
0: The BOD33 Synchronization Ready interrupt is disabled.
1: The BOD33 Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the
BOD33 Synchronization Ready Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the BOD33 Synchronization Ready Interrupt Enable bit, which enables the BOD33
Synchronization Ready interrupt.
z
Bit 10 – BOD33DET: BOD33 Detection Interrupt Enable
0: The BOD33 Detection interrupt is disabled.
1: The BOD33 Detection interrupt is enabled, and an interrupt request will be generated when the BOD33 Detection Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the BOD33 Detection Interrupt Enable bit, which enables the BOD33 Detection
interrupt.
z
Bit 9 – BOD33RDY: BOD33 Ready Interrupt Enable
0: The BOD33 Ready interrupt is disabled.
1: The BOD33 Ready interrupt is enabled, and an interrupt request will be generated when the BOD33 Ready
Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the BOD33 Ready Interrupt Enable bit, which enables the BOD33 Ready interrupt.
z
Bit 8 – DFLLRCS: DFLL Reference Clock Stopped Interrupt Enable
0: The DFLL Reference Clock Stopped interrupt is disabled.
1: The DFLL Reference Clock Stopped interrupt is enabled, and an interrupt request will be generated when the
DFLL Reference Clock Stopped Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the DFLL Reference Clock Stopped Interrupt Enable bit, which enables the DFLL
Reference Clock Stopped interrupt.
z
Bit 7 – DFLLLCKC: DFLL Lock Coarse Interrupt Enable
0: The DFLL Lock Coarse interrupt is disabled.
1: The DFLL Lock Coarse interrupt is enabled, and an interrupt request will be generated when the DFLL Lock
Coarse Interrupt flag is set.
Writing a zero to this bit has no effect.
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Writing a one to this bit will set the DFLL Lock Coarse Interrupt Enable bit, which enables the DFLL Lock Coarse
interrupt.
z
Bit 6 – DFLLLCKF: DFLL Lock Fine Interrupt Enable
0: The DFLL Lock Fine interrupt is disabled.
1: The DFLL Lock Fine interrupt is enabled, and an interrupt request will be generated when the DFLL Lock Fine
Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the DFLL Lock Fine Interrupt Disable/Enable bit, disable the DFLL Lock Fine interrupt and set the corresponding interrupt request.
z
Bit 5 – DFLLOOB: DFLL Out Of Bounds Interrupt Enable
0: The DFLL Out Of Bounds interrupt is disabled.
1: The DFLL Out Of Bounds interrupt is enabled, and an interrupt request will be generated when the DFLL Out Of
Bounds Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the DFLL Out Of Bounds Interrupt Enable bit, which enables the DFLL Out Of
Bounds interrupt.
z
Bit 4 – DFLLRDY: DFLL Ready Interrupt Enable
0: The DFLL Ready interrupt is disabled.
1: The DFLL Ready interrupt is enabled, and an interrupt request will be generated when the DFLL Ready Interrupt
flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the DFLL Ready Interrupt Enable bit, which enables the DFLL Ready interrupt and
set the corresponding interrupt request.
z
Bit 3 – OSC8MRDY: OSC8M Ready Interrupt Enable
0: The OSC8M Ready interrupt is disabled.
1: The OSC8M Ready interrupt is enabled, and an interrupt request will be generated when the OSC8M Ready
Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the OSC8M Ready Interrupt Enable bit, which enables the OSC8M Ready interrupt.
z
Bit 2 – OSC32KRDY: OSC32K Ready Interrupt Enable
0: The OSC32K Ready interrupt is disabled.
1: The OSC32K Ready interrupt is enabled, and an interrupt request will be generated when the OSC32K Ready
Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the OSC32K Ready Interrupt Enable bit, which enables the OSC32K Ready
interrupt.
z
Bit 1 – XOSC32KRDY: XOSC32K Ready Interrupt Enable
0: The XOSC32K Ready interrupt is disabled.
1: The XOSC32K Ready interrupt is enabled, and an interrupt request will be generated when the XOSC32K
Ready Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the XOSC32K Ready Interrupt Enable bit, which enables the XOSC32K Ready
interrupt.
z
Bit 0 – XOSCRDY: XOSC Ready Interrupt Enable
0: The XOSC Ready interrupt is disabled.
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1: The XOSC Ready interrupt is enabled, and an interrupt request will be generated when the XOSC Ready Interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the XOSC Ready Interrupt Enable bit, which enables the XOSC Ready interrupt.
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15.8.3 Interrupt Flag Status and Clear
Name:
INTFLAG
Offset:
0x08
Reset:
0x00000000
Property:
-
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DPLLLTO
DPLLLCKF
Access
R
R
R
R
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
B33SRDY
BOD33DET
BOD33RDY
DFLLRCS
DPLLLCKR
Access
R/W
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
DFLLLCKC
DFLLLCKF
DFLLOOB
DFLLRDY
OSC8MRDY
OSC32KRDY
XOSC32KRDY
XOSCRDY
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Access
Reset
Note:
Depending on the fuse settings, various bits of the INTFLAG register can be set to one at startup. Therefore the
user should clear those bits before using the corresponding interrupts.
z
Bits 31:18 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 17 – DPLLLTO: DPLL Lock Timeout
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DPLL Lock Timeout bit in the Status register (PCLKSR.DPLLLTO)
and will generate an interrupt request if INTENSET.DPLLLTO is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DPLL Lock Timeout interrupt flag.
z
Bit 16 – DPLLLCKF: DPLL Lock Fall
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DPLL Lock Fall bit in the Status register (PCLKSR.DPLLLCKF)
and will generate an interrupt request if INTENSET.DPLLLCKF is one.
Writing a zero to this bit has no effect.
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Writing a one to this bit clears the DPLL Lock Fall interrupt flag.
z
Bit 15 – DPLLLCKR: DPLL Lock Rise
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DPLL Lock Rise bit in the Status register (PCLKSR.DPLLLCKR)
and will generate an interrupt request if INTENSET.DPLLLCKR is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DPLL Lock Rise interrupt flag.
z
Bits 14:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 11 – B33SRDY: BOD33 Synchronization Ready
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the BOD33 Synchronization Ready bit in the Status register
(PCLKSR.B33SRDY) and will generate an interrupt request if INTENSET.B33SRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the BOD33 Synchronization Ready interrupt flag
z
Bit 10 – BOD33DET: BOD33 Detection
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the BOD33 Detection bit in the Status register (PCLKSR.BOD33DET)
and will generate an interrupt request if INTENSET.BOD33DET is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the BOD33 Detection interrupt flag.
z
Bit 9 – BOD33RDY: BOD33 Ready
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the BOD33 Ready bit in the Status register (PCLKSR.BOD33RDY)
and will generate an interrupt request if INTENSET.BOD33RDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the BOD33 Ready interrupt flag.
z
Bit 8 – DFLLRCS: DFLL Reference Clock Stopped
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DFLL Reference Clock Stopped bit in the Status register
(PCLKSR.DFLLRCS) and will generate an interrupt request if INTENSET.DFLLRCS is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DFLL Reference Clock Stopped interrupt flag.
z
Bit 7 – DFLLLCKC: DFLL Lock Coarse
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DFLL Lock Coarse bit in the Status register (PCLKSR.DFLLLCKC) and will generate an interrupt request if INTENSET.DFLLLCKC is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DFLL Lock Coarse interrupt flag.
z
Bit 6 – DFLLLCKF: DFLL Lock Fine
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DFLL Lock Fine bit in the Status register (PCLKSR.DFLLLCKF)
and will generate an interrupt request if INTENSET.DFLLLCKF is one.
Writing a zero to this bit has no effect.
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Writing a one to this bit clears the DFLL Lock Fine interrupt flag.
z
Bit 5 – DFLLOOB: DFLL Out Of Bounds
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DFLL Out Of Bounds bit in the Status register (PCLKSR.DFLLOOB) and will generate an interrupt request if INTENSET.DFLLOOB is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DFLL Out Of Bounds interrupt flag.
z
Bit 4 – DFLLRDY: DFLL Ready
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the DFLL Ready bit in the Status register (PCLKSR.DFLLRDY) and
will generate an interrupt request if INTENSET.DFLLRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DFLL Ready interrupt flag.
z
Bit 3 – OSC8MRDY: OSC8M Ready
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the OSC8M Ready bit in the Status register (PCLKSR.OSC8MRDY)
and will generate an interrupt request if INTENSET.OSC8MRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the OSC8M Ready interrupt flag.
z
Bit 2 – OSC32KRDY: OSC32K Ready
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the OSC32K Ready bit in the Status register (PCLKSR.OSC32KRDY)
and will generate an interrupt request if INTENSET.OSC32KRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the OSC32K Ready interrupt flag.
z
Bit 1 – XOSC32KRDY: XOSC32K Ready
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the XOSC32K Ready bit in the Status register
(PCLKSR.XOSC32KRDY) and will generate an interrupt request if INTENSET.XOSC32KRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the XOSC32K Ready interrupt flag.
z
Bit 0 – XOSCRDY: XOSC Ready
This flag is cleared by writing a one to it.
This flag is set on a zero-to-one transition of the XOSC Ready bit in the Status register (PCLKSR.XOSCRDY) and
will generate an interrupt request if INTENSET.XOSCRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the XOSC Ready interrupt flag.
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15.8.4 Power and Clocks Status
Name:
PCLKSR
Offset:
0x0C
Reset:
0x00000000
Property:
-
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DPLLLTO
DPLLLCKF
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
B33SRDY
BOD33DET
BOD33RDY
DFLLRCS
DPLLLCKR
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
DFLLLCKC
DFLLLCKF
DFLLOOB
DFLLRDY
OSC8MRDY
OSC32KRDY
XOSC32KRDY
XOSCRDY
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
z
Bits 31:18 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 17 – DPLLLTO: DPLL Lock Timeout
0: DPLL Lock time-out not detected.
1: DPLL Lock time-out detected.
z
Bit 16 – DPLLLCKF: DPLL Lock Fall
0: DPLL Lock fall edge not detected.
1: DPLL Lock fall edge detected.
z
Bit 15 – DPLLLCKR: DPLL Lock Rise
0: DPLL Lock rise edge not detected.
1: DPLL Lock fall edge detected.
z
Bits 14:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
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z
Bit 11 – B33SRDY: BOD33 Synchronization Ready
0: BOD33 synchronization is complete.
1: BOD33 synchronization is ongoing.
z
Bit 10 – BOD33DET: BOD33 Detection
0: No BOD33 detection.
1: BOD33 has detected that the I/O power supply is going below the BOD33 reference value.
z
Bit 9 – BOD33RDY: BOD33 Ready
0: BOD33 is not ready.
1: BOD33 is ready.
z
Bit 8 – DFLLRCS: DFLL Reference Clock Stopped
0: DFLL reference clock is running.
1: DFLL reference clock has stopped.
z
Bit 7 – DFLLLCKC: DFLL Lock Coarse
0: No DFLL coarse lock detected.
1: DFLL coarse lock detected.
z
Bit 6 – DFLLLCKF: DFLL Lock Fine
0: No DFLL fine lock detected.
1: DFLL fine lock detected.
z
Bit 5 – DFLLOOB: DFLL Out Of Bounds
0: No DFLL Out Of Bounds detected.
1: DFLL Out Of Bounds detected.
z
Bit 4 – DFLLRDY: DFLL Ready
0: The Synchronization is ongoing.
1: The Synchronization is complete.
This bit is cleared when the synchronization of registers between clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
z
Bit 3 – OSC8MRDY: OSC8M Ready
0: OSC8M is not ready.
1: OSC8M is stable and ready to be used as a clock source.
z
Bit 2 – OSC32KRDY: OSC32K Ready
0: OSC32K is not ready.
1: OSC32K is stable and ready to be used as a clock source.
z
Bit 1 – XOSC32KRDY: XOSC32K Ready
0: XOSC32K is not ready.
1: XOSC32K is stable and ready to be used as a clock source.
z
Bit 0 – XOSCRDY: XOSC Ready
0: XOSC is not ready.
1: XOSC is stable and ready to be used as a clock source.
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15.8.5 External Multipurpose Crystal Oscillator (XOSC) Control
Name:
XOSC
Offset:
0x10
Reset:
0x0080
Property:
Write-Protected
Bit
15
14
13
12
STARTUP[3:0]
Access
11
10
AMPGC
9
8
GAIN[2:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ONDEMAND
RUNSTDBY
XTALEN
ENABLE
R/W
R/W
R
R
R
R/W
R/W
R
1
0
0
0
0
0
0
0
Access
Reset
z
Bits 15:12 – STARTUP[3:0]: Start-Up Time
These bits select start-up time for the oscillator according to the table below.
The OSCULP32K oscillator is used to clock the start-up counter.
Table 15-7. Start-UpTime for External Multipurpose Crystal Oscillator
STARTUP[3:0]
Number of
OSCULP32K Clock
Cycles
Number of XOSC
Clock Cycles
Approximate Equivalent Time(1)(2)(3)
0x0
1
3
31µs
0x1
2
3
61µs
0x2
4
3
122µs
0x3
8
3
244µs
0x4
16
3
488µs
0x5
32
3
977µs
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Table 15-7. Start-UpTime for External Multipurpose Crystal Oscillator (Continued)
STARTUP[3:0]
Number of
OSCULP32K Clock
Cycles
Number of XOSC
Clock Cycles
Approximate Equivalent Time(1)(2)(3)
0x6
64
3
1953µs
0x7
128
3
3906µs
0x8
256
3
7813µs
0x9
512
3
15625µs
0xA
1024
3
31250µs
0xB
2048
3
62500µs
0xC
4096
3
125000µs
0xD
8192
3
250000µs
0xE
16384
3
500000µs
0xF
32768
3
1000000µs
Notes: 1.
z
Number of cycles for the start-up counter
2.
Number of cycles for the synchronization delay, before PCLKSR.XOSCRDY is set.
3.
Actual start-up time is n OSCULP32K cycles + 3 XOSC cycles, but given the time neglects the 3 XOSC
cycles.
Bit 11 – AMPGC: Automatic Amplitude Gain Control
0: The automatic amplitude gain control is disabled.
1: The automatic amplitude gain control is enabled. Amplitude gain will be automatically adjusted during Crystal
Oscillator operation.
z
Bits 10:8 – GAIN[2:0]: Oscillator Gain
These bits select the gain for the oscillator. The listed maximum frequencies are recommendations, and might vary
based on capacitive load and crystal characteristics. Setting this bit group has no effect when the Automatic Amplitude Gain Control is active.
Table 15-8. Oscillator Gain
GAIN[2:0]
0x0
2MHz
0x1
4MHz
0x2
8MHz
0x3
16MHz
0x4
30MHz
0x5-0x7
z
Recommended Max Frequency
Reserved
Bit 7 – ONDEMAND: On Demand Control
The On Demand operation mode allows an oscillator to be enabled or disabled, depending on peripheral clock
requests.
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In On Demand operation mode, i.e., if the XOSC.ONDEMAND bit has been previously written to one, the oscillator
will be running only when requested by a peripheral. If there is no peripheral requesting the oscillator s clock
source, the oscillator will be in a disabled state.
If On Demand is disabled, the oscillator will always be running when enabled.
In standby sleep mode, the On Demand operation is still active if the XOSC.RUNSTDBY bit is one. If
XOSC.RUNSTDBY is zero, the oscillator is disabled.
0: The oscillator is always on, if enabled.
1: The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. The oscillator is disabled if no peripheral is requesting the clock source.
z
Bit 6 – RUNSTDBY: Run in Standby
This bit controls how the XOSC behaves during standby sleep mode:
0: The oscillator is disabled in standby sleep mode.
1: The oscillator is not stopped in standby sleep mode. If XOSC.ONDEMAND is one, the clock source will be running when a peripheral is requesting the clock. If XOSC.ONDEMAND is zero, the clock source will always be
running in standby sleep mode.
z
Bits 5:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 2 – XTALEN: Crystal Oscillator Enable
This bit controls the connections between the I/O pads and the external clock or crystal oscillator:
0: External clock connected on XIN. XOUT can be used as general-purpose I/O.
1: Crystal connected to XIN/XOUT.
z
Bit 1 – ENABLE: Oscillator Enable
0: The oscillator is disabled.
1: The oscillator is enabled.
z
Bit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
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15.8.6 32kHz External Crystal Oscillator (XOSC32K) Control
Name:
XOSC32K
Offset:
0x14
Reset:
0x0080
Property:
Write-Protected
Bit
15
14
13
12
11
10
WRTLOCK
9
8
STARTUP[2:0]
Access
R
R
R
R/W
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ONDEMAND
RUNSTDBY
AAMPEN
EN32K
XTALEN
ENABLE
R/W
R/W
R/W
R
R/W
R/W
R/W
R
1
0
0
0
0
0
0
0
Access
Reset
z
Bits 15:13 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 12 – WRTLOCK: Write Lock
This bit locks the XOSC32K register for future writes to fix the XOSC32K configuration.
0: The XOSC32K configuration is not locked.
1: The XOSC32K configuration is locked.
z
Bit 11 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bits 10:8 – STARTUP[2:0]: Oscillator Start-Up Time
These bits select the start-up time for the oscillator according to Table 15-9.
The OSCULP32K oscillator is used to clock the start-up counter.
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Table 15-9. Start-Up Time for 32kHz External Crystal Oscillator
STARTUP[2:0]
Number of
OSCULP32K Clock
Cycles
Number of
XOSC32K Clock
Cycles
Approximate Equivalent Time
(OSCULP = 32kHz)(1)(2)(3)
0x0
1
3
122µs
0x1
32
3
1068µs
0x2
2048
3
62592µs
0x3
4096
3
125092µs
0x4
16384
3
500092µs
0x5
32768
3
1000092µs
0x6
65536
3
2000092µs
0x7
131072
3
4000092µs
Notes: 1.
z
Number of cycles for the start-up counter.
2.
Number of cycles for the synchronization delay, before PCLKSR.XOSC32KRDY is set.
3.
Start-up time is n OSCULP32K cycles + 3 XOSC32K cycles.
Bit 7 – ONDEMAND: On Demand Control
The On Demand operation mode allows an oscillator to be enabled or disabled depending on peripheral clock
requests.
In On Demand operation mode, i.e., if the ONDEMAND bit has been previously written to one, the oscillator will
only be running when requested by a peripheral. If there is no peripheral requesting the oscillator s clock source,
the oscillator will be in a disabled state.
If On Demand is disabled the oscillator will always be running when enabled.
In standby sleep mode, the On Demand operation is still active if the XOSC32K.RUNSTDBY bit is one. If
XOSC32K.RUNSTDBY is zero, the oscillator is disabled.
0: The oscillator is always on, if enabled.
1: The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. The oscillator is disabled if no peripheral is requesting the clock source.
z
Bit 6 – RUNSTDBY: Run in Standby
This bit controls how the XOSC32K behaves during standby sleep mode:
0: The oscillator is disabled in standby sleep mode.
1: The oscillator is not stopped in standby sleep mode. If XOSC32K.ONDEMAND is one, the clock source will be
running when a peripheral is requesting the clock. If XOSC32K.ONDEMAND is zero, the clock source will always
be running in standby sleep mode.
z
Bit 5 – AAMPEN: Automatic Amplitude Control Enable
0: The automatic amplitude control for the crystal oscillator is disabled.
1: The automatic amplitude control for the crystal oscillator is enabled.
z
Bit 4 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
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z
Bit 3 – EN32K: 32kHz Output Enable
0: The 32kHz output is disabled.
1: The 32kHz output is enabled.
z
Bit 2 – XTALEN: Crystal Oscillator Enable
This bit controls the connections between the I/O pads and the external clock or crystal oscillator:
0: External clock connected on XIN32. XOUT32 can be used as general-purpose I/O.
1: Crystal connected to XIN32/XOUT32.
z
Bit 1 – ENABLE: Oscillator Enable
0: The oscillator is disabled.
1: The oscillator is enabled.
z
Bit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
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15.8.7 32kHz Internal Oscillator (OSC32K) Control
Name:
OSC32K
Offset:
0x18
Reset:
0x003F0080
Property:
Write-Protected
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
CALIB[6:0]
Access
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
1
1
1
1
1
1
Bit
15
14
13
12
11
10
9
8
WRTLOCK
STARTUP[2:0]
Access
R
R
R
R/W
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ONDEMAND
RUNSTDBY
EN32K
ENABLE
R/W
R/W
R
R
R
R/W
R/W
R
1
0
0
0
0
0
0
0
Access
Reset
z
Bits 31:23 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 22:16 – CALIB[6:0]: Oscillator Calibration
These bits control the oscillator calibration.
This value must be written by the user.
Factory calibration values can be loaded from the non-volatile memory. Refer to “NVM Software Calibration Area
Mapping” on page 26.
z
Bits 15:13 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 12 – WRTLOCK: Write Lock
This bit locks the OSC32K register for future writes to fix the OSC32K configuration.
0: The OSC32K configuration is not locked.
1: The OSC32K configuration is locked.
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z
Bit 11 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bits 10:8 – STARTUP[2:0]: Oscillator Start-Up Time
These bits select start-up time for the oscillator according to Table 15-10.
The OSCULP32K oscillator is used as input clock to the startup counter.
Table 15-10. Start-Up Time for 32kHz Internal Oscillator
STARTUP[2:0]
Number of OSC32K
clock cycles
Approximate Equivalent Time
(OSCULP= 32 kHz)(1)(2)(3)
0x0
3
92µs
0x1
4
122µs
0x2
6
183µs
0x3
10
305µs
0x4
18
549µs
0x5
34
1038µs
0x6
66
2014µs
0x7
130
3967µs
Notes: 1.
z
Number of cycles for the start-up counter.
2.
Number of cycles for the synchronization delay, before PCLKSR.OSC32KRDY is set.
3.
Start-up time is n OSC32K cycles + 2 OSC32K cycles.
Bit 7 – ONDEMAND: On Demand Control
The On Demand operation mode allows an oscillator to be enabled or disabled depending on peripheral clock
requests.
In On Demand operation mode, i.e., if the ONDEMAND bit has been previously written to one, the oscillator will
only be running when requested by a peripheral. If there is no peripheral requesting the oscillator s clock source,
the oscillator will be in a disabled state.
If On Demand is disabled the oscillator will always be running when enabled.
In standby sleep mode, the On Demand operation is still active if the OSC32K.RUNSTDBY bit is one. If
OSC32K.RUNSTDBY is zero, the oscillator is disabled.
0: The oscillator is always on, if enabled.
1: The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. The oscillator is disabled if no peripheral is requesting the clock source.
z
Bit 6 – RUNSTDBY: Run in Standby
This bit controls how the OSC32K behaves during standby sleep mode:
0: The oscillator is disabled in standby sleep mode.
1: The oscillator is not stopped in standby sleep mode. If OSC32K.ONDEMAND is one, the clock source will be
running when a peripheral is requesting the clock. If OSC32K.ONDEMAND is zero, the clock source will always be
running in standby sleep mode.
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z
Bits 5:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bit 2 – EN32K: 32kHz Output Enable
0: The 32kHz output is disabled.
1: The 32kHz output is enabled.
z
Bit 1 – ENABLE: Oscillator Enable
0: The oscillator is disabled.
1: The oscillator is enabled.
z
Bit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
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15.8.8 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control
Name:
OSCULP32K
Offset:
0x1C
Reset:
0xXX
Property:
Write-Protected
Bit
7
6
5
4
3
WRTLOCK
Access
Reset
z
2
1
0
CALIB[4:0]
R/W
R
R
R/W
R/W
R/W
R/W
R/W
0
0
0
X
X
X
X
X
Bit 7 – WRTLOCK: Write Lock
This bit locks the OSCULP32K register for future writes to fix the OSCULP32K configuration.
0: The OSCULP32K configuration is not locked.
1: The OSCULP32K configuration is locked.
z
Bits 6:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 4:0 – CALIB[4:0]: Oscillator Calibration
These bits control the oscillator calibration.
These bits are loaded from Flash Calibration at startup.
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15.8.9 8MHz Internal Oscillator (OSC8M) Control
Name:
OSC8M
Offset:
0x20
Reset:
0xXXXX0382
Property:
Write-Protected
Bit
31
30
29
28
27
26
FRANGE[1:0]
Access
25
24
CALIB[11:8]
R/W
R/W
R
R
R/W
R/W
R/W
R/W
Reset
X
X
0
0
X
X
X
X
Bit
23
22
21
20
19
18
17
16
CALIB[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
PRESC[1:0]
Access
R
R
R
R
R
R
R/W
R/W
Reset
0
0
0
0
0
0
1
1
Bit
7
6
5
4
3
2
1
0
ONDEMAND
RUNSTDBY
R/W
R/W
R
R
R
R
R/W
R
1
0
0
0
0
0
1
0
Access
Reset
z
ENABLE
Bits 31:30 – FRANGE[1:0]: Oscillator Frequency Range
These bits control the oscillator frequency range according to the table below. These bits are loaded from Flash
Calibration at startup.
Table 15-11. Oscillator Frequency Range
FRANGE[1:0]
z
Description
0x0
4 to 6MHz
0x1
6 to 8MHz
0x2
8 to 11MHz
0x3
11 to 15MHz
Bits 29:28 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
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z
Bits 27:16 – CALIB[11:0]: Oscillator Calibration
These bits control the oscillator calibration. The calibration field is split in two:
CALIB[11:6] is for temperature calibration
CALIB[5:0] is for overall process calibration
These bits are loaded from Flash Calibration at startup.
z
Bits 15:10 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 9:8 – PRESC[1:0]: Oscillator Prescaler
These bits select the oscillator prescaler factor setting according to the table below.
Table 15-12. Oscillator Prescaler
PRESC[1:0]
z
Description
0x0
1
0x1
2
0x2
4
0x3
8
Bit 7 – ONDEMAND: On Demand Control
The On Demand operation mode allows an oscillator to be enabled or disabled depending on peripheral clock
requests.
In On Demand operation mode, i.e., if the ONDEMAND bit has been previously written to one, the oscillator will
only be running when requested by a peripheral. If there is no peripheral requesting the oscillator s clock source,
the oscillator will be in a disabled state.
If On Demand is disabled the oscillator will always be running when enabled.
In standby sleep mode, the On Demand operation is still active if the OSC8M.RUNSTDBY bit is one. If
OSC8M.RUNSTDBY is zero, the oscillator is disabled.
0: The oscillator is always on, if enabled.
1: The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. The oscillator is disabled if no peripheral is requesting the clock source.
z
Bit 6 – RUNSTDBY: Run in Standby
This bit controls how the OSC8M behaves during standby sleep mode:
0: The oscillator is disabled in standby sleep mode.
1: The oscillator is not stopped in standby sleep mode. If OSC8M.ONDEMAND is one, the clock source will be running when a peripheral is requesting the clock. If OSC8M.ONDEMAND is zero, the clock source will always be
running in standby sleep mode.
z
Bits 5:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 1 – ENABLE: Oscillator Enable
0: The oscillator is disabled or being enabled.
1: The oscillator is enabled or being disabled.
The user must ensure that the OSC8M is fully disabled before enabling it, and that the OSC8M is fully enabled
before disabling it by reading OSC8M.ENABLE.
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z
Bit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
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15.8.10 DFLL48M Control
Name:
DFLLCTRL
Offset:
0x24
Reset:
0x0080
Property:
Write-Protected, Write-Synchronized
Bit
15
14
13
12
11
10
9
8
WAITLOCK
BPLCKC
QLDIS
CCDIS
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ONDEMAND
RUNSTDBY
USBCRM
LLAW
STABLE
MODE
ENABLE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
1
0
0
0
0
0
0
0
Access
Reset
z
Bits 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 11 – WAITLOCK: Wait Lock
This bit controls the DFLL output clock, depending on lock status:
0: Output clock before the DFLL is locked.
1: Output clock when DFLL is locked.
z
Bit 10 – BPLCKC: Bypass Coarse Lock
This bit controls the coarse lock procedure:
0: Bypass coarse lock is disabled.
1: Bypass coarse lock is enabled.
z
Bit 9 – QLDIS: Quick Lock Disable
0: Quick Lock is enabled.
1: Quick Lock is disabled.
z
Bit 8 – CCDIS: Chill Cycle Disable
0: Chill Cycle is enabled.
1: Chill Cycle is disabled.
z
Bit 7 – ONDEMAND: On Demand Control
The On Demand operation mode allows an oscillator to be enabled or disabled depending on peripheral clock
requests.
In On Demand operation mode, i.e., if the ONDEMAND bit has been previously written to one, the oscillator will
only be running when requested by a peripheral. If there is no peripheral requesting the oscillator s clock source,
the oscillator will be in a disabled state.
If On Demand is disabled the oscillator will always be running when enabled.
In standby sleep mode, the On Demand operation is still active if the DFLLCTRL.RUNSTDBY bit is one. If
DFLLCTRL.RUNSTDBY is zero, the oscillator is disabled.
0: The oscillator is always on, if enabled.
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1: The oscillator is enabled when a peripheral is requesting the oscillator to be used as a clock source. The oscillator is disabled if no peripheral is requesting the clock source.
z
Bit 6 – RUNSTDBY: Run in Standby
This bit controls how the DFLL behaves during standby sleep mode:
0: The oscillator is disabled in standby sleep mode.
1: The oscillator is not stopped in standby sleep mode. If DFLLCTRL.ONDEMAND is one, the clock source will be
running when a peripheral is requesting the clock. If DFLLCTRL.ONDEMAND is zero, the clock source will always
be running in standby sleep mode.
z
Bit 5 – USBCRM: USB Clock Recovery Mode
0: USB Clock Recovery Mode is disabled.
1: USB Clock Recovery Mode is enabled.
z
Bit 4 – LLAW: Lose Lock After Wake
0: Locks will not be lost after waking up from sleep modes if the DFLL clock has been stopped.
1: Locks will be lost after waking up from sleep modes if the DFLL clock has been stopped.
z
Bit 3 – STABLE: Stable DFLL Frequency
0: FINE calibration tracks changes in output frequency.
1: FINE calibration register value will be fixed after a fine lock.
z
Bit 2 – MODE: Operating Mode Selection
0: The DFLL operates in open-loop operation.
1: The DFLL operates in closed-loop operation.
z
Bit 1 – ENABLE: DFLL Enable
0: The DFLL oscillator is disabled.
1: The DFLL oscillator is enabled.
Due to synchronization, there is delay from updating the register until the peripheral is enabled/disabled. The value
written to DFLLCTRL.ENABLE will read back immediately after written.
z
Bit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
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15.8.11 DFLL48M Value
Name:
DFLLVAL
Offset:
0x28
Reset:
0x00000000
Property:
Read-Synchronized, Write-Protected
Bit
31
30
29
28
27
26
25
24
DIFF[15:8]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DIFF[7:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
COARSE[5:0]
Access
FINE[9:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
FINE[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
z
Bits 31:16 – DIFF[15:0]: Multiplication Ratio Difference
In closed-loop mode (DFLLCTRL.MODE is written to one), this bit group indicates the difference between the ideal
number of DFLL cycles and the counted number of cycles. This value is not updated in open-loop mode, and
should be considered invalid in that case.
z
Bits 15:10 – COARSE[5:0]: Coarse Value
Set the value of the Coarse Calibration register. In closed-loop mode, this field is read-only.
z
Bits 9:0 – FINE[9:0]: Fine Value
Set the value of the Fine Calibration register. In closed-loop mode, this field is read-only.
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15.8.12 DFLL48M Multiplier
Name:
DFLLMUL
Offset:
0x2C
Reset:
0x00000000
Property:
Write-Protected
Bit
31
30
29
28
27
26
25
CSTEP[5:0]
Access
24
FSTEP[9:8]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
FSTEP[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
MUL[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
MUL[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
z
Bits 31:26 – CSTEP[5:0]: Coarse Maximum Step
This bit group indicates the maximum step size allowed during coarse adjustment in closed-loop mode. When
adjusting to a new frequency, the expected output frequency overshoot depends on this step size.
z
Bits 25:16 – FSTEP[9:0]: Fine Maximum Step
This bit group indicates the maximum step size allowed during fine adjustment in closed-loop mode. When adjusting to a new frequency, the expected output frequency overshoot depends on this step size.
z
Bits 15:0 – MUL[15:0]: DFLL Multiply Factor
This field determines the ratio of the CLK_DFLL output frequency to the CLK_DFLL_REF input frequency. Writing
to the MUL bits will cause locks to be lost and the fine calibration value to be reset to its midpoint.
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15.8.13 DFLL48M Synchronization
Name:
DFLLSYNC
Offset:
0x30
Reset:
0x00
Property:
Write-Protected
Bit
7
6
5
4
3
2
1
0
READREQ
Access
W
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
z
Bit 7 – READREQ: Read Request
To be able to read the current value of DFLLVAL in closed-loop mode, this bit should be written to one. The
updated value is available in DFLLVAL when PCLKSR.DFLLRDY is set.
z
Bits 6:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
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15.8.14 3.3V Brown-Out Detector (BOD33) Control
Name:
BOD33
Offset:
0x34
Reset:
0x00XX00XX
Property:
Write-Protected, Write-Synchronized
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
LEVEL[5:0]
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
CEN
MODE
PSEL[3:0]
Access
R/W
R/W
R/W
R/W
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
HYST
ENABLE
RUNSTDBY
ACTION[1:0]
Access
R
R/W
R
R/W
R/W
R/W
R/W
R
Reset
0
0
0
X
X
X
X
0
z
Bits 31:22 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 21:16 – LEVEL[5:0]: BOD33 Threshold Level
This field sets the triggering voltage threshold for the BOD33. See the “Electrical Characteristics” on page 1055 for
actual voltage levels. Note that any change to the LEVEL field of the BOD33 register should be done when the
BOD33 is disabled in order to avoid spurious resets or interrupts.
These bits are loaded from Flash User Row at startup. Refer to “NVM User Row Mapping” on page 25 for more
details.
z
Bits 15:12 – PSEL[3:0]: Prescaler Select
Selects the prescaler divide-by output for the BOD33 sampling mode according to the table below. The input clock
comes from the OSCULP32K 1kHz output.
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Table 15-13. Prescaler Select
PSEL[3:0]
Name
Description
0x0
DIV2
Divide clock by 2
0x1
DIV4
Divide clock by 4
0x2
DIV8
Divide clock by 8
0x3
DIV16
Divide clock by 16
0x4
DIV32
Divide clock by 32
0x5
DIV64
Divide clock by 64
0x6
DIV128
Divide clock by 128
0x7
DIV256
Divide clock by 256
0x8
DIV512
Divide clock by 512
0x9
DIV1K
Divide clock by 1024
0xA
DIV2K
Divide clock by 2048
0xB
DIV4K
Divide clock by 4096
0xC
DIV8K
Divide clock by 8192
0xD
DIV16K
Divide clock by 16384
0xE
DIV32K
Divide clock by 32768
0xF
DIV64K
Divide clock by 65536
z
Bits 11:10 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 9 – CEN: Clock Enable
0: The BOD33 sampling clock is either disabled and stopped, or enabled but not yet stable.
1: The BOD33 sampling clock is either enabled and stable, or disabled but not yet stopped.
Writing a zero to this bit will stop the BOD33 sampling clock.
Writing a one to this bit will start the BOD33 sampling clock.
z
Bit 8 – MODE: Operation Mode
0: The BOD33 operates in continuous mode.
1: The BOD33 operates in sampling mode.
z
Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bit 6 – RUNSTDBY: Run in Standby
0: The BOD33 is disabled in standby sleep mode.
1: The BOD33 is enabled in standby sleep mode.
z
Bit 5 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
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z
Bits 4:3 – ACTION[1:0]: BOD33 Action
These bits are used to select the BOD33 action when the supply voltage crosses below the BOD33 threshold.
These bits are loaded from Flash User Row at startup. Refer to “NVM User Row Mapping” on page 25 for more
details.
Table 15-14. BOD33 Action
ACTION[1:0]
Name
0x0
NONE
No action
0x1
RESET
The BOD33 generates a reset
0x2
INTERRUPT
0x3
z
Description
The BOD33 generates an interrupt
Reserved
Bit 2 – HYST: Hysteresis
This bit indicates whether hysteresis is enabled for the BOD33 threshold voltage:
0: No hysteresis.
1: Hysteresis enabled.
This bit is loaded from Flash User Row at startup. Refer to “NVM User Row Mapping” on page 25 for more details.
z
Bit 1 – ENABLE: Enable
0: BOD33 is disabled.
1: BOD33 is enabled.
This bit is loaded from Flash User Row at startup. Refer to “NVM User Row Mapping” on page 25 for more details.
z
Bit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
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15.8.15 Voltage Regulator System (VREG) Control
Name:
VREG
Offset:
0x3C
Reset:
0x0X00
Property:
Write-Protected
Bit
15
14
13
12
11
10
9
8
FORCELDO
Access
R
R
R/W
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RUNSTDBY
Access
R
R/W
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
z
Bits 15:14 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 13 – FORCELDO: Force LDO Voltage Regulator
0: The voltage regulator is in low power and low drive configuration in standby sleep mode.
1: The voltage regulator is in low power and high drive configuration in standby sleep mode.
z
Bits 12:7 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 6 – RUNSTDBY: Run in Standby
0: The voltage regulator is in low power configuration in standby sleep mode.
1: The voltage regulator is in normal configuration in standby sleep mode.
z
Bits 5:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
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15.8.16 Voltage References System (VREF) Control
Name:
VREF
Offset:
0x40
Reset:
0x0XXX0000
Property:
Write-Protected
Bit
31
30
29
28
27
26
25
24
CALIB[10:8]
Access
R
R
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
X
X
X
Bit
23
22
21
20
19
18
17
16
CALIB[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
X
X
X
X
X
X
X
X
Bit
15
14
13
12
11
10
9
8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
BGOUTEN
TSEN
Access
R
R
R
R
R
R/W
R/W
R
Reset
0
0
0
0
0
0
0
0
z
Bits 31:27 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 26:16 – CALIB[10:0]: Bandgap Voltage Generator Calibration
These bits are used to calibrate the output level of the bandgap voltage reference. These bits are loaded from
Flash Calibration Row at startup.
z
Bits 15:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 2 – BGOUTEN: Bandgap Output Enable
0: The bandgap output is not available as an ADC input channel.
1: The bandgap output is routed to an ADC input channel.
z
Bit 1 – TSEN: Temperature Sensor Enable
0: Temperature sensor is disabled.
1: Temperature sensor is enabled and routed to an ADC input channel.
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z
Bit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
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15.8.17 DPLL Control A
Name:
DPLLCTRLA
Offset:
0x44
Reset:
0x80
Property:
Write-Protected
Bit
Access
Reset
z
7
6
5
4
3
2
1
0
ONDEMAND
RUNSTDBY
R/W
R/W
R
R
R
R
R/W
R
1
0
0
0
0
0
0
0
ENABLE
Bit 7 – ONDEMAND: On Demand Clock Activation
0: The DPLL is always on when enabled.
1: The DPLL is activated only when a peripheral request the DPLL as a source clock. The DPLLCTRLA.ENABLE
bit must be one to validate that operation, otherwise the peripheral request has no effect.
z
Bit 6 – RUNSTDBY: Run in Standby
0: The DPLL is disabled in standby sleep mode.
1: The DPLL is not stopped in standby sleep mode.
z
Bits 5:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 1 – ENABLE: DPLL Enable
0: The DPLL is disabled.
1: The DPLL is enabled.
The software operation of enabling or disabling the DPLL takes a few clock cycles, so check the DPLLSTATUS.ENABLE status bit to identify when the DPLL is successfully activated or disabled.
z
Bit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
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15.8.18 DPLL Ratio Control
Name:
DPLLRATIO
Offset:
0x48
Reset:
0x00000000
Property:
Write-Protected
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
LDRFRAC[3:0]
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
LDR[11:8]
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
LDR[7:0]
Access
Reset
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
z
Bits 31:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 19:16 – LDRFRAC[3:0]: Loop Divider Ratio Fractional Part
Write this field with the fractional part of the frequency multiplier.
z
Bits 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 11:0 – LDR[11:0]: Loop Divider Ratio
Write this field with the integer part of the frequency multiplier.
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15.8.19 DPLL Control B
Name:
DPLLCTRLB
Offset:
0x4C
Reset:
0x00000000
Property:
Write-Protected
Bit
31
30
29
28
27
26
25
24
DIV[10:8]
Access
R
R
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
DIV[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
LBYPASS
LTIME[2:0]
Access
R
R
R
R/W
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
WUF
LPEN
REFCLK[1:0]
FILTER[1:0]
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
z
Bits 31:27 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 26:16 – DIV[10:0]: Clock Divider
These bits are used to set the XOSC clock source division factor. Refer to “Principle of Operation” on page 153.
z
Bits 15:13 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 12 – LBYPASS: Lock Bypass
0: Normal Mode: the CLK_FDPLL96M is turned off when lock signal is low.
1: Lock Bypass Mode: the CLK_FDPLL96M is always running, lock is irrelevant.
z
Bit 11 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
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z
Bits 10:8 – LTIME[2:0]: Lock Time
These bits select Lock Timeout.
Table 15-15. Lock Time
LTIME[2:0]
Name
0x0
DEFAULT
0x1-0x3
Description
No time-out
Reserved
0x4
8MS
Time-out if no lock within 8 ms
0x5
9MS
Time-out if no lock within 9 ms
0x6
10MS
Time-out if no lock within 10 ms
0x7
11MS
Time-out if no lock within 11 ms
z
Bits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 5:4 – REFCLK[1:0]: Reference Clock Selection
These bits select the CLK_FDPLL96M_REF source.
Table 15-16. Reference Clock Selection
REFCLK[1:0]
Name
0x0
XOSC32
0x1
XOSC
0x2
GCLK_DPLL
0x3
z
Description
XOSC32 clock reference
XOSC clock reference
GCLK_DPLL clock reference
Reserved
Bit 3 – WUF: Wake Up Fast
0: DPLL CK output is gated until complete startup time and lock time.
1: DPLL CK output is gated until startup time only.
z
Bit 2 – LPEN: Low-Power Enable
0: The time to digital converter is selected.
1: The time to digital converter is not selected, this will improve power consumption but increase the output jitter.
z
Bits 1:0 – FILTER[1:0]: Proportional Integral Filter Selection
These bits select the DPLL filter type.
Table 15-17. Proportional Integral Filter Selection
FILTER[1:0]
Name
Description
0x0
DEFAULT
0x1
LBFILT
Low bandwidth filter
0x2
HBFILT
High bandwidth filter
0x3
HDFILT
High damping filter
Default filter mode
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15.8.20 DPLL Status
Name:
DPLLSTATUS
Offset:
0x50
Reset:
0x00
Property:
-
Bit
7
6
5
4
3
2
1
0
DIV
ENABLE
CLKRDY
LOCK
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
z
Bits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 3 – DIV: Divider Enable
0: The reference clock divider is disabled.
1: The reference clock divider is enabled.
z
Bit 2 – ENABLE: DPLL Enable
0: The DPLL is disabled.
1: The DPLL is enabled.
z
Bit 1 – CLKRDY: Output Clock Ready
0: The DPLL output clock is off
1: The DPLL output clock in on.
z
Bit 0 – LOCK: DPLL Lock Status
0: The DPLL Lock signal is cleared.
1: The DPLL Lock signal is asserted.
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16.
WDT – Watchdog Timer
16.1
Overview
The Watchdog Timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover
from error situations such as runaway or deadlocked code. The WDT is configured to a predefined time-out period, and is
constantly running when enabled. If the WDT is not cleared within the time-out period, it will issue a system reset. An
early-warning interrupt is available to indicate an upcoming watchdog time-out condition.
The window mode makes it possible to define a time slot (or window) inside the total time-out period during which the
WDT must be cleared. If the WDT is cleared outside this window, either too early or too late, a system reset will be
issued. Compared to the normal mode, this can also catch situations where a code error causes the WDT to be cleared
frequently.
When enabled, the WDT will run in active mode and all sleep modes. It is asynchronous and runs from a CPUindependent clock source.The WDT will continue operation and issue a system reset or interrupt even if the main clocks
fail.
16.2
Features
z Issues a system reset if the Watchdog Timer is not cleared before its time-out period
z Early Warning interrupt generation
z Asynchronous operation from dedicated oscillator
z Two types of operation:
z
z
Normal mode
Window mode
z Selectable time-out periods, from 8 cycles to 16,000 cycles in normal mode or 16 cycles to 32,000 cycles in window
mode
z Always-on capability
16.3
Block Diagram
Figure 16-1. WDT Block Diagram
0xA5
0
CLEAR
GCLK_WDT
COUNT
PER/WINDOW/EWOFFSET
Early Warning Interrupt
Reset
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16.4
Signal Description
Not applicable.
16.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
16.5.1 I/O Lines
Not applicable.
16.5.2 Power Management
The WDT can continue to operate in any sleep mode where the selected source clock is running. The WDT interrupts
can be used to wake up the device from sleep modes. The events can trigger other operations in the system without
exiting sleep modes. Refer to “PM – Power Manager” on page 112 for details on the different sleep modes.
16.5.3 Clocks
The WDT bus clock (CLK_WDT_APB) is enabled by default, and can be enabled and disabled in the Power Manager.
Refer to “PM – Power Manager” on page 112 for details.
A generic clock (GCLK_WDT) is required to clock the WDT. This clock must be configured and enabled in the Generic
Clock Controller before using the WDT. Refer to “GCLK – Generic Clock Controller” on page 90 for details.
This generic clock is asynchronous to the user interface clock (CLK_WDT_APB). Due to this asynchronicity, accessing
certain registers will require synchronization between the clock domains. Refer to “Synchronization” on page 212 for
further details.
GCLK_WDT is intended to be sourced from the clock of the internal ultra-low-power (ULP) oscillator. Due to the ultralow-power design, the oscillator is not very accurate, and so the exact time-out period may vary from device to device.
This variation must be kept in mind when designing software that uses the WDT to ensure that the time-out periods used
are valid for all devices. For more information on ULP oscillator accuracy, consult the “Ultra Low Power Internal 32kHz
RC Oscillator (OSCULP32K) Characteristics” on page 1088.
GCLK_WDT can also be clocked from other sources if a more accurate clock is needed, but at the cost of higher power
consumption.
16.5.4 DMA
Not applicable.
16.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the WDT interrupts requires the Interrupt
Controller to be configured first. Refer to “Nested Vector Interrupt Controller” on page 29 for details.
16.5.6 Events
Not applicable.
16.5.7 Debug Operation
When the CPU is halted in debug mode, the WDT will halt normal operation. If the WDT is configured in a way that
requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result
during debugging. The WDT can be forced to halt operation during debugging.
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16.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the
following registers:
z
Interrupt Flag Status and Clear register (INTFLAG)
Write-protection is denoted by the Write-Protection property in the register description.
When the CPU is halted in debug mode, all write-protection is automatically disabled.
Write-protection does not apply for accesses through an external debugger. Refer to “PAC – Peripheral Access
Controller” on page 36 for details.
16.5.9 Analog Connections
Not applicable.
16.6
Functional Description
16.6.1 Principle of Operation
The Watchdog Timer (WDT) is a system for monitoring correct program operation, making it possible to recover from
error situations such as runaway code by issuing a reset. When enabled, the WDT is a constantly running timer that is
configured to a predefined time-out period. Before the end of the time-out period, the WDT should be reconfigured.
The WDT has two modes of operation, normal and window. Additionally, the user can enable Early Warning interrupt
generation in each of the modes. The description for each of the basic modes is given below. The settings in the Control
register (CTRL) and the Interrupt Enable register (INTENCLR/SET - refer to INTENCLR) determine the mode of
operation, as illustrated in Table 16-1.
The WDT operating modes are determined by settings of Enable bit in CTRL register (CTRL.ENABLE), Window Mode
Enable bit in CTRL register (CTRL.WEN) and Early Warning Interrupt Enable bit in INTENSET/INTENCLR registers
(INTENSET.EW/ EW.INTENCLR.EW)
Table 16-1. WDT Operating Modes
CTRL.ENABLE
CTRL.WEN
INTENSET.EW
Mode
0
x
x
Stopped
1
0
0
Normal
1
0
1
Normal with Early Warning interrupt
1
1
0
Window
1
1
1
Window with Early Warning interrupt
16.6.2 Basic Operation
16.6.2.1 Initialization
The following bits are enable-protected:
z
Window Mode Enable in the Control register (CTRL.WEN)
z
Always-On in the Control register (CTRL-ALWAYSON)
The following registers are enable-protected:
z
Configuration register (CONFIG)
z
Early Warning Interrupt Control register (EWCTRL)
Any writes to these bits or registers when the WDT is enabled or is being enabled (CTRL.ENABLE is one) will be
discarded. Writes to these registers while the WDT is being disabled will be completed after the disabling is complete.
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Enable-protection is denoted by the Enable-Protected property in the register description.
Initialization of the WDT can be done only while the WDT is disabled.
Normal Mode
z
Defining the required Time-Out Period bits in the Configuration register (CONFIG.PER).
Normal Mode with Early Warning interrupt
z
Defining the required Time-Out Period bits in the Configuration register (CONFIG.PER).
z
Defining Early Warning Interrupt Time Offset bits in the Early Warning Interrupt Control register (EWCTRL.
EWOFFSET).
z
Setting Early Warning Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.EW).
Window Mode
z
Defining Time-Out Period bits in the Configuration register (CONFIG.PER).
z
Defining Window Mode Time-Out Period bits in the Configuration register (CONFIG.WINDOW).
z
Setting Window Enable bit in the Control register (CTRL.WEN).
Window Mode with Early Warning interrupt
z
Defining Time-Out Period bits in the Configuration register (CONFIG.PER).
z
Defining Window Mode Time-Out Period bits in the Configuration register (CONFIG.WINDOW).
z
Setting Window Enable bit in the Control register (CTRL.WEN).
z
Defining Early Warning Interrupt Time Offset bits in the Early Warning Interrupt Control register (EWCTRL.
EWOFFSET).
z
Setting Early Warning Interrupt Enable bit in the Interrupt Enable Set register (INTENSET.EW).
16.6.2.2 Configurable Reset Values
On a power-on reset, some registers will be loaded with initial values from the NVM User Row. Refer to “NVM User Row
Mapping” on page 25 for more details.
This encompasses the following bits and bit groups:
z
Enable bit in the Control register (CTRL.ENABLE)
z
Always-On bit in the Control register (CTRL.ALWAYSON)
z
Watchdog Timer Windows Mode Enable bit in the Control register (CTRL.WEN)
z
Watchdog Timer Windows Mode Time-Out Period bits in the Configuration register (CONFIG.WINDOW)
z
Time-Out Period in the Configuration register (CONFIG.PER)
z
Early Warning Interrupt Time Offset bits in the Early Warning Interrupt Control register (EWCTRL.EWOFFSET)
For more information about fuse locations, see “NVM User Row Mapping” on page 25.
16.6.2.3 Enabling and Disabling
The WDT is enabled by writing a one to the Enable bit in the Control register (CTRL.ENABLE). The WDT is disabled by
writing a zero to CTRL.ENABLE.
The WDT can be disabled only while the Always-On bit in the Control register (CTRL.ALWAYSON) is zero.
16.6.2.4 Normal Mode
In normal-mode operation, the length of a time-out period is configured in CONFIG.PER. The WDT is enabled by writing
a one to the Enable bit in the Control register (CTRL.ENABLE). Once enabled, if the WDT is not cleared from the
application code before the time-out occurs, the WDT will issue a system reset. There are 12 possible WDT time-out
(TOWDT) periods, selectable from 8ms to 16s, and the WDT can be cleared at any time during the time-out period. A new
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WDT time-out period will be started each time the WDT is cleared by writing 0xA5 to the Clear register (CLEAR). Writing
any value other than 0xA5 to CLEAR will issue an immediate system reset.
By default, WDT issues a system reset upon a time-out, and the early warning interrupt is disabled. If an early warning
interrupt is required, the Early Warning Interrupt Enable bit in the Interrupt Enable register (INTENSET.EW) must be
enabled. Writing a one to the Early Warning Interrupt bit in the Interrupt Enable Set register (INTENSET.EW) enables the
interrupt, and writing a one to the Early Warning Interrupt bit in the Interrupt Enable Clear register (INTENCLR.EW)
disables the interrupt. If the Early Warning Interrupt is enabled, an interrupt is generated prior to a watchdog time-out
condition. In normal mode, the Early Warning Offset bits in the Early Warning Interrupt Control register
(EWCTRL.EWOFFSET) define the time where the early warning interrupt occurs. The normal-mode operation is
illustrated in Figure 16-2.
The Early Warning Offset bits define the number of GCLK_WDT clocks before the interrupt is generated, relative to the
start of the watchdog time-out period. For example, if the WDT is operating in normal mode with CONFIG.PER = 0x2 and
EWCTRL.EWOFFSET = 0x1, the Early Warning interrupt is generated 16 GCLK_WDT clock cycles from the start of the
watchdog time-out period, and the watchdog time-out system reset is generated 32 GCLK_WDT clock cycles from the
start of the watchdog time-out period. The user must take caution when programming the Early Warning Offset bits. If
these bits define an Early Warning interrupt generation time greater than the watchdog time-out period, the watchdog
time-out system reset is generated prior to the Early Warning interrupt. Thus, the Early Warning interrupt will never be
generated.
Figure 16-2. Normal-Mode Operation
System Reset
WDT Count
Timely WDT Clear
PER[3:0]=1
WDT Timeout
Early Warning Interrupt
EWOFFSET[3:0]=0
5
10
15
20
25
30
TOWDT
35
t [ms]
16.6.2.5 Window Mode
In window-mode operation, the WDT uses two different time-out periods, a closed window time-out period (TOWDTW) and
the normal, or open, time-out period (TOWDT). The closed window time-out period defines a duration from 8ms to 16s
where the WDT cannot be reset. If the WDT is cleared during this period, the WDT will issue a system reset. The normal
WDT time-out period, which is also from 8ms to 16s, defines the duration of the open period during which the WDT can
be cleared. The open period will always follow the closed period, and so the total duration of the time-out period is the
sum of the closed window and the open window time-out periods. The closed window is defined by the Window Period
bits in the Configuration register (CONFIG.WINDOW), and the open window is defined by the Period bits in the
Configuration register (CONFIG.PER).
By default, the WDT issues a system reset upon a time-out and the Early Warning interrupt is disabled. If an Early
Warning interrupt is required, INTENCLR/SET.EW must be set. Writing a one to INTENSET.EW enables the interrupt,
and writing a one to INTENCLR.EW disables the interrupt. If the Early Warning interrupt is enabled in window mode, the
interrupt is generated at the start of the open window period.
In a typical application where the system is in sleep mode, it can use this interrupt to wake up and clear the Watchdog
Timer, after which the system can perform other tasks or return to sleep mode.
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The window mode operation is illustrated in Figure 16-3.
Figure 16-3. Window-Mode Operation
WDT Count
Timely WDT Clear
Open
PER[3:0]=0
Early Warning Interrupt
Early WDT Clear
Closed
WINDOW[3:0]=0
WDT Timeout
5
10
15
20
TOWDTW
25
30
TOWDT
35
t [ms]
16.6.3 Additional Features
16.6.3.1 Always-On Mode
The always-on mode is enabled by writing a one to the Always-On bit in the Control register (CTRL.ALWAYSON). When
the always-on mode is enabled, the WDT runs continuously, regardless of the state of CTRL.ENABLE. Once written, the
Always-On bit can only be cleared by a power-on reset. The Configuration (CONFIG) and Early Warning Control
(EWCTRL) registers are read-only registers while the CTRL.ALWAYSON bit is set. Thus, the time period configuration
bits (CONFIG.PER, CONFIG.WINDOW, EWCTRL.EWOFFSET) of the WDT cannot be changed.
Enabling or disabling window-mode operation by writing the Window Enable bit (CTRL.WEN) is allowed while in the
always-on mode, but note that CONFIG.PER cannot be changed.
The Interrupt Clear and Interrupt Set registers are accessible in the always-on mode. The Early Warning interrupt can still
be enabled or disabled while in the always-on mode, but note that EWCTRL.EWOFFSET cannot be changed.
Table 16-2 shows the operation of the WDT when CTRL.ALWAYSON is set.
Table 16-2. WDT Operating Modes With Always-On
CTRL.WEN
INTENSET.EW
Mode
0
0
Always-on and normal mode
0
1
Always-on and normal mode with Early Warning interrupt
1
0
Always-on and window mode
1
1
Always-on and window mode with Early Warning interrupt
16.6.4 Interrupts
The WDT has the following interrupt sources:
z
Early Warning (EW): this is an asynchronous interrupt and can be used to wake-up the device from any sleep
mode.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the
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corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is
cleared, the interrupt is disabled or the WDT is reset. See INTFLAG for details on how to clear interrupt flags.
The WDT has one common interrupt request line for all the interrupt sources. The user must read INTFLAG to determine
which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to “Nested Vector Interrupt
Controller” on page 29 for details.
16.6.5 Synchronization
Due to the asynchronicity between CLK_WDT_APB and GCLK_WDT some registers must be synchronized when
accessed. A register can require:
z
Synchronization when written
z
Synchronization when read
z
Synchronization when written and read
z
No synchronization
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The Synchronization
Ready interrupt can be used to signal when synchronization is complete. This can be accessed via the Synchronization
Ready Interrupt Flag in the Interrupt Flag Status and Clear register (INTFLAG.SYNCRDY).
If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
The following registers need synchronization when written:
z
Control register (CTRL)
z
Clear register (CLEAR)
Write-synchronization is denoted by the Write-Synchronized property in the register description.
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16.7
Register Summary
Table 16-3. Register Summary
Offset
Name
Bit
Pos.
0x0
CTRL
7:0
0x1
CONFIG
7:0
0x2
EWCTRL
7:0
0x3
Reserved
ALWAYSON
WEN
WINDOW[3:0]
ENABLE
PER[3:0]
EWOFFSET[3:0]
0x4
INTENCLR
7:0
EW
0x5
INTENSET
7:0
EW
0x6
INTFLAG
7:0
EW
0x7
STATUS
7:0
0x8
CLEAR
7:0
SYNCBUSY
CLEAR[7:0]
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16.8
Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by
the Write-Protected property in each individual register description. Please refer to “Register Access Protection” on page
208 for details.
Some registers require synchronization when read and/or written. Synchronization is denoted by the Write-Synchronized
or the Read-Synchronized property in each individual register description. Please refer to “Synchronization” on page 212
for details.
Some registers are enable-protected, meaning they can be written only when the WDT is disabled. Enable-protection is
denoted by the Enable-Protected property in each individual register description.
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16.8.1 Control
Name:
CTRL
Offset:
0x0
Reset:
0xXX
Property:
Enable-Protected, Write-Protected, Write-Synchronized
Bit
7
6
5
4
3
ALWAYSON
Access
1
WEN
ENABLE
0
R/W
R
R
R
R
R/W
R/W
R
X
0
0
0
0
X
X
0
Reset
z
2
Bit 7 – ALWAYSON: Always-On
This bit allows the WDT to run continuously. After being written to one, this bit cannot be written to zero, and the
WDT will remain enabled until a power-on reset is received. When this bit is one, the Control register (CTRL), the
Configuration register (CONFIG) and the Early Warning Control register (EWCTRL) will be read-only, and any
writes to these registers are not allowed. Writing a zero to this bit has no effect.
0: The WDT is enabled and disabled through the ENABLE bit.
1: The WDT is enabled and can only be disabled by a power-on reset (POR).
This bit is not enable-protected.
This bit is loaded from NVM User Row at startup. Refer to “NVM User Row Mapping” on page 25 for more details.
z
Bits 6:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 2 – WEN: Watchdog Timer Window Mode Enable
This bit enables window mode.
This bit can only be written when CTRL.ENABLE is zero or CTRL.ALWAYSON is one:
z
When CTRL.ALWAYSON=0, this bit is enable-protected by CTRL.ENABLE.
z
When CTRL.ALWAYSON=1 this bit is not enable-protected by CTRL.ENABLE.
The initial value of this bit is loaded from Flash Calibration.
0: Window mode is disabled (normal operation).
1: Window mode is enabled.
This bit is loaded from NVM User Row at startup. Refer to “NVM User Row Mapping” on page 25 for more details.
z
Bit 1 – ENABLE: Enable
This bit enables or disables the WDT. Can only be written while CTRL.ALWAYSON is zero.
0: The WDT is disabled.
1: The WDT is enabled.
Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.
This bit is not enable-protected.
This bit is loaded from NVM User Row at startup. Refer to “NVM User Row Mapping” on page 25 for more details.
z
Bit 0 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
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16.8.2 Configuration
Name:
CONFIG
Offset:
0x1
Reset:
0xXX
Property:
Enable-Protected, Write-Protected, Write-Synchronized
Bit
7
6
5
4
3
2
WINDOW[3:0]
Access
Reset
z
1
0
PER[3:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
X
X
X
X
X
X
X
X
Bits 7:4 – WINDOW[3:0]: Window Mode Time-Out Period
In window mode, these bits determine the watchdog closed window period as a number of oscillator cycles. The
closed window periods are defined in Table 16-4.
These bits are loaded from NVM User Row at startup. Refer to “NVM User Row Mapping” on page 25 for more
details.
Table 16-4. Window Mode Time-Out Period
WINDOW[3:0]
0x0
8 clock cycles
0x1
16 clock cycles
0x2
32 clock cycles
0x3
64 clock cycles
0x4
128 clock cycles
0x5
256 clock cycles
0x6
512 clock cycles
0x7
1024 clock cycles
0x8
2048 clock cycles
0x9
4096 clock cycles
0xA
8192 clock cycles
0xB
16384 clock cycles
0xC-0xF
z
Description
Reserved
Bits 3:0 – PER[3:0]: Time-Out Period
These bits determine the watchdog time-out period as a number of GCLK_WDT clock cycles. In window mode
operation, these bits define the open window period. The different typical time-out periods are found in Table 16-5.
These bits are loaded from NVM User Row at startup. Refer to “NVM User Row Mapping” on page 25 for more
details.
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Table 16-5. Time-Out Period
PER[3:0]
Description
0x0
8 clock cycles
0x1
16 clock cycles
0x2
32 clock cycles
0x3
64 clock cycles
0x4
128 clock cycles
0x5
256 clock cycles
0x6
512 clock cycles
0x7
1024 clock cycles
0x8
2048 clock cycles
0x9
4096 clock cycles
0xA
8192 clock cycles
0xB
16384 clock cycles
0xC-0xF
Reserved
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16.8.3 Early Warning Interrupt Control
Name:
EWCTRL
Offset:
0x2
Reset:
0x0X
Property:
Enable-Protected, Write-Protected
Bit
7
6
5
4
3
2
1
0
EWOFFSET[3:0]
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
X
X
X
X
z
Bits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 3:0 – EWOFFSET[3:0]: Early Warning Interrupt Time Offset
These bits determine the number of GCLK_WDT clocks in the offset from the start of the watchdog time-out period
to when the Early Warning interrupt is generated. The Early Warning Offset is defined in Table 16-6. These bits
are loaded from NVM User Row at startup. Refer to “NVM User Row Mapping” on page 25 for more details.
Table 16-6. Early Warning Interrupt Time Offset
EWOFFSET[3:0]
Description
0x0
8 clock cycles
0x1
16 clock cycles
0x2
32 clock cycles
0x3
64 clock cycles
0x4
128 clock cycles
0x5
256 clock cycles
0x6
512 clock cycles
0x7
1024 clock cycles
0x8
2048 clock cycles
0x9
4096 clock cycles
0xA
8192 clock cycles
0xB
16384 clock cycles
0xC-0xF
Reserved
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16.8.4 Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set register (INTENSET).
Name:
INTENCLR
Offset:
0x4
Reset:
0x00
Property:
Write-Protected
Bit
7
6
5
4
3
2
1
0
EW
Access
R
R
R
R
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0
z
Bits 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 0 – EW: Early Warning Interrupt Enable
0: The Early Warning interrupt is disabled.
1: The Early Warning interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit disables the Early Warning interrupt.
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16.8.5 Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear register (INTENCLR).
Name:
INTENSET
Offset:
0x5
Reset:
0x00
Property:
Write-Protected
Bit
7
6
5
4
3
2
1
0
EW
Access
R
R
R
R
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0
z
Bits 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 0 – EW: Early Warning Interrupt Enable
0: The Early Warning interrupt is disabled.
1: The Early Warning interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit enables the Early Warning interrupt.
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16.8.6 Interrupt Flag Status and Clear
Name:
INTFLAG
Offset:
0x6
Reset:
0x00
Property:
-
Bit
7
6
5
4
3
2
1
0
EW
Access
R
R
R
R
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0
z
Bits 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 0 – EW: Early Warning
This flag is set when an Early Warning interrupt occurs, as defined by the EWOFFSET bit group in EWCTRL.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Early Warning interrupt flag.
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16.8.7 Status
Name:
STATUS
Offset:
0x7
Reset:
0x00
Property:
-
Bit
7
6
5
4
3
2
1
0
SYNCBUSY
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
z
Bit 7 – SYNCBUSY: Synchronization Busy
This bit is cleared when the synchronization of registers between clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
z
Bits 6:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
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16.8.8 Clear
Name:
CLEAR
Offset:
0x8
Reset:
0x00
Property:
Write-Protected, Write-Synchronized
Bit
7
6
5
4
3
2
1
0
CLEAR[7:0]
Access
W
W
W
W
W
W
W
W
Reset
0
0
0
0
0
0
0
0
z
Bits 7:0 – CLEAR[7:0]: Watchdog Clear
Writing 0xA5 to this register will clear the Watchdog Timer and the watchdog time-out period is restarted. Writing
any other value will issue an immediate system reset.
Table 16-7. Watchdog Clear
CLEAR[7:0]
Name
0x0-0xA4
0xA5
0xA6-0xFF
Description
Reserved
KEY
Clear Key
Reserved
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17.
17.1
RTC – Real-Time Counter
Overview
The Real-Time Counter (RTC) is a 32-bit counter with a 10-bit programmable prescaler that typically runs continuously to
keep track of time. The RTC can wake up the device from sleep modes using the alarm/compare wake up, periodic wake
up or overflow wake up mechanisms.
The RTC is typically clocked by the 1.024kHz output from the 32.768kHz High-Accuracy Internal Crystal
Oscillator(OSC32K) and this is the configuration optimized for the lowest power consumption. The faster 32.768kHz
output can be selected if the RTC needs a resolution higher than 1ms. The RTC can also be clocked from other sources,
selectable through the Generic Clock module (GCLK).
The RTC can generate periodic peripheral events from outputs of the prescaler, as well as alarm/compare interrupts and
peripheral events, which can trigger at any counter value. Additionally, the timer can trigger an overflow interrupt and
peripheral event, and be reset on the occurrence of an alarm/compare match. This allows periodic interrupts and
peripheral events at very long and accurate intervals.
The 10-bit programmable prescaler can scale down the clock source, and so a wide range of resolutions and time-out
periods can be configured. With a 32.768kHz clock source, the minimum counter tick interval is 30.5µs, and time-out
periods can range up to 36 hours. With the counter tick interval configured to 1s, the maximum time-out period is more
than 136 years.
17.2
Features
z 32-bit counter with 10-bit prescaler
z Multiple clock sources
z 32-bit or 16-bit Counter mode
z
One 32-bit or two 16-bit compare values
z Clock/Calendar mode
Time in seconds, minutes and hours (12/24)
Date in day of month, month and year
z Leap year correction
z
z
z Digital prescaler correction/tuning for increased accuracy
z Overflow, alarm/compare match and prescaler interrupts and events
z
17.3
Optional clear on alarm/compare match
Block Diagram
Figure 17-1. RTC Block Diagram (Mode 0 — 32-Bit Counter)
0
MATCHCLR
GCLK_RTC
10-bit
Prescaler
CLK_RTC_CNT
Overflow
COUNT
32
=
Periodic
Events
Compare n
32
COMPn
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Figure 17-2. RTC Block Diagram (Mode 1 — 16-Bit Counter)
0
GCLK_RTC
10-bit
Prescaler
CLK_RTC_CNT
COUNT
=
16
Overflow
16
Periodic
Events
PER
=
Compare n
16
COMPn
Figure 17-3. RTC Block Diagram (Mode 2 — Clock/Calendar)
0
MATCHCLR
GCLK_RTC
10-bit
Prescaler
CLK_RTC_CNT
32
Y/M/D H:M:S
32
Y/M/D H:M:S
=
MASKn
Periodic
Events
17.4
Overflow
CLOCK
Alarm n
ALARMn
Signal Description
Not applicable.
17.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
17.5.1 I/O Lines
Not applicable.
17.5.2 Power Management
The RTC can continue to operate in any sleep mode. The RTC interrupts can be used to wake up the device from sleep
modes. The events can trigger other operations in the system without exiting sleep modes. Refer to “PM – Power
Manager” on page 112 for details on the different sleep modes.
The RTC will be reset only at power-on (POR) or by writing a one to the Software Reset bit in the Control register
(CTRL.SWRST).
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17.5.3 Clocks
The RTC bus clock (CLK_RTC_APB) can be enabled and disabled in the Power Manager, and the default state of
CLK_RTC_APB can be found in the Peripheral Clock Masking section in the “PM – Power Manager” on page 112.
A generic clock (GCLK_RTC) is required to clock the RTC. This clock must be configured and enabled in the Generic
Clock Controller before using the RTC. Refer to “GCLK – Generic Clock Controller” on page 90 for details.
This generic clock is asynchronous to the user interface clock (CLK_RTC_APB). Due to this asynchronicity, accessing
certain registers will require synchronization between the clock domains. Refer to “Synchronization” on page 231 for
further details.
The RTC should never be used with the generic clock generator 0.
17.5.4 DMA
Not applicable.
17.5.5 Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the RTC interrupts requires the Interrupt
Controller to be configured first. Refer to “Nested Vector Interrupt Controller” on page 29 for details.
17.5.6 Events
To use the RTC event functionality, the corresponding events need to be configured in the event system. Refer to
“EVSYS – Event System” on page 400 for details.
17.5.7 Debug Operation
When the CPU is halted in debug mode the RTC will halt normal operation. The RTC can be forced to continue operation
during debugging. Refer to the Debug Control (DBGCTRL) register for details.
17.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the
following registers:
z
Interrupt Flag Status and Clear register ( INTFLAG)
z
Read Request register (READREQ)
z
Status register (STATUS)
z
Debug register (DBGCTRL)
Write-protection is denoted by the Write-Protection property in the register description.
When the CPU is halted in debug mode, all write-protection is automatically disabled.
Write-protection does not apply for accesses through an external debugger. Refer to “PAC – Peripheral Access
Controller” on page 36 for details.
17.5.9 Analog Connections
A 32.768kHz crystal can be connected to the XIN32 and XOUT32 pins, along with any required load capacitors. For
details on recommended crystal characteristics and load capacitors, refer to “Electrical Characteristics” on page 1055 for
details.
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17.6
Functional Description
17.6.1 Principle of Operation
The RTC keeps track of time in the system and enables periodic events, as well as interrupts and events at a specified
time. The RTC consists of a 10-bit prescaler that feeds a 32-bit counter. The actual format of the 32-bit counter depends
on the RTC operating mode.
17.6.2 Basic Operation
17.6.2.1 Initialization
The following bits are enable-protected, meaning that they can only be written when the RTC is disabled (CTRL.ENABLE
is zero):
z
Operating Mode bits in the Control register (CTRL.MODE)
z
Prescaler bits in the Control register (CTRL.PRESCALER)
z
Clear on Match bit in the Control register (CTRL.MATCHCLR)
z
Clock Representation bit in the Control register (CTRL.CLKREP)
The following register is enable-protected:
z
Event Control register (EVCTRL)
Any writes to these bits or registers when the RTC is enabled or being enabled (CTRL.ENABLE is one) will be discarded.
Writes to these bits or registers while the RTC is being disabled will be completed after the disabling is complete.
Enable-protection is denoted by the Enable-Protection property in the register description.
Before the RTC is enabled, it must be configured, as outlined by the following steps:
z
RTC operation mode must be selected by writing the Operating Mode bit group in the Control register
(CTRL.MODE)
z
Clock representation must be selected by writing the Clock Representation bit in the Control register
(CTRL.CLKREP)
z
Prescaler value must be selected by writing the Prescaler bit group in the Control register (CTRL.PRESCALER)
The RTC prescaler divides down the source clock for the RTC counter. The frequency of the RTC clock
(CLK_RTC_CNT) is given by the following formula:
f GCLK_RTC
f CLK_RTC_CNT = ---------------------------PRESCALER
2
The frequency of the generic clock, GCLK_RTC, is given by fGCLK_RTC, and fCLK_RTC_CNT is the frequency of the internal
prescaled RTC clock, CLK_RTC_CNT.
Note that in the Clock/Calendar mode, the prescaler must be configured to provide a 1Hz clock to the counter for correct
operation.
17.6.2.2 Enabling, Disabling and Resetting
The RTC is enabled by writing a one to the Enable bit in the Control register (CTRL.ENABLE). The RTC is disabled by
writing a zero to CTRL.ENABLE.
The RTC should be disabled before resetting it.
The RTC is reset by writing a one to the Software Reset bit in the Control register (CTRL.SWRST). All registers in the
RTC, except DBGCTRL, will be reset to their initial state, and the RTC will be disabled.
Refer to the CTRL register for details.
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17.6.3 Operating Modes
The RTC counter supports three RTC operating modes: 32-bit Counter, 16-bit Counter and Clock/Calendar. The
operating mode is selected by writing to the Operating Mode bit group in the Control register (CTRL.MODE).
17.6.3.1 32-Bit Counter (Mode 0)
When the RTC Operating Mode bits in the Control register (CTRL.MODE) are zero, the counter operates in 32-bit
Counter mode. The block diagram of this mode is shown in Figure 17-1. When the RTC is enabled, the counter will
increment on every 0-to-1 transition of CLK_RTC_CNT. The counter will increment until it reaches the top value of
0xFFFFFFFF, and then wrap to 0x00000000. This sets the Overflow interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG.OVF).
The RTC counter value can be read from or written to the Counter Value register (COUNT) in 32-bit format.
The counter value is continuously compared with the 32-bit Compare register (COMP0). When a compare match occurs,
the Compare 0interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMP0) is set on the next 0-to-1
transition of CLK_RTC_CNT.
If the Clear on Match bit in the Control register (CTRL.MATCHCLR) is one, the counter is cleared on the next counter
cycle when a compare match with COMP0 occurs. This allows the RTC to generate periodic interrupts or events with
longer periods than are possible with the prescaler events. Note that when CTRL.MATCHCLR is one, INTFLAG.CMP0
and INTFLAG.OVF will both be set simultaneously on a compare match with COMP0.
17.6.3.2 16-Bit Counter (Mode 1)
When CTRL.MODE is one, the counter operates in 16-bit Counter mode as shown in Figure 17-2. When the RTC is
enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. In 16-bit Counter mode, the 16-bit
Period register (PER) holds the maximum value of the counter. The counter will increment until it reaches the PER value,
and then wrap to 0x0000. This sets the Overflow interrupt flag in the Interrupt Flag Status and Clear register
(INTFLAG.OVF).
The RTC counter value can be read from or written to the Counter Value register (COUNT) in 16-bit format.
The counter value is continuously compared with the 16-bit Compare registers (COMPn, n=0–1). When a compare
match occurs, the Compare n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn, n=0–1) is set
on the next 0-to-1 transition of CLK_RTC_CNT.
17.6.3.3 Clock/Calendar (Mode 2)
When CTRL.MODE is two, the counter operates in Clock/Calendar mode, as shown in Figure 17-3. When the RTC is
enabled, the counter will increment on every 0-to-1 transition of CLK_RTC_CNT. The selected clock source and RTC
prescaler must be configured to provide a 1Hz clock to the counter for correct operation in this mode.
The time and date can be read from or written to the Clock Value register (CLOCK) in a 32-bit time/date format. Time is
represented as:
z
Seconds
z
Minutes
z
Hours
Hours can be represented in either 12- or 24-hour format, selected by the Clock Representation bit in the Control register
(CTRL.CLKREP). This bit can be changed only while the RTC is disabled.
Date is represented as:
z
Day as the numeric day of the month (starting at 1)
z
Month as the numeric month of the year (1 = January, 2 = February, etc.)
z
Year as a value counting the offset from a reference value that must be defined in software
The date is automatically adjusted for leap years, assuming every year divisible by 4 is a leap year. Therefore, the
reference value must be a leap year, e.g. 2000. The RTC will increment until it reaches the top value of 23:59:59
December 31st of year 63, and then wrap to 00:00:00 January 1st of year 0. This will set the Overflow interrupt flag in the
Interrupt Flag Status and Clear registers (INTFLAG.OVF).
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The clock value is continuously compared with the 32-bit Alarm register (ALARM0). When an alarm match occurs, the
Alarm 0 Interrupt flag in the Interrupt Flag Status and Clear registers (INTFLAG.ALARMn0) is set on the next 0-to-1
transition of CLK_RTC_CNT.
A valid alarm match depends on the setting of the Alarm Mask Selection bits in the Alarm 0 Mask register (MASK0.SEL).
These bits determine which time/date fields of the clock and alarm values are valid for comparison and which are
ignored.
If the Clear on Match bit in the Control register (CTRL.MATCHCLR) is one, the counter is cleared on the next counter
cycle when an alarm match with ALARM0 occurs. This allows the RTC to generate periodic interrupts or events with
longer periods than are possible with the prescaler events (see “Periodic Events” on page 229). Note that when
CTRL.MATCHCLR is one, INTFLAG.ALARM0 and INTFLAG.OVF will both be set simultaneously on an alarm match
with ALARM0.
17.6.4 Additional Features
17.6.4.1 Periodic Events
The RTC prescaler can generate events at periodic intervals, allowing flexible system tick creation. Any of the upper
eight bits of the prescaler (bits 2 to 9) can be the source of an event. When one of the Periodic Event Output bits in the
Event Control register (EVCTRL.PEREOn) is one, an event is generated on the 0-to1 transition of the related bit in the
prescaler, resulting in a periodic event frequency of:
f PERIODIC =
f GCLK _ RTC
2 n +3
fGCLK_RTC is the frequency of the internal prescaler clock, GCLK_RTC, and n is the position of the EVCTRL.PEREOn bit.
For example, PEREO will generate an event every 8 GCLK_RTC cycles, PEREO1 every 16 cycles, etc. This is shown in
Figure 17-4. Periodic events are independent of the prescaler setting used by the RTC counter, except if
CTRL.PRESCALER is zero. Then, no periodic events will be generated.
Figure 17-4. Example Periodic Events
GCLK_RTC
PEREO0
PEREO1
PEREO2
PEREO3
PEREO4
17.6.4.2 Frequency Correction
The RTC Frequency Correction module employs periodic counter corrections to compensate for a too-slow or too-fast
oscillator. Frequency correction requires that CTRL.PRESCALER is greater than 1.
The digital correction circuit adds or subtracts cycles from the RTC prescaler to adjust the frequency in approximately
1PPM steps. Digital correction is achieved by adding or skipping a single count in the prescaler once every 1024
GCLK_RTC cycles. The Value bit group in the Frequency Correction register (FREQCORR.VALUE) determines the
number of times the adjustment is applied over 976 of these periods. The resulting correction is as follows:
6
FREQCORR.VALUE
Correction in PPM = ----------------------------------------------------- ⋅ 10 PPM
1024 ⋅ 976
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This results in a resolution of 1.0006PPM.
The Sign bit in the Frequency Correction register (FREQCORR.SIGN) determines the direction of the correction. A
positive value will speed up the frequency, and a negative value will slow down the frequency.
Digital correction also affects the generation of the periodic events from the prescaler. When the correction is applied at
the end of the correction cycle period, the interval between the previous periodic event and the next occurrence may also
be shortened or lengthened depending on the correction value.
17.6.5 DMA Operation
Not applicable.
17.6.6 Interrupts
The RTC has the following interrupt sources:
z
Overflow (INTFLAG.OVF): this is an asynchronous interrupt and can be used to wake-up the device from any
sleep mode.
z
Compare n (INTFLAG.CMPn): this is an asynchronous interrupt and can be used to wake-up the device from any
sleep mode.
z
Alarm n (INTFLAG.ALARMn): this is an asynchronous interrupt and can be used to wake-up the device from any
sleep mode.
z
Synchronization Ready (INTFLAG.SYNCRDY): this is an asynchronous interrupt and can be used to wake-up the
device from any sleep mode.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is
cleared, the interrupt is disabled or the RTC is reset. See INTFLAG for details on how to clear interrupt flags. The RTC
has one common interrupt request line for all the interrupt sources. The user must read INTFLAG to determine which
interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to “Nested Vector Interrupt
Controller” on page 29 for details.
17.6.7 Events
The RTC can generate the following output events, which are generated in the same way as the corresponding
interrupts:
z
Overflow (OVF)
z
Period n (PERn)
z
Compare n (CMPn)
z
Alarm n (ALARMn)
Output events must be enabled to be generated. Writing a one to an Event Output bit in the Event Control register
(EVCTRL.xxEO) enables the corresponding output event. Writing a zero to this bit disables the corresponding output
event. Refer to “EVSYS – Event System” on page 400 for details.
17.6.8 Sleep Mode Operation
The RTC will continue to operate in any sleep mode where the source clock is active. The RTC interrupts can be used to
wake up the device from a sleep mode, or the RTC events can trigger other operations in the system without exiting the
sleep mode.
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An interrupt request will be generated after the wake-up if the Interrupt Controller is configured accordingly. Otherwise
the CPU will wake up directly, without triggering an interrupt. In this case, the CPU will continue executing from the
instruction following the entry into sleep.
The periodic events can also wake up the CPU through the interrupt function of the Event System. In this case, the event
must be enabled and connected to an event channel with its interrupt enabled. See “EVSYS – Event System” on page
400 for more information.
17.6.9 Synchronization
Due to the asynchronicity between CLK_RTC_APB and GCLK_RTC some registers must be synchronized when
accessed. A register can require:
z
Synchronization when written
z
Synchronization when read
z
Synchronization when written and read
z
No synchronization
When executing an operation that requires synchronization, the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set immediately, and cleared when synchronization is complete. The Synchronization
Ready interrupt can be used to signal when synchronization is complete. This can be accessed via the Synchronization
Ready Interrupt Flag in the Interrupt Flag Status and Clear register (INTFLAG.SYNCRDY).
If an operation that requires synchronization is executed while STATUS.SYNCBUSY is one, the bus will be stalled. All
operations will complete successfully, but the CPU will be stalled and interrupts will be pending as long as the bus is
stalled.
The following bits need synchronization when written:
z
Software Reset bit in the Control register (CTRL.SWRST)
z
Enable bit in the Control register (CTRL.ENABLE)
The following registers need synchronization when written:
z
The Counter Value register (COUNT)
z
The Clock Value register (CLOCK)
z
The Counter Period register (PER)
z
The Compare n Value registers (COMPn)
z
The Alarm n Value registers (ALARMn)
z
The Frequency Correction register (FREQCORR)
z
The Alarm n Mask register (MASKn)
Write-synchronization is denoted by the Write-Synchronization property in the register description.
The following registers need synchronization when read:
z
The Counter Value register (COUNT)
z
The Clock Value register (CLOCK)
Read-synchronization is denoted by the Read-Synchronization property in the register description.
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17.7
Register Summary
The register mapping depends on the Operating Mode bits in the Control register (CTRL.MODE). The register summary
is presented for each of the three modes.
Table 17-1. MODE0 - Mode Register Summary
Offset
0x00
0x01
0x02
0x03
0x04
0x05
Name
CTRL
READREQ
EVCTRL
Bit
Pos.
7:0
MATCHCLR
MODE[1:0]
ENABLE
SWRST
PRESCALER[3:0]
15:8
ADDR[5:0]
7:0
15:8
RREQ
RCONT
PEREO6
7:0
PEREO7
15:8
OVFEO
PEREO5
PEREO4
PEREO3
PEREO2
PEREO1
PEREO0
CMPEO0
0x06
INTENCLR
7:0
OVF
SYNCRDY
CMP0
0x07
INTENSET
7:0
OVF
SYNCRDY
CMP0
0x08
INTFLAG
7:0
OVF
SYNCRDY
CMP0
0x09
Reserved
0x0A
STATUS
7:0
SYNCBUSY
0x0B
DBGCTRL
7:0
0x0C
FREQCORR
7:0
0x0D
...
0x0F
Reserved
DBGRUN
SIGN
VALUE[6:0]
0x10
7:0
COUNT[7:0]
0x11
15:8
COUNT[15:8]
23:16
COUNT[23:16]
31:24
COUNT[31:24]
7:0
COMP[7:0]
0x12
COUNT
0x13
0x14
...
0x17
Reserved
0x18
0x19
0x1A
COMP0
0x1B
15:8
COMP[15:8]
23:16
COMP[23:16]
31:24
COMP[31:24]
Table 17-2. MODE1 - Mode Register Summary
Offset
0x00
0x01
0x02
0x03
0x04
0x05
Name
CTRL
READREQ
EVCTRL
Bit
Pos.
7:0
MODE[1:0]
ENABLE
SWRST
PRESCALER[3:0]
15:8
ADDR[5:0]
7:0
15:8
RREQ
RCONT
PEREO6
7:0
PEREO7
15:8
OVFEO
PEREO5
PEREO4
PEREO3
PEREO2
PEREO1
PEREO0
CMPEO1
CMPEO0
0x06
INTENCLR
7:0
OVF
SYNCRDY
CMP1
CMP0
0x07
INTENSET
7:0
OVF
SYNCRDY
CMP1
CMP0
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Offset
Name
Bit
Pos.
0x08
INTFLAG
7:0
OVF
SYNCBUSY
0x09
Reserved
0x0A
STATUS
7:0
0x0B
DBGCTRL
7:0
0x0C
FREQCORR
7:0
0x0D
...
0x0F
Reserved
0x10
0x11
COUNT
0x12
Reserved
0x13
Reserved
0x14
0x15
PER
0x16
Reserved
0x17
Reserved
0x18
0x19
0x1A
0x1B
COMP0
COMP1
SYNCRDY
CMP1
CMP0
DBGRUN
SIGN
VALUE[6:0]
7:0
COUNT[7:0]
15:8
COUNT[15:8]
7:0
PER[7:0]
15:8
PER[15:8]
7:0
COMP[7:0]
15:8
COMP[15:8]
7:0
COMP[7:0]
15:8
COMP[15:8]
Table 17-3. MODE2 - Mode Register Summary
Offset
0x00
0x01
0x02
0x03
0x04
0x05
Name
CTRL
READREQ
EVCTRL
Bit
Pos.
7:0
MATCHCLR
CLKREP
MODE[1:0]
ENABLE
SWRST
PRESCALER[3:0]
15:8
ADDR[5:0]
7:0
15:8
RREQ
RCONT
7:0
PEREO7
PEREO6
PEREO5
PEREO4
PEREO3
PEREO2
PEREO1
PEREO0
15:8
OVFEO
0x06
INTENCLR
7:0
OVF
SYNCRDY
ALARM0
0x07
INTENSET
7:0
OVF
SYNCRDY
ALARM0
0x08
INTFLAG
7:0
OVF
SYNCRDY
ALARM0
0x09
Reserved
0x0A
STATUS
7:0
SYNCBUSY
0x0B
DBGCTRL
7:0
0x0C
FREQCORR
7:0
0x0D
...
0x0F
Reserved
0x10
0x11
0x12
0x13
7:0
CLOCK
ALARMEO0
DBGRUN
SIGN
MINUTE[1:0]
15:8
23:16
31:24
VALUE[6:0]
SECOND[5:0]
HOUR[3:0]
MINUTE[5:2]
MONTH[1:0]
DAY[4:0]
YEAR[5:0]
HOUR[4]
MONTH[3:2]
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Offset
Name
0x14
...
0x17
Reserved
0x18
0x19
0x1A
7:0
ALARM0
0x1B
0x1C
Bit
Pos.
15:8
23:16
31:24
MASK
MINUTE[1:0]
7:0
SECOND[5:0]
HOUR[3:0]
MINUTE[5:2]
MONTH[1:0]
DAY[4:0]
YEAR[5:0]
HOUR[4]
MONTH[3:2]
SEL[2:0]
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17.8
Register Description
Registers can be 8, 16 or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by
the Write-Protected property in each individual register description. Please refer to “Register Access Protection” on page
226 for details.
Some registers require synchronization when read and/or written. Synchronization is denoted by the Write-Synchronized
or the Read-Synchronized property in each individual register description. Please refer to “Synchronization” on page 231
for details.
Some registers are enable-protected, meaning they can only be written when the RTC is disabled. Enable-protection is
denoted by the Enable-Protected property in each individual register description.
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17.8.1 Control - MODE0
Name:
CTRL
Offset:
0x00
Reset:
0x0000
Property:
Enable-Protected, Write-Protected, Write-Synchronized
Bit
15
14
13
12
11
10
9
8
PRESCALER[3:0]
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ENABLE
SWRST
MATCHCLR
Access
Reset
MODE[1:0]
R/W
R
R
R
R/W
R/W
R/W
W
0
0
0
0
0
0
0
0
z
Bits 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 11:8 – PRESCALER[3:0]: Prescaler
These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock
(CLK_RTC_CNT).
These bits are not synchronized.
Table 17-4. Prescaler
PRESCALER[3:0]
Name
0x0
DIV1
CLK_RTC_CNT = GCLK_RTC/1
0x1
DIV2
CLK_RTC_CNT = GCLK_RTC/2
0x2
DIV4
CLK_RTC_CNT = GCLK_RTC/4
0x3
DIV8
CLK_RTC_CNT = GCLK_RTC/8
0x4
DIV16
CLK_RTC_CNT = GCLK_RTC/16
0x5
DIV32
CLK_RTC_CNT = GCLK_RTC/32
0x6
DIV64
CLK_RTC_CNT = GCLK_RTC/64
0x7
DIV128
CLK_RTC_CNT = GCLK_RTC/128
0x8
DIV256
CLK_RTC_CNT = GCLK_RTC/256
0x9
DIV512
CLK_RTC_CNT = GCLK_RTC/512
0xA
DIV1024
CLK_RTC_CNT = GCLK_RTC/1024
0xB-0xF
Description
Reserved
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z
Bit 7 – MATCHCLR: Clear on Match
This bit is valid only in Mode 0 and Mode 2.
0: The counter is not cleared on a Compare/Alarm 0 match.
1: The counter is cleared on a Compare/Alarm 0 match.
This bit is not synchronized.
z
Bits 6:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 3:2 – MODE[1:0]: Operating Mode
These bits define the operating mode of the RTC.
These bits are not synchronized.
Table 17-5. Operating Mode
MODE[1:0]
Name
0x0
COUNT32
Mode 0: 32-bit Counter
0x1
COUNT16
Mode 1: 16-bit Counter
0x2
CLOCK
Mode 2: Clock/Calendar
0x3
z
Description
Reserved
Bit 1 – ENABLE: Enable
0: The peripheral is disabled or being disabled.
1: The peripheral is enabled or being enabled.
Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.
This bit is not enable-protected.
z
Bit 0 – SWRST: Software Reset
0: There is no reset operation ongoing.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the RTC, except DBGCTRL, to their initial state, and the RTC will be
disabled.
Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded.
Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete. CTRL.SWRST and
STATUS.SYNCBUSY will both be cleared when the reset is complete.
This bit is not enable-protected.
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17.8.2 Control - MODE1
Name:
CTRL
Offset:
0x00
Reset:
0x0000
Property:
Enable-Protected, Write-Protected, Write-Synchronized
Bit
15
14
13
12
11
10
9
8
PRESCALER[3:0]
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ENABLE
SWRST
MODE[1:0]
Access
R
R
R
R
R/W
R/W
R/W
W
Reset
0
0
0
0
0
0
0
0
z
Bits 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 11:8 – PRESCALER[3:0]: Prescaler
These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock
(CLK_RTC_CNT).
These bits are not synchronized.
Table 17-6. Prescaler
PRESCALER[3:0]
Name
0x0
DIV1
CLK_RTC_CNT = GCLK_RTC/1
0x1
DIV2
CLK_RTC_CNT = GCLK_RTC/2
0x2
DIV4
CLK_RTC_CNT = GCLK_RTC/4
0x3
DIV8
CLK_RTC_CNT = GCLK_RTC/8
0x4
DIV16
CLK_RTC_CNT = GCLK_RTC/16
0x5
DIV32
CLK_RTC_CNT = GCLK_RTC/32
0x6
DIV64
CLK_RTC_CNT = GCLK_RTC/64
0x7
DIV128
CLK_RTC_CNT = GCLK_RTC/128
0x8
DIV256
CLK_RTC_CNT = GCLK_RTC/256
0x9
DIV512
CLK_RTC_CNT = GCLK_RTC/512
0xA
DIV1024
CLK_RTC_CNT = GCLK_RTC/1024
0xB-0xF
Description
Reserved
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z
Bits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 3:2 – MODE[1:0]: Operating Mode
These bits define the operating mode of the RTC.
These bits are not synchronized.
Table 17-7. Operating Mode
MODE[1:0]
Name
0x0
COUNT32
Mode 0: 32-bit Counter
0x1
COUNT16
Mode 1: 16-bit Counter
0x2
CLOCK
Mode 2: Clock/Calendar
0x3
z
Description
Reserved
Bit 1 – ENABLE: Enable
0: The peripheral is disabled or being disabled.
1: The peripheral is enabled or being enabled.
Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.
This bit is not enable-protected.
z
Bit 0 – SWRST: Software Reset
0: There is no reset operation ongoing.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the RTC, except DBGCTRL, to their initial state, and the RTC will be
disabled.
Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded.
Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete. CTRL.SWRST and
STATUS.SYNCBUSY will both be cleared when the reset is complete.
This bit is not enable-protected.
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17.8.3 Control - MODE2
Name:
CTRL
Offset:
0x00
Reset:
0x0000
Property:
Enable-Protected, Write-Protected, Write-Synchronized
Bit
15
14
13
12
11
10
9
8
PRESCALER[3:0]
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
MATCHCLR
CLKREP
ENABLE
SWRST
R/W
R/W
R
R
R/W
R/W
R/W
W
0
0
0
0
0
0
0
0
Access
Reset
MODE[1:0]
z
Bits 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 11:8 – PRESCALER[3:0]: Prescaler
These bits define the prescaling factor for the RTC clock source (GCLK_RTC) to generate the counter clock
(CLK_RTC_CNT).
These bits are not synchronized.
Table 17-8. Prescaler
PRESCALER[3:0]
Name
0x0
DIV1
CLK_RTC_CNT = GCLK_RTC/1
0x1
DIV2
CLK_RTC_CNT = GCLK_RTC/2
0x2
DIV4
CLK_RTC_CNT = GCLK_RTC/4
0x3
DIV8
CLK_RTC_CNT = GCLK_RTC/8
0x4
DIV16
CLK_RTC_CNT = GCLK_RTC/16
0x5
DIV32
CLK_RTC_CNT = GCLK_RTC/32
0x6
DIV64
CLK_RTC_CNT = GCLK_RTC/64
0x7
DIV128
CLK_RTC_CNT = GCLK_RTC/128
0x8
DIV256
CLK_RTC_CNT = GCLK_RTC/256
0x9
DIV512
CLK_RTC_CNT = GCLK_RTC/512
0xA
DIV1024
CLK_RTC_CNT = GCLK_RTC/1024
0xB-0xF
Description
Reserved
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z
Bit 7 – MATCHCLR: Clear on Match
This bit is valid only in Mode 0 and Mode 2. This bit can be written only when the peripheral is disabled.
0: The counter is not cleared on a Compare/Alarm 0 match.
1: The counter is cleared on a Compare/Alarm 0 match.
This bit is not synchronized.
z
Bit 6 – CLKREP: Clock Representation
This bit is valid only in Mode 2 and determines how the hours are represented in the Clock Value (CLOCK) register. This bit can be written only when the peripheral is disabled.
0: 24 Hour
1: 12 Hour (AM/PM)
This bit is not synchronized.
z
Bits 5:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 3:2 – MODE[1:0]: Operating Mode
These bits define the operating mode of the RTC.
These bits are not synchronized.
Table 17-9. Operating Mode
MODE[1:0]
Name
0x0
COUNT32
Mode 0: 32-bit Counter
0x1
COUNT16
Mode 1: 16-bit Counter
0x2
CLOCK
Mode 2: Clock/Calendar
0x3
z
Description
Reserved
Bit 1 – ENABLE: Enable
0: The peripheral is disabled or being disabled.
1: The peripheral is enabled or being enabled.
Due to synchronization, there is delay from writing CTRL.ENABLE until the peripheral is enabled/disabled. The
value written to CTRL.ENABLE will read back immediately, and the Synchronization Busy bit in the Status register
(STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY will be cleared when the operation is complete.
This bit is not enable-protected.
z
Bit 0 – SWRST: Software Reset
0: There is no reset operation ongoing.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets all registers in the RTC, except DBGCTRL, to their initial state, and the RTC will be
disabled.
Writing a one to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation will be discarded.
Due to synchronization, there is a delay from writing CTRL.SWRST until the reset is complete. CTRL.SWRST and
STATUS.SYNCBUSY will both be cleared when the reset is complete.
This bit is not enable-protected.
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17.8.4 Read Request
Name:
READREQ
Offset:
0x02
Reset:
0x0010
Property:
-
Bit
15
14
13
12
11
10
9
8
RREQ
RCONT
Access
W
R/W
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
ADDR[5:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
1
0
0
0
0
z
Bit 15 – RREQ: Read Request
Writing a zero to this bit has no effect.
Writing a one to this bit requests synchronization of the register pointed to by the Address bit group (READREQ.ADDR) and sets the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY).
z
Bit 14 – RCONT: Read Continuously
Writing a zero to this bit disables continuous synchronization.
Writing a one to this bit enables continuous synchronization of the register pointed to by READREQ.ADDR. The
register value will be synchronized automatically every time the register is updated. READREQ.RCONT prevents
READREQ.RREQ from clearing automatically.
This bit is cleared when the register pointed to by READREQ.ADDR is written.
z
Bits 13:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 5:0 – ADDR[5:0]: Address
These bits select the offset of the register that needs read synchronization. In the RTC only COUNT and CLOCK,
which share the same address, are available for read synchronization. Therefore, ADDR is a read-only constant of
0x10.
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17.8.5 Event Control - MODE0
Name:
EVCTRL
Offset:
0x04
Reset:
0x0000
Property:
Enable-Protected, Write-Protected
Bit
15
14
13
12
11
10
9
OVFEO
Access
8
CMPEO0
R/W
R
R
R
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PEREO7
PEREO6
PEREO5
PEREO4
PEREO3
PEREO2
PEREO1
PEREO0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Access
Reset
z
Bit 15 – OVFEO: Overflow Event Output Enable
0: Overflow event is disabled and will not be generated.
1: Overflow event is enabled and will be generated for every overflow.
z
Bits 14:9 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 8 – CMPEO: Compare 0 Event Output Enable
0: Compare 0 event is disabled and will not be generated.
1: Compare 0 event is enabled and will be generated for every compare match.
z
Bits 7:0 – PEREOx [x=7..0]: Periodic Interval x Event Output Enable
0: Periodic Interval x event is disabled and will not be generated.
1: Periodic Interval x event is enabled and will be generated.
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17.8.6 Event Control - MODE1
Name:
EVCTRL
Offset:
0x04
Reset:
0x0000
Property:
Enable-Protected, Write-Protected
Bit
15
14
13
12
11
10
OVFEO
Access
9
8
CMPEO1
CMPEO0
R/W
R
R
R
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PEREO7
PEREO6
PEREO5
PEREO4
PEREO3
PEREO2
PEREO1
PEREO0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Access
Reset
z
Bit 15 – OVFEO: Overflow Event Output Enable
0: Overflow event is disabled and will not be generated.
1: Overflow event is enabled and will be generated for every overflow.
z
Bits 14:10 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 9:8 – CMPEOx [x=1..0]: Compare x Event Output Enable
0: Compare x event is disabled and will not be generated.
1: Compare x event is enabled and will be generated for every compare match.
z
Bits 7:0 – PEREOx [x=7..0]: Periodic Interval x Event Output Enable
0: Periodic Interval x event is disabled and will not be generated.
1: Periodic Interval x event is enabled and will be generated.
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17.8.7 Event Control - MODE2
Name:
EVCTRL
Offset:
0x04
Reset:
0x0000
Property:
Enable-Protected, Write-Protected
Bit
15
14
13
12
11
10
9
OVFEO
Access
8
ALARMEO0
R/W
R
R
R
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PEREO7
PEREO6
PEREO5
PEREO4
PEREO3
PEREO2
PEREO1
PEREO0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Access
Reset
z
Bit 15 – OVFEO: Overflow Event Output Enable
0: Overflow event is disabled and will not be generated.
1: Overflow event is enabled and will be generated for every overflow.
z
Bits 14:9 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 8 – ALARMEO: Alarm 0 Event Output Enable
0: Alarm 0 event is disabled and will not be generated.
1: Alarm 0 event is enabled and will be generated for every alarm.
z
Bits 7:0 – PEREOx [x=7..0]: Periodic Interval x Event Output Enable
0: Periodic Interval x event is disabled and will not be generated.
1: Periodic Interval x event is enabled and will be generated.
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17.8.8 Interrupt Enable Clear - MODE0
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Set register (INTENSET).
Name:
INTENCLR
Offset:
0x06
Reset:
0x00
Property:
Write-Protected
Bit
Access
Reset
z
7
6
5
4
3
2
1
0
OVF
SYNCRDY
R/W
R/W
R
R
R
R
R
R/W
0
0
0
0
0
0
0
0
CMP0
Bit 7 – OVF: Overflow Interrupt Enable
0: The Overflow interrupt is disabled.
1: The Overflow interrupt is enabled, and an interrupt request will be generated when the Overflow interrupt flag is
set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overflow Interrupt Enable bit and disable the corresponding interrupt.
z
Bit 6 – SYNCRDY: Synchronization Ready Interrupt Enable
0: The Synchronization Ready interrupt is disabled.
1: The Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the Synchronization Ready interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and disable the corresponding
interrupt.
z
Bits 5:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 0 – CMP: Compare 0 Interrupt Enable
0: The Compare 0 interrupt is disabled.
1: The Compare 0 interrupt is enabled, and an interrupt request will be generated when the Compare x interrupt
flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Compare 0 Interrupt Enable bit and disable the corresponding interrupt.
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17.8.9 Interrupt Enable Clear - MODE1
Name:
INTENCLR
Offset:
0x06
Reset:
0x00
Property:
Write-Protected
Bit
Access
Reset
z
7
6
5
4
3
OVF
SYNCRDY
R/W
R/W
R
R
R
0
0
0
0
0
2
1
0
CMP1
CMP0
R
R/W
R/W
0
0
0
Bit 7 – OVF: Overflow Interrupt Enable
0: The Overflow interrupt is disabled.
1: The Overflow interrupt is enabled, and an interrupt request will be generated when the Overflow interrupt flag is
set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overflow Interrupt Enable bit and disable the corresponding interrupt.
z
Bit 6 – SYNCRDY: Synchronization Ready Interrupt Enable
0: The Synchronization Ready interrupt is disabled.
1: The Synchronization Ready interrupt is enabled, and an interrupt request will be generated when the Synchronization Ready interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and disable the corresponding
interrupt.
z
Bits 5:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 1:0 – CMPx [x=1..0]: Compare x Interrupt Enable
0: The Compare x interrupt is disabled.
1: The Compare x interrupt is enabled, and an interrupt request will be generated when the Compare x interrupt
flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Compare x Interrupt Enable bit and disable the corresponding interrupt.
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17.8.10 Interrupt Enable Clear - MODE2
Name:
INTENCLR
Offset:
0x06
Reset:
0x00
Property:
Write-Protected
Bit
Access
Reset
z
7
6
5
4
3
2
1
0
OVF
SYNCRDY
R/W
R/W
R
R
R
R
R
R/W
0
0
0
0
0
0
0
0
ALARM0
Bit 7 – OVF: Overflow Interrupt Enable
0: The Overflow interrupt is disabled.
1: The Overflow interrupt is enabled, and an interrupt request will be generated when the Overflow interrupt flag is
set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Overflow Interrupt Enable bit and disable the corresponding interrupt.
z
Bit 6 – SYNCRDY: Synchronization Ready Interrupt Enable
0: The synchronization ready interrupt is disabled.
1: The synchronization ready interrupt is enabled, and an interrupt request will be generated when the Synchronization Ready interrupt flag is set.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Synchronization Ready Interrupt Enable bit and disable the corresponding
interrupt.
z
Bits 5:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 0 – ALARM: Alarm 0 Interrupt Enable
0: The Alarm 0 interrupt is disabled.
1: The Alarm 0 interrupt is enabled, and an interrupt request will be generated when the Alarm 0 interrupt flag is
set.
Writing a zero to this bit has no effect.
Writing a one to this bit disables the Alarm 0 interrupt.
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17.8.11 Interrupt Enable Set - MODE0
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Name:
INTENSET
Offset:
0x07
Reset:
0x00
Property:
Write-Protected
Bit
Access
Reset
z
7
6
5
4
3
2
1
0
OVF
SYNCRDY
R/W
R/W
R
R
R
R
R
R/W
0
0
0
0
0
0
0
0
CMP0
Bit 7 – OVF: Overflow Interrupt Enable
0: The overflow interrupt is disabled.
1: The overflow interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overflow Interrupt Enable bit and enable the Overflow interrupt.
z
Bit 6 – SYNCRDY: Synchronization Ready Interrupt Enable
0: The synchronization ready interrupt is disabled.
1: The synchronization ready interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Synchronization Ready Interrupt Enable bit and enable the Synchronization
Ready interrupt.
z
Bits 5:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 0 – CMP: Compare 0 Interrupt Enable
0: The compare 0 interrupt is disabled.
1: The compare 0 interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Compare 0 Interrupt Enable bit and enable the Compare 0 interrupt.
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17.8.12 Interrupt Enable Set - MODE1
Name:
INTENSET
Offset:
0x07
Reset:
0x00
Property:
Write-Protected
Bit
Access
Reset
z
7
6
5
4
3
OVF
SYNCRDY
R/W
R/W
R
R
R
0
0
0
0
0
2
1
0
CMP1
CMP0
R
R/W
R/W
0
0
0
Bit 7 – OVF: Overflow Interrupt Enable
0: The overflow interrupt is disabled.
1: The overflow interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overflow interrupt bit and enable the Overflow interrupt.
z
Bit 6 – SYNCRDY: Synchronization Ready Interrupt Enable
0: The synchronization ready interrupt is disabled.
1: The synchronization ready interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Synchronization Ready Interrupt Enable bit and enable the Synchronization
Ready interrupt.
z
Bits 5:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 1:0 – CMPx [x=1..0]: Compare x Interrupt Enable
0: The compare x interrupt is disabled.
1: The compare x interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Compare x Interrupt Enable bit and enable the Compare x interrupt.
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17.8.13 Interrupt Enable Set - MODE2
Name:
INTENSET
Offset:
0x07
Reset:
0x00
Property:
Write-Protected
Bit
Access
Reset
z
7
6
5
4
3
2
1
0
OVF
SYNCRDY
R/W
R/W
R
R
R
R
R
R/W
0
0
0
0
0
0
0
0
ALARM0
Bit 7 – OVF: Overflow Interrupt Enable
0: The overflow interrupt is disabled.
1: The overflow interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Overflow Interrupt Enable bit and enable the Overflow interrupt.
z
Bit 6 – SYNCRDY: Synchronization Ready Interrupt Enable
0: The synchronization ready interrupt is disabled.
1: The synchronization ready interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Synchronization Ready Interrupt bit and enable the Synchronization Ready
interrupt.
z
Bits 5:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 0 – ALARM: Alarm 0 Interrupt Enable
0: The alarm 0 interrupt is disabled.
1: The alarm 0 interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Alarm 0 Interrupt Enable bit and enable the Alarm 0 interrupt.
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17.8.14 Interrupt Flag Status and Clear - MODE0
Name:
INTFLAG
Offset:
0x08
Reset:
0x00
Property:
-
Bit
Access
Reset
z
7
6
5
4
3
2
1
0
OVF
SYNCRDY
R/W
R/W
R
R
R
R
R
R/W
0
0
0
0
0
0
0
0
CMP0
Bit 7 – OVF: Overflow
This flag is cleared by writing a one to the flag.
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will
be generated if INTENCLR/SET.OVF is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Overflow interrupt flag.
z
Bit 6 – SYNCRDY: Synchronization Ready
This flag is cleared by writing a one to the flag.
This flag is set on a 1-to-0 transition of the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY),
except when caused by enable or software reset, and an interrupt request will be generated if INTENCLR/SET.SYNCRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Synchronization Ready interrupt flag.
z
Bits 5:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 0 – CMP: Compare 0
This flag is cleared by writing a one to the flag.
This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition, and an interrupt
request will be generated if INTENCLR/SET.CMP0 is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Compare 0 interrupt flag.
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17.8.15 Interrupt Flag Status and Clear - MODE1
Name:
INTFLAG
Offset:
0x08
Reset:
0x00
Property:
-
Bit
Access
Reset
z
7
6
5
4
3
OVF
SYNCRDY
R/W
R/W
R
R
R
0
0
0
0
0
2
1
0
CMP1
CMP0
R
R/W
R/W
0
0
0
Bit 7 – OVF: Overflow
This flag is cleared by writing a one to the flag.
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will
be generated if INTENCLR/SET.OVF is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Overflow interrupt flag.
z
Bit 6 – SYNCRDY: Synchronization Ready
This flag is cleared by writing a one to the flag.
This flag is set on a 1-to-0 transition of the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY),
except when caused by enable or software reset, and an interrupt request will be generated if INTENCLR/SET.SYNCRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Synchronization Ready interrupt flag.
z
Bits 5:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 1:0 – CMPx [x=1..0]: Compare x
This flag is cleared by writing a one to the flag.
This flag is set on the next CLK_RTC_CNT cycle after a match with the compare condition and an interrupt
request will be generated if INTENCLR/SET.CMPx is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Compare x interrupt flag.
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17.8.16 Interrupt Flag Status and Clear - MODE2
Name:
INTFLAG
Offset:
0x08
Reset:
0x00
Property:
-
Bit
Access
Reset
z
7
6
5
4
3
2
1
0
OVF
SYNCRDY
R/W
R/W
R
R
R
R
R
R/W
0
0
0
0
0
0
0
0
ALARM0
Bit 7 – OVF: Overflow
This flag is cleared by writing a one to the flag.
This flag is set on the next CLK_RTC_CNT cycle after an overflow condition occurs, and an interrupt request will
be generated if INTENCLR/SET.OVF is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Overflow interrupt flag.
z
Bit 6 – SYNCRDY: Synchronization Ready
This flag is cleared by writing a one to the flag.
This flag is set on a 1-to-0 transition of the Synchronization Busy bit in the Status register (STATUS.SYNCBUSY),
except when caused by enable or software reset, and an interrupt request will be generated if INTENCLR/SET.SYNCRDY is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Synchronization Ready interrupt flag.
z
Bits 5:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 0 – ALARM: Alarm 0
This flag is cleared by writing a one to the flag.
This flag is set on the next CLK_RTC_CNT cycle after a match with ALARM0 condition occurs, and an interrupt
request will be generated if INTENCLR/SET.ALARM0 is also one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Alarm 0 interrupt flag.
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17.8.17 Status
Name:
STATUS
Offset:
0x0A
Reset:
0x00
Property:
-
Bit
7
6
5
4
3
2
1
0
SYNCBUSY
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
z
Bit 7 – SYNCBUSY: Synchronization Busy
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
z
Bits 6:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
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17.8.18 Debug Control
Name:
DBGCTRL
Offset:
0x0B
Reset:
0x00
Property:
-
Bit
7
6
5
4
3
2
1
0
DBGRUN
Access
R
R
R
R
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0
z
Bits 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 0 – DBGRUN: Run During Debug
This bit is not reset by a software reset.
Writing a zero to this bit causes the RTC to halt during debug mode.
Writing a one to this bit allows the RTC to continue normal operation during debug mode.
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17.8.19 Frequency Correction
Name:
FREQCORR
Offset:
0x0C
Reset:
0x00
Property:
Write-Protected, Write-Synchronized
Bit
7
6
5
4
SIGN
Access
Reset
z
3
2
1
0
VALUE[6:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 7 – SIGN: Correction Sign
0: The correction value is positive, i.e., frequency will be increased.
1: The correction value is negative, i.e., frequency will be decreased.
z
Bits 6:0 – VALUE[6:0]: Correction Value
These bits define the amount of correction applied to the RTC prescaler.
0: Correction is disabled and the RTC frequency is unchanged.
1–127: The RTC frequency is adjusted according to the value.
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17.8.20 Counter Value - MODE0
Name:
COUNT
Offset:
0x10
Reset:
0x00000000
Property:
Read-Synchronized, Write-Protected, Write-Synchronized
Bit
31
30
29
28
27
26
25
24
COUNT[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
COUNT[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
COUNT[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
COUNT[7:0]
Access
Reset
z
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:0 – COUNT[31:0]: Counter Value
These bits define the value of the 32-bit RTC counter.
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17.8.21 Counter Value - MODE1
Name:
COUNT
Offset:
0x10
Reset:
0x0000
Property:
Read-Synchronized, Write-Protected, Write-Synchronized
Bit
15
14
13
12
11
10
9
8
COUNT[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
COUNT[7:0]
Access
Reset
z
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 15:0 – COUNT[15:0]: Counter Value
These bits define the value of the 16-bit RTC counter.
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17.8.22 Clock Value - MODE2
Name:
CLOCK
Offset:
0x10
Reset:
0x00000000
Property:
Read-Synchronized, Write-Protected, Write-Synchronized
Bit
31
30
29
28
27
26
25
YEAR[5:0]
Access
24
MONTH[3:2]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
MONTH[1:0]
Access
DAY[4:0]
HOUR[4]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
HOUR[3:0]
Access
MINUTE[5:2]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
MINUTE[1:0]
Access
Reset
z
SECOND[5:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:26 – YEAR[5:0]: Year
The year offset with respect to the reference year (defined in software).
The year is considered a leap year if YEAR[1:0] is zero.
z
Bits 25:22 – MONTH[3:0]: Month
1 – January
2 – February
...
12 – December
z
Bits 21:17 – DAY[4:0]: Day
Day starts at 1 and ends at 28, 29, 30 or 31, depending on the month and year.
z
Bits 16:12 – HOUR[4:0]: Hour
When CTRL.CLKREP is zero, the Hour bit group is in 24-hour format, with values 0-23. When CTRL.CLKREP is
one, HOUR[3:0] has values 1-12 and HOUR[4] represents AM (0) or PM (1).
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Table 17-10. Hour
HOUR[4:0]
CLOCK.HOUR[4]
0
CLOCK.HOUR[3:0]
0x00 - 0x17
Hour (0 - 23)
0x18 - 0x1F
Reserved
0x0
0
1
1
z
Bits 11:6 – MINUTE[5:0]: Minute
0 – 59.
z
Bits 5:0 – SECOND[5:0]: Second
0– 59.
Description
Reserved
0x1 - 0xC
AM Hour (1 - 12)
0xD - 0xF
Reserved
0x0
Reserved
0x1 - 0xC
PM Hour (1 - 12)
0xF - 0xF
Reserved
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17.8.23 Counter Period - MODE1
Name:
PER
Offset:
0x14
Reset:
0x0000
Property:
Write-Protected, Write-Synchronized
Bit
15
14
13
12
11
10
9
8
PER[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PER[7:0]
Access
Reset
z
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 15:0 – PER[15:0]: Counter Period
These bits define the value of the 16-bit RTC period.
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17.8.24 Compare n Value - MODE0
Name:
COMP
Offset:
0x18
Reset:
0x00000000
Property:
Write-Protected, Write-Synchronized
Bit
31
30
29
28
27
26
25
24
COMP[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
COMP[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
COMP[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
COMP[7:0]
Access
Reset
z
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:0 – COMP[31:0]: Compare Value
The 32-bit value of COMPn is continuously compared with the 32-bit COUNT value. When a match occurs, the
Compare n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn) is set on the next counter
cycle, and the counter value is cleared if CTRL.MATCHCLR is one.
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17.8.25 Compare n Value - MODE1
Name:
COMPn
Offset:
0x18+n*0x2 [n=0..1]
Reset:
0x0000
Property:
Write-Protected, Write-Synchronized
Bit
15
14
13
12
11
10
9
8
COMP[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
COMP[7:0]
Access
Reset
z
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 15:0 – COMP[15:0]: Compare Value
The 16-bit value of COMPn is continuously compared with the 16-bit COUNT value. When a match occurs, the
Compare n interrupt flag in the Interrupt Flag Status and Clear register (INTFLAG.CMPn) is set on the next counter
cycle.
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17.8.26 Alarm 0 Value - MODE2
Name:
ALARM0
Offset:
0x18
Reset:
0x00000000
Property:
Write-Protected, Write-Synchronized
Bit
31
30
29
28
27
26
25
YEAR[5:0]
Access
24
MONTH[3:2]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
MONTH[1:0]
Access
DAY[4:0]
HOUR[4]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
HOUR[3:0]
Access
MINUTE[5:2]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
MINUTE[1:0]
Access
Reset
SECOND[5:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
The 32-bit value of ALARM0 is continuously compared with the 32-bit CLOCK value, based on the masking set by
MASKn.SEL. When a match occurs, the Alarm 0 interrupt flag in the Interrupt Flag Status and Clear register
(INTFLAG.ALARMn) is set on the next counter cycle, and the counter is cleared if CTRL.MATCHCLR is one.
z
Bits 31:26 – YEAR[5:0]: Year
The alarm year. Years are only matched if MASKn.SEL is 6.
z
Bits 25:22 – MONTH[3:0]: Month
The alarm month. Months are matched only if MASKn.SEL is greater than 4.
z
Bits 21:17 – DAY[4:0]: Day
The alarm day. Days are matched only if MASKn.SEL is greater than 3.
z
Bits 16:12 – HOUR[4:0]: Hour
The alarm hour. Hours are matched only if MASKn.SEL is greater than 2.
z
Bits 11:6 – MINUTE[5:0]: Minute
The alarm minute. Minutes are matched only if MASKn.SEL is greater than 1.
z
Bits 5:0 – SECOND[5:0]: Second
The alarm second. Seconds are matched only if MASKn.SEL is greater than 0.
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17.8.27 Alarm n Mask - MODE2
Name:
MASK
Offset:
0x1C
Reset:
0x00
Property:
Write-Protected, Write-Synchronized
Bit
7
6
5
4
3
2
1
0
SEL[2:0]
Access
R
R
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
z
Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 2:0 – SEL[2:0]: Alarm Mask Selection
These bits define which bit groups of Alarm n are valid.
Table 17-11. Alarm Mask Selection
SEL[2:0]
Name
0x0
OFF
0x1
SS
0x2
MMSS
0x3
HHMMSS
0x4
DDHHMMSS
0x5
MMDDHHMMSS
0x6
YYMMDDHHMMSS
0x7
Description
Alarm Disabled
Match seconds only
Match seconds and minutes only
Match seconds, minutes, and hours only
Match seconds, minutes, hours, and days only
Match seconds, minutes, hours, days, and months only
Match seconds, minutes, hours, days, months, and years
Reserved
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18.
DMAC – Direct Memory Access Controller
18.1
Overview
The Direct Memory Access Controller (DMAC) contains both a Direct Memory Access engine and a Cyclic Redundancy
Check (CRC) engine. The DMAC can transfer data between memories and peripherals, and thus off-load these tasks
from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU time. With access to
all peripherals, the DMAC can handle automatic transfer of data between communication modules.
For the DMA part of the DMAC, it has several DMA channels which all can receive different types of transfer triggers,
which will result in transfer requests from the DMA channels to the arbiter. Refer to Figure 18-1. The arbiter will grant one
DMA channel at a time to act as the active channel. When the active channel has been granted, the fetch engine of the
DMAC will fetch a transfer descriptor from SRAM into the internal memory of the active channel, before the active
channel starts its data transmission. A DMA channel's data transfer can be interrupted by a higher prioritized channel.
The DMAC will write back the updated transfer descriptor from the internal memory of the active channel to SRAM,
before the higher prioritized channel gets to start its transfer. Once a DMA channel is done with its transfer optionally
interrupts and events can be generated.
As one can see from Figure 18-1, the DMAC has four bus interfaces. The data transfer bus, which is used for performing
the actual DMA transfer is an AHB master interface. The AHB/APB Bridge bus is an APB slave interface and is the bus
used when writing and reading the I/O registers of the DMAC. The descriptor fetch bus is an AHB master interface and is
used by the fetch engine, to fetch transfer descriptors from SRAM before a transfer can be started or continued. At last
there is the write-back bus, which is an AHB master interface and it is used to write the transfer descriptor back to SRAM.
As mentioned, the DMAC also has a CRC module available. This can be used by software to detect an accidental error
in the transferred data and to take corrective action, such as requesting the data to be sent again or simply not using the
incorrect data.
18.2
Features
z Data transfer between
Peripheral to peripheral
Peripheral to memory
z Memory to peripheral
z Memory to memory
z
z
z Transfer trigger sources
Software
Events from Event System
z Dedicated requests from peripherals
z
z
z SRAM based transfer descriptors
z
z
Single transfer using one descriptor
Multi-buffer or circular buffer modes by linking multiple descriptors
z 12 channels
Enable 12 independent transfers
Automatic descriptor fetch for each channel
z Suspend/resume operation support for each channel
z
z
z Flexible arbitration scheme
z
z
4 configurable priority levels for each channel
Fixed or round-robin priority scheme within each priority level
z From 1 to 256kB data transfer in a single block transfer
z Multiple addressing modes
z
z
Static
Configurable increment scheme
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z Optional interrupt generation
On block transfer complete
On error detection
z On channel suspend
z
z
z 4 event inputs
One event input for each of the 4 least significant DMA channels
Can be selected to trigger normal transfers, periodic transfers or conditional transfers
z Can be selected to suspend or resume channel operation
z
z
z 4 event outputs
z
z
One output event for each of the 4 least significant DMA channels
Selectable generation on AHB, burst, block or transaction transfer complete
z Error management supported by write-back function
z
Dedicated Write-Back memory section for each channel to store ongoing descriptor transfer
z CRC polynomial software selectable to
z
z
18.3
CRC-16 (CRC-CCITT)
CRC-32 (IEEE 802.3)
Block Diagram
Figure 18-1. DMAC Block Diagram
CPU
M
AHB/APB
Bridge
SRAM
Descriptor Fetch
M
Data Transfer
S
S
Write-back
HIGH SPEED
BUS MATRIX
DMAC
MASTER
Fetch
Engine
DMA Channels
Channel n
Transfer
Triggers
n
Channel 1
Channel 0
Interrupts
Arbiter
Active
Channel
Interrupt /
Events
Events
CRC
Engine
18.4
Signal Description
Not applicable.
18.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
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18.5.1 I/O Lines
Not applicable.
18.5.2 Power Management
The DMAC will continue to operate in any sleep mode where the selected source clock is running. The DMAC’s interrupts
can be used to wake up the device from sleep modes. Events connected to the event system can trigger other operations
in the system without exiting sleep modes. Refer to “PM – Power Manager” on page 112 for details on the different sleep
modes. On hardware or software reset, all registers are set to their reset value.
18.5.3 Clocks
The DMAC bus clock (CLK_DMAC_APB) can be enabled and disabled in the power manager, and the default state of
CLK_DMAC_APB can be found in “Peripheral Clock Masking” on page 116.
An AHB clock (CLK_DMAC_AHB) is required to clock the DMAC. This clock must be configured and enabled in the
power manager before using the DMAC, and the default state of CLK_DMAC_AHB can be found in “Peripheral Clock
Masking” on page 116.
This bus clock (CLK_DMAC_APB) is always synchronous to the module clock (CLK_DMAC_AHB), but can be divided by
a prescaler and may run even when the module clock is turned off.
18.5.4 DMA
Not applicable.
18.5.5 Interrupts
The interrupt request line is connected to the interrupt controller. Using the DMAC interrupts requires the interrupt
controller to be configured first. Refer to “Nested Vector Interrupt Controller” on page 29 for details.
18.5.6 Events
The events are connected to the event system. Refer to “EVSYS – Event System” on page 400 for details on how to
configure the Event System.
18.5.7 Debug Operation
When the CPU is halted in debug mode the DMAC will halt normal operation. The DMAC can be forced to continue
operation during debugging. Refer to DBGCTRL for details.
18.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the
following registers:
z
Interrupt Pending (INTPEND) register
z
Channel ID (CHID) register
z
Channel Interrupt Flag Status and Clear (CHINTFLAG) register
Write-protection is denoted by the Write-Protected property in the register description.
Write-protection does not apply to accesses through an external debugger. Refer to “PAC – Peripheral Access
Controller” on page 36 for details.
18.5.9 Analog Connections
Not applicable.
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18.6
Functional Description
18.6.1 Principle of Operation
The DMAC consists of a DMA module and a CRC module.
18.6.1.1 DMA
The DMAC can, without interaction from the CPU, transfer data between peripherals and memories. The data transferred
by the DMAC are called transactions, and these transactions can be split into smaller data transfers. Figure 18-2 shows
the relationship between the different transfer sizes.
Figure 18-2. DMA Transfer Sizes
Link Enabled
Beat transfer
Link Enabled
Burst transfer
Link Enabled
Block transfer
DMA transaction
z
Beat transfer: Defined as the size of one data transfer bus access, and the size is selected by writing the Beat Size
bit group in the Block Transfer Control register (BTCTRL.BEATSIZE)
z
Burst transfer: Defined as n beat transfers, where n will differ from one device family to another. For this device
family, n is 1. A burst transfer is atomic, and cannot be interrupted.
z
Block transfer: The amount of data one transfer descriptor can transfer, and the amount can range from 1 to 64k
beats. In contrast to the burst transfer, a block transfer can be interrupted.
z
Transaction: The DMAC can link several transfer descriptors by having the first descriptor pointing to the second
and so forth, as shown in Figure 18-2. A DMA transaction is defined as all block transfers within a linked list, being
completed.
A transfer descriptor describes how a block transfer should be carried out by the DMAC, and it must remain in SRAM. For
further details on the transfer descriptor refer to “Transfer Descriptors” on page 272.
Figure 18-2 shows several block transfers linked together, which are called linked descriptors. For further information
about linked descriptors, refer to “Linked Descriptors” on page 279.
A DMA transfer is initiated by an incoming transfer trigger on one of the DMA channels. This trigger can be configured to
be either a software trigger, an event trigger or one of the dedicated peripheral triggers. The transfer trigger will result in
a DMA transfer request from the specific channel to the arbiter, and if there are several DMA channels with pending
transfer requests, the arbiter has to choose which channel to grant access to become the active channel. The DMA
channel granted access as the active channel will carry out the transaction as configured in the transfer descriptor. The
DMA channel can be interrupted by a higher prioritized channel after each burst transfer, but will resume its block
transfer when it is granted access as the active channel again.
For each beat transfer an optional output event can be generated, and for each block transfer optional interrupts and an
optional output event can be generated. When a transaction is completed, dependent of the configuration, the DMA
channel will either be suspended or disabled.
18.6.1.2 CRC
The internal CRC supports two commonly used CRC polynomials; CRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3). It
can be used with selectable DMA channel or independently, with I/O interface.
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18.6.2 Basic Operation
18.6.2.1 Initialization
The following DMAC registers are enable-protected, meaning that they can only be written when the DMAC is disabled
(CTRL.DMAENABLE is zero):
z
Descriptor Base Memory Address (BASEADDR) register
z
Write-Back Memory Base Address (WRBADDR) register
The following DMAC bit is enable-protected, meaning that it can only be written when both the DMAC and CRC are
disabled (CTRL.DMAENABLE and CTRL.CRCENABLE is zero):
z
Software Reset bit in Control register (CTRL.SWRST)
The following DMA channel register is enable-protected, meaning that it can only be written when the corresponding
DMA channel is disabled (CHCTRLA.ENABLE is zero):
z
Channel Control B (CHCTRLB) register, except the Command (CHCTRLB.CMD) and Channel Arbitration Level
(CHCTRLB.LVL) bits
The following DMA channel bit is enable-protected, meaning that it can only be written when the corresponding DMA
channel is disabled:
z
Channel Software Reset bit in Channel Control A register (CHCTRLA.SWRST)
The following CRC registers are enable-protected, meaning that they can only be written when the CRC is disabled
(CTRL.CRCENABLE is zero):
z
CRC Control (CRCCTRL) register
z
CRC Checksum (CRCCHKSUM) register
Enable-protection is denoted by the Enable-Protected property in the register description.
Before the DMAC is enabled, it must be configured, as outlined by the following steps:
z
The SRAM address of where the descriptor memory section is located must be written to the Description Base
Address (BASEADDR) register
z
The SRAM address of where the write-back section should be located must be written to the Write-Back Memory
Base Address (WRBADDR) register
z
Priority level x of the arbiter can be enabled by writing a one to the Priority Level x Enable bit in the Control
register(CTRL.LVLENx)
Before a DMA channel is enabled, the DMA channel and the corresponding first transfer descriptor must be configured,
as outlined by the following steps:
z
z
DMA channel configurations
z
The channel number of the DMA channel to configure must be written to the Channel ID (CHID) register
z
Trigger action must be selected by writing the Trigger Action bit group in the Channel Control B register
(CHCTRLB.TRIGACT)
z
Trigger source must be selected by writing the Trigger Source bit group in the Channel Control B register
(CHCTRLB.TRIGSRC)
Transfer Descriptor
z
The size of each access of the data transfer bus must be selected by writing the Beat Size bit group in the
Block Transfer Control register (BTCTRL.BEATSIZE)
z
The transfer descriptor must be made valid by writing a one to the Valid bit in the Block Transfer Control
register (BTCTRL.VALID)
z
Number of beats in the block transfer must be selected by writing the Block Transfer Count (BTCNT)
register
z
Source address for the block transfer must be selected by writing the Block Transfer Source Address
(SRCADDR) register
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z
Destination address for the block transfer must be selected by writing the Block Transfer Destination
Address (DSTADDR) register
If CRC calculation is needed the CRC module must be configured before it is enabled, as outlined by the following steps:
z
CRC input source must selected by writing the CRC Input Source bit group in the CRC Control register
(CRCCTRL.CRCSRC)
z
Type of CRC calculation must be selected by writing the CRC Polynomial Type bit group in the CRC Control
register (CRCCTRL.CRCPOLY)
z
If I/O is chosen as input source, the beat size must be selected by writing the CRC Beat Size bit group in the CRC
Control register (CRCCTRL.CRCBEATSIZE)
18.6.2.2 Enabling, Disabling and Resetting
The DMAC is enabled by writing a one to the DMA Enable bit in the Control register (CTRL.DMAENABLE). The DMAC is
disabled by writing a zero to CTRL.DMAENABLE.
A DMA channel is enabled by writing a one to Enable bit in the Channel Control A register (CHCTRLA.ENABLE), after
writing the corresponding channel id to the Channel ID bit group in the Channel ID register (CHID.ID). A DMA channel is
disabled by writing a zero to CHCTRLA.ENABLE.
The CRC is enabled by writing a one to the CRC Enable bit in the Control register (CTRL.CRCENABLE). The CRC is
disabled by writing a zero to CTRL.CRCENABLE.
The DMAC is reset by writing a one to the Software Reset bit in the Control register (CTRL.SWRST), when the DMAC
and CRC are disabled. All registers in the DMAC, except DBGCTRL, will be reset to their initial state.
A DMA channel is reset by writing a one to the Software Reset bit in the Channel Control A register (CHCTRLA.SWRST),
after writing the corresponding channel id to the Channel ID bit group in the Channel ID register (CHID.ID). The channel
registers will be reset to their initial state. The corresponding DMA channel must be disabled in order for the reset to take
effect.
18.6.2.3 Transfer Descriptors
Together with the channel configurations the transfer descriptors decides how a block transfer should be executed.
Before a DMA channel is enabled (CHCTRLA.ENABLE is written to one), and receives a transfer trigger, its first transfer
descriptor has to be initialized and valid (BTCTRL.VALID). The first transfer descriptor describes the first block transfer of
a transaction. For further details on the content of a transfer descriptor, refer to “Block Transfer Control” on page 324.
All transfer descriptors must reside in SRAM and the addresses stored in the Descriptor Memory Section Base Address
(BASEADDR) and Write-Back Memory Section Base Address (WRBADDR) registers tells the DMAC where to find the
descriptor memory section and the write-back memory section.
The descriptor memory section is where the DMAC expects to find the first transfer descriptors for all DMA channels. As
BASEADDR points only to the first transfer descriptor of channel 0, refer to Figure 18-3, all first transfer descriptors must
be stored in a contiguous memory section, where the transfer descriptors must be ordered according to their channel
number. Figure 18-3 shows an example of linked descriptors on DMA channel 0. For further details on linked descriptors,
refer to “Linked Descriptors” on page 279.
The write-back memory section is the section where the DMAC stores the transfer descriptors for the ongoing block
transfers. WRBADDR points to the ongoing transfer descriptor of channel 0. All ongoing transfer descriptors will be
stored in a contiguous memory section where the transfer descriptors are ordered according to their channel number.
Figure 18-3 shows an example of linked descriptors on DMA channel 0. For further details on linked descriptors, refer to
“Linked Descriptors” on page 279.
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Figure 18-3. Memory Sections
0x00000000
DSTADDR
DESCADDR
Channel 0 – Last Descriptor
SRCADDR
BTCNT
BTCTRL
DESCADDR
DSTADDR
DESCADDR
Channel 0 – Descriptor n-1
SRCADDR
BTCNT
BTCTRL
Descriptor Section
Channel n – First Descriptor
DESCADDR
BASEADDR
Channel 2 – First Descriptor
Channel 1 – First Descriptor
Channel 0 – First Descriptor
DSTADDR
SRCADDR
BTCNT
BTCTRL
Write-Back Section
Channel n Ongoing Descriptor
WRBADDR
Channel 2 Ongoing Descriptor
Channel 1 Ongoing Descriptor
Channel 0 Ongoing Descriptor
Device Memory Space
Undefined
Undefined
Undefined
Undefined
Undefined
The size of the descriptor and write-back memory sections is dependant on most significant enabled DMA channel, as
shown below:
Size = 128bits ⋅ ( MostSignificantEnabledChannelNumber + 1 )
For memory optimization, it is recommended to always use the less significant DMA channels if not all channels are
required.
The descriptor and write-back memory sections can either be two separate memory sections, or they can share memory
section (BASEADDR=WRBADDR). The benefit of having them in two separate sections, is that the same transaction for
a channel can be repeated without having to modify the first transfer descriptor. The benefit of having descriptor memory
and write-back memory in the same section is that it requires less SRAM. In addition, the latency from fetching the first
descriptor of a transaction to the first burst transfer is executed, is reduced.
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18.6.2.4 Arbitration
If a DMA channel is enabled and not suspended when it receives a transfer trigger, it will send a transfer request to the
arbiter. When the arbiter receives the transfer request it will include the DMA channel in the queue of channels having
pending transfers, and the corresponding Pending Channel x bit in the Pending Channels registers
(PENDCH.PENDCHx) will be set. Dependent of the arbitration scheme, the arbiter will choose which DMA channel will
be the next active channel. Refer to Figure 18-4. The active channel is the DMA channel being granted access to perform
its next burst transfer. When the arbiter has granted a DMA channel access to the DMAC, the corresponding
PENDCH.PENDCHx will be cleared. Depending on if the upcoming burst transfer is the first for the transfer request or
not, the corresponding Busy Channel x bit in the Busy Channels register (BUSYCH.BUSYCHx) will either be set or
remain one. When the channel has performed its granted burst transfer(s) it will either be fed into the queue of channels
with pending transfers, set to be waiting for a new transfer trigger, it will be suspended or it will be disabled. This depends
on the channel and block transfer configuration. If the DMA channel is fed into the queue of channels with pending
transfers, the corresponding BUSYCH.BUSYCHx will remain one. If the DMA channel is set to wait for a new transfer
trigger, suspended or disabled, the corresponding BUSYCH.BUSYCHx will be cleared.
If a DMA channel is suspended while it has a pending transfer, it will be removed from the queue of pending channels,
but the corresponding PENDCH.PENDCHx will remain set. When the same DMA channel is resumed, it will be added to
the queue of pending channels again. If a DMA channel gets disabled(CHCTRLA.ENABLE is zero) while it has a pending
transfer, it will be removed from the queue of pending channels, and the corresponding PENDCH.PENDCHx will be
cleared.
Figure 18-4. Arbiter Overview
Arbiter
Channel Enable
Channel Pending
Channel 0
Priority
decoder
Channel Suspend
Channel Priority Level
Channel Burst Done
Burst Done
Transfer Request
Channel Enable
Channel Number
Channel Suspend
Channel N
Active
Channel
Channel Pending
Channel Priority Level
Channel Burst Done
Level Enable
CTRL.LVLENx
ACTIVE.LVLEXx
PRICTRLx.LVLPRI
When a channel level is pending or the channel is transferring data, the corresponding Level Executing bit is set in the
Active Channel and Levels register (ACTIVE.LVLEXx).
Each DMA channel supports a 4-level priority scheme. The priority level for a channel is configured by writing to the
Channel Arbitration Level bit group in the Channel Control B register(CHCTRLB.LVL). As long as all priority levels are
enabled, a channel with lower priority level number will have priority over a channel with higher priority level number. A
priority level is enabled by writing the Priority Level x Enable bit in the Control register(CTRL.LVLENx) to one, for the
corresponding level.
Within each priority level the DMAC's arbiter can be configured to prioritize statically or dynamically. For the arbiter to
perform static arbitration within a priority level, the Level x Round-Robin Scheduling Enable bit in the Priority Control 0
register (PRICTRL0.RRLVLENx) has to be written to zero. When static arbitration is enabled (PRICTRL0.RRLVLENx is
zero), the arbiter will prioritize a low channel number over a high channel number as shown in Figure 18-5. When using
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the static scheme there is a risk of high channel numbers never being granted access as the active channel. This can be
avoided using a dynamic arbitration scheme.
Figure 18-5. Static Priority
Lowest Channel
Channel 0
Highest Priority
.
.
.
Channel x
Channel x+1
.
.
.
Highest Channel
Channel N
Lowest Priority
The dynamic arbitration scheme available in the DMAC is round-robin. Round-robin arbitration is enabled by writing
PRICTRL0.RRLVLENx to one, for a given priority level x. With the round-robin scheme, the channel number of the last
channel being granted access will have the lowest priority the next time the arbiter has to grant access to a channel
within the same priority level, as shown in Figure 18-6. The channel number of the last channel being granted access as
the active channel, will be stored in the Level x Channel Priority Number bit group in the Priority Control 0
register(PRICTRL0.LVLPRIx), for the corresponding priority level.
Figure 18-6. Round-Robin Scheduling
Channel x last acknowledged request
Channel (x+1) last acknowledged request
Channel 0
Channel 0
.
.
.
.
.
.
Channel x
Channel x+1
.
.
.
Channel N
Lowest Priority
Highest Priority
Channel x
Channel x+1
Channel x+2
Lowest Priority
Highest Priority
.
.
.
Channel N
18.6.2.5 Data Transmission
Before the DMAC can perform a data transmission, a DMA channel has to be configured and enabled, its corresponding
transfer descriptor has to be initialized and the arbiter has to grant the DMA channel access as the active channel.
Once the arbiter has granted a DMA channel access as the active channel (refer to Figure 18-1) the transfer descriptor
for the DMA channel will be fetched from SRAM using the fetch bus, and stored in the internal memory for the active
channel. Depending on if it is a new or ongoing block transfer, the transfer descriptor will either be fetched from the
descriptor memory section (BASEADDR) or the write-back memory section (WRBADDR). By using the data transfer bus,
the DMAC will read the data from the current source address and write it to the current destination address. For further
details on how the current source and destination addresses are calculated, refer to “Addressing” on page 277.
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The arbitration procedure is performed after each burst transfer. If the current DMA channel is granted access again, the
block transfer counter (BTCNT) of the internal transfer descriptor will be decremented with the number of beats in a
burst, and the active channel will perform a new burst transfer. If a different DMA channel than the current active channel
is granted access, the BTCNT of the internal transfer descriptor will be decremented with the number of beats in a burst.
The block transfer counter value will be written to the write-back section before the transfer descriptor of the newly
granted DMA channel is fetched into the internal memory of the active channel. The optional output event, Beat, will be
generated if configured and enabled.
When a block transfer has come to its end, BTCNT has reached zero, the Valid bit in the Block Transfer Control register
will be written to zero in the internal transfer descriptor for the active channel before the entire transfer descriptor is
written to the write-back memory. The optional interrupts, Channel Transfer Complete and Channel Suspend, and the
optional output event, Block, will be generated if configured and enabled. If it was the last block transfer in a transaction,
Next Address (DESCADDR) register will hold the value 0x00000000, and the DMA channel will either be suspended or
disabled, depending on the configuration in the Block Action bit group in the Block Transfer Control
register(BTCTRL.BLOCKACT). If the transaction has further block transfers pending, DESCADDR will hold the SRAM
address to the next transfer descriptor to be fetched. The DMAC will fetch the next descriptor into the internal memory of
the active channel and write its content to the write-back section for the channel, before the arbiter gets to choose the
next active channel.
18.6.2.6 Transfer Triggers and Actions
A DMA transfer can be started only when a DMA transfer request is detected. A transfer request can be triggered from
software, from peripheral, or from an event. There are dedicated Trigger Source selections for each DMA Channel
Control B (CHCTRLB.TRIGSRC).
The trigger actions are available in the Trigger Action bit group in the Channel Control B register (CHCTRLB.TRIGACT).
By default, a trigger starts a block transfer operation. If a single descriptor is defined for a channel, the channel is
automatically disabled when a block transfer is complete. If a list of linked descriptors is defined for a channel, the
channel is automatically disabled if the last descriptor in the list is executed or the channel will be waiting for the next
block transfer trigger if the list still has descriptors to execute. When enabled again, the channel will wait for the next
block transfer trigger. It is also possible to select the trigger to start beat or transaction transfers instead of a block
transfer.
If the trigger source generates a transfer request during an ongoing transfer, this will be kept pending
(CHSTATUS.PEND is one), and the transfer can start when the ongoing one is done. Only one pending transfer can be
kept, and so if the trigger source generates more transfer requests when one is already pending, these will be lost. All
channels pending status flags are also available in the Pending Channels register (PENDCH).
When the transfer starts, the corresponding Channel Busy status flag is set in Channel Status register
(CHSTATUS.BUSY). When the trigger action is complete, the Channel Busy status flag is cleared. All channels busy
status flags are also available in the Busy Channels register (BUSYCH) in DMAC.
Figure 18-7 on page 277 shows an example where triggers are used with two linked block descriptors.
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Figure 18-7. Trigger Action and Transfers
Beat Trigger Action
CHENn
Trigger Lost
Trigger
PENDCHn
BUSYCHn
Block Transfer
Data Transfer
BEAT
Block Transfer
BEAT
BEAT
BEAT
BEAT
BEAT
BEAT
BEAT
BEAT
BEAT
Block Trigger Action
CHENn
Trigger Lost
Trigger
PENDCHn
BUSYCHn
Block Transfer
Data Transfer
BEAT
Block Transfer
BEAT
BEAT
BEAT
Transaction Trigger Action
CHENn
Trigger Lost
Trigger
PENDCHn
BUSYCHn
Block Transfer
Data Transfer
BEAT
Block Transfer
BEAT
BEAT
BEAT
18.6.2.7 Addressing
For the DMAC to know from where to where it should transfer the data, each block transfer needs to have a source and
destination address defined. The source address can be set by writing the Transfer Source Address (SRCADDR)
register, and the destination address can be set by writing the Transfer Destination Address (SRCADDR) register.
The addressing of this DMAC module can be static or incremental, for either source or destination of a block transfer, or
both.
Incrementation for the source address of a block transfer is enabled by writing the Source Address Incrementation
Enable bit in the Block Transfer Control register (BTCTRL.SRCINC) to one. The step size of the incrementation is
configurable and can be chosen by writing the Step Selection bit in the Block Transfer Control
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register(BTCTRL.STEPSEL) to one, and the Address Increment Step Size bit group in the Block Transfer Control
register (BTCTRL.STEPSIZE), to the desired step size. If BTCTRL.STEPSEL is zero, the step size for the source
incrementation will be the size of one beat.
When source address incrementation is configured (BTCTRL.SRCINC is one), SRCADDR must be set to the source
address of the last beat transfer in the block transfer. The source address should be calculated as follows:
SRCADDR = SRCADDR START + BTCNT ⋅ ( BEATSIZE + 1 ) ⋅ 2
STEPSIZE
, where BTCTRL.STEPSEL is one
SRCADDR = SRCADDR START + BTCNT ⋅ ( BEATSIZE + 1 )
, where BTCTRL.STEPSEL is zero
z
SRCADDRSTART is the source address of the first beat transfer in the block transfer
z
BTCNT is the initial number of beats remaining in the block transfer
z
BEATSIZE is the configured number of bytes in a beat
z
STEPSIZE is the configured number of beats for each incrementation
Figure 18-8 shows an example where DMA channel 0 is configured to increment the source address by one beat
(BTCTRL.SRCINC is one) after each beat transfer, and DMA channel 1 is configured to increment source address by two
beats (BTCTRL.SRCINC is one, BTCTRL.STEPSEL is one, and BTCTRL.STEPSIZE is 0x1). As the destination address
for both channels are peripherals, destination incrementation is disabled(BTCTRL.DSTINC is zero).
Figure 18-8. Source Address Increment
SRC Data Buffer
a
b
c
d
e
DMA Channel 0
DMA Channel 1
{a,b}
{c,e}
PERIPHERAL 0
PERIPHERAL 1
f
Incrementation for the destination address of a block transfer is enabled by writing the Destination Address
Incrementation Enable bit in the Block Transfer Control register (BTCTRL.DSTINC) to one. The step size of the
incrementation is configurable and can be chosen by writing BTCTRL.STEPSEL to zero, and BTCTRL.STEPSIZE to the
desired step size. If BTCTRL.STEPSEL is one, the step size for the destination incrementation will be the size of one
beat.
When destination address incrementation is configured (BTCTRL.DSTINC is one), SRCADDR must be set to the
destination address of the last beat transfer in the block transfer. The destination address should be calculated as
follows:
DSTADDR = DSTADDR START + BTCNT ⋅ ( BEATSIZE + 1 ) ⋅ 2
STEPSIZE
, where BTCTRL.STEPSEL is zero
DSTADDR = DSTADDR START + BTCNT ⋅ ( BEATSIZE + 1 )
, where BTCTRL.STEPSEL is one
z
DSTADDRSTART is the destination address of the first beat transfer in the block transfer
z
BTCNT is the initial number of beats remaining in the block transfer
z
BEATSIZE is the configured number of bytes in a beat
z
STEPSIZE is the configured number of beats for each incrementation
Figure 18-9 shows an example where DMA channel 0 is configured to increment destination address by one beat
(BTCTRL.DSTINC is one) and DMA channel 1 is configured to increment destination address by two beats
(BTCTRL.DSTINC is one, BTCTRL.STEPSEL is zero, and BTCTRL.STEPSIZE is 0x1). As the source address for both
channels are peripherals, source incrementation is disabled(BTCTRL.SRCINC is zero).
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Figure 18-9. Destination Address Increment
DST Data Buffer
a
PERIPHERAL 0
PERIPHERAL 1
{a,b}
{c,d}
DMA Channel 0
DMA Channel 1
b
c
d
18.6.2.8 Error Handling
If a bus error is received from AHB slave during a DMA data transfer, the corresponding active channel is disabled and
the corresponding Channel Transfer Error Interrupt flag in the Channel Interrupt Status and Clear register
(CHINTFLAG.TERR) is set. If transfer error interrupt is enabled, optional error interrupt is generated. The transfer
counter will not be decremented and its current value is written-back in the write-back memory section before the channel
is disabled.
When the DMAC fetches an invalid descriptor (BTCTRL.VALID is zero) or when the channel is resumed and the DMA
fetches the next descriptor with null address (DESCADDR is 0x00000000), the corresponding channel operation is
suspended, the Channel Suspend Interrupt Flag in the Channel Interrupt Flag Status and Clear register
(CHINTFLAG.SUSP) is set and the Channel Fetch Error bit in the Channel Status register (CHSTATUS.FERR) is set. If
enabled, optional suspend interrupt is generated.
18.6.3 Additional Features
18.6.3.1 Linked Descriptors
A transaction can either consist of a single block transfer, or it can consist of several block transfers. When a transaction
consist of several block transfers it is called linked descriptors.
Figure 18-3 shows how linked descriptors work. When the first block transfer is completed on DMA channel 0, the DMAC
fetches the next transfer descriptor which is pointed to by the value stored in the Next Descriptor Address (DESCADDR)
register, in the first transfer descriptor. Fetching the next transfer descriptor (DESCADDR) is continued until the last
transfer descriptor. When the block transfer for the last transfer descriptor is executed and DESCADDR=0x00000000,
the transaction is terminated. For further details on how the next descriptor is fetched from SRAM, refer to “Data
Transmission” on page 275.
Adding Descriptor to the End of a List
To add a new descriptor at the end of the descriptor list, create the descriptor in SRAM, with DESCADDR=0x00000000
indicating it is the new last descriptor in the list, and modify the DESCADDR value of the current last descriptor to the
address of the newly created descriptor.
Modifying a Descriptor in a List
In order to add descriptors to a list, the following actions must be performed:
1.
Before enabling a channel, the Suspend interrupt must be enabled
2.
Reserve memory space addresses to configure a new descriptor
3.
Configure the new descriptor
z
Set the next descriptor address (DESCADDR)
z
Set the destination address (DSTADDR)
z
Set the source address (SRCADDR)
z
Configure the block transfer control (BTCTRL) including
z
Optionally enable the Suspend block action
z
Set the descriptor VALID bit
4.
In the existing list and for the descriptor which has to be updated, set the VALID bit to zero
5.
Read DESCADDR from the Write-Back memory
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z
z
6.
If the DMA has not already fetched the descriptor which requires changes:
z
Update the DESCADDR location of the descriptor from the List
z
Optionally clear the Suspend block action
z
Set the descriptor VALID bit to one
z
Optionally enable the Resume software command
If the DMA is executing the same descriptor as the one which requires changes:
z
Set the Channel Suspend software command and wait for the Suspend interrupt
z
Update the Write-Back next descriptor address (DESCRADDR)
z
Clear the interrupt sources and set the Resume software command
z
Update the DESCADDR location of the descriptor from the List
z
Optionally clear the Suspend block action
z
Set the descriptor VALID bit to one
Go to step 3 if needed
Adding a Descriptor Between Existing Descriptors
To insert a descriptor C between 2 existing descriptors (A & B), the descriptor currently executed by the DMA must be
identified.
1.
If DMA is executing descriptor B, descriptor C cannot be inserted.
2.
If DMA has not started to execute descriptor A, follow the steps:
3.
a.
Set the descriptor A VALID bit to 0
b.
Set the DESCADDR value of descriptor A to point descriptor C instead of descriptor B
c.
Set the DESCADDR value of descriptor C to point descriptor B
d.
Set the descriptor A VALID bit to 1.
If DMA is executing descriptor A,
a.
Apply the software suspend command to the channel and
b.
Perform steps 2a through 2d
Apply the software resume command to the channel.
18.6.3.2 Channel Suspend
The channel operation can be suspended at anytime by software, by setting the Suspend command in Command bit field
of Channel Control B register (CHCTRLB.CMD). When the ongoing burst transfer is completed, the channel operation is
suspended and the suspend command is automatically cleared.
It is also possible to suspend a channel operation after a block transfer completes. The software must set the Suspend
Block Action in the corresponding Block Transfer Control location (BTCTRL.BLOCKACT). When the block transfer is
completed, the channel operation is suspended. The channel is kept enabled, can receive transfer triggers, but it will be
removed from the arbitration scheme. The channel will automatically suspend the operation if an invalid transfer control
descriptor is fetched from system memory (BTCTRL.VALID=0). The Channel Fetch Error bit in the Channel Status
register (CHSTATUS.FERR) is set when an invalid descriptor is fetched. Only an enabled channel can be suspended. If
the channel is disabled when suspended, the internal suspend command is cleared. When suspended, the Channel
Suspend Interrupt flag in the Channel Interrupt Status and Clear register (CHINTFLAG.SUSP) is set and optional
suspend interrupt is generated.
For more details on transfer descriptors, refer to “Transfer Descriptors” on page 272.
18.6.3.3 Channel Resume and Next Suspend Skip
A channel operation can be resumed by software by setting the Resume command in Command bitfield of Channel
Control B register (CHCTRLB.CMD). If the channel is already suspended, the channel operation resumes from where it
previously stopped when the Resume command is detected. When the Resume command is issued before the channel
is suspended, the next suspend action is skipped and the channel continues the normal operation.
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Figure 18-10.Channel Suspend/Resume Operation
CHENn
Descriptor 0
(suspend disabled)
Memory Descriptor
Descriptor 1
(suspend enabled)
Descriptor 2
(suspend enabled)
Descriptor 3
(last)
Channel
suspended
Fetch
Transfer
Block
Transfer 0
Block
Transfer 1
Block
Transfer 2
Block
Transfer 3
Resume Command
Suspend skipped
18.6.3.4 Event Input Actions
The event input actions are available only for channels supporting event inputs. For details on channels with event input
support, refer to Table 22-6 and Table 22-4.
The Event Actions bits in the Channel Control B register (CHCTRLB.EVACT) specify the actions the DMA will take on an
input event. Before using event actions, the event controller must be configured first and the corresponding Channel
Event Input Enable bit (CHCTRLB.EVIE) must be set. The DMA supports only resynchronized events. For details on how
to configure the resynchronized event path, refer to the Event System.
Normal transfer: When this event action is selected for a channel, the event input is used to trigger a beat or burst
transfer on peripherals.
The transfer trigger is selected by setting the Trigger Source bits in Channel Control B register to zero
(CHCTRLB.TRIGSRC). The event is acknowledged as soon as the event is received. When received, the Channel
Pending status bit is set (CHSTATUS.PEND). If the event is received while the channel is pending, the event trigger is
lost. Figure 18-11 shows an example where beat transfers are enabled by internal events.
Figure 18-11.Beat Event Trigger Action
CHENn
Peripheral Trigger
Trigger Lost
Event
PENDCHn
BUSYCHn
Block Transfer
Data Transfer
BEAT
Block Transfer
BEAT
BEAT
BEAT
BEAT
BEAT
Periodic transfers: When this event action is selected for a channel, the event input is used to trigger a transfer on
peripherals with pending transfer requests. This type of event is intended to be used with peripheral triggers for example,
for timed communication protocols or periodic transfers between peripherals, as examples. The peripheral trigger is
selected by the Trigger Source bits in the Channel Control B register (CHCTRLB.TRIGSRC).
The event is acknowledged as soon as the event is received. The peripheral trigger request is stored internally when the
previous trigger action is completed (i.e. channel is not pending) and when an active event is received. If the peripheral
trigger is active, the DMA will wait for an event before the peripheral trigger is internally registered. When both event and
peripheral transfer trigger are active, the Channel Pending status bit is set (CHSTATUS.PEND). A software trigger will
now trigger a transfer.
Figure 18-12 shows an example where the peripheral beat transfers are enabled by periodic events.
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Figure 18-12.Periodic Event with Beat Peripheral Triggers
Trigger Lost
Trigger Lost
Event
Peripheral Trigger
PENDCHn
Block Transfer
Data Transfer
BEAT
Conditional transfer: When the conditional transfer event action is selected, the event input is used to trigger a
conditional transfer on peripherals with pending transfer requests. As example, this type of event can be used for
peripheral to peripheral transfers, where one peripheral is source of event and the second peripheral is source of DMA
trigger.
The peripheral Trigger Source must be set in Channel Control B register (CHCTRLB.TRIGSRC). Each peripheral trigger
is stored internally when the event is received. When the peripheral trigger is stored internally, the Channel Pending
status bit is set (CHSTATUS.PEND) and the event is acknowledged. A software trigger will now trigger a transfer.
Figure 18-13 shows an example where conditional event is enabled with peripheral beat trigger requests.
Figure 18-13.Conditional Event with Beat Peripheral Triggers
Event
Peripheral Trigger
PENDCHn
Data Transfer
Block Transfer
BEAT
BEAT
Conditional block transfer: When the conditional block event action is selected, the event input is used to trigger a
conditional block transfer on peripherals. The peripheral Trigger Source must be set in Channel Control B register
(CHCTRLB.TRIGSRC).
Before starting transfers within a block, an event must be received. When received, the event is acknowledged when the
block transfer is completed. A software trigger will trigger a transfer.
Figure 18-14 shows an example where conditional event block transfer is enabled with peripheral beat trigger requests.
Figure 18-14.Conditional Block Transfer with Beat Peripheral Triggers
Event
Peripheral Trigger
PENDCHn
Block Transfer
Data Transfer
Block Transfer
BEAT
BEAT
BEAT
BEAT
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Channel suspend: When the channel suspend event action is selected, the event input is used to suspend an ongoing
channel operation. The event is acknowledged when the current AHB access is completed. For further details on channel
suspend, refer to “Channel Suspend” on page 280.
Channel resume: When the channel resume event action is selected, the event input is used to resume a suspended
channel operation. The event is acknowledged as soon as the event is received and the Channel Suspend Interrupt Flag
(CHINTFLAG.SUSP) is cleared. For further details on channel suspend, refer to “Channel Suspend” on page 280.
Skip next block suspend: This event can be used to skip the next block suspend action. If the channel is suspended
before the event rises, the channel operation is resumed and the event is acknowledged. If the event rises before a
suspend block action is detected, the event is kept until the next block suspend detection. When the block transfer is
completed, the channel continues the operation (not suspended) and the event is acknowledged.
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18.6.3.5 Event Output Selections
The event output selections are available only for channels supporting event outputs. The pulse width of an event output
from a channel is one AHB clock cycle.
The Channel Event Output Enable can be set in Control B register (CHCTRLB.EVOE). The Event Output Selection is
available in each Descriptor Block Control location (BTCTRL.EVOSEL). It is possible to generate events after each beat,
burst or block transfer. To enable an event when the transaction is complete, the block event selection must be set in the
last transfer descriptor only. Figure 18-15 shows an example where the event output generation is enabled in the first
block transfer, and disabled in the second block.
Figure 18-15.Event Output Generation
Beat Event Output
Block Transfer
Data Transfer
Block Transfer
BEAT
BEAT
BEAT
BEAT
Event Output
Block Event Output
Block Transfer
Data Transfer
BEAT
Block Transfer
BEAT
BEAT
BEAT
Event Output
18.6.3.6 Aborting Transfers
Transfers on any channel can be gracefully aborted by software, by disabling the corresponding DMA channel. It is also
possible to abort all ongoing or pending transfers, by disabling the DMAC.
When DMAC disable request is detected:
z
Active channel with ongoing transfers will be disabled when the ongoing beat access is completed and the WriteBack memory section is updated. This prevents transfer corruption before the channel is disabled.
z
All other enabled channels will be disabled in the next clock cycle.
The corresponding Channel Enable bit in the Channel Control A register (CHCTRLA.ENABLE) is read as zero when the
channel is disabled.
The corresponding DMAC Enable bit in the Control register (CTRL.DMAENABLE) is read as zero when the entire DMAC
module is disabled.
18.6.3.7 CRC Operation
A cyclic redundancy check (CRC) is an error detection technique used to find accidental errors in data. It is commonly
used to determine whether the data during a transmission, or data present in data and programme memories has been
corrupted or not. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be
appended to the data and used as a checksum. When the same data are later received or read, the device or application
repeats the calculation. If the new CRC result does not match the one calculated earlier, the block contains a data error.
The application will then detect this and may take a corrective action, such as requesting the data to be sent again or
simply not using the incorrect data.
Typically, a CRC-n applied to a data block of arbitrary length will detect any single error burst not longer than n bits (any
single alteration that spans no more than n bits of the data), and will detect the fraction 1-2-n of all longer error bursts. The
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CRC module in DMAC supports two commonly used CRC polynomials: CRC-16 (CRC-CCITT) and CRC-32 (IEEE
802.3).
z
z
CRC-16:
z
Polynomial: x16 + x12 + x5+1
z
Hex value: 0x1021
CRC-32:
z
Polynomial: x32 +x26+x23 +x22 +x16 +x12 +x11 +x10 +x8 +x7 +x5 +x4 +x2 +x+1
z
Hex value: 0x04C11DB7
The data source for the CRC module must be selected in software as either the DMA channels or the APB bus interface.
The CRC module then takes data input from the selected source and generates a checksum based on these data. The
checksum is available in the CRC Checksum register (CRCCHKSUM). When CRC-32 polynomial is used, the final
checksum read is bit reversed and complemented, as shown in Figure 18-16 on page 285.
The CRC polynomial to be used is configurable, and the default setting is CRC-16. The CRC module operates on byte
only. When the DMA is used as data source for the CRC module, the DMA channel beat size setting will be used. When
used with APB bus interface, the application must set the CRC Beat Size bit field of CRC Control register
(CRCCTRL.CRCBEATSIZE). 8-, 16- or 32-bit bus transfer access type is supported. The corresponding number of bytes
will be written in the CRCDATAIN register and the CRC module will operate on the input data in a byte by byte manner.
Figure 18-16.CRC Generator Block Diagram
DMAC
Channels
CRCDATAIN
CRCCTRL
8
16
8
CRC-16
32
CRC-32
crc32
CHECKSUM
bit-reverse +
complement
Checksum
read
CRC on DMA data: CRC-16 or CRC-32 calculations can be performed on data passing through any DMA channel. Once
a DMA channel is selected as the source, the CRC module will continuously generate the CRC on the data passing
through the DMA channel. The checksum is available for readout once the DMA transaction is completed or aborted. A
CRC can also be generated on SRAM, Flash or I/O memory by passing these data through a DMA channel. If the latter
is done, the destination register for the DMA data can be the data input (CRCDATAIN) register in the CRC module.
CRC using the I/O interface: Before using the CRC module with the I/O interface, the application must set the CRC
Beat Size bits in the CRC Control register (CRCCTRL.CRCBEATSIZE). 8/16/32-bit bus transfer type can be selected.
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CRC can be performed on any data by loading them into the CRC module using the CPU and writing the data to the
CRCDATAIN register. Using this method, an arbitrary number of bytes can be written to the register by the CPU, and
CRC is done continuously for each byte. This means if a 32-bit data is written to the CRCDATAIN register the CRC
module takes 4 cycles to calculate the CRC. The CRC complete is signaled by the CRCBUSY bit in the CRCSTATUS
register. New data can be written only when CRCBUSY flag is not set.
18.6.4 DMA Operation
Not applicable.
18.6.5 Interrupts
The DMAC has the following interrupt sources:
z
Transfer Complete (TCMPL): Indicates that a block transfer is completed on the corresponding channel. Refer to
“Data Transmission” on page 275 for details.
z
Transfer Error (TERR): Indicates that a bus error has occurred during a burst transfer, or that an invalid descriptor
has been fetched. Refer to “Error Handling” on page 279 for details.
z
Channel Suspend (SUSP): Indicates that the corresponding channel has been suspended. Refer to “Channel
Suspend” on page 280 and “Data Transmission” on page 275 for details.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Channel Interrupt Flag Status and
Clear (CHINTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by
writing a one to the corresponding bit in the Channel Interrupt Enable Set (CHINTENSET) register, and disabled by
writing a one to the corresponding bit in the Channel Interrupt Enable Clear (CHINTENCLR) register. An interrupt request
is generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains
active until the interrupt flag is cleared, the interrupt is disabled, the DMAC is reset or the corresponding DMA channel is
reset. See CHINTFLAG for details on how to clear interrupt flags. All interrupt requests are ORed together on system
level to generate one combined interrupt request to the NVIC. Refer to “Nested Vector Interrupt Controller” on page 29
for details.
The user must read the Channel Interrupt Status (INTSTATUS) register to identify the channels with pending interrupts
and must read the Channel Interrupt Flag Status and Clear (CHINTFLAG) register to determine which interrupt condition
is present for the corresponding channel. It is also possible to read the Interrupt Pending register (INTPEND), which
provides the lowest channel number with pending interrupt and the respective interrupt flags.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to “Nested Vector Interrupt
Controller” on page 29 for details.
18.6.6 Events
The DMAC can generate the following output events:
z
Channel (CH): Generated when a block transfer for a given channel has been completed, or when a beat transfer
within a block transfer for a given channel has been completed. Refer to “Event Output Selections” on page 284 for
details.
Writing a one to the Channel Control B Event Output Enable bit (CHCTRLB.EVOE) enables the corresponding output
event configured in the Event Output Selection bit group in the Block Transfer Control register (BTCTRL.EVOSEL).
Writing a zero to CHCTRLB.EVOE disables the corresponding output event. Refer to “EVSYS – Event System” on page
400 for details on configuring the event system.
The DMAC can take the following actions on an input event:
z
Transfer and Periodic Transfer Trigger (TRIG): normal transfer or periodic transfers on peripherals are enabled
z
Conditional Transfer Trigger (CTRIG): conditional transfers on peripherals are enabled
z
Conditional Block Transfer Trigger (CBLOCK): conditional block transfers on peripherals are enabled
z
Channel Suspend Operation (SUSPEND): suspend a channel operation
z
Channel Resume Operation (RESUME): resume a suspended channel operation
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z
Skip Next Block Suspend Action (SSKIP): skip the next block suspend transfer condition
Writing a one to the Channel Control B Event Input Enable bit (CHCTRLB.EVIE) enables the corresponding action on
input event. Writing a zero to this bit disables the corresponding action on input event. Note that several actions can be
enabled for incoming events. If several events are connected to the peripheral, any enabled action will be taken for any of
the incoming events. For further details on event input actions, refer to “Event Input Actions” on page 281. Refer to the
Event System chapter for details on configuring the event system.
18.6.7 Sleep Mode Operation
In standby sleep mode, the DMAC will be internally disabled, but maintains its current configuration.
18.6.8 Synchronization
Not applicable.
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18.7
Register Summary
Table 18-1. DMAC Register Summary
Offset
0x00
0x01
0x02
0x03
Name
CTRL
CRCCTRL
Bit
Pos.
7:0
15:8
CRCDATAIN[7:0]
23:16
CRCDATAIN[23:16]
0x07
31:24
CRCDATAIN[31:24]
0x08
7:0
CRCCHKSUM[7:0]
0x0B
15:8
CRCCHKSUM[15:8]
23:16
CRCCHKSUM[23:16]
31:24
CRCCHKSUM[31:24]
0x0C
CRCSTATUS
7:0
0x0D
DBGCTRL
7:0
0x0E
QOSCTRL
7:0
0x0F
Reserved
0x10
7:0
0x11
15:8
0x12
SWTRIGCTRL
LVLEN0
CRCSRC[5:0]
CRCDATAIN[15:8]
CRCCHKSUM
LVLEN1
15:8
7:0
0x09
LVLEN2
CRCPOLY[1:0]
15:8
0x0A
SWRST
LVLEN3
0x05
CRCDATAIN
DMAENABLE
7:0
0x04
0x06
CRCENABLE
CRCBEATSIZE[1:0]
CRCZERO
DBGRUN
DQOS
SWTRIG7
SWTRIG6
SWTRIG5
FQOS
SWTRIG4
WRQOS
SWTRIG3
SWTRIG2
SWTRIG1
SWTRIG0
SWTRIG11
SWTRIG10
SWTRIG9
SWTRIG8
23:16
0x13
31:24
0x14
7:0
RRLVLEN0
LVLPRI0[3:0]
15:8
RRLVLEN1
LVLPRI1[3:0]
23:16
RRLVLEN2
LVLPRI2[3:0]
31:24
RRLVLEN3
LVLPRI3[3:0]
0x15
0x16
PRICTRL0
0x17
0x18
...
0x1F
0x20
0x21
Reserved
INTPEND
0x22
Reserved
0x23
Reserved
0x24
0x25
0x26
7:0
15:8
PEND
BUSY
FERR
7:0
CHINT7
CHINT6
CHINT5
CHINT4
SUSP
TCMPL
TERR
CHINT3
CHINT2
CHINT1
CHINT0
CHINT11
CHINT10
CHINT9
CHINT8
BUSYCH3
BUSYCH2
BUSYCH1
BUSYCH0
BUSYCH11
BUSYCH10
BUSYCH9
BUSYCH8
23:16
31:24
0x28
7:0
0x29
15:8
0x2B
ID[3:0]
15:8
INTSTATUS
0x27
0x2A
CRCBUSY
BUSYCH
BUSYCH7
BUSYCH6
BUSYCH5
BUSYCH4
23:16
31:24
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Offset
Name
Bit
Pos.
0x2C
7:0
0x2D
15:8
0x2E
PENDCH
0x2F
PENDCH7
PENDCH6
PENDCH5
PENDCH4
PENDCH3
PENDCH2
PENDCH1
PENDCH0
PENDCH11
PENDCH10
PENDCH9
PENDCH8
LVLEX3
LVLEX2
LVLEX1
LVLEX0
ENABLE
SWRST
23:16
31:24
0x30
7:0
0x31
15:8
ACTIVE
ABUSY
ID[4:0]
0x32
23:16
BTCNT[7:0]
0x33
31:24
BTCNT[15:8]
0x34
7:0
BASEADDR[7:0]
0x35
15:8
BASEADDR[15:8]
0x36
BASEADDR
23:16
BASEADDR[23:16]
0x37
31:24
BASEADDR[31:24]
0x38
7:0
WRBADDR[7:0]
0x39
0x3A
WRBADDR
0x3B
0x3C
...
0x3E
15:8
WRBADDR[15:8]
23:16
WRBADDR[23:16]
31:24
WRBADDR[31:24]
Reserved
0x3F
CHID
7:0
0x40
CHCTRLA
7:0
0x41
...
0x43
Reserved
0x44
7:0
0x45
15:8
0x46
CHCTRLB
0x47
23:16
ID[3:0]
LVL[1:0]
EVOE
EVIE
EVACT[2:0]
TRIGSRC[5:0]
TRIGACT[1:0]
31:24
0x48
...
0x4B
Reserved
CMD[1:0]
0x4C
CHINTENCLR
7:0
SUSP
TCMPL
TERR
0x4D
CHINTENSET
7:0
SUSP
TCMPL
TERR
0x4E
CHINTFLAG
7:0
SUSP
TCMPL
TERR
0x4F
CHSTATUS
7:0
FERR
BUSY
PEND
Table 18-2. DMAC SRAM Register Summary - Descriptor/Write-Back Memory Section
Offset
0x00
0x01
0x02
0x03
Name
BTCTRL
BTCNT
Bit
Pos.
7:0
15:8
BLOCKACT[1:0]
STEPSIZE[2:0]
STEPSEL
DSTINC
7:0
BTCNT[7:0]
15:8
BTCNT[15:8]
EVOSEL[1:0]
SRCINC
VALID
BEATSIZE[1:0]
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Offset
Name
Bit
Pos.
0x04
7:0
SRCADDR[7:0]
0x05
15:8
SRCADDR[15:8]
23:16
SRCADDR[23:16]
31:24
SRCADDR[31:24]
0x06
SRCADDR
0x07
0x08
7:0
DSTADDR[7:0]
0x09
15:8
DSTADDR[15:8]
0x0A
DSTADDR
23:16
DSTADDR[23:16]
0x0B
31:24
DSTADDR[31:24]
0x0C
7:0
DESCADDR[7:0]
0x0D
0x0E
0x0F
DESCADDR
15:8
DESCADDR[15:8]
23:16
DESCADDR[23:16]
31:24
DESCADDR[31:24]
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18.8
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit quarters
and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Write-protection is denoted by
the Write-Protected property in each individual register description. Please refer to “Register Access Protection” on page
269 for details.
Some registers are enable-protected, meaning they can only be written when the DMAC is disabled. Enable-protection is
denoted by the Enable-Protected property in each individual register description.
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18.8.1 DMAC Registers
18.8.1.1 Control
Name:
CTRL
Offset:
0x00
Reset:
0x0000
Property:
Enable-Protected, Write-Protected
Bit
15
14
13
12
11
10
9
8
LVLEN3
LVLEN2
LVLEN1
LVLEN0
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
CRCENABLE
DMAENABLE
SWRST
Access
R
R
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
z
Bits 15:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 11:8 – LVLENx [x=3..0]: Priority Level x Enable
0: Transfer requests for Priority level x will not be handled.
1: Transfer requests for Priority level x will be handled.
When this bit is set, all requests with the corresponding level will be fed into the arbiter block. When cleared, all
requests with the corresponding level will be ignored.
For details on arbitration schemes, refer to “Arbitration” on page 274 section.
These bits are not enable-protected.
z
Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 2 – CRCENABLE: CRC Enable
0: The CRC module is disabled.
1: The CRC module is enabled.
Writing a zero to this bit will disable the CRC module if the CRC Status Busy bit in the CRC Status register (CRCSTATUS.CRCBUSY) is zero. If the CRCSTATUS.CRCBUSY is one, the write will be ignored and the CRC module
will not be disabled.
Writing a one to this bit will enable the CRC module.
This bit is not enable-protected.
z
Bit 1 – DMAENABLE: DMA Enable
0: The peripheral is disabled.
1: The peripheral is enabled.
Writing a zero to this bit during an ongoing transfer, the bit will not be cleared until the internal data transfer buffer
is empty and the DMA transfer is aborted. The internal data transfer buffer will be empty once the ongoing burst
transfer is completed.
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Writing a one to this bit will enable the DMA module.
This bit is not enable-protected.
z
Bit 0 – SWRST: Software Reset
0: There is no reset operation ongoing.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit when both the DMAC and the CRC module are disabled (DMAENABLE and CRCENABLE
is zero), resets all registers in the DMAC, except DBGCTRL, to their initial state If either the DMAC or CRC module
is enabled, the reset request will be ignored and the DMAC will return an access error.
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18.8.1.2 CRC Control
Name:
CRCCTRL
Offset:
0x02
Reset:
0x0000
Property:
Enable-Protected, Write-Protected
Bit
15
14
13
12
11
10
9
8
CRCSRC[5:0]
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
CRCPOLY[1:0]
CRCBEATSIZE[1:0]
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
z
Bits 15:14 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 13:8 – CRCSRC[5:0]: CRC Input Source
These bits select the input source for generating the CRC, as shown in Table 18-3. The selected source is locked
until either the CRC generation is completed or the CRC module is disabled. This means the CRCSRC cannot be
modified when the CRC operation is ongoing. The lock is signaled by the CRCBUSY status bit. CRC generation
complete is generated and signaled from the selected source when used with the DMA channel.
Table 18-3. CRC Input Source
CRCSRC[5:0]
Name
0x0
NOACT
0x1
IO
0x2-0x1F
0x20-0x3F
Description
No action
I/O interface
Reserved
CHN
DMA channel n
z
Bits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 3:2 – CRCPOLY[1:0]: CRC Polynomial Type
These bits select the CRC polynomial type, as shown in Table 18-4.
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Table 18-4. CRC Polynomial Type
CRCPOLY[1:0]
Name
0x0
CRC16
CRC-16 (CRC-CCITT)
0x1
CRC32
CRC32 (IEEE 802.3)
0x2-0x3
z
Description
Reserved
Bits 1:0 – CRCBEATSIZE[1:0]: CRC Beat Size
These bits define the size of the data transfer for each bus access when the CRC is used with I/O interface, as
shown in Table 18-5.
Table 18-5. CRC Beat Size
CRCBEATSIZE[1:0]
Name
0x0
BYTE
0x1
HWORD
0x2
WORD
0x3
Description
Byte bus access
Half-word bus access
Word bus access
Reserved
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18.8.1.3 CRC Data Input
Name:
CRCDATAIN
Offset:
0x04
Reset:
0x00000000
Property:
Write-Protected
Bit
31
30
29
28
27
26
25
24
CRCDATAIN[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
CRCDATAIN[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
CRCDATAIN[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
CRCDATAIN[7:0]
Access
Reset
z
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:0 – CRCDATAIN[31:0]: CRC Data Input
These bits store the data for which the CRC checksum is computed. After the CRCDATAIN register has been written, the number of cycles for the new CRC checksum to be ready is dependent of the configuration of the CRC
Beat Size bit group in the CRC Control register(CRCCTRL.CRCBEATSIZE). Each byte needs one clock cycle to
be calculated.
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18.8.1.4 CRC Checksum
The CRCCHKSUM represents the 16- or 32-bit checksum value and the generated CRC.
Name:
CRCCHKSUM
Offset:
0x08
Reset:
0x00000000
Property:
Enable-Protected, Write-Protected
Bit
31
30
29
28
27
26
25
24
CRCCHKSUM[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
CRCCHKSUM[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
CRCCHKSUM[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
CRCCHKSUM[7:0]
Access
Reset
z
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:0 – CRCCHKSUM[31:0]: CRC Checksum
These bits store the generated CRC result. The 16 MSB bits are always read zero when CRC-16 is enabled.
These bits should only be read when CRC Module Busy bit in the CRC Status register (CRCSTATUS.BUSY) is
zero.
If CRC-16 is selected and CRCSTATUS.BUSY is zero (CRC generation is completed), this bit group will contain a
valid checksum.
If CRC-32 is selected and CRCSTATUS.BUSY is zero (CRC generation is completed), this bit group will contain a
valid reversed checksum. Bit 31 is swapped with bit 0, bit 30 with bit 1, etc.
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18.8.1.5 CRC Status
Name:
CRCSTATUS
Offset:
0x0C
Reset:
0x00
Property:
Write-Protected
Bit
7
6
5
4
3
2
1
0
CRCZERO
CRCBUSY
Access
R
R
R
R
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0
z
Bits 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 1 – CRCZERO: CRC Zero
This bit is cleared when a new CRC source is selected.
This bit is set when the CRC generation is complete and the CRC Checksum is zero.
z
Bit 0 – CRCBUSY: CRC Module Busy
When used with an I/O interface (CRCCTRL.CRCSRC is 0x1), this bit is cleared by writing a one to it.
When used with an I/O interface (CRCCTRL.CRCSRC is 0x1), this bit is set when the CRC Data Input (CRCDATAIN) register is written.
When used with a DMA channel (CRCCTRL.CRCSRC is 0x20 to 0x3F), this bit is cleared when the corresponding
DMA channel is disabled.
When used with a DMA channel (CRCCTRL.CRCSRC is 0x20 to 0x3F), this bit is set when the corresponding
DMA channel is enabled.
Writing a zero to this bit has no effect.
When used with an I/O interface(CRCCTRL.CRCSRC is 0x1), writing a one to this bit will clear the CRC Module
Busy bit.
When used with a DMA channel, writing a one to this bit has no effect.
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18.8.1.6 Debug Control
Name:
DBGCTRL
Offset:
0x0D
Reset:
0x00
Property:
Write-Protected
Bit
7
6
5
4
3
2
1
0
DBGRUN
Access
R
R
R
R
R
R
R
R/W
Reset
0
0
0
0
0
0
0
0
z
Bits 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 0 – DBGRUN: Debug Run
This bit is not reset by a software reset.
This bit controls the functionality when the CPU is halted by an external debugger.
0: The DMAC is halted when the CPU is halted by an external debugger.
1: The DMAC continues normal operation when the CPU is halted by an external debugger.
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18.8.1.7 QOS Control
Name:
QOSCTRL
Offset:
0x0E
Reset:
0x15
Property:
Enable-Protected, Write-Protected
Bit
7
6
5
4
3
DQOS[1:0]
2
1
FQOS[1:0]
0
WBQOS[1:0]
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
1
0
1
0
1
z
Bits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 5:4 – DQOS[1:0]: DATA Quality of Service
These bits define the SRAM quality of service of the DMAC DATA master. Refer to “SRAM Quality of Service” on
page 34.
z
Bits 3:2 – FQOS[1:0]: Fetch Quality of Service
These bits define the SRAM quality of service of the DMAC Fetch master. Refer to “SRAM Quality of Service” on
page 34.
z
Bits 1:0 – WBQOS[1:0]: WB Quality of Service
These bits define the SRAM quality of service of the DMAC WB master. Refer to “SRAM Quality of Service” on
page 34.
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18.8.1.8 Software Trigger Control
Name:
SWTRIGCTRL
Offset:
0x10
Reset:
0x00000000
Property:
Write-Protected
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
SWTRIG11
SWTRIG10
SWTRIG9
SWTRIG8
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
SWTRIG7
SWTRIG6
SWTRIG5
SWTRIG4
SWTRIG3
SWTRIG2
SWTRIG1
SWTRIG0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Access
Reset
z
Bits 31:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 11:0 – SWTRIGx [x=11..0]: Channel x Software Trigger
This bit is cleared when the Channel Pending bit in the Channel Status register (CHSTATUS.PEND) for the corresponding channel is set, or by writing a one to it.
This bit is set if CHSTATUS.PEND is already one, when writing a one to this bit.
Writing a zero to this bit will clear the bit.
Writing a one to this bit will generate a DMA software trigger on channel x, if CHSTATUS.PEND is zero for channel
x.
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18.8.1.9 Priority Control 0
Name:
PRICTRL0
Offset:
0x14
Reset:
0x00000000
Property:
Write-Protected
Bit
31
30
29
28
27
26
RRLVLEN3
Access
25
24
LVLPRI3[3:0]
R/W
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
RRLVLEN2
Access
LVLPRI2[3:0]
R/W
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
RRLVLEN1
Access
LVLPRI1[3:0]
R/W
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
RRLVLEN0
Access
Reset
z
LVLPRI0[3:0]
R/W
R
R
R
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 31 – RRLVLEN3: Level 3 Round-Robin Scheduling Enable
0: Static scheduling scheme for channels with level 3 priority.
1: Round-robin scheduling scheme for channels with level 3 priority.
For details on scheduling schemes, refer to “Arbitration” on page 274.
z
Bits 30:28 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 27:24 – LVLPRI3[3:0]: Level 3 Channel Priority Number
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN3 is one) for priority level 3, this register holds the
channel number of the last DMA channel being granted access as the active channel with priority level 3.
When static arbitration is enabled (PRICTRL0.RRLVLEN3 is zero) for priority level 3, and the value of this bit
group is non-zero, it will not affect the static priority scheme. If the value of this bit group is x, channel x will have
the highest priority. The priority will decrease as the channel number increases from x to n, where n is the maximum number of channels. Channel n has higher priority than channel 0, and the priority will continue to decrease
from channel 0 to channel (x-1).
This bit group is not reset when round-robin scheduling gets disabled (PRICTRL0.RRLVLEN3 written to zero).
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z
Bit 23 – RRLVLEN2: Level 2 Round-Robin Scheduling Enable
0: Static scheduling scheme for channels with level 2 priority.
1: Round-robin scheduling scheme for channels with level 2 priority.
For details on scheduling schemes, refer to “Arbitration” on page 274.
z
Bits 22:20 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 19:16 – LVLPRI2[3:0]: Level 2 Channel Priority Number
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN2 is one) for priority level 2, this register holds the
channel number of the last DMA channel being granted access as the active channel with priority level 2.
When static arbitration is enabled (PRICTRL0.RRLVLEN2 is zero) for priority level 2, and the value of this bit
group is non-zero, it will not affect the static priority scheme. If the value of this bit group is x, channel x will have
the highest priority. The priority will decrease as the channel number increases from x to n, where n is the maximum number of channels. Channel n has higher priority than channel 0, and the priority will continue to decrease
from channel 0 to channel (x-1).
This bit group is not reset when round-robin scheduling gets disabled (PRICTRL0.RRLVLEN2 written to zero).
z
Bit 15 – RRLVLEN1: Level 1 Round-Robin Scheduling Enable
0: Static scheduling scheme for channels with level 1 priority.
1: Round-robin scheduling scheme for channels with level 1 priority.
For details on scheduling schemes, refer to “Arbitration” on page 274.
z
Bits 14:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 11:8 – LVLPRI1[3:0]: Level 1 Channel Priority Number
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN1 is one) for priority level 1, this register holds the
channel number of the last DMA channel being granted access as the active channel with priority level 1.
When static arbitration is enabled (PRICTRL0.RRLVLEN1 is zero) for priority level 1, and the value of this bit
group is non-zero, it will not affect the static priority scheme. If the value of this bit group is x, channel x will have
the highest priority. The priority will decrease as the channel number increases from x to n, where n is the maximum number of channels. Channel n has higher priority than channel 0, and the priority will continue to decrease
from channel 0 to channel (x-1).
This bit group is not reset when round-robin scheduling gets disabled (PRICTRL0.RRLVLEN1 written to zero).
z
Bit 7 – RRLVLEN0: Level 0 Round-Robin Scheduling Enable
0: Static scheduling scheme for channels with level 0 priority.
1: Round-robin scheduling scheme for channels with level 0 priority.
For details on scheduling schemes, refer to “Arbitration” on page 274.
z
Bits 6:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 3:0 – LVLPRI0[3:0]: Level 0 Channel Priority Number
When round-robin arbitration is enabled (PRICTRL0.RRLVLEN0 is one) for priority level 0, this register holds the
channel number of the last DMA channel being granted access as the active channel with priority level 0.
When static arbitration is enabled (PRICTRL0.RRLVLEN0 is zero) for priority level 0, and the value of this bit
group is non-zero, it will not affect the static priority scheme. If the value of this bit group is x, channel x will have
the highest priority. The priority will decrease as the channel number increases from x to n, where n is the maxi-
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mum number of channels. Channel n has higher priority than channel 0, and the priority will continue to decrease
from channel 0 to channel (x-1).
This bit group is not reset when round-robin scheduling gets disabled (PRICTRL0.RRLVLEN0 written to zero).
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18.8.1.10 Interrupt Pending
This register allows the user to identify the lowest DMA channel with pending interrupt.
Name:
INTPEND
Offset:
0x20
Reset:
0x0000
Property:
-
Bit
15
14
13
12
PEND
BUSY
FERR
Access
R
R
R
R
Reset
0
0
0
Bit
7
6
5
11
10
9
8
SUSP
TCMPL
TERR
R
R/W
R/W
R/W
0
0
0
0
0
4
3
2
1
0
ID[3:0]
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
z
Bit 15 – PEND: Pending
This bit is read one when the channel selected by Channel ID field (ID) is pending.
z
Bit 14 – BUSY: Busy
This bit is read one when the channel selected by Channel ID field (ID) is busy.
z
Bit 13 – FERR: Fetch Error
This bit is read one when the channel selected by Channel ID field (ID) fetched an invalid descriptor.
z
Bits 12:11 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 10 – SUSP: Channel Suspend
This bit is read one when the channel selected by Channel ID field (ID) has pending Suspend interrupt.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Channel ID (ID) Suspend interrupt flag.
z
Bit 9 – TCMPL: Transfer Complete
This bit is read one when the channel selected by Channel ID field (ID) has pending Transfer Complete interrupt.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Channel ID (ID) Transfer Complete interrupt flag.
z
Bit 8 – TERR: Transfer Error
This bit is read one when the channel selected by Channel ID field (ID) has pending Transfer Error interrupt.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Channel ID (ID) Transfer Error interrupt flag.
z
Bits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
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z
Bits 3:0 – ID[3:0]: Channel ID
These bits store the lowest channel number with pending interrupts. The number is valid if Suspend (SUSP),
Transfer Complete (TCMPL) or Transfer Error (TERR) bits are set. The Channel ID field is refreshed when a new
channel (with channel number less than the current one) with pending interrupts is detected, or when the application clears the corresponding channel interrupt sources. When no pending channels interrupts are available, these
bits will always return zero value when read.
When the bits are written, indirect access to the corresponding Channel Interrupt Flag register is enabled.
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18.8.1.11 Interrupt Status
Name:
INTSTATUS
Offset:
0x24
Reset:
0x00000000
Property:
-
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
CHINT11
CHINT10
CHINT9
CHINT8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
CHINT7
CHINT6
CHINT5
CHINT4
CHINT3
CHINT2
CHINT1
CHINT0
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
z
Bits 31:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 11:0 – CHINTx [x=11..0]: Channel x Pending Interrupt
This bit is set when Channel x has pending interrupt.
This bit is cleared when the corresponding Channel x interrupts are disabled or the interrupts sources are cleared.
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18.8.1.12 Busy Channels
Name:
BUSYCH
Offset:
0x28
Reset:
0x00000000
Property:
-
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
BUSYCH11
BUSYCH10
BUSYCH9
BUSYCH8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
BUSYCH7
BUSYCH6
BUSYCH5
BUSYCH4
BUSYCH3
BUSYCH2
BUSYCH1
BUSYCH0
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
z
Bits 31:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 11:0 – BUSYCHx [x=11..0]: Busy Channel x
This bit is cleared when the channel trigger action for DMA channel x is complete, when a bus error for DMA channel x is detected, or when DMA channel x is disabled.
This bit is set when DMA channel x starts a DMA transfer.
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18.8.1.13 Pending Channels
Name:
PENDCH
Offset:
0x2C
Reset:
0x00000000
Property:
-
Bit
31
30
29
28
27
26
25
24
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
PENDCH11
PENDCH10
PENDCH9
PENDCH8
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PENDCH7
PENDCH6
PENDCH5
PENDCH4
PENDCH3
PENDCH2
PENDCH1
PENDCH0
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
z
Bits 31:12 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 11:0 – PENDCHx [x=11..0]: Pending Channel x
This bit is cleared when trigger execution defined by channel trigger action settings for DMA channel x is started,
when a bus error for DMA channel x is detected or when DMA channel x is disabled. For details on trigger action
settings, refer to Table 18-7.
This bit is set when a transfer is pending on DMA channel x.
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18.8.1.14 Active Channel and Levels
Name:
ACTIVE
Offset:
0x30
Reset:
0x00000000
Property:
-
Bit
31
30
29
28
27
26
25
24
BTCNT[15:8]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
BTCNT[7:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
ABUSY
ID[4:0]
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
LVLEX3
LVLEX2
LVLEX1
LVLEX0
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
z
Bits 31:16 – BTCNT[15:0]: Active Channel Block Transfer Count
These bits hold the 16-bit block transfer count of the ongoing transfer. This value is stored in the active channel
and written back in the corresponding Write-Back channel memory location when the arbiter grants a new channel
access. The value is valid only when the active channel active busy flag (ABUSY) is set.
z
Bit 15 – ABUSY: Active Channel Busy
This bit is cleared when the active transfer count is written back in the Write-Back memory section.
This flag is set when the next descriptor transfer count is read from the Write-Back memory section.
z
Bits 14:13 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 12:8 – ID[4:0]: Active Channel ID
These bits hold the channel index currently stored in the active channel registers. The value is updated each time
the arbiter grants a new channel transfer access request.
z
Bits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
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z
Bits 3:0 – LVLEXx [x=3..0]: Level x Channel Trigger Request Executing
This bit is set when a level-x channel trigger request is executing or pending.
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18.8.1.15 Descriptor Memory Section Base Address
Name:
BASEADDR
Offset:
0x34
Reset:
0x00000000
Property:
Enable-Protected, Write-Protected
Bit
31
30
29
28
27
26
25
24
BASEADDR[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
BASEADDR[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
BASEADDR[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
BASEADDR[7:0]
Access
Reset
z
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:0 – BASEADDR[31:0]: Descriptor Memory Base Address
These bits store the Descriptor memory section base address. The value must be 128-bit aligned.
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18.8.1.16 Write-Back Memory Section Base Address
Name:
WRBADDR
Offset:
0x38
Reset:
0x00000000
Property:
Enable-Protected, Write-Protected
Bit
31
30
29
28
27
26
25
24
WRBADDR[31:24]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
WRBADDR[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
WRBADDR[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
WRBADDR[7:0]
Access
Reset
z
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bits 31:0 – WRBADDR[31:0]: Write-Back Memory Base Address
These bits store the Write-Back memory base address. The value must be 128-bit aligned.
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18.8.1.17 Channel ID
Name:
CHID
Offset:
0x3F
Reset:
0x00
Property:
-
Bit
7
6
5
4
3
2
1
0
ID[3:0]
Access
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
z
Bits 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 3:0 – ID[3:0]: Channel ID
These bits define the channel number that will be accessed. Before reading or writing a channel register, the channel ID bit group must be written first.
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18.8.1.18 Channel Control A
Name:
CHCTRLA
Offset:
0x40
Reset:
0x00
Property:
Enable-Protected, Write-Protected
Bit
7
6
5
4
3
2
1
0
ENABLE
SWRST
Access
R
R
R
R
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0
z
Bits 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 1 – ENABLE: Channel Enable
0: DMA channel is disabled.
1: DMA channel is enabled.
Writing a zero to this bit during an ongoing transfer, the bit will not be cleared until the internal data transfer buffer
is empty and the DMA transfer is aborted. The internal data transfer buffer will be empty once the ongoing burst
transfer is completed.
Writing a one to this bit will enable the DMA channel.
This bit is not enable-protected.
z
Bit 0 – SWRST: Channel Software Reset
0: There is no reset operation ongoing.
1: The reset operation is ongoing.
Writing a zero to this bit has no effect.
Writing a one to this bit resets the channel registers to their initial state. The bit can be set when the channel is disabled (ENABLE = 0). Writing a one to this bit will be ignored as long as the channel is enabled (ENABLE = 1). This
bit is automatically cleared when the reset is completed.
Writing a one to this bit when the corresponding DMA channel is disabled (ENABLE is zero), resets all registers for
the corresponding DMA channel to their initial state If the corresponding DMA channel is enabled, the reset
request will be ignored.
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18.8.1.19 Channel Control B
Name:
CHCTRLB
Offset:
0x44
Reset:
0x00000000
Property:
Enable-Protected, Write-Protected
Bit
31
30
29
28
27
26
25
24
CMD[1:0]
Access
R
R
R
R
R
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
TRIGACT[1:0]
Access
R/W
R/W
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
TRIGSRC[5:0]
Access
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
EVOE
EVIE
LVL[1:0]
EVACT[2:0]
Access
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
z
Bits 31:26 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 25:24 – CMD[1:0]: Software Command
These bits define the software commands, as shown in Table 18-6.
These bits are not enable-protected.
Table 18-6. Software Command
CMD[1:0]
Name
0x0
NOACT
0x1
SUSPEND
Channel suspend operation
0x2
RESUME
Channel resume operation
0x3
Description
No action
Reserved
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z
Bits 23:22 – TRIGACT[1:0]: Trigger Action
These bits define the trigger action used for a transfer, as shown in Table 18-7.
Table 18-7. Trigger Action
TRIGACT[1:0]
Name
0x0
BLOCK
Description
One trigger required for each block transfer
0x1
Reserved
0x2
BEAT
One trigger required for each beat transfer
0x3
TRANSACTION
One trigger required for each transaction
z
Bits 21:14 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 13:8 – TRIGSRC[5:0]: Peripheral Trigger Source
These bits define the peripheral trigger which is source of the transfer. For details on trigger selection and trigger
modes, refer to “Transfer Triggers and Actions” on page 276 and Table 18-7.
Table 18-8. Peripheral Trigger Source
Value
Name
Description
0x00
DISABLE
0x01
SERCOM0 RX
SERCOM0 RX Trigger
0x02
SERCOM0 TX
SERCOM0 TX Trigger
0x03
SERCOM1 RX
SERCOM1 RX Trigger
0x04
SERCOM1 TX
SERCOM1 TX Trigger
0x05
SERCOM2 RX
SERCOM2 RX Trigger
0x06
SERCOM2 TX
SERCOM2 TX Trigger
0x07
SERCOM3 RX
SERCOM3 RX Trigger
0x08
SERCOM3 TX
SERCOM3 TX Trigger
0x09
SERCOM4 RX
SERCOM4 RX Trigger
0x0A
SERCOM4 TX
SERCOM4 TX Trigger
0x0B
SERCOM5 RX
SERCOM5 RX Trigger
0x0C
SERCOM5 TX
SERCOM5 TX Trigger
0x0D
TCC0 OVF
TCC0 Overflow Trigger
0x0E
TCC0 MC0
TCC0 Match/Compare 0 Trigger
0x0F
TCC0 MC1
TCC0 Match/Compare 1 Trigger
0x10
TCC0 MC2
TCC0 Match/Compare 2 Trigger
0x11
TCC0 MC3
TCC0 Match/Compare 3 Trigger
0x12
TCC1 OVF
TCC1 Overflow Trigger
Only software/event triggers
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Table 18-8. Peripheral Trigger Source (Continued)
Value
Name
Description
0x13
TCC1 MC0
TCC1 Match/Compare 0 Trigger
0x14
TCC1 MC1
TCC1 Match/Compare 1 Trigger
0x15
TCC2 OVF
TCC2 Overflow Trigger
0x16
TCC2 MC0
TCC2 Match/Compare 0 Trigger
0x17
TCC2 MC1
TCC2 Match/Compare 1 Trigger
0x18
TC3 OVF
TC3 Overflow Trigger
0x19
TC3 MC0
TC3 Match/Compare 0 Trigger
0x1A
TC3 MC1
TC3 Match/Compare 1 Trigger
0x1B
TC4 OVF
TC4 Overflow Trigger
0x1C
TC4 MC0
TC4 Match/Compare 0 Trigger
0x1D
TC4 MC1
TC4 Match/Compare 1 Trigger
0x1E
TC5 OVF
TC5 Overflow Trigger
0x1F
TC5 MC0
TC5 Match/Compare 0 Trigger
0x20
TC5 MC1
TC5 Match/Compare 1 Trigger
0x21
Reserved
0x22
Reserved
0x23
Reserved
0x24
Reserved
0x25
Reserved
0x26
Reserved
0x27
0x28 - 0x2C
ADC RESRDY
ADC Result Ready Trigger
Reserved
z
Bit 7 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write this bit to zero
when this register is written. This bit will always return zero when read.
z
Bits 6:5 – LVL[1:0]: Channel Arbitration Level
These bits define the arbitration level used for the DMA channel. The available levels are shown in Table 18-9,
where a high level has priority over a low level. For further details on arbitration schemes, refer to “Arbitration” on
page 274.
These bits are not enable-protected.
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Table 18-9. Channel Arbitration Level
LVL[1:0]
Name
0x0
LVL0
Channel Priority Level 0
0x1
LVL1
Channel Priority Level 1
0x2
LVL2
Channel Priority Level 2
0x3
LVL3
Channel Priority Level 3
0x4-0x7
z
Description
Reserved
Bit 4 – EVOE: Channel Event Output Enable
This bit indicates if the Channel event generation is enabled. The event will be generated for every condition
defined in the descriptor Event Output Selection (BTCTRL.EVOSEL).
0: Channel event generation is disabled.
1: Channel event generation is enabled.
This bit is available only on channels with event output support. Refer to Table 22-6 and Table 22-4 for details.
z
Bit 3 – EVIE: Channel Event Input Enable
0: Channel event action will not be executed on any incoming event.
1: Channel event action will be executed on any incoming event.
This bit is available only on channels with event input support. Refer to Table 22-6 and Table 22-4 for details.
z
Bits 2:0 – EVACT[2:0]: Event Input Action
These bits define the event input action, as shown in Table 18-10. The action is executed only if the corresponding
EVIE bit in CHCTRLB register of the channel is set. For details on event actions, refer to “Event Input Actions” on
page 281.
These bits are available only for channels with event input support. Refer to Table 22-6 and Table 22-4 for details.
Table 18-10. Event Input Action
EVACT[2:0]
Name
0x0
NOACT
0x1
TRIG
0x2
CTRIG
Conditional transfer trigger
0x3
CBLOCK
Conditional block transfer
0x4
SUSPEND
Channel suspend operation
0x5
RESUME
Channel resume operation
0x6
SSKIP
0x7
Description
No action
Transfer and periodic transfer trigger
Skip next block suspend action
Reserved
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18.8.1.20 Channel Interrupt Enable Clear
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Channel Interrupt Enable Set (CHINTENSET) register.
Name:
CHINTENCLR
Offset:
0x4C
Reset:
0x00
Property:
Write-Protected
Bit
7
6
5
4
3
2
1
0
SUSP
TCMPL
TERR
Access
R
R
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
z
Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 2 – SUSP: Channel Suspend Interrupt Enable
0: The Channel Suspend interrupt is disabled.
1: The Channel Suspend interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Channel Suspend Interrupt Enable bit, which disables the Channel Suspend
interrupt.
z
Bit 1 – TCMPL: Transfer Complete Interrupt Enable
0: The Channel Transfer Complete interrupt is disabled. When block action is set to none, the TCMPL flag will not
be set when a block transfer is completed.
1: The Channel Transfer Complete interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Channel Transfer Complete Interrupt Enable bit, which disables the Channel
Transfer Complete interrupt.
z
Bit 0 – TERR: Transfer Error Interrupt Enable
0: The Channel Transfer Error interrupt is disabled.
1: The Channel Transfer Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Channel Transfer Error Interrupt Enable bit, which disables the Channel
Transfer Error interrupt.
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18.8.1.21 Channel Interrupt Enable Set
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register
will also be reflected in the Channel Interrupt Enable Clear (CHINTENCLR) register.
Name:
CHINTENSET
Offset:
0x4D
Reset:
0x00
Property:
Write-Protected
Bit
7
6
5
4
3
2
1
0
SUSP
TCMPL
TERR
Access
R
R
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
z
Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 2 – SUSP: Channel Suspend Interrupt Enable
0: The Channel Suspend interrupt is disabled.
1: The Channel Suspend interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Channel Suspend Interrupt Enable bit, which enables the Channel Suspend
interrupt.
z
Bit 1 – TCMPL: Transfer Complete Interrupt Enable
0: The Channel Transfer Complete interrupt is disabled.
1: The Channel Transfer Complete interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Channel Transfer Complete Interrupt Enable bit, which enables the Channel
Transfer Complete interrupt.
z
Bit 0 – TERR: Transfer Error Interrupt Enable
0: The Channel Transfer Error interrupt is disabled.
1: The Channel Transfer Error interrupt is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Channel Transfer Error Interrupt Enable bit, which enables the Channel Transfer Error interrupt.
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18.8.1.22 Channel Interrupt Flag Status and Clear
Name:
CHINTFLAG
Offset:
0x4E
Reset:
0x00
Property:
-
Bit
7
6
5
4
3
2
1
0
SUSP
TCMPL
TERR
Access
R
R
R
R
R
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
z
Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 2 – SUSP: Channel Suspend
This flag is cleared by writing a one to it.
This bit is set when a block transfer with suspend block action is completed, when a software suspend command is
executed, when a suspend event is received or when an invalid descriptor is fetched by the DMA.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Channel Suspend interrupt flag for the corresponding channel.
For details on available software commands, refer to Table 18-6.
For details on available event input actions, refer to Table 18-10.
For details on available block actions, refer to Table 18-14.
z
Bit 1 – TCMPL: Transfer Complete
This flag is cleared by writing a one to it.
This flag is set when a block transfer is completed and the corresponding interrupt block action is enabled.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Complete interrupt flag for the corresponding channel.
z
Bit 0 – TERR: Transfer Error
This flag is cleared by writing a one to it.
This flag is set when a bus error is detected during a beat transfer or when the DMAC fetches an invalid descriptor.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Error interrupt flag for the corresponding channel.
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18.8.1.23 Channel Status
Name:
CHSTATUS
Offset:
0x4F
Reset:
0x00
Property:
-
Bit
7
6
5
4
3
2
1
0
FERR
BUSY
PEND
Access
R
R
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
z
Bits 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 2 – FERR: Fetch Error
This bit is cleared when the software resume command is executed.
This bit is set when an invalid descriptor is fetched.
z
Bit 1 – BUSY: Channel Busy
This bit is cleared when the channel trigger action is complete, when a bus error is detected or when the channel is
disabled.
This bit is set when the DMA channel starts a DMA transfer.
z
Bit 0 – PEND: Channel Pending
This bit is cleared when trigger execution defined by channel trigger action settings is started, when a bus error is
detected or when the channel is disabled. For details on trigger action settings, refer to Table 18-7.
This bit is set when a transfer is pending on the DMA channel.
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18.8.2 DMAC SRAM Registers
18.8.2.1 Block Transfer Control
The BTCTRL register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
Name:
BTCTRL
Offset:
0x00
Bit
15
14
13
STEPSIZE[2:0]
Bit
7
6
12
11
10
STEPSEL
DSTINC
SRCINC
4
3
2
5
BLOCKACT[1:0]
z
9
8
BEATSIZE[1:0]
1
EVOSEL[1:0]
0
VALID
Bits 15:13 – STEPSIZE[2:0]: Address Increment Step Size
These bits select the address increment step size, as shown in Table 18-11. The setting apply to source or destination address, depending on STEPSEL setting.
Table 18-11. Address Increment Step Size
z
STEPSIZE[2:0]
Name
Description
0x0
X1
Next ADDR 3V.
3 - TCC0/WO[6] on PA16 and TCC0/WO[7] on PA17 are not available. Errata
reference: 11622
Fix/Workaround:
None
4 - On pin PA24 and PA25 the pull-up and pull-down configuration is not
disabled automatically when alternative pin function is enabled. Errata
reference: 12368
Fix/Workaround:
For pin PA24 and PA25, the GPIO pull-up and pull-down must be disabled before
enabling alternative functions on them.
5 - If APB clock is stopped and GCLK clock is running, APB read access to
read-synchronized registers will freeze the system. The CPU and the DAP
AHB-AP are stalled, as a consequence debug operation is impossible.
Errata reference: 10416
Fix/Workaround:
Do not make read access to read-synchronized registers when APB clock is
stopped and GCLK is running. To recover from this situation, power cycle the
device or reset the device using the RESETN pin.
6 - In I2C Slave mode, writing the CTRLB register when in the AMATCH or
DRDY interrupt service routines can cause the state machine to reset. Errata
reference: 13574
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
1131
Fix/Workaround:
Write CTRLB.ACKACT to 0 using the following sequence:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = 0;
// Re-enable interrupts if applicable.
Write CTRLB.ACKACT to 1 using the following sequence:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
// Re-enable interrupts if applicable.
Otherwise, only write to CTRLB in the AMATCH or DRDY interrupts if it is to close
out a transaction.
When not closing a transaction, clear the AMATCH interrupt by writing a 1 to its bit
position instead of using CTRLB.CMD. The DRDY interrupt is automatically
cleared by reading/writing to the DATA register in smart mode. If not in smart
mode, DRDY should be cleared by writing a 1 to its bit position.
Code replacements examples:
Current:
SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
Change to:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
// Re-enable interrupts if applicable.
Current:
SERCOM - CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
Change to:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = 0;
// Re-enable interrupts if applicable.
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
1132
Current:
/* ACK or NACK address */
SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
Change to:
// CMD=0x3 clears all interrupts, so to keep the result similar,
// PREC is cleared if it was set.
if (SERCOM - INTFLAG.bit.PREC) SERCOM - INTFLAG.reg =
SERCOM_I2CS_INTFLAG_PREC;
SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
7 - PA24 and PA25 cannot be used as input when configured as GPIO with
continuous sampling (cannot be read by PORT). Errata reference: 12005
Fix/Workaround:
- Use PA24 and PA25 for peripherals or only as output pins.
- Or configure PA31 to PA24 for on-demand sampling (CTRL[31:24] all zeroes)
and access the IN register through the APB (not the IOBUS), to allow waiting for
on-demand sampling.
8 - The SYSTICK calibration value is incorrect. Errata reference: 14154
Fix/Workaround:
The correct SYSTICK calibration value is 0x40000000. This value should not be
used to initialize the Systick RELOAD value register, which should be initialized
instead with a value depending on the main clock frequency and on the tick period
required by the application. For a detailed description of the SYSTICK module,
refer to the official ARM Cortex-M0+ documentation.
9 - In Standby, Idle1 and Idle2 sleep modes the device might not wake up
from sleep. An External Reset, Power on Reset or Watch Dog Reset will start
the device again. Errata reference: 13140
Fix/Workaround:
the SLEEPPRM bits in the NVMCTRL.CTRLB register must be written to 3
(NVMCTRL - CTRLB.bit.SLEEPPRM = 3) to ensure correct operation of the
device. The average power consumption of the device will increase with 20uA
compared to numbers in the electrical characteristics chapter.
10 - While the internal startup is not completed, PA07 pin is driven low by
the chip. Then as all the other pins it is configured as an High Impedance
pin. Errata reference: 12118
Fix/Workaround:
None
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
1133
11 - Digital pin outputs from Timer/Counters, AC (Analog Comparator),
GCLK (Generic Clock Controller), and SERCOM (I2C and SPI) do not change
value during standby sleep mode. Errata reference: 12537
Fix/Workaround:
Set the voltage regulator in Normal mode before entering STANDBY sleep mode
in order to keep digital pin output enabled. This is done by setting the RUNSTDBY
bit in the VREG register.
12 - The voltage regulator in low power mode is not functional at
temperatures above 85C. Errata reference: 12291
Fix/Workaround:
Enable normal mode on the voltage regulator in standby sleep mode.
Example code:
// Set the voltage regulator in normal mode configuration in standby sleep mode
SYSCTRL->VREG.bit.RUNSTDBY = 1;
13 - If the external XOSC32K is broken, neither the external pin RST nor the
GCLK software reset can reset the GCLK generators using XOSC32K as
source clock. Errata reference: 12164
Fix/Workaround:
Do a power cycle to reset the GCLK generators after an external XOSC32K
failure.
47.1.2 DSU
1 - If a debugger has issued a DSU Cold-Plugging procedure and then
released the CPU from the resulting ""CPU Reset Extension"", the CPU will
be held in ""CPU Reset Extension"" after any upcoming reset event. Errata
reference: 12015
Fix/workaround:
The CPU must be released from the ""CPU Reset Extension"" either by writing a
one in the DSU STATUSA.CRSTEXT register or by applying an external reset
with SWCLK high or by power cycling the device.
2 - The MBIST ""Pause-on-Error"" feature is not functional on this device.
Errata reference: 14324
Fix/Workaround: Do not use the ""Pause-on-Error"" feature.
47.1.3 PM
1 - In debug mode, if a watchdog reset occurs, the debug session is lost.
Errata reference: 12196
Fix/Workaround:
A new debug session must be restart after a watchdog reset.
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
1134
47.1.4 XOSC32K
1 - The automatic amplitude control of the XOSC32K does not work. Errata
reference: 10933
Fix/Workaround:
Use the XOSC32K with Automatic Amplitude control disabled
(XOSC32K.AAMPEN = 0)
47.1.5 DFLL48M
1 - The DFLL clock must be requested before being configured otherwise a
write access to a DFLL register can freeze the device. Errata reference: 9905
Fix/Workaround:
Write a zero to the DFLL ONDEMAND bit in the DFLLCTRL register before
configuring the DFLL module.
2 - If the DFLL48M reaches the maximum or minimum COARSE or FINE
calibration values during the locking sequence, an out of bounds interrupt
will be generated. These interrupts will be generated even if the final
calibration values at DFLL48M lock are not at maximum or minimum, and
might therefore be false out of bounds interrupts. Errata reference: 10669
Fix/Workaround:
Check that the lockbits: DFLLLCKC and DFLLLCKF in the SYSCTRL Interrupt
Flag Status and Clear register (INTFLAG) are both set before enabling the
DFLLOOB interrupt.
3 - The DFLL status bits in the PCLKSR register during the USB clock
recovery mode can be wrong after a USB suspend state. Errata reference:
11938
Fix/Workaround:
Do not monitor the DFLL status bits in the PCLKSR register during the USB clock
recovery mode.
47.1.6 FDPLL
1 - The lock flag (DPLLSTATUS.LOCK) may clear randomly. When the lock
flag randomly clears, DPLLLCKR and DPLLLCKF interrupts will also trigger,
and the DPLL output is masked. Errata reference: 11791
Fix/Workaround:
Set DPLLCTRLB.LBYPASS to 1 to disable masking of the DPLL output by the
lock status.
2 - FDPLL lock time-out values are different from the parameters in the
datasheet. Errata reference: 12145
Atmel | SMART SAM R21 [DATASHEET]
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1135
Fix/Workaround:
The time-out values are:
- DPLLCTRLB.LTIME[2:0] = 4 : 10ms
- DPLLCTRLB.LTIME[2:0] = 5 : 10ms
- DPLLCTRLB.LTIME[2:0] = 6 : 11ms
- DPLLCTRLB.LTIME[2:0] = 7 : 11ms
47.1.7 DMAC
1 - If data is written to CRCDATAIN in two consecutive instructions, the CRC
computation may be incorrect. Errata reference: 13507
Fix/Workaround:
Add a NOP instruction between each write to CRCDATAIN register.
47.1.8 NVMCTRL
1 - Default value of MANW in NVM.CTRLB is 0. Errata reference: 13134
This can lead to spurious writes to the NVM if a data write is done through a
pointer with a wrong address corresponding to NVM area.
Fix/Workaround:
Set MANW in the NVM.CTRLB to 1 at startup
2 - When the part is secured and EEPROM emulation area configured to
none, the CRC32 is not executed on the entire flash area but up to the onchip flash size minus half a row. Errata reference: 11988
Fix/Workaround:
When using CRC32 on a protected device with EEPROM emulation area
configured to none, compute the reference CRC32 value to the full chip flash size
minus half row.
3 - When external reset is active it causes a high leakage current on VDDIO.
Errata reference: 13446
Fix/Workaround:
Minimize the time external reset is active.
47.1.9 SERCOM
1 - The I2C Slave SCL Low Extend Time-out (CTRLA.SEXTTOEN) and Master
SCL Low Extend Time-out (CTRLA.MEXTTOEN) cannot be used if SCL Low
Time-out (CTRLA.LOWTOUT) is disabled. When SCTRLA.LOWTOUT=0, the
GCLK_SERCOM_SLOW is not requested. Errata reference: 12003
Fix/Workaround:
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
1136
To use the Master or Slave SCL low extend time-outs, enable the SCL Low Timeout (CTRLA.LOWTOUT=1).
2 - In USART autobaud mode, missing stop bits are not recognized as
inconsistent sync (ISF) or framing (FERR) errors. Errata reference: 13852
Fix/Workaround:
None
3 - If the SERCOM is enabled in SPI mode with SSL detection enabled
(CTRLB.SSDE) and CTRLB.RXEN=1, an erroneous slave select low interrupt
(INTFLAG.SSL) can be generated. Errata reference: 13369
Fix/Workaround:
Enable the SERCOM first with CTRLB.RXEN=0. In a subsequent write, set
CTRLB.RXEN=1.
4 - In TWI master mode, an ongoing transaction should be stalled
immediately when DBGCTRL.DBGSTOP is set and the CPU enters debug
mode. Instead, it is stopped when the current byte transaction is completed
and the corresponding interrupt is triggered if enabled. Errata reference:
12499
Fix/Workaround:
In TWI master mode, keep DBGCTRL.DBGSTOP=0 when in debug mode.
47.1.10 USB
1 - The FLENC register negative sign management is not correct. Errata
reference: 11472
Fix/Workaround:
The following rule must be used for negative values:
- FLENC 8h is equal to 0 decimal.
- FLENC 9h to Fh are equal to -1 to -7 decimal instead of -7 to -1.
47.1.11 TC
1 - Spurious TC overflow and Match/Capture events may occur. Errata
reference: 13268
Fix/Workaround:
Do not use the TC overflow and Match/Capture events. Use the corresponding
Interrupts instead.
47.1.12 TCC
1 - The TCC interrupts FAULT1, FAULT0, FAULTB, FAULTA, DFS, ERR,and
CNT cannot wake up the chip from standby mode. Errata reference: 11951
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
1137
Fix/Workaround:
Do not use the TCC interrupts FAULT1, FAULT0, FAULTB, FAULTA, DFS, ERR,
or CNT to wake up the chip from standby mode.
2 - If the OVF flag in the INTFLAG register is already set when enabling the
DMA, this will trigger an immediate DMA transfer and overwrite the current
buffered value in the TCC register. Errata reference: 12127
Fix/Workaround:
None
3 - In RAMP 2 mode with Fault keep, qualified and restart: Errata reference:
13262
If a fault occurred at the end of the period during the qualified state, the switch to
the next ramp can have two restarts.
Fix/Workaround:
Avoid faults few cycles before the end or the beginning of a ramp.
4 - With blanking enabled, a recoverable fault that occurs during the first
increment of a rising TCC is not blanked. Errata reference: 12519
Fix/Workaround:
None
5 - In Dual slope mode a Retrigger Event does not clear the TCC counter.
Errata reference: 12354
Fix/Workaround:
None
6 - In two ramp mode, two events will be generated per cycle, one on each
ramp’s end. EVCTRL.CNTSEL.END cannot be used to identify the end of a
double ramp cycle. Errata reference: 12224
Fix/Workaround:
None
7 - If an input event triggered STOP action is performed at the same time as
the counter overflows, the first pulse width of the subsequent counter start
can be altered with one prescaled clock cycle. Errata reference: 12107
Fix/Workaround:
None
8 - When the RUNSTDBY bit is written after the TCC is enabled, the
respective TCC APB bus is stalled and the RUNDSTBY bit in the TCC CTRLA
register is not enabled-protected. Errata reference: 12477
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
1138
Fix/Workaround:
None.
9 - TCC fault filtering on inverted fault is not working. Errata reference:
12512
Fix/Workaround:
Use only non-inverted faults.
10 - When waking up from the STANDBY power save mode, the
SYNCBUSY.CTRLB and SYNCBUSY.STATUS bits may be locked to 1. Errata
reference: 12227
Fix/Workaround:
After waking up from STANDBY power save mode, perform a software reset of
the TCC if you are using the SYNCBUSY.CTRLB and SYNCBUSY.STATUS bits
11 - When the Peripheral Access Controller (PAC) protection is enabled,
writing to WAVE or WAVEB registers will not cause a hardware exception.
Errata reference: 11468
Fix/Workaround:
None
12 - If the MCx flag in the INTFLAG register is set when enabling the DMA,
this will trigger an immediate DMA transfer and overwrite the current
buffered value in the TCC register. Errata reference: 12155
Fix/Workaround:
None
47.1.13 PTC
1 - WCOMP interrupt flag is not stable. The WCOMP interrupt flag will not
always be set as described in the datasheet. Errata reference: 12860
Fix/Workaround:
Do not use the WCOMP interrupt. Use the WCOMP event.
47.2
Revision B
47.2.1 Device
1 - In single shot mode and at 125°C, the ADC conversions have linearity
errors. Errata reference: 13277
Fix/Workaround:
- Workaround 1: At 125°C, do not use the ADC in single shot mode; use the
ADC in free running mode only.
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
1139
- Workaround 2: At 125°C, use the ADC in single shot mode only with
VDDANA > 3V.
2 - On pin PA24 and PA25 the pull-up and pull-down configuration is not
disabled automatically when alternative pin function is enabled. Errata
reference: 12368
Fix/Workaround:
For pin PA24 and PA25, the GPIO pull-up and pull-down must be disabled before
enabling alternative functions on them.
3 - The PDM2 mode (i.e. when using two PDM microphones) does not work.
Errata reference: 13410
Fix/Workaround:
None. Only one PDM microphone can be connected. Thus, the I2S controller
should be configured in normal Receive mode with one slot.
4 - The I2S is non-functional in the slave mode (i.e. when (FSSEL=1,
SCKSEL=1). Errata reference: 13407
Fix/Workaround:
None. FSSEL and SCKSEL must be 0.
5 - If APB clock is stopped and GCLK clock is running, APB read access to
read-synchronized registers will freeze the system. The CPU and the DAP
AHB-AP are stalled, as a consequence debug operation is impossible.
Errata reference: 10416
Fix/Workaround:
Do not make read access to read-synchronized registers when APB clock is
stopped and GCLK is running. To recover from this situation, power cycle the
device or reset the device using the RESETN pin.
6 - In I2C Slave mode, writing the CTRLB register when in the AMATCH or
DRDY interrupt service routines can cause the state machine to reset. Errata
reference: 13574
Fix/Workaround:
Write CTRLB.ACKACT to 0 using the following sequence:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = 0;
// Re-enable interrupts if applicable.
Write CTRLB.ACKACT to 1 using the following sequence:
// If higher priority interrupts exist, then disable so that the
Atmel | SMART SAM R21 [DATASHEET]
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1140
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
// Re-enable interrupts if applicable.
Otherwise, only write to CTRLB in the AMATCH or DRDY interrupts if it is to close
out a transaction.
When not closing a transaction, clear the AMATCH interrupt by writing a 1 to its bit
position instead of using CTRLB.CMD. The DRDY interrupt is automatically
cleared by reading/writing to the DATA register in smart mode. If not in smart
mode, DRDY should be cleared by writing a 1 to its bit position.
Code replacements examples:
Current:
SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
Change to:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
// Re-enable interrupts if applicable.
Current:
SERCOM - CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
Change to:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = 0;
// Re-enable interrupts if applicable.
Current:
/* ACK or NACK address */
SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
Change to:
// CMD=0x3 clears all interrupts, so to keep the result similar,
// PREC is cleared if it was set.
if (SERCOM - INTFLAG.bit.PREC) SERCOM - INTFLAG.reg =
SERCOM_I2CS_INTFLAG_PREC;
SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
1141
7 - PA24 and PA25 cannot be used as input when configured as GPIO with
continuous sampling (cannot be read by PORT). Errata reference: 12005
Fix/Workaround:
- Use PA24 and PA25 for peripherals or only as output pins.
- Or configure PA31 to PA24 for on-demand sampling (CTRL[31:24] all zeroes)
and access the IN register through the APB (not the IOBUS), to allow waiting for
on-demand sampling.
8 - Rx serializer in the RIGHT Data Slot Formatting Adjust mode
(SERCTRL.SLOTADJ clear) does not work when the slot size is not 32 bits.
Errata reference: 13411
Fix/Workaround:
In SERCTRL.SERMODE RX, SERCTRL.SLOTADJ RIGHT must be used with
CLKCTRL.SLOTSIZE 32.
9 - The SYSTICK calibration value is incorrect. Errata reference: 14154
Fix/Workaround:
The correct SYSTICK calibration value is 0x40000000. This value should not be
used to initialize the Systick RELOAD value register, which should be initialized
instead with a value depending on the main clock frequency and on the tick period
required by the application. For a detailed description of the SYSTICK module,
refer to the official ARM Cortex-M0+ documentation.
10 - Depending CPU clock/ I2S clock ratio, the SYNCBUSY.CKEN0 flag
occasionally stuck at 1 when starting a new audio stream with
CTRLA.SWRST=1, then CTRLA.ENABLE=1, then CTRLA.CKEN0=1 Errata
reference: 13408
Fix/Workaround:
Disable the IP by writing 0 to CTRLA.ENABLE before resetting it
(CTRLA.SWRST=1).
11 - In Standby, Idle1 and Idle2 sleep modes the device might not wake up
from sleep. An External Reset, Power on Reset or Watch Dog Reset will start
the device again. Errata reference: 13140
Fix/Workaround:
the SLEEPPRM bits in the NVMCTRL.CTRLB register must be written to 3
(NVMCTRL - CTRLB.bit.SLEEPPRM = 3) to ensure correct operation of the
device. The average power consumption of the device will increase with 20uA
compared to numbers in the electrical characteristics chapter.
12 - While the internal startup is not completed, PA07 pin is driven low by
the chip. Then as all the other pins it is configured as an High Impedance
pin. Errata reference: 12118
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
1142
Fix/Workaround:
None
13 - Digital pin outputs from Timer/Counters, AC (Analog Comparator),
GCLK (Generic Clock Controller), and SERCOM (I2C and SPI) do not change
value during standby sleep mode. Errata reference: 12537
Fix/Workaround:
Set the voltage regulator in Normal mode before entering STANDBY sleep mode
in order to keep digital pin output enabled. This is done by setting the RUNSTDBY
bit in the VREG register.
14 - The voltage regulator in low power mode is not functional at
temperatures above 85C. Errata reference: 12291
Fix/Workaround:
Enable normal mode on the voltage regulator in standby sleep mode.
Example code:
// Set the voltage regulator in normal mode configuration in standby sleep mode
SYSCTRL->VREG.bit.RUNSTDBY = 1;
15 - If the external XOSC32K is broken, neither the external pin RST nor the
GCLK software reset can reset the GCLK generators using XOSC32K as
source clock. Errata reference: 12164
Fix/Workaround:
Do a power cycle to reset the GCLK generators after an external XOSC32K
failure.
47.2.2 DSU
1 - If a debugger has issued a DSU Cold-Plugging procedure and then
released the CPU from the resulting ""CPU Reset Extension"", the CPU will
be held in ""CPU Reset Extension"" after any upcoming reset event. Errata
reference: 12015
Fix/workaround:
The CPU must be released from the ""CPU Reset Extension"" either by writing a
one in the DSU STATUSA.CRSTEXT register or by applying an external reset
with SWCLK high or by power cycling the device.
2 - The MBIST ""Pause-on-Error"" feature is not functional on this device.
Errata reference: 14324
Fix/Workaround: Do not use the ""Pause-on-Error"" feature.
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
1143
47.2.3 PM
1 - In debug mode, if a watchdog reset occurs, the debug session is lost.
Errata reference: 12196
Fix/Workaround:
A new debug session must be restart after a watchdog reset.
47.2.4 XOSC32K
1 - The automatic amplitude control of the XOSC32K does not work. Errata
reference: 10933
Fix/Workaround:
Use the XOSC32K with Automatic Amplitude control disabled
(XOSC32K.AAMPEN = 0)
47.2.5 DFLL48M
1 - The DFLL clock must be requested before being configured otherwise a
write access to a DFLL register can freeze the device. Errata reference: 9905
Fix/Workaround:
Write a zero to the DFLL ONDEMAND bit in the DFLLCTRL register before
configuring the DFLL module.
2 - If the DFLL48M reaches the maximum or minimum COARSE or FINE
calibration values during the locking sequence, an out of bounds interrupt
will be generated. These interrupts will be generated even if the final
calibration values at DFLL48M lock are not at maximum or minimum, and
might therefore be false out of bounds interrupts. Errata reference: 10669
Fix/Workaround:
Check that the lockbits: DFLLLCKC and DFLLLCKF in the SYSCTRL Interrupt
Flag Status and Clear register (INTFLAG) are both set before enabling the
DFLLOOB interrupt.
3 - The DFLL status bits in the PCLKSR register during the USB clock
recovery mode can be wrong after a USB suspend state. Errata reference:
11938
Fix/Workaround:
Do not monitor the DFLL status bits in the PCLKSR register during the USB clock
recovery mode.
47.2.6 DMAC
1 - If data is written to CRCDATAIN in two consecutive instructions, the CRC
computation may be incorrect. Errata reference: 13507
Fix/Workaround:
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
1144
Add a NOP instruction between each write to CRCDATAIN register.
47.2.7 NVMCTRL
1 - Default value of MANW in NVM.CTRLB is 0. Errata reference: 13134
This can lead to spurious writes to the NVM if a data write is done through a
pointer with a wrong address corresponding to NVM area.
Fix/Workaround:
Set MANW in the NVM.CTRLB to 1 at startup
2 - When the part is secured and EEPROM emulation area configured to
none, the CRC32 is not executed on the entire flash area but up to the onchip flash size minus half a row. Errata reference: 11988
Fix/Workaround:
When using CRC32 on a protected device with EEPROM emulation area
configured to none, compute the reference CRC32 value to the full chip flash size
minus half row.
3 - When external reset is active it causes a high leakage current on VDDIO.
Errata reference: 13446
Fix/Workaround:
Minimize the time external reset is active.
47.2.8 SERCOM
1 - The I2C Slave SCL Low Extend Time-out (CTRLA.SEXTTOEN) and Master
SCL Low Extend Time-out (CTRLA.MEXTTOEN) cannot be used if SCL Low
Time-out (CTRLA.LOWTOUT) is disabled. When SCTRLA.LOWTOUT=0, the
GCLK_SERCOM_SLOW is not requested. Errata reference: 12003
Fix/Workaround:
To use the Master or Slave SCL low extend time-outs, enable the SCL Low Timeout (CTRLA.LOWTOUT=1).
2 - In USART autobaud mode, missing stop bits are not recognized as
inconsistent sync (ISF) or framing (FERR) errors. Errata reference: 13852
Fix/Workaround:
None
3 - If the SERCOM is enabled in SPI mode with SSL detection enabled
(CTRLB.SSDE) and CTRLB.RXEN=1, an erroneous slave select low interrupt
(INTFLAG.SSL) can be generated. Errata reference: 13369
Fix/Workaround:
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
1145
Enable the SERCOM first with CTRLB.RXEN=0. In a subsequent write, set
CTRLB.RXEN=1.
4 - In TWI master mode, an ongoing transaction should be stalled
immediately when DBGCTRL.DBGSTOP is set and the CPU enters debug
mode. Instead, it is stopped when the current byte transaction is completed
and the corresponding interrupt is triggered if enabled. Errata reference:
12499
Fix/Workaround:
In TWI master mode, keep DBGCTRL.DBGSTOP=0 when in debug mode.
47.2.9 TC
1 - Spurious TC overflow and Match/Capture events may occur. Errata
reference: 13268
Fix/Workaround:
Do not use the TC overflow and Match/Capture events. Use the corresponding
Interrupts instead.
47.2.10 TCC
1 - In RAMP 2 mode with Fault keep, qualified and restart: Errata reference:
13262
If a fault occurred at the end of the period during the qualified state, the switch to
the next ramp can have two restarts.
Fix/Workaround:
Avoid faults few cycles before the end or the beginning of a ramp.
2 - With blanking enabled, a recoverable fault that occurs during the first
increment of a rising TCC is not blanked. Errata reference: 12519
Fix/Workaround:
None
3 - In Dual slope mode a Retrigger Event does not clear the TCC counter.
Errata reference: 12354
Fix/Workaround:
None
4 - In two ramp mode, two events will be generated per cycle, one on each
ramp’s end. EVCTRL.CNTSEL.END cannot be used to identify the end of a
double ramp cycle. Errata reference: 12224
Fix/Workaround:
None
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
1146
5 - If an input event triggered STOP action is performed at the same time as
the counter overflows, the first pulse width of the subsequent counter start
can be altered with one prescaled clock cycle. Errata reference: 12107
Fix/Workaround:
None
6 - When the RUNSTDBY bit is written after the TCC is enabled, the
respective TCC APB bus is stalled and the RUNDSTBY bit in the TCC CTRLA
register is not enabled-protected. Errata reference: 12477
Fix/Workaround:
None.
7 - TCC fault filtering on inverted fault is not working. Errata reference:
12512
Fix/Workaround:
Use only non-inverted faults.
8 - When waking up from the STANDBY power save mode, the
SYNCBUSY.CTRLB and SYNCBUSY.STATUS bits may be locked to 1. Errata
reference: 12227
Fix/Workaround:
After waking up from STANDBY power save mode, perform a software reset of
the TCC if you are using the SYNCBUSY.CTRLB and SYNCBUSY.STATUS bits
9 - When the Peripheral Access Controller (PAC) protection is enabled,
writing to WAVE or WAVEB registers will not cause a hardware exception.
Errata reference: 11468
Fix/Workaround:
None
10 - If the MCx flag in the INTFLAG register is set when enabling the DMA,
this will trigger an immediate DMA transfer and overwrite the current
buffered value in the TCC register. Errata reference: 12155
Fix/Workaround:
None
47.2.11 PTC
1 - WCOMP interrupt flag is not stable. The WCOMP interrupt flag will not
always be set as described in the datasheet. Errata reference: 12860
Fix/Workaround:
Do not use the WCOMP interrupt. Use the WCOMP event.
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
1147
47.3
Revision C
47.3.1 Device
1 - In single shot mode and at 125°C, the ADC conversions have linearity
errors. Errata reference: 13277
Fix/Workaround:
- Workaround 1: At 125°C, do not use the ADC in single shot mode; use the
ADC in free running mode only.
- Workaround 2: At 125°C, use the ADC in single shot mode only with
VDDANA > 3V.
2 - In the table ""NVM User Row Mapping"", the WDT Window bitfield default
value on silicon is not as specified in the datasheet. The datasheet defines
the default value as 0x5, while it is 0xB on silicon. Errata reference: 13951
Fix/Workaround:
None.
3 - On pin PA24 and PA25 the pull-up and pull-down configuration is not
disabled automatically when alternative pin function is enabled. Errata
reference: 12368
Fix/Workaround:
For pin PA24 and PA25, the GPIO pull-up and pull-down must be disabled before
enabling alternative functions on them.
4 - If APB clock is stopped and GCLK clock is running, APB read access to
read-synchronized registers will freeze the system. The CPU and the DAP
AHB-AP are stalled, as a consequence debug operation is impossible.
Errata reference: 10416
Fix/Workaround:
Do not make read access to read-synchronized registers when APB clock is
stopped and GCLK is running. To recover from this situation, power cycle the
device or reset the device using the RESETN pin.
5 - In I2C Slave mode, writing the CTRLB register when in the AMATCH or
DRDY interrupt service routines can cause the state machine to reset. Errata
reference: 13574
Fix/Workaround:
Write CTRLB.ACKACT to 0 using the following sequence:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = 0;
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
1148
// Re-enable interrupts if applicable.
Write CTRLB.ACKACT to 1 using the following sequence:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
// Re-enable interrupts if applicable.
Otherwise, only write to CTRLB in the AMATCH or DRDY interrupts if it is to close
out a transaction.
When not closing a transaction, clear the AMATCH interrupt by writing a 1 to its bit
position instead of using CTRLB.CMD. The DRDY interrupt is automatically
cleared by reading/writing to the DATA register in smart mode. If not in smart
mode, DRDY should be cleared by writing a 1 to its bit position.
Code replacements examples:
Current:
SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
Change to:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
// Re-enable interrupts if applicable.
Current:
SERCOM - CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
Change to:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = 0;
// Re-enable interrupts if applicable.
Current:
/* ACK or NACK address */
SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
Change to:
// CMD=0x3 clears all interrupts, so to keep the result similar,
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
1149
// PREC is cleared if it was set.
if (SERCOM - INTFLAG.bit.PREC) SERCOM - INTFLAG.reg =
SERCOM_I2CS_INTFLAG_PREC;
SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
6 - PA24 and PA25 cannot be used as input when configured as GPIO with
continuous sampling (cannot be read by PORT). Errata reference: 12005
Fix/Workaround:
- Use PA24 and PA25 for peripherals or only as output pins.
- Or configure PA31 to PA24 for on-demand sampling (CTRL[31:24] all zeroes)
and access the IN register through the APB (not the IOBUS), to allow waiting for
on-demand sampling.
7 - Rx serializer in the RIGHT Data Slot Formatting Adjust mode
(SERCTRL.SLOTADJ clear) does not work when the slot size is not 32 bits.
Errata reference: 13411
Fix/Workaround:
In SERCTRL.SERMODE RX, SERCTRL.SLOTADJ RIGHT must be used with
CLKCTRL.SLOTSIZE 32.
8 - The SYSTICK calibration value is incorrect. Errata reference: 14154
Fix/Workaround:
The correct SYSTICK calibration value is 0x40000000. This value should not be
used to initialize the Systick RELOAD value register, which should be initialized
instead with a value depending on the main clock frequency and on the tick period
required by the application. For a detailed description of the SYSTICK module,
refer to the official ARM Cortex-M0+ documentation.
9 - In Standby, Idle1 and Idle2 sleep modes the device might not wake up
from sleep. An External Reset, Power on Reset or Watch Dog Reset will start
the device again. Errata reference: 13140
Fix/Workaround:
the SLEEPPRM bits in the NVMCTRL.CTRLB register must be written to 3
(NVMCTRL - CTRLB.bit.SLEEPPRM = 3) to ensure correct operation of the
device. The average power consumption of the device will increase with 20uA
compared to numbers in the electrical characteristics chapter.
10 - While the internal startup is not completed, PA07 pin is driven low by
the chip. Then as all the other pins it is configured as an High Impedance
pin. Errata reference: 12118
Fix/Workaround:
None
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
1150
11 - The voltage regulator in low power mode is not functional at
temperatures above 85C. Errata reference: 12291
Fix/Workaround:
Enable normal mode on the voltage regulator in standby sleep mode.
Example code:
// Set the voltage regulator in normal mode configuration in standby sleep mode
SYSCTRL->VREG.bit.RUNSTDBY = 1;
12 - If the external XOSC32K is broken, neither the external pin RST nor the
GCLK software reset can reset the GCLK generators using XOSC32K as
source clock. Errata reference: 12164
Fix/Workaround:
Do a power cycle to reset the GCLK generators after an external XOSC32K
failure.
47.3.2 DSU
1 - If a debugger has issued a DSU Cold-Plugging procedure and then
released the CPU from the resulting ""CPU Reset Extension"", the CPU will
be held in ""CPU Reset Extension"" after any upcoming reset event. Errata
reference: 12015
Fix/workaround:
The CPU must be released from the ""CPU Reset Extension"" either by writing a
one in the DSU STATUSA.CRSTEXT register or by applying an external reset
with SWCLK high or by power cycling the device.
2 - The MBIST ""Pause-on-Error"" feature is not functional on this device.
Errata reference: 14324
Fix/Workaround: Do not use the ""Pause-on-Error"" feature.
47.3.3 PM
1 - In debug mode, if a watchdog reset occurs, the debug session is lost.
Errata reference: 12196
Fix/Workaround:
A new debug session must be restart after a watchdog reset.
47.3.4 XOSC32K
1 - The automatic amplitude control of the XOSC32K does not work. Errata
reference: 10933
Fix/Workaround:
Use the XOSC32K with Automatic Amplitude control disabled
(XOSC32K.AAMPEN = 0)
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
1151
47.3.5 DFLL48M
1 - The DFLL clock must be requested before being configured otherwise a
write access to a DFLL register can freeze the device. Errata reference: 9905
Fix/Workaround:
Write a zero to the DFLL ONDEMAND bit in the DFLLCTRL register before
configuring the DFLL module.
2 - If the DFLL48M reaches the maximum or minimum COARSE or FINE
calibration values during the locking sequence, an out of bounds interrupt
will be generated. These interrupts will be generated even if the final
calibration values at DFLL48M lock are not at maximum or minimum, and
might therefore be false out of bounds interrupts. Errata reference: 10669
Fix/Workaround:
Check that the lockbits: DFLLLCKC and DFLLLCKF in the SYSCTRL Interrupt
Flag Status and Clear register (INTFLAG) are both set before enabling the
DFLLOOB interrupt.
3 - The DFLL status bits in the PCLKSR register during the USB clock
recovery mode can be wrong after a USB suspend state. Errata reference:
11938
Fix/Workaround:
Do not monitor the DFLL status bits in the PCLKSR register during the USB clock
recovery mode.
47.3.6 DMAC
1 - If data is written to CRCDATAIN in two consecutive instructions, the CRC
computation may be incorrect. Errata reference: 13507
Fix/Workaround:
Add a NOP instruction between each write to CRCDATAIN register.
47.3.7 NVMCTRL
1 - Default value of MANW in NVM.CTRLB is 0. Errata reference: 13134
This can lead to spurious writes to the NVM if a data write is done through a
pointer with a wrong address corresponding to NVM area.
Fix/Workaround:
Set MANW in the NVM.CTRLB to 1 at startup
2 - When the part is secured and EEPROM emulation area configured to
none, the CRC32 is not executed on the entire flash area but up to the onchip flash size minus half a row. Errata reference: 11988
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Fix/Workaround:
When using CRC32 on a protected device with EEPROM emulation area
configured to none, compute the reference CRC32 value to the full chip flash size
minus half row.
3 - When external reset is active it causes a high leakage current on VDDIO.
Errata reference: 13446
Fix/Workaround:
Minimize the time external reset is active.
47.3.8 SERCOM
1 - The I2C Slave SCL Low Extend Time-out (CTRLA.SEXTTOEN) and Master
SCL Low Extend Time-out (CTRLA.MEXTTOEN) cannot be used if SCL Low
Time-out (CTRLA.LOWTOUT) is disabled. When SCTRLA.LOWTOUT=0, the
GCLK_SERCOM_SLOW is not requested. Errata reference: 12003
Fix/Workaround:
To use the Master or Slave SCL low extend time-outs, enable the SCL Low Timeout (CTRLA.LOWTOUT=1).
2 - In USART autobaud mode, missing stop bits are not recognized as
inconsistent sync (ISF) or framing (FERR) errors. Errata reference: 13852
Fix/Workaround:
None
3 - If the SERCOM is enabled in SPI mode with SSL detection enabled
(CTRLB.SSDE) and CTRLB.RXEN=1, an erroneous slave select low interrupt
(INTFLAG.SSL) can be generated. Errata reference: 13369
Fix/Workaround:
Enable the SERCOM first with CTRLB.RXEN=0. In a subsequent write, set
CTRLB.RXEN=1.
4 - In TWI master mode, an ongoing transaction should be stalled
immediately when DBGCTRL.DBGSTOP is set and the CPU enters debug
mode. Instead, it is stopped when the current byte transaction is completed
and the corresponding interrupt is triggered if enabled. Errata reference:
12499
Fix/Workaround:
In TWI master mode, keep DBGCTRL.DBGSTOP=0 when in debug mode.
47.3.9 TC
1 - Spurious TC overflow and Match/Capture events may occur. Errata
reference: 13268
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Fix/Workaround:
Do not use the TC overflow and Match/Capture events. Use the corresponding
Interrupts instead.
47.3.10 TCC
1 - In RAMP 2 mode with Fault keep, qualified and restart: Errata reference:
13262
If a fault occurred at the end of the period during the qualified state, the switch to
the next ramp can have two restarts.
Fix/Workaround:
Avoid faults few cycles before the end or the beginning of a ramp.
2 - With blanking enabled, a recoverable fault that occurs during the first
increment of a rising TCC is not blanked. Errata reference: 12519
Fix/Workaround:
None
3 - In Dual slope mode a Retrigger Event does not clear the TCC counter.
Errata reference: 12354
Fix/Workaround:
None
4 - In two ramp mode, two events will be generated per cycle, one on each
ramp’s end. EVCTRL.CNTSEL.END cannot be used to identify the end of a
double ramp cycle. Errata reference: 12224
Fix/Workaround:
None
5 - If an input event triggered STOP action is performed at the same time as
the counter overflows, the first pulse width of the subsequent counter start
can be altered with one prescaled clock cycle. Errata reference: 12107
Fix/Workaround:
None
6 - When the RUNSTDBY bit is written after the TCC is enabled, the
respective TCC APB bus is stalled and the RUNDSTBY bit in the TCC CTRLA
register is not enabled-protected. Errata reference: 12477
Fix/Workaround:
None.
7 - TCC fault filtering on inverted fault is not working. Errata reference:
12512
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Fix/Workaround:
Use only non-inverted faults.
8 - When waking up from the STANDBY power save mode, the
SYNCBUSY.CTRLB and SYNCBUSY.STATUS bits may be locked to 1. Errata
reference: 12227
Fix/Workaround:
After waking up from STANDBY power save mode, perform a software reset of
the TCC if you are using the SYNCBUSY.CTRLB and SYNCBUSY.STATUS bits
9 - When the Peripheral Access Controller (PAC) protection is enabled,
writing to WAVE or WAVEB registers will not cause a hardware exception.
Errata reference: 11468
Fix/Workaround:
None
10 - If the MCx flag in the INTFLAG register is set when enabling the DMA,
this will trigger an immediate DMA transfer and overwrite the current
buffered value in the TCC register. Errata reference: 12155
Fix/Workaround:
None
47.3.11 PTC
1 - WCOMP interrupt flag is not stable. The WCOMP interrupt flag will not
always be set as described in the datasheet. Errata reference: 12860
Fix/Workaround:
Do not use the WCOMP interrupt. Use the WCOMP event.
47.4
Revision D
47.4.1 Device
1 - In single shot mode and at 125°C, the ADC conversions have linearity
errors. Errata reference: 13277
Fix/Workaround:
- Workaround 1: At 125°C, do not use the ADC in single shot mode; use the
ADC in free running mode only.
- Workaround 2: At 125°C, use the ADC in single shot mode only with
VDDANA > 3V.
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2 - In the table ""NVM User Row Mapping"", the WDT Window bitfield default
value on silicon is not as specified in the datasheet. The datasheet defines
the default value as 0x5, while it is 0xB on silicon. Errata reference: 13951
Fix/Workaround:
None.
3 - On pin PA24 and PA25 the pull-up and pull-down configuration is not
disabled automatically when alternative pin function is enabled. Errata
reference: 12368
Fix/Workaround:
For pin PA24 and PA25, the GPIO pull-up and pull-down must be disabled before
enabling alternative functions on them.
4 - If APB clock is stopped and GCLK clock is running, APB read access to
read-synchronized registers will freeze the system. The CPU and the DAP
AHB-AP are stalled, as a consequence debug operation is impossible.
Errata reference: 10416
Fix/Workaround:
Do not make read access to read-synchronized registers when APB clock is
stopped and GCLK is running. To recover from this situation, power cycle the
device or reset the device using the RESETN pin.
5 - In I2C Slave mode, writing the CTRLB register when in the AMATCH or
DRDY interrupt service routines can cause the state machine to reset. Errata
reference: 13574
Fix/Workaround:
Write CTRLB.ACKACT to 0 using the following sequence:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = 0;
// Re-enable interrupts if applicable.
Write CTRLB.ACKACT to 1 using the following sequence:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
// Re-enable interrupts if applicable.
Otherwise, only write to CTRLB in the AMATCH or DRDY interrupts if it is to close
out a transaction.
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When not closing a transaction, clear the AMATCH interrupt by writing a 1 to its bit
position instead of using CTRLB.CMD. The DRDY interrupt is automatically
cleared by reading/writing to the DATA register in smart mode. If not in smart
mode, DRDY should be cleared by writing a 1 to its bit position.
Code replacements examples:
Current:
SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT;
Change to:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = SERCOM_I2CS_CTRLB_ACKACT;
// Re-enable interrupts if applicable.
Current:
SERCOM - CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT;
Change to:
// If higher priority interrupts exist, then disable so that the
// following two writes are atomic.
SERCOM - STATUS.reg = 0;
SERCOM - CTRLB.reg = 0;
// Re-enable interrupts if applicable.
Current:
/* ACK or NACK address */
SERCOM - CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(0x3);
Change to:
// CMD=0x3 clears all interrupts, so to keep the result similar,
// PREC is cleared if it was set.
if (SERCOM - INTFLAG.bit.PREC) SERCOM - INTFLAG.reg =
SERCOM_I2CS_INTFLAG_PREC;
SERCOM - INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH;
6 - PA24 and PA25 cannot be used as input when configured as GPIO with
continuous sampling (cannot be read by PORT). Errata reference: 12005
Fix/Workaround:
- Use PA24 and PA25 for peripherals or only as output pins.
- Or configure PA31 to PA24 for on-demand sampling (CTRL[31:24] all zeroes)
and access the IN register through the APB (not the IOBUS), to allow waiting for
on-demand sampling.
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7 - Rx serializer in the RIGHT Data Slot Formatting Adjust mode (SERCTRL.SLOTADJ clear)
does not work when the slot size is not 32 bits. Errata reference: 13411
Fix/Workaround:
In SERCTRL.SERMODE RX, SERCTRL.SLOTADJ RIGHT must be used with
CLKCTRL.SLOTSIZE 32.
8 - The SYSTICK calibration value is incorrect. Errata reference: 14154
Fix/Workaround:
The correct SYSTICK calibration value is 0x40000000. This value should not be used to initialize
the Systick RELOAD value register, which should be initialized instead with a value depending on
the main clock frequency and on the tick period required by the application. For a detailed
description of the SYSTICK module, refer to the official ARM Cortex-M0+ documentation.
9 - While the internal startup is not completed, PA07 pin is driven low by the chip. Then as all
the other pins it is configured as an High Impedance pin. Errata reference: 12118
Fix/Workaround:
None
10 - If the external XOSC32K is broken, neither the external pin RST nor the GCLK software
reset can reset the GCLK generators using XOSC32K as source clock. Errata reference:
12164
Fix/Workaround:
Do a power cycle to reset the GCLK generators after an external XOSC32K failure.
11 - The voltage regulator in low power mode is not functional at temperatures above 85C.
Errata reference: 12291
Fix/Workaround:
Enable normal mode on the voltage regulator in standby sleep mode.
Example code:
// Set the voltage regulator in normal mode configuration in standby sleep mode
SYSCTRL->VREG.bit.RUNSTDBY = 1;
47.4.2 DSU
1 - If a debugger has issued a DSU Cold-Plugging procedure and then released the CPU
from the resulting ""CPU Reset Extension"", the CPU will be held in ""CPU Reset
Extension"" after any upcoming reset event. Errata reference: 12015
Fix/workaround:
The CPU must be released from the ""CPU Reset Extension"" either by writing a one in the DSU
STATUSA.CRSTEXT register or by applying an external reset with SWCLK high or by power
cycling the device.
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2 - The MBIST ""Pause-on-Error"" feature is not functional on this device. Errata reference:
14324
Fix/Workaround: Do not use the ""Pause-on-Error"" feature.
47.4.3 PM
1 - In debug mode, if a watchdog reset occurs, the debug session is lost. Errata reference:
12196
Fix/Workaround:
A new debug session must be restart after a watchdog reset.
47.4.4 XOSC32K
1 - The automatic amplitude control of the XOSC32K does not work. Errata reference: 10933
Fix/Workaround:
Use the XOSC32K with Automatic Amplitude control disabled (XOSC32K.AAMPEN = 0)
47.4.5 DFLL48M
1 - The DFLL clock must be requested before being configured otherwise a write access to a
DFLL register can freeze the device. Errata reference: 9905
Fix/Workaround:
Write a zero to the DFLL ONDEMAND bit in the DFLLCTRL register before configuring the DFLL
module.
2 - If the DFLL48M reaches the maximum or minimum COARSE or FINE calibration values
during the locking sequence, an out of bounds interrupt will be generated. These interrupts
will be generated even if the final calibration values at DFLL48M lock are not at maximum or
minimum, and might therefore be false out of bounds interrupts. Errata reference: 10669
Fix/Workaround:
Check that the lockbits: DFLLLCKC and DFLLLCKF in the SYSCTRL Interrupt Flag Status and
Clear register (INTFLAG) are both set before enabling the DFLLOOB interrupt.
3 - The DFLL status bits in the PCLKSR register during the USB clock recovery mode can be
wrong after a USB suspend state. Errata reference: 11938
Fix/Workaround:
Do not monitor the DFLL status bits in the PCLKSR register during the USB clock recovery mode.
47.4.6 DMAC
1 - If data is written to CRCDATAIN in two consecutive instructions, the CRC computation
may be incorrect. Errata reference: 13507
Fix/Workaround:
Add a NOP instruction between each write to CRCDATAIN register.
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47.4.7 NVMCTRL
1 - Default value of MANW in NVM.CTRLB is 0. Errata reference: 13134
This can lead to spurious writes to the NVM if a data write is done through a pointer with a wrong
address corresponding to NVM area.
Fix/Workaround:
Set MANW in the NVM.CTRLB to 1 at startup
2 - When the part is secured and EEPROM emulation area configured to none, the CRC32 is
not executed on the entire flash area but up to the on-chip flash size minus half a row. Errata
reference: 11988
Fix/Workaround:
When using CRC32 on a protected device with EEPROM emulation area configured to none,
compute the reference CRC32 value to the full chip flash size minus half row.
3 - When external reset is active it causes a high leakage current on VDDIO. Errata
reference: 13446
Fix/Workaround:
Minimize the time external reset is active.
47.4.8 SERCOM
1 - The I2C Slave SCL Low Extend Time-out (CTRLA.SEXTTOEN) and Master SCL Low
Extend Time-out (CTRLA.MEXTTOEN) cannot be used if SCL Low Time-out
(CTRLA.LOWTOUT) is disabled. When SCTRLA.LOWTOUT=0, the GCLK_SERCOM_SLOW is
not requested. Errata reference: 12003
Fix/Workaround:
To use the Master or Slave SCL low extend time-outs, enable the SCL Low Time-out
(CTRLA.LOWTOUT=1).
2 - In USART autobaud mode, missing stop bits are not recognized as inconsistent sync
(ISF) or framing (FERR) errors. Errata reference: 13852
Fix/Workaround:
None
3 - If the SERCOM is enabled in SPI mode with SSL detection enabled (CTRLB.SSDE) and
CTRLB.RXEN=1, an erroneous slave select low interrupt (INTFLAG.SSL) can be generated.
Errata reference: 13369
Fix/Workaround:
Enable the SERCOM first with CTRLB.RXEN=0. In a subsequent write, set CTRLB.RXEN=1.
4 - In TWI master mode, an ongoing transaction should be stalled immediately when
DBGCTRL.DBGSTOP is set and the CPU enters debug mode. Instead, it is stopped when the
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current byte transaction is completed and the corresponding interrupt is triggered if
enabled. Errata reference: 12499
Fix/Workaround:
In TWI master mode, keep DBGCTRL.DBGSTOP=0 when in debug mode.
47.4.9 TC
1 - Spurious TC overflow and Match/Capture events may occur. Errata reference: 13268
Fix/Workaround:
Do not use the TC overflow and Match/Capture events. Use the corresponding Interrupts instead.
47.4.10 TCC
1 - In RAMP 2 mode with Fault keep, qualified and restart: Errata reference: 13262
If a fault occurred at the end of the period during the qualified state, the switch to the next ramp can
have two restarts.
Fix/Workaround:
Avoid faults few cycles before the end or the beginning of a ramp.
2 - With blanking enabled, a recoverable fault that occurs during the first increment of a
rising TCC is not blanked. Errata reference: 12519
Fix/Workaround:
None
3 - In Dual slope mode a Retrigger Event does not clear the TCC counter. Errata reference:
12354
Fix/Workaround:
None
4 - In two ramp mode, two events will be generated per cycle, one on each ramp’s end.
EVCTRL.CNTSEL.END cannot be used to identify the end of a double ramp cycle. Errata
reference: 12224
Fix/Workaround:
None
5 - If an input event triggered STOP action is performed at the same time as the counter
overflows, the first pulse width of the subsequent counter start can be altered with one
prescaled clock cycle. Errata reference: 12107
Fix/Workaround:
None
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6 - When the RUNSTDBY bit is written after the TCC is enabled, the respective TCC APB bus
is stalled and the RUNDSTBY bit in the TCC CTRLA register is not enabled-protected. Errata
reference: 12477
Fix/Workaround:
None.
7 - TCC fault filtering on inverted fault is not working. Errata reference: 12512
Fix/Workaround:
Use only non-inverted faults.
8 - When waking up from the STANDBY power save mode, the SYNCBUSY.CTRLB and
SYNCBUSY.STATUS bits may be locked to 1. Errata reference: 12227
Fix/Workaround:
After waking up from STANDBY power save mode, perform a software reset of the TCC if you are
using the SYNCBUSY.CTRLB and SYNCBUSY.STATUS bits
9 - When the Peripheral Access Controller (PAC) protection is enabled, writing to WAVE or
WAVEB registers will not cause a hardware exception. Errata reference: 11468
Fix/Workaround:
None
10 - If the MCx flag in the INTFLAG register is set when enabling the DMA, this will trigger an
immediate DMA transfer and overwrite the current buffered value in the TCC register. Errata
reference: 12155
Fix/Workaround:
None
47.4.11 PTC
1 - WCOMP interrupt flag is not stable. The WCOMP interrupt flag will not always be set as
described in the datasheet. Errata reference: 12860
Fix/Workaround:
Do not use the WCOMP interrupt. Use the WCOMP event.
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48.
Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The referring revision in this
section are referring to the document revision.
48.1
Rev. G – 05/2016
General:
Removed references to device variant B.
Removed references to EEPROM Read While Write (RWW).
“I/O Multiplexing and Considerations” on page 12:
SWDIO added to the COM column in Table 5-1.
“EVSYS – Event System” on page 400:
CTRL.SWRST bit description updated.
“TCC – Timer/Counter for Control Applications” on page 609:
Table 28-1 on page 609: Number of waveform output (WO_NUM) for TCC0 updated from 8 to 6.
Register Summary: INTENCLR, INTENSET and INTFLAG registers updated.
“USB – Universal Serial Bus” on page 702:
HSOFC.FLENCE bit description updated.
“Schematic Checklist” on page 1112:
“External Real Time Oscillator” on page 1117: Table listing equivalent internal pin capacitance removed and replaced
with a reference to the electrical characteristics chapter.
48.2
Rev. F – 11/2015
Introduced 256KB+512KB Flash Offering:
“Ordering Information” on page 6: Added ATSAMR21E19A-MF and -MFT.
“Product Mapping” on page 23: Added SAM R21E19A to “Physical Memory Map” on page 24.
“Block Diagrams” on page 8: Updated “SAM R21 Interconnection” on page 9.
“DSU – Device Service Unit” on page 45: Added SAM R21E18A to Table 11-8.
“Electrical Characteristics” on page 1055: Added STANDBY current consumption numbers for SAM R21E19A in
“Power Consumption” on page 1060.
“Packaging Information” on page 1107: Added “32-pin QFN (32M5)” on page 1110.
“Electrical Characteristics at 125°C” on page 1171: Added VDD minimum voltage for SAM R21E19 in “General
Operating Ratings” on page 1171 and added section “Supply Characteristics” on page 1172.
“AT86RF233 Extended Feature Set” on page 1005
Added “High Data Rate Modes” on page 1013 (Only applicable for T= -40°C to 85°C).
“I/O Multiplexing and Considerations” on page 12:
Added USB/SOF1kHz to PA23 in the COM column in Table 5-1.
“SYSCTRL – System Controller” on page 143:
Updated description in “Drift Compensation” on page 151.
“NVMCTRL – Non-Volatile Memory Controller” on page 350
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Updated Product Dependencies, Clocks section: Removed reference to the AUTOWS bit.
“ADC – Analog-to-Digital Converter” on page 802:
Table 30-14: ADC AIN9 pin removed.
References to AREFB replaced with VREFB.
INPUTCTRL Register: Updated Table 30-14.
REFCTRL.REFSEL: Value 0x3 corrected to “Reserved” in Table 30-7.
“RFCTRL – AT86RF233 Front-End Control Signal Interface” on page 876
Updated Product Dependencies section.
“Electrical Characteristics” on page 1055
“Digital Frequency Locked Loop (DFLL48M) Characteristics” on page 1086: Removed note from Table 42-40.
“Schematic Checklist” on page 1112:
“Power Supply Connections” on page 1112: VDDCORE decoupling capacitor value updated from 100nF to 1µF.
References to AREFB replaced with VREFB.
“Electrical Characteristics at 125°C” on page 1171
“Digital Frequency Locked Loop (DFLL48M) Characteristics” on page 1187: Removed note from DFLL48M
Characteristics - Closed Loop Mode table.
“Power Consumption” on page 1174: Power consumption units updated.
48.3
Rev. E – 02/2015
“Description” on page 1
CoreMark score updated from 2.14 to 2.46 CoreMark/MHz.
“Processor And Architecture” on page 28:
“Configuration” on page 33: Removed green connection dots between DMAC Data and AHB-APB Bridge A and
Bridge B.
“AT86RF233 Microcontroller Interface” on page 883:
Figure 35-1: EXTINT1 replaced by EXTINT0.
“Schematic Checklist” on page 1112
Updated description in “Unused or Unconnected Pins” on page 1115.
“References” on page 1170:
Removed reference [7] AT86RF233 Software Programming Model.
48.4
Rev. D – 02/2015
“Description” on page 1 and “Features” on page 2:
Updated 250kB/s to 250kb/s.
“PORT” on page 373:
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“I/O Pin Configuration” on page 378: Removed reference to “open-drain”.
Access for DRVSTR bit in Pin Configuration n register (PINCFGn.DRVCTR) updated from W to R/W.
Errata:
Updated errata for revision A, B, C, D: Added Errata Reference 13507.
48.5
Rev. C – 01/2015
“DSU – Device Service Unit” on page 45:
Register Description: DID.DEVSEL, Table 11-8 Device Selection updated.
“SYSCTRL – System Controller” on page 143:
Removed references to XOSC32K and OSC32K 1kHz clock output option:
- XOSC32K: “32kHz External Crystal Oscillator (XOSC32K) Operation” on page 148
- OSC32K: “32kHz Internal Oscillator (OSC32K) Operation” on page 149
1kHz Output Enable (EN1K) bit set as reserved bit:
- Bit 4 in XOSC32K
- Bit 3 in OSC32K
“Electrical Characteristics” on page 1055:
“Brown-Out Detectors Characteristics” on page 1070: Added Figure 42-3 and Figure 42-4 and updated conditions in
Table 42-17 and Table 42-18.
Errata:
Updated errata for revision A: Added Errata Reference 10933, 12015, 12291, 12354, 12368, 12499, 13268, 13277,
13574.
Updated errata for revision B: Added Errata Reference 10933, 12015, 12291, 12368, 12499, 13268, 13277, 13574.
Updated errata for revision C: Added Errata Reference 12291, 13574, 13951.
Added errata for revision D.
“Electrical Characteristics at 125°C” on page 1171:
Electrical characteristics for 125°C added.
48.6
Rev. B – 09/2014
“Block Diagrams” on page 8
NVM Controller bus connection changed from Master to Slave.
“Clock System” on page 82
“Register Synchronization” on page 83 updated by splitting the section into “Common Synchronizer Register
Synchronization” on page 83 and “Distributed Synchronizer Register Synchronization” on page 86.
“Electrical Characteristics” on page 1055
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“Analog-to-Digital (ADC) Characteristics” on page 1072: Added note defining gain accuracy parameter in:
- ADC Differential Mode, Table 42-20
- ADC Single-Ended Mode, Table 42-21
Errata
Updated errata for revision A and B: Added Errata Reference 13140, 12860.
Added errata for revision C.
48.7
Rev. A – 07/2014
Initial revision
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Appendix A. Continuous Transmission Test Mode
A.1
Overview
The AT86RF233 offers a Continuous Transmission Test Mode to support final application / production tests as well as
certification tests. Using this test mode, the radio transceiver transmits continuously a previously transferred frame
(PRBS mode) or a continuous wave signal (CW mode).
In CW mode, two different signal frequencies per channel can be transmitted:
z
f1[MHz] = Fc[MHz] = 2405[MHz] + 5[MHz] x (k – 11), for k = 11, 12, ..., 26[MHz] + 0.5MHz
z
f2[MHz] = Fc[MHz] = 2405[MHz] + 5[MHz] x (k – 11), for k = 11, 12, ..., 26[MHz] - 0.5MHz
Where Fc is the channel center frequency, refer to “RF Channel Selection” on page 994.
Note:
1.
In CW mode, it is not possible to transmit a RF signal directly on the channel center frequency.
PSDU data in the Frame Buffer must contain at least a valid PHR (see “Introduction – IEEE 802.15.4-2006 Frame
Format” on page 947). It is recommended to use a frame of maximum length (127 bytes) and arbitrary PSDU data for the
PRBS mode. The SHR and the PHR are not transmitted. The transmission starts with the PSDU data and is repeated
continuously.
A.2
Configuration
Before enabling Continuous Transmission Test Mode all register configurations should be done as follow:
z
TX channel setting (optional)
z
TX output power setting (optional)
z
Mode selection (PRBS / CW)
A register access to register 0x36 and 0x1C enables the Continuous Transmission Test Mode.
The transmission is started by enabling the PLL (TRX_CMD = PLL_ON) and writing the TX_START command to
register 0x02.
Even for CW signal transmission, it is required to write valid PSDU data to the Frame Buffer. For PRBS mode it is
recommended to write a frame of maximum length.
The detailed programming sequence is shown in Table 48-1. The column R/W informs about writing (W) or reading (R) a
register or the Frame Buffer.
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Table 48-1. Continuous Transmission Programming Sequence.
Step
Action
Register
R/W
Value
Description
1
RESET
2
Register
Access
0x0E
W
0x01
Set IRQ mask register, enable IRQ_0 (PLL_LOCK)
3
Register
Access
0x04
W
0x00
Disable TX_AUTO_CRC_ON
4
Register
Access
0x02
W
0x03
Set radio transceiver state TRX_OFF
5
Register
Access
0x03
W
0x01
Set clock at internal pad CLKM)
6
Register
Access
0x08
W
0x33
Set IEEE 802.15.4 CHANNEL, for example channel 19
7
Register
Access
0x05
W
0x00
Set TX output power, for example to PTX_MAX
8
Register
Access
0x01
R
0x08
Verify TRX_OFF state
9
Register
Access
0x36
W
0x0F
Enable Continuous Transmission Test Mode – step # 1
10(1)
Register
Access
0x0C
W
0x03
Enable raw data mode
11(1)
Register
Access
0x0A
W
0x37
Enable raw data mode
12(2)
Frame Buffer
Write Access
13
Register
Access
0x1C
W
0x54
Enable Continuous Transmission Test Mode – step # 2
14
Register
Access
0x1C
W
0x46
Enable Continuous Transmission Test Mode – step # 3
15
Register
Access
0x02
W
0x09
Enable PLL_ON state
16
Interrupt event
0x0F
R
0x01
Wait for IRQ_0 (PLL_LOCK)
17
Register
Access
0x02
W
0x02
18
Measurement
19
Register
Access
20
RESET
Reset AT86RF233
Write packet header containing the following number of
bytes for with PSDU data (even for CW mode), refer to
Table 48-2
W
Initiate Transmission,
enter BUSY_TX state
Perform measurement
0x1C
W
0x00
Disable Continuous Transmission Test Mode
Reset AT86RF233
Notes: 1.
Only required for CW mode, do not configure for PRBS mode.
2.
Frame Buffer content varies for different modulation schemes.
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The content of the Frame Buffer has to be defined for Continuous Transmission PRBS mode or CW mode. To measure
the power spectral density (PSD) mask of the transmitter it is recommended to use a random sequence of maximum
length for the PSDU data.
To measure CW signals it is necessary to write either 0x00 or 0xFF to the Frame Buffer, for details refer to Table 48-2.
Table 48-2. Frame Buffer Content for various Continuous Transmission Modulation Schemes.
Step
12
Action
Frame Content
Frame Buffer Access
Note:
1.
Comment
Random Sequence
Modulated RF signal
Number of bytes and 0x00 (each byte of
PSDU)
Fc – 0.5MHz, CW signal
Number of bytes and 0xFF (each byte of
PSDU)
Fc + 0.5MHz, CW signal
It is recommended to use a frame of maximum length (127 bytes).
A.3
Register Description
A.3.1
TST_CTRL_DIGI
The TST_CTRL_DIG register enables the continuous transmission test mode.
Name:
TST_CTRL_DIGI
Offset:
0x36
Reset:
0x00
Property:
-
Bit
7
6
5
4
3
2
1
0
TST_CTRL_DIG
0x36
Access
Reset
z
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit 3:0 - TST_CTRL_DIG
The register bits TST_CTRL_DIG with value 0xF enables continuous transmission.
Table 48-3. TST_CTRL_DIG
Value
Description
0x0
No mode is active
0xF
Continuous Transmission enabled
All other values are reserved
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Appendix B. References
1.
IEEE Standard 802.15.4™ 2003: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (WPANs).
2.
IEEE Standard 802.15.4™ 2006: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (WPANs).
3.
IEEE Standard 802.15.4™ 2011: Low-Rate Wireless Personal Area Networks (WPANs).
4.
ANSI/ESD STM5.1 - 2007, Electrostatic Discharge Sensitivity Testing - Human Body Model (HBM); JESD22A114E - 2006; CEI/IEC 60749-26 - 2006; AEC-Q100-002-Ref-D.
5.
ESD-STM5.3.1-1999: ESD Association Standard Test Method for electrostatic discharge sensitivity testing Charged Device Model (CDM).
6.
NIST FIPS PUB 197: Advanced Encryption Standard (AES), Federal Information Processing Standards Publication 197, US Department of Commerce/NIST, November 26, 2001.
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Appendix C. Electrical Characteristics at 125°C
C.1
Disclaimer
All typical values are measured at T = 25°C unless otherwise specified. All minimum and maximum values are valid
across operating temperature and voltage unless otherwise specified.
C.2
Absolute Maximum Ratings
Stresses beyond those listed in Table C-1 may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Table C-1.
Symbol
Absolute Maximum Ratings
Parameter
Condition
Min.
Max.
Units
VDD
Power supply voltage
0
3.8
V
IDD
Current into a VDD pin
-
28
mA
IGND
Current out of a GND pin
-
39
mA
VPIN
Pin voltage with respect to GND
and VDD
GND-0.3V
VDD+0.3V
V
VANA
Voltage on RFP, RFN, AVDD and
DVDD
-0.3
2.0
V
VESD
ESD robustness
PRF
Input RF level
Human Body Model (HBM) [4]
4
kV
Charged Device Model (CDM)
[5]
550
V
+10
dBm
260
C
150
C
T = 10s
TLEAD
Lead temperature
Tstorgae
Storage temperature
Note:
(soldering profile compliant with
IPC/JEDEC J STD 020B)
-60
1. Maximum source current is 14mA and maximum sink current is 19.5mA per cluster. A cluster is a group of GPIOs as
shown in . Also note that each VDD/GND pair is connected to 2 clusters so current consumption through the pair will
be a sum of the clusters source/sink currents.
Caution! ESD sensitive device.
Precaution should be used when handling the device in order to prevent permanent damage.
C.3
General Operating Ratings
The device must operate within the ratings listed in Table C-2 in order for all other electrical characteristics and typical
characteristics of the device to be valid.
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Table C-2.
General Operating Conditions
Symbol
Parameter
Condition
Min.
1.8(1)
VDD
Power supply voltage
Voltage on VDDIN, VDDIO and
VDDANA(2)
VDD1.8
Power supply voltage
(on AVDD and DVDD)
External supply voltage(3)
VDDANA
Analog supply voltage
TA
Temperature range
TJ
Junction temperature
Notes: 1.
Max.
Units
3.3
3.6
V
1.7
1.8
1.9
V
1.8(1)
3.3
3.6
V
-40
25
125
°C
-
-
145
°C
2.35(4)
With BOD33 disabled. If the BOD33 is enabled, check Table 42-17.
2.
Even if an implementation uses the external 1.8V voltage supply VDD1.8 it is required to connect VDD.
3.
AT86RF233 register 0x10 (VREG_CTRL) needs to be programmed to disable internal voltage regulators and supply blocks by an external 1.8V supply, refer to “Voltage Regulators (AVREG, DVREG)” on page 983.
Applicable for the SAM R21E19 due to the VDD minimum supply voltage of the Serial Flash.
4.
C.4
Typ.
Supply Characteristics
The following characteristics are applicable to the operating temperature range: TA = -40°C to 125°C, unless otherwise
specified and are valid for a junction temperature up to TJ = 100 C. Refer to “Power Supply and Start-Up Considerations”
on page 20.
Table 48-4. Supply Characteristics
Voltage
Symbol
Conditions
VDDIO
VDDIN
VDDANA
Full Voltage Range
Note:
1.
Min.
Max.
Units
1.8 / 2.35(1)
3.6
V
2.35V is only applicable for the SAM R21E19 due to the VDD minimum supply voltage of the Serial Flash.
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C.5
Maximum Clock Frequencies
Table C-3.
Maximum GCLK Generator Output Frequencies
Symbol
Description
Conditions
Max.
Units
Undivided
96
MHz
Divided
32
MHz
Max.
Units
fGCLKGEN0 / fGCLK_MAIN
fGCLKGEN1
fGCLKGEN2
fGCLKGEN3
fGCLKGEN4
fGCLKGEN5
GCLK Generator Output
Frequency
fGCLKGEN6
fGCLKGEN7
fGCLKGEN8
Table C-4.
Maximum Peripheral Clock Frequencies
Symbol
Description
fCPU
CPU clock frequency
32
MHz
fAHB
AHB clock frequency
32
MHz
fAPBA
APBA clock frequency
32
MHz
fAPBB
APBB clock frequency
32
MHz
fAPBC
APBC clock frequency
32
MHz
DFLL48M Reference clock frequency
33
KHz
FDPLL96M Reference clock frequency
2
MHz
FDPLL96M 32k Reference clock frequency
32
KHz
fGCLK_WDT
WDT input clock frequency
48
MHz
fGCLK_RTC
RTC input clock frequency
48
MHz
fGCLK_EIC
EIC input clock frequency
48
MHz
fGCLK_USB
USB input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_0
EVSYS channel 0 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_1
EVSYS channel 1 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_2
EVSYS channel 2 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_3
EVSYS channel 3 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_4
EVSYS channel 4 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_5
EVSYS channel 5 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_6
EVSYS channel 6 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_7
EVSYS channel 7 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_8
EVSYS channel 8 input clock frequency
48
MHz
fGCLK_DFLL48M_REF
fGCLK_DPLL
fGCLK_DPLL_32K
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Table C-4.
Maximum Peripheral Clock Frequencies (Continued)
Symbol
Max.
Units
fGCLK_EVSYS_CHANNEL_9
EVSYS channel 9 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_10
EVSYS channel 10 input clock frequency
48
MHz
fGCLK_EVSYS_CHANNEL_11
EVSYS channel 11 input clock frequency
48
MHz
fGCLK_SERCOMx_SLOW
Common SERCOM slow input clock
frequency
48
MHz
fGCLK_SERCOM0_CORE
SERCOM0 input clock frequency
48
MHz
fGCLK_SERCOM1_CORE
SERCOM1 input clock frequency
48
MHz
fGCLK_SERCOM2_CORE
SERCOM2 input clock frequency
48
MHz
fGCLK_SERCOM3_CORE
SERCOM3 input clock frequency
48
MHz
fGCLK_SERCOM4_CORE
SERCOM4 input clock frequency
48
MHz
fGCLK_SERCOM5_CORE
SERCOM5 input clock frequency
48
MHz
fGCLK_TCC0, GCLK_TCC1
TCC0,TCC1 input clock frequency
80
MHz
fGCLK_TCC2, GCLK_TC3
TCC2,TC3 input clock frequency
80
MHz
fGCLK_TC4, GCLK_TC5
TC4,TC5 input clock frequency
48
MHz
ADC input clock frequency
48
MHz
fGCLK_AC_DIG
AC digital input clock frequency
48
MHz
fGCLK_AC_ANA
AC analog input clock frequency
64
KHz
PTC input clock frequency
48
MHz
fGCLK_ADC
fGCLK_PTC
C.6
Description
Power Consumption
The values in Table C-5 are measured values of power consumption under the following conditions, except where noted:
z
Operating conditions
z
VVDDIN = 3.3V
z
Wake up time from sleep mode is measured from the edge of the wakeup signal to the execution of the first
instruction fetched in flash.
z
Oscillators
z
z
XOSC32K (32kHz crystal oscillator) stopped
z
XOSC (crystal oscillator) running with external 32MHz clock on XIN
z
DFLL48M stopped
Clocks
z
XOSC used as main clock source, except otherwise specified
z
CPU, AHB clocks undivided
z
APBA clock divided by 4
z
APBB and APBC bridges off
z
The following AHB module clocks are running: NVMCTRL, APBA bridge
z
The following peripheral clocks running: PM, SYSCTRL, RTC
z
z
All other AHB clocks stopped
All other peripheral clocks stopped
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z
I/Os are inactive with internal pull-up
z
CPU is running on flash with 1 wait states
z
Cache enabled
z
BOD33 disabled
z
AT86RF233 has to be set in Deep Sleep
z
Stacked serial Flash not included
Table C-5.
Mode
Current Consumption
Min.
Typ.
Max.
CPU running a While(1) algorithm
-
3.75
4.12
CPU running a While(1) algorithm VDDIN=1.8V,
CPU is running on Flash with 3 wait states
-
3.77
4.13
CPU running a While(1) algorithm, CPU is
running on Flash with 3 wait states with
GCLKIN as reference
-
62*freq
+422
62*freq
+484
CPU running a Fibonacci algorithm
-
4.85
5.29
CPU running a Fibonacci algorithm
VDDIN=1.8V, CPU is running on flash with 3
-
4.87
5.29
-
88*freq
+424
88*freq
+486
-
6.70
7.30
-
5.98
6.41
-
108*freq
+426
108*freq
+492
IDLE0
-
2.40
2.69
IDLE1
-
1.79
2.05
IDLE2
-
1.50
1.76
XOSC32K running
RTC running at 1kHz(1)
-
350.0
852
XOSC32K and RTC stopped()
-
348.0
850
ACTIVE
Conditions
TA
Units
mA
µA
(with freq
in MHz)
mA
wait states
CPU running a Fibonacci algorithm, CPU is
running on Flash with 3 wait states with
GCLKIN as reference
CPU running a CoreMark algorithm
CPU running a CoreMark algorithm
VDDIN=1.8V, CPU is running on flash with 3
125 C
µA
(with freq
in MHz)
mA
wait states
CPU running a CoreMark algorithm, CPU is
running on Flash with 3 wait states with
GCLKIN as reference
STANDBY
Note:
1.
µA
(with freq
in MHz)
mA
µA
Measurements were done with SYSCTRL->VREG.bit.RUNSTDBY = 1
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Table C-6.
Wake-up Time
Mode
Conditions
IDLE0
Min.
Typ.
Max.
OSC8M used as main clock source, Cache
disabled
3.9
4
4.1
OSC8M used as main clock source, Cache
disabled
13.5
14.9
16.4
IDLE1
I
IDLE2
I
STANDBY
I
Figure C-1.
TA
OSC8M used as main clock source, Cache
disabled
125 C
OSC8M used as main clock source, Cache
disabled
Units
µs
14.4
15.8
17.2
19.2
20.6
22.1
Measurement Schematic
VDDIN
VDDANA
VDDIO
Amp 0
VDDCORE
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C.7
Analog Characteristics
C.7.1
Power-On Reset (POR) Characteristics
VPOT+
VPOT-
Figure C-2.
Parameter
Conditions
Voltage threshold on VDD
rising
Voltage threshold on VDD falling
I
VDD falls at 1V/ms or slower
Min.
Typ.
Max.
Units
1.27
1.45
1.58
V
0.53
0.99
1.32
V
POR Operating Principle
VDD
Symbol
POR Characteristics
VPOT+
VPOT-
Time
Reset
Table C-7.
Atmel | SMART SAM R21 [DATASHEET]
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C.7.2
Brown-Out Detectors Characteristics
BOD33
Table C-8.
BOD33 Characteristics
Symbol
Parameter
Conditions
Temp.
Min.
Typ.
Max.
Units
-
34
-
mV
I
Step size, between
adjacent values in
BOD33.LEVEL
VHYST
VBOD+ - VBOD-
Hysteresis ON
35
-
170
mV
Detection time
Time with
VDDANA < VTH
necessary to
generate a
reset signal
-
0.9(1)
-
s
25 C
-
25
48
-40- to 125 C
-
-
50
25 C
-
0.034
0.21
-40- to 125 C
-
-
2.92
0.132
0.38
tDET
IIdleBOD33
Current
consumption om
Active/Idle mode
ISbyBOD33
Current
consumption in
Standby mode
tSTARTUP
Startup time
Note:
C.7.3
1.
Continuous mode
Sampling mode
25 C
Sampling mode
-40- to 125 C
1.62
-40- to 125 C
-
1.2(1)
-
µA
µA
s
These values are based on simulation. These values are not covered by test limits in production or
characterization.
Analog-to-Digital (ADC) Characteristics
Table C-9.
Operating Conditions
Symbol
Parameter
RES
Resolution
ADC Clock frequency
fCLK_ADC
Conditions
(1)
Sample rate
Min.
Typ.
Max.
Units
I
8
-
12
bits
I
30
-
2100
kHz
Single shot (with
VDDANA > 3.0V)(4)
5
-
300
ksps
Free running
5
-
350
ksps
0.5
-
-
cycles
-
6
-
cycles
1.0
-
VDDANA-0.6
V
-
1.0
-
V
-
VDDANA/1.48
-
V
-1.0
-
+1.0
%
(1)
Sampling time
Conversion time(1)
VREF
Voltage reference range
VREFINT1V
Internal 1V reference (2)
1x Gain
(2)
VREFINTVCC0
Internal ratiometric reference 0
VREFINTVCC0
Internal ratiometric reference 0(2)
error
Voltage Error
2.0V <
VDDANA2.0V
-
VDDANA/2
-
V
VREFINTVCC1
Internal ratiometric reference 1(2)
error
2.0V <
VDDANA 3.0V (cf. ADC errata)
Differential Mode
Parameter
Conditions
Min.
Typ.
Max.
Units
-
10.5
10.9
bits
Effective Number Of Bits
With gain compensation
TUE
Total Unadjusted Error
I
1x Gainn
1.5
4.3
17.0
LSB
INLI
Integral Non Linearity
1x Gainn
1.0
1.3
6.5
LSB
DNL
Differential Non Linearity
1x Gainn
+/-0.3
+/-0.5
+/-0.95
LSB
Ext. Ref 1x
-15.0
2.5
+20.0
mV
-20
-1.5
+20.0
mV
Bandgap
-15.0
-5.0
+15.0
mV
Ext. Ref. 0.5x
+/-0.1
+/-0.2
+/-0.45
%
Ext. Ref. 2x to 16x
+/-0.1
+/-0.2
+/-2.0
%
Ext. Ref. 1x
-10.0
-1.5
+10.0
mV
VREF=VDDANA/1.48
-10.0
0.5
+15.0
mV
Bandgap
-10.0
3.0
+15.0
mV
64.2
70.0
78.9
dB
I
I
I
Gain Error
Gain Accuracy(5)
Offset Error
VREF=VDDANA/1.48
SFDR
Spurious Free Dynamic Range
SINAD
Signal-to-Noise and Distortion
FCLK_ADC = 2.1MHz
61.4
65.0
66
dB
Signal-to-Noise Ratio
FIN = 40kHz
64.3
65.5
66.0
dB
Total Harmonic Distortion
AIN = 95%FSR
-74.8
-64.0
-65.0
dB
Noise RMS
T=25 C
0.6
1.0
1.6
mV
SNR
THD
1x Gain
Notes: 1. Maximum numbers are based on characterization and not tested in production, and valid for 5% to 95% of the input
voltage range.
2. Dynamic parameter numbers are based on characterization and not tested in production.
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3. Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel common mode voltage):
c.
d.
If |VIN| > VREF/4
z
VCM_IN < 0.95*VDDANA + VREF/4 – 0.75V
z
VCM_IN > VREF/4 -0.05*VDDANA -0.1V
If |VIN| < VREF/4
z
VCM_IN < 1.2*VDDANA - 0.75V
z
VCM_IN > 0.2*VDDANA - 0.1V
4. The ADC channels on pins PA08, PA09 are powered from the VDDIO power supply. The ADC performance of these
pins will not be the same as all the other ADC channels on pins powered from the VDDANA power supply.
5. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x 100) /
(2*Vref/GAIN)
Table C-11.
Symbol
ENOB
Single-Ended Mode
Parameter
Conditions
Min.
Typ.
Max.
Units
Effective Number of Bits
With gain compensation
-
9.5
9.8
Bits
TUE
Total Unadjusted Error
1x gain
-
10.5
40.0
LSB
INL
Integral Non-Linearity
1x gain
1.0
1.6
7.5
LSB
DNL
Differential Non-Linearity
1x gain
+/-0.5
+/-0.6
+/-0.95
LSB
Gain Error
Ext. Ref. 1x
-10.0
0.7
+10.0
mV
Ext. Ref. 0.5x
+/-0.1
+/-0.34
+/-0.4
%
Ext. Ref. 2x to 16X
+/-0.01
+/-0.1
+/-0.15
%
-5.0
1.5
+10.0
mV
63.1
65.0
66.5
dB
Gain Accuracy(4)
Offset Error
Ext. Ref. 1x
SFDR
Spurious Free Dynamic Range
SINAD
Signal-to-Noise and Distortion
FCLK_ADC = 2.1MHz
50.7
59.5
61.0
dB
Signal-to-Noise Ratio
FIN = 40kHz
49.9
60.0
64.0
dB
Total Harmonic Distortion
AIN = 95%FSR
-65.4
-63.0
-62.1
dB
Noise RMS
T = 25 C
-
1.0
-
mV
SNR
THD
1x Gain
Notes: 1. Maximum numbers are based on characterization and not tested in production, and for 5% to 95% of the input voltage
range.
2. Respect the input common mode voltage through the following equations (where VCM_IN is the Input channel common mode voltage) for all VIN:
z
VCM_IN < 0.7*VDDANA + VREF/4 – 0.75V
z
VCM_IN > VREF/4 – 0.3*VDDANA - 0.1V
3. The ADC channels on pins PA08, PA09 are powered from the VDDIO power supply. The ADC performance of these
pins will not be the same as all the other ADC channels on pins powered from the VDDANA power supply.
4. The gain accuracy represents the gain error expressed in percent. Gain accuracy (%) = (Gain Error in V x 100) /
(Vref/GAIN)
Inputs and Sample and Hold Acquisition Times
The analog voltage source must be able to charge the sample and hold (S/H) capacitor in the ADC in order to achieve
maximum accuracy. Seen externally the ADC input consists of a resistor ( R SAMPLE ) and a capacitor ( C SAMPLE ). In
addition, the source resistance ( R SOURCE ) must be taken into account when calculating the required sample and hold
time. Figure C-3 shows the ADC input channel equivalent circuit.
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Figure C-3.
ADC Input
VDDANA/2
Analog Input
AINx
RSOURCE
CSAMPLE
RSAMPLE
VIN
To achieve n bits of accuracy, the C SAMPLE capacitor must be charged at least to a voltage of
V CSAMPLE ≥ V IN × ( 1 – 2
–( n + 1 )
The minimum sampling time
)
t SAMPLEHOLD for a given R SOURCE can be found using this formula:
t SAMPLEHOLD ≥ ( R SAMPLE + R SOURCE ) × ( C SAMPLE ) × ( n + 1 ) × ln ( 2 )
for a 12 bits accuracy:
t SAMPLEHOLD ≥ ( R SAMPLE + R SOURCE ) × ( C SAMPLE ) × 9.02
where
1
t SAMPLEHOLD = --------------------2 × f ADC
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1181
C.7.4
Analog Comparator Characteristics
Table C-12.
Symbol
Electrical and Timing
Parameter
Conditions
I
Positive input voltage
range
I
I
Negative input voltage
range
I
I
Offset
-
VDDANA
V
Hysteresis = 0, Fast mode
-15
0.0
+15
mV
Hysteresis = 0, Low power mode
-25
0.0
+25
mV
Hysteresis = 1, Fast mode
20
50
83
mV
Hysteresis = 1, Low power mode
15
40
75
mV
Changes for VACM=VDDANA/2
100mV overdrive, Fast mode
-
60
116
ns
Changes for VACM=VDDANA/2
100mV overdrive, Low power
mode
-
225
370
ns
Enable to ready delay
Fast mode
-
1
2
s
Enable to ready delay
Low power mode
-
12
19
s
-
0.75
1.58
LSB
-
0.25
0.95
LSB
Offset Error (1)(2)
-0.200
0.260
+1.035
LSB
Gain Error (1)(2)
0.55
1.2
2.0
LSB
Min.
Typ.
Max.
Units
-
0.667
-
V
2.2
2.4
2.7
mV/ C
-9
1
14
mV/V
-13.0
-
13.0
C
INL(3)
C.7.5
0
Units
VDDANA
Startup time
DNL
Notes: 1.
Max.
-
Propagation delay
VSCALE
Typ.
0
Hysteresis
tSTARTUP
Min.
(3)
According to the standard equation V(X)=VLSB*(X+1); VLSB=VDDANA/64
2.
Data computed with the Best Fit method
3.
Data computed using histogram
Temperature Sensor Characteristics
Table C-13.
Symbol
Temperature Sensor Characteristics(1)
Parameter
Temperature sensor output
voltage
I
Conditions
T= 25 C, VDDANA = 3.3V
I
Temperature sensor slope
I
Variation over VDDANA voltage
VDDANA=1.8V to 3.6V
I
Temperature sensor
accuracy
Using the method described in
section 36.9.8.2
Note:
1.
These values are based on characterization. These values are not covered by test limits in production.
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1182
C.8
NVM Characteristics
Table C-14.
Maximum Operation Frequency
VDD range
NVM Wait States
1.8V to 2.7V
2.7V to 3.6V
Maximum Operating Frequency
0
14
1
28
2
40
0
24
1
40
Units
MHz
Note that on this flash technology, a max number of 4 consecutive write is allowed per row. Once this number is reached,
a row erase is mandatory.
Table C-15.
Flash Endurance and Data Retention
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
RetNVM25k
Retention after up to 25k
Average ambient 55°C
10
50
-
Years
RetNVM2.5k
Retention after up to 2.5k
Average ambient 55°C
20
100
-
Years
RetNVM100
Retention after up to 100
Average ambient 55°C
25
>100
-
Years
CycNVM
Cycling Endurance(1)
-40°C < Ta < 125°C
25k
150k
-
Cycles
Min.
Typ.
Max.
Units
Note:
1.
An endurance cycle is a write and an erase operation.
EEPROM Emulation(1) Endurance and Data Retention
Table C-16.
Symbol
Parameter
Conditions
RetEEPROM100k
Retention after up to 100k
Average ambient 55 C
10
50
-
Years
RetEEPROM10k
Retention after up to 10k
Average ambient 55 C
20
100
-
Years
CycEEPROM
Cycling Endurance(2)
-40 C < Ta < 125 C
100k
600k
-
Cycles
Notes: 1.
2.
Table C-17.
Symbol
The EEPROM emulation is a software emulation described in the App note AT03265.
An endurance cycle is a write and an erase operation.
NVM Characteristics
Parameter
Conditions
Min.
Typ.
Max.
Units
tFPP
Page programming time
-
-
-
2.5
ms
tFRE
Row erase time
I
-
-
-
6
ms
tFCE
DSU chip erase time
(CHIP_ERASE)
-
-
-
240
ms
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1183
C.9
Oscillators Characteristics
C.9.1
Crystal Oscillator (XOSC) Characteristics
Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN.
Table C-18.
Symbol
fCPXIN
Digital Clock Characteristics
Parameter
Conditions
XIN clock frequency
I
Min.
Typ.
Max.
Units
-
-
32
MHz
Crystal Oscillator Characteristics
The following table describes the characteristics for the oscillator when a crystal is connected between XIN and XOUT as
shown in Figure C-4. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range
given in the table. The exact value of CL can be found in the crystal datasheet. The capacitance of the external capacitors
(CLEXT) can then be computed as follows:
C LEXT = 2 ( CL – C STRAY – C SHUNT )
where CSTRAY is the capacitance of the pins and PCB, CSHUNT is the shunt capacitance of the crystal.
Table C-19.
Symbol
fOUT
ESR
Crystal Oscillator Characteristics
Parameter
Crystal oscillator frequency
Crystal Equivalent Series
Resistance
Safety Factor = 3
The AGC doesn t have any
noticeable impact on these
measurements.
CXIN
Parasitic capacitor load
CXOUT
Parasitic capacitor load
Conditions
Min.
Typ.
Max.
Units
0.4
-
32
MHz
f = 0.455MHz, CL = 100pF
XOSC.GAIN = 0
-
-
5.6K
f = 2MHz, CL = 20pF
XOSC.GAIN = 0
-
-
416
f = 4MHz, CL = 20pF
XOSC.GAIN = 1
-
-
243
f = 8MHz, CL = 20pF
XOSC.GAIN = 2
-
-
138
f = 16MHz, CL = 20pF
XOSC.GAIN = 3
-
-
66
f = 32MHz, CL = 18pF
XOSC.GAIN = 4
-
-
56
I
-
5.9
-
pF
-
3.2
-
pF
I
Ω
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1184
Table C-19.
Symbol
IXOSC
tSTARTUP
Figure C-4.
Crystal Oscillator Characteristics (Continued)
Parameter
Conditions
Current Consumption
Startup time
Min.
Typ.
Max.
f = 2MHz, CL = 20pF, AGC off
27
65
90
f = 2MHz, CL = 20pF, AGC on
14
52
79
f = 4MHz, CL = 20pF, AGC off
61
117
161
f = 4MHz, CL = 20pF, AGC on
23
74
110
f = 8MHz, CL = 20pF, AGC off
131
226
319
f = 8MHz, CL = 20pF, AGC on
56
128
193
f = 16MHz, CL = 20pF, AGC off
305
502
742
f = 16MHz, CL = 20pF, AGC on
116
307
627
f = 32MHz, CL = 18pF, AGC off
1031
1622
2344
f = 32MHz, CL = 18pF, AGC on
278
615
1422
f = 2MHz, CL = 20pF,
XOSC.GAIN = 0, ESR = 600Ω
-
14K
48K
f = 4MHz, CL = 20pF,
XOSC.GAIN = 1, ESR = 100Ω
-
6800
19.5K
f = 8MHz, CL = 20pF,
XOSC.GAIN = 2, ESR = 35Ω
-
5550
13K
f = 16MHz, CL = 20pF,
XOSC.GAIN = 3, ESR = 25Ω
-
6750
14.5K
f = 32MHz, CL = 18pF,
XOSC.GAIN = 4, ESR = 40Ω
-
5.3K
9.6K
Units
µA
cycles
Oscillator Connection
Xin
C LEXT
Crystal
LM
C SHUNT
RM
C STRAY
CM
Xout
C LEXT
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1185
C.9.2
External 32kHz Crystal Oscillator (XOSC32K) Characteristics
Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32 pin.
Table C-20.
Symbol
Digital Clock Characteristics
Parameter
Conditions
Min.
Typ.
Max.
Units
fCPXIN32
XIN32 clock frequency
I
-
32.768
-
kHz
I
XIN32 clock duty cycle
I
-
50
-
%
Crystal Oscillator Characteristics
Figure C-4 and the equation in “Crystal Oscillator (XOSC) Characteristics” on page 1184 also applies to the 32kHz
oscillator connection. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range
given in the table. The exact value of CL can be found in the crystal datasheet.
Table C-21.
Symbol
32kHz Crystal Oscillator Characteristics
Parameter
Conditions
Min.
Typ.
Max.
Units
fOUT
Crystal oscillator frequency
I
-
32768
-
Hz
tSTARTUP
Startup time
ESRXTAL = 39.9kΩ, CL = 12.5pF
-
28K
31K
cycles
CL
Crystal load capacitance
I
-
-
12.5
CSHUNT
Crystal shunt capacitance
I
-
0.1
-
CXIN32
Parasitic capacitor load
-
3.1
-
CXOUT32
Parasitic capacitor load
-
3.3
-
IXOSC32K
Current consumption
-
1.22
2.44
µA
ESR
Crystal equivalent series
resistance f=32.768kHz
Safety Factor = 3
-
-
141
kΩ
TQFP64/48/32 packages
CL=12.5pF
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pF
1186
C.9.3
Digital Frequency Locked Loop (DFLL48M) Characteristics
Table C-22.
Symbol
DFLL48M Characteristics - Open Loop Mode(1) (Device Variant A)
Parameter
Conditions
DFLLVAL.COARSE =
DFLL48M COARSE CAL
Min.
Typ.
Max.
Units
47
48
49
MHz
-
403
457
A
7
8
9
s
Min.
Typ.
Max.
Units
I
fOUT
Output frequency
DFLLVAL.FINE = 512
DFLLVAL.COARSE =
DFLL48M COARSE CAL
I
IDFLL
Power consumption on VDDIN
DFLLVAL.FINE = 512
tSTARTUP
DFLLVAL.COARSE =
DFLL48M COARSE CAL
Startup time
DFLLVAL.FINE = 512
fOUT within 90% of final value
Note:
1.
Table C-23.
Symbol
DFLL48M in Open loop after calibration at room temperature.
DFLL48M Characteristics - Closed Loop Mode (Device Variant A)
Parameter
Conditions
fOUT
Average Output frequency
fREF = 32.768kHz
47.76
48
48.24
MHz
fREF
Reference frequency
I
0.732
32.768
33
kHz
Jitter
Period Jitter
fREF = 32.768kHz
-
-
1.04
ns
IDFLL
Power consumption on VDDIN
fREF = 32.768kHz
-
425
482
A
100
200
500
s
Conditions
Min.
Typ.
Max.
Units
Calibrated against a 32.768kHz
reference at 25 C, over [-40, +125]C,
over [1.8, 3.6]V
28.508
32.768
35.389
Calibrated against a 32.768kHz
reference at 25 C, at VDD=3.3V
32.276
32.768
33.260
Calibrated against a 32.768kHz
reference at 25 C, over [1.8, 3.6]V
31.457
32.768
34.079
fREF = 32.768kHz
DFLLVAL.COARSE =
DFLL48M COARSE CAL
tLOCK
Lock time
DFLLVAL.FINE = 512
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.CCDIS = 1
DFLLMUL.FSTEP = 10
C.9.4
32.768kHz Internal oscillator (OSC32K) Characteristics
Table C-24.
Symbol
fOUT
32kHz RC Oscillator Characteristics (Device Variant A)
Parameter
Output frequency
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kHz
1187
Symbol
C.9.5
Parameter
Conditions
Min.
Typ.
Max.
Units
IOSC32K
Current consumption
I
-
0.79
1.80
A
tSTARTUP
Startup time
I
-
1
2
cycle
Duty
Duty Cycle
I
-
50
-
%
Min.
Typ.
Max.
Units
Calibrated against a 32.768kHz
reference at 25 C, over [-40,
+125]C, over [1.8, 3.6]V
25.559
32.768
40.305
Calibrated against a 32.768kHz
reference at 25 C, at VDD=3.3V
31.293
32.768
34.570
Calibrated against a 32.768kHz
reference at 25 C, over [1.8, 3.6]V
31.293
32.768
34.570
-
-
180
nA
Ultra Low Power Internal 32kHz RC Oscillator (OSCULP32K) Characteristics
Table C-25.
Symbol
fOUT
Ultra Low Power Internal 32kHz RC Oscillator Characteristics
Parameter
Conditions
Output frequency
IOSCULP32K
(1)(2)
tSTARTUP
Startup time
I
-
10
-
cycles
Duty
Duty Cycle
I
-
50
-
%
Notes: 1.
2.
C.9.6
kHz
These values are based on simulation. These values are not covered by test limits in production or
characterization.
This oscillator is always on.
8MHz RC Oscillator (OSC8M) Characteristics
Figure C-5.
Symbol
Internal 8MHz RC Oscillator Characteristics (Device Variant A)
Parameter
Conditions
Min.
Typ.
Max.
Calibrated against a 8MHz reference
at 25 C, over [-40, +125]C, over [1.8,
3.6]V
7.54
8
8.19
Calibrated against a 8MHz reference
at 25 C, at VDD=3.3V
7.94
8
8.06
Calibrated against a 8MHz reference
at 25 C, over [1.8, 3.6]V
7.92
8
8.08
Units
I
fOUT
Output frequency
MHz
IOSC8M
Current consumption
IDLE2 on OSC32K versus IDLE2 on
calibrated OSC8M enabled at 8MHz
(FRANGE=1, PRESC=0)
-
64
100
A
tSTARTUP
Startup time
I
-
2.1
3
s
Duty
Duty cycle
I
-
50
-
%
I DLE
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1188
C.9.7
Fractional Digital Phase Locked Loop (FDPLL96M) Characteristics
Table C-26.
Symbol
FDPLL96M Characteristics(1) (Device Variant A)
Parameter
Conditions
Min.
Typ.
Max.
Units
fIN
Input frequency
32
-
2000
KHz
fOUT
Output frequency
48
-
96
MHz
IFDPLL96M
Current consumption
fIN= 32 kHz, fOUT= 48 MHz
500
700
fIN= 32 kHz, fOUT= 96 MHz
900
1200
1.5
2.0
fIN= 32 kHz, fOUT= 96 MHz
3.0
10.0
fIN= 2 MHz, fOUT= 48 MHz
1.3
2.0
fIN= 2 MHz, fOUT= 96 MHz
3.0
7.0
After startup, time to get lock
signal.
1.3
2
ms
25
50
s
50
60
%
fIN= 32 kHz, fOUT= 48 MHz
Jp
Period jitter
tLOCK
Lock Time
-
Note:
C.9.8
Duty cycle
1.
%
fIN= 32 kHz, fOUT= 96 MHz
fIN= 2 MHz, fOUT= 96 MHz
Duty
A
40
All values have been characterized with FILTSEL[1/0] as default value.
USB Characteristics
The USB shares the same characteristics as in the -40 C to 85 C.
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1189
C.10 Timing Characteristics
C.10.1 SERCOM in SPI Mode Timing
Data are not available in this current datasheet revision
C.10.2 SERCOM in I2C Mode Timing
Data are not available in this current datasheet revision
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1190
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1191
Table of Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1. Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1
2.2
SAM R21E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SAM R21G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1
3.2
MCU Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SAM R21 Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4. Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.1
4.2
SAM R21G - QFN48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SAM R21E - QFN32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5. I/O Multiplexing and Considerations . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1
5.2
5.3
5.4
5.5
Multiplexed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Multiplexed Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Other Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog and RF Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital I/O Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
13
14
17
18
6. Power Supply and Start-Up Considerations . . . . . . . . . . . . . . . . . . . 20
6.1
6.2
6.3
6.4
Power Domain Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Reset and Brown-Out Detector. . . . . . . . . . . . . . . . . . . . . . . . . . .
20
20
21
22
7. Product Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8. Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.1
8.2
8.3
Embedded Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Physical Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
NVM Calibration and Auxiliary Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9. Processor And Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9.1
9.2
9.3
9.4
9.5
9.6
Cortex M0+ Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Nested Vector Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Micro Trace Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High-Speed Bus System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AHB-APB Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAC – Peripheral Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
29
31
32
35
36
10. Peripherals Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . 43
11. DSU – Device Service Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
11.1
11.2
11.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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1192
11.4
11.5
11.6
11.7
11.8
11.9
11.10
11.11
11.12
11.13
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Debug Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chip-Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Intellectual Property Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
46
47
48
48
49
50
51
56
59
12. Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous and Asynchronous Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enabling a Peripheral. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On-demand, Clock Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Consumption vs Speed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocks after Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82
83
83
87
88
88
88
13. GCLK – Generic Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
90
90
91
91
92
97
98
14. PM – Power Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
112
112
113
113
113
115
122
123
15. SYSCTRL – System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
15.1
15.2
15.3
15.4
15.5
15.6
15.7
15.8
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
143
143
144
145
145
146
160
162
16. WDT – Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
16.1
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
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16.2
16.3
16.4
16.5
16.6
16.7
16.8
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
206
206
207
207
208
213
214
17. RTC – Real-Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
17.1
17.2
17.3
17.4
17.5
17.6
17.7
17.8
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
224
224
224
225
225
227
232
235
18. DMAC – Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . 267
18.1
18.2
18.3
18.4
18.5
18.6
18.7
18.8
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
267
267
268
268
268
270
288
291
19. EIC – External Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . 331
19.1
19.2
19.3
19.4
19.5
19.6
19.7
19.8
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
331
331
331
332
332
333
337
338
20. NVMCTRL – Non-Volatile Memory Controller . . . . . . . . . . . . . . . . 350
20.1
20.2
20.3
20.4
20.5
20.6
20.7
20.8
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
350
350
350
350
351
351
357
358
21. PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
21.1
21.2
21.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
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21.4
21.5
21.6
21.7
21.8
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
374
374
376
381
383
22. EVSYS – Event System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
22.1
22.2
22.3
22.4
22.5
22.6
22.7
22.8
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
400
400
401
401
401
402
407
408
23. SERCOM – Serial Communication Interface . . . . . . . . . . . . . . . . . 426
23.1
23.2
23.3
23.4
23.5
23.6
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
426
426
426
426
427
428
24. SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiver and
Transmitter 434
24.1
24.2
24.3
24.4
24.5
24.6
24.7
24.8
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
434
434
435
435
435
437
448
450
25. SERCOM SPI – SERCOM Serial Peripheral Interface . . . . . . . . . . 472
25.1
25.2
25.3
25.4
25.5
25.6
25.7
25.8
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
472
472
472
472
473
474
483
485
26. SERCOM I2C – SERCOM Inter-Integrated Circuit . . . . . . . . . . . . . 505
26.1
26.2
26.3
26.4
26.5
26.6
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
505
505
505
506
506
507
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26.7
26.8
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525
Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
27. TC – Timer/Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
27.1
27.2
27.3
27.4
27.5
27.6
27.7
27.8
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
568
568
569
570
570
571
582
585
28. TCC – Timer/Counter for Control Applications . . . . . . . . . . . . . . . . 609
28.1
28.2
28.3
28.4
28.5
28.6
28.7
28.8
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
609
609
610
610
611
612
642
645
29. USB – Universal Serial Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
29.1
29.2
29.3
29.4
29.5
29.6
29.7
29.8
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
702
702
703
703
703
706
722
730
30. ADC – Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . 802
30.1
30.2
30.3
30.4
30.5
30.6
30.7
30.8
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
802
802
802
803
804
805
815
817
31. AC – Analog Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842
31.1
31.2
31.3
31.4
31.5
31.6
31.7
31.8
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Additional Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
842
842
843
843
843
845
851
854
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31.9
Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855
32. PTC - Peripheral Touch Controller . . . . . . . . . . . . . . . . . . . . . . . . . 871
32.1
32.2
32.3
32.4
32.5
32.6
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
871
871
872
873
873
875
33. RFCTRL – AT86RF233 Front-End Control Signal Interface . . . . . . 876
33.1
33.2
33.3
33.4
33.5
33.6
33.7
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Dependencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
876
876
876
876
876
877
878
34. Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
34.1
34.2
Basic Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879
Extended Feature Set Application Schematic . . . . . . . . . . . . . . . . . . . . . . . 881
35. AT86RF233 Microcontroller Interface . . . . . . . . . . . . . . . . . . . . . . . 883
35.1
35.2
35.3
35.4
35.5
35.6
35.7
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Timing Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Radio Transceiver Status Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Radio Transceiver Identification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sleep/Wake-up and Transmit Signal (SLP_TR). . . . . . . . . . . . . . . . . . . . . .
Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
883
884
885
890
891
894
896
36. AT86RF233 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902
36.1
36.2
Basic Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902
Extended Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915
37. AT86RF233 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . 947
37.1
37.2
37.3
37.4
37.5
37.6
37.7
Introduction – IEEE 802.15.4-2006 Frame Format . . . . . . . . . . . . . . . . . . .
Frame Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frame Check Sequence (FCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Received Signal Strength Indicator (RSSI) . . . . . . . . . . . . . . . . . . . . . . . . .
Energy Detection (ED) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clear Channel Assessment (CCA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Link Quality Indication (LQI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
947
952
961
964
965
968
972
38. AT86RF233 Module Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 975
38.1
38.2
38.3
38.4
38.5
38.6
Receiver (RX). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmitter (TX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frame Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Regulators (AVREG, DVREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Battery Monitor (BATMON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal Oscillator (XOSCRF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
975
979
981
983
987
989
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38.7
38.8
Frequency Synthesizer (PLL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993
Automatic Filter Tuning (FTN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
39. AT86RF233 Radio Transceiver Usage . . . . . . . . . . . . . . . . . . . . . 1003
39.1
39.2
Frame Receive Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003
Frame Transmit Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003
40. AT86RF233 Extended Feature Set . . . . . . . . . . . . . . . . . . . . . . . . 1005
40.1
40.2
40.3
40.4
40.5
40.6
40.7
40.8
40.9
40.10
40.11
40.12
Security Module (AES). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Random Number Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High Data Rate Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Antenna Diversity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX/TX Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RX and TX Frame Time Stamping (TX_ARET) . . . . . . . . . . . . . . . . . . . . .
Frame Buffer Empty Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Frame Buffer Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alternate Start-Of-Frame Delimiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reduced Power Consumption Mode (RPC) . . . . . . . . . . . . . . . . . . . . . . .
Time-Of-Flight Module (TOM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase Difference Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1005
1013
1013
1020
1025
1027
1030
1032
1033
1034
1039
1050
41. AT86RF233 Register Reference . . . . . . . . . . . . . . . . . . . . . . . . . . 1052
42. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1055
42.1
42.2
42.3
42.4
42.5
42.6
42.7
42.8
42.9
42.10
42.11
42.12
42.13
42.14
42.15
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
General Operating Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Clock Frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NVM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillators Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PTC Typical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AT86RF233 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1055
1055
1056
1057
1057
1060
1063
1067
1069
1082
1083
1090
1094
1095
1101
43. Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1107
43.1
43.2
Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1107
Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1108
44. Soldering Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111
45. Schematic Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1112
45.1
45.2
45.3
45.4
45.5
45.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Analog Reference Connections . . . . . . . . . . . . . . . . . . . . . . . . . .
External Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unused or Unconnected Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocks and Crystal Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1112
1112
1113
1115
1115
1116
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45.7
45.8
Programming and Debug Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119
USB Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1123
46. About This Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125
46.1
46.2
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1125
Acronyms and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1126
47. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1131
47.1
47.2
47.3
47.4
Revision A
Revision B
Revision C
Revision D
.................................................
.................................................
.................................................
.................................................
1131
1139
1148
1155
48. Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1163
48.1
48.2
48.3
48.4
48.5
48.6
48.7
Rev. G – 05/2016 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rev. F – 11/2015 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rev. E – 02/2015 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rev. D – 02/2015 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rev. C – 01/2015 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rev. B – 09/2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rev. A – 07/2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1163
1163
1164
1164
1165
1165
1166
Appendix A. Continuous Transmission Test Mode . . . . . . . . . . . . . . . 1167
A.1
A.2
A.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1167
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1169
Appendix B. References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1170
Appendix C. Electrical Characteristics at 125°C . . . . . . . . . . . . . . . . . 1171
C.1
C.2
C.3
C.4
C.5
C.6
C.7
C.8
C.9
C.10
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171
General Operating Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1171
Supply Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1172
Maximum Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1173
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1174
Analog Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1177
NVM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1183
Oscillators Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1184
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1190
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1192
Atmel | SMART SAM R21 [DATASHEET]
Atmel-42223G–SAM-R21_Datasheet–05/2016
1199
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