BM20/BM23
Bluetooth® 4.1 Stereo Audio Module
Features:
Complete, Fully Certified, Embedded
2.4 GHz Bluetooth® Version 4.1
Module
Bluetooth Classic (BDR/EDR)
Bluetooth SIG Certified
Onboard embedded Bluetooth Stack
Transparent UART mode for seamless serial
data over UART interface
Easy to configure with Windows GUI or direct
by MCU
Compact surface mount module: 29 x 15 x
3
2.5 mm
Castellated surface mount pads for easy
and reliable host PCB mounting
Environmentally friendly, RoHS compliant
Perfect for Portable Battery Operated
Devices
Internal Battery Regulator Circuitry
Worldwide regulatory certifications
Audio-In / Out
2
BM23 support digital audio I S format.
BM20 support analog audio output.
Operational:
Operating voltage: 3.0V to 4.2V
Temperature range: ‐20C to 70°C
Simple, UART interface
Integrated crystal, internal voltage
regulator, and matching circuitry
Multiple I/O pins for control and status
RF/Analog:
Frequency: 2.402 to 2.480 GHz
Receive Sensitivity: ‐91 dBm (π/4
DQPSK)
Power Output: class 2 / +4dBm max.
Connection Distance: >10m
(free space and no interference)
Audio processor
Build-in four languages (Chinese/ English/ Spanish/
French) voice prompts and 20 events for each one
(This function can be set up in “IS20XXS_UI” tool.)
Support SCMS-T
Audio Codec
20 bit DAC and 16 bit ADC codec
98dB SNR DAC playback
Peripherals
Built-in Lithium-ion battery charger (up to 350mA)
Integrate 3V, 1.8V configurable switching regulator and
LDO
Built-in ADC for battery monitor and voltage sense.
A line-in port for external audio input
Two LED drivers
Flexible HCI interface
High speed HCI-UART (Universal Asynchronous
Receiver Transmitter) interface (up to 921600bps)
MAC/Baseband/Higher Layer:
Secure AES128 encryption
Bluetooth profiles
- HFP v1.6
- HSP v1.1
- A2DP v1.2
- AVRCP v1.5
- SPP v1.0
- PBAP v1.0
Antenna:
Printed Antenna
Compliance:
Bluetooth SIG QDID
Module certified for the United States (FCC) and
Canada (IC), Korea (LCC), Taiwan (NCC), Japan
(MIC) and China(SRRC)
Support 64 kb/s A-Law or -Law PCM format, or
CVSD (Continuous Variable Slope Delta
Modulation) for SCO channel operation.
Noise suppression
Echo suppression
SBC and optional AAC decoding
Packet loss concealment
2015 Microchip Technology Inc.
Preliminary Edition
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Figure 1:
General Description:
Stereo module is a fully-certified
Bluetooth® Version 4.1 (BDR/EDR) module
for designers who want to add Bluetooth®
wireless audio and voice applications to their
products.
This Bluetooth SIG certified module
provides a complete wireless solution with
Bluetooth stack, integrated antenna, and
worldwide radio certifications in a compact
3
surface mount package, 29x15x2.5 mm .
2015 Microchip Technology Inc.
Preliminary Edition
This stereo module built-in Li-Ion charger
and BM23 contain a digital audio interface. It
supports HSP, HFP, SPP, A2DP, and
AVRCP profiles. Both AAC and SBC codecs
are supported for A2DP. Note that the
customer must connect their own external
analog CODEC/DSP/amplifier and MCU for
audio output.
Applications:
Bluetooth sound bar
Bluetooth stereo speaker phone
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Stereo Module
Table of Contents
1.
DEVICE OVERVIEW .........................................................................................................6
2.
APPLICATION INFORMATION .....................................................................................12
3.
ELECTRICAL CHARACTERISTICS...............................................................................20
4.
PRINTED ANTENNA INFORMATION ..........................................................................25
4.1.
MODULE RADIATION PATTERN..............................................................................25
4.2. MODULE PLACEMENT RULE ..................................................................................26
5.
REFERENCE CIRCUIT ....................................................................................................27
5.1. BM20 REFERENCE CIRCUIT ................................................................................27
5.2. BM23 REFERENCE CIRCUIT ....................................................................................28
6.
MODULE OUTLINE AND REFLOW PROFILE ............................................................29
7.
PACKAGING AND STORAGE INFORMATION ..........................................................34
APPENDIX A: CERTIFICATION NOTICES ..........................................................................36
A.1 REGULATORY APPROVAL .......................................................................................36
A.2 United States .................................................................................................................36
A.2.1 LABELING AND USER INFORMATION REQUIREMENTS .............................37
A.2.2 RF EXPOSURE .............................................................................................................38
A.2.3 HELPFUL WEB SITES ...................................................................................................38
A.3 Canada ...........................................................................................................................39
A.3.1 LABELING AND USER INFORMATION REQUIREMENTS .............................................39
A.3.2 RF EXPOSURE.............................................................................................................40
A.3.3 WEB SITES .................................................................................................................40
A.4 Europe ............................................................................................................................40
A.4.1 ABELING AND USER INFORMATION REQUIREMENTS ...............................41
A.4.2 ANTENNA REQUIREMENTS ...............................................................................41
A.4.3 HELPFUL WEB SITES ...........................................................................................42
A.5 Japan ..............................................................................................................................43
A.5.1 LABELING AND USER INFORMATION REQUIREMENTS .............................43
A.5.2 HELPFUL WEB SITES ...........................................................................................44
A.6 Korea ..............................................................................................................................44
A.6.1 LABELING AND USER INFORMATION REQUIREMENTS .............................44
A.6.2 HELPFUL WEB SITES ...........................................................................................44
A.7 Taiwan ............................................................................................................................45
A.7.1 LABELING AND USER INFORMATION REQUIREMENTS .............................45
A.7.2 HELPFUL WEB SITES ...........................................................................................45
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A.8 China .............................................................................................................................46
A.8.1 LABELING AND USER INFORMATION REQUIREMENTS .............................46
A.9 Other Regulatory Jurisdictions ..................................................................................46
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TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your
Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications
will be refined and enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications
Department via E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
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http://www.microchip.com
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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Abbreviations List:
HFP: Hands-free Profile
AVRCP: Audio Video Remote Control Profile
A2DP: Advanced Audio Distribution Profile
PBAP: Phone Book Access Profile
HSP: Headset Profile
SPP: Serial Port Profile
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Stereo Module
1. DEVICE OVERVIEW
The stereo module series include BM20 and BM23. The chip integrates Bluetooth 4.1 radio
transceiver, PMU and DSP. Figure 1-1and 1-2 shows the application block diagram.
FIGURE 1‐1: BM20 Typical Application
The following depicts an example of BM20 module operate as an independent system or connected
to an MCU.
Audio Output
IS2020S
16M Hz
Crystal
Microphone
I2C
Aux_In
EEPROM
IC
UART
BM20
MCU
Option
FIGURE 1‐2: BM23 Typical Application
The following depicts an example of BM23 module connected to an MCU, external DSP/CODEC.
IS2023S
16M Hz
Crystal
I2S
DSP
UART
MCU
Microphone
I2C
Aux_In
EEPROM
IC
BM23
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1.1. INTERFACE DESCRIPTION
BM20 pin diagram is shown in Figure 1-3. The pin descriptions are shown in Table 1-1
FIGURE 1-3: BM20 PIN DIAGRAM
TABLE 1‐1: BM20 PIN DESCRIPTION
Pin No.
Pin type
Name
1
I/O
P0_0
2
I
EAN
3
I
P3_0
4
I
P2_0
5
I/O
P1_5
6
I/O
P0_4
7
8
O
O
SPKR
AOHPM
2015 Microchip Technology Inc.
Description
IO pin, default pull-high input (Note 1)
1. Slide Switch Detector, active low.
2. UART TX_IND, active low.
Embedded ROM/External Flash enable
H: Embedded; L: External Flash
IO pin, default pull-high input (Note 1)
Line-in Detector (default), active low.
IO pin, default pull-high input
System Configuration,
H: Application L: Baseband(IBDK Mode)
IO pin, default pull-high input (Note 1)
1. NFC detection pin, active low.
2. Out_Ind_0
3. Slide Switch Detector, active low.
4. Buzzer Signal Output
IO pin, default pull-high input. (Note 1)
1. NFC detection pin, active low.
2. Out_Ind_0
R-channel analog headphone output
Headphone common mode output/sense input.
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Pin No.
Pin type
Name
9
O
SPKL
L-channel analog headphone output
10
P
VDDA
Positive power supply/reference voltage for CODEC, no need to add power
to this pin.
11
I
MIC1_P
Mic 1 mono differential analog positive input
12
I
MIC1_N
Mic 1 mono differential analog negative input
13
P
MIC_BIAS
14
I
AIR
R-channel single-ended analog inputs
15
I
AIL
L-channel single-ended analog inputs
16
I
RST
System Reset Pin, Low: reset
17
P
VCC_RF
18
I/O
P0_1
19
P
VDD_IO
Power output , no need to add power to this pin
20
P
ADAP_IN
5V Power adaptor input
21
P
BAT_IN
22
-
NC
23
P
GND
24
P
SYS_PWR
System Power Output
BAT mode: 3.0~4.2V
Adapter mode: 4.0V
25
P
BK_OUT
1.8V buck output, no need to add power to this pin
26
I
MFB
1. Power key when in off mode
2. UART_RX_IND: MCU use to wakeup BT (Note 1)
27
I
LED1
LED Driver 1
28
I
LED2
LED Driver 2
29
I
P2_4
30
I
P0_2
31
I/O
P0_3
32
O
HCI_TXD
HCI-UART TX data
33
I
HCI_RXD
HCI-UART RX data
34
I
P0_5
35
I
P2_7
2015 Microchip Technology Inc.
Description
Electric microphone biasing voltage
1.28V RF LDO output, no need to add power to this pin.
IO pin, default pull-high input (Note 1)
1. FWD key when class 2 RF (default), active low.
2. Class1 TX Control signal of external RF T/R switch, active high.
3.0V~4.2V Li-Ion battery input
No Connection
Ground Pin
IO pin, default pull-high input
System Configuration,
L: Boot Mode with P2_0 low combination
IO pin, default pull-high input (Note 1)
Play/Pause key (default), active low.
IO pin, default pull-high input (Note 1)
1. REV key (default), active low.
2. Buzzer Signal Output
3. Out_Ind_1
4. Class1 RX Control signal of external RF T/R switch, active high.
IO pin, default pull-high input (Note 1)
Volume down (default), active low.
IO pin, default pull-high input (Note 1)
Volume up key (default), active low.
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Pin No.
Pin type
Name
Description
36
I
P2_4
IO pin, default pull-high input
System Configuration,
L: Boot Mode with P2_0 low combination
37
P
GND
Ground Pin
38
-
NC
No Connection
39
-
NC
No Connection
40
-
NC
No Connection
* I: signal input pin
* O: signal output pin
* I/O: signal input/output pin
* P: power pin
Note 1: These button or functions can be setup by “IS20XXS_UI” tool.
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BM23 pin diagram is shown in Figure 1-4. The pin descriptions are shown in Table 1-2
FIGURE 1-4: BM23 PIN DIAGRAM
TABLE 1‐2: BM23 PIN DESCRIPTION
Pin No.
Pin Type
Name
1
I/O
P0_0
2
3
4
5
6
7
I/O
I/O
I/O
I
O
I/O
RFS0
TFS0
SLK0
DR0
DT0
P0_4
8
I
EAN
9
I
MIC1_P
10
11
12
13
14
I
P
P
I
I
MIC1_N
MIC_BIAS
VDDA
AIR
AIL
2015 Microchip Technology Inc.
Description
IO pin, default pull-high input (Note 1)
UART TX_IND
2
I S interface: DAC Left/Right Clock
2
I S interface: ADC Left/Right Clock
2
I S interface: Bit Clock
2
I S interface: DAC Digital Left/Right Data
2
I S interface: ADC Digital Left/Right Data
IO pin, default pull-high input
Embedded ROM/External Flash enable
High: ROM mode;
Low: External Flash mode
Mic 1 mono differential analog positive input
Mic 1 mono differential analog negative input
Power output, microphone biasing voltage
Power output, reserve for external cap to fine tune audio frequency
response,
no need
to R-channel
add power to this pin
Stereo analog
line in,
Stereo analog line in, L-channel
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Pin No.
I/O
Name
Description
15
P
GND
16
I
RST_N
17
--
NC
--
18
--
NC
--
19
P
VDDIO
20
I/O
P1_5
IO pin, default pull-high input
21
I/O
P0_1
IO pin, default pull-high input
22
P
ADAP_IN
23
P
BAT_IN
24
--
NC
25
P
SYS_PWR
System Power Output
BAT mode: 3.3~4.2V
Adapter mode: 4.0V
26
P
BK_OUT
Power output, 1v8 pin, no need to add power to this pin
27
P
MFB
1.
2.
28
P
LED1
LED Driver 1, 4mA max
29
P
LED2
LED Driver 2, 4mA max
30
I
P2_4
IO pin, default pull-high input
System Configuration,
L: Boot Mode with P2_0 low combination
31
I/O
P0_2
IO pin, default pull-high input
32
I/O
P0_3
IO pin, default pull-high input
33
O
HCI_TXD
HCI-UART TX data
34
I
HCI_RXD
HCI-UART RX data
35
I/O
P0_5
IO pin, default pull-high input
36
I/O
P2_7
IO pin, default pull-high input
37
I/O
P2_0
IO pin, default pull-high input
38
I/O
P3_0
IO pin, default pull-high input
Ground
System Reset Pin, active when rising edge.
Power output, VDDIO pin, no need to add power to this pin
5V power adaptor input
3.3~4.2V Li-ion battery input
--
Power key when in off mode
UART_RX_IND: MCU use to wakeup BT
39
I
P2_0
IO pin, default pull-high input
System Configuration,
H: Application L: Baseband(IBDK Mode)
40
P
GND
Ground.
41
--
NC
--
42
--
NC
--
43
--
NC
--
* I: signal input pin
* O: signal output pin
* I/O: signal input/output pin
* P: power pin
Note 1: These button or functions can be setup by “IS20XXS_UI” tool.
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Stereo Module
2. APPLICATION INFORMATION
2.1. OPERATION WITH EXTERNAL MCU
Stereo module support UART command set to make an external MCU to control module.
Here is the connection interface between BMXX and MCU.
FIGURE 2-1: INTERFACE BETWEEN MCU AND BMXX MODULE
MCU_
WAKEUP
UART_RX
MCU
UART_TX
P0_0
UART interface
UART interface
BT_
WAKEUP
HCI_TXD
BMXX
HCI_RXD
MFB
MCU can control module by UART interface and wakeup module by PWR pin. Stereo module
provide wakeup MCU function by connect to P0_0 pin of module.
“UART Command Set” document provide all function which module support and UI tool will help
you to set up your system support UART command.
For more detail description, please reference “UART_CommandSet_v154” document and
“IS20XXS_UI” tool.
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Stereo Module
Here are some suggestions of UART control signal timing sequence:
FIGURE 2-2: POWER ON/OFF SEQUENCE
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FIGURE 2-3: TIMING SEQUENCE OF RX INDICATION AFTER POWER ON
FIGURE 2-4: TIMING SEQUENCE OF POWER OFF
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FIGURE 2-5: TIMING SEQUENCE OF POWER ON (NACK)
FIGURE 2-6: RESET TIMING SEQUENCE IF MODULE HANGS UP
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FIGURE 2-7: TIMING SEQUENCE OF POWER DROP PROTECTION
Power
BAT_IN +4V
2.9V ~
RST_N from Reset IC
If BT’s BAT use adaptor translates voltage by LDO, we recommend use “Reset IC” to avoid power
off suddenly. Rest IC spec output pin must be “Open Drain”、delay time ≦ 10ms
Recommend part: TCM809SVNB713 or G691L263T73
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2.2. I2S Signal Application for BM23
2
BM23 support I S digital audio signal interface to connect your external CODEC/DSP. It provide 8k
2
Hz, 44.1k Hz and 48k Hz sampling rate; it also support 16 bits and 24bits data format. The I S setting
can be set up by UI and DSP tools.
.
The external CODEC/DSP needs to be connected to SLK0, RFS0, TFS0, DR0, and DT0 (pins 4, 2, 3,
2
5, and 6 respectively). The I S signal connection between BM23 and external DSP as below:
FIGURE 2-9: MASTER MODE REFERENCE CONNECTION
BCLK
SCLK0
RFS0
DACLRC
EXTERNAL
DSP/CODEC
TFS0
ADCDAT
DR0
DACDAT
DT0
BM23
FIGURE 2-10: SLAVE MODE REFERENCE CONNECTION
BCLK
SCLK0
RFS0
DACLRC
(*1)
EXTERNAL
DSP/CODEC
ADCDAT
(*2)
DACDAT
TFS0
BM23
DR0
DT0
Note 1: For 002 version chip or module, system should connect line 1 in slave mode figure.
And, system not support ADC signal from external DSP/CODEC.
Note 2: For other version chip or module, system should connect line 2 in slave mode figure.
About “Mast” or “Slave” mode setting, you can use “DSP Configuration Tool” to set up system.
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Stereo Module
The clock and data timing as below:
2
FIGURE 2-11: TIMING FOR I S MODES (both master and slave)
1/fs
SCLKn
Left Channel
RFSn/TFSn
DRn/DTn
Bn-1 Bn-2
Right Channel
B1 B0
Bn-1 Bn-2
B1 B0
Word Length
FIGURE 2-12: TIMING FOR PCM MODES (both master and slave)
1/fs
SCLK0
RFS0/TFS0
Left Channel
DR0/DT0
Right Channel
B1 B0 Bn-1 Bn-2
Bn-1 Bn-2
B1 B0
Word Length
2.3. RESET (RST_N)
RST is module reset pin which is active LOW. To reset the module, the RST_N must hold LOW for at
least 63ns.
2.4. STATUS LED (LED1, LED2)
The status LED provide below status indication:
Standby
Inquiry
Link
Link Back
Low Battery
Page
Battery Charging
Each status indication LED flashing sequence and brightness is configurable by UI tool.
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Stereo Module
2.5. EXTERNAL CONFIGURATION
Stereo module can be configured and firmware programmed using an external configuration and
programming tool available from Microchip. Figure 2‐7 shows the configuration and firmware
programming interface on BM23. It is recommended to include a pin header on the main PCB for
development.
Configuration and firmware programming modes are entered accordingly to the system
configuration I/O pins as shown in Table 2-1. Pin P20, P24 and EAN pin have internal pull‐up.
FIGURE 2-13: EXTERNAL PROGRAMMING HEADER CONNECTIONS
(Here is the interface connect example of the BM23)
TABLE 2-1: SYSTEM CONFIGURATION SETTINGS
P20
P24
EAN
Operational Mode
High
High
High
APP mode (Normal operation)
High
Low
High
Test mode (Write EEPROM)
Low
Low
High
Write Flash (Firmware programming if flash build-in in chip)
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3. ELECTRICAL CHARACTERISTICS
Table 3-1: ABSOLUTE MAXIMUM SPECIFICATION
Symbol
BAT_IN
ADAP_IN
TSTORE
TOPERATION
Parameter
Input voltage for battery
Input voltage for adaptor
Storage temperature
Operation temperature
Min
0
0
-65
-20
Max
4.3
7.0
+150
+70
Unit
V
V
ºC
ºC
Table 3-2: RECOMMENDED OPERATING CONDITION
Symbol
BAT_IN
ADAP_IN
TOPERATION
Parameter
Input voltage for battery
Input voltage for adaptor
Operation temperature
Min
3
4.5
-20
Typical
3.7
5
+25
Max
4.2
5.5
+70
Unit
V
V
ºC
Note:
Absolute and Recommended operating condition tables reflect typical usage for device.
TABLE 3-3: I/O AND RESET LEVEL
Parameter
I/O Supply Voltage (VDD_IO)
I/O Voltage Levels
VIL input logic levels low
VIH input logic levels high
VOL output logic levels low
VOH output logic levels high
RESET
VTH,RES threshold voltage
Min.
2.7
Typ.
3.0
‐0.3
2.0
Max.
3.3
Units
V
0.8
3.6
0.4
V
V
V
V
2.4
1.6
V
Note:
(1) VDD_IO voltage is programmable by EEPROM parameters.
(2) These parameters are characterized but not tested in manufacturing.
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Table 3-4: BATTERY CHARGER
Parameter
Min
Typical
Max
Unit
ADAP_IN Input Voltage
4.5
5.0
5.5
V
3
4.5
mA
170
200
240
mA
160
180
240
mA
330
350
420
mA
180
220
270
mA
Supply current to charger only
Maximum Battery
Fast Charge Current
Note: ENX2=0
Maximum Battery
Fast Charge Current
Note: ENX2=1
Headroom > 0.7V
(ADAP_IN=5V)
Headroom = 0.3V
(ADAP_IN=4.5V)
Headroom > 0.7V
(ADAP_IN=5V)
Headroom = 0.3V
(ADAP_IN=4.5V)
Trickle Charge Voltage Threshold
3
V
Battery Charge Termination Current,
(% of Fast Charge Current)
10
%
Note:
(1) Headroom = VADAP_IN – VBAT
(2) ENX2 is not allowed to be enabled when VADAP_IN – VBAT > 2V
(3) These parameters are characterized but not tested in manufacturing.
Table 3-5: LED DRIVER
Parameter
Open-drain Voltage
Programmable Current Range
Intensity Control
Current Step
Power Down Open-drain Current
Shutdown Current
Min
Typical
0
Max
Unit
3.6
5.25
V
mA
step
mA
μA
μA
16
0.35
1
1
Note:
(1) Test condition: SAR_VDD=1.8V, temperature=25 ºC.
(2) These parameters are characterized but not tested in manufacturing.
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Table 3-6: AUDIO CODEC ANALOGUE TO DIGITAL CONVERTER
T= 25oC, Vdd=3.0V, 1KHz sine wave input, Bandwidth = 20Hz~20KHz
Parameter (Condition)
Min.
Resolution
Output Sample Rate
Signal to Noise Ratio Note: 1
(SNR @MIC or Line-in mode)
Digital Gain
Digital Gain Resolution
Typ.
8
Max.
Unit
16
48
Bits
KHz
88
-54
MIC Boost Gain
dB
2~6
4.85
dB
dB
20
dB
Analog Gain
60
Analog Gain Resolution
2.0
Input full-scale at maximum gain (differential)
4
Input full-scale at minimum gain (differential)
800
3dB bandwidth
Microphone mode (input impedance)
THD+N (microphone input) @30mVrms input
20
24
0.02
dB
dB
mV
rms
mV
rms
KHz
KΩ
%
Note:
(1) fin=1KHz, B/W=20~20KHz, A-weighted, THD+N < 1%, 150mVpp input
(2) These parameters are characterized but not tested in manufacturing.
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Preliminary Edition
Page 22
Stereo Module
Table 3-7: AUDIO CODEC DIGITAL TO ANALOGUE CONVERTER
T= 25oC, Vdd=3.0V, 1KHz sine wave input, Bandwidth = 20Hz~20KHz
Parameter (Condition)
Min.
Over-sampling rate
Resolution
Output Sample Rate
Signal to Noise Ratio Note: 1
(SNR @cap-less mode) for 48kHz
Signal to Noise Ratio Note: 1
(SNR @single-end mode) for 48kHz
Digital Gain
Typ.
Max.
Unit
20
48
fs
Bits
KHz
128
16
8
96
dB
98
dB
-54
Digital Gain Resolution
4.85
dB
2~6
Analog Gain
dB
-28
Analog Gain Resolution
3
dB
1
dB
Output Voltage Full-scale Swing (AVDD=2.8V) Note:3
742.5
mV rms
Maximum Output Power (16Ω load)
34.5
mW
Maximum Output Power (32Ω load)
17.2
mW
Allowed Load
Resistive
Capacitive
8
16
THD+N (16Ω load)
Signal to Noise Ratio (SNR @ 16Ωload)
O.C.
Ω
500
pF
0.05
%
96
dB
Note:
(1) fin=1KHz, B/W=20~20KHz, A-weighted, THD+N < 0.01%, 0dBFS signal, Load=100KΩ
(2) These parameters are characterized but not tested in manufacturing.
(3) Vdd, AVDD are generated by internal LDO
Table 3-8: TRANSMITTER SECTION FOR BDR AND EDR
Parameter
Maximum RF transmit
power(BM20)
Maximum RF transmit
power(BM23)
EDR/BDR
Relative transmit power
Min
Typ
Max
2
-4
-1.2
Bluetooth
specification
Unit
-6 to 4
dBm
-6 to 4
1
-4 to 1
dB
Note:
The RF Transmit power is calibrated during production using MP Tool software and MT8852 Bluetooth Test
equipment.
Test condition: VCC_RF= 1.28V, temperature=25 ºC.
2015 Microchip Technology Inc.
Preliminary Edition
Page 23
Stereo Module
Table 3-9: RECEIVER SECTION FOR BDR AND EDR
Modulation
Sensitivity at
0.1% BER
Sensitivity at
0.01% BER
Min
Typ
Max
Bluetooth
specification
Unit
GFSK
-90
≤-70
dBm
π/4 DQPSK
-91
≤-70
dBm
8DPSK
-82
≤-70
dBm
Note:
(1) Test condition: VCC_RF= 1.28V, temperature=25 ºC.
(2) These parameters are characterized but not tested in manufacturing.
Table 3-10: SYSTEM CURRENT CONSUMPTION OF ANALOG AUDIO OUTPUT
System Status
System Off Mode
Typ.
Max.
Unit
2
5
uA
Standby Mode
0.8
mA
Linked Mode
0.4
mA
SCO Link
7.8
mA
A2DP Link (V p-p=200mV; 1k tone signal)
10.7
mA
Note: Use BM20 EVB as test platform.
Test condition: BAT_IN= 3.8V, link with HTC EYE cell phone; distance between cell phone and EVB: 30cm.
2
Table 3-11: SYSTEM CURRENT CONSUMPTION OF DIGITAL AUDIO OUTPUT(I S)
System Status
System Off Mode
Typ.
Max.
Unit
2
5
uA
Standby Mode
0.4
mA
Linked Mode
0.4
mA
SCO Link
9.3
mA
11.7
mA
A2DP Link (1k tone signal)
Note: Use BM23 EVB as test platform
Test condition: BAT_IN= 3.8V, link with HTC M8 cell phone; distance between cell phone and EVB: 30cm;
2
I S signal link with YAMAHA YDA174 EVB
2015 Microchip Technology Inc.
Preliminary Edition
Page 24
Stereo Module
4. PRINTED ANTENNA INFORMATION
4.1. MODULE RADIATION PATTERN
The stereo module contains a PCB printed antenna. The PCB printed antenna radiation pattern is
shown in Figure 4-2.
FIGURE 4-1: ANTENNA KEEP OUT AREA EXAMPLES
FIGURE 4-2: ANTENNA 3D RADIATION PATTERN @2441 MHz
2015 Microchip Technology Inc.
Preliminary Edition
Page 25
Stereo Module
4.2. MODULE PLACEMENT RULE
On the main PCB, the areas under the antenna should not contain any top, inner layer, or
bottom copper as shown in Figure 4‐1. A low‐impedance ground plane will ensure the best radio
performance (best range, lowest noise). The ground plane can be extended beyond the minimum
recommended as need for the main PCB EMC noise reduction. For the best range performance,
keep all external metal away from the ceramic chip antenna at least 15 mm.
Here are some examples of good and poor placement on a carrier board with GND plane.
FIGURE 4-3: MODULE PLACEMENT EXAMPLES
Poor Case
Good Case
Acceptable Case
Worse Case
System GND Plane
FIGURE 4-4: GND PLANE ON MAIN APPLICATION BOARD
2015 Microchip Technology Inc.
Preliminary Edition
Page 26
VBUS
DD+
ID
GND
3
5
4
2
1
3
1
4
2
10
1
1
P3_0
C15
0.1u/16V
AOHPM
2
1
1
R7
0
R6
0
MIC_N1
MIC_P1
1
C13
2.2u/6.3V
SPKR
SPKL
JP5
JP 1x2
1
2
2
2
2
R75
1K
Li Battery
Connector
LINE_R
LINE_L
R4
2K
C14
1u/16V
C10
1u/16V
2
C93
NP-0603
R3
1K
P3
USBM3121-051-1-BN-R
1
5V
2
3
4
C18
5
10u/16V
TSH-3865D
P2
P1
PJ-2001-5K
3
5
4
2
1
AIR
AIL
C19
10u/16V
BAT_IN
R8
NP-0603
C17
1u/16V
C16
1u/16V
R5
NP-0603
MIC_BIAS
C72
2.2u/6.3V
C9
1u/16V
MFB 3
JP6
JP 1x1
1
1
C26
1u/10V
LED-HR
2
LED2
Q3
STS2301
2
LED-B
2
LED1
1
2
3
4
5
6
7
8
9
10
MIC_P1 11
MIC_N1 12
MIC_BIAS13
14
AIR
P0_0
EAN
P3_0
P2_0
AMP_EN
NFC
SPKR
AOHPM
SPKL
2
P0_0
EAN
P3_0
P2_0
P1_5
P0_4
SPKR
AOHPM
SPKL
VDDA
MIC1_P
MIC1_N
MIC_BIAS
AIR
ANT1
ANT2
ANT3
R12
100K
R10
100K
LED2
1
LED1
1
AIL
RST_N
P7
PJ-2001-5K
LINE
INPUT
MIC1
7
8
6
9
P0_1
1
38
39
40
37
36
35
34
33
32
31
30
29
28
27
26
25
24
1
STS2306
Q4
SLIDE_SW 1
2
SYS_PWR
P2_4
P2_7
P0_5
HCI_RXD
HCI_TXD
P0_3
P0_2
P2_4
LED2
LED1
MFB
3
1
2
VDD_IO
SYS_PWR
P0_0
2
R13
10K
SW8
SW-1BIT
Slide Switch Circuit
SYS_PWR
GND
P2_4
P2_7
P0_5
HCI_RXD
HCI_TXD
P0_3
P0_2
P2_4
LED2
LED1
MFB
BK_OUT
SYS_PWR
ON
2
1
AIL
RST
VCC_RF
P0_1
VDD_IO
ADAP_IN
BAT_IN
NC
GND
15
16
17
18
19
20
21
22
23
UART_RXD
UART_TXD
RESET_n
Audio AMP Enable
MFB/RX_IND
TX_IND
HCI_RXD
HCI_TXD
RST_N
AMP_EN
MFB
P0_0
UART CONTROL
(by MCU)
SW-TACT
1
2
C11
15p/50V
1
2
3
4
5
6
7
8
JP2
SW5
FWD
1
3
1
3
C12
15p/50V
P2_7
C8
15p/50V
P0_1
MMBT3904
Q1
DP1
DP-4
RST_N
Thursday , April 16, 2015
Date:
Sheet
1
of
Hsinchu City 30078, Taiwan
TEL. 886-3-5778385
MAIN CIRCUIT
Title
JP3
JP 1x8
1
2
3
4
5
6
7
8
1
Rev
1.1
P/N
XXXX
5F, No.5, Industry E. Rd. VII, Hsinchu Science Park,
P2_4
HCI_RXD
HCI_TXD
EAN
BM20 Reference Circuit
5V
BAT_IN
P2_0
RESERVE For
BLUETOOTH DEBUG
SW-TACT
SW7
Size
B
Board Name
JP 1x8
2
4
2
4
VOL+
3
SW6
4
R2
2K
1
Backup Plug-In Reset Circuit
SW-TACT
P0_5
C7
15p/50V
P0_3
C4
15p/50V
P0_2
5V
C3
1u/16V
4
3
SW2
SW-TACT
2
1
VOL-
1
2
R1
1K/1%
MFB
SYS_PWR
SW-TACT
3
4
SW4
REV
1
2
SW-TACT
3
4
SW3
PLAY/PAUSE
2
SW1
SW-TACT
4
1
RESET
BUTTON
2
3 1
3
1
2
MFB
1
2
C92
NP-0603
D
Stereo
Jack
G
Preliminary Edition
S
2015 Microchip Technology Inc.
VDD_IO
5V
BAT_IN
2
PCB1
BM20
Stereo Module
5. REFERENCE CIRCUIT
5.1. BM20 REFERENCE CIRCUIT
Page 27
LED2 2
RED
1
LED1 2
TP4
TP-4
RST_N
BLUE
MIC_BIAS
P2 DC-JACK
3
2
1
C20
0.1u/16V
C18
1u/16V
ADAP_IN
DC POWER SOURCE
C7
4.7u/10V
C5
10u/16V
MIC_BIAS
CODEC_VO
P0_0
RFS0
TFS0
SLK0
DR0
DT0
P0_4
EAN
MIC1_P
MIC1_N
MIC_BIAS
VDDA
AIR
AIL
GND
LED2 LED-HR
1
LED1 LED-B
1
LED
TP2
TP-4
BAT_IN
ADAP_IN
SYS_PWR
P2_4
LED2
LED1
MFB
HCI_RXD
HCI_TXD
P2_0
P3_0
C13
0.1u/16V
SYS_PWR
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
4
JP4
SJP 1x2
3
C16
0.1u/16V
C17
1u/16V
BAT_IN
BATTERY CONNECTOR
GND
P2_0
P3_0
P2_0
P2_7
P0_5
HCI_RXD
HCI_TXD
P0_3
P0_2
P2_4
LED2
LED1
MFB
BK_OUT
RST
NC
NC
VDD_IO
P1_5
P0_1
ADAP_IN
BAT_IN
AMB_DET
SYS_PWR
16
17
18
19
20
21
22
23
24
25
1
P0_0
2
RFS0
3
TFS0
4
SLK0
5
DR0
6
DT0
7
P0_4
8
EAN
MIC_P1 9
10
MIC_N1
11
12
13
AIR
14
AIL
15
1
PCB1
FP-BM23
2
1
1
D2
SPE0572
P1
PJ-3894D-S125
4
2
1
3
R8
1
2K
2
C1
2.2u/6.3V
R6
1K
1
2
1
2
C3
P3_0
C11
0.1u/16V
SPE0572
D3
SPE0572
D1
1
1
R11
1K
R10
1K
2
2
JP1
JP 1x8
1
2
3
4
5
6
7
8
R12
10K
R9
10K
C10
10u/16V
C12
470p/50V
C8
470p/50V
C9
10u/16V
0.047u/25V
MIC_N1
0.047u/25V
MIC_P1
MIC_BIAS
C2
2.2u/6.3V
2
2
2
2
2
33
33
33
33
33
C4
220p/50V
C6
R7 1K
RFS0 1
TFS0 1
SLK0 1
DR0 1
DT0 1
R2
R3
R1
R5
R4
STEREO AUX LINE INPUT
*P30 Low Active
Line In Detect
TP3
TP-4
TP1
TP-4
MIC INPUT
Receive frame synchronization
Transmit frame synchronization
Serial clock
Serial data receive
Serial data transmit
2
1
2
1
2
1
1
2
1
Preliminary Edition
2
2015 Microchip Technology Inc.
1
I2S INTERFACE
1
2
DP1 DP-4
HCI_RXD
HCI_TXD
RST_N
AMP_EN
MFB
P0_0
BAT_IN
P2_4 System Configuration
Sheet
2
Reference Circuit of BM23
Friday , March 13, 2015
Date:
of
Hsinchu City 30078, Taiwan
TEL. 886-3-5778385
Reference Circuit of BM23
Title
Size
B
JP2
JP 1x8
1
2
3
4
5
6
7
8
2
Rev
1.0
P/N
XXXX
5F, No.5, Industry E. Rd. VII, Hsinchu Science Park,
EAN System Configuration
MFB PWR/MFB/UART_RX_IND
P3_0 LINE IN Detection
P2_0 System Configuration
AIL
P0_4 Audio AMP Enable(ROM)
AIR
Board Name
JP3
JP 1x8
1
2
3
4
5
6
7
8
GPIO Description
P2_4
HCI_RXD
HCI_TXD
EAN
P0_0 UART_TX_IND(Flash)
ADAP_IN
P2_0
RESERVE For
BLUETOOTH DEBUG
P0_4
UART_RXD
UART_TXD
RESET_n
Audio AMP Enable
MFB/RX_IND
TX_IND
UART CONTROL
(by MCU)
Stereo Module
5.2. BM23 REFERENCE CIRCUIT
Page 28
Stereo Module
6. MODULE OUTLINE AND REFLOW PROFILE
6.1. MODULE DIMENSION AND PCB FOOT PRINT
FIGURE 6-1: BM20 Outline Dimension
PCB dimension:
X : 15.0 mm
Y : 29.0 mm
Tolerances: 0.25 mm
2015 Microchip Technology Inc.
Preliminary Edition
Page 29
Stereo Module
FIGURE 6-2: BM23 Outline Dimension
PCB dimension:
X : 15.0 mm
Y : 29.0 mm
Tolerances: 0.25 mm
2015 Microchip Technology Inc.
Preliminary Edition
Page 30
Stereo Module
FIGURE 6-3: BM20 PCB FOOT PRINT
Note: The “Keep Out Area” is reserved for RF performance check.
2015 Microchip Technology Inc.
Preliminary Edition
Page 31
Stereo Module
FIGURE 6-4: BM23 PCB FOOT PRINT
Note: The “Keep Out Area” is reserved for RF performance check.
2015 Microchip Technology Inc.
Preliminary Edition
Page 32
Stereo Module
6.2 REFLOW PROFILE
FIGURE 6-5: REFLOW PROFILE
peak: 260 +5/-0℃
Slope: 1~2℃/sec max.
(217℃ to peak)
Ramp down rate :
Max. 3℃/sec.
217℃
Preheat: 150~200℃
20~40 sec.
60 ~ 180 sec.
60 ~150sec
Time (sec)
25℃
Soldering Recommendations
Stereo module was assembled using standard lead‐free reflow profile IPC/JEDEC J‐STD‐020. The
module can be soldered to the main PCB using standard leaded and lead‐free solder reflow
profiles. To avoid damaging of the module, the recommendations are listed as follows:
•
•
•
•
•
•
Refer to Microchip Technology Application Note AN233 Solder Reflow
Recommendation (DS00233) for the soldering reflow recommendations
Do not exceed peak temperature (TP) of 250 degree C
Refer to the solder paste data sheet for specific reflow profile recommendations
Use no‐clean flux solder paste
Do not wash as moisture can be trapped under the shield
Use only one flow. If the PCB requires multiple flows, apply the module on the final flow.
2015 Microchip Technology Inc.
Preliminary Edition
Page 33
Stereo Module
7. PACKAGING AND STORAGE INFORMATION
The module is packaged into trays (see following page) of sixty three (63) modules in a 7 x 9 format.
These trays are then sealed into bags. Ten sealed bags are then placed in a box of 630 pieces with a
3
dimension of 36 * 16 * 9.5 cm .
The shelf life of each module in a sealed bag is 12 months at
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