EMC1188-1-AIA

EMC1188 Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications PRODUCT FEATURES Datasheet General Description Applications The EMC1188 is a high accuracy, low cost, 1.8V System Management Bus (SMBus) compatible temperature sensor. Advanced features such as Resistance Error Correction (REC), Beta Compensation (to support CPU diodes requiring the BJT/transistor model including 65nm and lower geometry processors) and automatic diode type detection combine to provide a robust solution for complex environmental monitoring applications. The ability to communicate at 1.8V SMBus levels provides compatible I/O for the advanced processors found in today’s tablet and smartphone applications.  The EMC1188 monitors four temperature (three external and one internal) channels, providing ±1°C accuracy for both external and internal diode temperatures. Additionally, the EMC1188provides a hardware programmable system shutdown feature that is programmed at part power-up via two pull-up resistor values and that cannot be masked or corrupted through the SMBus. REC automatically eliminates the temperature error caused by series resistance allowing greater flexibility in routing thermal diodes. Frequency hopping* and analog filters ensure remote diode traces can be as far as eight (8) inches without degrading the signal. Beta Compensation eliminates temperature errors caused by low, variable beta transistors common in today's fine geometry processors. The automatic beta detection feature monitors the external diode/transistor and determines the optimum sensor settings for accurate temperature measurements regardless of processor technology. This frees the user from providing unique sensor configurations for each temperature monitoring application. These advanced features plus ±1°C measurement accuracy provide a low-cost, highly flexible and accurate solution for critical temperature monitoring applications.    Notebook Computers Desktop Computers Industrial Embedded applications Features  Hardware Thermal Shutdown — triggers dedicated SYS_SHDN pin — hardware configured range 77°C to 112°C in 1°C steps — cannot be disabled or modified by software  Support for diodes requiring the BJT/transistor model — Supports 65nm and lower geometry CPU thermal diodes   Pin and register compatible with EMC1424 Automatically determines external diode type and optimal settings Resistance Error Correction Frequency hops the remote sample frequency to reject DC converter and other coherent noise sources* Consecutive Alert queue to further reduce false Alerts Up to 3 External Temperature Monitor  — 25°C typ, ±1°C max accuracy (20°C < TDIODE < 110°C) — 0.125°C resolution — Supports up to 2.2nF diode filter capacitor Anti-parallel diodes for extra diode support Internal     Temperature Monitor — ±1°C accuracy — 0.125°C resolution     3.3V Supply Voltage 1.8V SMBus operation Programmable temperature limits for ALERT (85°C default high limit and 0°C default low limit) Available in small 10-pin 3mm x 3mm DFN RoHS compliant package VDD EMC1188 Switching Current VDD = 3.3V SYS_SHDN Limit DP1 Thermal diode Low Limit Registers High Limit Registers Internal Temperature Register Internal Temp Diode SMBus Interface External Temperature Register(s) Digital Mux ΔΣ ADC Digital Mux Analog Mux Limit Comparator CPU DN1 DP2 / DN3* Antiparallel diodes* DN2 /DP3* SMCLK Configuration Register Status Registers Interupt Masking 1.8V – 3.3V VDD Conversion Rate Register SMDATA ALERT Optional Antiparallel diode SYS_SHDN Host EMC1188 DP1 DN1 Interna l Diod e SMCLK SMDATA ALERT SMBus Interface DP2 / DN3 DN2 / DP3 SYS_SHDN Power Control GND * Technology covered under the US patent 7,193,543. SMSC EMC1188 Revision 1.0 (07-11-13) DATASHEET Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Ordering Information: ORDERING NUMBER PACKAGE FEATURES EMC1188-1-AIA-TR 10-pin DFN 3mm x 3mm (RoHS compliant) Up to four temperature sensors, hardware set system shutdown, ALERT and SYS_SHDN pins, fixed SMBus address SMBUS ADDRESS 1001_1100(r/w) This product meets the halogen maximum concentration values per IEC61249-2-21 For RoHS compliance and environmental information, please visit www.smsc.com/rohs Please contact your SMSC sales representative for additional documentation related to this product such as application notes, anomaly sheets, and design guidelines. Copyright © 2013 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders. The Microchip name and logo, and the Microchip logo are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Revision 1.0 (07-11-13) 2 DATASHEET SMSC EMC1188 Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Table of Contents Chapter 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chapter 2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chapter 3 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 SMBus Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chapter 4 System Management Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 Communications Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 SMBus Start Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.2 SMBus Address and RD / WR Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.3 SMBus Data Bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.4 SMBus ACK and NACK Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.5 SMBus Stop Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.6 SMBus Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1.7 SMBus and I2C Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 SMBus Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 Write Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 Read Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3 Send Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.4 Receive Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Alert Response Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13 13 13 13 14 14 14 14 15 15 15 15 16 Chapter 5 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.1 Conversion Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Dynamic Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 .SYS_SHDN Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Hardware Thermal Shutdown Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 ALERT Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1 ALERT Pin Interrupt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2 ALERT Pin Comparator Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 ALERT and SYS_SHDN Pin Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.1 Beta Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.2 Resistance Error Correction (REC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.3 Programmable External Diode Ideality Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8 Diode Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.9 Consecutive Alerts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.10 Digital Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.11 Temperature Measurement Results and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 17 18 19 20 20 20 20 21 21 21 22 22 22 22 24 Chapter 6 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1 Data Read Interlock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Temperature Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Status Register 02h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Configuration Register 03h / 09h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMSC EMC1188 3 DATASHEET 28 28 29 30 Revision 1.0 (07-11-13) Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet 6.5 Conversion Rate Register 04h / 0Ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.6 Limit Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7 Scratchpad Registers 11h and 12h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8 Therm Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.9 External Diode Fault Register 1Bh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.10 Software Thermal Shutdown Configuration Register 1Dh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.11 Hardware Thermal Shutdown Limit Register 1Eh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.12 Channel Mask Register 1Fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13 Consecutive ALERT Register 22h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.14 Beta Configuration Register 26h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.15 External Diode Ideality Factor Register 27h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.16 High Limit Status Register 35h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.17 Low Limit Status Register 36h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.18 Therm Limit Status Register 37h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.19 Filter Control Register 40h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.20 Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.21 SMSC ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.22 Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 32 33 33 34 34 35 36 36 38 39 41 41 42 42 43 43 43 Chapter 7 Typical Operating Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Chapter 8 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.1 Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Chapter 9 Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Revision 1.0 (07-11-13) 4 DATASHEET SMSC EMC1188 Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet List of Figures Figure 1.1 Figure 2.1 Figure 4.1 Figure 5.1 Figure 5.2 Figure 5.3 Figure 5.4 Figure 5.5 Figure 8.1 Figure 8.2 Figure 8.3 Figure 8.4 EMC1188 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 EMC1188 Pin Diagram DFN-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SMBus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 System Diagram for EMC1188 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Block Diagram of Hardware Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Isolating ALERT and SYS_SHDN Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Temperature Filter Step Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Temperature Filter Impulse Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10-Pin DFN Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10-Pin DFN Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10 Pin DFN PCB Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 EMC1188-1 10-Pin DFN Package Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 SMSC EMC1188 5 DATASHEET Revision 1.0 (07-11-13) Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet List of Tables Table 2.1 EMC1188 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2.2 Pin Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 3.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 3.3 SMBus Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 4.1 Protocol Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4.2 Write Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4.3 Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4.4 Send Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4.5 Receive Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4.6 Alert Response Address Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 5.1 Supply Current vs. Conversion Rate for EMC1188 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 5.2 SYS_SHDN Threshold Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 5.3 Temperature Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 6.1 Register Set in Hexadecimal Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 6.2 Temperature Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 6.3 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 6.4 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 6.5 Conversion Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 6.6 Conversion Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 6.7 Temperature Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 6.8 Scratchpad Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 6.9 Therm Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 6.10 External Diode Fault Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 6.11 Software Thermal Shutdown Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 6.12 Hardware Thermal Shutdown Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 6.13 Channel Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 6.14 Consecutive ALERT Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 6.15 Consecutive Alert / Therm Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 6.16 Beta Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 6.17 CPU Beta Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 6.18 Ideality Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 6.19 Ideality Factor Look-Up Table (Diode Model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 6.20 Substrate Diode Ideality Factor Look-Up Table (BJT Model) . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 6.21 High Limit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 6.22 Low Limit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 6.23 Therm Limit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 6.24 Filter Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 6.25 FILTER Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 6.26 Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 6.27 Manufacturer ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 6.28 Revision Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 9.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Revision 1.0 (07-11-13) 6 DATASHEET SMSC EMC1188 Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Chapter 1 Block Diagram VDD EMC1188 Switching Current SYS_SHDN Limit Conversion Rate Register DN2 /DP3* External Temperature Register(s) Internal Temperature Register Low Limit Registers SMBus Interface Anti-parallel diodes* ΔΣ ADC Digital Mux Analog Mux Digital Mux DN1 DP2 / DN3* Limit Comparator DP1 High Limit Registers Internal Temp Diode SMCLK SMDATA Configuration Register Status Registers Interupt Masking ALERT SYS_SHDN GND Figure 1.1 EMC1188 Block Diagram SMSC EMC1188 7 DATASHEET Revision 1.0 (07-11-13) Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Chapter 2 Pin Description EMC1188 VDD 1 10 SMCLK DP1 2 9 SMDATA DN1 3 8 ALERT DP2 / DN3 4 7 SYS_SHDN DN2 / DP3 5 6 GND Exposed pad Figure 2.1 EMC1188 Pin Diagram DFN-10 Table 2.1 EMC1188 Pin Description PIN NUMBER NAME 1 VDD Power supply 2 DP1 External diode 1 positive (anode) connection AIO 3 DN1 External diode 1 negative (cathode) connection AIO 4 DP2 / DN3 External diode 2 positive (anode) connection / External Diode 3 negative (cathode) connection for anti-parallel diodes AIO 5 DN2 / DP3 External diode 2 negative (cathode) connection / External Diode 3 positive (anode) connection for anti-parallel diodes AIO 6 GND 7 SYS_SHDN 8 ALERT 9 SMDATA Revision 1.0 (07-11-13) FUNCTION Ground TYPE Power Power Active low system shutdown output signal requires pull-up resistor which selects the Hardware Thermal Shutdown Limit OD (5V) Active low digital ALERT output signal - requires pull-up resist OD (5V) SMBus Data input/output - requires pull-up resistor 8 DATASHEET DIOD (5V) SMSC EMC1188 Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Table 2.1 EMC1188 Pin Description (continued) PIN NUMBER NAME 10 SMCLK Bottom Pad Exposed Pad FUNCTION SMBus Clock input - requires pull-up resistor Not internally connected, but recommend grounding. TYPE DI (5V) - The pin types are described Table 2.2. Table 2.2 Pin Types PIN TYPE Power AIO DI DESCRIPTION This pin is used to supply power or ground to the device. Analog Input / Output -This pin is used as an I/O for analog signals. Digital Input - This pin is used as a digital input. This pin is 5V tolerant. DIOD Digital Input / Open Drain Output - This pin is used as a digital I/O. When it is used as an output, it is open drain and requires a pull-up resistor. This pin is 5V tolerant. OD Open Drain Digital Output - This pin is used as a digital output. It is open drain and requires a pull-up resistor. This pin is 5V tolerant. SMSC EMC1188 9 DATASHEET Revision 1.0 (07-11-13) Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Chapter 3 Electrical Specifications 3.1 Absolute Maximum Ratings Table 3.1 Absolute Maximum Ratings DESCRIPTION RATING UNIT Supply Voltage (VDD) -0.3 to 4.0 V Voltage on 5V tolerant pins (V5VT_pin) -0.3 to 5.5 V 0 to 3.6 V -0.3 to VDD +0.3 V Operating Temperature Range -40 to +125 °C Storage Temperature Range -55 to +150 °C Voltage on 5V tolerant pins (|V5VT_pin - VDD|) (see Note 3.1) Voltage on any other pin to Ground Lead Temperature Range Refer to JEDEC Spec. J-STD-020 ESD Rating, All pins HBM 2000 V Note: Stresses at or above those listed could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note 3.1 3.2 For the 5V tolerant pins that have a pull-up resistor (SMCLK, SMDATA,SYS_SHDN and ALERT), the pull-up voltage must not exceed 3.6V when the device is unpowered. Electrical Specifications Table 3.2 Electrical Specifications VDD = 3.0V to 3.6V, TA = -40°C to 125°C, all typical values at TA = 27°C unless otherwise noted. CHARACTERISTIC SYMBOL MIN TYP MAX UNITS CONDITIONS DC Power Supply Voltage VDD Supply Current IDD Revision 1.0 (07-11-13) 3.0 3.3 3.6 V 200 410 µA 0.0625 conversion / sec, dynamic averaging disabled 215 425 µA 1 conversion / sec, dynamic averaging disabled 325 465 µA 4 conversions / sec, dynamic averaging disabled 890 1050 µA 4 conversions / sec, dynamic averaging enabled 10 DATASHEET SMSC EMC1188 Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Table 3.2 Electrical Specifications (continued) VDD = 3.0V to 3.6V, TA = -40°C to 125°C, all typical values at TA = 27°C unless otherwise noted. CHARACTERISTIC SYMBOL MIN TYP MAX 1120 UNITS µA CONDITIONS > 16 conversions / sec, dynamic averaging enabled Internal Temperature Monitor Temperature Accuracy ±0.25 Temperature Resolution ±1 °C -5°C < TA < 100°C ±2 °C -40°C < TA < 125°C 0.125 °C External Temperature Monitor Temperature Accuracy Temperature Resolution Capacitive Filter ±0.25 ±1 °C +20°C < TDIODE < +110°C 0°C < TA < 100°C ±0.5 ±2 °C -40°C < TDIODE < 127°C 0.125 CFILTER °C 2.2 2.7 nF Connected across external diode ALERT and SYS_SHDN pins Output Low Voltage VOL Leakage Current ILEAK 3.3 0.4 ±5 V ISINK = 8mA µA ALERT and pins Device powered or unpowered TA < 85°C pull-up voltage < 3.6V SMBus Electrical Characteristics Table 3.3 SMBus Electrical Specifications VDD = 3.0 to 3.6V, TA = -40°C to 125°C, all typical values are at TA = 27°C unless otherwise noted. CHARACTERISTIC SYMBOL MIN TYP MAX UNITS CONDITIONS SMBus Interface Input High Voltage VIH 1.4 VDD V 5V Tolerant. Voltage threshold based on 1.8V operation Input Low Voltage VIL -0.3 0.8 V 5V Tolerant. Voltage threshold based on 1.8V operation Leakage Current ILEAK ±5 µA Powered or unpowered TA < 85°C Hysteresis 50 Input Capacitance CIN Output Low Sink Current IOL SMSC EMC1188 mV 5 pF 8.2 15 11 DATASHEET mA SMDATA = 0.4V Revision 1.0 (07-11-13) Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Table 3.3 SMBus Electrical Specifications (continued) VDD = 3.0 to 3.6V, TA = -40°C to 125°C, all typical values are at TA = 27°C unless otherwise noted. CHARACTERISTIC SYMBOL MIN TYP MAX UNITS CONDITIONS SMBus Timing Clock Frequency fSMB Spike Suppression tSP Bus Free Time Stop to Start tBUF 1.3 µs Hold Time: Start tHD:STA 0.6 µs Setup Time: Start tSU:STA 0.6 µs Setup Time: Stop tSU:STO 0.6 µs Data Hold Time tHD:DAT 0 µs When transmitting to the master Data Hold Time tHD:DAT 0.3 µs When receiving from the master Data Setup Time tSU:DAT 100 ns Clock Low Period tLOW 1.3 µs Clock High Period tHIGH 0.6 µs Clock/Data Fall time tFALL 300 ns Min = 20+0.1CLOAD ns Clock/Data Rise time tRISE 300 ns Min = 20+0.1CLOAD ns Capacitive Load CLOAD 400 pF per bus line Timeout tTIMEOUT 35 ms Disabled by default Revision 1.0 (07-11-13) 10 25 400 kHz 50 ns 12 DATASHEET SMSC EMC1188 Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Chapter 4 System Management Bus Interface Protocol 4.1 Communications Protocol The EMC1188 communicates with a host controller, such as an SMSC SIO, through the SMBus. The SMBus is a two-wire serial communication protocol between a computer host and its peripheral devices. A detailed timing diagram is shown in Figure 4.1. For the first 15ms after power-up the device may not respond to SMBus communications. . T LOW T HD:STA T HIGH T SU:STO T FALL SMCLK T RISE T HD:STA T SU:DAT T HD:DAT T SU:STA SMDATA TBUF S P S S - Start Condition P - Stop Condition P Figure 4.1 SMBus Timing Diagram 4.1.1 SMBus Start Bit The SMBus Start bit is defined as a transition of the SMBus Data line from a logic ‘1’ state to a logic ‘0’ state while the SMBus Clock line is in a logic ‘1’ state. 4.1.2 SMBus Address and RD / WR Bit The SMBus Address Byte consists of the 7-bit client address followed by the RD / WR indicator bit. If this RD / WR bit is a logic ‘0’, the SMBus Host is writing data to the client device. If this RD / WR bit is a logic ‘1’, the SMBus Host is reading data from the client device. The EMC1188-1 SMBus address is hard coded to 1001_1100(r/w). 4.1.3 SMBus Data Bytes All SMBus Data bytes are sent most significant bit first and composed of 8-bits of information. 4.1.4 SMBus ACK and NACK Bits The SMBus client will acknowledge all data bytes that it receives. This is done by the client device pulling the SMBus data line low after the 8th bit of each byte that is transmitted. This applies to the Write Byte protocol. The Host will NACK (not acknowledge) the last data byte to be received from the client by holding the SMBus data line high after the 8th data bit has been sent. SMSC EMC1188 13 DATASHEET Revision 1.0 (07-11-13) Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet 4.1.5 SMBus Stop Bit The SMBus Stop bit is defined as a transition of the SMBus Data line from a logic ‘0’ state to a logic ‘1’ state while the SMBus clock line is in a logic ‘1’ state. When the device detects an SMBus Stop bit and it has been communicating with the SMBus protocol, it will reset its client interface and prepare to receive further communications. 4.1.6 SMBus Timeout The EMC1188 supports SMBus Timeout. If the clock line is held low for longer than tTIMEOUT, the device will reset its SMBus protocol. This function can be enabled by setting the TIMEOUT bit (see Section 6.13, "Consecutive ALERT Register 22h"). 4.1.7 SMBus and I2C Compatibility The EMC1188 is compatible with SMBus and I2C. The major differences between SMBus and I2C devices are highlighted here. For more information, refer to the SMBus 2.0 and I2C specifications. For information on using the EMC1188 in an I2C system, refer to SMSC AN 14.0 SMSC Dedicated Slave Devices in I2C Systems. 1. EMC1188 supports I2C fast mode at 400kHz. This covers the SMBus max time of 100kHz. 2. Minimum frequency for SMBus communications is 10kHz. 3. The SMBus client protocol will reset if the clock is held at a logic ‘0’ for longer than 30ms. This timeout functionality is disabled by default in the EMC1188 and can be enabled by writing to the TIMEOUT bit. I2C does not have a timeout. 4. I2C devices do not support the Alert Response Address functionality (which is optional for SMBus). Attempting to communicate with the EMC1188 SMBus interface with an invalid slave address or invalid protocol will result in no response from the device and will not affect its register contents. Stretching of the SMCLK signal is supported, provided other devices on the SMBus control the timing. 4.2 SMBus Protocols The device supports Send Byte, Read Byte, Write Byte, Receive Byte, and the Alert Response Address as valid protocols as shown below. All of the below protocols use the convention in Table 4.1. Table 4.1 Protocol Format Revision 1.0 (07-11-13) DATA SENT TO DEVICE DATA SENT TO THE HOST # of bits sent # of bits sent 14 DATASHEET SMSC EMC1188 Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet 4.2.1 Write Byte The Write Byte is used to write one byte of data to the registers, as shown in Table 4.2. Table 4.2 Write Byte Protocol START SLAVE ADDRESS WR ACK REGISTER ADDRESS ACK REGISTER DATA ACK STOP 1 -> 0 YYYY_YYY 0 0 XXh 0 XXh 0 0 -> 1 4.2.2 Read Byte The Read Byte protocol is used to read one byte of data from the registers as shown in Table 4.3. Table 4.3 Read Byte Protocol START SLAVE ADDRESS WR ACK REGISTER ADDRESS ACK START SLAVE ADDRESS RD ACK REGISTER DATA NACK STOP 1 -> 0 YYYY_ YYY 0 0 XXh 0 1 -> 0 YYYY_ YYY 1 0 XX 1 0 -> 1 4.2.3 Send Byte The Send Byte protocol is used to set the internal address register pointer to the correct address location. No data is transferred during the Send Byte protocol as shown in Table 4.4. Table 4.4 Send Byte Protocol START SLAVE ADDRESS WR ACK REGISTER ADDRESS ACK STOP 1 -> 0 YYYY_YYY 0 0 XXh 0 0 -> 1 4.2.4 Receive Byte The Receive Byte protocol is used to read data from a register when the internal register address pointer is known to be at the right location (e.g. set via Send Byte). This is used for consecutive reads of the same register as shown in Table 4.5. Table 4.5 Receive Byte Protocol START SLAVE ADDRESS RD ACK REGISTER DATA NACK STOP 1 -> 0 YYYY_YYY 1 0 XXh 1 0 -> 1 SMSC EMC1188 15 DATASHEET Revision 1.0 (07-11-13) Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet 4.3 Alert Response Address The ALERT output can be used as a processor interrupt or as an SMBus Alert. When it detects that the ALERT pin is asserted, the host will send the Alert Response Address (ARA) to the general address of 0001_100xb. All devices with active interrupts will respond with their client address as shown in Table 4.6. Table 4.6 Alert Response Address Protocol START ALERT RESPONSE ADDRESS RD ACK DEVICE ADDRESS NACK STOP 1 -> 0 0001_100 1 0 YYYY_YYY 1 0 -> 1 The EMC1188 will respond to the ARA in the following way: 1. Send Slave Address and verify that full slave address was sent (i.e. the SMBus communication from the device was not prematurely stopped due to a bus contention event). 2. Set the MASK_ALL bit to clear the ALERT pin. APPLICATION NOTE: The ARA does not clear the Status Register and if the MASK_ALL bit is cleared prior to the Status Register being cleared, the ALERT pin will be reasserted. Revision 1.0 (07-11-13) 16 DATASHEET SMSC EMC1188 Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Chapter 5 Product Description The is an SMBus temperature sensor with Hardware Thermal Shutdown. The EMC1188 monitors one internal diode and up to three externally connected temperature diodes. Thermal management is performed in cooperation with a host device. This consists of the host reading the temperature data of both the external and internal temperature diodes of the EMC1188 and using that data to control the speed of one or more fans. The EMC1188 has two levels of monitoring. The first provides a maskable ALERT signal to the host when the measured temperatures exceeds user programmable limits. This allows the EMC1188 to be used as an independent thermal watchdog to warn the host of temperature hot spots without direct control by the host. The second level of monitoring asserts the SYS_SHDN pin when the External Diode temperature exceeds a hardware specified threshold temperature.Additionally, the internal diode and External Diode 2 and 3 can be configured to assert the SYS_SHDN pin when the measured temperature exceeds user programmable limits. For the EMC1188, External Diode channels 2 and 3 are only compatible with general purpose diodes (such as a 2N3904). Figure 5.1 shows a system level block diagram of the EMC1188. VDD = 3.3V 1.8V – 3.3V VDD CPU Thermal diode Host EMC1188 DP1 DN1 Internal Diode SMCLK SMDATA ALERT Optional Anti-parallel diode SMBus Interface DP2 / DN3 DN2 / DP3 SYS_SHDN Power Control Figure 5.1 System Diagram for EMC1188 5.1 Conversion Rates The EMC1188 may be configured for different conversion rates based on the system requirements. The conversion rate is configured as described in Section 6.5. The default conversion rate is 4 conversions per second. Other available conversion rates are shown in Table 6.6, "Conversion Rate". 5.2 Dynamic Averaging Dynamic averaging causes the EMC1188 to measure the external diode channels for an extended time based on the selected conversion rate. This functionality can be disabled for increased power savings at the lower conversion rates (see Section 6.4, "Configuration Register 03h / 09h"). When dynamic averaging is enabled, the device will automatically adjust the sampling and measurement time for the external diode channels. This allows the device to average 2x or 16x longer than the normal 11 bit operation (nominally 21ms per channel) while still maintaining the selected conversion rate. The SMSC EMC1188 17 DATASHEET Revision 1.0 (07-11-13) Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet benefits of dynamic averaging are improved noise rejection due to the longer integration time as well as less random variation of the temperature measurement. When enabled, the dynamic averaging applies when a one-shot command is issued. The device will perform the desired averaging during the one-shot operation according to the selected conversion rate. When enabled, the dynamic averaging will affect the average supply current based on the chosen conversion rate as shown in Table 5.1. Table 5.1 Supply Current vs. Conversion Rate for EMC1188 AVERAGE SUPPLY CURRENT (TYPICAL) AVERAGING FACTOR (BASED ON 11-BIT OPERATION) CONVERSION RATE ENABLED (DEFAULT) DISABLED ENABLED (DEFAULT) DISABLED 1 / 16 sec 230uA 220uA 16x 1x 1 / 8 sec 275uA 220uA 16x 1x 1 / 4 sec 350uA 220uA 16x 1x 1 / 2 sec 405uA 220uA 16x 1x 1 / sec 480uA 250uA 8x 1x 2 / sec 850uA 290uA 4x 1x 4 / sec (default) 890uA 370uA 2x 1x 8 / sec 970uA 525uA 1x 1x 16 / sec 990uA 690uA 0.5x 0.5x 32 / sec 1030uA 1050uA 0.25x 0.25x 64 / sec 1500uA 1100uA 0.125x 0.125x 5.3 .SYS_SHDN Output The SYS_SHDN output is asserted independently of the ALERT output and cannot be masked. If the External Diode 1 temperature exceeds the Hardware Thermal Shutdown Limit for the programmed number of consecutive measurements, the SYS_SHDN pin is asserted. The Hardware Thermal Shutdown Limit is defined at power-up via the pull-up resistors on the SYS_SHDN and ALERT pins as shown in Table 5.2. This limit cannot be modified or masked via software. In addition to External Diode 1 channel triggering the SYS_SHDN pin when the measured temperature exceeds to the Hardware Thermal Shutdown Limit, each of the measurement channels can be configured to assert the SYS_SHDN pin when they exceed the corresponding THERM Limit. When the SYS_SHDN pin is asserted, it will not release until the External Diode 1 temperature drops below the Hardware Thermal Shutdown Limit minus 10°C and all other measured temperatures drop below the THERM Limit minus the THERM Hysteresis value (when linked to SYS_SHDN). Figure 5.2 shows a block diagram of the interaction between the input channels and the SYS_SHDN pin. Revision 1.0 (07-11-13) 18 DATASHEET SMSC EMC1188 Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Internal Diode S/W Set Sensor (EMC1188 only) S/W Set Sensor Temperature Conversion and up to 4 THERM Limit Registers S/W Set Sensor Hardware Thermal Shutdown SMBus Traffic Software Shutdown Enable H/W Thermal Shutdown Sensor 3.3V Temperature Conversion SW_SHDN 3.3V SYS_SHDN HW_SHDN ALERT Function Select Figure 5.2 Block Diagram of Hardware Thermal Shutdown 5.4 Hardware Thermal Shutdown Limit The Hardware Thermal Shutdown Limit temperature is determined by pull-up resistors on the SYS_SHDN and ALERT pins shown in Table 5.2. Table 5.2 SYS_SHDN Threshold Temperature SYS_SHD PULL-UP ALERT PULL-UP 4.7K OHM ±10% 6.8K OHM ±10% 10K OHM ±10% 15K OHM ±10% 22K OHM ±10% 33K OHM ±10% 4.7K OHM ±10% 77°C 83°C 89°C 95°C 101°C 107°C 6.8K OHM ±10% 78°C 84°C 90°C 96°C 102°C 108°C 10K OHM ±10% 79°C 85°C 91°C 97°C 103°C 109°C 15K OHM ±10% 80°C 86°C 92°C 98°C 104°C 110°C 22K OHM ±10% 81°C 87°C 93°C 99°C 105°C 111°C 33K OHM ±10% 82°C 88°C 94°C 100°C 106°C 112°C SMSC EMC1188 19 DATASHEET Revision 1.0 (07-11-13) Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet 5.5 ALERT Output The ALERT pin is an open drain output and requires a pull-up resistor to VDD and has two modes of operation: interrupt mode and comparator mode. The mode of the ALERT output is selected via the ALERT / COMP bit in the Configuration Register (see Section 6.4). 5.5.1 ALERT Pin Interrupt Mode When configured to operate in interrupt mode, the ALERT pin asserts low when an out of limit measurement (> high limit or < low limit) is detected on any diode or when a diode fault is detected, functioning as any standard ALERT in on the SMBus. The ALERT pin will remain asserted as long as an out-of-limit condition remains. Once the out-of-limit condition has been removed, the ALERT pin will remain asserted until the appropriate status bits are cleared. The ALERT pin can be masked by setting the MASK_ALL bit. Once the ALERT pin has been masked, it will be de-asserted and remain de-asserted until the MASK_ALL bit is cleared by the user. Any interrupt conditions that occur while the ALERT pin is masked will update the Status Register normally. There are also individual channel masks (see Section 6.12). The ALERT pin is used as an interrupt signal or as an SMBus Alert signal that allows an SMBus slave to communicate an error condition to the master. One or more ALERT outputs can be hard-wired together. 5.5.2 ALERT Pin Comparator Mode When the ALERT pin is configured to operate in comparator mode, it will be asserted if any of the measured temperatures exceeds the respective high limit. The ALERT pin will remain asserted until all temperatures drop below the corresponding high limit minus the Therm Hysteresis value. When the ALERT pin is asserted in comparator mode, the corresponding high limit status bits will be set. Reading these bits will not clear them until the ALERT pin is deasserted. Once the ALERT pin is deasserted, the status bits will be automatically cleared. The MASK_ALL bit will not block the ALERT pin in this mode; however, the individual channel masks (see Section 6.12) will prevent the respective channel from asserting the ALERT pin. 5.6 ALERT and SYS_SHDN Pin Considerations Because of the decode method used to determine the Hardware Thermal Shutdown Limit, it is important that the pull-up resistance on both the ALERT and SYS_SHDN pins be within the tolerances shown in Table 5.2. Additionally, the pull-up resistor on the ALERT and SYS_SHDN pins must be connected to the same 3.3V supply that drives the VDD pin. For 15ms after power up, the ALERT and SYS_SHDN pins must not be pulled low or the Hardware Thermal Shutdown Limit will not be decoded properly. If the system requirements do not permit these conditions, the ALERT and SYS_SHDN pins must be isolated from their respective busses during this time. One method of isolating the ALERT pin is shown in Figure 5.3. Revision 1.0 (07-11-13) 20 DATASHEET SMSC EMC1188 Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet +3.3V VDD 1 10 SMCLK DP1 2 9 SMDATA DN1 3 8 ALERT DP2/DN3 4 7 SYS_SHDN DN2/DP3 5 6 GND EMC1188 4.7K 33K +2.5 - 5V 22K Shared Alert +3.3V 4.7K 33K +2.5 - 5V 22K Shared SYS_SHDN Figure 5.3 Isolating ALERT and SYS_SHDN Pin 5.7 Temperature Measurement The EMC1188 can monitor the temperature of up to three externally connected diode. The device contains programmable High, Low, and Therm limits for all measured temperature channels. If the measured temperature goes below the Low limit or above the High limit, the ALERT pin can be asserted (based on user settings). 5.7.1 Beta Compensation The EMC1188 is configured to monitor the temperature of basic diodes (e.g., 2N3904) or CPU thermal diodes. It automatically detects the type of external diode (CPU diode or diode connected transistor) and determines the optimal setting to reduce temperature errors introduced by beta variation. Compensating for this error is also known as implementing the transistor or BJT model for temperature measurement. For discrete transistors configured with the collector and base shorted together, the beta is generally sufficiently high such that the percent change in beta variation is very small. For example, a 10% variation in beta for two forced emitter currents with a transistor whose ideal beta is 50 would contribute approximately 0.25°C error at 100°C. However for substrate transistors where the base-emitter junction is used for temperature measurement and the collector is tied to the substrate, the proportional beta variation will cause large error. For example, a 10% variation in beta for two forced emitter currents with a transistor whose ideal beta is 0.5 would contribute approximately 8.25°C error at 100°C. For the EMC1188 the External Diode 2 and External Diode 3 channels do not support Beta Compensation. 5.7.2 Resistance Error Correction (REC) Parasitic resistance in series with the external diodes will limit the accuracy obtainable from temperature measurement devices. The voltage developed across this resistance by the switching diode currents cause the temperature measurement to read higher than the true temperature. SMSC EMC1188 21 DATASHEET Revision 1.0 (07-11-13) Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Contributors to series resistance are PCB trace resistance, on die (i.e. on the processor) metal resistance, bulk resistance in the base and emitter of the temperature transistor. Typically, the error caused by series resistance is +0.7°C per ohm. The EMC1188 automatically corrects up to 100 ohms of series resistance. 5.7.3 Programmable External Diode Ideality Factor The EMC1188 is designed for external diodes with an ideality factor of 1.008. Not all external diodes, processor or discrete, will have this exact value. This variation of the ideality factor introduces error in the temperature measurement which must be corrected for. This correction is typically done using programmable offset registers. Since an ideality factor mismatch introduces an error that is a function of temperature, this correction is only accurate within a small range of temperatures. To provide maximum flexibility to the user, the EMC1188 provides a 6-bit register for each external diode where the ideality factor of the diode used is programmed to eliminate errors across all temperatures. APPLICATION NOTE: When monitoring a substrate transistor or CPU diode and beta compensation is enabled, the Ideality Factor should not be adjusted. Beta Compensation automatically corrects for most ideality errors. 5.8 Diode Faults The EMC1188 detects an open on the DP and DN pins, and a short across the DP and DN pins. For each temperature measurement made, the device checks for a diode fault on the external diode channel(s). When a diode fault is detected, the ALERT pin asserts (unless masked, see Section 5.9) and the temperature data reads 00h in the MSB and LSB registers (note: the low limit will not be checked). A diode fault is defined as one of the following: an open between DP and DN, a short from VDD to DP, or a short from VDD to DN. If a short occurs across DP and DN or a short occurs from DP to GND, the low limit status bit is set and the ALERT pin asserts (unless masked). This condition is indistinguishable from a temperature measurement of 0.000°C (-64°C in extended range) resulting in temperature data of 00h in the MSB and LSB registers. If a short from DN to GND occurs (with a diode connected), temperature measurements will continue as normal with no alerts. 5.9 Consecutive Alerts The EMC1188 contain multiple consecutive alert counters. One set of counters applies to the ALERT pin and the second set of counters applies to the SYS_SHDN pin. Each temperature measurement channel has a separate consecutive alert counter for each of the ALERT and SYS_SHDN pins. All counters are user programmable and determine the number of consecutive measurements that a temperature channel(s) must be out-of-limit or reporting a diode fault before the corresponding pin is asserted. See Section 6.13, "Consecutive ALERT Register 22h" for more details on the consecutive alert function. 5.10 Digital Filter To reduce the effect of noise and temperature spikes on the reported temperature, the External Diode channel uses a programmable digital filter. This filter can be configured as Level 1, Level 2, or Disabled (default) (see Section 6.19). The typical filter performance is shown in Figure 5.4 and Figure 5.5. Revision 1.0 (07-11-13) 22 DATASHEET SMSC EMC1188 Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Filter Step Response Temperature (C) 90 Disabled 80 70 Level1 Level2 60 50 40 30 20 10 0 0 2 4 6 8 10 12 14 Samples Figure 5.4 Temperature Filter Step Response Filter Impulse Response 90 Temperature (C) 80 Disabled 70 60 50 Level1 40 Level2 30 20 10 0 0 2 4 6 8 10 12 14 Samples Figure 5.5 Temperature Filter Impulse Response SMSC EMC1188 23 DATASHEET Revision 1.0 (07-11-13) Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet 5.11 Temperature Measurement Results and Data The temperature measurement results are stored in the internal and external temperature registers. These are then compared with the values stored in the high and low limit registers. Both external and internal temperature measurements are stored in 11-bit format with the eight (8) most significant bits stored in a high byte register and the three (3) least significant bits stored in the three (3) MSB positions of the low byte register. All other bits of the low byte register are set to zero. The EMC1188 has two selectable temperature ranges. The default range is from 0°C to +127°C and the temperature is represented as binary number able to report a temperature from 0°C to +127.875°C in 0.125°C steps. The extended range is an extended temperature range from -64°C to +191°C. The data format is a binary number offset by 64°C. The extended range is used to measure temperature diodes with a large known offset (such as AMD processor diodes) where the diode temperature plus the offset would be equivalent to a temperature higher than +127°C. Table 5.3 shows the default and extended range formats. Table 5.3 Temperature Data Format TEMPERATURE (°C) DEFAULT RANGE 0°C TO 127°C EXTENDED RANGE -64°C TO 191°C Diode Fault 000 0000 0000 000 0000 0000 -64 000 0000 0000 000 0000 0000 -1 000 0000 0000 001 1111 1000 0 000 0000 0000 010 0000 0000 0.125 000 0000 0001 010 0000 0001 1 000 0000 1000 010 0000 1000 64 010 0000 0000 100 0000 0000 65 010 0000 1000 100 0000 1000 127 011 1111 1000 101 1111 1000 127.875 011 1111 1111 101 1111 1111 128 011 1111 1111 110 0000 0000 190 011 1111 1111 111 1111 0000 191 011 1111 1111 111 1111 1000 >= 191.875 011 1111 1111 111 1111 1111 Revision 1.0 (07-11-13) 24 DATASHEET SMSC EMC1188 Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Chapter 6 Register Description The registers shown in Table 6.1 are accessible through the SMBus. An entry of ‘-’ indicates that the bit is not used and will always read ‘0’. Table 6.1 Register Set in Hexadecimal Order REGISTER ADDRESS R/W REGISTER NAME FUNCTION DEFAULT VALUE 00h R Internal Diode Data High Byte Stores the integer data for the Internal Diode 00h 01h R External Diode Data High Byte Stores the integer data for External Diode 00h 02h R Status Stores the status bits for the Internal Diode and External Diode 00h 03h R/W Configuration Controls the general operation of the device (mirrored at address 09h) 04h R/W Conversion Rate Controls the conversion rate for updating temperature data (mirrored at address 0Ah) 06h (4/sec) 05h R/W Internal Diode High Limit Stores the 8-bit high limit for the Internal Diode (mirrored at address 0Bh) 55h (85°C) 06h R/W Internal Diode Low Limit Stores the 8-bit low limit for the Internal Diode (mirrored at address 0Ch) 00h (0°C) 55h (85°C) 00h (0°C) PAGE Page 28 Page 28 Page 30 Page 31 Page 32 07h R/W External Diode High Limit High Byte Stores the integer portion of the high limit for External Diode (mirrored at register 0Dh) 08h R/W External Diode Low Limit High Byte Stores the integer portion of the low limit for External Diode (mirrored at register 0Eh) 09h R/W Configuration Controls the general operation of the device (mirrored at address 03h) 0Ah R/W Conversion Rate Controls the conversion rate for updating temperature data (mirrored at address 04h) SMSC EMC1188 25 DATASHEET Page 30 06h (4/sec) Page 31 Revision 1.0 (07-11-13) Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Table 6.1 Register Set in Hexadecimal Order (continued) REGISTER ADDRESS R/W REGISTER NAME FUNCTION DEFAULT VALUE 0Bh R/W Internal Diode High Limit Stores the 8-bit high limit for the Internal Diode (mirrored at address 05h) 55h (85°C) 0Ch R/W Internal Diode Low Limit Stores the 8-bit low limit for the Internal Diode (mirrored at address 06h) 00h (0°C) 55h (85°C) PAGE Page 32 0Dh R/W External Diode High Limit High Byte Stores the integer portion of the high limit for External Diode (mirrored at register 07h) 0Eh R/W External Diode Low Limit High Byte Stores the integer portion of the low limit for External Diode (mirrored at register 08h) 00h (0°C) 10h R External Diode Data Low Byte Stores the fractional data for External Diode 00h Page 28 11h R/W Scratchpad Scratchpad register for software compatibility 00h Page 33 12h R/W Scratchpad Scratchpad register for software compatibility 00h Page 33 13h R/W External Diode High Limit Low Byte Stores the fractional portion of the high limit for External Diode 00h 14h R/W External Diode Low Limit Low Byte Stores the fractional portion of the low limit for External Diode 00h 15h R/W External Diode 2 High Limit High Byte Stores the integer portion of the high limit for External Diode 2 55h (85°C) 16h R/W External DIode 2 Low Limit High Byte Stores the integer portion of the low limit for External Diode 2 00h (0°C) 17h R/W External Diode 2 High Limit Low Byte Stores the fractional portion of the high limit External Diode 2 00h 18h R/W External Diode 2 Low Limit Low Byte Stores the fractional portion of the low limit for External Diode 2 00h 19h R/W External Diode Therm Limit Stores the 8-bit critical temperature limit for External Diode 55h (85°C) Page 33 1Ah R/W External Diode 2 Therm Limit Stores the 8-bit critical temperature limit for External Diode 2 55h (85°C) Page 33 1Bh R-C External Diode Fault Stores status bits indicating which external diode detected a diode fault 00h Page 34 1Dh R/W SYS_SHDN Configuration Controls which software channels, if any, are linked to the SYS_SHDN pin 00h Page 34 Page 32 Page 32 Page 32 Revision 1.0 (07-11-13) 26 DATASHEET SMSC EMC1188 Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Table 6.1 Register Set in Hexadecimal Order (continued) REGISTER ADDRESS R/W REGISTER NAME FUNCTION DEFAULT VALUE PAGE 1Eh R Hardware Thermal Shutdown Limit When read, returns the selected Hardware Thermal Shutdown Limit N/A Page 35 1Fh R/W Channel Mask Register Controls the masking of individual channels 00h Page 36 20h R/W Internal Diode Therm Limit Stores the 8-bit critical temperature limit for the Internal Diode 55h (85°C 0Ah (10°C) Page 33 21h R/W Therm Hysteresis Stores the 8-bit hysteresis value that applies to all Therm limits 22h R/W Consecutive ALERT Controls the number of out-of-limit conditions that must occur before an interrupt is asserted 70h 23h R External Diode 2 Data High Byte Stores the integer data for External Diode 2 00h 24h R External Diode 2 Data Low Byte Stores the fractional data for External Diode 2 00h 26h R/W External Diode 2 Beta Configuration Stores the Beta Compensation circuitry settings for External Diode 2 08h 07h (EMC1188) Page 39 27h R/W External Diode Ideality Factor Stores the ideality factor for External Diode 12h (1.008) Page 39 28h R/W External Diode 2 Ideality Factor Stores the ideality factor for External Diode 2 12h (1.008) Page 39 29h R Internal Diode Data Low Byte Stores the fractional data for the Internal Diode 00h Page 28 2Ah R External Diode 3 High Byte Stores the integer data for External Diode 3 00h 2Bh R External Diode 3 Low Byte Stores the fractional data for External Diode 3 00h 2Ch R/W External Diode 3 High Limit High Byte Stores the integer portion of the high limit for External Diode 3 55h (85°C) 2Dh R/W External Diode 3 Low Limit High Byte Stores the integer portion of the low limit for External Diode 3 00h (0°C) 2Eh R/W External Diode 3 High Limit Low Byte Stores the fractional portion of the high limit for External Diode 3 00h 2Fh R/W External Diode 3 Low Limit Low Byte Stores the fractional portion of the low limit for External Diode 3 00h 30h R/W External Diode 3 Therm Limit Stores the 8-bit critical temperature limit for External Diode 3 55h (85°C) Page 33 31h R/W External Diode 3 Ideality Factor Stores the ideality factor for External Diode 3 12h (1.008) Page 39 Page 36 Page 28 Page 28 Page 32 SMSC EMC1188 27 DATASHEET Revision 1.0 (07-11-13) Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Table 6.1 Register Set in Hexadecimal Order (continued) REGISTER ADDRESS R/W REGISTER NAME FUNCTION DEFAULT VALUE PAGE 35h R-C High Limit Status Status bits for the High Limits 00h Page 41 36h R-C Low Limit Status Status bits for the Low Limits 00h Page 41 37h R Therm Limit Status Status bits for the Therm Limits 00h Page 42 40h R/W Filter Control Controls the digital filter setting for the External Diode channel 00h Page 42 FDh R Product ID (EMC1824) Stores a fixed value that identifies the device 27h Page 43 FEh R Manufacturer ID Stores a fixed value that represents SMSC 5Dh Page 43 FFh R Revision Stores a fixed value that represents the revision number 07h Page 43 6.1 Data Read Interlock When any temperature channel high byte register is read, the corresponding low byte is copied into an internal ‘shadow’ register. The user is free to read the low byte at any time and be guaranteed that it will correspond to the previously read high byte. Regardless if the low byte is read or not, reading from the same high byte register again will automatically refresh this stored low byte data. 6.2 Temperature Data Registers Table 6.2 Temperature Data Registers ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 00h R Internal Diode High Byte 128 64 32 16 8 4 2 1 00h 29h R Internal Diode Low Byte 0.5 0.25 0.125 - - - - - 00h 01h R External Diode High Byte 128 64 32 16 8 4 2 1 00h 10h R External Diode Low Byte 0.5 0.25 0.125 - - - - - 00h 23h R External Diode 2 High Byte 128 64 32 16 8 4 2 1 00h 24h R External Diode 2 Low Byte 0.5 0.25 0.125 - - - - - 00h Revision 1.0 (07-11-13) 28 DATASHEET SMSC EMC1188 Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Table 6.2 Temperature Data Registers (continued) ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 2Ah R External Diode 3 High Byte 128 64 32 16 8 4 2 1 00h 2Bh R External Diode 3 Low Byte 0.5 0.25 0.125 - - - - - 00h As shown in Table 6.2, all temperatures are stored as an 11-bit value with the high byte representing the integer value and the low byte representing the fractional value left justified to occupy the MSBits. 6.3 Status Register 02h Table 6.3 Status Register ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 02h R Status BUSY - - HIGH LOW FAULT THERM HWSD 00h The Status Register reports general error conditions. To identify specific channels, refer to Section 6.9, Section 6.16, Section 6.17, and Section 6.18. The individual Status Register bits are cleared when the appropriate High Limit, Low Limit, or Therm Limit register has been read or cleared. Bit 7 - BUSY - This bit indicates that the ADC is currently converting. This bit does not cause either the ALERT or THERM pin to be asserted. Bit 4 - HIGH - This bit is set when any of the temperature channels exceeds its programmed high limit. See the High Limit Status Register for specific channel information (Section 6.16). When set, this bit will assert the ALERT pin. Bit 3 - LOW - This bit is set when any of the temperature channels drops below its programmed low limit. See the Low Limit Status Register for specific channel information (Section 6.17). When set, this bit will assert the ALERT pin. Bit 2 - FAULT - This bit is asserted when a diode fault is detected on any of the external diode channels. See the External Diode Fault Register for specific channel information (Section 6.9). When set, this bit will assert the ALERT pin. Bit 1 - THERM - This bit is set when the any of the temperature channels exceeds its programmed Therm Limit. See the Therm Limit Status Register for specific channel information (Section 6.18). When set, this bit will assert the THERM pin. SMSC EMC1188 29 DATASHEET Revision 1.0 (07-11-13) Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Bit 0 - HWSD - This bit is set when the External Diode 1 Temperature exceeds the Hardware Thermal Shutdown Limit set by the pull-up resistors on the ALERT and SYS_SHDN pins. When set, this bit will assert the SYS_SHDN pin. 6.4 Configuration Register 03h / 09h Table 6.4 Configuration Register ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT R/W Configuration MASK_ ALL - ALERT/ COMP RECD RECD2 RANGE DAVG_ DIS APDD 00h 03h 09h The Configuration Register controls the basic operation of the device. This register is fully accessible at either address. Bit 7 - MASK_ALL - Masks the ALERT pin from asserting.  ‘0’ - (default) - The ALERT pin is not masked. If any of the appropriate status bits are set the ALERT pin will be asserted.  ‘1’ - The ALERT pin is masked. It will not be asserted for any interrupt condition unless it is configured in comparator mode. The Status Register will be updated normally. Bit 5 - ALERT/COMP - Controls the operation of the ALERT pin.  ‘0’ (default) - The ALERT acts as an Alert pin and has interrupt behavior as described in Section 5.5.1.  ‘1’ - The ALERT acts as a THERM pin and has comparator behavior as described in Section 5.5.2. In this mode the MASK_ALL bit is ignored. Bit 4 - RECD - Disables the Resistance Error Correction (REC) for External Diode.  ‘0’ (default) - REC is enabled for External Diode.  ‘1’ - REC is disabled for External Diode. Bit 3 - RECD2 - Disables the Resistance Error Correction (REC) for External Diode 2 and External Diode 3.  ‘0’ (default) - REC is enabled for External Diode 2 and External Diode 3.  ‘1’ - REC is disabled for External Diode 2 and External Diode 3. Bit 2 - RANGE - Configures the measurement range and data format of the temperature channels.  ‘0’ (default) - The temperature measurement range is 0°C to +127.875°C and the data format is binary.  ‘1’ -The temperature measurement range is -64°C to +191.875°C and the data format is offset binary (see Table 5.3). Bit 1 - DAVG_DIS - Disables the dynamic averaging feature on all temperature channels.  ‘0’ (default) - The dynamic averaging feature is enabled. All temperature channels will be converted with an averaging factor that is based on the conversion rate as shown in Table 6.6.  ‘1’ - The dynamic averaging feature is disabled. All temperature channels will be converted with a maximum averaging factor of 1x (equivalent to 11-bit conversion). For higher conversion rates, this averaging factor will be reduced as shown in Table 6.6. Revision 1.0 (07-11-13) 30 DATASHEET SMSC EMC1188 Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Bit 0 - APDD - Disables the anti-parallel diode operation. Beta Compensation is disabled on External Diode 2 and 3 regardless of APDD setting. In addition, External Diode 2 Beta Configuration register will be ignored. 6.5  ‘0’ (default) - Anti-parallel diode mode is enabled. Two external diodes will be measured on the DP2 and DN2 pins.  ‘1’ - Anti-parallel diode mode is disabled. Only one external diode will be measured on the DP2 and DN2 pins. Conversion Rate Register 04h / 0Ah Table 6.5 Conversion Rate Register ADDR R/W REGISTER B7 B6 B5 B4 R/W Conversion Rate - - - - 04h 0Ah B3 B2 B1 B0 DEFAULT 06h (4/sec) CONV[3:0] The Conversion Rate Register controls how often the temperature measurement channels are updated and compared against the limits. This register is fully accessible at either address. Bits 3-0 - CONV[3:0] - Determines the conversion rate as shown in Table 6.6. Table 6.6 Conversion Rate CONV[3:0] HEX 3 2 1 0 CONVERSIONS / SECOND 0h 0 0 0 0 1 1h 0 0 0 1 1 2h 0 0 1 0 1 3h 0 0 1 1 4h 0 1 0 0 1 5h 0 1 0 1 2 6h 0 1 1 0 4 (default) 7h 0 1 1 1 8 8h 1 0 0 0 16 9h 1 0 0 1 32 Ah 1 0 1 0 64 Bh - Fh SMSC EMC1188 All others 1 31 DATASHEET Revision 1.0 (07-11-13) Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet 6.6 Limit Registers Table 6.7 Temperature Limit Registers ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT R/W Internal Diode High Limit 128 64 32 16 8 4 2 1 55h (85°C) R/W Internal Diode Low Limit 128 64 32 16 8 4 2 1 00h (0°C) R/W External Diode High Limit High Byte 128 64 32 16 8 4 2 1 55h (85°C) R/W External Diode High Limit Low Byte 0.5 0.25 0.125 - - - - - 00h R/W External Diode Low Limit High Byte 128 64 32 16 8 4 2 1 00h (0°C) R/W External Diode Low Limit Low Byte 0.5 0.25 0.125 - - - - - 00h R/W External Diode 2 High Limit High Byte 128 64 32 16 8 4 2 1 55h (85°C) R/W External Diode 2 Low Limit High Byte 128 64 32 16 8 4 2 1 00h (0°C) 17h R/W External Diode 2 High Limit Low Byte 0.5 0.25 0.125 - - - - - 00h 18h R/W External Diode 2 Low Limit Low Byte 0.5 0.25 0.125 - - - - - 00h R/W External Diode 3 High Limit High Byte 128 64 32 16 8 4 2 1 55h (85°C) 05h 0Bh 06h 0Ch 07h 0Dh 13h 08h 0Eh 14h 15h 16h 2Ch Revision 1.0 (07-11-13) 32 DATASHEET SMSC EMC1188 Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Table 6.7 Temperature Limit Registers (continued) ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT R/W External Diode 3 Low Limit High Byte 128 64 32 16 8 4 2 1 00h (0°C) 2Eh R/W External Diode 3 High Limit Low Byte 0.5 0.25 0.125 - - - - - 00h 2Fh R/W External Diode 3 Low Limit Low Byte 0.5 0.25 0.125 - - - - - 00h 2Dh The device contains both high and low limits for all temperature channels. If the measured temperature exceeds the high limit, then the corresponding status bit is set and the ALERT pin is asserted. Likewise, if the measured temperature is less than or equal to the low limit, the corresponding status bit is set and the ALERT pin is asserted. The data format for the limits must match the selected data format for the temperature so that if the extended temperature range is used, the limits must be programmed in the extended data format. The limit registers with multiple addresses are fully accessible at either address. 6.7 Scratchpad Registers 11h and 12h Table 6.8 Scratchpad Register ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 11h R/W Scratchpad 7 6 5 4 3 2 1 0 00h 12h R/W Scratchpad 7 6 5 4 3 2 1 0 00h The Scratchpad Registers are Read / Write registers that are used for place holders to be software compatible with legacy programs. Reading from the registers will return what is written to them. 6.8 Therm Limit Registers Table 6.9 Therm Limit Registers ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 19h R/W External Diode Therm Limit 128 64 32 16 8 4 2 1 55h (85°C) 1Ah R/W External Diode 2 Therm Limit 128 64 32 16 8 4 2 1 55h (85°C) SMSC EMC1188 33 DATASHEET Revision 1.0 (07-11-13) Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Table 6.9 Therm Limit Registers (continued) ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 20h R/W Internal Diode Therm Limit 128 64 32 16 8 4 2 1 55h (85°C) 21h R/W Therm Hysteresis 128 64 32 16 8 4 2 1 0Ah (10°C) 30h R/W External Diode 3 Therm Limit 128 64 32 16 8 4 2 1 55h (85°C) The Therm Limit Registers are used to determine whether a critical thermal event has occurred. If the measured temperature exceeds the Therm Limit, the SYS_SHDN pin will be asserted (if the corresponding measurement channel is linked to the SYS_SHDN pin - see Section 6.10, "Software Thermal Shutdown Configuration Register 1Dh"). The limit setting must match the chosen data format of the temperature reading registers. 6.9 External Diode Fault Register 1Bh Table 6.10 External Diode Fault Register ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 1Bh R-C External Diode Fault - - - - E3FLT E2FLT E1FLT - 00h The External Diode Fault Register indicates which of the external diodes caused the FAULT bit in the Status Register to be set. This register is cleared when it is read. Bit 3 - E3FLT - This bit is set if the External Diode 3 channel reported a diode fault. Bit 2 - E2FLT - This bit is set if the External Diode 2 channel reported a diode fault. Bit 1 - E1FLT - This bit is set if the External Diode 1 channel reported a diode fault. 6.10 Software Thermal Shutdown Configuration Register 1Dh Table 6.11 Software Thermal Shutdown Configuration Register ADDR. 1Dh R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT R/W Software Thermal Shutdown Configuration - - - - E3SYS E2SYS EXT1SYS INTSYS 00h The Software Thermal Shutdown Configuration Register controls whether any of the software channels will assert the SYS_SHDN pin. If a channel is enabled, the temperature is compared against the corresponding Therm Limit. If the measured temperature exceeds the Therm Limit, the SYS_SHDN pin is asserted. This functionality is in addition to the Hardware Shutdown circuitry. Revision 1.0 (07-11-13) 34 DATASHEET SMSC EMC1188 Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Bit 3 - E3SYS - Configures the External Diode 3 channel to assert the SYS_SHDN pin based on its Therm Limit.  ‘0’ (default) - The External Diode 3 channel is not linked to the SYS_SHDN pin. If the temperature exceeds its Therm Limit, the E3THERM status bit is set but the SYS_SHDN pin is not asserted.  ‘1’ - The External Diode 3 channel is linked to the SYS_SHDN pin. If the temperature exceeds its Therm Limit, the E3THERM status bit is set and the SYS_SHDN pin is asserted. It will remain asserted until the temperature drops below its Therm Limit minus the Therm Hysteresis. Bit 2 - E2SYS - Configures the External Diode 2 channel to assert the SYS_SHDN pin based on its Therm Limit.  ‘0’ (default) - The External Diode 2 channel is not linked to the SYS_SHDN pin. If the temperature exceeds its Therm Limit, the E2THERM status bit is set but the SYS_SHDN pin is not asserted.  ‘1’ - The External Diode 2 channel is linked to the SYS_SHDN pin. If the temperature exceeds its Therm Limit, the E2THERM status bit is set and the SYS_SHDN pin is asserted. It will remain asserted until the temperature drops below its Therm Limit minus the Therm Hysteresis. Bit 1 - EXT1SYS - configures the External Diode 1 channel to assert the SYS_SHDN pin based on its Therm Limit.  ‘0’ (default) - The External Diode 1 channel is not linked to the SYS_SHDN pin. If the temperature exceeds the Therm Limit, the E1THERM status bit is set but the SYS_SHDN pin is not asserted.  ‘1’ - The External Diode 1 channel is linked to the SYS_SHDN pin. If the temperature exceeds its Therm Limit, the E1THERM status bit is set and the SYS_SHDN pin is asserted. It will remain asserted until the temperature drops below its Therm Limit minus the Therm Hysteresis. Bit 0 - INTSYS - Configures the Internal Diode channel to assert the SYS_SHDN pin based on its Therm Limit. 6.11  ‘0’ (default) - The Internal Diode channel is not linked to the SYS_SHDN pin. If the temperature exceeds its Therm Limit, the ITHERM status bit is set but the SYS_SHDN pin is not asserted.  ‘1’ - The Internal Diode channel is linked to the SYS_SHDN pin. If the temperature exceeds its Therm Limit, the ITHERM status bit is set and the SYS_SHDN pin is asserted. It will remain asserted until the temperature drops below its Therm Limit minus the Therm Hysteresis. Hardware Thermal Shutdown Limit Register 1Eh Table 6.12 Hardware Thermal Shutdown Limit Register ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 1Eh R Hardware Thermal Shutdown Limit 128 64 32 16 8 4 2 1 N/A This read only register returns the Hardware Thermal Shutdown Limit selected by the value of the pullup resistors on the ALERT and SYS_SHDN pins. The data represents the hardware set temperature in °C using the active temperature setting set by the RANGE bit in the Configuration Register. See Table 5.3, "Temperature Data Format" for the data format. When the External Diode 1 Temperature exceeds this limit, the SYS_SHDN pin is asserted and will remain asserted until the External Diode 1 Temperature drops below this limit minus 10°C. SMSC EMC1188 35 DATASHEET Revision 1.0 (07-11-13) Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet 6.12 Channel Mask Register 1Fh Table 6.13 Channel Mask Register ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 1Fh R/W Channel Mask - - - - E3 MASK E2 MASK E1 MASK INT MASK 00h The Channel Mask Register controls individual channel masking. When a channel is masked, the ALERT pin will not be asserted when the masked channel reads a diode fault or out of limit error. The channel mask does not mask the SYS_SHDN pin. Bit 3 - E3MASK - Masks the ALERT pin from asserting when the External Diode 3 channel is out of limit or reports a diode fault.  ‘0’ (default) - The External Diode 3 channel will cause the ALERT pin to be asserted if it is out of limit or reports a diode fault.  ‘1’ - The External Diode 3 channel will not cause the ALERT pin to be asserted if it is out of limit or reports a diode fault. Bit 2 - E2MASK - Masks the ALERT pin from asserting when the External Diode 2 channel is out of limit or reports a diode fault.  ‘0’ (default) - The External Diode 2 channel will cause the ALERT pin to be asserted if it is out of limit or reports a diode fault.  ‘1’ - The External Diode 2 channel will not cause the ALERT pin to be asserted if it is out of limit or reports a diode fault. Bit 1 - E1MASK - Masks the ALERT pin from asserting when the External Diode1 channel is out of limit or reports a diode fault.  ‘0’ (default) - The External Diode1 channel will cause the ALERT pin to be asserted if it is out of limit or reports a diode fault.  ‘1’ - The External Diode1 channel will not cause the ALERT pin to be asserted if it is out of limit or reports a diode fault. Bit 0 - INTMASK - Masks the ALERT pin from asserting when the Internal Diode temperature is out of limit. 6.13  ‘0’ (default) - The Internal Diode channel will cause the ALERT pin to be asserted if it is out of limit.  ‘1’ - The Internal Diode channel will not cause the ALERT pin to be asserted if it is out of limit. Consecutive ALERT Register 22h Table 6.14 Consecutive ALERT Register ADDR. R/W REGISTER B7 22h R/W Consecutive ALERT TIME OUT B6 B5 B4 CTHRM[2:0] B3 B2 CALRT[2:0] B1 B0 DEFAULT - 70h The Consecutive ALERT Register determines how many times an out-of-limit error or diode fault must be detected in consecutive measurements before the ALERT or SYS_SHDN pin is asserted. Additionally, the Consecutive ALERT Register controls the SMBus Timeout functionality. Revision 1.0 (07-11-13) 36 DATASHEET SMSC EMC1188 Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet An out-of-limit condition (i.e. HIGH, LOW, or FAULT) occurring on the same temperature channel in consecutive measurements will increment the consecutive alert counter. The counters will also be reset if no out-of-limit condition or diode fault condition occurs in a consecutive reading. When the ALERT pin is configured as an interrupt, when the consecutive alert counter reaches its programmed value, the following will occur: the STATUS bit(s) for that channel and the last error condition(s) (i.e. E1HIGH or E2LOW and/or E2FAULT) will be set to ‘1’, the ALERT pin will be asserted, the consecutive alert counter will be cleared, and measurements will continue. When the ALERT pin is configured as a comparator, the consecutive alert counter will ignore diode fault and low limit errors and only increment if the measured temperature exceeds the High Limit. Additionally, once the consecutive alert counter reaches the programmed limit, the ALERT pin will be asserted, but the counter will not be reset. It will remain set until the temperature drops below the High Limit minus the Therm Hysteresis value. For example, if the CALRT[2:0] bits are set for 4 consecutive alerts on an EMC1188 device, the high limits are set at 70°C, and none of the channels are masked, the ALERT pin will be asserted after the following four measurements: 1. Internal Diode reads 71°C and both external diodes read 69°C. Consecutive alert counter for INT is incremented to 1. 2. Both the Internal Diode and External Diode1 read 71°C and External Diode 2 reads 68°C. Consecutive alert counter for INT is incremented to 2 and for EXT is set to 1. 3. The External Diode1 reads 71°C and both the Internal Diode and External Diode 2 read 69°C. Consecutive alert counter for INT and EXT2 are cleared and EXT1 is incremented to 2. 4. The Internal Diode reads 71°C and both external diodes read 71°C. Consecutive alert counter for INT is set to 1EXT2 is set to 1, and EXT is incremented to 3. 5. The Internal Diode reads 71°C and both the external diode read 71°C. Consecutive alert counter for INT is incremented to 2EXT2 is set to 2, and EXT is incremented to 4. The appropriate status bits are set for EXT and the ALERT pin is asserted. EXT counter is reset to 0 and all other counters hold the last value until the next temperature measurement. Bit 7 - TIMEOUT - Determines whether the SMBus Timeout function is enabled.  ‘0’ (default) - The SMBus Timeout feature is disabled. The SMCLK line can be held low indefinitely without the device resetting its SMBus protocol.  ‘1’ - The SMBus Timeout feature is enabled. If the SMCLK line is held low for more than tTIMEOUT, the device will reset the SMBus protocol. Bits 6-4 CTHRM[2:0] - Determines the number of consecutive measurements that must exceed the corresponding Therm Limit and Hardware Thermal Shutdown Limit before the SYS_SHDN pin is asserted. All temperature channels use this value to set the respective counters. The consecutive THERM counter is incremented whenever any of the measurements exceed the corresponding Therm Limit or if the External Diode 1 measurement exceeds the Hardware Thermal Shutdown Limit. If the temperature drops below the Therm Limit or Hardware Thermal Shutdown Limit, the counter is reset. If the programmed number of consecutive measurements exceed the Therm Limit or Hardware Thermal Shutdown Limit, and the appropriate channel is linked to the SYS_SHDN pin, the SYS_SHDN pin will be asserted low. Once the SYS_SHDN pin is asserted, the consecutive Therm counter will not reset until the corresponding temperature drops below the appropriate limit minus the corresponding hysteresis. The bits are decoded as shown in Table 6.15. The default setting is 4 consecutive out of limit conversions. Bits 3-1 - CALRT[2:0] - Determine the number of consecutive measurements that must have an out of limit condition or diode fault before the ALERT pin is asserted. temperature channels use this value to set the respective counters. The bits are decoded as shown in Table 6.15. The default setting is 1 consecutive out of limit conversion. SMSC EMC1188 37 DATASHEET Revision 1.0 (07-11-13) Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Table 6.15 Consecutive Alert / Therm Settings NUMBER OF CONSECUTIVE OUT OF LIMIT MEASUREMENTS 2 1 0 0 0 0 1 (default for CALRT[2:0]) 0 0 1 2 0 1 1 3 1 1 1 4 (default for CTHRM[2:0]) 6.14 Beta Configuration Register 26h Table 6.16 Beta Configuration Register ADDR. R/W REGISTER B7 B6 B5 B4 B3 26h R External Diode 2 Beta Configuration - - - - ENABLE2 B2 B1 B0 BETA2[2:0] DEFAULT 07h These registers are used to set the Beta Compensation factor that is used for External Diode 2. The ENABLE2 control is disabled for the EMC1188.  The BETA[2:0] bits will be automatically updated to indicate the current setting. Bit 2-0 - BETA[2:0] - These bits always reflect the current beta configuration settings. If auto-detection circuitry is enabled, these bits will be updated automatically and writing to these bits will have no effect. If the auto-detection circuitry is disabled, these bits will determine the beta configuration setting that is used for the respective channels.BETA2[2:0] is set to 111b and cannot be changed for the EMC1188. Care should be taken when setting the BETA[2:0] bits when the auto-detection circuitry is disabled. If the Beta Compensation factor is set at a beta value that is higher than the transistor beta, the circuit may introduce measurement errors. When measuring a discrete thermal diode (such as 2N3904) or a CPU diode that functions like a discrete thermal diode (such as an AMD processor diode), the BETA2:0] bits should be set to ‘111b’. Table 6.17 CPU Beta Values BETA[2:0] HEX ENABLE 2 1 0 0h 0 0 0 0 0.11 1h 0 0 0 1 0.18 2h 0 0 1 0 0.25 3h 0 0 1 1 0.33 Revision 1.0 (07-11-13) 38 DATASHEET MINIMUM BETA SMSC EMC1188 Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Table 6.17 CPU Beta Values (continued) BETA[2:0] HEX ENABLE 2 1 0 4h 0 1 0 0 0.43 5h 0 1 0 1 1.00 6h 0 1 1 0 2.33 7h 0 1 1 1 Disabled 8h - Fh 1 X X X Auto-detection 6.15 MINIMUM BETA External Diode Ideality Factor Register 27h Table 6.18 Ideality Configuration Registers ADDR. 27h 28h 31h R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT R/W External Diode Ideality Factor - - IDEALITY[5:0] 12h R/W External Diode 2 Ideality Factor - - IDEALITY2[5:0] 12h R/W External Diode 3 Ideality Factor - - IDEALITY3[5:0] 12h This register stores the ideality factors that are applied to the external diode. Table 6.19 defines each setting and the corresponding ideality factor. Beta Compensation and Resistance Error Correction automatically correct for most diode ideality errors; therefore, it is not recommended that these settings be updated without consulting SMSC. Table 6.19 Ideality Factor Look-Up Table (Diode Model) SETTING FACTOR SETTING FACTOR SETTING FACTOR 08h 0.9949 18h 1.0159 28h 1.0371 09h 0.9962 19h 1.0172 29h 1.0384 0Ah 0.9975 1Ah 1.0185 2Ah 1.0397 0Bh 0.9988 1Bh 1.0200 2Bh 1.0410 0Ch 1.0001 1Ch 1.0212 2Ch 1.0423 SMSC EMC1188 39 DATASHEET Revision 1.0 (07-11-13) Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Table 6.19 Ideality Factor Look-Up Table (Diode Model) (continued) SETTING FACTOR SETTING FACTOR SETTING FACTOR 0Dh 1.0014 1Dh 1.0226 2Dh 1.0436 0Eh 1.0027 1Eh 1.0239 2Eh 1.0449 0Fh 1.0040 1Fh 1.0253 2Fh 1.0462 10h 1.0053 20h 1.0267 30h 1.0475 11h 1.0066 21h 1.0280 31h 1.0488 12h 1.0080 22h 1.0293 32h 1.0501 13h 1.0093 23h 1.0306 33h 1.0514 14h 1.0106 24h 1.0319 34h 1.0527 15h 1.0119 25h 1.0332 35h 1.0540 16h 1.0133 26h 1.0345 36h 1.0553 17h 1.0146 27h 1.0358 37h 1.0566 For CPU substrate transistors that require the BJT transistor model, the ideality factor behaves slightly differently than for discrete diode-connected transistors. Refer to Table 6.20 when using a CPU substrate transistor. Table 6.20 Substrate Diode Ideality Factor Look-Up Table (BJT Model) SETTING FACTOR SETTING FACTOR SETTING FACTOR 08h 0.9869 18h 1.0079 28h 1.0291 09h 0.9882 19h 1.0092 29h 1.0304 0Ah 0.9895 1Ah 1.0105 2Ah 1.0317 0Bh 0.9908 1Bh 1.0120 2Bh 1.0330 0Ch 0.9921 1Ch 1.0132 2Ch 1.0343 0Dh 0.9934 1Dh 1.0146 2Dh 1.0356 0Eh 0.9947 1Eh 1.0159 2Eh 1.0369 0Fh 0.9960 1Fh 1.0173 2Fh 1.0382 10h 0.9973 20h 1.0187 30h 1.0395 11h 0.9986 21h 1.0200 31h 1.0408 12h 1.0000 22h 1.0213 32h 1.0421 13h 1.0013 23h 1.0226 33h 1.0434 14h 1.0026 24h 1.0239 34h 1.0447 15h 1.0039 25h 1.0252 35h 1.0460 Revision 1.0 (07-11-13) 40 DATASHEET SMSC EMC1188 Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Table 6.20 Substrate Diode Ideality Factor Look-Up Table (BJT Model) (continued) SETTING FACTOR SETTING FACTOR SETTING FACTOR 16h 1.0053 26h 1.0265 36h 1.0473 17h 1.0066 27h 1.0278 37h 1.0486 APPLICATION NOTE: When measuring a 65nm Intel CPU, the Ideality Setting should be the default 12h. When measuring a 45nm Intel CPU, the Ideality Setting should be 15h. 6.16 High Limit Status Register 35h Table 6.21 High Limit Status Register ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 35h R-C High Limit Status - - - - E3HIGH E2HIGH EHIGH IHIGH 00h The High Limit Status Register contains the status bits that are set when a temperature channel high limit is exceeded. If any of these bits are set, the HIGH status bit in the Status Register is set. Reading from the High Limit Status Register will clear all bits if. Reading from the register will also clear the HIGH status bit in the Status Register. The ALERT pin will be set if the programmed number of consecutive alert counts have been met and any of these status bits are set. The status bits will remain set until read unless the ALERT pin is configured as a comparator output (see Section 5.5.2). Bit 3 - E3HIGH - This bit is set when the External Diode 3 channel exceeds its programmed high limit. Bit 2 - E2HIGH - This bit is set when the External Diode 2 channel exceeds its programmed high limit. Bit 1 - E1HIGH - This bit is set when the External Diode 1 channel exceeds its programmed high limit. Bit 0 - IHIGH - This bit is set when the Internal Diode channel exceeds its programmed high limit. 6.17 Low Limit Status Register 36h Table 6.22 Low Limit Status Register ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 36h R-C Low Limit Status - - - - E3LOW E2LOW ELOW ILOW 00h The Low Limit Status Register contains the status bits that are set when a temperature channel drops below the low limit. If any of these bits are set, then the LOW status bit in the Status Register is set. Reading from the Low Limit Status Register will clear all bits. Reading from the register will also clear the LOW status bit in the Status Register. The ALERT pin will be set if the programmed number of consecutive alert counts have been met and any of these status bits are set. SMSC EMC1188 41 DATASHEET Revision 1.0 (07-11-13) Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet The status bits will remain set until read unless the ALERT pin is configured as a comparator output (see Section 5.5.2). Bit 3 - This bit is set when the External Diode 3 channel drops below its programmed low limit. Bit 2 - E2LOW - This bit is set when the External Diode 2 channel drops below its programmed low limit. Bit 1 - E1LOW - This bit is set when the External Diode 1 channel drops below its programmed low limit. Bit 0 - ILOW - This bit is set when the Internal Diode channel drops below its programmed low limit. 6.18 Therm Limit Status Register 37h Table 6.23 Therm Limit Status Register ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 37h R-C Therm Limit Status - - - - E3 THERM E2 THERM E1 THERM ITHERM 00h The Therm Limit Status Register contains the status bits that are set when a temperature channel Therm Limit is exceeded. If any of these bits are set, the THERM status bit in the Status Register is set. Reading from the Therm Limit Status Register will not clear the status bits. Once the temperature drops below the Therm Limit minus the Therm Hysteresis, the corresponding status bits will be automatically cleared. The THERM bit in the Status Register will be cleared when all individual channel THERM bits are cleared. Bit 3 - This bit is set when the External Diode 3 channel exceeds its programmed Therm Limit. When set, this bit will assert the THERM pin. Bit 2 - E2THERM - This bit is set when the External Diode 2 channel exceeds its programmed Therm Limit. When set, this bit will assert the THERM pin. Bit 1 - E1THERM - This bit is set when the External Diode 1 channel exceeds its programmed Therm Limit. When set, this bit will assert the THERM pin. Bit 0- ITHERM - This bit is set when the Internal Diode channel exceeds its programmed Therm Limit. When set, this bit will assert the THERM pin. 6.19 Filter Control Register 40h Table 6.24 Filter Configuration Register ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 40h R/W Filter Control - - - - - - B1 B0 DEFAULT FILTER[1:0] 00h The Filter Configuration Register controls the digital filter on the External Diode channel. Bits 1-0 - FILTER[1:0] - Control the level of digital filtering that is applied to the External Diode temperature measurement as shown in Table 6.25. See Figure 5.4 and Figure 5.5 for examples on the filter behavior. Revision 1.0 (07-11-13) 42 DATASHEET SMSC EMC1188 Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Table 6.25 FILTER Decode FILTER[1:0] 6.20 1 0 AVERAGING 0 0 Disabled (default) 0 1 Level 1 1 0 Level 1 1 1 Level 2 Product ID Register Table 6.26 Product ID Register ADDR R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT FDh R Product ID (EMC1188) 0 0 1 0 0 1 1 1 27h The Product ID Register holds a unique value that identifies the device. 6.21 SMSC ID Register Table 6.27 Manufacturer ID Register ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT FEh R SMSC ID 0 1 0 1 1 1 0 1 5Dh The Manufacturer ID register contains an 8-bit word that identifies the SMSC as the manufacturer of the EMC1188. 6.22 Revision Register Table 6.28 Revision Register ADDR. R/W REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT FFh R Revision 0 0 0 0 0 1 1 1 07h The Revision register contains an 8-bit word that identifies the die revision. SMSC EMC1188 43 DATASHEET Revision 1.0 (07-11-13) Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Chapter 7 Typical Operating Curves Tem perature Error vs. Am bient Tem perature (2N3904, TDIODE = 42.5°C, VDD = 3.3V) 1.0 1.0 0.8 0.8 0.6 Temperature Error (°C) Temperature Error (°C) Tem perature Error vs. Filter Capacitor (2N3904, TA = 27°C, TDIODE = 27°C, VDD = 3.3V) 0.5 0.3 0.0 -0.3 -0.5 -0.8 -1.0 0 1000 2000 3000 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 4000 -1.0 -40 -25 -10 Filter Capacitor (pF) Temperature Error (°C) Temperature Error (°C) Revision 1.0 (07-11-13) 5 4 Beta Compensation Disabled 3 2 1 0 Beta Compensation Enabled -1 20 110 125 95 110 125 Temperature Error vs. CPU Temperature Typical 65nm CPU from major vendor (TA = 27°C, VDD = 3.3V, BETA = 011, CFILTER = 470pF) Tem perature Error vs. External Diode Tem perature (2N3904, TA = 42.5°C, VDD = 3.3V) 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -40 -25 -10 5 20 35 50 65 80 95 External Diode Tem perature (°C) 5 20 35 50 65 80 Am bient Tem perature (°C) 40 60 80 100 120 CPU Temperature (°C) 44 DATASHEET SMSC EMC1188 Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Chapter 8 Package Information Figure 8.1 10-Pin DFN Package Drawing SMSC EMC1188 45 DATASHEET Revision 1.0 (07-11-13) Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet 8.1 Package Markings Figure 8.2 10-Pin DFN Package Dimensions Figure 8.3 10 Pin DFN PCB Footprint The EMC1188 devices will be marked as shown in Figure 8.4. Revision 1.0 (07-11-13) 46 DATASHEET SMSC EMC1188 Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet TOP LINE 1: Device code, first 2 of last 6 digits of lot number 4 3 L L LINE 2: Last 4 digits of lot number L L L L ex PIN 1 BOTTOM BOTTOM MARKING IS NOT ALLOWED Figure 8.4 EMC1188-1 10-Pin DFN Package Markings SMSC EMC1188 47 DATASHEET Revision 1.0 (07-11-13) Quad Channel 1°C Temperature Sensor with Hardware Thermal Shutdown and 1.8V SMBus Communications Datasheet Chapter 9 Datasheet Revision History Table 9.1 Customer Revision History REVISION LEVEL & DATE Rev. 1.0 (07-11-13) Revision 1.0 (07-11-13) SECTION/FIGURE/ENTRY CORRECTION Formal document release 48 DATASHEET SMSC EMC1188