HV2301PJ-G

Supertex inc. HV2301 Low Charge Injection, 8-Channel, High Voltage, Enhanced Analog Switch with Bleed Resistors Features ►► ►► ►► ►► ►► ►► ►► ►► ►► ►► ►► ►► ►► General Description HVCMOS technology for high performance Integrated bleed resistors on the outputs 8 Channels of high voltage analog switch 3.3 or 5.0V CMOS input logic level 20MHz data shift clock frequency Very low quiescent power dissipation (-10µA) Low parasitic capacitance DC to 50MHz analog signal frequency -60dB typical off-isolation at 5MHz CMOS logic circuitry for low power Excellent noise immunity Cascadable serial data register with latches Flexible operating supply voltages The Supertex HV2301 is a low charge injection, 8-channel, high voltage analog switch integrated circuit (IC) with bleed resistors. The device can be used in applications requiring high voltage switching, controlled by low voltage control signals, such as medical ultrasound imaging, piezoelectric transducer driver, and printers. The built-in bleed resistors eliminate voltage built up on capacitive loads such as piezoelectric transducers. The HV2301 is an enhanced version of the HV232. Input data is shifted into an 8-bit shift register that can then be retained in an 8-bit latch. To reduce any possible clock feedthrough noise, the latch enable bar should be left high until all bits are clocked in. Data is clocked in during the rising edge of the clock. Using HVCMOS technology, this device combines high voltage bilateral DMOS switches and low power CMOS logic to provide efficient control of high voltage analog signals. Applications ►► ►► ►► ►► ►► Medical ultrasound imaging NDT metal flaw detection Piezoelectric transducer drivers Inkjet printer heads Optical MEMS modules The device is suitable for various combinations of high voltage supplies, e.g., VPP/VNN: +40V/-160V, +100V/-100V, and +160V/40V. Block Diagram Latches CLK DIN 8-Bit Shift Register DOUT VDD GND Supertex inc. LE CLR Level Shifters Output Switches D LE CL SW0 D LE CL SW1 D LE CL SW2 D LE CL SW6 D LE CL SW7 VNN VPP RGND ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com HV2301 Ordering Information Package Options 48-Lead LQFP Device 28-Lead PLCC 7.00x7.00mm body 1.60mm height (max) 0.50mm pitch .453x.453in body .180in height (max) .050in pitch HV2301FG-G HV2301PJ-G HV2301 -G indicates the part is RoHS compliant (Green) Absolute Maximum Ratings Pin Configuration Parameter Value VDD logic supply 48 -0.5V to +7V VPP -VNN differential supply 220V VPP positive supply -0.5V to VNN+200V VNN negative supply +0.5V to -200V Logic input voltage 48-Lead LQFP (FG) (top view) -0.5V to VDD +0.3V Analog signal range 4 VNN to VPP Peak analog signal current/channel Storage temperature 1 28 26 3.0A -65°C to 150°C Power dissipation: 48-Lead LQFP 28-Lead PLCC 1.0W 1.2W Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Operating Conditions 28-Lead PLCC (PJ) (top view) Product Marking Top Marking YYWW HV2301FG LLLLLLLLL Sym Parameter Value VDD Logic power supply voltage 3.0V to 5.5V VPP Positive high voltage supply 40V to VNN +200V VNN Negative high voltage supply VIH High level input voltage 0.9VDD to VDD VIL Low-level input voltage 0V to 0.1VDD VSIG Analog signal voltage peak-to-peak TA 1 -40V to -160V VNN +10V to VPP -10V Operating free air temperature 0 C to 70 C O O Notes: 1. Power up/down sequence is arbtrary except GND must be powered-up first and powered down last. 2. VSIG must be VNN ≤ VSIG ≤ VPP or floating during power up/down transition. 3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec. Bottom Marking CCCCCCCC AAA YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking Package may or may not include the following marks: Si or 48-Lead LQFP (FG) Top Marking YYWW AAA HV2301PJ LLLLLLLLLL Bottom Marking CCCCCCCCCCC YY = Year Sealed WW = Week Sealed L = Lot Number A = Assembler ID C = Country of Origin* = “Green” Packaging *May be part of top marking Package may or may not include the following marks: Si or 28-Lead PLCC (PJ) Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 2 HV2301 DC Electrical Characteristics (Over operating conditions unless otherwise specified ) Sym RONS 0OC Parameter Small signal switch on-resistance +25OC +70OC Units Conditions Min Max Min Typ Max Min Max - 30 - 26 38 - 48 ISIG = 5.0mA - 25 - 22 27 - 32 ISIG = 200mA - 25 - 22 27 - 30 - 18 - 18 24 - 27 - 23 - 20 25 - 30 ISIG = 5.0mA - 22 - 16 25 - 27 ISIG = 200mA Ω ISIG = 5.0mA ISIG = 200mA VPP = +40V VNN = -160V VPP = +100V VNN = -100V VPP = +160V VNN = -40V ΔRONS Small signal switch on-resistance matching - 20 - 5.0 20 - 20 % ISIG = 5.0mA, VPP = +100V, VNN = - 100V RONL Large signal switch on-resistance - - - 15 - - - Ω VSIG = VPP -10V, ISIG = 1.0A RINT Value of output bleed resistance - - 20 35 50 - - KΩ Output switch to RGND IRINT = 0.5mA ISOL Switch off leakage per switch - 5.0 - 1.0 10 - 15 μA VSIG = VPP -10V, VNN +10V DC offset switch off - 300 - 100 300 - 300 mV DC offset switch on - 500 - 100 500 - 500 mV IPPQ Quiescent VPP supply current - - - 10 50 - - μA All switches off INNQ Quiescent VNN supply current - - - -10 -50 - - μA All switches off IPPQ Quiescent VPP supply current - - - 10 50 - - μA All switches on, ISW = 5.0mA INNQ Quiescent VNN supply current - - - -10 -50 - - μA All switches on, ISW = 5.0mA ISW Switch output peak current - 3.0 - 3.0 2.0 - 2.0 A VSIG duty cycly < 0.1% fSW Output switching frequency - - - - 50 - - kHz - 4.0 - - 5.0 - 5.5 - 3.5 - - 3.5 - 3.5 - 3.5 - - 3.5 - 4.0 VPP = +160V VNN = -40V - 4.5 - - 5.0 - 5.5 VPP = +40V VNN = -160V - 3.5 - - 3.5 - 3.5 - 3.5 - - 3.5 - 4.0 VOS IPP INN Average VPP supply current Average VNN supply curent No load Duty cycle = 50% VPP = +40V VNN = -160V mA mA VPP = +100V VNN = -100V VPP = +100V VNN = -100V VPP = +160V VNN = -40V All output switches are turning on and off at 50kHz with no load All output switches are turning on and off at 50kHz with no load IDD Average VDD supply current - 4.0 - - 4.0 - 4.0 mA fCLK = 5.0MHz, VDD = 5.0V IDDQ Quiescent VDD supply current - 10 - - 10 - 10 μA All logic inputs are static ISOR Data out source current 0.45 - 0.45 0.70 - 0.40 - mA VOUT = VDD -0.7V ISINK Data out sink current 0.45 - 0.45 0.70 - 0.40 - mA VOUT = 0.7V CIN Logic input capacitance - 10 - - 10 - 10 pF --- Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 3 HV2301 AC Electrical Characteristics (Over recommended operating conditions: VDD = 5.0V, tR = tF ≤5ns, 50% duty cycle, CLOAD = 20pF unless otherwise specified) Sym 0OC Parameter tSD Set up time before LE rises tWLE Time width of LE tDO Clock delay time to data out tWCL Time width of CL tSU Set up time data to clock tH Hold time data from clock +25OC +70OC Units Conditions Min Max Min Typ Max Min Max 25 - 25 - - 25 - 56 - - 56 - 56 - 12 - - 12 - 12 - - 120 - 95 140 - 167 - 58 - 40 69 - 85 55 - 55 30 - 55 - 39 - 47 30 - 58 - 16 - 21 10 - 26 - 2 - 2 - - 2 - - - - - 8.0 - - - 20 - - 20 - 20 - 50 - 50 ns --- ns ns ns ns ns ns VDD = 3.0V VDD = 5.0V VDD = 3.0V VDD = 5.0V --VDD = 3.0V VDD = 5.0V VDD = 3.0 or 5.0V VDD = 3.0V fCLK Clock frequency tR, tF Clock rise and fall times - 50 tON Turn on time - 5.0 - - 5.0 - 5.0 μs VSIG = VPP -10V, RLOAD = 10kΩ tOFF Turn off time - 5.0 - - 5.0 - 5.0 μs VSIG = VPP -10V, RLOAD = 10kΩ - 20 - - 20 - 20 - 20 - - 20 - 20 - 20 - - 20 - 20 -30 - -30 -33 - -30 - -58 - -58 - - -58 - -60 - -60 -70 - -60 - dB f = 5.0MHz, 50Ω load - 300 - - 300 - 300 mA 300ns pulse width, 2.0% duty cycle CSG(OFF) Off capacitance SW to GND 5.0 17 5.0 12 17 5.0 17 pF 0V, f = 1.0MHz CSG(ON) 25 50 25 38 50 25 50 pF 0V, f = 1.0MHz +VSPK - - - - 150 - - -VSPK - - - - 150 - - - - - - 150 - - - - - - 150 - - +VSPK - - - - 150 - - -VSPK - - - - 150 - - - - - 820 - - - - - - 600 - - - - - - 350 - - - dv/dt Maximun VSIG slew rate KO Off isolation KCR Switch crosstalk IID +VSPK -VSPK QC Output switch isolation diode current On capacitance SW to GND Output voltage spike Charge injection Supertex inc. MHz --- VDD = 5.0V VPP = +40V, VNN = -160V V/ns VPP = +100V, VNN = -100V VPP = +160V, VNN = -40V dB f = 5.0MHz, 1kΩ/15pF load f = 5.0MHz, 50Ω load VPP = +40V, VNN = -160V, RLOAD = 50Ω mV VPP = +100V, VNN = -100V, RLOAD = 50Ω VPP = +160V, VNN = -40V, RLOAD = 50Ω VPP = +40V, VNN = -160V, VSIG = 0V pC VPP = +100V, VNN = -100V, VSIG = 0V VPP = +160V, VNN = -40V, VSIG = 0V ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 4 HV2301 Truth Table D0 D1 D2 D3 D4 D5 D6 D7 LE CLR SW0 SW1 SW2 SW3 SW4 SW5 SW6 L L L Off H L L On L L L Off H L L On L L L Off H L L On L L L Off H L L On L L L Off H L L On L L L Off H L L On L L L Off H L L On SW7 L L L Off H L L On X X X X X X X X H L Hold Previous State X X X X X X X X X H All Switches Off Notes: 1. The eight switches operate independently. 2. Serial data is clocked in on the L to H transition of the CLK. 3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flow through the latch. 4. DOUT is high when data in the shift register 7 is high. 5. Shift register clocking has no effect on the switch states if LE is high. 6. The CLR clear input overrides all other inputs. Typical Waveforms DN DN+1 DATA IN 50% LE 50% DN-1 50% 50% tWLE tSD 50% CLOCK tSU 50% th tDO DATA OUT 50% tON tOFF VOUT (typ) OFF 90% 10% ON CLR 50% Supertex inc. tWCL 50% ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 5 HV2301 Test Circuits VPP - 10V ISOL VPP - 10V RL VOUT VOUT Open Open 10kΩ RGND RGND RGND VPP VPP VDD VNN VNN GND 5V VPP VNN Switch OFF Leakage VDD VPP 5V VNN GND VNN VPP VDD VNN GND 5V TON/TOFF Test Circuit DC Offset ON/OFF VIN = 10VP–P @5.0MHz VPP VIN = 10VP–P @5.0MHz VSIG IID VOUT RL 50Ω NC VNN 50Ω RGND VPP VDD VPP VNN 5V VPP VNN GND VNN KO = 20Log RGND RGND VOUT VIN VPP 5V VDD VNN GND VPP VPP VDD VNN VNN GND KCR = 20Log Isolation Diode Current OFF Isolation VOUT VIN Crosstalk +VSPK ∆VOUT VOUT VOUT –VSPK 1000pF RL 50Ω RGND VSIG 1kΩ RGND VPP VPP VDD VNN VNN GND 5V VPP VPP VDD VNN VNN GND 5V Q = 1000pF x ∆VOUT Charge Injection Supertex inc. Output Voltage Spike ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 6 5V HV2301 Pin Configuration 48-Lead LQFP (FG) Pin Configuration 28-Lead PLCC (PJ) Pin # Pin Name Pin # Pin Name Pin # Pin Name Pin # Pin Name 1 SW5 25 VNN 1 SW3 15 NC 2 NC 26 NC 2 SW3 16 DIN 3 SW4 27 RGND 3 SW2 17 CLK 4 NC 28 GND 4 SW2 18 LE 5 SW4 29 VDD 5 SW1 19 CLR 6 NC 30 NC 6 SW1 20 DOUT 7 NC 31 NC 7 SW0 21 SW7 8 SW3 32 NC 8 SW0 22 SW7 9 NC 33 DIN 9 NC 23 SW6 10 SW3 34 CLK 10 VPP 24 SW6 11 NC 35 LE 11 RGND 25 SW5 12 SW2 36 CLR 12 VNN 26 SW5 13 NC 37 DOUT 13 GND 27 SW4 14 SW2 38 NC 14 VDD 28 SW4 15 NC 39 SW7 16 SW1 40 NC 17 NC 41 SW7 18 SW1 42 NC 19 NC 43 SW6 20 SW0 44 NC 21 NC 45 SW6 22 SW0 46 NC 23 NC 47 SW5 24 VPP 48 NC Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 7 HV2301 48-Lead LQFP Package Outline (FG) 7.00x7.00mm body, 1.60mm height (max), 0.50mm pitch D D1 E E1 Note 1 (Index Area D1/4 x E1/4) 48 1 e b Top View L2 View B A A2 L Seating Plane Side View A1 θ L1 Gauge Plane Seating Plane View B Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol MIN Dimension NOM (mm) MAX A A1 A2 b D D1 E E1 1.40* 0.05 1.35 0.17 8.80* 6.80* 8.80* 6.80* - - 1.40 0.22 9.00 7.00 9.00 7.00 1.60 0.15 1.45 0.27 9.20* 7.20* 9.20* 7.20* e 0.50 BSC L 0.45 0.60 0.75 L1 1.00 REF JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-48LQFPFG Version, D041309. Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 8 L2 0.25 BSC θ 0O 3.5O 7O HV2301 28-Lead PLCC Package Outline (PJ) .453x.453in. body, .180in. height (max), .050in. pitch .048/.042 x 45O D D1 1 4 26 28 .150 MAX .056/.042 x 45O Note 1 (Index Area) .075 MAX E1 E Note 2 .020max (3 Places) Top View Vertical Side View View A b1 A Base .020 MIN Plane A1 A2 Seating Plane e b Horizontal Side View R View A Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Actual shape of this feature may vary. Symbol Dimension (inches) A A1 A2 b b1 D D1 E E1 MIN .165 .090 .062 .013 .026 .485 .450 .485 .450 NOM .172 .105 - - - .490 .453 .490 .453 MAX .180 .120 .083 .021 .032 .495 .456 .495 .456 e .050 BSC R .025 .035 .045 JEDEC Registration MS-018, Variation AB, Issue A, June, 1993. Drawings not to scale. Supertex Doc. #: DSPD-28PLCCPJ, Version B031111. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2011 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP - HV2301 A040811 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com 9