HV2662LA-G

HV2662/HV2762 Low Harmonic Distortion, 24-Channel SPST High-Voltage Analog Switch Features General Description • • • • • • • • • • • • • • HV2662/HV2762 are low-charge injection, low harmonic distortion, 24-channel, high-voltage analog switch integrated circuits (ICs). These ICs excel in applications requiring high-voltage switching controlled by low-voltage control signals, such as medical ultrasound imaging, piezoelectric transducer driver, and printers. HV2762 provides integrated bleed resistors that eliminate voltage build-up on capacitive loads such as piezoelectric transducers. HV2662 does not have integrated bleed resistors. 24-Channel of High-Voltage Analog Switch 3.3V or 5.0V CMOS Input Logic Level 24-Channel SPST Configuration 20 MHz Data Shift Clock Frequency HVCMOS Technology for High Performance Very Low Quiescent Power Dissipation (~10 µA) Low Parasitic Capacitance DC to 50 MHz Analog Signal Frequency -60 dB Typical OFF-Isolation at 5.0 MHz CMOS Logic Circuitry for Low Power Excellent Noise Immunity Cascadable Serial Data Register with Latches Flexible Operating Supply Voltages Integrated Bleed Resistors on Outputs (HV2762 HV2662/HV2762 shift input data into a 24-bit shift register that can then be retained in a 24-bit latch. To reduce any possible clock feed through noise, the latch-enable bar should be left high until all bits are clocked in during the rising edge of the clock. Using High-Voltage CMOS technology, these ICs combine high-voltage, bilateral DMOS switches and low-power CMOS logic to provide efficient control of high voltage analog signals. Only) Applications • • • • Medical Ultrasound Imaging Piezoelectric Transducer Drivers Inkjet Printer Heads Optical MEMS Modules The device is suitable for various combinations of high voltage supplies, e.g., VPP/VNN: +40V/-160V, +100V/100V, and +160V/-40V. Package Types 1 2 3 4 5 6 7 8 9 10 A B C D E Top View F G H J K See Table 2-1 for pin information.  2016-2020 Microchip Technology Inc. 64-ball VFBGA DS20005372B-page 1 HV2662/HV2762 Functional Block Diagram Latches CLK DIN 24-Bit Shift Register DOUT VDD Note: GND LE CLR Level Output Shifters Switches D LE CLR SW0 D LE CLR SW1 D LE CLR SW2 D LE CLR SW22 D LE CLR SW23 VPP VNN RGND Bleed resistors and RGND only apply to HV2762. DS20005372B-page 2  2016-2020 Microchip Technology Inc. HV2662/HV2762 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† VDD Logic Supply ............................................................................................................................................................. -0.50 to +6.5V VPP - VNN Differential Supply ......................................................................................................................................................... 220V VPP Positive Supply ..................................................................................................................................................-0.5 to VNN + 200V VNN Negative Supply ........................................................................................................................................................ +0.5 to -200V Logic Input Voltage .................................................................................................................................................. -0.5V to VDD +0.3V Analog Signal Range ............................................................................................................................................................ VNN to VPP Peak Analog Signal Current/Channel ............................................................................................................................................. 2.0A Storage Temperature ................................................................................................................................................... -65°C to +150°C Power Dissipation .......................................................................................................................................................................... 1.0W † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (1,2,3) Symbol Parameter Value VDD Logic Power Supply Voltage 3.0V to 5.5V (2) VPP Positive High-Voltage Supply VNN Negative High-Voltage Supply -40V to -160V (2) VIH High-Level Input Voltage 0.9VDD to VDD VIL Low-Level Input Voltage VSIG TA +40V to VNN +200V (2) 0V to 0.1 VDD Analog Signal Voltage Peak-to-Peak VNN +10V to VPP -10V (3) Operating Free Air Temperature 0°C to +70°C Note 1: Power-up/down sequence is arbitrary except GND must be powered-up first and powered-down last. 2: Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0 msec. 3: VSIG must be VNN ≤ VSIG ≤ VPP or floating during power-up/down transition. DC ELECTRICAL CHARACTERISTICS Electrical Specifications: Over recommended operating conditions unless otherwise specified. See test circuits in Figure 3-2. Parameter Small Signal Switch ON-Resistance Symbol 0°C +25°C Min. Max. Min. RONS Typ. +70°C Max. Min. Max. Units Conditions — — — 26 — — — — — — 22 — — — ISIG = 5.0 mA VPP = +40V, I 200 mA VNN = -160V — — — 22 — — — ISIG = 5.0 mA — — — 18 — — — — — — 20 — — — — — — 16 — — — SIG = Ω VPP = +100V, ISIG = 200 mA VNN = -100V ISIG = 5.0 mA VPP = +160V, I = 200 mA VNN = -40V SIG Small Signal Switch ΔRONS ON-Resistance Matching — 20 — 5.0 20 — 20 % ISIG = 5.0 mA, VPP = +100V, VNN = -100V Large Signal Switch ON-Resistance — — — 30 — — — Ω VSIG = VPP -10V, ISIG = 1A (Note 1) RONL Note 1: Specification is obtained by characterization and is not 100% tested. 2: Design guidance only.  2016-2020 Microchip Technology Inc. DS20005372B-page 3 HV2662/HV2762 DC ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Over recommended operating conditions unless otherwise specified. See test circuits in Figure 3-2. Parameter Symbol 0°C +25°C Min. Max. Min. Typ. +70°C Max. Min. Max. Units Conditions Output-Switch Shunt Resistance (HV2762 Only) RINT — — 20 35 50 — — KΩ Output Switch to RGND, IRINT = 0.5 mA Switch OFF-Leakage per Switch ISOL — 5.0 — 1.0 10 — 15 μA VSIG = VPP -10V, VNN +10V DC Offset Switch OFF VOS — 300 — 100 300 — 300 mV — 500 — 100 500 — 500 No load for HV2762. RLOAD = 100 KΩ for HV2662 μA All switches OFF μA All switches ON, ISW = 5.0 mA VSIG duty cycle < 0.1% (Note 1) DC Offset Switch ON Quiescent VPP Supply Current IPPQ — — — 10 50 — — Quiescent VNN Supply Current INNQ — — — -10 -50 — — Quiescent VPP Supply Current IPPQ — — — 10 50 — — Quiescent VNN Supply Current INNQ — — — -10 -50 — — Switch Output Peak Current ISW — — — 2.0 1.3 — — A Output Switching Frequency fSW — — — — 50 — — kHz — 4.0 — — 4.5 — 5.0 — 4.0 — — 4.5 — 5.0 — 4.0 — — 4.5 — 5.0 VPP= +160V, VNN = -40V — 4.0 — — 4.5 — 5.0 VPP = +40V, VNN = -160V — 4.0 — — 4.5 — 5.0 — 4.0 — — 4.5 — 5.0 Average VPP Supply Current Average VNN Supply Current IPP INN Duty cycle = 50% (Note 1) VPP= +40V, VNN = -160V mA mA VPP= +100V, VNN = -100V VPP= +100V, VNN = -100V VPP= +160V, VNN = -40V All output switches are turning ON and OFF at 50 kHz with no load. All output switches are turning ON and OFF at 50 kHz with no load. Average VDD Supply Current IDD — 8.0 — — 8.0 — 8.0 mA fCLK = 5.0 MHz, VDD = 5.0V Quiescent VDD Supply Current IDDQ — 10 — — 10 — 10 μA All logic inputs are static Data Out Source Current ISOR 0.45 — 0.45 0.70 — 0.40 — mA VOUT = VDD -0.7V Data Out Sink Current ISINK 0.45 — 0.45 0.70 — 0.40 — mA VOUT = 0.7V Logic Input Capacitance CIN — 10 — — 10 — 10 pF (Note 2) Note 1: Specification is obtained by characterization and is not 100% tested. 2: Design guidance only. DS20005372B-page 4  2016-2020 Microchip Technology Inc. HV2662/HV2762 AC ELECTRICAL CHARACTERISTICS Electrical Specifications: Over recommended operating conditions unless otherwise specified. See test circuits in Figure 3-2. Parameter Symbol Setup Time Before LE Rises tSD Min. Typ. Max. Min. Max. 25 — 25 — — 25 — 56 12 9.0 8.0 55 21 7.0 5.0 5.0 — — — — 40 30 — — — — — 8 20 56 12 9.0 8.0 55 21 7.0 5.0 5.0 — — — — — — — — — — — — — — — 40 30 — — — — — 8 20 56 12 9.0 8.0 55 21 7.0 5.0 5.0 — — — — 40 30 — — — — — 8 20 tR, tF — 50 — — 50 — 50 tON tOFF — — — 5.0 5.0 20 — — — — — — 5.0 5.0 20 — — — 5.0 5.0 20 — 20 — — 20 — 20 — 20 — — 20 — 20 -30 — -30 -33 — -30 — -58 — -58 -60 — -58 — Clock Delay Time to Data Out tDO Clock Frequency Clock Rise and Fall Times Turn ON Time Turn OFF Time Maximum VSIG Slew Rate 70°C Max. tWLE Hold Time Data from Clock 25°C Min. Time Width of LE Time Width of CLR Setup Time Data to Clock 0°C tWCLR tSU tH fCLK dv/dt OFF Isolation KO Switch Crosstalk KCR -60 — -60 -70 — -60 — IID — 300 — — 300 — 300 CSG(OFF) — 14 — 9.0 14 — 14 CSG(ON) — 17 — 12 17 — 17 Output Switch Isolation Diode Current OFF Capacitance SW to GND ON Capacitance SW to GND — — — — 150 — — +VSPK -VSPK — — — — 150 — — +VSPK — — — — 150 — — Output Voltage Spike (per Switch) -VSPK — — — — 150 — — +VSPK — — — — 150 — — -VSPK — — — — 150 — — Note 1: Specification is obtained by characterization and is not 100% tested.  2016-2020 Microchip Technology Inc. Units ns Conditions (Note 1) VDD = 3.0V (Note 1) VDD = 5.0V (Note 1) VDD = 3.0V (Note 1) ns VDD = 5.0V (Note 1) ns (Note 1) VDD = 3.0V (Note 1) ns VDD = 5.0V (Note 1) VDD = 3.0V (Note 1) ns VDD = 5.0V (Note 1) VDD = 3.0V MHz VDD = 5.0V (Note 1) ns ns (Note 1) μs VSIG = VPP -10V, RLOAD = 10 kΩ VPP = +40V, VNN = -160V (Note 1) VPP = +100V, VNN = -100V V/ns (Note 1) VPP = +160V, VNN = -40V (Note 1) f = 5.0 MHz, 1.0 KΩ//15 pF load (Note 1) dB f = 5.0 MHz, 50Ω load (Note 1) f = 5.0 MHz, 50Ω load dB (Note 1) mA 300 ns pulse width, 2.0% duty cycle (Note 1) pF VSIG = 0V, f = 1.0 MHz (Note 1) VPP = +40V, VNN = -160V RLOAD = 50Ω (Note 1) mV VPP = +100V, VNN = -100V RLOAD = 50Ω (Note 1) VPP = +160V, VNN = -40V RLOAD = 50Ω (Note 1) DS20005372B-page 5 HV2662/HV2762 AC ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Over recommended operating conditions unless otherwise specified. See test circuits in Figure 3-2. Parameter Charge Injection (per Switch) Symbol QC 0°C 25°C 70°C Min. Max. Min. Typ. Max. Min. Max. — — — 820 — — — — — — 600 — — — — — — 350 — — — Units Conditions pC VPP = +40V, VNN = -160V (Note 1) VPP = +100V, VNN = -100V (Note 1) VPP = +160V, VNN = -40V (Note 1) Note 1: Specification is obtained by characterization and is not 100% tested. TEMPERATURE SPECIFICATIONS Electrical Specifications: Unless otherwise specified, for all specifications TA =TJ = +25°C Parameter Symbol Min Typ Max Units TA -65 — +150 °C θja — 36 — °C/W Conditions Temperature Ranges Storage Temperature Package Thermal Resistances Thermal Resistance, 64-Ball VFBGA DS20005372B-page 6  2016-2020 Microchip Technology Inc. HV2662/HV2762 2.0 PIN DESCRIPTION The locations of the balls are listed in Package Types. TABLE 2-1: BALL DESCRIPTION 64-BALL VFBGA Pin # HV2662 HV2762 Description A1 SW22B SW22B Analog switch 22 terminal B A2 VNN VNN A3 SW21B SW21B Analog switch 21 terminal B A4 SW20B SW20B Analog switch 20 terminal B A5 SW19B SW19B Analog switch 19 terminal B A6 SW18B SW18B Analog switch 18 terminal B A7 SW17B SW17B Analog switch 17 terminal B A8 SW16B SW16B Analog switch 16 terminal B A9 SW15B SW15B Analog switch 15 terminal B A10 SW15A SW15A Analog switch 15 terminal A B1 SW23B SW23B Analog switch 23 terminal B B2 SW23A SW23A Analog switch 23 terminal A B3 SW22A SW22A Analog switch 22 terminal A B4 SW21A SW21A Analog switch 21 terminal A B5 SW20A SW20A Analog switch 20 terminal A B6 SW19A SW19A Analog switch 19 terminal A B7 SW18A SW18A Analog switch 18 terminal A B8 SW17A SW17A Analog switch 17 terminal A B9 SW16A SW16A Analog switch 16 terminal A B10 SW14B SW14B C1 NC NC No connect C2 VPP VPP Positive supply voltage Negative supply voltage Analog switch 14 terminal B C9 SW14A SW14A Analog switch 14 terminal A C10 SW13B SW13B Analog switch 13 terminal B D1 CLR CLR D2 NC RGND D9 VNN VNN D10 SW13A SW13A Latch clear logic input No connect/Ground for bleed resistor Negative supply voltage Analog switch 13 terminal A E1 LE LE E2 CLK CLK E9 SW12B SW12B E10 SW12A SW12A F1 VDD VDD Logic supply voltage F2 GND GND Ground F9 SW11B SW11B F10 SW11A SW11A G1 DIN DIN G2 DOUT DOUT G9 SW10B SW10B G10 VNN VNN H1 NC RGND VPP VPP H2  2016-2020 Microchip Technology Inc. Latch-enable logic input, low active Clock logic input for shift register Analog switch 12 terminal B Analog switch 12 terminal A Analog switch 11 terminal B Analog switch 11 terminal A Data-in logic input Data-out logic output Analog switch 10 terminal B Negative supply voltage No connect/ Ground for bleed resistor Positive supply voltage DS20005372B-page 7 HV2662/HV2762 TABLE 2-1: BALL DESCRIPTION 64-BALL VFBGA (CONTINUED) Pin # HV2662 HV2762 Description H9 SW10A SW10A Analog switch 10 terminal A H10 SW9B SW9B Analog switch 9 terminal B J1 SW0A SW0A Analog switch 0 terminal A J2 SW0B SW0B Analog switch 0 terminal B J3 SW1B SW1B Analog switch 1 terminal B J4 SW2B SW2B Analog switch 2 terminal B J5 SW3B SW3B Analog switch 3 terminal B J6 SW4B SW4B Analog switch 4 terminal B J7 SW5B SW5B Analog switch 5 terminal B J8 SW6B SW6B Analog switch 6 terminal B J9 SW7B SW7B Analog switch 7 terminal B J10 SW9A SW9A Analog switch 9 terminal A K1 SW1A SW1A Analog switch 1 terminal A K2 VNN VNN K3 SW2A SW2A Analog switch 2 terminal A K4 SW3A SW3A Analog switch 3 terminal A K5 SW4A SW4A Analog switch 4 terminal A K6 SW5A SW5A Analog switch 5 terminal A K7 SW6A SW6A Analog switch 6 terminal A K8 SW7A SW7A Analog switch 7 terminal A K9 SW8A SW8A Analog switch 8 terminal A K10 SW8B SW8B Analog switch 8 terminal B DS20005372B-page 8 Negative supply voltage  2016-2020 Microchip Technology Inc. HV2662/HV2762 3.0 FUNCTIONAL DESCRIPTION DN - 1 DN DN + 1 DATA IN DIN 5 0% LE 50% 50% 50% tWLE tSD 50% CLOCK 50% th tSU tDO DATA OUT DOUT VOUT 50% tON tOFF OFF 90% (typ) 1 0% ON CLR 5 0% 5 0% tWCL FIGURE 3-1: TABLE 3-1: D0 1 D1 L H — — — — — — — — — — L H — — — — — — — — — — — — X X — — — — — — X X Logic Timing Waveforms. TRUTH TABLE ... ... X X D15 D16 — — — — — — L H — — — — — — — — — — L H — — — — — — X X — — — — — — X X ... ... X X CLR4 SW05,6 D232 LE3 — — — — — — — — — — L L L L L L L L L L L L L L L L L L L L OFF ON — — — — — — — — — — — — L H X X L L L L L L H X L L L L L L L H — — — — — — SW1 — — OFF ON — — — — — — ... ... SW15 SW16 — — — — — — OFF ON — — — — — — — — — — OFF ON — — — — — — — — — — — — — — — — — — HOLD PREVIOUS STATE ALL SWITCHES OFF ... ... SW23 — — — — — — — — — — — — — — OFF ON Note 1: Serial data is clocked in on the L to H transition of the CLK. 2: DOUT is high when data in the register 23 is high. 3: Shift registers clocking has no effect on the switch states if LE is high. 4: The CLR clear input overrides all other inputs. 5: The 24 switches operate independently. 6: All 24 switches go to a state retaining their latched condition at the rising edge of LE. When LE is low, the shift registers data flow through the latch.  2016-2020 Microchip Technology Inc. DS20005372B-page 9 HV2662/HV2762 3.1 Application Information VPP -10V ISOL VPP -10V 10kΩ RLOAD VOUT VOUT Open Open RGND RGND RGND VPP VPP VDD VNN VNN GND 5V VPP VPP VDD VNN VNN GND Switch Off Leakage per Switch 5V VPP VDD VNN VNN GND 5V TON/TOFF Test Circuit DC Offset Switch ON/OFF VIN =10VPP @5.0MHz VIN =10VPP @5.0MHz VSIG IID VOUT VNN RLOAD VPP VPP VDD VNN VNN GND KO = 20Log 5V NC 50Ω RGND RGND 50Ω RGND VPP VPP VDD VNN VNN GND 5V VPP VPP VDD VNN VNN GND VOUT VIN KCR = 20Log Output Switch Isolation Diode Current OFF Isolation 5V VOUT VIN Switch Crosstalk +VSPK ΔVOUT VOUT VOUT –VSPK 1000pF VSIG RGND RLOAD 50Ω RGND 1kΩ VPP VPP VDD VNN VNN GND Q = 1000pF x ΔVOUT Charge Injection Note: VPP 5V VPP VPP VDD VNN VNN GND 5V Output Voltage Spike RGND only applies to HV2762. FIGURE 3-2: DS20005372B-page 10 Test Circuits.  2016-2020 Microchip Technology Inc. HV2662/HV2762 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 64-Ball VFBGA XXXXXXXXX XXXXXXXXX XXXXXXX e3 YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: Example HV2662 GA e3 15 03343 Product Code or Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator (e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for product code or customer-specific information. Package may or not include the corporate logo.  2016-2020 Microchip Technology Inc. DS20005372B-page 11 HV2662/HV2762 64-Ball Very Thin Fine Pitch Ball Grid Array (GA) - 7x7x1.0 mm Body [VFBGA] Supertex Legacy Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A D/4 B E/4 E 0.10 C 2X 0.10 C TOP VIEW A3 A SEATING PLANE C SIDE VIEW SEE DETAIL B D1 e e/2 E1 DETAIL A BOTTOM VIEW Microchip Technology Drawing C04-370-GA Rev A Sheet 1 of 2 DS20005372B-page 12  2016-2020 Microchip Technology Inc. HV2662/HV2762 64-Ball Very Thin Fine Pitch Ball Grid Array (GA) - 7x7x1.0 mm Body [VFBGA] Supertex Legacy Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging NX Øb Ø0.15 Ø0.05 C A B C SOLDER BALL DETAIL A 0.10 C 0.08 C C A1 DETAIL A Units Dimension Limits N Number of Pins e Pitch A Overall Height Standoff A1 A3 Molded Cap Thickness E Overall Width E1 Overall Ball Pitch D Overall Length D1 Overall Ball Pitch Øb Ball Diameter MIN 0.16 0.25 MILLIMETERS NOM 64 0.65 BSC 0.45 REF 7.00 BSC 5.85 BSC 7.00 BSC 5.85 BSC 0.30 MAX 1.00 0.25 0.35 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-370-GA Rev A Sheet 2 of 2  2016-2020 Microchip Technology Inc. DS20005372B-page 13 HV2662/HV2762 64-Ball Very Thin Fine Pitch Ball Grid Array (GA) - 7x7x1.0 mm Body [VFBGA] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 ØX C2 E1 E2 RECOMMENDED LAND PATTERN Units Dimension Limits Contact Pitch E1 Contact Pitch E2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Diameter (X64) X MIN MILLIMETERS NOM 0.65 BSC 0.65 BSC 5.85 5.85 0.25 MAX Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2370-GA Rev A DS20005372B-page 14  2016-2020 Microchip Technology Inc. HV2662/HV2762 APPENDIX A: REVISION HISTORY Revision A (May 2016) • Converted Supertex Docs #’s DSFP-2662 and DSFP-HV2762 to Microchip DS20005372. • Merged HV2662 and HV2762 into one document. • Updated “Product Identification System”. Removed parts with a package code of “LA”; Added package “GA”. • EOL of 64-Ball LFGA package (LB) per PCN JAON-20WQKC840. • Added information for 64-Ball VFBGA (GA) throughout. • Minor text changes throughout. Revision B (August 2020) • Updated Packaging Information section. • Made minor typographical corrections.  2016-2020 Microchip Technology Inc. DS20005372B-page 15 HV2662/HV2762 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device - XX X - Package Environmental Options X Media Type Device: HV2662 = 24-Channel, HV Analog Switch HV2762 = 24-Channel, HV Analog Switch with Bleed Resistors Package: GA = 64-ball VFBGA Environmental G = Lead (Pb)-free/RoHS-compliant package Media Type: (blank) = 120/Tray for GA package DS20005372B-page 16 Examples: a) HV2662GA-G: 64-ball VFBGA package, 120/Tray b) HV2762GA-G: 64-ball VFBGA package, 120/Tray  2016-2020 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specifications contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is secure when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods being used in attempts to breach the code protection features of the Microchip devices. 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Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. 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