KSZ8051MNL/RNL
10Base-T/100Base-TX
Physical Layer Transceiver
General Description
Features
The KSZ8051 is a single supply 10Base-T/100Base-TX
• Single-chip 10Base-T/100Base-TX IEEE 802.3
Ethernet physical layer transceiver for transmission and
compliant Ethernet Transceiver
reception of data over standard CAT-5 unshielded twisted
• MII Interface support (KSZ8051MNL)
pair (UTP) cable.
• RMII v1.2 Interface support with 50MHz reference clock
The KSZ8051 is a highly integrated, compact solution. It
output to MAC, and option to input 50MHz reference
reduces board cost and simplifies board layout by using
clock (KSZ8051RNL)
on-chip termination resistors for the differential pairs and
• Back-to-Back mode support for 100Mbps copper
by integrating a low noise regulator to supply the 1.2V
repeater or media converter
core.
• MDC/MDIO Management Interface for PHY register
The KSZ8051MNL offers the Media Independent Interface
configuration
(MII) and the KSZ8051RNL offers the Reduced Media
•
Programmable interrupt output
Independent Interface (RMII) for direct connection with MII/
• LED outputs for link, activity and speed status indication
RMII compliant Ethernet MAC processors and switches.
• On-chip termination resistors for the differential pairs
A 25MHz crystal is used to generate all required clocks,
including the 50MHz RMII reference clock output for the
• Baseline Wander Correction
KSZ8051RNL.
• HP Auto MDI/MDI-X for reliable detection and
The KSZ8051 provides diagnostic features to facilitate
correction for straight-through and crossover cables
system bring-up and debugging in production testing and
with disable and enable option
in product deployment. Parametric NAND tree support
• Auto-negotiation to automatically select the highest link
enables fault detection between KSZ8051 I/Os and board.
up speed (10/100 Mbps) and duplex (half/full)
®
Micrel LinkMD TDR-based cable diagnostics permit
• Power down and power saving modes
identification of faulty copper cabling.
• LinkMD® TDR-based cable diagnostics for identification
The KSZ8051MNL and KSZ8051RNL are available in 32of faulty copper cabling
pin, lead-free QFN packages (See Ordering Information).
• Parametric NAND Tree support for fault detection
Data sheets and support documentation can be found on
between chip I/Os and board.
Micrel’s web site at: www.micrel.com.
____________________________________________________________________________________________________________
Functional Diagram
LinkMD is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
July 2010
M9999-070910-1.0
Micrel, Inc.
KSZ8051MNL/RNL
More Features
Applications
•
•
•
•
•
•
• Loopback modes for diagnostics
• Single 3.3V power supply with VDD I/O options for
1.8V, 2.5V, or 3.3V
• Built-in 1.2V regulator for core
• Available in 32-pin (5mm x 5mm) QFN package
Game Console
IP Phone
IP Set-top Box
IP TV
LOM
Printer
Ordering Information
Part Number
KSZ8051MNL
KSZ8051MNLI
Package
Lead Finish
Description
0°C to 70°C
32-Pin QFN
Pb-Free
MII, Commercial Temperature
(1)
-40°C to 85°C
32-Pin QFN
Pb-Free
MII, Industrial Temperature
0°C to 70°C
32-Pin QFN
Pb-Free
RMII, Commercial Temperature
(1)
-40°C to 85°C
32-Pin QFN
Pb-Free
RMII, Industrial Temperature
KSZ8051RNL
KSZ8051RNLI
Temp. Range
Note:
1. Contact factory for lead time.
July 2010
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Revision History
Revision
Date
Summary of Changes
1.0
6/22/10
Data sheet created.
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KSZ8051MNL/RNL
Contents
General Description .............................................................................................................................................................. 1
Features ................................................................................................................................................................................. 1
Functional Diagram............................................................................................................................................................... 1
Applications........................................................................................................................................................................... 2
Ordering Information ............................................................................................................................................................ 2
Revision History.................................................................................................................................................................... 3
Contents................................................................................................................................................................................. 4
List of Figures........................................................................................................................................................................ 7
List of Tables ......................................................................................................................................................................... 8
Pin Configuration – KSZ8051MNL ....................................................................................................................................... 9
Pin Description – KSZ8051MNL......................................................................................................................................... 10
Strapping Options – KSZ8051MNL.................................................................................................................................... 13
Pin Configuration – KSZ8051RNL ..................................................................................................................................... 14
Pin Description – KSZ8051RNL ......................................................................................................................................... 15
Strapping Options – KSZ8051RNL .................................................................................................................................... 18
Functional Description: 10Base-T/100Base-TX Transceiver ......................................................................................... 19
100Base-TX Transmit....................................................................................................................................................... 19
100Base-TX Receive........................................................................................................................................................ 19
10Base-T Transmit ........................................................................................................................................................... 19
10Base-T Receive ............................................................................................................................................................ 19
Scrambler/De-scrambler (100Base-TX only).................................................................................................................... 20
SQE and Jabber Function (10Base-T only)...................................................................................................................... 20
PLL Clock Synthesizer...................................................................................................................................................... 20
Auto-Negotiation ............................................................................................................................................................... 20
MII Data Interface (KSZ8051MNL only) ............................................................................................................................. 21
MII Signal Definition.......................................................................................................................................................... 22
Transmit Clock (TXC) ................................................................................................................................................... 22
Transmit Enable (TXEN) .............................................................................................................................................. 22
Transmit Data [3:0] (TXD[3:0]) ..................................................................................................................................... 22
Receive Clock (RXC).................................................................................................................................................... 22
Receive Data Valid (RXDV).......................................................................................................................................... 22
Receive Data[3:0] (RXD[3:0]) ....................................................................................................................................... 23
Receive Error (RXER) .................................................................................................................................................. 23
Carrier Sense (CRS) .................................................................................................................................................... 23
Collision (COL) ............................................................................................................................................................. 23
MII Signal Diagram ........................................................................................................................................................... 23
RMII Data Interface (KSZ8051RNL only) ........................................................................................................................... 24
RMII – 25MHz Clock Mode............................................................................................................................................... 24
RMII – 50MHz Clock Mode............................................................................................................................................... 24
RMII Signal Definition ....................................................................................................................................................... 24
Reference Clock (REF_CLK) ....................................................................................................................................... 24
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Transmit Enable (TXEN) .............................................................................................................................................. 25
Transmit Data [1:0] (TXD[1:0]) ..................................................................................................................................... 25
Carrier Sense/Receive Data Valid (CRS_DV).............................................................................................................. 25
Receive Data [1:0] (RXD[1:0]) ...................................................................................................................................... 25
Receive Error (RXER) .................................................................................................................................................. 25
Collision Detection........................................................................................................................................................ 25
RMII Signal Diagram......................................................................................................................................................... 25
RMII – 25MHz Clock Mode........................................................................................................................................... 26
RMII – 50MHz Clock Mode........................................................................................................................................... 26
Back-to-Back Mode – 100Mbps Copper Repeater / Media Converter............................................................................ 27
MII Back-to-Back Mode (KSZ8051MNL only)................................................................................................................... 27
RMII Back-to-Back Mode (KSZ8051RNL only) ................................................................................................................ 28
MII Management (MIIM) Interface....................................................................................................................................... 28
Interrupt (INTRP) ................................................................................................................................................................. 29
HP Auto MDI/MDI-X ............................................................................................................................................................. 29
Straight Cable ................................................................................................................................................................... 29
Crossover Cable ............................................................................................................................................................... 30
LinkMD® Cable Diagnostics................................................................................................................................................ 30
NAND Tree Support ............................................................................................................................................................ 30
NAND Tree I/O Testing..................................................................................................................................................... 32
Power Management ............................................................................................................................................................ 32
Power Saving Mode.......................................................................................................................................................... 32
Energy Detect Power Down Mode ................................................................................................................................... 32
Power Down Mode ........................................................................................................................................................... 32
Slow Oscillator Mode ........................................................................................................................................................ 32
Reference Circuit for Power and Ground Connections .................................................................................................. 33
Register Map........................................................................................................................................................................ 34
Register Description ........................................................................................................................................................... 34
Register Description (Continued)...................................................................................................................................... 35
Register Description (Continued)...................................................................................................................................... 36
Register Description (Continued)...................................................................................................................................... 37
Register Description (Continued)...................................................................................................................................... 38
Register Description (Continued)...................................................................................................................................... 39
Register Description (Continued)...................................................................................................................................... 40
Register Description (Continued)...................................................................................................................................... 41
Register Description (Continued)...................................................................................................................................... 42
Register Description (Continued)...................................................................................................................................... 43
Absolute Maximum Ratings(1) ............................................................................................................................................ 44
Operating Ratings(2) ............................................................................................................................................................ 44
Electrical Characteristics(3) ................................................................................................................................................ 44
Electrical Characteristics(3) (Continued) ........................................................................................................................... 45
Timing Diagrams ................................................................................................................................................................. 46
MII SQE Timing (10Base-T) ............................................................................................................................................. 46
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MII Transmit Timing (10Base-T) ....................................................................................................................................... 47
MII Receive Timing (10Base-T) ........................................................................................................................................ 48
MII Transmit Timing (100Base-TX) .................................................................................................................................. 49
MII Receive Timing (100Base-TX) ................................................................................................................................... 50
RMII Timing....................................................................................................................................................................... 51
Auto-Negotiation Timing ................................................................................................................................................... 52
MDC/MDIO Timing ........................................................................................................................................................... 53
Reset Timing..................................................................................................................................................................... 54
Reset Circuit ........................................................................................................................................................................ 55
Reference Circuits for LED Strapping Pins...................................................................................................................... 56
Magnetics Specification ..................................................................................................................................................... 57
Reference Clock – Connection and Selection.................................................................................................................. 57
Package Information........................................................................................................................................................... 59
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List of Figures
Figure 1. Auto-Negotiation Flow Chart................................................................................................................................. 21
Figure 2. KSZ8051MNL MII Interface .................................................................................................................................. 23
Figure 3. KSZ8051RNL RMII Interface (25MHz Clock Mode) ............................................................................................ 26
Figure 4. KSZ8051RNL RMII Interface (50MHz Clock Mode) ............................................................................................ 26
Figure 5. KSZ8051MNL/RNL and KSZ8041FTL Back-to-Back Media Converter ............................................................... 27
Figure 6. Typical Straight Cable Connection ....................................................................................................................... 29
Figure 7. Typical Crossover Cable Connection ................................................................................................................... 30
Figure 8. KSZ8051MNL/RNL Power and Ground Connections........................................................................................... 33
Figure 9. MII SQE Timing (10Base-T) ................................................................................................................................. 46
Figure 10. MII Transmit Timing (10Base-T) ......................................................................................................................... 47
Figure 11. MII Receive Timing (10Base-T) .......................................................................................................................... 48
Figure 12. MII Transmit Timing (100Base-TX)..................................................................................................................... 49
Figure 13. MII Receive Timing (100Base-TX)...................................................................................................................... 50
Figure 14. RMII Timing – Data Received from RMII ............................................................................................................ 51
Figure 15. RMII Timing – Data Input to RMII ....................................................................................................................... 51
Figure 16. Auto-Negotiation Fast Link Pulse (FLP) Timing ................................................................................................. 52
Figure 17. MDC/MDIO Timing.............................................................................................................................................. 53
Figure 18. Reset Timing....................................................................................................................................................... 54
Figure 19. Recommended Reset Circuit.............................................................................................................................. 55
Figure 20. Recommended Reset Circuit for interfacing with CPU/FPGA Reset Output...................................................... 55
Figure 21. Reference Circuits for LED Strapping Pins......................................................................................................... 56
Figure 22. 25MHz Crystal / Oscillator Reference Clock Connection ................................................................................... 57
Figure 23. 50MHz Oscillator Reference Clock Connection ................................................................................................. 58
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KSZ8051MNL/RNL
List of Tables
Table 1. MII Signal Definition ............................................................................................................................................... 22
Table 2. RMII Signal Description.......................................................................................................................................... 24
Table 3. MII Signal Connection for MII Back-to-Back Mode (100Base-TX Copper Repeater)............................................ 27
Table 4. RMII Signal Connection for RMII Back-to-Back Mode (100Base-TX Copper Repeater) ...................................... 28
Table 5. MII Management Frame Format – for KSZ8051MNL/RNL .................................................................................... 28
Table 6. MDI/MDI-X Pin Definition ....................................................................................................................................... 29
Table 7. NAND Tree Test Pin Order – for KSZ8051MNL .................................................................................................... 31
Table 8. NAND Tree Test Pin Order – for KSZ8051RNL .................................................................................................... 31
Table 9. KSZ8051MNL/RNL Power Pin Description............................................................................................................ 33
Table 10. MII SQE Timing (10Base-T) Parameters ............................................................................................................. 46
Table 11. MII Transmit Timing (10Base-T) Parameters ...................................................................................................... 47
Table 12. MII Receive Timing (10Base-T) Parameters ....................................................................................................... 48
Table 13. MII Transmit Timing (100Base-TX) Parameters .................................................................................................. 49
Table 14. MII Receive Timing (100Base-TX) Parameters ................................................................................................... 50
Table 15. RMII Timing Parameters – KSZ8051RNL (25MHz input to XI pin, 50MHz output from REF_CLK pin).............. 51
Table 16. RMII Timing Parameters – KSZ8051RNL (50MHz input to XI pin)...................................................................... 51
Table 17. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters ............................................................................... 52
Table 18. MDC/MDIO Timing Parameters ........................................................................................................................... 53
Table 19. Reset Timing Parameters .................................................................................................................................... 54
Table 20. Magnetics Selection Criteria ................................................................................................................................ 57
Table 21. Qualified Single Port 10/100 Magnetics............................................................................................................... 57
Table 22. 25MHz Crystal / Reference Clock Selection Criteria ........................................................................................... 58
Table 23. 50MHz Oscillator / Reference Clock Selection Criteria ....................................................................................... 58
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KSZ8051MNL/RNL
Pin Configuration – KSZ8051MNL
32-Pin (5mm x 5mm) QFN
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KSZ8051MNL/RNL
Pin Description – KSZ8051MNL
(1)
Pin Number
Pin Name
1
GND
Gnd
2
VDD_1.2
P
Type
Pin Function
Ground
1.2V core VDD
(power supplied by KSZ8051MNL)
Decouple with 2.2uF and 0.1uF capacitors to ground.
3
VDDA_3.3
P
3.3V analog VDD
4
RXM
I/O
Physical receive or transmit signal (- differential)
5
RXP
I/O
Physical receive or transmit signal (+ differential)
6
TXM
I/O
Physical transmit or receive signal (- differential)
7
TXP
I/O
Physical transmit or receive signal (+ differential)
8
XO
O
Crystal feedback – for 25 MHz crystal
This pin is a no connect if oscillator or external clock source is used.
9
XI
I
Crystal / Oscillator / External Clock Input
25MHz +/-50ppm
10
REXT
I
Set physical transmit output current
Connect a 6.49KΩ resistor to ground on this pin.
11
MDIO
I/O
Management Interface (MII) Data I/O
This pin has a weak pull-up, is open drain like, and requires an external 1.0KΩ pullup resistor.
12
MDC
I
Management Interface (MII) Clock Input
This clock pin is synchronous to the MDIO data pin.
13
RXD3 /
Ipu/O
PHYAD0
14
RXD2 /
Ipd/O
PHYAD1
15
RXD1 /
Ipd/O
PHYAD2
16
RXD0 /
Ipu/O
DUPLEX
17
VDDIO
P
18
RXDV /
Ipd/O
CONFIG2
19
RXC /
Ipd/O
B-CAST_OFF
20
RXER /
Ipd/O
ISO
21
INTRP /
Ipu/Opu
(2)
MII Mode:
MII Receive Data Output[3]
Config Mode:
The pull-up/pull-down value is latched as PHYADDR[0] at the
de-assertion of reset. See “Strapping Options” section for details.
MII Mode:
MII Receive Data Output[2]
Config Mode:
The pull-up/pull-down value is latched as PHYADDR[1] at the
de-assertion of reset. See “Strapping Options” section for details.
MII Mode:
MII Receive Data Output[1]
Config Mode:
The pull-up/pull-down value is latched as PHYADDR[2] at the
de-assertion of reset. See “Strapping Options” section for details.
MII Mode:
MII Receive Data Output[0]
Config Mode:
The pull-up/pull-down value is latched as DUPLEX at the
de-assertion of reset. See “Strapping Options” section for details.
(2)
(2)
(2)
/
/
/
/
3.3V, 2.5V or 1.8V digital VDD
MII Mode:
MII Receive Data Valid Output /
Config Mode:
The pull-up/pull-down value is latched as CONFIG2 at the
de-assertion of reset. See “Strapping Options” section for details.
MII Mode:
MII Receive Clock Output
Config Mode:
The pull-up/pull-down value is latched as B-CAST_OFF at the
de-assertion of reset. See “Strapping Options” section for details.
MII Mode:
MII Receive Error Output /
Config Mode:
The pull-up/pull-down value is latched as ISOLATE at the
de-assertion of reset. See “Strapping Options” section for details.
Interrupt Output: Programmable Interrupt Output
This pin has a weak pull-up, is open drain like, and requires an external 1.0KΩ pullup resistor.
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Pin Number
KSZ8051MNL/RNL
Pin Name
(1)
Type
Config Mode:
NAND_Tree#
22
TXC
Pin Function
I/O
The pull-up/pull-down value is latched as NAND Tree# at the
de-assertion of reset. See “Strapping Options” section for details.
MII Mode:
MII Transmit Clock Output
MII Back-to-Back Mode:
MII Transmit Clock Input
23
TXEN
I
MII Mode:
MII Transmit Enable Input
24
TXD0
I
MII Mode:
MII Transmit Data Input[0]
25
TXD1
I
MII Mode:
MII Transmit Data Input[1]
26
TXD2
I
MII Mode:
MII Transmit Data Input[2]
27
TXD3
I
MII Mode:
MII Transmit Data Input[3]
COL /
Ipd/O
MII Mode:
MII Collision Detect Output /
Config Mode:
The pull-up/pull-down value is latched as CONFIG0 at the
de-assertion of reset. See “Strapping Options” section for details.
28
CONFIG0
29
CRS /
Ipd/O
CONFIG1
30
LED0 /
Ipu/O
NWAYEN
(3)
(3)
(3)
(3)
MII Mode:
MII Carrier Sense Output /
Config Mode:
The pull-up/pull-down value is latched as CONFIG1 at the
de-assertion of reset. See “Strapping Options” section for details.
LED Output:
Programmable LED0 Output /
Config Mode:
Latched as Auto-Negotiation Enable (register 0h, bit 12) at the
de-assertion of reset. See “Strapping Options” section for details.
The LED0 pin is programmable via register 1Fh bits [5:4], and is defined as follows.
LED mode = [00]
Link/Activity
Pin State
LED Definition
No Link
High
OFF
Link
Low
ON
Activity
Toggle
Blinking
Link
Pin State
LED Definition
No Link
High
OFF
Link
Low
ON
LED mode = [01]
LED mode = [10], [11]
31
LED1 /
SPEED
Ipu/O
Reserved
LED Output:
Programmable LED1 Output /
Config Mode:
reset.
Latched as SPEED (register 0h, bit 13) at the de-assertion of
See “Strapping Options” section for details.
The LED1 pin is programmable via register 1Fh bits [5:4], and is defined as follows.
LED mode = [00]
Speed
Pin State
LED Definition
10Base-T
High
OFF
100Base-TX
Low
ON
Activity
Pin State
LED Definition
No Activity
High
OFF
LED mode = [01]
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Pin Number
KSZ8051MNL/RNL
Pin Name
(1)
Type
Pin Function
Activity
Toggle
LED mode = [10], [11]
32
RST#
I
PADDLE
GND
Gnd
Blinking
Reserved
Chip Reset (active low)
Ground
Notes:
1.
P = Power supply.
Gnd = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin with internal pull-up (see Electrical
Characteristics for value) otherwise.
2.
MII Rx Mode: The RXD[3:0] bits are synchronous with RXC. When RXDV is asserted, RXD[3:0] presents valid data to the MAC. RXD[3:0] is
invalid data from the PHY when RXDV is de-asserted.
3.
MII Tx Mode: The TXD[3:0] bits are synchronous with TXC. When TXEN is asserted, TXD[3:0] presents valid data from the MAC. TXD[3:0] has
no effect on the PHY when TXEN is de-asserted.
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KSZ8051MNL/RNL
Strapping Options – KSZ8051MNL
(1)
Pin Number
Pin Name
15
PHYAD2
Ipd/O
14
PHYAD1
Ipd/O
The PHY Address is latched at de-assertion of reset and is configurable to any value
from 0 to 7.
13
PHYAD0
Ipu/O
The default PHY Address is 00001.
Type
Pin Function
PHY Address 00000 is enabled only if the B-CAST_OFF strapping pin is pulled high.
PHY Address bits [4:3] are set to ‘00’ by default.
The CONFIG[2:0] strap-in pins are latched at the de-assertion of reset.
18
CONFIG2
Ipd/O
29
CONFIG1
Ipd/O
CONFIG[2:0]
Mode
28
CONFIG0
Ipd/O
000
MII (default)
110
MII Back-to-Back
001 – 101, 111
Reserved – not used
20
ISO
Ipd/O
ISOLATE mode
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into register 0h bit 10.
31
SPEED
Ipu/O
SPEED mode
Pull-up (default) = 100Mbps
Pull-down = 10Mbps
At the de-assertion of reset, this pin value is latched into register 0h bit 13 as the
Speed Select, and also is latched into register 4h (Auto-Negotiation Advertisement)
as the Speed capability support.
16
DUPLEX
Ipu/O
DUPLEX mode
Pull-up (default) = Half Duplex
Pull-down = Full Duplex
At the de-assertion of reset, this pin value is latched into register 0h bit 8.
30
NWAYEN
Ipu/O
Nway Auto-Negotiation Enable
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
At the de-assertion of reset, this pin value is latched into register 0h bit 12.
19
B-CAST_OFF
Ipd/O
Broadcast Off – for PHY Address 0
Pull-up = PHY Address 0 is set as an unique PHY address
Pull-down (default) = PHY Address 0 is set as a broadcast PHY address
At the de-assertion of reset, this pin value is latched by the chip.
21
NAND_Tree#
Ipu/Opu
NAND Tree Mode
Pull-up (default) = Disable
Pull-down = Enable
At the de-assertion of reset, this pin value is latched by the chip.
Note:
1.
Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin with internal pull-up (see Electrical
Characteristics for value) otherwise.
The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC MII receive input pins may drive high/low during power-up or reset,
and consequently cause the PHY strap-in pins on the MII signals to be latched to the unintended high/low states. In this case, external pull-ups (4.7K) or
pull-downs (1.0K) should be added on these PHY strap-in pins to ensure the intended values are strapped-in correctly.
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KSZ8051MNL/RNL
Pin Configuration – KSZ8051RNL
32-Pin (5mm x 5mm) QFN
July 2010
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KSZ8051MNL/RNL
Pin Description – KSZ8051RNL
(1)
Pin Number
Pin Name
1
GND
Gnd
2
VDD_1.2
P
Type
Pin Function
Ground
1.2V core VDD
(power supplied by KSZ8051RNL)
Decouple with 2.2uF and 0.1uF capacitors to ground.
3
VDDA_3.3
P
3.3V analog VDD
4
RXM
I/O
Physical receive or transmit signal (- differential)
5
RXP
I/O
Physical receive or transmit signal (+ differential)
6
TXM
I/O
Physical transmit or receive signal (- differential)
7
TXP
I/O
Physical transmit or receive signal (+ differential)
8
XO
O
Crystal feedback – for 25 MHz crystal
This pin is a no connect if oscillator or external clock source is used.
9
10
XI
REXT
I
I
25MHz Mode:
25MHz +/-50ppm Crystal / Oscillator / External Clock Input
50MHz Mode:
50MHz +/-50ppm Oscillator / External Clock Input
Set physical transmit output current
Connect a 6.49KΩ resistor-to-ground on this pin.
11
MDIO
I/O
Management Interface (MII) Data I/O
This pin has a weak pull-up, is open drain like, and requires an external 1.0KΩ pullup resistor.
12
MDC
I
Management Interface (MII) Clock Input
This clock pin is synchronous to the MDIO data pin.
13
PHYAD0
Ipu/O
The pull-up/pull-down value is latched as PHYADDR[0] at the de-assertion of reset.
See “Strapping Options” section for details.
14
PHYAD1
Ipd/O
The pull-up/pull-down value is latched as PHYADDR[1] at the de-assertion of reset.
See “Strapping Options” section for details.
15
RXD1 /
Ipd/O
RMII Mode:
RMII Receive Data Output[1]
Config Mode:
The pull-up/pull-down value is latched as PHYADDR[2] at the
de-assertion of reset. See “Strapping Options” section for details.
RMII Mode:
RMII Receive Data Output[0]
Config Mode:
The pull-up/pull-down value is latched as DUPLEX at the
de-assertion of reset. See “Strapping Options” section for details.
PHYAD2
16
RXD0 /
Ipu/O
DUPLEX
17
VDDIO
P
18
CRS_DV /
Ipd/O
CONFIG2
19
REF_CLK /
Ipd/O
(2)
(2)
/
/
3.3V, 2.5V or 1.8V digital VDD
RMII Mode:
RMII Carrier Sense/Receive Data Valid Output /
Config Mode:
The pull-up/pull-down value is latched as CONFIG2 at the
de-assertion of reset. See “Strapping Options” section for details.
RMII Mode:
25MHz Mode: This pin provides the 50MHz RMII reference clock
output to the MAC. See also XI (pin 9).
50MHz Mode: This pin is a no connect. See also XI (pin 9).
B-CAST_OFF
20
RXER /
Ipd/O
ISO
21
INTRP /
Ipu/Opu
Config Mode:
The pull-up/pull-down value is latched as B-CAST_OFF at the
de-assertion of reset. See “Strapping Options” section for details.
RMII Mode:
RMII Receive Error Output /
Config Mode:
The pull-up/pull-down value is latched as ISOLATE at the
de-assertion of reset. See “Strapping Options” section for details.
Interrupt Output: Programmable Interrupt Output
This pin has a weak pull-up, is open drain like, and requires an external 1.0KΩ pullup resistor.
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Pin Number
KSZ8051MNL/RNL
Pin Name
(1)
Type
Pin Function
Config Mode:
NAND_Tree#
The pull-up/pull-down value is latched as NAND Tree# at the
de-assertion of reset. See “Strapping Options” section for details.
22
NC
O
No connect- It is recommended to tie this unused pin directly to ground.
23
TXEN
I
RMII Transmit Enable Input
24
TXD0
I
RMII Transmit Data Input[0]
25
TXD1
I
RMII Transmit Data Input[1]
26
NC
I
No connect- It is recommended to tie this unused pin directly to ground.
27
NC
I
No connect- It is recommended to tie this unused pin directly to ground.
28
CONFIG0
Ipd/O
The pull-up/pull-down value is latched as CONFIG0 at the de-assertion of reset.
See “Strapping Options” section for details.
29
CONFIG1
Ipd/O
The pull-up/pull-down value is latched as CONFIG1 at the de-assertion of reset.
See “Strapping Options” section for details.
LED0 /
Ipu/O
LED Output:
Programmable LED0 Output /
Config Mode:
Latched as Auto-Negotiation Enable (register 0h, bit 12) at the
de-assertion of reset. See “Strapping Options” section for details.
30
NWAYEN
(3)
(3)
The LED0 pin is programmable via register 1Fh bits [5:4], and is defined as follows.
LED mode = [00]
Link/Activity
Pin State
LED Definition
No Link
High
OFF
Link
Low
ON
Activity
Toggle
Blinking
Link
Pin State
LED Definition
No Link
High
OFF
Link
Low
ON
LED mode = [01]
LED mode = [10], [11]
31
LED1 /
SPEED
Ipu/O
Reserved
LED Output:
Programmable LED1 Output /
Config Mode:
reset.
Latched as SPEED (register 0h, bit 13) at the de-assertion of
See “Strapping Options” section for details.
The LED1 pin is programmable via register 1Fh bits [5:4], and is defined as follows.
LED mode = [00]
Speed
Pin State
LED Definition
10Base-T
High
OFF
100Base-TX
Low
ON
Activity
Pin State
LED Definition
No Activity
High
OFF
Activity
Toggle
Blinking
LED mode = [01]
LED mode = [10], [11]
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KSZ8051MNL/RNL
(1)
Pin Number
Pin Name
32
RST#
I
PADDLE
GND
Gnd
Type
Pin Function
Chip Reset (active low)
Ground
Notes:
1.
P = Power supply.
Gnd = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin with internal pull-up (see Electrical
Characteristics for value) otherwise.
2.
RMII Rx Mode: The RXD[1:0] bits are synchronous with the 50MHz RMII Reference Clock. For each clock period in which CRS_DV is asserted,
two bits of recovered data are sent by the PHY to the MAC.
3.
RMII Tx Mode: The TXD[1:0] bits are synchronous with the 50MHz RMII Reference Clock . For each clock period in which TXEN is asserted, two
bits of data are received by the PHY from the MAC.
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Strapping Options – KSZ8051RNL
(1)
Pin Number
Pin Name
15
PHYAD2
Ipd/O
14
PHYAD1
Ipd/O
The PHY Address is latched at de-assertion of reset and is configurable to any value
from 0 to 7.
13
PHYAD0
Ipu/O
The default PHY Address is 00001.
Type
Pin Function
PHY Address 00000 is enabled only if the B-CAST_OFF strapping pin is pulled high.
PHY Address bits [4:3] are set to ‘00’ by default.
The CONFIG[2:0] strap-in pins are latched at the de-assertion of reset.
18
CONFIG2
Ipd/O
29
CONFIG1
Ipd/O
CONFIG[2:0]
Mode
28
CONFIG0
Ipd/O
001
RMII
101
RMII Back-to-Back
000, 010 – 100, 110, 111
Reserved – not used
20
ISO
Ipd/O
ISOLATE mode
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into register 0h bit 10.
31
SPEED
Ipu/O
SPEED mode
Pull-up (default) = 100Mbps
Pull-down = 10Mbps
At the de-assertion of reset, this pin value is latched into register 0h bit 13 as the
Speed Select, and also is latched into register 4h (Auto-Negotiation Advertisement)
as the Speed capability support.
16
DUPLEX
Ipu/O
DUPLEX mode
Pull-up (default) = Half Duplex
Pull-down = Full Duplex
At the de-assertion of reset, this pin value is latched into register 0h bit 8.
30
NWAYEN
Ipu/O
Nway Auto-Negotiation Enable
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
At the de-assertion of reset, this pin value is latched into register 0h bit 12.
19
B-CAST_OFF
Ipd/O
Broadcast Off – for PHY Address 0
Pull-up = PHY Address 0 is set as an unique PHY address
Pull-down (default) = PHY Address 0 is set as a broadcast PHY address
At the de-assertion of reset, this pin value is latched by the chip.
21
NAND_Tree#
Ipu/Opu
NAND Tree Mode
Pull-up (default) = Disable
Pull-down = Enable
At the de-assertion of reset, this pin value is latched by the chip.
Note:
1.
Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset; output pin with internal pull-up (see Electrical
Characteristics for value) otherwise.
The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC MII receive input pins may drive high/low during power-up or reset,
and consequently cause the PHY strap-in pins on the RMII signals to be latched to the unintended high/low states. In this case, external pull-ups (4.7K)
or pull-downs (1.0K) should be added on these PHY strap-in pins to ensure the intended values are strapped-in correctly.
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KSZ8051MNL/RNL
Functional Description: 10Base-T/100Base-TX Transceiver
The KSZ8051MNL/RNL is an integrated single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE
802.3 Specification, and reduces board cost and simplifies board layout by using on-chip termination resistors for the two
differential pairs and by integrating the regulator to supply the 1.2V core.
On the copper media side, the KSZ8051MNL/RNL supports 10Base-T and 100Base-TX for transmission and reception of
data over a standard CAT-5 unshielded twisted pair (UTP) cable, and HP auto MDI/MDI-X for reliable detection of and
correction for straight-through and crossover cables.
On the MAC processor side, the KSZ8051MNL offers the Media Independent Interface (MII) and the KSZ8051RNL offers
the Reduced Media Independent Interface (RMII) for direct connection with MII/RMII compliant Ethernet MAC processors
and switches.
The MII management bus option gives the MAC processor complete access to the KSZ8051MNL/RNL control and status
registers. Additionally, an interrupt pin eliminates the need for the processor to poll for PHY status change.
100Base-TX Transmit
The 100Base-TX transmit function performs parallel-to-serial conversion, 4B/5B encoding, scrambling, NRZ-to-NRZI
conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial bit
stream. The data and control stream is then converted into 4B/5B coding and followed by a scrambler. The serialized data
is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is set by
an external 6.49kΩ 1% resistor for the 1:1 transformer ratio.
The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave-shaped 10Base-T output is also incorporated into the 100Base-TX
transmitter.
100Base-TX Receive
The 100Base-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted pair
cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization.
This is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used to
compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion circuit
converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used
to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/5B
decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.
10Base-T Transmit
The 10Base-T drivers are incorporated with the 100Base-TX drivers to allow for transmission using the same magnetic.
The drivers perform internal wave-shaping and pre-emphasis, and output 10Base-T signals with a typical amplitude of
2.5V peak. The 10Base-T signals have harmonic contents that are at least 27dB below the fundamental frequency when
driven by an all-ones Manchester-encoded signal.
10Base-T Receive
On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and
a PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data.
A squelch circuit rejects signals with levels less than 400 mV or with short pulse widths to prevent noise at the RXP and
RXM inputs from falsely trigger the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming
signal and the KSZ8051MNL/RNL decodes a data frame. The receive clock is kept active during idle periods in between
data reception.
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KSZ8051MNL/RNL
Scrambler/De-scrambler (100Base-TX only)
The scrambler is used to spread the power spectrum of the transmitted signal to reduce EMI and baseline wander, and
the de-scrambler is needed to recover the scrambled signal.
SQE and Jabber Function (10Base-T only)
In 10Base-T operation, a short pulse is put out on the COL pin after each frame is transmitted. This SQE Test is required
as a test of the 10Base-T transmit/receive path. If transmit enable (TXEN) is high for more than 20 ms (jabbering), the
10Base-T transmitter is disabled and COL is asserted high. If TXEN is then driven low for more than 250 ms, the 10BaseT transmitter is re-enabled and COL is de-asserted (returns to low).
PLL Clock Synthesizer
The KSZ8051MNL/RNL generates all internal clocks and all external clocks for system timing from an external 25MHz
crystal, oscillator, or reference clock. For the KSZ8051RNL in RMII 50MHz clock mode, these clocks are generated from
an external 50MHz oscillator or system clock.
Auto-Negotiation
The KSZ8051MNL/RNL conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3 Specification.
Auto-negotiation allows UTP (Unshielded Twisted Pair) link partners to select the highest common mode of operation.
During auto-negotiation, link partners advertise capabilities across the UTP link to each other, and then compare their own
capabilities with those they received from their link partners. The highest speed and duplex setting that is common to the
two link partners is selected as the mode of operation.
The following list shows the speed and duplex operation mode from highest to lowest priority.
•
Priority 1: 100Base-TX, full-duplex
•
Priority 2: 100Base-TX, half-duplex
•
Priority 3: 10Base-T, full-duplex
• Priority 4: 10Base-T, half-duplex
If auto-negotiation is not supported or the KSZ8051MNL/RNL link partner is forced to bypass auto-negotiation, then the
KSZ8051MNL/RNL sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and
allows the KSZ8051MNL/RNL to establish link by listening for a fixed signal protocol in the absence of auto-negotiation
advertisement protocol.
Auto-negotiation is enabled by either hardware pin strapping (NWAYEN, pin 30) or software (register 0h, bit 12).
By default, auto-negotiation is enabled after power-up or hardware reset. Afterwards, auto-negotiation can be enabled or
disabled by register 0h, bit 12. If auto-negotiation is disabled, the speed is set by register 0h, bit 13, and the duplex is set
by register 0h, bit 8.
The auto-negotiation link up process is shown in the following flow chart.
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Figure 1. Auto-Negotiation Flow Chart
MII Data Interface (KSZ8051MNL only)
The Media Independent Interface (MII) is compliant with the IEEE 802.3 Specification. It provides a common interface
between MII PHYs and MACs, and has the following key characteristics:
•
Pin count is 15 pins (6 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision
indication).
•
10Mbps and 100Mbps data rates are supported at both half and full duplex.
•
Data transmission and reception are independent and belong to separate signal groups.
•
Transmit data and receive data are each 4-bit wide, a nibble.
By default, the KSZ8051MNL is configured to MII mode after it is powered up or hardware reset with the following:
•
A 25MHz crystal connected to XI, XO (pins 9, 8), or an external 25MHz clock source (oscillator) connected to XI.
•
The CONFIG[2:0] strapping pins (pins 18, 29, 28) set to ‘000’ (default setting).
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MII Signal Definition
The following table describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information.
MII
Signal Name
Direction
(with respect to PHY,
KSZ8051MNL signal)
Direction
(with respect to MAC)
TXC
Output
Input
Transmit Clock
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
TXEN
Input
Output
Transmit Enable
TXD[3:0]
Input
Output
Transmit Data [3:0]
RXC
Output
Input
Receive Clock
RXDV
Output
Input
Receive Data Valid
RXD[3:0]
Output
Input
Receive Data [3:0]
Description
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
RXER
Output
Input, or (not required)
Receive Error
CRS
Output
Input
Carrier Sense
COL
Output
Input
Collision Detection
Table 1. MII Signal Definition
Transmit Clock (TXC)
TXC is sourced by the PHY. It is a continuous clock that provides the timing reference for TXEN and TXD[3:0].
TXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.
Transmit Enable (TXEN)
TXEN indicates the MAC is presenting nibbles on TXD[3:0] for transmission. It is asserted synchronously with the first
nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII, and is negated
prior to the first TXC following the final nibble of a frame.
TXEN transitions synchronously with respect to TXC.
Transmit Data [3:0] (TXD[3:0])
TXD[3:0] transitions synchronously with respect to TXC. When TXEN is asserted, TXD[3:0] are accepted for transmission
by the PHY. TXD[3:0] is ”00” to indicate idle when TXEN is de-asserted. Values other than “00” on TXD[3:0] while TXEN
is de-asserted are ignored by the PHY.
Receive Clock (RXC)
RXC provides the timing reference for RXDV, RXD[3:0], and RXER.
•
In 10Mbps mode, RXC is recovered from the line while carrier is active. RXC is derived from the PHY’s reference
clock when the line is idle, or link is down.
•
In 100Mbps mode, RXC is continuously recovered from the line. If link is down, RXC is derived from the PHY’s
reference clock.
RXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.
Receive Data Valid (RXDV)
RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on RXD[3:0].
•
In 10Mbps mode, RXDV is asserted with the first nibble of the SFD (Start of Frame Delimiter), “5D”, and remains
asserted until the end of the frame.
• In 100Mbps mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the frame.
RXDV transitions synchronously with respect to RXC.
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Receive Data[3:0] (RXD[3:0])
RXD[3:0] transitions synchronously with respect to RXC. For each clock period in which RXDV is asserted, RXD[3:0]
transfers a nibble of recovered data from the PHY.
Receive Error (RXER)
RXER is asserted for one or more RXC periods to indicate that a Symbol Error (e.g., a coding error that a PHY is capable
of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame
presently being transferred from the PHY.
RXER transitions synchronously with respect to RXC. While RXDV is de-asserted, RXER has no effect on the MAC.
Carrier Sense (CRS)
CRS is asserted and de-asserted as follows:
•
In 10Mbps mode, CRS assertion is based on the reception of valid preambles. CRS de-assertion is based upon
the reception of an end-of-frame (EOF) marker.
•
In 100Mbps mode, CRS is asserted when a start-of-stream delimiter or /J/K symbol pair is detected. CRS is deasserted when an end-of-stream delimiter or /T/R symbol pair is detected. Additionally, the PMA layer de-asserts
CRS if IDLE symbols are received without /T/R.
Collision (COL)
COL is asserted in half-duplex mode whenever the transmitter and receiver are simultaneously active on the line. This is
used to inform the MAC that a collision has occurred during its transmission to the PHY.
COL transitions asynchronously with respect to TXC and RXC.
MII Signal Diagram
The KSZ8051MNL MII pin connections to the MAC are shown in the following figure.
Figure 2. KSZ8051MNL MII Interface
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KSZ8051MNL/RNL
RMII Data Interface (KSZ8051RNL only)
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). It provides
a common interface between physical layer and MAC layer devices, and has the following key characteristics:
•
Pin count is 8 pins (3 pins for data transmission, 4 pins for data reception, 1 pin for the 50MHz reference clock).
•
10Mbps and 100Mbps data rates are supported at both half and full duplex.
•
Data transmission and reception are independent and belong to separate signal groups.
•
Transmit data and receive data are each 2-bit wide, a dibit.
RMII – 25MHz Clock Mode
The KSZ8051RNL is configured to RMII – 25MHz Clock Mode after it is powered up or hardware reset with the following:
•
A 25MHz crystal connected to XI, XO (pins 9, 8), or an external 25MHz clock source (oscillator) connected to XI.
•
The CONFIG[2:0] strapping pins (pins 18, 29, 28) set to ‘001’.
•
Register 1Fh, bit 7 is set to ‘0’ (default value) to select 25MHz Clock Mode.
RMII – 50MHz Clock Mode
The KSZ8051RNL is configured to RMII – 50MHz Clock Mode after it is powered up or hardware reset with the following:
•
An external 50MHz clock source (oscillator) connected to XI (pin 9).
•
The CONFIG[2:0] strapping pins (pins 18, 29, 28) set to ‘001’.
•
Register 1Fh, bit 7 is set to ‘1’ to select 50MHz Clock Mode.
RMII Signal Definition
The following table describes the RMII signals. Refer to RMII Specification v1.2 for detailed information.
RMII
Signal Name
Direction
(with respect to PHY,
KSZ8051RNL signal)
Direction
(with respect to
MAC)
REF_CLK
Output (25MHz clock mode) /
Input /
(50MHz clock
mode)
Input or
Synchronous 50 MHz reference clock for
receive, transmit and control interface
TXEN
Input
Output
Transmit Enable
TXD[1:0]
Input
Output
Transmit Data [1:0]
CRS_DV
Output
Input
Carrier Sense/Receive Data Valid
RXD[1:0]
Output
Input
Receive Data [1:0]
RXER
Output
Input, or (not
required)
Receive Error
Description
Table 2. RMII Signal Description
Reference Clock (REF_CLK)
REF_CLK is a continuous 50MHz clock that provides the timing reference for TX_EN, TXD[1:0], CRS_DV, RXD[1:0], and
RX_ER.
For 25MHz Clock Mode, the KSZ8051RNL generates and outputs the 50MHz RMII REF_CLK to the MAC at REF_CLK
(pin 19).
For 50MHz Clock Mode, the KSZ8051RNL takes in the 50MHz RMII REF_CLK from the MAC or system board at XI (pin
9) and has the REF_CLK (pin 19) left as a no connect.
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Transmit Enable (TXEN)
TXEN indicates that the MAC is presenting dibits on TXD[1:0] for transmission. It is asserted synchronously with the first
dibit of the preamble and remains asserted while all dibits to be transmitted are presented on the RMII, and is negated
prior to the first REF_CLK following the final dibit of a frame.
TXEN transitions synchronously with respect to REF_CLK.
Transmit Data [1:0] (TXD[1:0])
TXD[1:0] transitions synchronously with respect to REF_CLK. When TXEN is asserted, TXD[1:0] are accepted for
transmission by the PHY.
TXD[1:0] is ”00” to indicate idle when TXEN is de-asserted. Values other than “00” on TXD[1:0] while TXEN is de-asserted
are ignored by the PHY.
Carrier Sense/Receive Data Valid (CRS_DV)
CRS_DV is asserted by the PHY when the receive medium is non-idle. It is asserted asynchronously on detection of
carrier. This is when squelch is passed in 10Mbps mode, and when 2 non-contiguous zeroes in 10 bits are detected in
100Mbps mode. Loss of carrier results in the de-assertion of CRS_DV.
So long as carrier detection criteria are met, CRS_DV remains asserted continuously from the first recovered dibit of the
frame through the final recovered dibit, and it is negated prior to the first REF_CLK that follows the final dibit. The data on
RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous
relative to REF_CLK, the data on RXD[1:0] is "00" until proper receive signal decoding takes place.
Receive Data [1:0] (RXD[1:0])
RXD[1:0] transitions synchronously with respect to REF_CLK. For each clock period in which CRS_DV is asserted,
RXD[1:0] transfers two bits of recovered data from the PHY.
RXD[1:0] is "00" to indicate idle when CRS_DV is de-asserted. Values other than “00” on RXD[1:0] while CRS_DV is deasserted are ignored by the MAC.
Receive Error (RXER)
RXER is asserted for one or more REF_CLK periods to indicate that a Symbol Error (e.g. a coding error that a PHY is
capable of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the
frame presently being transferred from the PHY.
RXER transitions synchronously with respect to REF_CLK. While CRS_DV is de-asserted, RX_ER has no effect on the
MAC.
Collision Detection
The MAC regenerates the COL signal of the MII from TXEN and CRS_DV.
RMII Signal Diagram
The KSZ8051RNL RMII pin connections to the MAC are shown in the following figures for 25MHz Clock Mode and 50MHz
Clock Mode.
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KSZ8051MNL/RNL
RMII – 25MHz Clock Mode
Figure 3. KSZ8051RNL RMII Interface (25MHz Clock Mode)
RMII – 50MHz Clock Mode
Figure 4. KSZ8051RNL RMII Interface (50MHz Clock Mode)
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KSZ8051MNL/RNL
Back-to-Back Mode – 100Mbps Copper Repeater / Media Converter
Two KSZ8051MNL/RNL devices can be connected back-to-back to form a 100Base-TX to 100Base-TX copper repeater.
A KSZ8051MNL/RNL and a KSZ8041FTL can be connected back-to-back to provide a low cost media converter solution.
Media conversion is between 100Base-TX copper and 100Base-FX fiber. On the copper side, link up at 10Base-T is not
allowed, and is blocked during auto-negotiation.
Figure 5. KSZ8051MNL/RNL and KSZ8041FTL Back-to-Back Media Converter
MII Back-to-Back Mode (KSZ8051MNL only)
In MII Back-to-Back mode, a KSZ8051MNL interfaces with another KSZ8051MNL, or a KSZ8041FTL to provide a
complete 100Mbps copper repeater, or media converter solution, respectively.
The KSZ8051MNL devices are configured to MII Back-to-Back mode after power-up or reset with the following:
•
Strapping pin CONFIG[2:0] (pins 18, 29, 28) set to ‘110’
•
A common 25MHz reference clock connected to XI (pin 9)
•
MII signals connected as shown in the following table.
KSZ8051MNL (100Base-TX copper)
KSZ8051MNL (100Base-TX copper)
[Device 1]
[Device 2]
Pin Name
Pin Number
Pin Type
Pin Name
Pin Number
Pin Type
RXC
19
Output
TXC
22
Input
RXDV
18
Output
TXEN
23
Input
RXD3
13
Output
TXD3
27
Input
RXD2
14
Output
TXD2
26
Input
RXD1
15
Output
TXD1
25
Input
RXD0
16
Output
TXD0
24
Input
TXC
22
Input
RXC
19
Output
TXEN
23
Input
RXDV
18
Output
TXD3
27
Input
RXD3
13
Output
TXD2
26
Input
RXD2
14
Output
TXD1
25
Input
RXD1
15
Output
TXD0
24
Input
RXD0
16
Output
Table 3. MII Signal Connection for MII Back-to-Back Mode (100Base-TX Copper Repeater)
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RMII Back-to-Back Mode (KSZ8051RNL only)
In RMII Back-to-Back mode, a KSZ8051RNL interfaces with another KSZ8051RNL, or a KSZ8041FTL to provide a
complete 100Mbps copper repeater, or media converter solution, respectively.
The KSZ8051RNL devices are configured to RMII Back-to-Back mode after power-up or reset with the following:
•
Strapping pin CONFIG[2:0] (pins 18, 29, 28) set to ‘101’
•
A common 50MHz reference clock connected to XI (pin 9)
•
RMII signals connected as shown in the following table.
KSZ8051RNL (100Base-TX copper)
KSZ8051RNL (100Base-TX copper)
[Device 1]
[Device 2]
Pin Name
Pin Number
Pin Type
Pin Name
Pin Number
Pin Type
CRSDV
18
Output
TXEN
23
Input
RXD1
15
Output
TXD1
25
Input
RXD0
16
Output
TXD0
24
Input
TXEN
23
Input
CRSDV
18
Output
TXD1
25
Input
RXD1
15
Output
TXD0
24
Input
RXD0
16
Output
Table 4. RMII Signal Connection for RMII Back-to-Back Mode (100Base-TX Copper Repeater)
MII Management (MIIM) Interface
The KSZ8051MNL/RNL supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input /
Output (MDIO) Interface. This interface enables upper-layer device, like a MAC processor, to monitor and control the state
of the KSZ8051MNL/RNL. An external device with MIIM capability is used to read the PHY status and/or configure the
PHY settings. Further details on the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3 Specification.
The MIIM interface consists of the following:
•
A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
•
A specific protocol that operates across the aforementioned physical connection that allows the external controller
to communicate with one or more PHY devices.
•
A set of 16-bit MDIO registers. Registers [0:8] are standard registers, and their functions are defined per the IEEE
802.3 Specification. The additional registers are provided for expanded functionality. See “Register Map” section
for details.
As the default, the KSZ8051MNL/RNL supports unique PHY addresses 1 to 7, and broadcast PHY address 0. The latter is
defined per the IEEE 802.3 Specification, and can be used to read/write to a single KSZ8051MNL/RNL device, or write to
multiple KSZ8051MNL/RNL devices simultaneously.
Optionally, PHY address 0 can be disabled as the broadcast address by either hardware pin strapping (B-CAST_OFF, pin
19) or software (register 16h, bit 9), and assigned as a unique PHY address.
The PHYAD[2:0] strapping pins are used to assigned a unique PHY address between 0 and 7 to each KSZ8051MNL/RNL
device.
The following table shows the MII Management frame format for the KSZ8051MNL/RNL.
Preamble
Start of
Frame
Read/Write
PHY
REG
OP Code
Address
Address
Bits [4:0]
Bits [4:0]
TA
Data
Idle
Bits [15:0]
Read
32 1’s
01
10
00AAA
RRRRR
Z0
DDDDDDDD_DDDDDDDD
Z
Write
32 1’s
01
01
00AAA
RRRRR
10
DDDDDDDD_DDDDDDDD
Z
Table 5. MII Management Frame Format – for KSZ8051MNL/RNL
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Interrupt (INTRP)
INTRP (pin 21) is an optional interrupt signal that is used to inform the external controller that there has been a status
update to the KSZ8051MNL/RNL PHY register. Register 1Bh, bits [15:8] are the interrupt control bits to enable and
disable the conditions for asserting the INTRP signal. Register 1Bh, bits [7:0] are the interrupt status bits to indicate which
interrupt conditions have occurred. The interrupt status bits are cleared after reading register 1Bh.
Register 1Fh, bit 9 sets the interrupt level to active high or active low. The default is active low.
The MII management bus option gives the MAC processor complete access to the KSZ8051MNL/RNL control and status
registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change.
HP Auto MDI/MDI-X
HP Auto MDI/MDI-X configuration eliminates the confusion of whether to use a straight cable or a crossover cable
between the KSZ8051MNL/RNL and its link partner. This feature allows the KSZ8051MNL/RNL to use either type of cable
to connect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and receive
pairs from the link partner, and then assigns transmit and receive pairs of the KSZ8051MNL/RNL accordingly.
HP Auto MDI/MDI-X is enabled by default. It is disabled by writing a one to register 1Fh, bit 13. MDI and MDI-X mode is
selected by register 1Fh, bit 14 if HP Auto MDI/MDI-X is disabled.
An isolation transformer with symmetrical transmit and receive data paths is recommended to support auto MDI/MDI-X.
The IEEE 802.3 Standard defines MDI and MDI-X as follows:
MDI
MDI-X
RJ-45 Pin
Signal
RJ-45 Pin
Signal
1
TX+
1
RX+
2
TX-
2
RX-
3
RX+
3
TX+
6
RX-
6
TX-
Table 6. MDI/MDI-X Pin Definition
Straight Cable
A straight cable connects a MDI device to a MDI-X device, or a MDI-X device to a MDI device. The following figure depicts
a typical straight cable connection between a NIC card (MDI) and a switch, or hub (MDI-X).
Figure 6. Typical Straight Cable Connection
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Crossover Cable
A crossover cable connects a MDI device to another MDI device, or a MDI-X device to another MDI-X device. The
following figure depicts a typical crossover cable connection between two switches or hubs (two MDI-X devices).
Figure 7. Typical Crossover Cable Connection
LinkMD® Cable Diagnostics
The LinkMD® function utilizes time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems,
such as open circuits, short circuits and impedance mismatches.
LinkMD® works by sending a pulse of known amplitude and duration down the MDI or MDI-X pair, and then analyzing the
shape of the reflected signal to determine the type of fault. The time duration for the reflected signal to return provides the
approximate distance to the cabling fault. The LinkMD® function processes this TDR information and presents it as a
numerical value that can be translated to a cable distance.
LinkMD® is initiated by accessing register 1Dh, the LinkMD® Control/Status Register, in conjunction with register 1Fh, the
PHY Control 2 Register. The latter register is used to disable auto MDI/MDI-X and to select either MDI or MDI-X as the
cable differential pair for testing.
NAND Tree Support
The KSZ8051MNL/RNL provides parametric NAND tree support for fault detection between chip I/Os and board. The
NAND tree is a chain of nested NAND gates in which each KSZ8051MNL/RNL digital I/O (NAND tree input) pin is an input
to one NAND gate along the chain. At the end of the chain, the CRS/CONFIG1 pin provides the output for the nested
NAND gates.
The NAND tree test process includes:
•
Enabling NAND tree mode
•
Pulling all NAND tree input pins high
•
Driving low each NAND tree input pin sequentially per the NAND tree pin order
•
Checking the NAND tree output to ensure there is a toggle high-to-low or low-to-high for each NAND tree input
driven low
The following tables list the NAND tree pin order.
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Pin Number
Pin Name
NAND Tree
Description
11
MDIO
Input
12
MDC
Input
13
RXD3
Input
14
RXD2
Input
15
RXD1
Input
16
RXD0
Input
18
RXDV
Input
19
RXC
Input
20
RXER
Input
21
INTRP
Input
22
TXC
Input
23
TXEN
Input
24
TXD0
Input
25
TXD1
Input
26
TXD2
Input
27
TXD3
Input
30
LED0
Input
31
LED1
Input
28
COL
Input
29
CRS
Output
Table 7. NAND Tree Test Pin Order – for KSZ8051MNL
Pin Number
Pin Name
NAND Tree
Description
11
MDIO
Input
12
MDC
Input
13
PHYAD0
Input
14
PHYAD1
Input
15
RXD1
Input
16
RXD0
Input
18
CRS_DV
Input
19
REF_CLK
Input
20
RXER
Input
21
INTRP
Input
23
TXEN
Input
24
TXD0
Input
25
TXD1
Input
30
LED0
Input
31
LED1
Input
28
CONFIG0
Input
29
CONFIG1
Output
Table 8. NAND Tree Test Pin Order – for KSZ8051RNL
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NAND Tree I/O Testing
The following procedure can be used to check for faults on the KSZ8051MNL/RNL digital I/O pin connections to the
board:
1. Enable NAND tree mode by either hardware pin strapping (NAND_Tree#, pin 21) or software (register 16h, bit 5).
2. Use board logic to drive all KSZ8051MNL/RNL NAND tree input pins high.
3. Use board logic to drive each NAND tree input pin, per KSZ8051MNL/RNL NAND Tree pin order, as follow:
a. Toggle the first pin (MDIO) from high to low, and verify the CRS/CONFIG1 pin switch from low to high to
indicate that the first pin is connected properly.
b. Leave the first pin (MDIO) low.
c. Toggle the second pin (MDC) from high to low, and verify the CRS/CONFIG1 pin switch from high to low
to indicate that the second pin is connected properly.
d. Leave the first pin (MDIO) and the second pin (MDC) low.
e. Toggle the third pin from high to low, and verify the CRS/CONFIG1 pin switch from low to high to indicate
that the third pin is connected properly.
f. Continue with this sequence until all KSZ8051MNL/RNL NAND tree input pins have been toggled.
Each KSZ8051MNL/RNL NAND tree input pin must cause the CRS/CONFIG1 output pin to toggle high-to-low or low-tohigh to indicate a good connection. If the CRS/CONFIG1 pin fails to toggle when the KSZ8051MNL/RNL input pin toggles
from high to low, the input pin has a fault.
Power Management
The KSZ8051MNL/RNL offers the following power management modes:
Power Saving Mode
Power Saving Mode is used to reduce the transceiver power consumption when the cable is unplugged. It is enabled by
writing a one to register 1Fh, bit 10, and is in effect when auto-negotiation mode is enabled and cable is disconnected (no
link).
In this mode, the KSZ8051MNL/RNL shuts down all transceiver blocks, except for transmitter, energy detect and PLL
circuits.
By default, Power Saving Mode is disabled after power-up.
Energy Detect Power Down Mode
Energy Detect Power Down Mode is used to further reduce the transceiver power consumption when the cable is unplugged. It is enabled by writing a zero to register 18h, bit 11, and is in effect when auto-negotiation mode is enabled and
cable is disconnected (no link).
In this mode, the KSZ8051MNL/RNL shuts down all transceiver blocks, except for transmitter and energy detect circuits.
Further power consumption is achieved by extending the time interval in between transmissions of link pulses to check for
the presence of a link partner. The periodic transmission of link pulses is needed to ensure two link partners in the same
low power state and with auto MDI/MDI-X disabled can wake up when the cable is connected between them.
By default, Energy Detect Power Down Mode is disabled after power-up.
Power Down Mode
Power Down Mode is used to power down the KSZ8051MNL/RNL device when it is not in use after power-up. It is
enabled by writing a one to register 0h, bit 11.
In this mode, the KSZ8051MNL/RNL disables all internal functions, except for the MII management interface. The
KSZ8051MNL/RNL exits (disables) Power Down Mode after register 0h, bit 11 is set back to zero.
Slow Oscillator Mode
Slow Oscillator Mode is used to disconnect the input reference crystal/clock on XI (pin 9) and select the on-chip slow
oscillator when the KSZ8051MNL/RNL device is not in use after power-up. It is enabled by writing a one to register 11h,
bit 5.
Slow Oscillator Mode works in conjunction with Power Down Mode to put the KSZ8051MNL/RNL device in the lowest
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power state with all internal functions disabled, except for the MII management interface. To properly exit this mode and
return to normal PHY operation, use the following programming sequence:
1. Disable Slow Oscillator Mode by writing a zero to register 11h, bit 5.
2. Disable Power Down Mode by writing a zero to register 0h, bit 11.
3. Initiate software reset by writing a one to register 0h, bit 15.
Reference Circuit for Power and Ground Connections
The KSZ8051MNL/RNL is a single 3.3V supply device with a built-in regulator to supply the 1.2V core. The power and
ground connections are shown in the following figure and table for 3.3V VDDIO.
Figure 8. KSZ8051MNL/RNL Power and Ground Connections
Power Pin
Pin Number
Description
VDD_1.2
2
Decouple with 2.2uF and 0.1uF capacitors-to-ground.
VDDA_3.3
3
Connect to board’s 3.3V supply through ferrite bead.
Decouple with 22uF and 0.1uF capacitors-to-ground.
VDDIO
17
Connect to board’s 3.3V supply for 3.3V VDDIO.
Decouple with 22uF and 0.1uF capacitors-to-ground.
Table 9. KSZ8051MNL/RNL Power Pin Description
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Register Map
Register Number (Hex)
Description
0h
Basic Control
1h
Basic Status
2h
PHY Identifier 1
3h
PHY Identifier 2
4h
Auto-Negotiation Advertisement
5h
Auto-Negotiation Link Partner Ability
6h
Auto-Negotiation Expansion
7h
Auto-Negotiation Next Page
8h
Link Partner Next Page Ability
9h – 10h
Reserved
11h
AFE Control 1
12h – 14h
Reserved
15h
RXER Counter
16h
Operation Mode Strap Override
17h
Operation Mode Strap Status
18h
Expanded Control
19h – 1Ah
Reserved
1Bh
Interrupt Control/Status
1Ch
Reserved
1Dh
LinkMD® Control/Status
1Eh
PHY Control 1
1Fh
PHY Control 2
Register Description
Address
Name
(1)
Description
Mode
Default
1 = Software reset
RW/SC
0
RW
0
RW
Set by SPEED strapping pin.
Register 0h – Basic Control
0.15
Reset
0 = Normal operation
This bit is self-cleared after a ‘1’ is written to it.
0.14
Loop-back
1 = Loop-back mode
0 = Normal operation
0.13
Speed Select
1 = 100Mbps
See “Strapping Options” section
for details.
0 = 10Mbps
This bit is ignored if auto-negotiation is enabled
(register 0.12 = 1).
0.12
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AutoNegotiation
Enable
1 = Enable auto-negotiation process
0 = Disable auto-negotiation process
If enabled, auto-negotiation result overrides
settings in register 0.13 and 0.8.
34
RW
Set by NWAYEN strapping pin.
See “Strapping Options” section
for details.
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KSZ8051MNL/RNL
Register Description (Continued)
Address
Name
(1)
Description
Mode
Default
1 = Power down mode
RW
0
RW
Set by ISO strapping pin.
Register 0h – Basic Control
0.11
Power Down
0 = Normal operation
If software reset (register 0.15) is used to exit
Power Down mode (register 0.11 = 1), two
software reset writes (register 0.15 = 1) are
required. First write clears Power Down mode;
second write resets chip and re-latches the pin
strapping pin values.
0.10
Isolate
1 = Electrical isolation of PHY from MII
See “Strapping Options” section
for details.
0 = Normal operation
0.9
Restart AutoNegotiation
1 = Restart auto-negotiation process
RW/SC
0
RW
Inverse of DUPLEX strapping pin
value.
0 = Normal operation.
This bit is self-cleared after a ‘1’ is written to it.
0.8
Duplex Mode
1 = Full-duplex
0 = Half-duplex
See “Strapping Options” section
for details.
0.7
Collision Test
1 = Enable COL test
RW
0
RO
000_0000
RO
0
RO
1
RO
1
RO
1
RO
1
RO
0000
RO
1
RO
0
RO/LH
0
RO
1
0 = Disable COL test
0.6:0
Reserved
Register 1h – Basic Status
1.15
100Base-T4
1 = T4 capable
0 = Not T4 capable
100Base-TX
Full Duplex
1 = Capable of 100Mbps full-duplex
1.13
100Base-TX
Half Duplex
1 = Capable of 100Mbps half-duplex
1.12
10Base-T Full
Duplex
1 = Capable of 10Mbps full-duplex
10Base-T Half
Duplex
1 = Capable of 10Mbps half-duplex
1.14
1.11
1.10:7
Reserved
1.6
No Preamble
0 = Not capable of 100Mbps full-duplex
0 = Not capable of 100Mbps half-duplex
0 = Not capable of 10Mbps full-duplex
0 = Not capable of 10Mbps half-duplex
1 = Preamble suppression
0 = Normal preamble
1.5
1.4
AutoNegotiation
Complete
Remote Fault
1 = Auto-negotiation process completed
0 = Auto-negotiation process not completed
1 = Remote fault
0 = No remote fault
1.3
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AutoNegotiation
Ability
1 = Capable to perform auto-negotiation
0 = Not capable to perform auto-negotiation
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Register Description (Continued)
(1)
Address
Name
Description
Mode
Default
1.2
Link Status
1 = Link is up
RO/LL
0
1.1
Jabber Detect
RO/LH
0
1 = Supports extended capabilities registers
RO
1
Assigned to the 3rd through 18th bits of the
Organizationally Unique Identifier (OUI).
Kendin Communication’s OUI is 0010A1 (hex)
RO
0022h
Assigned to the 19th through 24th bits of the
Organizationally Unique Identifier (OUI).
Kendin Communication’s OUI is 0010A1 (hex)
RO
0001_01
Six bit manufacturer’s model number
RO
01_0101
Four bit manufacturer’s revision number
RO
Indicates silicon revision
RW
0
RO
0
RW
0
RO
0
RW
00
RO
0
RW
Set by SPEED strapping pin.
0 = Link is down
1 = Jabber detected
0 = Jabber not detected (default is low)
1.0
Extended
Capability
Register 2h – PHY Identifier 1
2.15:0
PHY ID
Number
Register 3h – PHY Identifier 2
3.15:10
PHY ID
Number
3.9:4
Model Number
3.3:0
Revision
Number
Register 4h – Auto-Negotiation Advertisement
4.15
Next Page
1 = Next page capable
0 = No next page capability.
4.14
Reserved
4.13
Remote Fault
1 = Remote fault supported
0 = No remote fault
4.12
Reserved
4.11:10
Pause
[00] = No PAUSE
[10] = Asymmetric PAUSE
[01] = Symmetric PAUSE
[11] = Asymmetric & Symmetric PAUSE
4.9
100Base-T4
1 = T4 capable
0 = No T4 capability
4.8
4.7
4.6
4.5
4.4:0
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100Base-TX
Full-Duplex
1 = 100Mbps full-duplex capable
100Base-TX
Half-Duplex
1 = 100Mbps half-duplex capable
10Base-T
Full-Duplex
1 = 10Mbps full-duplex capable
10Base-T
Half-Duplex
1 = 10Mbps half-duplex capable
Selector Field
See “Strapping Options” section
for details.
0 = No 100Mbps full-duplex capability
RW
Set by SPEED strapping pin.
See “Strapping Options” section
for details.
0 = No 100Mbps half-duplex capability
RW
1
RW
1
RW
0_0001
0 = No 10Mbps full-duplex capability
0 = No 10Mbps half-duplex capability
[00001] = IEEE 802.3
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Register Description (Continued)
Address
Name
(1)
Description
Mode
Default
RO
0
RO
0
RO
0
RO
0
RO
00
RO
0
RO
0
RO
0
RO
0
RO
0
RO
0_0001
RO
0000_0000_000
RO/LH
0
RO
0
RO
1
RO/LH
0
RO
0
Register 5h – Auto-Negotiation Link Partner Ability
5.15
Next Page
1 = Next page capable
0 = No next page capability
5.14
Acknowledge
1 = Link code word received from partner
0 = Link code word not yet received
5.13
Remote Fault
5.12
Reserved
5.11:10
Pause
1 = Remote fault detected
0 = No remote fault
[00] = No PAUSE
[10] = Asymmetric PAUSE
[01] = Symmetric PAUSE
[11] = Asymmetric & Symmetric PAUSE
5.9
100Base-T4
1 = T4 capable
5.8
100Base-TX
Full-Duplex
1 = 100Mbps full-duplex capable
100Base-TX
Half-Duplex
1 = 100Mbps half-duplex capable
5.6
10Base-T
Full-Duplex
1 = 10Mbps full-duplex capable
5.5
10Base-T
Half-Duplex
1 = 10Mbps half-duplex capable
0 = No T4 capability
5.7
5.4:0
Selector Field
0 = No 100Mbps full-duplex capability
0 = No 100Mbps half-duplex capability
0 = No 10Mbps full-duplex capability
0 = No 10Mbps half-duplex capability
[00001] = IEEE 802.3
Register 6h – Auto-Negotiation Expansion
6.15:5
Reserved
6.4
Parallel
Detection Fault
6.3
6.2
6.1
1 = Fault detected by parallel detection
0 = No fault detected by parallel detection
Link Partner
Next Page
Able
1 = Link partner has next page capability
Next Page
Able
1 = Local device has next page capability
Page Received
0 = Link partner does not have next page
capability
0 = Local device does not have next page
capability
1 = New page received
0 = New page not received yet
6.0
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Link Partner
AutoNegotiation
Able
1 = Link partner has auto-negotiation capability
0 = Link partner does not have auto-negotiation
capability
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Register Description (Continued)
Address
Name
(1)
Description
Mode
Default
RW
0
RO
0
RW
1
RW
0
RO
0
RW
000_0000_0001
RO
0
RO
0
RO
0
RO
0
RO
0
RO
000_0000_0000
RW
0000_0000_00
RW
0
RW
0_0000
RO/SC
0000h
Register 7h – Auto-Negotiation Next Page
7.15
Next Page
1 = Additional next page(s) will follow
0 = Last page
7.14
Reserved
7.13
Message Page
1 = Message page
0 = Unformatted page
7.12
Acknowledge2
7.11
Toggle
7.10:0
Message Field
1 = Will comply with message
0 = Cannot comply with message
1 = Previous value of the transmitted link code
word equaled logic one
0 = Logic zero
11-bit wide field to encode 2048 messages
Register 8h – Link Partner Next Page Ability
8.15
Next Page
1 = Additional Next Page(s) will follow
0 = Last page
8.14
Acknowledge
8.13
Message Page
1 = Successful receipt of link word
0 = No successful receipt of link word
1 = Message page
0 = Unformatted page
8.12
Acknowledge2
1 = Able to act on the information
0 = Not able to act on the information
8.11
Toggle
1 = Previous value of transmitted link code
word equal to logic zero
0 = Previous value of transmitted link code
word equal to logic one
8.10:0
Message Field
Register 11h – AFE Control 1
11.15:6
Reserved
11.5
Slow Oscillator
Mode Enable
Slow Oscillator Mode is used to disconnect the
input reference crystal/clock on the XI pin and
select the on-chip slow oscillator when the
KSZ8051 device is not in use after power-up.
1 = Enable
0 = Disable
This bit automatically sets software power down
to the analog side when enabled.
11.4:0
Reserved
Register 15h – RXER Counter
15.15:0
July 2010
RXER Counter
Receive error counter for Symbol Error frames
38
M9999-070910-1.0
Micrel, Inc.
KSZ8051MNL/RNL
Register Description (Continued)
Address
Name
(1)
Description
Mode
Default
Register 16h – Operation Mode Strap Override
16.15:11
Reserved
RW
0000_0
16.10
Reserved
RO
0
16.9
B-CAST_OFF
override
RW
0
16.8
Reserved
RW
0
16.7
MII B-to-B
override
RW
0
RW
0
RW
0
RW
000
RW
0
RW
1
1 = Override strap-in for B-CAST_OFF
If bit is ‘1’, PHY Address 0 is non-broadcast.
1 = Override strap-in for MII Back-to-Back
mode (set also bit 0 of this register to 1)
This bit is applicable for KSZ8051MNL only.
16.6
RMII B-to-B
override
1 = Override strap-in for RMII Back-to-Back
mode (set also bit 1 of this register to 1)
This bit is applicable for KSZ8051RNL only.
16.5
NAND Tree
override
16.4:2
Reserved
16.1
RMII override
1 = Override strap-in for NAND Tree mode
1 = Override strap-in for RMII mode
This bit is applicable for KSZ8051RNL only.
16.0
MII override
1 = Override strap-in for MII mode
This bit is applicable for KSZ8051MNL only.
Register 17h – Operation Mode Strap Status
17.15:13
PHYAD[2:0]
strap-in status
RO
[000] = Strap to PHY Address 0
[001] = Strap to PHY Address 1
[010] = Strap to PHY Address 2
[011] = Strap to PHY Address 3
[100] = Strap to PHY Address 4
[101] = Strap to PHY Address 5
[110] = Strap to PHY Address 6
[111] = Strap to PHY Address 7
17.12:10
Reserved
17.9
B-CAST_OFF
strap-in status
RO
1 = Strap to B-CAST_OFF
RO
If bit is ‘1’, PHY Address 0 is non-broadcast.
17.8
Reserved
17.7
MII B-to-B
strap-in status
1 = Strap to MII Back-to-Back mode
17.6
RMII B-to-B
strap-in status
1 = Strap to RMII Back-to-Back mode
17.5
NAND Tree
strap-in status
1 = Strap to NAND Tree mode
RO
17.4:2
Reserved
17.1
RMII
strap-in status
1 = Strap to RMII mode
RO
MII
strap-in status
1 = Strap to MII mode
17.0
July 2010
RO
RO
This bit is applicable for KSZ8051MNL only.
RO
This bit is applicable for KSZ8051RNL only.
RO
This bit is applicable for KSZ8051RNL only.
RO
This bit is applicable for KSZ8051MNL only.
39
M9999-070910-1.0
Micrel, Inc.
KSZ8051MNL/RNL
Register Description (Continued)
Address
Name
(1)
Description
Mode
Default
RW
0000
RW
1
RW
0
RW
000
RW
0
RW
00_0000
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RO/SC
0
RO/SC
0
Register 18h – Expanded Control
18.15:12
Reserved
18.11
EDPD
Disabled
Energy Detect Power Down mode
1 = Disable
0 = Enable
18.10
100Base-TX
Preamble
Restore
1 = Restore received preamble to MII output
(random latency)
0 = Consume 1-byte preamble before sending
frame to MII output for fixed latency
This bit is applicable for KSZ8051MNL only.
18.9:7
Reserved
18.6
10Base-T
Preamble
Restore
1 = Restore received preamble to MII output
0 = Remove all 7-bytes of preamble before
sending frame (starting with SFD) to MII
output
This bit is applicable for KSZ8051MNL only.
18.5:0
Reserved
Register 1Bh – Interrupt Control/Status
1b.15
1b.14
1b.13
1b.12
1b.11
1b.10
1b.9
1b.8
1b.7
1b.6
July 2010
Jabber
Interrupt
Enable
Receive Error
Interrupt
Enable
1 = Enable Jabber Interrupt
0 = Disable Jabber Interrupt
1 = Enable Receive Error Interrupt
0 = Disable Receive Error Interrupt
Page Received
Interrupt
Enable
1 = Enable Page Received Interrupt
Parallel Detect
Fault Interrupt
Enable
1 = Enable Parallel Detect Fault Interrupt
Link Partner
Acknowledge
Interrupt
Enable
1 = Enable Link Partner Acknowledge Interrupt
Link Down
Interrupt
Enable
Remote Fault
Interrupt
Enable
0 = Disable Page Received Interrupt
0 = Disable Parallel Detect Fault Interrupt
0 = Disable Link Partner Acknowledge
Interrupt
1= Enable Link Down Interrupt
0 = Disable Link Down Interrupt
1 = Enable Remote Fault Interrupt
0 = Disable Remote Fault Interrupt
Link Up
Interrupt
Enable
1 = Enable Link Up Interrupt
Jabber
Interrupt
1 = Jabber occurred
Receive Error
Interrupt
0 = Disable Link Up Interrupt
0 = Jabber did not occurred
1 = Receive Error occurred
0 = Receive Error did not occurred
40
M9999-070910-1.0
Micrel, Inc.
KSZ8051MNL/RNL
Register Description (Continued)
Address
Name
1b.5
1b.4
1b.3
1b.2
1b.1
1b.0
(1)
Description
Mode
Default
Page Receive
Interrupt
1 = Page Receive occurred
RO/SC
0
Parallel Detect
Fault Interrupt
1 = Parallel Detect Fault occurred
RO/SC
0
Link Partner
Acknowledge
Interrupt
1 = Link Partner Acknowledge occurred
RO/SC
0
RO/SC
0
RO/SC
0
RO/SC
0
RW/SC
0
RO
00
RO
0
RW
000
RO
0_0000_0000
RO
0000_00
RO
0
RO
0
Link Down
Interrupt
Remote Fault
Interrupt
Link Up
Interrupt
0 = Page Receive did not occur
0 = Parallel Detect Fault did not occur
0 = Link Partner Acknowledge did not occur
1 = Link Down occurred
0 = Link Down did not occur
1 = Remote Fault occurred
0 = Remote Fault did not occur
1 = Link Up occurred
0 = Link Up did not occur
®
Register 1Dh – LinkMD Control/Status
1d.15
1d.14:13
Cable
Diagnostic
Test Enable
1 = Enable cable diagnostic test. After test
has completed, this bit is self-cleared.
Cable
Diagnostic
Test Result
[00] = normal condition
0 = Indicates cable diagnostic test (if enabled)
has completed and the status information
is valid for read.
[01] = open condition has been detected in
cable
[10] = short condition has been detected in
cable
[11] = cable diagnostic test has failed
1d.12
Short Cable
Indicator
1d.11:9
Reserved
1d.8:0
Cable Fault
Counter
1 = Short cable (