KSZ9021GQ
Gigabit Ethernet Transceiver with GMII/MII Support
Highlights
Applications
• Single-chip 10/100/1000Mbps IEEE 802.3 compliant Ethernet Transceiver
• GMII/MII standard compliant interface
• Auto-negotiation to automatically select the highest link up speed (10/100/100Mbps) and duplex
(half/full)
• On-chip termination resistors for the differential
pairs
• On-chip LDO controller to support single 3.3V
supply operation – requires only external FET to
generate 1.2V for the core
• Jumbo frame support up to 16KB
• 125MHz Reference Clock Output
• Programmable LED outputs for link, activity and
speed
• Baseline Wander Correction
• LinkMD® TDR-based cable diagnostics for identification of faulty copper cabling
• Parametric NAND Tree support for fault detection
between chip I/Os and board.
• Loopback modes for diagnostics
• Automatic MDI/MDI-X crossover for detection and
correction of pair swap at all speeds of operation
• Automatic detection and correction of pair swaps,
pair skew and pair polarity
• MDC/MDIO Management Interface for PHY register configuration
• Interrupt pin option
• Power down and power saving modes
• Operating Voltages
- Core:
1.2V (external FET or regulator)
- I/O:
3.3V or 2.5V
- Transceiver: 3.3V
• Available in 128-pin PQFP (14mm x 20mm) package
•
•
•
•
•
•
•
•
•
•
•
2009-2019 Microchip Technology Inc.
Laser/Network Printer
Network Attached Storage (NAS)
Network Server
Gigabit LAN on Motherboard (GLOM)
Broadband Gateway
Gigabit SOHO/SMB Router
IPTV
IP Set-top Box
Game Console
Triple-play (data, voice, video) Media Center
Media Converter
DS00003115A-page 1
KSZ9021GQ
TO OUR VALUED CUSTOMERS
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To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the
revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are
using.
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DS00003115A-page 2
2009-2019 Microchip Technology Inc.
KSZ9021GQ
Table of Contents
1.0 Introduction ..................................................................................................................................................................................... 4
2.0 Pin Description and Configuration .................................................................................................................................................. 5
3.0 Functional Overview ..................................................................................................................................................................... 18
4.0 Register Map ................................................................................................................................................................................. 33
5.0 Operational Characteristics ........................................................................................................................................................... 44
6.0 Timing Diagrams ........................................................................................................................................................................... 47
7.0 Package Information ..................................................................................................................................................................... 57
Appendix A: Data Sheet Revision History ........................................................................................................................................... 58
The Microchip Web Site ...................................................................................................................................................................... 59
Customer Change Notification Service ............................................................................................................................................... 59
Customer Support ............................................................................................................................................................................... 59
Product Identification System ............................................................................................................................................................. 60
2009-2019 Microchip Technology Inc.
DS00003115A-page 3
KSZ9021GQ
1.0
INTRODUCTION
1.1
General Description
The KSZ9021GQ is a completely integrated triple speed (10Base-T/100Base-TX/1000Base-T) Ethernet Physical Layer
Transceiver for transmission and reception of data on standard CAT-5 unshielded twisted pair (UTP) cable.
The KSZ9021GQ provides the industry standard GMII/MII (Gigabit Media Independent Interface / Media Independent
Interface) for direct connection to GMII/MII MACs in Gigabit Ethernet Processors and Switches for data transfer at 1000
Mbps or 10/100Mbps speed.
The KSZ9021GQ reduces board cost and simplifies board layout by using on-chip termination resistors for the four differential pairs and by integrating a LDO controller to drive a low cost MOSFET to supply the 1.2V core.
The KSZ9021GQ provides diagnostic features to facilitate system bring-up and debugging in production testing and in
product deployment. Parametric NAND tree support enables fault detection between KSZ9021 I/Os and board. Microchip LinkMD® TDR-based cable diagnostics permit identification of faulty copper cabling. Remote and local loopback
functions provide verification of analog and digital data paths.
The KSZ9021GQ is available in a 128-pin, RoHS Compliant PQFP package (See Product Identification System on page
60).
Functional Diagram
MII /
GMII
10/100/1000 Mbps
MII / GMII
ETHERNET MAC
KSZ9021GQ
MDC / MDIO
MANAGEMENT
RJ-45
CONNECTOR
KSZ9021GQ FUNCTIONAL DIAGRAM
MAGNETICS
FIGURE 1-1:
ON-CHIP TERMINATION
RESISTORS
1.2
MEDIA TYPES:
10BASE-T
100BASE-TX
1000BASE-T
LDO
CONTROLLER
VIN
3.3VA
DS00003115A-page 4
VOUT
1.2V (for core voltages )
2009-2019 Microchip Technology Inc.
KSZ9021GQ
2.0
PIN DESCRIPTION AND CONFIGURATION
2.1
Pin Diagram
128-PIN PQFP (TOP VIEW)
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
VSS
INT_N
DVDDH
COL
MDIO
MDC
CRS
VSSPST
RX_CLK
RX_ER
DVDDH
VSSPST
RX_DV / CLK125_EN
RXD0 / MODE0
RXD1 / MODE1
DVDDL
DVDDL
VSS
VSS
RXD2 / MODE2
DVDDH
DVDDH
VSSPST
VSSPST
RXD3 / MODE3
RXD4
RXD5
DVDDL
DVDDL
RXD6
VSS
VSS
RXD7
DVDDH
DVDDH
TX_EN
VSSPST
GTX_CLK
FIGURE 2-1:
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
TX_ER
DVDDH
VSSPST
TXD7
TXD6
TXD5
TXD4
DVDDH
DVDDL
VSS
TXD3
TXD2
TXD1
TXD0
VSS
DVDDL
LED1 / PHYAD0
VSSPST
DVDDH
LED2 / PHYAD1
LED3 / PHYAD2
LED4 / PHYAD3
LED5 / PHYAD4
VSS
VSS
DVDDL
NC
NC
NC
NC
NC
NC
TXRXP_A
TXRXM_A
AVDDH
AGNDH
AGNDL_ADC_A
AVDDL
AVDDL
AGNDL_ADC_B
AGNDH
AVDDH
TXRXP_B
TXRXM_B
AGNDH
TXRXP_C
TXRXM_C
AVDDH
AGNDH
AGNDL_ADC_C
AVDDL
AVDDL
AGNDL_ADC_D
AGNDH
AVDDH
TXRXP_D
TXRXM_D
AVDDH
NC
NC
NC
NC
NC
LED6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
DVDDL
VSS
DVDDL
DVDDH
CLK125_NDO
VSSPST
VSSPST
RESET_N
NC
NC
VSS
DVDDL
TX_CLK
A1
AGNDH
LDO_O
AGNDL _PLL
AVDDL_PLL
AVDDL_PLL
AVDDH
XO
XI
AVDDH
ISET
AGNDH_BG
AVDDH
2009-2019 Microchip Technology Inc.
DS00003115A-page 5
KSZ9021GQ
2.2
Pin Description
Pin
Number
Pin Name
Type
(Note 1)
1
NC
-
No connect
2
NC
-
No connect
3
NC
-
No connect
4
NC
-
No connect
5
NC
-
No connect
6
NC
-
No connect
7
TXRXP_A
I/O
Pin Function
Media Dependent Interface[0], positive signal of differential pair
1000Base-T Mode:
TXRXP_A corresponds to BI_DA+ for MDI configuration and
BI_DB+ for MDI-X configuration, respectively.
10Base-T / 100Base-TX Mode:
TXRXP_A is the positive transmit signal (TX+) for MDI configuration
and the positive receive signal (RX+) for MDI-X configuration,
respectively.
8
TXRXM_A
I/O
Media Dependent Interface[0], negative signal of differential pair
1000Base-T Mode:
TXRXM_A corresponds to BI_DA- for MDI configuration and
BI_DB- for MDI-X configuration, respectively.
10Base-T / 100Base-TX Mode:
TXRXM_A is the negative transmit signal (TX-) for MDI configuration and the negative receive signal (RX-) for MDI-X configuration,
respectively.
9
AVDDH
P
10
AGNDH
Gnd
3.3V analog VDD
Analog ground
11
AGNDL_ADC_A
Gnd
Analog ground
12
AVDDL
P
1.2V analog VDD
13
AVDDL
P
14
AGNDL_ADC_B
Gnd
Analog ground
1.2V analog VDD
15
AGNDH
Gnd
Analog ground
16
AVDDH
P
17
TXRXP_B
I/O
3.3V analog VDD
Media Dependent Interface[1], positive signal of differential pair
1000Base-T Mode:
TXRXP_B corresponds to BI_DB+ for MDI configuration and
BI_DA+ for MDI-X configuration, respectively.
10Base-T / 100Base-TX Mode:
TXRXP_B is the positive receive signal (RX+) for MDI configuration
and the positive transmit signal (TX+) for MDI-X configuration,
respectively.
DS00003115A-page 6
2009-2019 Microchip Technology Inc.
KSZ9021GQ
Pin
Number
Pin Name
Type
(Note 1)
18
TXRXM_B
I/O
Pin Function
Media Dependent Interface[1], negative signal of differential pair
1000Base-T Mode:
TXRXM_B corresponds to BI_DB- for MDI configuration and
BI_DA- for MDI-X configuration, respectively.
10Base-T / 100Base-TX Mode:
TXRXM_B is the negative receive signal (RX-) for MDI configuration
and the negative transmit signal (TX-) for MDI-X configuration,
respectively.
19
AGNDH
Gnd
Analog ground
20
TXRXP_C
I/O
Media Dependent Interface[2], positive signal of differential pair
1000Base-T Mode:
TXRXP_C corresponds to BI_DC+ for MDI configuration and
BI_DD+ for MDI-X configuration, respectively.
10Base-T / 100Base-TX Mode:
TXRXP_C is not used.
21
TXRXM_C
I/O
Media Dependent Interface[2], negative signal of differential pair
1000Base-T Mode:
TXRXM_C corresponds to BI_DC- for MDI configuration and
BI_DD- for MDI-X configuration, respectively.
10Base-T / 100Base-TX Mode:
TXRXM_C is not used.
22
AVDDH
P
3.3V analog VDD
23
AGNDH
Gnd
Analog ground
24
AGNDL_ADC_C
Gnd
Analog ground
25
AVDDL
P
1.2V analog VDD
26
AVDDL
P
1.2V analog VDD
27
AGNDL_ADC_D
Gnd
28
AGNDH
Gnd
29
AVDDH
P
30
TXRXP_D
I/O
Analog ground
Analog ground
3.3V analog VDD
Media Dependent Interface[3], positive signal of differential pair
1000Base-T Mode:
TXRXP_D corresponds to BI_DD+ for MDI configuration and
BI_DC+ for MDI-X configuration, respectively.
10Base-T / 100Base-TX Mode:
TXRXP_D is not used.
31
TXRXM_D
I/O
Media Dependent Interface[3], negative signal of differential pair
1000Base-T Mode:
TXRXM_D corresponds to BI_DD- for MDI configuration and
BI_DC- for MDI-X configuration, respectively.
10Base-T / 100Base-TX Mode:
TXRXM_D is not used.
32
AVDDH
P
3.3V analog VDD
33
NC
-
No connect
34
NC
-
No connect
35
NC
-
No connect
36
NC
-
No connect
2009-2019 Microchip Technology Inc.
DS00003115A-page 7
KSZ9021GQ
Pin
Number
Pin Name
Type
(Note 1)
37
NC
-
No connect
38
LED6
I/O
LED Output:
Pin Function
Programmable LED6 Output
The LED6 pin is programmed via register 11h bits [7:6], LED_SEL[1:0],
and is defined as followed:
LED_SEL[1:0] = (1,1)
LED_SEL[1:0] = (0,1)
// 6-LED Configuration (default)
// 5-LED Configuration
10Base-T-Link
Pin State
Link off
H
OFF
Link on
L
ON
LED_SEL[1:0] = (1,0)
// 4-LED Configuration
10Base-T-Link /
Activity
Link off
Pin State
LED Definition
H
OFF
Link on
L
ON
Activity (RX, TX)
Toggle
Blinking
LED_SEL[1:0] = (0,0)
39
DVDDL
P
40
VSS
Gnd
Digital ground
41
VSS
Gnd
Digital ground
DS00003115A-page 8
LED Definition
// Reserved – not used
1.2V digital VDD
2009-2019 Microchip Technology Inc.
KSZ9021GQ
Pin
Number
42
Pin Name
Type
(Note 1)
LED5 /
PHYAD4
I/O
Pin Function
LED Output:
Programmable LED5 Output /
Configuration Mode:
The pull-up/pull-down value is latched as PHYADD[4]
during power-up / reset. See “Strapping Options” section for details.
The LED5 pin is programmed via register 11h bits [7:6], LED_SEL[1:0],
and is defined as followed:
LED_SEL[1:0] = (1,1)
LED_SEL[1:0] = (0,1)
// 6-LED Configuration (default)
// 5-LED Configuration
100Base-T-Link
Pin State
Link off
H
OFF
Link on
L
ON
LED_SEL[1:0] = (1,0)
// 4-LED Configuration
100Base-T-Link /
Activity
Pin State
LED4 /
PHYAD3
I/O
LED Definition
Link off
H
OFF
Link on
L
ON
Activity (RX, TX)
Toggle
Blinking
LED_SEL[1:0] = (0,0)
43
LED Definition
// Reserved – not used
LED Output:
Programmable LED4 Output /
Configuration Mode:
The pull-up/pull-down value is latched as PHYADD[3] during powerup / reset. See “Strapping Options” section for details.
The LED4 pin is programmed via register 11h bits [7:6], LED_SEL[1:0],
and is defined as follows:
LED_SEL[1:0] = (1,1)
LED_SEL[1:0] = (0,1)
// 6-LED Configuration (default)
// 5-LED Configuration
1000Base-T-Link
Pin State
Link off
H
OFF
Link on
L
ON
LED_SEL[1:0] = (1,0)
// 4-LED Configuration
1000Base-T-Link /
Activity
Pin State
LED Definition
Link off
H
OFF
Link on
L
ON
Activity (RX, TX)
Toggle
Blinking
LED_SEL[1:0] = (0,0)
2009-2019 Microchip Technology Inc.
LED Definition
// Reserved – not used
DS00003115A-page 9
KSZ9021GQ
Pin
Number
44
Pin Name
LED3 /
PHYAD2
Type
(Note 1)
I/O
Pin Function
LED Output:
Programmable LED3 Output /
Configuration Mode:
The pull-up/pull-down value is latched as PHYADD[2] during
power-up / reset. See “Strapping Options” section for details.
The LED3 pin is programmed via register 11h bits [7:6], LED_SEL[1:0],
and is defined as follows:
LED_SEL[1:0] = (1,1)
LED_SEL[1:0] = (0,1)
LED_SEL[1:0] = (0,1)
// 6-LED Configuration (default)
// 5-LED Configuration
// 4-LED Configuration
Duplex / Collision
Pin State
Half Duplex
H
OFF
Full Duplex
L
ON
Collision
Toggle
Blinking
LED_SEL[1:0] = (0,0)
45
LED2 /
PHYAD1
I/O
LED Definition
// Reserved – not used
LED Output:
Programmable LED2 Output /
Configuration Mode:
The pull-up/pull-down value is latched as PHYADD[1] during powerup / reset. See “Strapping Options” section for details.
The LED2 pin is programmed via register 11h bits [7:6], LED_SEL[1:0],
and is defined as follows:
LED_SEL[1:0] = (1,1)
// 6-LED Configuration (default)
Receive Activity
46
DVDDH
P
47
VSSPST
Gnd
DS00003115A-page 10
Pin State
LED Definition
No Receive Activity
H
OFF
Receive Activity
L, Toggle
ON, Blinking
LED_SEL[1:0] = (0,1)
// Reserved – not used
LED2 pin is internally pulled high.
LED_SEL[1:0] = (1,0)
// Reserved – not used
LED2 pin is internally pulled high.
LED_SEL[1:0] = (0,0)
// Reserved – not used
3.3V or 2.5V digital VDD
Digital ground
2009-2019 Microchip Technology Inc.
KSZ9021GQ
Pin
Number
48
Pin Name
Type
(Note 1)
LED1 /
PHYAD0
I/O
Pin Function
LED Output:
Programmable LED1 Output /
Configuration Mode:
The pull-up/pull-down value is latched as PHYADD[0] during
power-up / reset. See “Strapping Options” section for details.
The LED1 pin is programmed via register 11h bits [7:6], LED_SEL[1:0],
and is defined as follows:
LED_SEL[1:0] = (1,1)
// 6-LED Configuration (default)
Transmit Activity
Pin State
No Transmit Activity
H
OFF
Transmit Activity
L, Toggle
ON, Blinking
LED_SEL[1:0] = (1,0)
// 5-LED Configuration
Receive /Transmit
Activity
49
DVDDL
P
50
VSS
Gnd
51
TXD0
I
LED Definition
Pin State
LED Definition
No Receive / Transmit H
Activity
OFF
Receive / Transmit
Activity
ON, Blinking
L, Toggle
LED_SEL[1:0] = (1,0)
// Reserved – not used
LED1 pin is internally pulled high.
LED_SEL[1:0] = (0,0)
// Reserved – not used
1.2V digital VDD
Digital ground
GMII Mode:
GMII TXD0 (Transmit Data 0) Input
MII Mode:
MII TXD0 (Transmit Data 0) Input
52
TXD1
I
GMII Mode:
GMII TXD1 (Transmit Data 1) Input
MII Mode:
MII TXD1 (Transmit Data 1) Input
53
TXD2
I
GMII Mode:
GMII TXD2 (Transmit Data 2) Input
MII Mode:
MII TXD2 (Transmit Data 2) Input
54
TXD3
I
GMII Mode:
GMII TXD3 (Transmit Data 3) Input
MII Mode:
MII TXD3 (Transmit Data 3) Input
55
VSS
Gnd
2009-2019 Microchip Technology Inc.
Digital ground
DS00003115A-page 11
KSZ9021GQ
Pin
Number
Pin Name
Type
(Note 1)
56
DVDDL
P
57
DVDDH
P
3.3V or 2.5V digital VDD
58
TXD4
I
GMII Mode:
Pin Function
1.2V digital VDD
GMII TXD4 (Transmit Data 4) Input
MII Mode:
This pin is not used and can be driven high or low
59
TXD5
I
GMII Mode:
GMII TXD5 (Transmit Data 5) Input
MII Mode:
This pin is not used and can be driven high or low
60
TXD6
I
GMII Mode:
GMII TXD6 (Transmit Data 6) Input
MII Mode:
This pin is not used and can be driven high or low
61
TXD7
I
GMII Mode:
GMII TXD7 (Transmit Data 7) Input
MII Mode:
This pin is not used and can be driven high or low
62
VSSPST
Gnd
Digital ground
63
DVDDH
P
3.3V or 2.5V digital VDD
64
TX_ER
I
GMII Mode:
GMII TX_ER (Transmit Error) Input
MII Mode:
MII TX_ER (Transmit Error) Input
If GMII / MII MAC does not provide the TX_ER output signal, this pin
should be tied low.
65
GTX_CLK
I
GMII Mode:
GMII GTX_CLK (Transmit Reference Clock) Input
66
VSSPST
Gnd
67
TX_EN
I
Digital ground
GMII Mode:
GMII TX_EN (Transmit Enable) Input
MII Mode:
MII TX_EN (Transmit Enable) Input
68
DVDDH
P
3.3V or 2.5V digital VDD
69
70
DVDDH
P
3.3V or 2.5V digital VDD
RXD7
O
GMII Mode:
GMII RXD7 (Receive Data 7) Output
MII Mode:
This pin is not used and is driven low.
71
VSS
Gnd
Digital ground
72
VSS
Gnd
Digital ground
DS00003115A-page 12
2009-2019 Microchip Technology Inc.
KSZ9021GQ
Pin
Number
Pin Name
Type
(Note 1)
73
RXD6
O
Pin Function
GMII Mode:
GMII RXD6 (Receive Data 6) Output
MII Mode:
This pin is not used and is driven low.
74
DVDDL
P
1.2V digital VDD
75
76
DVDDL
P
1.2V digital VDD
RXD5
O
GMII Mode:
GMII RXD5 (Receive Data 5) Output
MII Mode:
This pin is not used and is driven low.
77
RXD4
O
GMII Mode:
GMII RXD4 (Receive Data 4) Output
MII Mode:
This pin is not used and is driven low.
78
RXD3 /
I/O
GMII Mode:
GMII RXD3 (Receive Data 3) Output
MODE3
MII Mode:
MII RXD3 (Receive Data 3) Output /
Configuration Mode:
The pull-up/pull-down value is latched as MODE3 during power-up
/ reset. See “Strapping Options” section for details.
79
VSSPST
Gnd
Digital ground
80
VSSPST
Gnd
Digital ground
81
DVDDH
P
3.3V or 2.5V digital VDD
82
DVDDH
P
3.3V or 2.5V digital VDD
83
RXD2 /
I/O
GMII Mode:
GMII RXD2 (Receive Data 2) Output
MODE2
MII Mode:
MII RXD2 (Receive Data 2) Output) /
Configuration Mode:
The pull-up/pull-down value is latched as MODE2 during power-up
/ reset. See “Strapping Options” section for details.
84
VSS
Gnd
Digital ground
85
VSS
Gnd
Digital ground
86
DVDDL
P
1.2V digital VDD
87
DVDDL
P
1.2V digital VDD
88
RXD1 /
I/O
MODE1
GMII Mode:
GMII RXD1 (Receive Data 1) Output
MII Mode:
MII RXD1 (Receive Data 1) Output /
Configuration Mode:
The pull-up/pull-down value is latched as MODE1 during power-up
/ reset. See “Strapping Options” section for details.
2009-2019 Microchip Technology Inc.
DS00003115A-page 13
KSZ9021GQ
Pin
Number
Pin Name
Type
(Note 1)
89
RXD0 /
I/O
Pin Function
GMII Mode:
GMII RXD0 (Receive Data 0) Output
MODE0
MII Mode:
MII RXD0 (Receive Data 0) Output /
Configuration Mode:
The pull-up/pull-down value is latched as MODE0 during power-up
/ reset. See “Strapping Options” section for details.
90
RX_DV /
I/O
GMII Mode:
GMII RX_DV (Receive Data Valid) Output
CLK125_EN
MII Mode:
MII RX_DV (Receive Data Valid) Output /
Configuration Mode:
Latched as CLK125_NDO Output Enable during power-up / reset.
See “Strapping Options” section for details.
91
VSSPST
Gnd
Digital ground
92
DVDDH
P
3.3V or 2.5V digital VDD
93
RX_ER
O
GMII Mode:
GMII RX_ER (Receive Error) Output
MII Mode:
MII RX_ER (Receive Error) Output
94
RX_CLK
O
GMII Mode:
GMII RX_CLK (Receive Reference Clock) Output
MII Mode:
MII RX_CLK (Receive Reference Clock) Output
95
VSSPST
Gnd
96
CRS
O
Digital ground
GMII Mode:
GMII CRS (Carrier Sense) Output
MII Mode:
MII CRS (Carrier Sense) Output
97
MDC
Ipu
98
MDIO
Ipu/O
Management Data Clock Input
This pin is the input reference clock for MDIO (pin 98).
Management Data Input / Output
This pin is synchronous to MDC (pin 97) and requires an external pull-up
resistor to DVDDH (digital VDD) in a range from 1.0K to 4.7K.
99
COL
O
GMII Mode:
GMII COL (Collision Detected) Output
MII Mode:
MII COL (Collision Detected) Output
100
DVDDH
DS00003115A-page 14
P
3.3V or 2.5V digital VDD
2009-2019 Microchip Technology Inc.
KSZ9021GQ
Pin
Number
Pin Name
Type
(Note 1)
101
INT_N
O
Pin Function
Interrupt Output
This pin provides a programmable interrupt output and requires an external pull-up resistor to DVDDH (digital VDD) in a range from 1.0K to
4.7K when active low.
Register 1Bh is the Interrupt Control/Status Register for programming the
interrupt conditions and reading the interrupt status. Register 1Fh bit 14
sets the interrupt output to active low (default) or active high.
102
VSS
Gnd
103
DVDDL
P
Digital ground
104
VSS
Gnd
105
DVDDL
P
1.2V digital VDD
1.2V digital VDD
Digital ground
106
DVDDH
P
3.3V or 2.5V digital VDD
107
CLK125_NDO
O
125MHz Clock Output
This pin provides a 125MHz reference clock output option for use by the
MAC.
108
VSSPST
Gnd
Digital ground
109
VSSPST
Gnd
Digital ground
110
RESET_N
Ipu
Chip Reset (active low)
Hardware pin configurations are strapped-in at the de-assertion (rising
edge) of RESET_N. See “Strapping Options” section for more details.
111
NC
-
No connect
112
NC
-
No connect
113
VSS
Gnd
114
DVDDL
P
1.2V digital VDD
115
TX_CLK
O
MII Mode:
Digital ground
MII TX_CLK (Transmit Reference Clock) Output
116
A1
I
117
AGNDH
Gnd
118
LDO_O
O
Factory test pin – float for normal operation
Analog ground
On-chip 1.2V LDO Controller Output
This pin drives the input gate of a P-channel MOSFET to generate 1.2V
for the chip’s core voltages. If 1.2V is provided by the system and this pin
is not used, it can be left floating.
119
AGNDL_PLL
Gnd
120
AVDDL_PLL
P
Analog ground
1.2V analog VDD for PLL
121
AVDDL_PLL
P
1.2V analog VDD for VCO
122
AVDDH
P
3.3V analog VDD
123
XO
O
25MHz Crystal feedback
This pin is a no connect if oscillator or external clock source is used.
124
XI
I
Crystal / Oscillator / External Clock Input
25MHz +/-50ppm tolerance
125
AVDDH
2009-2019 Microchip Technology Inc.
P
3.3V analog VDD
DS00003115A-page 15
KSZ9021GQ
Pin
Number
Pin Name
Type
(Note 1)
126
ISET
I/O
Set transmit output level
127
AGNDH_BG
Gnd
Analog ground
128
AVDDH
P
Pin Function
Connect a 4.99K 1% resistor to ground on this pin
3.3V analog VDD
Note 1:
P = Power supply.
Gnd = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipu = Input with internal pull-up.
Ipu/O = Input with internal pull-up / Output.
DS00003115A-page 16
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KSZ9021GQ
2.3
Strapping Options
Pin Number
Pin Name
Type
(Note 1)
42
43
44
45
48
PHYAD4
PHYAD3
PHYAD2
PHYAD1
PHYAD0
I/O
I/O
I/O
I/O
I/O
The PHY Address, PHYAD[4:0], is latched at power-up / reset and is configurable to any value from 1 to 31. Each PHY address bit is configured as
follows:
78
83
88
89
MODE3
MODE2
MODE1
MODE0
I/O
I/O
I/O
I/O
The MODE[3:0] strap-in pins are latched at power-up / reset and are
defined as follows:
Pin Function
Pull-up = 1
Pull-down = 0
MODE[3:0]
Mode
0000
90
CLK125_EN
I/O
Reserved - not used
0001
GMII / MII Mode
0010
Reserved - not used
0011
Reserved - not used
0100
NAND Tree Mode
0101
Reserved - not used
0110
Reserved - not used
0111
Chip Power Down Mode
1000
Reserved - not used
1001
Reserved - not used
1010
Reserved - not used
1011
Reserved - not used
1100
Reserved - not used
1101
Reserved - not used
1110
Reserved - not used
1111
Reserved - not used
CLK125_EN is latched at power-up / reset and is defined as follows:
Pull-up = Enable 125MHz Clock Output
Pull-down = Disable 125MHz Clock Output
Pin 107 (CLK125_NDO) provides the 125MHz reference clock output
option for use by the MAC.
Note 1:
I/O = Bi-directional.
Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may be driven
during power-up or reset, and consequently cause the PHY strap-in pins on the GMII/MII signals to be latched
to the incorrect configuration. In this case, it is recommended to add external pull-ups/pull-downs on the PHY
strap-in pins to ensure the PHY is configured to the correct pin strap-in mode.
2009-2019 Microchip Technology Inc.
DS00003115A-page 17
KSZ9021GQ
3.0
FUNCTIONAL OVERVIEW
The KSZ9021GQ is a completely integrated triple speed (10Base-T/100Base-TX/1000Base-T) Ethernet Physical Layer
Transceiver solution for transmission and reception of data over a standard CAT-5 unshielded twisted pair (UTP) cable.
Its on-chip proprietary 1000Base-T transceiver and Manchester/MLT-3 signaling-based 10Base-T/100Base-TX transceivers are all IEEE 802.3 compliant.
The KSZ9021GQ reduces board cost and simplifies board layout by using on-chip termination resistors for the four differential pairs and by integrating a LDO controller to drive a low cost MOSFET to supply the 1.2V core.
On the copper media interface, the KSZ9021GQ can automatically detect and correct for differential pair misplacements
and polarity reversals, and correct propagation delays and re-sync timing between the four differential pairs, as specified
in the IEEE 802.3 standard for 1000Base-T operation.
The KSZ9021GQ provides the GMII/MII interface for a direct and seamless connection to GMACs in Gigabit Ethernet
Processors and Switches for data transfer at 10/100/1000 Mbps speed.
The following figure shows a high-level block diagram of the KSZ9021GQ.
FIGURE 3-1:
KSZ9021GQ BLOCK DIAGRAM
PMA
TX10/100/1000
CLOCK
RESET
CONFIGURATIONS
PMA
RX1000
PCS1000
MEDIA
INTERFACE
PMA
RX100
GMII / MII
INTERFACE
PCS100
PMA
RX10
PCS10
AUTO
NEGOTIATION
DS00003115A-page 18
LED
DRIVERS
2009-2019 Microchip Technology Inc.
KSZ9021GQ
3.1
3.1.1
Functional Description: 10Base-T/100Base-TX Transceiver
100BASE-TX TRANSMIT
The 100Base-TX transmit function performs parallel to serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI conversion, and MLT-3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125MHz serial
bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized
data is further converted from NRZ-to-NRZI format, and then transmitted in MLT-3 current output. The output current is
set by an external 4.99K 1% resistor for the 1:1 transformer ratio.
The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave-shaped 10Base-T output is also incorporated into the 100Base-TX transmitter.
3.1.2
100BASE-TX RECEIVE
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT-3-to-NRZI conversion, data
and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted
pair cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization.
This is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used
to compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion
circuit converts the MLT-3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then
used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/
5B decoder. Finally, the NRZ serial data is converted to the GMII/MII format and provided as the input data to the MAC.
3.1.3
SCRAMBLER/DE-SCRAMBLER (100BASE-TX ONLY)
The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI)
and baseline wander. Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register
(LFSR). The scrambler generates a 2047-bit non-repetitive sequence, and the receiver then de-scrambles the incoming
data stream using the same sequence as at the transmitter.
3.1.4
10BASE-T TRANSMIT
The output 10Base-T driver is incorporated into the 100Base-TX driver to allow transmission with the same magnetic.
They are internally wave-shaped and pre-emphasized into typical outputs of 2.5V amplitude. The harmonic contents are
at least 31 dB below the fundamental when driven by an all-ones Manchester-encoded signal.
3.1.5
10BASE-T RECEIVE
On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit
and a phase-locked loop (PLL) perform the decoding function. The Manchester-encoded data stream is separated into
clock signal and NRZ data. A squelch circuit rejects signals with levels less than 300 mV or with short pulse widths in
order to prevent noises at the receive inputs from falsely triggering the decoder. When the input exceeds the squelch
limit, the PLL locks onto the incoming signal and the KSZ9021GQ decodes a data frame. The receiver clock is maintained active during idle periods in between receiving data frames.
2009-2019 Microchip Technology Inc.
DS00003115A-page 19
KSZ9021GQ
3.2
Functional Description: 1000Base-T Transceiver
The 1000Base-T transceiver is based-on a mixed-signal / digital signal processing (DSP) architecture, which includes
the analog front-end, digital channel equalizers, trellis encoders/decoders, echo cancellers, cross-talk cancellers, precision clock recovery scheme, and power efficient line drivers.
The following figure shows a high-level block diagram of a single channel of the 1000Base-T transceiver for
one of the four differential pairs.
FIGURE 3-2:
XTAL
KSZ9021GQ 1000BASE-T BLOCK DIAGRAM - SINGLE CHANNEL
OTHER
CHANNELS
CLOCK
GENERATION
TX
SIGNAL
SIDE-STREAM
SCRAMBLER
&
SYMBOL ENCODER
TRANSMIT
BLOCK
ANALOG
HYBRID
PCS STATE
MACHINES
NEXT
CANCELLER
NEXT
Canceller
NEXT Canceller
ECHO
CANCELLER
BASELINE
WANDER
COMPENSATION
AGC
RXADC
+
LED DRIVER
PAIR SWAP
&
ALIGN UNIT DESCRAMBLER
+
DECODER
FFE
SLICER
RX
SIGNAL
CLOCK & PHASE
RECOVERY
AUTONEGOTIATION
MII
REGISTERS
DFE
MII
MANAGEMENT
CONTROL
PMA STATE
MACHINES
3.2.1
ANALOG ECHO CANCELLATION CIRCUIT
In 1000Base-T mode, the analog echo cancellation circuit helps to reduce the near-end echo. This analog hybrid circuit
relieves the burden of the ADC and the adaptive equalizer.
This circuit is disabled in 10Base-T/100Base-TX mode.
3.2.2
AUTOMATIC GAIN CONTROL (AGC)
In 1000Base-T mode, the automatic gain control (AGC) circuit provides initial gain adjustment to boost up the signal
level. This pre-conditioning circuit is used to improve the signal-to-noise ratio of the receive signal.
3.2.3
ANALOG-TO-DIGITAL CONVERTER (ADC)
In 1000Base-T mode, the analog-to-digital converter (ADC) digitizes the incoming signal. ADC performance is essential
to the overall performance of the transceiver.
This circuit is disabled in 10Base-T/100Base-TX mode.
DS00003115A-page 20
2009-2019 Microchip Technology Inc.
KSZ9021GQ
3.2.4
TIMING RECOVERY CIRCUIT
In 1000Base-T mode, the mixed-signal clock recovery circuit together with the digital phase locked loop is used to
recover and track the incoming timing information from the received data. The digital phase locked loop has very low
long-term jitter to maximize the signal-to-noise ratio of the receive signal.
The 1000Base-T slave PHY is required to transmit the exact receive clock frequency recovered from the received data
back to the 1000Base-T master PHY. Otherwise, the master and slave will not be synchronized after long transmission.
Additionally, this helps to facilitate echo cancellation and NEXT removal.
3.2.5
ADAPTIVE EQUALIZER
In 1000Base-T mode, the adaptive equalizer provides the following functions:
• Detection for partial response signaling
• Removal of NEXT and ECHO noise
• Channel equalization
Signal quality is degraded by residual echo that is not removed by the analog hybrid and echo due to impedance mismatch. The KSZ9021GQ employs a digital echo canceller to further reduce echo components on the receive signal.
In 1000Base-T mode, data transmission and reception occurs simultaneously on all four pairs of wires (four channels).
This results in high frequency cross-talk coming from adjacent wires. The KSZ9021GQ employs three NEXT cancellers
on each receive channel to minimize the cross-talk induced by the other three channels.
In 10Base-T/100Base-TX mode, the adaptive equalizer needs only to remove the inter-symbol interference and recover
the channel loss from the incoming data.
3.2.6
TRELLIS ENCODER AND DECODER
In 1000Base-T mode, the transmitted 8-bit data is scrambled into 9-bit symbols and further encoded into 4D-PAM5 symbols. The initial scrambler seed is determined by the specific PHY address to reduce EMI when more than one
KSZ9021GQ are used on the same board. On the receiving side, the idle stream is examined first. The scrambler seed,
pair skew, pair order and polarity have to be resolved through the logic. The incoming 4D-PAM5 data is then converted
into 9-bit symbols and then de-scrambled into 8-bit data.
3.3
3.3.1
Functional Description: Additional 10/100/1000 PHY Features
AUTO MDI/MDI-X
The Automatic MDI/MDI-X feature eliminates the need to determine whether to use a straight cable or a crossover cable
between the KSZ9021GQ and its link partner. This auto-sense function detects the MDI/MDI-X pair mapping from the
link partner, and then assigns the MDI/MDI-X pair mapping of the KSZ9021GQ accordingly.
The following table shows the KSZ9021GQ 10/100/1000 pin-out assignments for MDI/MDI-X pin mapping.
TABLE 3-1:
MDI / MDI-X PIN MAPPING
MDI
MDI-X
Pin (RJ-45 pair)
1000Base-T
100Base-TX
10Base-T
1000Base-T
100Base-TX
10Base-T
TXRXP/M_A (1,2)
A+/-
TX+/-
TX+/-
B+/-
RX+/-
RX+/-
TXRXP/M_B (3,6)
B+/-
RX+/-
RX+/-
A+/-
TX+/-
TX+/-
TXRXP/M_C (4,5)
C+/-
Not used
Not used
D+/-
Not used
Not used
TXRXP/M_D (7,8)
D+/-
Not used
Not used
C+/-
Not used
Not used
Auto MDI/MDI-X is enabled by default. It is disabled by writing a one to register 28 (1Ch) bit 6. MDI and MDI-X mode is
set by register 28 (1Ch) bit 7 if auto MDI/MDI-X is disabled.
An isolation transformer with symmetrical transmit and receive data paths is recommended to support auto MDI/MDI-X.
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DS00003115A-page 21
KSZ9021GQ
3.3.2
PAIR- SWAP, ALIGNMENT, AND POLARITY CHECK
In 1000Base-T mode, the KSZ9021GQ
• detects incorrect channel order and automatically restore the pair order for the A, B, C, D pairs (four channels)
• supports 50±/-10ns difference in propagation delay between pairs of channels in accordance with the IEEE 802.3
standard, and automatically corrects the data skew so the corrected four pairs of data symbols are synchronized
Incorrect pair polarities of the differential signals are automatically corrected for all speeds.
3.3.3
WAVE SHAPING, SLEW RATE CONTROL AND PARTIAL RESPONSE
In communication systems, signal transmission encoding methods are used to provide the noise-shaping feature and
to minimize distortion and error in the transmission channel.
• For 1000Base-T, a special partial response signaling method is used to provide the band-limiting feature for the
transmission path.
• For 100Base-TX, a simple slew rate control method is used to minimize EMI.
• For 10Base-T, pre-emphasis is used to extend the signal quality through the cable.
3.3.4
PLL CLOCK SYNTHESIZER
The KSZ9021GQ generates 125MHz, 25MHz and 10MHz clocks for system timing. Internal clocks are generated from
the external 25 MHz crystal or reference clock.
3.4
Auto-Negotiation
The KSZ9021GQ conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3 Specification.
Auto-negotiation allows UTP (Unshielded Twisted Pair) link partners to select the highest common mode of operation.
During auto-negotiation, link partners advertise capabilities across the UTP link to each other, and then compare their
own capabilities with those they received from their link partners. The highest speed and duplex setting that is common
to the two link partners is selected as the mode of operation.
The following list shows the speed and duplex operation mode from highest to lowest.
•
•
•
•
•
•
Priority 1: 1000Base-T, full-duplex
Priority 2: 1000Base-T, half-duplex
Priority 3: 100Base-TX, full-duplex
Priority 4: 100Base-TX, half-duplex
Priority 5: 10Base-T, full-duplex
Priority 6: 10Base-T, half-duplex
If auto-negotiation is not supported or the KSZ9021GQ link partner is forced to bypass auto-negotiation for 10Base-T
and 100Base-TX modes, then the KSZ9021GQ sets its operating mode by observing the input signal at its receiver. This
is known as parallel detection, and allows the KSZ9021GQ to establish link by listening for a fixed signal protocol in the
absence of auto-negotiation advertisement protocol.
The auto-negotiation link up process is shown in the following flow chart.
DS00003115A-page 22
2009-2019 Microchip Technology Inc.
KSZ9021GQ
FIGURE 3-3:
AUTO-NEGOTIATION FLOW CHART
For 1000Base-T mode, auto-negotiation is required and always used to establish a link. During 1000Base-T auto-negotiation, the Master and Slave configuration is first resolved between link partners, and then the link is established with
the highest common capabilities between link partners.
Auto-negotiation is enabled by default at power-up or after hardware reset. Afterwards, auto-negotiation can be enabled
or disabled through register 0 bit 12. If auto-negotiation is disabled, the speed is set by register 0 bits 6 and 13, and the
duplex is set by register 0 bit 8.
If the speed is changed on the fly, the link goes down and either auto-negotiation or parallel detection will initiate until a
common speed between KSZ9021GQ and its link partner is re-established for a link.
If link is already established and there is no change of speed on the fly, then the changes will not take effect unless either
auto-negotiation is restarted through register 0 bit 9, or a link down to link up transition occurs (i.e., disconnecting and
reconnecting the cable).
After auto-negotiation is completed, the link status is updated in register 1 and the link partner capabilities are updated
in registers 5, 6, and 10.
The auto-negotiation finite state machines employ interval timers to manage the auto-negotiation process. The duration
of these timers under normal operating conditions are summarized in the following table.
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DS00003115A-page 23
KSZ9021GQ
TABLE 3-2:
AUTO-NEGOTIATION TIMERS
Auto-Negotiation Interval Timers
Transmit Burst interval
Time Duration
16 ms
Transmit Pulse interval
68 us
FLP detect minimum time
17.2 us
FLP detect maximum time
185 us
Receive minimum Burst interval
6.8 ms
Receive maximum Burst interval
112 ms
Data detect minimum interval
35.4 us
Data detect maximum interval
95 us
NLP test minimum interval
4.5 ms
NLP test maximum interval
30 ms
Link Loss time
52 ms
Break Link time
1480 ms
Parallel Detection wait time
830 ms
Link Enable wait time
1000 ms
3.5
GMII Interface
The Gigabit Media Independent Interface (GMII) is compliant to the IEEE 802.3 Specification. It provides a common
interface between GMII PHYs and MACs, and has the following key characteristics:
• Pin count is 24 pins (11 pins for data transmission, 11 pins for data reception, and 2 pins for carrier and collision
indication).
• 1000Mbps is supported at both half and full duplex.
• Data transmission and reception are independent and belong to separate signal groups.
• Transmit data and receive data are each 8-bit wide, a byte.
In GMII operation, the GMII pins function as follow:
•
•
•
•
•
The MAC sources the transmit reference clock, GTX_CLK, at 125MHz for 1000Mbps.
The PHY recovers and sources the receive reference clock, RX_CLK, at 125MHz for 1000Mbps.
TX_EN, TXD[7:0] and TX_ER are sampled by the KSZ9021GQ on the rising edge of GTX_CLK.
RX_DV, RXD[7:0], and RX_ER are sampled by the MAC on the rising edge of RX_CLK.
CRS and COL are driven by the KSZ9021GQ and are not required to transition synchronously with respect to
either GTX_CLK or RX_CLK.
The KSZ9021GQ combines GMII mode with MII mode to form GMII/MII mode to support data transfer at 10/100/1000
Mbps speed. After power-up or reset, the KSZ9021GQ is configured to GMII/MII mode if the MODE[3:0] strap-in pins
are set to 0001. See Strapping Options section.
The KSZ9021GQ has the option to output a low jitter 125MHz reference clock on CLK125_NDO (pin 107). This clock
provides a lower cost reference clock alternative for GMII/MII MACs that require a 125MHz crystal or oscillator. The
125MHz clock output is enabled after power-up or reset if the CLK125_EN strap-in pin is pulled high.
The KSZ9021GQ provides a dedicated transmit clock input pin for GMII mode, defined as follows:
GTX_CLK (input, pin 65):
DS00003115A-page 24
Sourced by MAC in GMII mode for 1000Mbps speed.
2009-2019 Microchip Technology Inc.
KSZ9021GQ
3.5.1
GMII SIGNAL DEFINITION
The following table describes the GMII signals. Refer to Clause 35 of the IEEE 802.3 Specification for more detailed
information.
TABLE 3-3:
GMII
Signal Name
(per spec)
GMII SIGNAL DEFINITION
GMII
Signal Name
(per KSZ9021GQ)
Pin Type
(with respect to
PHY)
Pin Type
(with respect to
MAC)
Description
GTX_CLK
GTX_CLK
Input
Output
Transmit Reference Clock
(125MHz for 1000Mbps)
TX_EN
TX_EN
Input
Output
Transmit Enable
TXD[7:0]
TXD[7:0]
Input
Output
Transmit Data [7:0]
TX_ER
TX_ER
Input
Output
Transmit Error
RX_CLK
RX_CLK
Output
Input
Receive Reference Clock
(125MHz for 1000Mbps)
RX_DV
RX_DV
Output
Input
Receive Data Valid
RXD[7:0]
RXD[7:0]
Output
Input
Receive Data [7:0]
RX_ER
RX_ER
Output
Input
Receive Error
CRS
CRS
Output
Input
Carrier Sense
COL
COL
Output
Input
Collision Detected
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DS00003115A-page 25
KSZ9021GQ
3.5.2
GMII SIGNAL DIAGRAM
The KSZ9021GQ GMII pin connections to the MAC are shown in the following figure.
FIGURE 3-4:
KSZ9021GQ GMII INTERFACE
KSZ9021GQ
GTX_CLK
TX_EN
TXD[7:0]
TX_ER
GTX_CLK
TX_EN
TXD[7:0]
TX_ER
RX_CLK
RX_CLK
RX_DV
RX_DV
RXD[7:0]
RX_ER
3.6
GMII
ETHERNET MAC
RXD[7:0]
RX_ER
CRS
CRS
COL
COL
MII Interface
The Media Independent Interface (MII) is compliant with the IEEE 802.3 Specification. It provides a common interface
between MII PHYs and MACs, and has the following key characteristics:
• Pin count is 16 pins (7 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision indication).
• 10Mbps and 100Mbps are supported at both half and full duplex.
• Data transmission and reception are independent and belong to separate signal groups.
• Transmit data and receive data are each 4-bit wide, a nibble.
In MII operation, the MII pins function as follow:
• The PHY sources the transmit reference clock, TX_CLK, at 25MHz for 100Mbps and 2.5MHz for 10Mbps.
• The PHY recovers and sources the receive reference clock, RX_CLK, at 25MHz for 100Mbps and 2.5MHz for
10Mbps.
DS00003115A-page 26
2009-2019 Microchip Technology Inc.
KSZ9021GQ
• TX_EN, TXD[3:0] and TX_ER are driven by the MAC and shall transition synchronously with respect to TX_CLK.
• RX_DV, RXD[3:0], and RX_ER are driven by the KSZ9021GQ and shall transition synchronously with respect to
RX_CLK.
• CRS and COL are driven by the KSZ9021GQ and are not required to transition synchronously with respect to
either TX_CLK or RX_CLK.
The KSZ9021GQ combines GMII mode with MII mode to form GMII/MII mode to support data transfer at 10/100/1000
Mbps speeds. After the power-up or reset, the KSZ9021GQ is then configured to GMII/MII mode if the MODE[3:0] strapin pins are set to 0001. See Strapping Options section.
The KSZ9021GQ has the option to output a low jitter 125MHz reference clock on CLK125_NDO (pin 107). This clock
provides a lower cost reference clock alternative for GMII/MII MACs that require a 125MHz crystal or oscillator. The
125MHz clock output is enabled after power-up or reset if the CLK125_EN strap-in pin is pulled high.
The KSZ9021GQ provides a dedicated transmit clock output pin for MII mode, defined as follow:
• TX_CLK (output, pin 115)
3.6.1
:
Sourced by KSZ9021GQ in MII mode for 10/100Mbps speed
MII SIGNAL DEFINITION
The following table describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information.
TABLE 3-4:
MII
Signal Name
(per spec)
MII SIGNAL DEFINITION
Pin Type
(with respect to
PHY)
Pin Type
(with respect to
MAC)
TX_CLK
Output
Input
Transmit Reference Clock
(25MHz for 100Mbps, 2.5MHz for
10Mbps)
TX_EN
TX_EN
Input
Output
Transmit Enable
TXD[3:0]
TXD[3:0]
Input
Output
Transmit Data [3:0]
TX_ER
TX_ER
Input
Output
Transmit Error
RX_CLK
RX_CLK
Output
Input
Receive Reference Clock
(25MHz for 100Mbps, 2.5MHz for
10Mbps)
TX_CLK
MII
Signal Name
(per KSZ9021GQ)
Description
RX_DV
RX_DV
Output
Input
Receive Data Valid
RXD[3:0]
RXD[3:0]
Output
Input
Receive Data [3:0]
RX_ER
RX_ER
Output
Input
Receive Error
CRS
CRS
Output
Input
Carrier Sense
COL
COL
Output
Input
Collision Detected
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DS00003115A-page 27
KSZ9021GQ
3.6.2
MII SIGNAL DIAGRAM
The KSZ9021GQ MII pin connections to the MAC are shown in the following figure.
FIGURE 3-5:
KSZ9021GQ MII INTERFACE
KSZ9021GQ
TX_CLK
TX_CLK
TX_EN
TX_EN
TXD[3:0]
TX_ER
TXD[3:0]
TX_ER
RX_CLK
RX_CLK
RX_DV
RX_DV
RXD[3:0]
RX_ER
3.7
MII
ETHERNET MAC
RXD[3:0]
RX_ER
CRS
CRS
COL
COL
MII Management (MIIM) Interface
The KSZ9021GQ supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the state of the KSZ9021GQ. An
external device with MIIM capability is used to read the PHY status and/or configure the PHY settings. Further detail on
the MIIM interface can be found in Clause 22.2.4.5 of the IEEE 802.3 Specification.
The MIIM interface consists of the following:
• A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
• A specific protocol that operates across the aforementioned physical connection that allows an external controller
to communicate with one or more KSZ9021GQ device. Each KSZ9021GQ device is assigned a PHY address
between 1 and 31 by the PHYAD[4:0] strapping pins.
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KSZ9021GQ
• A 32 register address space to access the KSZ9021GQ IEEE Defined Registers, Vendor Specific Registers and
Extended Registers. See Register Map section.
The following table shows the MII Management frame format for the KSZ9021GQ.
TABLE 3-5:
MII MANAGEMENT FRAME FORMAT – FOR KSZ9021GQ
Start of
Frame
Preamble
Read/Write
OP Code
PHY
Address
Bits [4:0]
REG
Address
Bits [4:0]
Data
Bits [15:0]
TA
Idle
Read
32 1’s
01
10
AAAAA
RRRRR
Z0
DDDDDDDD_DDDDDDDD Z
Write
32 1’s
01
01
AAAAA
RRRRR
10
DDDDDDDD_DDDDDDDD Z
3.8
Interrupt (INT_N)
INT_N (pin 101) is an optional interrupt signal that is used to inform the external controller that there has been a status
update in the KSZ9021GQ PHY register. Bits [15:8] of register 27 (1Bh) are the interrupt control bits to enable and disable the conditions for asserting the INT_N signal. Bits [7:0] of register 27 (1Bh) are the interrupt status bits to indicate
which interrupt conditions have occurred. The interrupt status bits are cleared after reading register 27 (1Bh).
Bit 14 of register 31 (1Fh) sets the interrupt level to active high or active low. The default is active low.
The MII management bus option gives the MAC processor complete access to the KSZ9021GQ control and status registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change.
3.9
LED Mode
The KSZ9021GQ provides six programmable LED output pins (LED1 thru LED6) that are configurable to
support three LED modes. Bits [7:6] of register 17 (11h) are the LED Mode Select [1:0] bits, and are
defined as follows:
•
•
•
•
00 = Reserved – not used
10 = 4-LED Configuration
01 = 5-LED Configuration
11 = 6-LED Configuration (default setting after power-up / reset)
3.9.1
4-LED CONFIGURATION
In this LED mode, the link and activity are combined into one LED for each speed. The unused pins LED2 and LED1
are internally pulled high.
TABLE 3-6:
4-LED CONFIGURATION – PIN DEFINITION
LED pin
LED6
LED5
LED4
LED3
Pin State
LED Definition
Description
H
OFF
10Base-T, Link off
L
ON
10Base-T, Link on
Toggle
Blinking
10Base-T, Activity
H
OFF
100Base-TX, Link off
L
ON
100Base-TX, Link on
Toggle
Blinking
100Base-TX, Activity
H
OFF
1000Base-T, Link off
L
ON
1000Base-T, Link on
Toggle
Blinking
1000Base-T, Activity
H
OFF
Half-duplex
L
ON
Full-duplex
Toggle
Blinking
Collision
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KSZ9021GQ
3.9.2
5-LED CONFIGURATION
In this LED mode, the transmit and receive activities are combined into pin LED1. The unused pin LED2 is internally
pulled high.
TABLE 3-7:
5-LED CONFIGURATION – PIN DEFINITION
LED pin
Pin State
LED6
LED5
LED4
LED3
LED1
3.9.3
LED Definition
Description
H
OFF
10Base-T, Link off
L
ON
10Base-T, Link on
H
OFF
100Base-TX, Link off
L
ON
100Base-TX, Link on
H
OFF
1000Base-T, Link off
L
ON
1000Base-T, Link on
H
OFF
Half-duplex
L
ON
Full-duplex
Toggle
Blinking
Collision
H
OFF
No Activity
L
ON
Transmit or Receive Activity
Toggle
Blinking
6-LED CONFIGURATION
In this LED mode, all six LED pins are used. Pins LED2 and LED1 are dedicated for receive activity and transmit activity,
respectively, for all speeds.
TABLE 3-8:
6-LED CONFIGURATION – PIN DEFINITION
LED pin
LED6
Pin State
LED Definition
Description
H
OFF
10Base-T, Link off
L
ON
10Base-T, Link on
LED5
H
OFF
100Base-TX, Link off
L
ON
100Base-TX, Link on
LED4
H
OFF
1000Base-T, Link off
L
ON
1000Base-T, Link on
H
OFF
Half-duplex
L
ON
Full-duplex
Toggle
Blinking
Collision
LED3
LED2
LED1
H
OFF
No Receive Activity
L
ON
Receive Activity
Toggle
Blinking
H
OFF
No Transmit Activity
L
ON
Transmit Activity
Toggle
Blinking
Each LED output pin can directly drive a LED with a series resistor (typically 220Ω to 470Ω).
For activity indication, the LED output toggles at approximately 12.5Hz (80ms) to ensure visibility to the human eye.
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KSZ9021GQ
3.10
NAND Tree Support
The KSZ9021GQ provides parametric NAND tree support for fault detection between chip I/Os and board. The NAND
tree mode is enabled at power-up / reset with the MODE[3:0] strap-in pins set to 0100.
The following table lists the NAND tree pin order.
TABLE 3-9:
NAND TREE TEST PIN ORDER – FOR KSZ9021GQ
Pin
Description
LED6
Input
LED5
Input
LED4
Input
LED3
Input
LED2
Input
LED1
Input
TXD0
Input
TXD1
Input
TXD2
Input
TXD3
Input
TXD4
Input
TXD5
Input
TXD6
Input
TXD7
Input
TX_ER
Input
GTX_CLK
Input
TX_EN
Input
RXD7
Input
RXD6
Input
RXD5
Input
RXD4
Input
RX_DV
Input
RX_ER
Input
RX_CLK
Input
CRS
Input
COL
Input
INT_N
Input
MDC
Input
A1
Input
MDIO
Input
CLK125_NDO
Output
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DS00003115A-page 31
KSZ9021GQ
3.11
Power Management
The KSZ9021GQ offers the following power management modes:
3.11.1
POWER SAVING MODE
This mode is a KSZ9021GQ green feature to reduce power consumption when the cable is unplugged. It is in effect
when auto-negotiation mode is enabled and the cable is disconnected (no link).
3.11.2
SOFTWARE POWER-DOWN MODE
This mode is used to power down the KSZ9021GQ device when it is not in use after power-up. Power-down mode is
enabled by writing a one to register 0h bit 11. In the power-down state, the KSZ9021GQ disables all internal functions,
except for the MII management interface. The KSZ9021GQ exits power-down mode after writing a zero to register 0h
bit 11.
3.11.3
CHIP POWER-DOWN MODE
This mode provides the lowest power state for the KSZ9021GQ when it is not in use and is mounted on the board. Chip
power-down mode is enabled at power-up / reset with the MODE[3:0] strap-in pins set to 0111. The KSZ9021GQ exits
chip power down mode when a hardware reset is applied to RESET_N (pin 110) with the MODE[3:0] strap-in pins set
to an operating mode other than chip power-down mode.
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KSZ9021GQ
4.0
REGISTER MAP
The IEEE 802.3 Specification provides a 32 register address space for the PHY. Registers 0 thru 15 are standard PHY
registers, defined per the specification. Registers 16 thru 31 are vendor specific registers.
The KSZ9021GQ uses the IEEE provided register space for IEEE Defined Registers and Vendor Specific Registers,
and uses the following registers to access Extended Registers:
• Register 11 (Bh) for Extended Register – Control
• Register 12 (Ch) for Extended Register – Data Write
• Register 13 (Dh) for Extended Register – Data Read
Examples:
• Extended Register Read
1. Write register 11 (Bh) with 0103h
2. Read register 13 (Dh)
// Read from Operation Mode Strap Status Register
// Set register 259 (103h) for read
// Read register value
• Extended Register Write
1. Write register 11 (Bh) with 8102h
2. Write register 12 (Ch) with 0010h
// Write to Operation Mode Strap Override Register
// Set register 258 (102h) for write
// Write 0010h value to register to set NAND Tree mode
Register Number (Hex)
Description
IEEE Defined Registers
0 (0h)
Basic Control
1 (1h)
Basic Status
2 (2h)
PHY Identifier 1
3 (3h)
PHY Identifier 2
4 (4h)
Auto-Negotiation Advertisement
5 (5h)
Auto-Negotiation Link Partner Ability
6 (6h)
Auto-Negotiation Expansion
7 (7h)
Auto-Negotiation Next Page
8 (8h)
Auto-Negotiation Link Partner Next Page Ability
9 (9h)
1000Base-T Control
10 (Ah)
1000Base-T Status
11 (Bh)
Extended Register – Control
12 (Ch)
Extended Register – Data Write
13 (Dh)
Extended Register – Data Read
14 (Eh)
Reserved
15 (Fh)
Extended – MII Status
Vendor Specific Registers
16 (10h)
Reserved
17 (11h)
Remote Loopback, LED Mode
18 (12h)
LinkMD® – Cable Diagnostic
19 (13h)
Digital PMA/PCS Status
20 (14h)
Reserved
21 (15h)
RXER Counter
22 (16h) – 26 (1Ah)
Reserved
27 (1Bh)
Interrupt Control/Status
28 (1Ch)
Digital Debug Control 1
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KSZ9021GQ
Register Number (Hex)
Description
29 (1Dh) – 30 (1Eh)
Reserved
31 (1Fh)
PHY Control
Extended Registers
257 (101h)
Strap Status
258 (102h)
Operation Mode Strap Override
259 (103h)
Operation Mode Strap Status
263 (107h)
Analog Test Register
4.1
Register Description
4.1.1
Address
IEEE DEFINED REGISTERS
Name
Description
Mode
(Note 1)
Default
Register 0 (0h) – Basic Control
0.15
Reset
1 = Software PHY reset
0 = Normal operation
RW/SC
0
This bit is self-cleared after a ‘1’ is written to
it.
0.14
Loop-back
1 = Loop-back mode
0 = Normal operation
RW
0
0.13
Speed Select
(LSB)
[0.6, 0.13]
[1,1] = Reserved
[1,0] = 1000Mbps
[0,1] = 100Mbps
[0,0] = 10Mbps
RW
Hardware Setting
RW
1
This bit is ignored if auto-negotiation is
enabled (register 0.12 = 1).
0.12
Auto-Negotia- 1 = Enable auto-negotiation process
tion Enable
0 = Disable auto-negotiation process
If enabled, auto-negotiation result overrides
settings in register 0.13, 0.8 and 0.6.
0.11
Power Down
1 = Power down mode
0 = Normal operation
RW
0
0.10
Isolate
1 = Electrical isolation of PHY from GMII/
MII
0 = Normal operation
RW
0
0.9
Restart AutoNegotiation
1 = Restart auto-negotiation process
0 = Normal operation
RW/SC
0
This bit is self-cleared after a ‘1’ is written to
it.
0.8
Duplex Mode
1 = Full-duplex
0 = Half-duplex
RW
Hardware Setting
0.7
Collision Test
1 = Enable COL test
0 = Disable COL test
RW
0
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KSZ9021GQ
Address
0.6
Name
Speed Select
(MSB)
Description
[0.6, 0.13]
[1,1] = Reserved
[1,0] = 1000Mbps
[0,1] = 100Mbps
[0,0] = 10Mbps
Mode
(Note 1)
Default
RW
0
RO
00_0000
This bit is ignored if auto-negotiation is
enabled (register 0.12 = 1).
0.5:0
Reserved
Register 1 (1h) – Basic Status
1.15
100Base-T4
1 = T4 capable
0 = Not T4 capable
RO
0
1.14
100Base-TX
Full Duplex
1 = Capable of 100Mbps full-duplex
0 = Not capable of 100Mbps full-duplex
RO
1
1.13
100Base-TX
Half Duplex
1 = Capable of 100Mbps half-duplex
0 = Not capable of 100Mbps half-duplex
RO
1
1.12
10Base-T Full 1 = Capable of 10Mbps full-duplex
Duplex
0 = Not capable of 10Mbps full-duplex
RO
1
1.11
10Base-T Half 1 = Capable of 10Mbps half-duplex
Duplex
0 = Not capable of 10Mbps half-duplex
RO
1
1.10:9
Reserved
RO
00
1.8
Extended Sta- 1 = Extended Status Information in Reg. 15. RO
tus
0 = No Extended Status Information in Reg.
15.
1
1.7
Reserved
RO
0
1.6
No Preamble
RO
1
1.5
Auto-Negotia- 1 = Auto-negotiation process completed
RO
tion Complete 0 = Auto-negotiation process not completed
0
1.4
Remote Fault
0
1.3
Auto-Negotia- 1 = Capable to perform auto-negotiation
RO
tion Ability
0 = Not capable to perform auto-negotiation
1
1.2
Link Status
RO/LL
0
1.1
Jabber Detect 1 = Jabber detected
0 = Jabber not detected (default is low)
RO/LH
0
1.0
Extended
Capability
RO
1
1 = Preamble suppression
0 = Normal preamble
1 = Remote fault
0 = No remote fault
1 = Link is up
0 = Link is down
1 = Supports extended capabilities registers
RO/LH
Register 2 (2h) – PHY Identifier 1
2.15:0
PHY ID Number
Assigned to the 3rd through 18th bits of the RO
Organizationally Unique Identifier (OUI).
Kendin Communication’s OUI is 0010A1
(hex)
0022h
Register 3 (3h) – PHY Identifier 2
3.15:10
PHY ID Number
Assigned to the 19th through 24th bits of
the Organizationally Unique Identifier
(OUI). Kendin Communication’s OUI is
0010A1 (hex)
2009-2019 Microchip Technology Inc.
RO
0001_01
DS00003115A-page 35
KSZ9021GQ
Address
Name
Description
Mode
(Note 1)
Default
3.9:4
Model Number
Six bit manufacturer’s model number
RO
10_0001
3.3:0
Revision
Number
Four bit manufacturer’s revision number
RO
Indicates silicon revision
RW
0
RO
0
RW
0
RO
0
Register 4 (4h) – Auto-Negotiation Advertisement
4.15
Next Page
1 = Next page capable
0 = No next page capability.
4.14
Reserved
4.13
Remote Fault
4.12
Reserved
4.11:10
Pause
[4.11, 4.10]
[0,0] = No PAUSE
[1,0] = Asymmetric PAUSE (link partner)
[0,1] = Symmetric PAUSE
[1,1] = Symmetric & Asymmetric PAUSE
(local device)
RW
00
4.9
100Base-T4
1 = T4 capable
0 = No T4 capability
RO
0
4.8
100Base-TX
Full-Duplex
1 = 100Mbps full-duplex capable
0 = No 100Mbps full-duplex capability
RW
1
4.7
100Base-TX
Half-Duplex
1 = 100Mbps half-duplex capable
0 = No 100Mbps half-duplex capability
RW
1
4.6
10Base-T
Full-Duplex
1 = 10Mbps full-duplex capable
0 = No 10Mbps full-duplex capability
RW
1
4.5
10Base-T
Half-Duplex
1 = 10Mbps half-duplex capable
0 = No 10Mbps half-duplex capability
RW
1
4.4:0
Selector Field [00001] = IEEE 802.3
RW
0_0001
1 = Remote fault supported
0 = No remote fault
Register 5 (5h) – Auto-Negotiation Link Partner Ability
5.15
Next Page
1 = Next page capable
0 = No next page capability
RO
0
5.14
Acknowledge
1 = Link code word received from partner
0 = Link code word not yet received
RO
0
5.13
Remote Fault
1 = Remote fault detected
0 = No remote fault
RO
0
5.12
Reserved
RO
0
5.11:10
Pause
[5.11, 5.10]
[0,0] = No PAUSE
[1,0] = Asymmetric PAUSE (link partner)
[0,1] = Symmetric PAUSE
[1,1] = Symmetric & Asymmetric PAUSE
(local device)
RW
00
5.9
100Base-T4
1 = T4 capable
0 = No T4 capability
RO
0
5.8
100Base-TX
Full-Duplex
1 = 100Mbps full-duplex capable
0 = No 100Mbps full-duplex capability
RO
0
5.7
100Base-TX
Half-Duplex
1 = 100Mbps half-duplex capable
0 = No 100Mbps half-duplex capability
RO
0
5.6
10Base-T
Full-Duplex
1 = 10Mbps full-duplex capable
0 = No 10Mbps full-duplex capability
RO
0
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KSZ9021GQ
Address
Name
Description
5.5
10Base-T
Half-Duplex
1 = 10Mbps half-duplex capable
0 = No 10Mbps half-duplex capability
5.4:0
Selector Field [00001] = IEEE 802.3
Mode
(Note 1)
Default
RO
0
RO
0_0000
RO
0000_0000_000
Register 6 (6h) – Auto-Negotiation Expansion
6.15:5
Reserved
6.4
Parallel
Detection
Fault
1 = Fault detected by parallel detection
0 = No fault detected by parallel detection.
RO/LH
0
6.3
Link Partner
Next Page
Able
1 = Link partner has next page capability
0 = Link partner does not have next page
capability
RO
0
6.2
Next Page
Able
1 = Local device has next page capability
0 = Local device does not have next page
capability
RO
1
6.1
Page
Received
1 = New page received
0 = New page not received yet
RO/LH
0
6.0
Link Partner
1 = Link partner has auto-negotiation capa- RO
Auto-Negotia- bility
tion Able
0 = Link partner does not have auto-negotiation capability
0
Register 7 (7h) – Auto-Negotiation Next Page
7.15
Next Page
1 = Additional next page(s) will follow
0 = Last page
RW
0
7.14
Reserved
7.13
Message
Page
1 = Message page
0 = Unformatted page
RO
0
RW
1
7.12
Acknowledge2
1 = Will comply with message
0 = Cannot comply with message
RW
0
7.11
Toggle
1 = Previous value of the transmitted link
code word equaled logic one
0 = Logic zero
RO
0
7.10:0
Message
Field
11-bit wide field to encode 2048 messages RW
000_0000_0001
Register 8 (8h) – Auto-Negotiation Link Partner Next Page Ability
8.15
Next Page
1 = Additional Next Page(s) will follow
0 = Last page
RO
0
8.14
Acknowledge
1 = Successful receipt of link word
0 = No successful receipt of link word
RO
0
8.13
Message
Page
1 = Message page
0 = Unformatted page
RO
0
8.12
Acknowledge2
1 = Able to act on the information
0 = Not able to act on the information
RO
0
8.11
Toggle
1 = Previous value of transmitted link code
word equal to logic zero
0 = Previous value of transmitted link code
word equal to logic one
RO
0
8.10:0
Message
Field
RO
000_0000_0000
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DS00003115A-page 37
KSZ9021GQ
Address
Name
Description
Mode
(Note 1)
Default
Register 9 (9h) – 1000Base-T Control
9:15:13
Test Mode
Bits
Transmitter test mode operations
[9.15:13]
Mode
[000] Normal Operation
[001] Test mode 1 –Transmit waveform
test
[010] Test mode 2 –Transmit jitter test in
Master mode
[011] Test mode 3 –Transmit jitter test in
Slave mode
[100] Test mode 4 –Transmitter distortion
test
[101] Reserved, operations not identified
[110] Reserved, operations not identified
[111] Reserved, operations not identified
RW
000
9.12
MASTERSLAVE
Manual Config Enable
1 = Enable MASTER-SLAVE Manual configuration value
0 = Disable MASTER-SLAVE Manual configuration value
RW
0
9.11
MASTERSLAVE
Manual Config Value
1 = Configure PHY as MASTER during
RW
MASTER-SLAVE negotiation
0 = Configure PHY as SLAVE during MASTER-SLAVE negotiation
0
This bit is ignored if MASTER-SLAVE Manual Config is disabled (register 9.12 = 0).
9.10
Port Type
1 = Indicate the preference to operate as
multiport device (MASTER)
0 = Indicate the preference to operate as
single-port device (SLAVE)
RW
0
This bit is valid only if the MASTER-SLAVE
Manual Config Enable bit is disabled (register 9.12 = 0).
9.9
1000Base-T
Full-Duplex
1 = Advertise PHY is 1000Base-T fullduplex capable
0 = Advertise PHY is not 1000Base-T full
duplex capable
RW
1
9.8
1000Base-T
Half-Duplex
1 = Advertise PHY is 1000Base-T halfduplex capable
0 = Advertise PHY is not 1000Base-T halfduplex capable
RW
Hardware Setting
9.7:0
Reserved
Write as 0, ignore on read
RO
Register 10 (Ah) – 1000Base-T Status
10.15
MASTERSLAVE
configuration
fault
1 = MASTER-SLAVE configuration fault
RO/LH/
detected
SC
0 = No MASTER-SLAVE configuration fault
detected
0
10.14
MASTERSLAVE
configuration
resolution
1 = Local PHY configuration resolved to
MASTER
0 = Local PHY configuration resolved to
SLAVE
0
DS00003115A-page 38
RO
2009-2019 Microchip Technology Inc.
KSZ9021GQ
Address
Name
Description
Mode
(Note 1)
Default
10.13
Local
1 = Local Receiver OK (loc_rcvr_status = 1) RO
Receiver Sta- 0 = Local Receiver not OK (loc_rcvr_status
tus
= 0)
0
10.12
Remote
1 = Remote Receiver OK (rem_rcvr_status RO
Receiver Sta- = 1)
tus
0 = Remote Receiver not OK
(rem_rcvr_status = 0)
0
10.11
LP 1000T FD
1 = Link Partner is capable of 1000Base-T
full-duplex
0 = Link Partner is not capable of
1000Base-T full-duplex
RO
0
10.10
LP 1000T HD
1 = Link Partner is capable of 1000Base-T
half-duplex
0 = Link Partner is not capable of
1000Base-T half-duplex
RO
0
10.9:8
Reserved
10.7:0
Idle Error
Count
Cumulative count of errors detected when
receiver is receiving idles and PMA_TXMODE.indicate = SEND_N.
RO
00
RO/SC
0000_0000
RW
0
The counter is incremented every symbol
period that rxerror_status = ERROR.
Register 11 (Bh) – Extended Register – Control
11.15
Extended
Register –
read/write
select
1 = Write Extended Register
0 = Read Extended Register
11.14:9
Reserved
RW
000_000
11.8
Extended
Register –
page
Select page for Extended Register
RW
0
11.7:0
Extended
Register –
address
Select Extended Register Address
RW
0000_0000
RW
0000_0000_0000_0000
RO
0000_0000_0000_0000
Register 12 (Ch) – Extended Register – Data Write
12.15:0
Extended
Register –
write
16-bit value to write to Extend Register
Address in register 11 (Bh) bits [7:0]
Register 13 (Dh) – Extended Register – Data Read
13.15:0
Extended
Register –
read
16-bit value read from Extend Register
Address in register 11 (Bh) bits [7:0]
Register 15 (Fh) – Extended – MII Status
15.15
1000Base-X
Full-duplex
1 = PHY able to perform 1000Base-X fullduplex
0 = PHY not able to perform 1000Base-X
full-duplex
RO
0
15.14
1000Base-X
Half-duplex
1 = PHY able to perform 1000Base-X halfduplex
0 = PHY not able to perform 1000Base-X
half-duplex
RO
0
2009-2019 Microchip Technology Inc.
DS00003115A-page 39
KSZ9021GQ
Address
Name
Description
Mode
(Note 1)
Default
15.13
1000Base-T
Full-duplex
1 = PHY able to perform 1000Base-T fullduplex 1000BASE-X
0 = PHY not able to perform 1000Base-T
full-duplex
RO
1
15.12
1000Base-T
Half-duplex
1 = PHY able to perform 1000Base-T halfduplex
0 = PHY not able to perform 1000Base-T
half-duplex
RO
1
15.11:0
Reserved
Ignore when read
RO
-
Note 1:
RW = Read/Write.
RO = Read only.
SC = Self-cleared.
LH = Latch high.
LL = Latch low.
4.1.2
Address
VENDOR SPECIFIC REGISTERS
Name
Description
Mode
(Note 1)
Default
Register 17 (11h) – Remote Loopback, LED Mode
17.15:9
Reserved
RW
0000_001
17.8
Remote
Loopback
1 = Enable Remote Loopback
0 = Disable Remote Loopback
RW
0
17.7:6
LED Mode
Select
[17.7, 17.6]
[0,0] = Reserved – not used
[1,0] = 4-LED Configuration
[0,1] = 5-LED Configuration
[1,1] = 6-LED Configuration
RW
11
17.5:4
Reserved
RW
11
17.3
LED Test
Enable
RW
0
17.2:1
Reserved
RW
00
17.0
Reserved
RO
0
Reserved
RW/SC
0
18.14:8
Reserved
RW
000_0000
18.7:0
Reserved
RO
0000_0000
RO/LH
0000_0000_0000_0
1 = Enable LED test mode
0 = Disable LED test mode
Register 18 (12h) – LinkMD® – Cable Diagnostic
18.15
Register 19 (13h) – Digital PMA/PCS Status
19.15:3
Reserved
19.2
1000Base-T
Link Status
1000 Base-T Link Status
1 = Link status is OK
0 = Link status is not OK
RO
0
19.1
100Base-TX
Link Status
100 Base-TX Link Status
1 = Link status is OK
0 = Link status is not OK
RO
0
DS00003115A-page 40
2009-2019 Microchip Technology Inc.
KSZ9021GQ
Address
19.0
Name
Description
Reserved
Mode
(Note 1)
Default
RO
0
RO/RC
0000_0000_0000_0000
RW
0
Register 21 (15h) – RXER Counter
21.15:0
RXER
Counter
Receive error counter for Symbol Error
frames
Register 27 (1Bh) – Interrupt Control/Status
27.15
Jabber Interrupt Enable
1 = Enable Jabber Interrupt
0 = Disable Jabber Interrupt
27.14
Receive Error 1 = Enable Receive Error Interrupt
Interrupt
0 = Disable Receive Error Interrupt
Enable
RW
0
27.13
Page
Received
Interrupt
Enable
1 = Enable Page Received Interrupt
0 = Disable Page Received Interrupt
RW
0
27.12
Parallel
Detect Fault
Interrupt
Enable
1 = Enable Parallel Detect Fault Interrupt
0 = Disable Parallel Detect Fault Interrupt
RW
0
27.11
Link Partner
Acknowledge
Interrupt
Enable
1 = Enable Link Partner Acknowledge
Interrupt
0 = Disable Link Partner Acknowledge
Interrupt
RW
0
27.10
Link Down
Interrupt
Enable
1 = Enable Link Down Interrupt
0 = Disable Link Down Interrupt
RW
0
27.9
Remote Fault 1 = Enable Remote Fault Interrupt
Interrupt
0 = Disable Remote Fault Interrupt
Enable
RW
0
27.8
Link Up Inter- 1 = Enable Link Up Interrupt
rupt Enable
0 = Disable Link Up Interrupt
RW
0
27.7
Jabber Interrupt
1 = Jabber occurred
0 = Jabber did not occurred
RO/RC
0
27.6
Receive Error
Interrupt
1 = Receive Error occurred
0 = Receive Error did not occurred
RO/RC
0
27.5
Page Receive 1 = Page Receive occurred
Interrupt
0 = Page Receive did not occurred
RO/RC
0
27.4
Parallel
Detect Fault
Interrupt
RO/RC
0
27.3
Link Partner
1 = Link Partner Acknowledge occurred
Acknowledge 0 = Link Partner Acknowledge did not
Interrupt
occurred
RO/RC
0
27.2
Link Down
Interrupt
RO/RC
0
27.1
Remote Fault 1 = Remote Fault occurred
Interrupt
0 = Remote Fault did not occurred
RO/RC
0
27.0
Link Up Inter- 1 = Link Up occurred
rupt
0 = Link Up did not occurred
RO/RC
0
1 = Parallel Detect Fault occurred
0 = Parallel Detect Fault did not occurred
1 = Link Down occurred
0 = Link Down did not occurred
2009-2019 Microchip Technology Inc.
DS00003115A-page 41
KSZ9021GQ
Address
Name
Description
Mode
(Note 1)
Default
Register 28 (1Ch) – Digital Debug Control 1
28.15:8
Reserved
28.7
mdi_set
mdi_set has no function when swapoff
(reg28.6) is de-asserted
RW
0000_0000
RW
0
RW
0
RW
00_000
RW
0
RW
0
RW
0
1 = When swapoff is asserted, if mdi_set is
asserted, chip will operate at MDI mode
0 = When swapoff is asserted, if mdi_set is
de-asserted, chip will operate at MDI-X
mode
28.6
swapoff
28.5:1
Reserved
28.0
PCS Loopback
1 = Disable auto crossover function
0 = Enable auto crossover function
1 = Enable 10Base-T and 100Base-TX
Loopback for register 0h bit 14
0 = normal function
Register 31 (1Fh) – PHY Control
31.15
Reserved
31.14
Interrupt
Level
31.13:12
Reserved
RW
00
31.11:10
Reserved
RO/LH/
RC
00
31.9
Enable Jabber
RW
1
31.8:7
Reserved
RW
00
31.6
Speed status
1000Base-T
1 = Indicate chip final speed status at
1000Base-T
RO
0
31.5
Speed status
100Base-TX
1 = Indicate chip final speed status at
100Base-TX
RO
0
31.4
Speed status
10Base-T
1 = Indicate chip final speed status at
10Base-T
RO
0
31.3
Duplex status Indicate chip duplex status
1 = Full-duplex
0 = Half-duplex
RO
0
31.2
1000Base-T
Mater/Slave
status
1 = Indicate 1000Base-T Master mode
0 = Indicate 1000Base-T Slave mode
RO
0
31.1
Software
Reset
1 = Reset chip, except all registers
0 = Disable reset
RW
0
31.0
Link Status
Check Fail
1 = Fail
0 = Not Failing
RO
0
1 = Interrupt pin active high
0 = Interrupt pin active low
1 = Enable jabber counter
0 = Disable jabber counter
Note 1:
RW = Read/Write.
RC = Read-cleared
RO = Read only.
SC = Self-cleared.
LH = Latch high.
DS00003115A-page 42
2009-2019 Microchip Technology Inc.
KSZ9021GQ
4.1.3
Address
EXTENDED REGISTERS
Name
Description
Mode
(Note 1)
Default
Register 257 (101h) – Strap Status
257.15:6
Reserved
257.5
CLK125_EN
status
1 = CLK125_EN strap-in is enabled
0 = CLK125_EN strap-in is disabled
RO
RO
257.4:0
PHYAD[4:0]
status
Strapped-in value for PHY Address
RO
Register 258 (102h) – Operation Mode Strap Override
258.15:8
Reserved
258.7
Tri-state all
digital I/Os
258.6:5
Reserved
258.4
NAND Tree
override
258.3:2
Reserved
258.1
GMII / MII
override
258.0
Reserved
RW
1 = Tri-state all digital I/Os for further
RW
power saving during software power down
0
RW
1 = Override strap-in for NAND Tree mode RW
RW
1 = Override strap-in for GMII / MII mode
RW
RW
Register 259 (103h) – Operation Mode Strap Status
259.15:5
Reserved
RO
259.4
NAND Tree
1 = Strap to NAND tree mode
strap-in status
RO
259.3:2
Reserved
RO
259.1
GMII / MII
1 = Strap to GMII / MII mode
strap-in status
RO
259.0
Reserved
RO
Register 263 (107h) – Analog Test Register
263.15
LDO disable
263.14:9
Reserved
263.8
Low frequency oscillator mode
1 = LDO controller disable
0 = LDO controller enable
RW
0
RW
000_000
1 = Low frequency oscillator mode enable RW
0 = Low frequency oscillator mode disable
0
Use for further power saving during software power down
263.7:0
Reserved
RW
0000_0000
Note 1:
RW = Read/Write.
RO = Read only.
2009-2019 Microchip Technology Inc.
DS00003115A-page 43
KSZ9021GQ
5.0
OPERATIONAL CHARACTERISTICS
5.1
Absolute Maximum Ratings (See Note 1)
Supply Voltage
(DVDDL, AVDDL, AVDDL_PLL) ...........................................................................................................-0.5V to VDD+10%
(AVDDH)..............................................................................................................................................-0.5V to VDD +10%
(DVDDH) .............................................................................................................................................-0.5V to VDD +10%
Input Voltage (all inputs)......................................................................................................................-0.5V to VDD +10%
Output Voltage (all outputs).................................................................................................................-0.5V to VDD +10%
Lead Temperature (soldering, 10sec.)..................................................................................................................... 260°C
Storage Temperature (Ts)........................................................................................................................-55°C to +150°C
5.2
Operating Ratings (See Note 2)
Supply Voltage
(DVDDL, AVDDL, AVDDL_PLL) ........................................................................................................ +1.140V to +1.260V
(AVDDH)............................................................................................................................................ +3.135V to +3.465V
(DVDDH @ 3.3V) .............................................................................................................................. +3.135V to +3.465V
(DVDDH @ 2.5V) .............................................................................................................................. +2.375V to +2.625V
Ambient Temperature
(TA Commercial: KSZ9021GQ) ....................................................................................................................0°C to +70°C
(TA Industrial: KSZ9021GQI)40°C to +85°C
Maximum Junction Temperature (TJ Max)............................................................................................................... 125°C
Thermal Resistance (JA).................................................................................................................................41.54°C/W
Thermal Resistance (JC).................................................................................................................................19.78°C/W
5.3
Electrical Characteristics (See Note 3)
Symbol
Parameter
Condition
Min
Typ
Max
Units
Supply Current – Core / Digital I/Os
ICORE
1.2V total of:
1000Base-T Link-up (no traffic)
DVDDL (1.2V digital core) + 1000Base-T Full-duplex @ 100% utilizaAVDDL (1.2V analog core) + tion
AVDDL_PLL (1.2V for PLL)
100Base-TX Link-up (no traffic)
100Base-TX Full-duplex @ 100% utilization
10Base-T Link-up (no traffic)
DS00003115A-page 44
522
mA
555
mA
159
mA
160
mA
7
mA
10Base-T Full-duplex @ 100% utilization
7
mA
Power-saving Mode (cable un-plugged)
15
mA
Software Power Down Mode (register
0.11 =1)
1.3
mA
Chip Power Down Mode
(strap-in pins MODE[3:0] = 0111)
1.2
mA
2009-2019 Microchip Technology Inc.
KSZ9021GQ
Symbol
IDVDDH_2.5
IDVDDH_3.3
Parameter
2.5V for digital I/Os
(GMII / MII operating @
2.5V)
3.3V for digital I/Os
(GMII / MII operating @
3.3V)
Condition
Min
Typ
Max
Units
1000Base-T Link-up (no traffic)
22
mA
1000Base-T Full-duplex @ 100% utilization
39
mA
100Base-TX Link-up (no traffic)
15
mA
100Base-TX Full-duplex @ 100% utilization
19
mA
10Base-T Link-up (no traffic)
10
mA
10Base-T Full-duplex @ 100% utilization
11
mA
Power-saving Mode (cable un-plugged)
14
mA
Software Power Down Mode (register
0.11 =1)
8
mA
Chip Power Down Mode
(strap-in pins MODE[3:0] = 0111)
1
mA
1000Base-T Link-up (no traffic)
32
mA
1000Base-T Full-duplex @ 100% utilization
57
mA
100Base-TX Link-up (no traffic)
19
mA
100Base-TX Full-duplex @ 100% utilization
25
mA
10Base-T Link-up (no traffic)
13
mA
10Base-T Full-duplex @ 100% utilization
17
mA
Power-saving Mode (cable un-plugged)
23
mA
Software Power Down Mode (register
0.11 =1)
16
mA
Chip Power Down Mode
(strap-in pins MODE[3:0] = 0111)
1
mA
Supply Current – Transceiver (equivalent to current draw through external transformer center taps for PHY transceivers with current-mode transmit drivers)
IAVDDH
3.3V for transceiver
1000Base-T Link-up (no traffic)
74
mA
1000Base-T Full-duplex @ 100% utilization
73
mA
100Base-TX Link-up (no traffic)
28
mA
100Base-TX Full-duplex @ 100% utilization
28
mA
10Base-T Link-up (no traffic)
35
mA
10Base-T Full-duplex @ 100% utilization
43
mA
Power-saving Mode (cable un-plugged)
35
mA
Software Power Down Mode (register
0.11 =1)
2
mA
Chip Power Down Mode
(strap-in pins MODE[3:0] = 0111)
1
mA
CMOS Inputs
VIH
VIL
IIN
Input High Voltage
Input Low Voltage
Input Current
2009-2019 Microchip Technology Inc.
DVDDH = 3.3V
2.0
V
DVDDH = 2.5V
1.8
V
DVDDH = 3.3V
0.8
V
DVDDH = 2.5V
0.7
V
10
µA
VIN = GND ~ VDDIO
-10
DS00003115A-page 45
KSZ9021GQ
Symbol
Parameter
Condition
Min
Typ
Max
Units
CMOS Outputs
VOH
Output High Voltage
DVDDH = 3.3V
2.4
DVDDH = 2.5V
2.0
VOL
Output Low Voltage
DVDDH = 3.3V
0.4
DVDDH = 2.5V
0.4
V
|Ioz|
Output Tri-State Leakage
10
µA
V
V
V
LED Outputs
ILED
Output Drive Current
Each LED pin (LED1, LED2, LED4, LED5,
LED6)
8
mA
100Base-TX Transmit (measured differentially after 1:1 transformer)
VO
Peak Differential Output Volt- 100 termination across differential outage
put
0.95
VIMB
Output Voltage Imbalance
tr, tf
Rise/Fall Time
3
Rise/Fall Time Imbalance
0
100 termination across differential output
Duty Cycle Distortion
Overshoot
VSET
Reference Voltage of ISET
R(ISET) = 4.99K
Output Jitter
Peak-to-peak
1.05
V
2
%
5
ns
0.5
ns
± 0.25
ns
5
%
0.535
0.7
V
1.4
ns
2.8
V
10Base-T Transmit (measured differentially after 1:1 transformer)
VP
Peak Differential Output Volt- 100 termination across differential outage
put
Jitter Added
Peak-to-peak
Harmonic Rejection
Transmit all-one signal sequence
2.2
3.5
ns
-31
dB
400
mV
10Base-T Receive
VSQ
Squelch Threshold
5MHz square wave
300
Note 1: Exceeding the absolute maximum rating may damage the device. Stresses greater than the absolute maximum rating may cause permanent damage to the device. Operation of the device at these or any other
conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability.
2: The device is not guaranteed to function outside its operating rating.
3: TA = 25°C. Specification is for packaged product only.
DS00003115A-page 46
2009-2019 Microchip Technology Inc.
KSZ9021GQ
6.0
TIMING DIAGRAMS
6.1
GMII Transmit Timing
FIGURE 6-1:
TABLE 6-1:
GMII TRANSMIT TIMING – DATA INPUT TO PHY
GMII TRANSMIT TIMING PARAMETERS
Timing Parameter
Description
Min
Typ
Max
Unit
tcyc
GTX_CLK period
7.5
8.0
8.5
ns
tsu
TX_EN, TXD[7:0], TX_ER setup time to rising
edge of GTX_CLK
2.0
ns
thd
TX_EN, TXD[7:0], TX_ER hold time from rising
edge of GTX_CLK
0
ns
thi
GTX_CLK high pulse width
2.5
ns
tlo
GTX_CLK low pulse width
2.5
ns
tr
GTX_CLK rise time
1.0
ns
tf
GTX_CLK fall time
1.0
ns
1000Base-T
2009-2019 Microchip Technology Inc.
DS00003115A-page 47
KSZ9021GQ
6.2
GMII Receive Timing
FIGURE 6-2:
TABLE 6-2:
GMII RECEIVE TIMING – DATA INPUT TO MAC
GMII RECEIVE TIMING PARAMETERS
Timing Parameter
Description
Min
Typ
Max
Unit
tcyc
RX_CLK period
7.5
8.0
8.5
ns
tsu
RX_DV, RXD[7:0], RX_ER setup time to rising
edge of RX_CLK
2.5
ns
thd
RX_DV, RXD[7:0], RX_ER hold time from rising
edge of RX_CLK
0.5
ns
thi
RX_CLK high pulse width
2.5
ns
tlo
RX_CLK low pulse width
2.5
tr
RX_CLK rise time
1.0
ns
tf
RX_CLK fall time
1.0
ns
1000Base-T
DS00003115A-page 48
ns
2009-2019 Microchip Technology Inc.
KSZ9021GQ
6.3
MII Transmit Timing
FIGURE 6-3:
TABLE 6-3:
MII TRANSMIT TIMING – DATA INPUT TO PHY
MII TRANSMIT TIMING PARAMETERS
Timing Parameter
Description
Min
Typ
Max
Unit
10Base-T
tcyc
TX_CLK period
tsu
TX_EN, TXD[3:0], TX_ER setup time to rising
edge of TX_CLK
15
400
ns
ns
thd
TX_EN, TXD[3:0], TX_ER hold time from rising
edge of TX_CLK
0
ns
thi
TX_CLK high pulse width
140
260
ns
tlo
TX_CLK low pulse width
140
260
ns
100Base-TX
tcyc
TX_CLK period
tsu
TX_EN, TXD[3:0], TX_ER setup time to rising
edge of TX_CLK
15
ns
thd
TX_EN, TXD[3:0], TX_ER hold time from rising
edge of TX_CLK
0
ns
thi
TX_CLK high pulse width
14
26
ns
tlo
TX_CLK low pulse width
14
26
ns
2009-2019 Microchip Technology Inc.
40
ns
DS00003115A-page 49
KSZ9021GQ
6.4
MII Receive Timing
FIGURE 6-4:
TABLE 6-4:
MII RECEIVE TIMING – DATA INPUT TO MAC
MII RECEIVE TIMING PARAMETERS
Timing Parameter
Description
Min
Typ
Max
Unit
10Base-T
tcyc
RX_CLK period
tsu
RX_DV, RXD[3:0], RX_ER setup time to rising
edge of RX_CLK
10
400
ns
ns
thd
RX_DV, RXD[3:0], RX_ER hold time from rising
edge of RX_CLK
10
ns
thi
RX_CLK high pulse width
140
260
ns
tlo
RX_CLK low pulse width
140
260
ns
100Base-TX
tcyc
RX_CLK period
40
ns
tsu
RX_DV, RXD[3:0], RX_ER setup time to rising
edge of RX_CLK
10
ns
thd
RX_DV, RXD[3:0], RX_ER hold time from rising
edge of RX_CLK
10
ns
thi
RX_CLK high pulse width
14
26
ns
tlo
RX_CLK low pulse width
14
26
ns
DS00003115A-page 50
2009-2019 Microchip Technology Inc.
KSZ9021GQ
6.5
Auto-Negotiation Timing
FIGURE 6-5:
AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING
AUTO-NEGOTIATION
FAST LINK PULSE (FLP) TIMING
FLP
BURST
FLP
BURST
TX+/TX-
tFLPW
tBTB
CLOCK
PULSE
TX+/TX-
tPW
DATA
PULSE
DATA
PULSE
CLOCK
PULSE
tPW
tCTD
tCTC
TABLE 6-5:
AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING PARAMETERS
Timing Parameter
Description
tBTB
FLP Burst to FLP Burst
tFLPW
FLP Burst width
tPW
Clock/Data Pulse width
tCTD
Clock Pulse to Data Pulse
55.5
64
69.5
µs
tCTC
Clock Pulse to Clock Pulse
111
128
139
µs
Number of Clock/Data Pulse per FLP
Burst
17
2009-2019 Microchip Technology Inc.
Min
Typ
Max
Units
8
16
24
ms
2
ms
100
ns
33
DS00003115A-page 51
KSZ9021GQ
6.6
MDC/MDIO Timing
FIGURE 6-6:
MDC/MDIO TIMING
tP
MDC
tMD1
tMD2
VALID
DATA
MDIO
(PHY INPUT)
VALID
DATA
tMD3
VALID
DATA
MDIO
(PHY OUTPUT)
TABLE 6-6:
MDC/MDIO TIMING PARAMETERS
Timing Parameter
Description
Min
Typ
Unit
tP
MDC period
t1MD1
MDIO (PHY input) setup to rising edge of MDC
10
tMD2
MDIO (PHY input) hold from rising edge of MDC
10
ns
tMD3
MDIO (PHY output) delay from rising edge of MDC
0
ns
DS00003115A-page 52
400
Max
ns
ns
2009-2019 Microchip Technology Inc.
KSZ9021GQ
6.7
Reset Timing
The recommended KSZ9021GQ power-p reset timing is summarized in the following figure and table.
FIGURE 6-7:
RESET TIMING
SUPPLY
VOLTAGE
tsr
RESET_N
TABLE 6-7:
RESET TIMING PARAMETERS
Parameter
Description
Min
tsr
Stable supply voltage to reset high
10
Max
Units
ms
After the de-assertion of reset, it is recommended to wait a minimum of 100µs before starting programming on the MIIM
(MDC/MDIO) Interface.
2009-2019 Microchip Technology Inc.
DS00003115A-page 53
KSZ9021GQ
6.8
Reset Circuit
The following reset circuit is recommended for powering up the KSZ9021GQ if reset is triggered by the power supply.
FIGURE 6-8:
RECOMMENDED RESET CIRCUIT
DVDDH
D1: 1N4148
D1
KSZ9021GQ
R 10K
RESET_N
C 10uF
The following reset circuit is recommended for applications where reset is driven by another device (e.g., CPU or
FPGA). At power-on-reset, R, C and D1 provide the necessary ramp rise time to reset the KSZ9021GQ device. The
RST_OUT_N from CPU/FPGA provides the warm reset after power up.
FIGURE 6-9:
RECOMMENDED RESET CIRCUIT FOR INTERFACING WITH CPU/FPGA RESET
OUTPUT
DVDDH
KSZ9021GQ
R 10K
D1
CPU/FPGA
RESET_N
RST_OUT_N
D2
C 10uF
D1, D2: 1N4148
DS00003115A-page 54
2009-2019 Microchip Technology Inc.
KSZ9021GQ
6.9
Reference Circuits – LED Strap-in Pins
The pull-up and pull-down reference circuits for the LED5/PHYAD4, LED4/PHYAD3, LED3/PHYAD2, LED2/PHYAD1
and LED1/PHYAD0 strapping pins are shown in the following figure.
FIGURE 6-10:
REFERENCE CIRCUITS FOR LED STRAPPING PINS
DVDDH
PULL-UP
KSZ9021GQ
LED PIN
DVDDH
PULL-DOWN
KSZ9021GQ
LED PIN
2009-2019 Microchip Technology Inc.
DS00003115A-page 55
KSZ9021GQ
6.10
Reference Clock – Connection and Selection
A crystal or external clock source, such as an oscillator, is used to provide the reference clock for the KSZ9021GQ. The
reference clock is 25 MHz for all operating modes of the KSZ9021GQ.
The following figure and table shows the reference clock connection to XI (pin 124) and XO (pin 123) of the
KSZ9021GQ, and the reference clock selection criteria.
FIGURE 6-11:
25MHZ CRYSTAL / OSCILLATOR REFERENCE CLOCK CONNECTION
22pF
22pF
XI
XI
25MHz OSC
+/-50ppm
22pF
22pF
XO
NC
TABLE 6-8:
XO
NC
25MHz XTAL
+/-50ppm
REFERENCE CRYSTAL/CLOCK SELECTION CRITERIA
Characteristics
Value
Units
Frequency
25
MHz
Frequency tolerance (max)
50
ppm
6.11
Magnetics Specification
A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode
chokes is recommended for exceeding FCC requirements.
The following tables provide recommended magnetic characteristics and a list of qualified magnetics for the
KSZ9021GQ.
TABLE 6-9:
MAGNETICS SELECTION CRITERIA
Parameter
Value
Turns ratio
1 CT : 1 CT
Test Condition
Open-circuit inductance (min.)
350H
100mV, 100kHz, 8mA
Insertion loss (max.)
1.0dB
0MHz – 100MHz
HIPOT (min.)
1500Vrms
TABLE 6-10:
QUALIFIED SINGLE PORT 10/100/1000 MAGNETICS
Magnetic Manufacturer
Part Number
Pulse
TDK
DS00003115A-page 56
Auto MDI-X
Number of Port
H5007NL
Yes
1
TLA-7T101LF
Yes
1
2009-2019 Microchip Technology Inc.
KSZ9021GQ
7.0
PACKAGE INFORMATION
FIGURE 7-1:
Note:
128-PIN (14MM X 20MM) PQFP PACKAGE OUTLINE AND RECOMMENDED
LAND PATTERN
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
2009-2019 Microchip Technology Inc.
DS00003115A-page 57
KSZ9021GQ
APPENDIX A:
TABLE A-1:
DATA SHEET REVISION HISTORY
REVISION HISTORY
Revision
DS00003115A (07-18-19)
Section/Figure/Entry
Correction
Replaces previous Micrel version M9999-091010-1.2
1.2 (09-10-10)
All
Added support for 2.5V VDD I/O.
Added LED drive current.
Updated KSZ9021GQ pin outs throughout data
sheet to reflect pin out changes for silicon revision
A3.
Updated boilerplate.
1.1 (10-13-09)
All
Updated current consumption in Electrical Characteristics section.
Corrected data sheet omission of register 1 bit 8 for
1000Base-T Extended Status information.
Added the following register bits to provide further
power saving during software power down: Tristate all digital I/Os (reg. 258.7), LDO disable (reg.
263.15), Low frequency oscillator mode (reg. 263.8).
Corrected tsu minimum for 1000Base-T in GMII
Receive Timing Parameters table.
1.0 (01-16-09)
Data Sheet created
DS00003115A-page 58
2009-2019 Microchip Technology Inc.
KSZ9021GQ
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make
files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information:
• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion
groups, Microchip consultant program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive
e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or
development tool of interest.
To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales
offices are also available to help customers. A listing of sales offices and locations is included in the back of this document.
Technical support is available through the web site at: http://www.microchip.com/support
2009-2019 Microchip Technology Inc.
DS00003115A-page 59
KSZ9021GQ
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
-
[X]
Temperature
Range
Device:
KSZ9021GQ
Temperature:
Blank
I
Package:
GQ
Tape and Reel
Option:
Blank
TR
DS00003115A-page 60
=
0C to
= -40C to
=
XXX
-
Package
+70C
+85C
[X](1)
Tape and Reel
Option
(Commercial)
(Industrial)
128-pin PQFP
= Standard packaging (tray)
= Tape and Reel(1)
Examples:
a)
KSZ9021GQ
Commercial Temperature, GMII/MII
128-pin PQFP,
RoHS Compliant package, Tray
b)
KSZ9021GQI
Industrial Temperature, GMII/MII
128-pin PQFP,
RoHS Compliant package, Tray
Note 1:
Tape and Reel identifier only appears in the
catalog part number description. This
identifier is used for ordering purposes and is
not printed on the device package. Check
with your Microchip Sales Office for package
availability with the Tape and Reel option.
2009-2019 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be
superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO
REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold
harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or
otherwise, under any Microchip intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch,
MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo,
PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and
other countries.
APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero,
motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux,
TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the
U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM,
ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain,
Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net,
PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher,
SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in
other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other
countries.
All other trademarks mentioned herein are property of their respective companies.
© 2009-2019, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 9781522445920
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2009-2019 Microchip Technology Inc.
DS00003115A-page 61
Worldwide Sales and Service
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DS00003115A-page 62
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05/14/19
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