LAN9221/LAN9221i
High-Performance 16-bit Non-PCI 10/100 Ethernet Controller
with Variable Voltage I/O
Highlights
•
•
•
•
Optimized for high performance applications
Efficient architecture with low CPU overhead
Easily interfaces to most 16-bit embedded CPU’s
1.8V to 3.3V variable voltage I/O accommodates
wide range of I/O signalling without voltage level
shifters
• Integrated PHY with HP Auto-MDIX support
• Integrated checksum offload engine helps reduce
CPU load
• Low pin count and small body size package for
small form factor system designs
Target Applications
•
•
•
•
•
•
•
Cable, satellite, and IP set-top boxes
Digital video recorders and DVD recorder/players
Digital TV
Digital media clients/servers and home gateways
Video-over IP solutions, IP PBX & video phones
Wireless routers & access points
High-end audio distribution systems
Key Benefits
• Non-PCI Ethernet controller for high performance
applications
- 16-bit interface with fast bus cycle times
- Burst-mode read support
• Minimizes dropped packets
- Internal buffer memory can store over 200
packets
- Automatic PAUSE and back-pressure flow
control
• Minimizes CPU overhead
- Supports Slave-DMA
- Interrupt Pin with Programmable Hold-off
timer
• Reduces system cost and increases design flexibility
• SRAM-like interface easily interfaces to most
embedded CPU’s or SoC’s
• Reduced Power Modes
- Numerous power management modes
- Wake on LAN
- Magic packet wakeup
- Wakeup indicator event signal
- Link Status Change
2006-2017 Microchip Technology Inc.
• Single chip Ethernet controller
- Fully compliant with IEEE 802.3/802.3u standards
- Integrated Ethernet MAC and PHY
- 10BASE-T and 100BASE-TX support
- Full- and Half-duplex support
- Full-duplex flow control
- Backpressure for half-duplex flow control
- Preamble generation and removal
- Automatic 32-bit CRC generation and
checking
- Automatic payload padding and pad removal
- Loop-back modes
• Flexible address filtering modes
- One 48-bit perfect address
- 64 hash-filtered multicast addresses
- Pass all multicast
- Promiscuous mode
- Inverse filtering
- Pass all incoming with status report
- Disable reception of broadcast packets
• Integrated 10/100 Ethernet PHY
- Supports HP Auto-MDIX
- Auto-negotiation
- Supports energy-detect power down
• Host bus interface
- Simple, SRAM-like interface
- 16-bit data bus
- 16Kbyte FIFO with flexible TX/RX allocation
- One configurable host interrupt
• Miscellaneous features
- Small form factor, 56-pin QFN RoHS Compliant package
- Integrated 1.8V regulator
- Integrated checksum offload engine
- Mixed endian support
- General Purpose Timer
- Optional EEPROM interface
- Support for 3 status LEDs multiplexed with
Programmable GPIO signals
• Single 3.3V Power Supply with Variable Voltage
I/O
• Commercial and Industrial Temperature Support
DS00002416A-page 1
LAN9221/LAN9221i
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the
revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
DS00002416A-page 2
2006-2017 Microchip Technology Inc.
LAN9221/LAN9221i
Table of Contents
1.0 General Description ........................................................................................................................................................................ 4
2.0 Pin Description and Configuration .................................................................................................................................................. 8
3.0 Functional Description .................................................................................................................................................................. 15
4.0 Internal Ethernet PHY ................................................................................................................................................................... 56
5.0 Register Description ...................................................................................................................................................................... 65
6.0 Timing Diagrams ......................................................................................................................................................................... 113
7.0 Operational Characteristics ......................................................................................................................................................... 125
8.0 Package Information ................................................................................................................................................................... 134
Appendix A: Data Sheet Revision History ......................................................................................................................................... 136
2006-2017 Microchip Technology Inc.
DS00002416A-page 3
LAN9221/LAN9221i
1.0
GENERAL DESCRIPTION
The LAN9221/LAN9221i is a full-featured, single-chip 10/100 Ethernet controller designed for embedded applications
where performance, flexibility, ease of integration and system cost control are required. The LAN9221/LAN9221i has
been specifically designed to provide high performance and throughput for 16-bit applications. The LAN9221/LAN9221i
is fully IEEE 802.3 10BASE-T and 802.3u 100BASE-TX compliant, and supports HP Auto-MDIX. The variable voltage
I/O signals of the LAN9221/LAN9221i accommodate lower voltage I/O signalling without the need for voltage level shifters.
The LAN9221/LAN9221i includes an integrated Ethernet MAC and PHY with a high-performance SRAM-like slave interface. The simple, yet highly functional host bus interface provides a glue-less connection to most common 16-bit microprocessors and microcontrollers as well as 32-bit microprocessors with a 16-bit external bus. The integrated checksum
offload engines enable the automatic generation of the 16-bit checksum for received and transmitted Ethernet frames,
offloading the task from the CPU. The LAN9221/LAN9221i also includes large transmit and receive data FIFOs to
accommodate high latency applications. In addition, the LAN9221/LAN9221i memory buffer architecture allows highly
efficient use of memory resources by optimizing packet granularity.
Applications
The LAN9221/LAN9221i is well suited for many high-performance embedded applications, including:
•
•
•
•
•
•
•
•
Cable, satellite and IP set-top boxes
High-end audio distribution systems
Digital video recorders
DVD Recorders/Players
Digital TV
Digital media clients/servers
Home gateways
Industrial and embedded systems with extended temperature support
The LAN9221/LAN9221i also supports features which reduce or eliminate packet loss. Its internal 16-KByte SRAM can
hold over 200 received packets. If the receive FIFO gets too full, the LAN9221/LAN9221i can automatically generate
flow control packets to the remote node, or assert back-pressure on the remote node by generating network collisions.
The LAN9221/LAN9221i supports numerous power management and wakeup features. The LAN9221/LAN9221i can
be placed in a reduced power mode and can be programmed to issue an external wake signal via several methods,
including “Magic Packet”, “Wake on LAN” and “Link Status Change”. This signal is ideal for triggering system power-up
using remote Ethernet wakeup events. The device can be removed from the low power state via a host processor command.
DS00002416A-page 4
2006-2017 Microchip Technology Inc.
LAN9221/LAN9221i
1.1
Block Diagram
FIGURE 1-1:
SYSTEM BLOCK DIAGRAM
System Memory
System
Peripherals
Magnetics
Microprocessor/
Microcontroller
System Bus
LAN9221/
LAN9221i
25MHz
XTAL
Ethernet
LEDS/
GPIO
EEPROM
(Optional)
The Microchip LAN9221/LAN9221i integrated 10/100 MAC/PHY controller is a peripheral chip that performs the function
of translating parallel data from a host controller into Ethernet packets. The LAN9221/LAN9221i Ethernet MAC/PHY
controller is designed and optimized to function in an embedded environment. All communication is performed with programmed I/O transactions using the simple SRAM-like host interface bus.
The diagram shown above, describes a typical system configuration of the LAN9221/LAN9221i in a typical embedded
environment.
The LAN9221/LAN9221i is a general purpose, platform independent, Ethernet controller. The LAN9221/LAN9221i consists of four major functional blocks. The four blocks are:
•
•
•
•
10/100 Ethernet PHY
10/100 Ethernet MAC
RX/TX FIFOs
Host Bus Interface (HBI)
2006-2017 Microchip Technology Inc.
DS00002416A-page 5
LAN9221/LAN9221i
1.2
Internal Block Overview
This section provides an overview of each of these functional blocks as shown in Figure 1-2, "Internal Block Diagram".
FIGURE 1-2:
INTERNAL BLOCK DIAGRAM
25MHz
EEPROM
(Optional )
+3.3V
PME
Wakup Indicator
Power
Management
Host Bus Interface
(HBI)
16-bit SRAM I/F
3.3V to 1.8V
Core Regulator
2kB to 14kB
Configurable TX FIFO
TX Status FIFO
PIO
Controller
RX Status FIFO
IRQ
FIFO _SEL
Interrupt
Controller
GP Timer
1.3
2kB to 14kB
Configurable RX FIFO
EEPROM
Controller
PLL
RX Checksum
Offload Engine
TX Checksum
Offload Engine
10/100
Ethernet
MAC
10/100
Ethernet
PHY
LAN
MIL - RX Elastic
Buffer - 128 bytes
MIL - TX Elastic
Buffer - 2K bytes
10/100 Ethernet PHY
The LAN9221/LAN9221i integrates an IEEE 802.3 physical layer for twisted pair Ethernet applications. The PHY can
be configured for either 100 Mbps (100BASE-TX) or 10 Mbps (10BASE-T) Ethernet operation in either full or half duplex
configurations. The PHY block supports HP Auto-MDIX and auto-negotiation.
Minimal external components are required for the utilization of the Integrated PHY.
1.4
10/100 Ethernet MAC
The transmit and receive data paths are separate within the MAC allowing the highest performance especially in full
duplex mode. The data paths connect to the PIO interface Function via separate busses to increase performance. Payload data as well as transmit and receive status is passed on these busses.
A third internal bus is used to access the MAC’s Control and Status Registers (CSR’s). This bus is accessible from the
host through the PIO interface function.
On the backend, the MAC interfaces with the internal 10/100 PHY through a MII (Media Independent Interface) port
internal to the LAN9221/LAN9221i. The MAC CSR's also provide a mechanism for accessing the PHY’s internal registers through the internal SMI (Serial Management Interface) bus.
The MAC Interface Layer (MIL), within the MAC, contains a 2K Byte transmit and a 128 Byte receive FIFO which is separate from the TX and RX FIFOs. The FIFOs within the MAC are not directly accessible from the host interface. The
differentiation between the TX/RX FIFO memory buffers and the MAC buffers is that when the transmit or receive packets are in the MAC buffers, the host no longer can control or access the TX or RX data. The MAC buffers (both TX and
RX) are in effect the working buffers of the Ethernet MAC logic. In the case of reception, the data must be moved first
to the RX FIFOs for the host to access the data. For TX operations, the MIL operates in store-and-forward mode and
will queue an entire frame before beginning transmission.
DS00002416A-page 6
2006-2017 Microchip Technology Inc.
LAN9221/LAN9221i
1.5
Receive and Transmit FIFOs
The Receive and Transmit FIFOs allow increased packet buffer storage to the MAC. The FIFOs are a conduit between
the host interface and the MAC through which all transmitted and received data and status information is passed. Deep
FIFOs allow a high degree of latency tolerance relative to the various transport and OS software stacks thus reducing
or minimizing overrun conditions. Like the MAC, the FIFOs have separate receive and transmit data paths. In addition,
the RX and TX FIFOs are configurable in size, allowing increased flexibility.
1.6
Interrupt Controller
The LAN9221/LAN9221i supports a single programmable interrupt. The programmable nature of this interrupt allows
the user the ability to optimize performance dependent upon the application requirement. Both the polarity and buffer
type of the interrupt pin are configurable for the external interrupt processing. The interrupt line can be configured as an
open-drain output to facilitate the sharing of interrupts with other devices. In addition, a programmable interrupt deassertion interval is provided.
1.7
GPIO Interface
A 3-bit GPIO and 2-bit GPO (Multiplexed on the EEPROM and LED Pins) interface is included in the
LAN9221/LAN9221i. It is accessible through the host bus interface via the CSRs. The GPIO signals can function as
inputs, push-pull outputs and open drain outputs. The GPIO’s (GPO’s are not configurable) can also be configured to
trigger interrupts with programmable polarity.
1.8
Serial EEPROM Interface
A serial EEPROM interface is included in the LAN9221/LAN9221i. The serial EEPROM is optional and can be programmed with the LAN9221/LAN9221i MAC address. The LAN9221/LAN9221i can optionally load the MAC address
automatically after hardware reset, or soft reset.
1.9
Power Management Controls
The LAN9221/LAN9221i supports comprehensive array of power management modes to allow use in power sensitive
applications. Wake on LAN, Link Status Change and Magic Packet detection are supported by the LAN9221/LAN9221i.
An external PME (Power Management Event) interrupt is provided to indicate detection of a wakeup event.
1.10
General Purpose Timer
The general-purpose timer has no dedicated function within the LAN9221/LAN9221i and may be programmed to issue
a timed interrupt.
1.11
Host Bus Interface (SRAM Interface)
The host bus interface provides a FIFO interface for the transmit and receive data paths, as well as an interface for the
LAN9221/LAN9221i Control and Status Registers (CSR’s).
The host bus interface is the primary bus for connection to the embedded host system. This interface models an asynchronous SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface. Programmed I/O transactions are
supported.
The LAN9221/LAN9221i host bus interface supports 16-bit bus transfers. Internally, all data paths are 32-bits wide. The
LAN9221/LAN9221i can be interfaced to either Big-Endian or Little-Endian processors and includes mixed endian support for FIFO accesses.
2006-2017 Microchip Technology Inc.
DS00002416A-page 7
LAN9221/LAN9221i
PIN DESCRIPTION AND CONFIGURATION
PME
EECLK/GPO4**
EECS
EEDIO/GPO3**
VDD18CORE
D0
D1
D2
D3
D4
D5
VDDVARIO
D6
41
40
39
38
37
36
35
34
33
32
31
30
29
56-QFN PIN CONFIGURATION (TOP VIEW)
nRESET
FIGURE 2-1:
42
2.0
IRQ
43
28
D7
TPO-
44
27
D8
TPO+
45
26
D9
VDD33A
46
LAN9221/LAN9221i
25
D10
TPI-
47
56-QFN
24
VDDVARIO
TPI+
48
(TOP VIEW)
23
D11
VDD33A
49
22
D12
VSS
14
nRD
TEST
15
13
56
FIFO_SEL
VDDVARIO
12
nWR
A1
16
11
55
A2
XTAL1/CLKIN**
10
nCS
A3
17
9
54
A4
XTAL2
8
VDDVARIO
A5
18
7
53
A6
VDD18A
6
D15
A7
19
5
52
GPIO2/nLED3**
AMDIX_EN
4
D14
GPIO1/nLED2**
20
3
51
GPIO0/nLED1**
VDD33A
2
D13
VDD18CORE
21
1
50
VDD33REG
EXRES
**DENOTES A MULTIFUNCTION PIN
NOTE: When HP Auto-MDIX is activated , the TPO+/- pins can function as TPI +/- and vice-versa
NOTE: Exposed pad (VSS) on bottom of package must be connected to ground
DS00002416A-page 8
2006-2017 Microchip Technology Inc.
LAN9221/LAN9221i
2.1
Pin List
TABLE 2-1:
HOST BUS INTERFACE SIGNALS
Name
Symbol
Buffer
Type
#
Pins
Host Data
D[15:0]
VIS/VO8
16
Bi-directional data port.
Host Address
A[7:1]
VIS
7
7-bit Address Port. Used to select Internal CSR’s and
TX and RX FIFOs.
Read Strobe
nRD
VIS
1
Active low strobe to indicate a read cycle.
Write Strobe
nWR
VIS
1
Active low strobe to indicate a write cycle. This signal,
qualified with nCS, is also used to wakeup the
LAN9221/LAN9221i when it is in a reduced power
state.
Chip Select
nCS
VIS
1
Active low signal used to qualify read and write
operations. This signal qualified with nWR is also used
to wakeup the LAN9221/LAN9221i when it is in a
reduced power state.
Interrupt
Request
IRQ
VO8/
VOD8
1
Programmable Interrupt request. Programmable
polarity, source and buffer types.
FIFO Select
FIFO_SEL
VIS
1
When driven high all accesses to the
LAN9221/LAN9221i are to the RX or TX Data FIFOs.
In this mode, the A[7:3] upper address inputs are
ignored.
TABLE 2-2:
Description
LAN INTERFACE SIGNALS
Name
Symbol
Buffer
Type
# Pins
TPO+
TPO+
AO
1
Transmit Positive Output (normal)
Receive Positive Input (reversed)
TPO-
TPO-
AO
1
Transmit Negative Output (normal)
Receive Negative Input (reversed)
TPI+
TPI+
AI
1
Receive Positive Input (normal)
Transmit Positive Input (reversed)
TPI-
TPI-
AI
1
Receive Negative Input (normal)
Transmit Negative Output (reversed)
PHY External Bias
Resistor
EXRES
AI
1
Must be connected to ground through a 12.4K
ohm 1% resistor.
Note:
Description
The pin names for the twisted pair pins shown above apply to a normal connection. If HP Auto-MDIX is
enabled and a reverse connection is detected, or a reverse connection is manually selected, the input pins
become outputs, and vice-versa, as indicated in the descriptions.
2006-2017 Microchip Technology Inc.
DS00002416A-page 9
LAN9221/LAN9221i
TABLE 2-3:
SERIAL EEPROM INTERFACE SIGNALS
Name
Symbol
EEPROM Data,
GPO3, TX_EN,
TX_CLK
EEDIO/GPO3/
TX_EN/TX_CLK
Buffer
Type
# Pins
Description
VIS/VO8
1
EEPROM Data: This bi-directional pin can be
connected to a serial EEPROM DIO. This is
optional.
General Purpose Output 3: This pin can also
function as a general purpose output, or it can
be configured to monitor the TX_EN or
TX_CLK signals on the internal MII port. When
configured as a GPO signal, or as a
TX_EN/TX_CLK monitor, the EECS pin is
deasserted so as to never unintentionally
access the serial EEPROM. This signal cannot
function as a general-purpose input.
EEPROM Chip
Select
EECS
VO8
1
Serial EEPROM chip select.
EEPROM Clock,
GPO4 RX_DV,
RX_CLK
EECLK/GPO4/
RX_DV/RX_CLK
VO8
(PU)
1
EEPROM Clock: Serial EEPROM Clock pin.
DS00002416A-page 10
General Purpose Output 4: This pin can also
function as a general-purpose output, or it can
be configured to monitor the RX_DV or
RX_CLK signals on the internal MII port. When
configured as a GPO signal, or as an
RX_DV/RX_CLK monitor, the EECS pin is
deasserted so as to never unintentionally
access the serial EEPROM. This signal cannot
function as a general-purpose input.
Note:
When the EEPROM interface is not
used, the EECLK pin must be left
unconnected.
Note:
When
operating
at
reduced
VDDVARIO voltage levels (less
than 3.0V), this pin must be pulledup with an external resistor. Refer to
Section 2.2, "External Pull-Up/PullDown Resistors" for more information.
Note:
This pin must not be pulled low by
an external resistor or driven low
externally under any conditions.
2006-2017 Microchip Technology Inc.
LAN9221/LAN9221i
TABLE 2-4:
SYSTEM AND POWER SIGNALS
Name
Symbol
Buffer
Type
# Pins
Description
Crystal 1, Clock In
XTAL1/CLKIN
lCLK
1
External 25MHz Crystal Input. This pin can also
be connected to single-ended TTL oscillator
(CLKIN). If this method is implemented, XTAL2
should be left unconnected.
Crystal 2
XTAL2
OCLK
1
External 25MHz Crystal output.
Reset
nRESET
VIS
(PU)
1
Active-low reset input. Resets all logic and
registers within the LAN9221/LAN9221i. This
signal is pulled high with a weak internal pull-up
resistor.
Note:
The LAN9221/LAN9221i must be
reset on power-up via nRESET or
following power-up via a soft reset
(SRST). The LAN9221/LAN9221i
must always be read at least once
after reset, or upon return from a
power-saving state or write operations will not function. See Section
3.11, "Detailed Reset Description,"
on page 39 for additional information
Note:
Wakeup Indicator
PME
2006-2017 Microchip Technology Inc.
VO8/
VOD8
1
When
operating
at
reduced
VDDVARIO voltage levels (less than
3.0V), this pin must be pulled-high to
a valid level with an external resistor
or must be driven as an input. Refer
to Section 2.2, "External PullUp/Pull-Down Resistors" for more
information.
When programmed to do so, is asserted when
the LAN9221/LAN9221i detects a wake event
and is requesting the system to wake up from
the associated sleep state. The polarity and
buffer type of this signal is programmable.
Note:
Detection of a Power Management
Event, and assertion of the PME signal
will
not
wakeup
the
LAN9221/LAN9221i.
The
LAN9221/LAN9221i will only wake
up when it detects a host write cycle
(assertion of nCS and nWR).
Although
any
write
to
the
LAN9221/LAN9221i, regardless of
the data written, will wake-up the
device when it is in a power-saving
mode, it is required that the
BYTE_TEST register be used for
this purpose.
DS00002416A-page 11
LAN9221/LAN9221i
TABLE 2-4:
SYSTEM AND POWER SIGNALS (CONTINUED)
Name
Symbol
Auto-MDIX Enable
AMDIX_EN
Test
General Purpose
I/O data,
nLED1 (Speed
Indicator),
nLED2 (Link &
Activity Indicator),
Buffer
Type
# Pins
Description
VIS
(PU)
1
Enables Auto-MDIX. Pull high or leave
unconnected to enable Auto-MDIX, pull low to
disable Auto-MDIX.
Note:
When
operating
at
reduced
VDDVARIO voltage levels (less than
3.0V), this pin must be pulled to a
valid level with an external resistor.
Refer to Section 2.2, "External PullUp/Pull-Down Resistors" for more
information.
TEST
VIS
(PD)
1
Reserved for internal test purposes only.
Note:
When operating at a reduced
VDDVARIO voltage (less than 3.0V),
this pin must be connected to ground
or pulled-low with an external resistor. When VDDVARIO = 3.3V, this
pin may be left unconnected. Refer
to Section 2.2, "External PullUp/Pull-Down Resistors" for more
information.
GPIO[2:0]/
nLED[3:1]
VIS/
VO12/
VOD12
3
General Purpose I/O data: These three
general-purpose signals are fully programmable
as either push-pull output, open-drain output or
input by writing the GPIO_CFG configuration
register in the CSR’s. They are also multiplexed
as GP LED connections.
GPIO signals are Schmitt-triggered inputs.
When configured as LED outputs these signals
are open-drain.
nLED3 (FullDuplex
Indicator).
nLED1 (Speed Indicator). This signal is driven
low when the operating speed is 100Mb. During
auto-negotiation, when the cable is
disconnected, and during 10Mbs operation, this
signal is driven high.
nLED2 (Link & Activity Indicator). This signal
is driven low (LED on) when the
LAN9221/LAN9221i detects a valid link. This
signal is pulsed high (LED off) for 80mS
whenever transmit or receive activity is
detected. This signal is then driven low again
for a minimum of 80mS, after which time it will
repeat the process if TX or RX activity is
detected. Effectively, LED2 is activated solid for
a link. When transmit or receive activity is
sensed LED2 will flash as an activity indicator.
nLED3 (Full-Duplex Indicator). This signal is
driven low when the link is operating in fullduplex mode.
Variable Voltage
I/O Power
VDDVARIO
P
4
Common Ground
VSS
P
1 pad
DS00002416A-page 12
Variable Voltage I/O logic power supply pins.
Refer to Section 7.2, "Operating Conditions**,"
on page 125 for additional details.
Common Ground
2006-2017 Microchip Technology Inc.
LAN9221/LAN9221i
TABLE 2-4:
SYSTEM AND POWER SIGNALS (CONTINUED)
Name
Symbol
Buffer
Type
# Pins
Description
+3.3V Regulator
Power Supply
VDD33REG
P
1
+3.3V power supply for internal +1.8V regulator.
+3.3V Analog
Power
VDD33A
P
3
+3.3V analog power supply pins.
+1.8V Analog
Power
VDD18A
P
1
+1.8V analog power supply pin. This pin must
be connected externally to VDD18CORE.
Core Voltage
Decoupling
VDD18CORE
P
2
+1.8 V from internal core regulator. Both pins
must be connected together externally. Each
pin requires a 0.01uF decoupling capacitor. In
addition, pin 2 requires a bulk 4.7uF capacitor
(
工商网监
湘ICP备2023018690号
