MAX3671ETN2T

19-4437; Rev 0; 2/09 KIT ATION EVALU E L B A AVAIL Low-Jitter Frequency Synthesizer with Selectable Input Reference Features ♦ Two Reference Clock Inputs: LVPECL ♦ Nine Phase-Aligned Clock Outputs: LVPECL ♦ Input Frequencies: 62.5MHz,125MHz, 250MHz, 312.5MHz ♦ Output Frequencies: 62.5MHz, 125MHz, 156.25MHz, 250MHz, 312.5MHz The MAX3671 is a low-jitter frequency synthesizer that accepts two reference clock inputs and generates nine phase-aligned outputs. The device features 40kHz jitter transfer bandwidth, 0.3psRMS (12kHz to 20MHz) integrated phase jitter, and best-in-class power-supply noise rejection (PSNR), making it ideal for jitter cleanup, frequency translation, and clock distribution in Gigabit Ethernet applications. The MAX3671 operates from a single +3.3V supply and typically consumes 400mW. The IC is available in an 8mm x 8mm, 56-pin TQFN package, and operates from -40°C to +85°C. ♦ Low-Jitter Generation: 0.3psRMS (12kHz to 20MHz) ♦ Clock Failure Indicator for Both Reference Clocks ♦ External Feedback Provides Zero-Delay Capability ♦ Low Output Skew: 20ps Typical Applications Ordering Information Gigabit Ethernet Routers and Switches PART TEMP RANGE PIN-PACKAGE Jitter Cleanup MAX3671ETN+ -40°C to +85°C 56 TQFN-EP* Clock Distribution +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Frequency Translation Pin Configuration and Typical Application Circuits appear at end of data sheet. Functional Diagram SEL_CLK CPLL 0.1μF DM CREG 0.22μF DA REFCLK0 0 REFCLK0 DIV M REFCLK1 1 REFCLK1 PFD CP VCO 62.5MHz DIV A PLL_BYPASS OUTA_EN 1 OUTA3 0 OUTA3 OUTA2 2.5GHz OUTA2 OUTA1 IN0FAIL IN1FAIL OUTA1 SIGNAL QUALIFIER AND LOCK DETECT OUTA0 OUTA0 LOCK DIV N MR OUTB_EN POWER-ON RESET (POR) DIV B 1 OUTB4 0 OUTB4 OUTB3 OUTB3 OUTB2 1 OUTB2 0 OUTB1 MAX3671 OUTB1 OUTB0 OUTB0 FB_SEL FB_IN FB_IN DB ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3671 General Description MAX3671 Low-Jitter Frequency Synthesizer with Selectable Input Reference ABSOLUTE MAXIMUM RATINGS Supply Voltage Range (VCC, VCC_VCO)..............-0.3V to +4.0V LVPECL Output Current (OUTA[3:0], OUTA[3 : 0], OUTB[4:0], OUTB[4 : 0]) .............................-56mA All Other Pins..............................................-0.3V to (VCC + 0.3V) Continuous Power Dissipation (TA = +70°C) 56-Pin TQFN (derate 47.6mW/°C above 70°C)..........3808mW Operating Junction Temperature (TJ)................-55°C to +150°C Storage Temperature Range .............................-65°C to +160°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, TA = -40°C to +85°C, CPLL = 0.1µF, CREG = 0.22µF. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) PARAMETER TYP MAX UNITS LVPECL outputs unterminated 120 175 mA VCC Rising (Note 1) 2.55 V VCC Falling (Note 1) 2.45 V Supply Current SYMBOL ICC CONDITIONS MIN POWER-ON RESET LVCMOS/LVTTL INPUTS (MR, SEL_CLK, PLL_BYPASS, FB_SEL) Input High Voltage VIH Input Low Voltage VIL 2.0 Input High Current I IH VIN = VCC Input Low Current I IL VIN = GND V 0.8 V 75 μA -75 μA 2.4 V LVCMOS/LVTTL OUTPUTS (IN0FAIL, IN1FAIL, LOCK) Output High Voltage VOH I OH = -8mA Output Low Voltage VOL I OL = +8mA 0.4 V VCC 0.7 V LVPECL INPUTS (REFCLK0, REFCLK0, REFCLK1, REFCLK1, FB_IN, FB_IN) (Note 2) Input High Voltage VIH Input Low Voltage VIL VCC 2.0 Input Bias Voltage VCMI VCC 1.8 Differential-Input Swing V VCC 1.34 0.15 V 1.9 VP-P Differential-Input Impedance > 40 k
Common-Mode Input Impedance > 14 k
1.5 pF Input Capacitance Input Current Input Inrush Current When Power is Off (Steady State) Input Inrush Current Overshoot When Power is Off 2 VIH = VCC - 0.7V, VIL = VCC - 2.0V -100 +100 μA (Notes 3, 4) 8 mA IOVERSHOOT (Notes 3, 4) 6 mA IDC _______________________________________________________________________________________ Low-Jitter Frequency Synthesizer with Selectable Input Reference (VCC = +3.0V to +3.6V, TA = -40°C to +85°C, CPLL = 0.1µF, CREG = 0.22µF. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS REFERENCE CLOCK INPUTS (REFCLK0, REFCLK0, REFCLK1, REFCLK1) Reference Clock Frequency fREF Table 1 MHz Reference Clock Frequency Tolerance -200 +200 ppm Reference Clock Duty Cycle 40 60 % Reference Clock Amplitude Detection Assert Threshold VDT Differential swing (Notes 5, 6) 200 mVP-P LVPECL OUTPUTS (OUTA[3:0], OUTA[3:0], OUTB[4:0], OUTB[4:0]) (Note 7) Output High Voltage VOH VCC 1.13 VCC 0.98 VCC 0.83 V Output Low Voltage VOL VCC 1.85 VCC 1.70 VCC 1.55 V 1.1 1.45 1.8 VP-P 130 μA Differential-Output Swing Output Current When Disabled VO = VCC - 2.0V to VCC - 0.7V Output Frequency f OUT Output Rise/Fall Time tR, tF Output Duty Cycle Output-to-Output Skew t SKEW Tables 2, 3 20% to 80% (Note 8) 150 MHz 500 PLL_BYPASS = 0 48 52 PLL_BYPASS = 1 (Note 9) 45 55 Within output bank 20 All outputs 40 ps % ps OTHER AC ELECTRICAL SPECIFICATIONS PLL Jitter Transfer Bandwidth 40 Jitter Peaking 0.1 dB PFD Compare Frequency 62.5 MHz VCO Center Frequency kHz 2.5 Random Jitter Generation Integrated 12kHz to 20MHz (Notes 5, 8) Determinisitic Jitter Caused by Power-Supply Noise (Note 10) 0.3 GHz 1.0 psRMS 5 psP-P Frequency Difference Between Reference Clock and VCO Within Which the PLL is Considered in Lock 500 ppm Frequency Difference Between Reference Clock and VCO at Which the PLL is Considered Out-of-Lock 800 ppm 600 μs PLL Lock Time tLOCK Figure 2 _______________________________________________________________________________________ 3 MAX3671 ELECTRICAL CHARACTERISTICS (continued) MAX3671 Low-Jitter Frequency Synthesizer with Selectable Input Reference ELECTRICAL CHARACTERISTICS (continued) (VCC = +3.0V to +3.6V, TA = -40°C to +85°C, CPLL = 0.1µF, CREG = 0.22µF. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN Master Reset (MR) Minimum Pulse Width TYP MAX 100 Propagation Delay from Input to FB_IN FB_SEL = 1 (Notes 8, 11) Propagation Delay from Input to Any Output PLL_BYPASS = 1 -120 ns +120 1.0 UNITS ps ns During the power-on-reset time, the LVPECL outputs are held to logic-low (OUTxx = low, OUTxx = high). See the PowerOn-Reset (POR) section for more information. Note 2: LVPECL inputs can be AC- or DC-coupled. Note 3: For hot-pluggable purposes, the device can receive LVPECL inputs when no supply voltage is applied. Measured with VCC pins connected to GND. See Figure 1. Note 4: Measured with LVPECL input (VIH, VIL) as specified. Note 5: Measured using reference clock input with 550ps rise/fall time (20% to 80%). Note 6: When input differential swing is below the specified threshold, a clock failure is declared. See Figure 4. Note 7: LVPECL outputs terminated 50Ω to VTT = VCC - 2V. Note 8: Guaranteed by design and characterization. Note 9: Measured with 50% duty cycle at reference clock input. Note 10: Measured with 50mVP-P sinusoidal noise on the power supply, fNOISE = 100kHz. Note 11: Measured with fREFCLKx = fFB_IN and matched slew rates. Note 1: 4 _______________________________________________________________________________________ Low-Jitter Frequency Synthesizer with Selectable Input Reference MAX3671 INRUSH CURRENT (mA) IOVERSHOOT IDC t Figure 1. LVPECL Input Inrush Current POWER-ON-RESET (~ 20μs) VCC REFCLK0 REFCLK1 OUTxx IN0FAIL IN1FAIL HIGH HIGH tLOCK (~ 600μs) LOCK SEL_CLK PLL LOCKED TO REFCLK0 LOW Figure 2. Power-Up, PLL Locks to REFCLK0 _______________________________________________________________________________________ 5 Typical Operating Characteristics (VCC = 3.3V, TA = +25°C, unless otherwise noted.) -90 -100 -110 -120 -130 -90 -100 -110 -120 -130 -80 -90 -100 -110 -120 -130 -140 -140 -140 -150 -150 -160 -160 10k 100k 1M 10M 100M 100 1k OFFSET FREQUENCY (Hz) 1M 10M 100 100M -90 -100 -110 -120 -130 -90 -110 -120 -130 -140 -150 -150 -160 RANDOM JITTER = 0.28psRMS INTEGRATED 12kHz TO 20MHz -100 -140 10k 100k 1M 10M 100M 100M 0 -5 -10 -15 -20 -30 1k 10k 100k 1M 10M 1k 100M 10k DIFFERENTIAL OUTPUT WAVEFORM AT 312.5MHz MAX3671 toc07 1M 100k JITTER FREQUENCY (Hz) OFFSET FREQUENCY (Hz) DIFFERENTIAL OUTPUT WAVEFORM AT 156.25MHz 10M -25 100 OFFSET FREQUENCY (Hz) 1M 5 -160 1k 100k JITTER TRANSFER -80 PHASE NOISE (dBc/Hz) -80 -70 10k OFFSET FREQUENCY (Hz) JITTER TRANSFER (dB) RANDOM JITTER = 0.27psRMS INTEGRATED 12kHz TO 20MHz 100 1k PHASE NOISE AT 312.5MHz -60 MAX3671 toc04 -70 100k OFFSET FREQUENCY (Hz) PHASE NOISE AT 250MHz -60 10k MAX3671 toc06 1k MAX3671 toc05 100 RANDOM JITTER = 0.28psRMS INTEGRATED 12kHz TO 20MHz -70 -150 -160 MAX3671 toc03 RANDOM JITTER = 0.29psRMS INTEGRATED 12kHz TO 20MHz -80 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) -80 -70 PHASE NOISE (dBc/Hz) RANDOM JITTER = 0.41psRMS INTEGRATED 12kHz TO 20MHz -60 REFERENCE CLOCK AMPLITUDE DETECTION ASSERT THRESHOLD vs. INPUT FREQUENCY MAX3671 toc08 300 MAX3671 toc09 MAX3671 toc01 -70 PHASE NOISE AT 156.25MHz PHASE NOISE AT 125MHz -60 MAX3671 toc02 PHASE NOISE AT 62.5MHz -60 PHASE NOISE (dBc/Hz) 280 200mV/div ASSERT THRESHOLD (mVP-P) MAX3671 Low-Jitter Frequency Synthesizer with Selectable Input Reference 200mV/div 260 INPUT RISE/FALL TIME = 550ps 240 220 200 180 INPUT RISE/FALL TIME = 270ps 160 140 120 100 800ps/div 400ps/div 50 100 150 200 250 300 350 REFERENCE CLOCK INPUT FREQUENCY (MHz) 6 _______________________________________________________________________________________ Low-Jitter Frequency Synthesizer with Selectable Input Reference JITTER HISTOGRAM WITH SUPPLY NOISE (SUPPLY NOISE = 50mVP-P, 100kHz) MAX3671 toc11 400 DJ = 5psP-P 350 300 250 ALL OUTPUTS ENABLED AND UNTERMINATED 200 fNOISE = 100kHz 35 DETERMINISTIC JITTER (psP-P) ALL OUTPUTS ENABLED AND TERMINATED 450 40 MAX3671 toc10 500 SUPPLY CURRENT (mA) DETERMINISTIC JITTER vs. POWER-SUPPLY NOISE AMPLITUDE 150 100 30 fNOISE = 200kHz 25 20 fNOISE = 1MHz 15 10 5 50 0 0 -40 -15 10 35 60 85 0 2ps/div SPUR POWER (dBc) -20 -30 -40 SUPPLY NOISE = 100mVP-P -50 -60 -70 -80 100 150 200 250 300 35 SUPPLY NOISE = 50mVP-P POWER-ON-RESET MAX3671 toc15 40 MAX3671 toc14 fOUT = 125MHz DETERMINISTIC JITTER vs. POWER-SUPPLY NOISE FREQUENCY DETERMINISTIC JITTER (psP-P) MAX3671 toc13 SPURS CAUSED BY POWER-SUPPLY NOISE vs. SUPPLY NOISE FREQUENCY -10 50 SUPPLY NOISE AMPLITUDE (mVP-P) TEMPERATURE (°C) 0 MAX3671 toc12 SUPPLY CURRENT vs. TEMPERATURE VCC 30 SUPPLY NOISE = 100mVP-P 25 OUTxx 20 15 SUPPLY NOISE = 50mVP-P 10 LOCK 5 -90 -100 0 10k 100k 10M 1M 10k SUPPLY NOISE FREQUENCY (Hz) 100k 10M 1M 200μs/div SUPPLY NOISE FREQUENCY (Hz) REFERENCE CLOCK FAILURE DETECTION MASTER RESET MAX3671 toc17 MAX3671 toc16 MR REFCLK1 OUTxx IN1FAIL LOCK LOCK 40μs/div 2ms/div _______________________________________________________________________________________ 7 MAX3671 Typical Operating Characteristics (continued) (VCC = 3.3V, TA = +25°C, unless otherwise noted.) Low-Jitter Frequency Synthesizer with Selectable Input Reference MAX3671 Pin Description PIN 8 NAME FUNCTION 1 IN0FAIL REFCLK0 Failure Indicator, LVCMOS/LVTTL Output. Low indicates REFCLK0 fails the clock qualification. Once a failed clock is detected, the indicator status is latched and updated every 128 PFD cycles (~ 2μs). 2 RSVD1 Reserved. Leave pin open. 3 4 5 6 RSVD2 REFCLK0 REFCLK0 DM Reserved. Connect to GND. 7, 22, 30, 41, 49, 52 VCC Power Supply. Connect to +3.3V. 8, 14, 23, 29, 42, 48, 53 GND Supply Ground Reference Clock Input 0, Differential LVPECL Four-Level Control Input for Reference Clock Input Divider. See Table 1. Master Reset, LVCMOS/LVTTL Input. Connect this pin high or leave open for normal operation. Has internal 90k
pullup to VCC. Connect low to reset the device. A reset is not required at power-up. If the output divider settings are changed on the fly, a reset is required to phase align the outputs. This input has a 100ns minimum pulse width and is asynchronous to the reference clock. While in reset, all clock outputs are held to logiclow. See Table 6. 9 MR 10 11 REFCLK1 REFCLK1 Reference Clock Input 1, Differential LVPECL 12 SEL_CLK Reference Clock Select, LVCMOS/LVTTL Input. Connect low or leave open to select REFCLK0 as the reference clock. Has internal 90k
pulldown to GND. Connect high to select REFCLK1 as the reference clock. 13 VCC_VCO Power Supply for VCO. Connect to +3.3V. 15 CPLL Connection for PLL Filter Capacitor. Connect a 0.1μF capacitor between this pin and GND. 16 CREG Connection for VCO Regulator Capacitor. Connect a 0.22μF capacitor between this pin and GND. 17 FB_SEL External Feedback Select, LVCMOS/LVTTL Input. Connect high to select external feedback for zero-delay buffer configuration. Connect low or leave open for internal feedback. Has internal 90k
pulldown to GND. 18 19 20 21 24 25 26 27 28 31 32 33 34 35 36 FB_IN FB_IN OUTB0 OUTB0 OUTB1 OUTB1 OUTB2 OUTB2 DB OUTB3 OUTB3 OUTB4 OUTB4 OUTB_EN OUTA_EN External Feedback Clock Input, Differential LVPECL. Used for zero-delay buffer configuration. Clock Output B0, Differential LVPECL Clock Output B1, Differential LVPECL Clock Output B2, Differential LVPECL Four-Level Control Input for B-Group Output Divider. See Table 3. Clock Output B3, Differential LVPECL Clock Output B4, Differential LVPECL Three-Level Control Input for B-Group Output Enable. See Table 5. Three-Level Control Input for A-Group Output Enable. See Table 4. _______________________________________________________________________________________ Low-Jitter Frequency Synthesizer with Selectable Input Reference PIN NAME 37 38 39 40 43 44 45 46 47 OUTA3 OUTA3 OUTA2 OUTA2 DA OUTA1 OUTA1 OUTA0 OUTA0 50 PLL_BYPASS FUNCTION Clock Output A3, Differential LVPECL Clock Output A2, Differential LVPECL Four-Level Control Input for A-Group Output Divider. See Table 2. Clock Output A1, Differential LVPECL Clock Output A0, Differential LVPECL PLL Bypass Control, LVCMOS/LVTTL Input. Connect low or open for normal operation. Has internal 90k
pulldown to GND. Connect high to bypass the PLL, connecting the selected reference clock directly to the clock outputs. In this mode, the clock qualification function is not valid. To reduce spurious jitter in bypass mode, the internal VCO should be disabled by shorting the CREG pin to GND. 51 RSVD3 Reserved. Connect to VCC. 54 RSVD4 Reserved. Leave pin open. 55 LOCK PLL Lock Indicator, LVCMOS/LVTTL Output. Low indicates PLL is locked. 56 IN1FAIL — EP REFCLK1 Failure Indicator, LVCMOS/LVTTL Output. Low indicates REFCLK1 fails the clock qualification. Once a failed clock is detected, the indicator status is latched and updated every 128 PFD cycles (~ 2μs). Exposed Pad. Connect to supply ground for proper electrical and thermal performance. Detailed Description The MAX3671 integrates two differential LVPECL reference inputs with a 2:1 mux, a PLL with configurable dividers, nine differential LVPECL clock outputs, and a selectable external feedback input for zero-delay buffer applications (see the Functional Diagram). The two reference clock inputs are continuously monitored for clock failure by the internal PLL and associated logic. If the primary clock fails, the user can switch over to the secondary clock using the 2:1 mux. The PLL accepts reference input frequencies of 62.5, 125, 250, or 312.5MHz and generates output frequencies of 62.5, 125, 156.25, 250, or 312.5MHz. The nine clock outputs are organized into two groups (A and B). Each group has a configurable frequency divider and output-enable control. Phase-Locked Loop (PLL) The PLL contains a phase-frequency detector (PFD), charge pump (CP) with a lowpass filter, and voltagecontrolled oscillator (VCO). The PFD compares the divided reference frequency to the divided VCO output at 62.5MHz, and generates a control signal to keep the VCO phase and frequency locked to the selected reference clock. Using a high-frequency VCO (2.5GHz) and low-loop bandwidth (40kHz), the MAX3671 attenuates reference clock jitter while maintaining lock and generates low-jitter clock outputs at multiple frequencies. Typical jitter generation is 0.3psRMS (integrated 12kHz to 20MHz). To minimize supply noise-induced jitter, the VCO supply (VCC_VCO) is isolated from the core logic and output buffer supplies. Additionally, the MAX3671 uses an internal low-dropout (LDO) regulator to attenuate noise from the power supply. This allows the device to achieve excellent power-supply noise rejection, significantly reducing the impact on jitter generation. Clock Failure Conditions The MAX3671 clock failure detection is performed using the combination of amplitude qualification and PLL frequency and phase-error qualification. The failure status is indicated for REFCLK0 and REFCLK1 at _______________________________________________________________________________________ 9 MAX3671 Pin Description (continued) MAX3671 Low-Jitter Frequency Synthesizer with Selectable Input Reference IN0FAIL and IN1FAIL, respectively. Once an indicator is asserted low, it is latched and updated every 128 PFD cycles (~ 2µs). It should be noted that when the PLL is locked to a reference clock, the clock failure indicator for the other reference clock is only valid for amplitude qualification and frequency qualification. BOTH INPUTS OPEN VCC 130Ω VCC 130Ω Amplitude Qualification A reference clock input fails amplitude qualification if any of the following conditions occur: • Either one or both inputs (REFCLKx, REFCLKx) are shorted to VCC or GND. • Both inputs (REFCLKx, REFCLKx) are disconnected from the source and have 130Ω to VCC and 82Ω to GND at each input. See Figure 3. • Input reference clock differential swing is below the clock failure assert threshold as specified in the Electrical Characteristics. See Figure 4. The response time for these conditions is typically between 50ns and 300ns. MAX3671 LVPECL 82Ω 82Ω Figure 3. Positions for Open-Circuit Detection DIFFERENTIAL INPUT: (REFCLKx - REFCLKx) Phase Qualification A reference clock input fails phase qualification when the phase error at the PFD output exceeds the error window (0.75ns typical) for more than five of eight PFD cycles. A reference clock input is qualified when phase error at the PFD output is within the phase-error window for eight consecutive PFD cycles. Note that phase qualification only applies to the reference input currently being used by the PLL. Frequency Qualification A reference clock input becomes frequency qualified if the input frequency is within ±2.4% of the nominal frequency. The reference input becomes frequency disqualified if the input frequency moves away from the nominal frequency by more than ±8%. 10 0V VDT Figure 4. Input Amplitude Detection Threshold ______________________________________________________________________________________ Low-Jitter Frequency Synthesizer with Selectable Input Reference CONNECTION FROM DM PIN INPUT FREQUENCY (MHz) GND 62.5 VCC 125 Open 250 10k
to GND 312.5 If the frequency difference between the reference clock input and the VCO at the PFD input becomes within 500ppm, the PLL is considered to be in lock (LOCK = 0). When the frequency difference between the reference clock input and the VCO at the PFD input becomes greater than 800ppm, the PLL is considered out-of-lock. It should be noted that the LOCK indicator is not part of the frequency qualification used for the INxFAIL indicators. Table 2. Divider A Configuration for A-Group Output Frequencies Input and Output Frequencies CONNECTION FROM DA PIN OUTPUT FREQUENCY AT OUTA[3:0] (MHz) GND 62.5 VCC 125 Open 156.25 10k
to GND 312.5 The MAX3671 input and output dividers are configured using four-level control inputs DM, DA, and DB. Each divider is independent and can have a unique setting. The input connection and associated frequencies are listed in Tables 1, 2, and 3. Output-Enable Controls Each output group (A and B) has a three-level control input OUTA_EN and OUTB_EN. See Tables 4 and 5 for configuration settings. When clock outputs are disabled, they are high impedance. Unused enabled outputs should be left open. Table 3. Divider B Configuration for B-Group Output Frequencies CONNECTION FROM DB PIN OUTPUT FREQUENCY AT OUTB[4:0] (MHz) GND 62.5 VCC 125 Open 250 10k
to GND 312.5 Power-On-Reset (POR) At power-on, an internal signal is generated to hold the MAX3671 in a reset state. This internal reset time is about 20µs after VCC reaches 3.0V (Figure 2). During the POR time, the outputs are held to logic-low (OUTxx = low and OUTxx = high). See Table 6 for output signal status during POR. After this internal reset time, the PLL starts to lock to the reference clock selected by SEL_CLK. Table 4. OUTA[3:0] Enable Control CONNECTION FROM OUTA_EN PIN A-GROUP OUTPUT ENABLED A-GROUP OUTPUT DISABLED TO HIGH IMPEDANCE GND OUTA0, OUTA1, OUTA2, OUTA3 — VCC* — OUTA0, OUTA1, OUTA2, OUTA3 Open OUTA0, OUTA1 OUTA2, OUTA3 *Connecting both OUTA_EN and OUTB_EN to VCC enables a factory test mode and forces all indicators to GND. This is not a valid mode of operation. Table 5. OUTB[4:0] Enable Control B-GROUP OUTPUT DISABLED TO HIGH IMPEDANCE CONNECTION FROM OUTB_EN PIN B-GROUP OUTPUT ENABLED GND OUTB0, OUTB1, OUTB2, OUTB3, OUTB4 — VCC* OUTB0 OUTB1, OUTB2, OUTB3, OUTB4 Open OUTB0, OUTB1, OUTB2 OUTB3, OUTB4 *Connecting both OUTA_EN and OUTB_EN to VCC enables a factory test mode and forces all indicators to GND. This is not a valid mode of operation. ______________________________________________________________________________________ 11 MAX3671 PLL Out-of-Lock Condition Table 1. Divider M Configuration for Input Frequencies MAX3671 Low-Jitter Frequency Synthesizer with Selectable Input Reference Master Reset After power-up, an external master reset (MR) can be provided to reset the internal dividers. This input requires a minimum reset pulse width of 100ns (active low) and is asynchronous to the reference clock. While MR is low, all clock outputs are held to logic-low (OUTxx = low, OUTxx = high). See Table 6 for the output signal status during master reset. When the master reset input is deasserted (MR = 1), the PLL starts to lock to the reference clock selected by SEL_CLK. Master reset is only needed for applications where divider configurations are changed on the fly and the clock outputs need to maintain phase alignment. A master reset is not required at power-up. External Feedback for Zero-Delay Buffer The MAX3671 can be operated with either internal or external PLL feedback path, controlled by the FB_SEL input. Connecting FB_SEL to GND selects internal feedback. For applications where a known phase relationship between the reference clock input and the external feedback input (FB_IN, FB_IN) are needed for phase synchronization, connect FB_SEL to VCC for zero-delay buffer configuration and provide external feedback to the FB_IN input. PLL Bypass Mode PLL bypass mode is provided for test purposes. In PLL bypass mode (PLL_BYPASS = 1), the selected reference clock is connected to the LVPECL clock outputs directly. The output clock frequency is the same as the input clock frequency and the clock qualification function is not valid. To reduce spurious jitter in bypass mode, the internal VCO should be disabled by shorting the CREG pin to GND. Applications Information Interfacing with LVPECL Inputs Figure 5 shows the equivalent LVPECL input circuit for REFCLK0, REFCLK1, and FB_IN. These inputs are internally biased to allow AC- or DC-coupling and have > 40kΩ differential input impedance. When AC-coupled, these inputs can accept LVDS, CML, and LVPECL signals. Unused reference clock inputs should be left open. Interfacing with LVPECL Outputs Figure 6 shows the equivalent LVPECL output circuit. These outputs are designed to drive a pair of 50Ω transmission lines terminated with 50Ω to VTT = VCC 2V. If a separate termination voltage (VTT) is not available, other termination methods can be used such as those shown in Figures 7 and 8. Unused outputs, enabled or disabled, can be left open or properly terminated. For more information on LVPECL terminations and how to interface with other logic families, refer to Application Note 291: HFAN-01.0: Introduction to LVDS, PECL, and CML. Layout Considerations The clock inputs and outputs are critical paths for the MAX3671, and care should be taken to minimize discontinuities on the transmission lines. Maintain 100Ω differential (or 50Ω single-ended) impedance in and out of the MAX3671. Avoid using vias and sharp corners. Termination networks should be placed as close as possible to receiving clock inputs. Provide space between differential output pairs to reduce crosstalk, especially if the A and B group outputs are operating at different frequencies. Table 6. Output Signal Status During Power-On-Reset or Master Reset OUTPUT 12 DURING POWER-ON-RESET (FOR ~ 20μs AFTER VCC > 3.0V) DURING MASTER RESET (MR = 0) NOTES IN0FAIL 1 Forced high regardless of reference input qualification. IN1FAIL 1 Forced high regardless of reference input qualification. PLL out-of-lock. LOCK 1 OUTA[3:0] Logic-Low — OUTB[4:0] Logic-Low — ______________________________________________________________________________________ Low-Jitter Frequency Synthesizer with Selectable Input Reference The 56-pin TQFN package features an exposed pad (EP), which provides a low-resistance thermal path for heat removal from the IC and must be connected to the circuit board ground plane for proper operation. VCC VCC VCC - 1.34V > 20kΩ > 20kΩ 200Ω REFCLKx, FB_IN 200Ω REFCLKx, FB_IN MAX3671 ESD STRUCTURES Figure 5. Equivalent LVPECL Input Circuit +3.3V VCC +3.3V 130Ω +3.3V +3.3V 130Ω Z = 50Ω LVPECL OUTxx LVPECL Z = 50Ω 82Ω 82Ω OUTxx ESD STRUCTURES Figure 7. Thevenin Equivalent LVPECL Termination MAX3671 Figure 6. Equivalent LVPECL Output Circuit ______________________________________________________________________________________ 13 MAX3671 Power Supply and Ground Connections The MAX3671 has seven supply connection pins; installation of a bypass capacitor at each supply pin is recommended. All seven supply connections should be driven from the same source to eliminate the possibility of independent power-supply sequencing. Excessive supply noise can result in increased jitter. MAX3671 Low-Jitter Frequency Synthesizer with Selectable Input Reference +3.3V +3.3V 0.1μF Z = 50Ω 50Ω LVPECL LVPECL 0.1μF 50Ω 0.1μF Z = 50Ω 150Ω 150Ω Figure 8. AC-Coupled LVPECL Termination OUTA1 DA OUTA1 OUTA0 OUTA0 GND PLL_BYPASS VCC RSVD3 VCC RSVD4 GND LOCK TOP VIEW IN1FAIL Pin Configuration 56 55 54 53 52 51 50 49 48 47 46 45 44 43 IN0FAIL 1 42 GND RSVD1 2 41 VCC RSVD2 3 40 OUTA2 REFCLK0 4 39 OUTA2 REFCLK0 5 38 OUTA3 DM 6 37 OUTA3 VCC 7 36 OUTA_EN MAX3671 GND 8 35 OUTB_EN MR 9 34 OUTB4 REFCLK1 10 33 OUTB4 REFCLK1 11 32 OUTB3 SEL_CLK 12 31 OUTB3 EP* VCC_VCO 13 30 VCC GND 14 29 GND DB OUTB2 OUTB2 OUTB1 GND OUTB1 VCC OUTB0 FB_IN OUTB0 FB_IN FB_SEL CPLL CREG 15 16 17 18 19 20 21 22 23 24 25 26 27 28 THIN QFN (8mm × 8mm × 0.8mm) *THE EXPOSED PAD OF THE TQFN PACKAGE MUST BE SOLDERED TO GROUND FOR PROPER THERMAL AND ELECTRICAL OPERATION. 14 ______________________________________________________________________________________ Low-Jitter Frequency Synthesizer with Selectable Input Reference +3.3V Z = 50Ω VCC REFCLK0 VCC_VCO 0.1μF 0.22μF CREG CPLL 0.1μF 0.1μF 0.1μF 156.25MHz Z = 50Ω OUTA3 50Ω 62.5MHz BACKPLANE REFERENCE CLOCK 50Ω 0.1μF 0.1μF 50Ω 0.1μF 50Ω 0.1μF Z = 50Ω REFCLK0 Z = 50Ω OUTA3 150Ω MAX3671 REFCLK1 10GE PHY 150Ω 0.1μF 156.25MHz Z = 50Ω OUTA0 50Ω REFCLK1 0.1μF 10GE PHY 50Ω 0.1μF Z = 50Ω OUTA0 150Ω 150Ω DM DA OUTA_EN OUTB_EN DB OUTB4 +3.3V 0.1μF 125MHz Z = 50Ω 50Ω 0.1μF GBE PHY 50Ω 0.1μF Z = 50Ω OUTB4 150Ω 150Ω SEL_CLK PLL_BYPASS 0.1μF FB_IN FB_IN FB_SEL MR 125MHz Z = 50Ω OUTB0 50Ω 0.1μF 50Ω Z = 50Ω OUTB0 GND EP IN1FAIL IN0FAIL 0.1μF LOCK GBE PHY 150Ω 150Ω ______________________________________________________________________________________ 15 MAX3671 Typical Application Circuits MAX3671 Low-Jitter Frequency Synthesizer with Selectable Input Reference Typical Application Circuits (continued) OUTA[3:0] 62.5MHz 4 x 156.25MHz MAX3671 8kHz IN0 CLK0 62.5MHz REFCLK0 OUTB[4:0] 5 x 125MHz MAX9450 8kHz IN1 OUTA[3:0] 4 x 156.25MHz MAX3671 QA 25MHz 125MHz REFCLK0 OUTB[4:0] 5 x 312.5MHz MAX3624 2 x 125MHz QB[1:0] Chip Information PROCESS: BiCMOS Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 56 TQFN-EP T5688+3 21-0135 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.