MCP3913A1T-E/MV

MCP3913 3V Six-Channel Analog Front End Features Description • Six Synchronous Sampling 24-Bit Resolution Delta-Sigma A/D Converters • 94.5 dB SINAD, -107 dBc Total Harmonic Distortion (THD) (up to 35th Harmonic), 112 dBFS SFDR for Each Channel • Enables 0.1% Typical Active Power Measurement Error Over a 10,000:1 Dynamic Range • Advanced Security Features: - 16-Bit Cyclic Redundancy Check (CRC) Checksum on All Communications for Secure Data Transfers - 16-Bit CRC Checksum and Interrupt Alert for Register Map Configuration - Register Map Lock with 8-Bit Secure Key • 2.7V-3.6V AVDD, DVDD • Programmable Data Rate Up to 125 ksps: - 4 MHz Maximum Sampling Frequency - 16 MHz Maximum Master Clock • Oversampling Ratio Up to 4096 • Ultra-Low Power Shutdown Mode with 512). This SINC1 filter provides additional rejection at a low cost with little modification to the -3 dB bandwidth. The resolution (number of possible output codes expressed in powers of two or in bits) of the digital filter is 24-bit maximum for any OSR and data format choice. The resolution depends only on the OSR[2:0] bits setting in the CONFIG0 register per Table 5-3. Once the OSR is chosen, the resolution is fixed and the output code respects the data format defined by the WIDTH_DATA[1:0] bits setting in the STATUSCOM register (see Section 5.5 “ADC Output Coding”). DS20005227C-page 31 MCP3913 The gain of the transfer function of this filter is one at each multiple of DMCLK (typically 1 MHz), so a proper anti-aliasing filter must be placed at the inputs. This will attenuate the frequency content around DMCLK and keep the desired accuracy over the baseband of the converter. This anti-aliasing filter can be a simple, firstorder RC network, with a sufficiently low time constant to generate high rejection at the DMCLK frequency. Any unsettled data are automatically discarded to avoid data corruption. Each data ready pulse corresponds to fully settled data at the output of the decimation filter. The first data available at the output of the decimation TABLE 5-3: filter are present after the complete settling time of the filter (see Table 5-3). After the first data have been processed, the delay between two data ready pulses coming from the same ADC channel is one DRCLK period. The data stream from input to output is delayed by an amount equal to the settling time of the filter (which is the group delay of the filter). The achievable resolution, the -3 dB bandwidth and the settling time at the output of the decimation filter (the output of the ADC) are dependent on the OSR of each SINC filter, and are summarized in Table 5-3. OVERSAMPLING RATIO AND SINC FILTER SETTLING TIME OSR[2:0] OSR3 OSR1 Total OSR Resolution in Bits (No Missing Code) Settling Time -3 dB Bandwidth 32 1 32 17 96/DMCLK 0.26 * DRCLK 0 0 0 0 0 1 64 1 64 20 192/DMCLK 0.26 * DRCLK 0 1 0 128 1 128 23 384/DMCLK 0.26 * DRCLK 0 1 1 256 1 256 24 768/DMCLK 0.26 * DRCLK 1 0 0 512 1 512 24 1536/DMCLK 0.26 * DRCLK 1 0 1 512 2 1024 24 2048/DMCLK 0.37 * DRCLK 1 1 0 512 4 2048 24 3072/DMCLK 0.42 * DRCLK 1 1 1 512 8 4096 24 5120/DMCLK 0.43 * DRCLK 0 0 -20 Magnitude (dB) Ma agnitude (dB) -20 -40 -60 -80 -100 -40 -60 -80 -100 -120 -140 -120 1 10 100 1000 10000 100000 Input Frequency (Hz) FIGURE 5-3: SINC Filter Frequency Response, OSR = 256, MCLK = 4 MHz, PRE[1:0] = 00. DS20005227C-page 32 -160 1 100 10000 Input Frequency (Hz) 1000000 FIGURE 5-4: SINC Filter Frequency Response, OSR = 4096 (in pink), OSR = 512 (in blue), MCLK = 4 MHz, PRE[1:0] = 00.  2013-2020 Microchip Technology Inc. MCP3913 5.5 Equation 5-3 is only true for DC inputs. For AC inputs, this transfer function needs to be multiplied by the transfer function of the SINC3 + SINC1 filter (see Equation 5-1 and Equation 5-3). ADC Output Coding The second-order modulator, SINC3 + SINC1 filter, PGA, VREF and the analog input structure all work together to produce the device transfer function for the Analog-to-Digital conversion (see Equation 5-3). EQUATION 5-3: Each channel data are calculated on 24-bit (23-bit plus sign) and coded in two’s complement format, MSB first. The output format can then be modified by the WIDTH_DATA[1:0] settings in the STATUSCOM register to allow 16-/24-/32-bit format compatibility (see Section 8.6 “STATUSCOM Register – Status and Communication Register” for more information). DATA_CHn = (CHn+ – CHn-)  8,388,608  G 1.5  VREF+ – VREF-  For 24-Bit Mode, WIDTH_Data[1:0] = 01 (Default) For other than the default 24-bit data formats, Equation 5-3 should be multiplied by a scaling factor, depending on the data format used (defined by WIDTH_DATA[1:0]). The data format and associated scaling factors are given in Figure 5-5. In case of positive saturation (CHn+ – CHn- > VREF/1.5), the output is locked to 7FFFFF for 24-bit mode. In case of negative saturation (CHn+ – CHn- < -VREF/1.5), the output code is locked to 800000 for 24-bit mode. 23 0 DATA DATA [23:16] [15:8] 15 WIDTH_DATA[1:0] = 00 16-Bit DATA DATA [23:16] [15:8] Scaling Factor DATA [7:0] 0 DATA Unformatted ADC Data x1/256 Rounded WIDTH_DATA[1:0] = 01 24-Bit 23 WIDTH_DATA[1:0] = 10 32-Bit with Zeros Padded 31 WIDTH_DATA[1:0] = 11 32-Bit with Sign Extension FIGURE 5-5: DATA DATA [23:16] [15:8] 0 DATA [7:0] x1 0 DATA DATA [23:16] [15:8] DATA [7:0] DATA DATA DATA [23] [23:16] [15:8] DATA [7:0] 31 0x00 x256 0 x1 Output Data Formats.  2013-2020 Microchip Technology Inc. DS20005227C-page 33 MCP3913 The ADC resolution is a function of the OSR (Section 5.4 “SINC3 + SINC1 Filter”). The resolution is the same for all channels. No matter what the resolution is, the ADC output data are always calculated in 24-bit TABLE 5-4: words, with added zeros at the end if the OSR is not large enough to produce 24-bit resolution (left justification). OSR = 256 (AND HIGHER) OUTPUT CODE EXAMPLES ADC Output Code (MSB First) Hexadecimal Decimal, 24-Bit Resolution 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0x7FFFFF + 8,388,607 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0x7FFFFE + 8,388,606 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000000 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0xFFFFFF –1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0x800001 – 8,388,607 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x800000 – 8,388,608 TABLE 5-5: OSR = 128 OUTPUT CODE EXAMPLES ADC Output Code (MSB First) Hexadecimal Decimal, 23-Bit Resolution 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0x7FFFFE + 4,194,303 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 0x7FFFFC + 4,194,302 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000000 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0xFFFFFE –1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0x800002 – 4,194,303 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x800000 – 4,194,304 Hexadecimal Decimal, 20-Bit Resolution TABLE 5-6: OSR = 64 OUTPUT CODE EXAMPLES ADC Output Code (MSB First) 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0x7FFFF0 + 524, 287 0x7FFFE0 + 524, 286 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000000 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0xFFFFF0 –1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0x800010 – 524,287 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x800000 – 524, 288 Hexadecimal Decimal, 17-Bit Resolution TABLE 5-7: OSR = 32 OUTPUT CODE EXAMPLES ADC Output Code (MSB First) 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0x7FFF80 + 65, 535 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0x7FFF00 + 65, 534 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000000 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0xFFFF80 –1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0x800080 – 65,535 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x800000 – 65, 536 DS20005227C-page 34  2013-2020 Microchip Technology Inc. MCP3913 5.6 5.6.1 Voltage Reference INTERNAL VOLTAGE REFERENCE The MCP3913 contains an internal voltage reference source specially designed to minimize drift over temperature. In order to enable the internal voltage reference, the VREFEXT bit in the Configuration register must be set to ‘0’ (Default mode). This internal VREF supplies reference voltage to all channels. The typical value of this voltage reference is 1.2V, ±2%. The internal reference has a very low typical temperature coefficient of ±7 ppm/°C, allowing the output to have minimal variation with respect to temperature, since they are proportional to (1/VREF). The noise of the internal voltage reference is low enough not to significantly degrade the SNR of the ADC if compared to a precision external low noise voltage reference. The output pin for the internal voltage reference is REFIN+/OUT. If the voltage reference is only used as an internal VREF, adding bypass capacitance on REFIN+/OUT is not necessary for keeping ADC accuracy, but a minimal 0.1 µF ceramic capacitance can be connected to avoid EMI/EMC susceptibility issues due to the antenna created by the REFIN+/OUT pin, if left floating. The bypass capacitors also help applications where the voltage reference output is connected to other circuits. In this case, additional buffering may be needed since the output drive capability of this output is low. by this noise component, even at maximum OSR. This auto-zeroing algorithm is performed synchronously with the MCLK coming to the device. 5.6.3 TEMPERATURE COMPENSATION (VREFCAL[7:0]) The internal voltage reference consists of a proprietary circuit and algorithm to compensate first-order and second-order temperature coefficients. The compensation enables very low-temperature coefficients (typically 9 ppm/°C) on the entire range of temperatures, from -40°C to +125°C. This temperature coefficient varies from part to part. This temperature coefficient can be adjusted on each part through the VREFCAL[7:0] bits present in the CONFIG0 register (bits 7 to 0). These register settings are only for advanced users. VREFCAL[7:0] should not be modified unless the user wants to calibrate the temperature coefficient of the whole system or application. The default value of this register is set to 0x50. The default value (0x50) was chosen to optimize the standard deviation of the tempco across process variation. The value can be slightly improved to around 7 ppm/°C if the VREFCAL[7:0] bits are written at 0x50, but this setting degrades the standard deviation of the VREF tempco. The typical variation of the temperature coefficient of the internal voltage reference, with respect to the VREFCAL register code, is shown in Figure 5-6. Modifying the value stored in the VREFCAL[7:0] bits may also vary the voltage reference, in addition to the temperature coefficient. 60 5.6.2 50 DIFFERENTIAL EXTERNAL VOLTAGE INPUTS When the VREFEXT bit is set to ‘1’, the two reference pins (REFIN+/OUT, REFIN-) become a differential voltage reference input. The voltage at the REFIN+/OUT is noted VREF+ and the voltage at the REFIN- pin is noted VREF-. The differential voltage input value is shown in Equation 5-4. VREF Drift (ppm) Adding too much capacitance on the REFIN+/OUT pin may slightly degrade the THD performance of the ADCs. 40 30 20 10 0 0 EQUATION 5-4: VREF = VREF+ – VREFThe specified VREF range is from 1.1V to 1.3V. The REFIN- pin voltage (VREF-) should be limited to ±0.1V, with respect to AGND. Typically, for single-ended reference applications, the REFIN- pin should be directly connected to AGND with its own separate track to avoid any spike due to switching noise. These buffers are injecting a certain quantity of 1/f noise into the system, noise that can be modulated with the incoming input signals and that can limit the SNR at very high OSR (OSR > 256). To overcome this limitation, these buffers include an auto-zeroing algorithm that greatly diminishes their 1/f noise, as well as their offset, so that the SNR of the system is not limited  2013-2020 Microchip Technology Inc. 64 128 192 VREFCAL Register Trim Code (decimal) FIGURE 5-6: Trim Code Chart. 5.6.4 256 VREF Tempco vs. VREFCAL VOLTAGE REFERENCE BUFFERS Each channel includes a voltage reference buffer tied to the REFIN+/OUT pin, which allows the internal capacitors to properly charge with the voltage reference signals, even in the case of an external voltage reference connection with weak load regulation specifications. This ensures that the correct amount of current is sourced to each channel to ensure their accuracy specifications and diminishes the constraints on the voltage reference load regulation. DS20005227C-page 35 MCP3913 5.7 Both AVDD and DVDD are monitored, so either power supply can sequence first. Power-on Reset The MCP3913 contains an internal POR circuit that monitors both analog and digital supply voltages during operation. The typical threshold for a power-up event detection is 2.0V, ±10% and a typical start-up time (tPOR) of 50 µs. The POR circuit has a built-in hysteresis for improved transient spike immunity that has a typical value of 200 mV. Proper decoupling capacitors (0.1 µF in parallel with 10 µF) should be mounted as close as possible to the AVDD and DVDD pins, providing additional transient immunity. Note: Figure 5-7 illustrates the different conditions at a power-up and a power-down event in typical conditions. All internal DC biases are not settled until at least 1 ms in worst-case conditions after a system POR. Any data ready pulse occurring within 1 ms, plus the SINC filter settling time after system Reset, should be ignored to ensure proper accuracy. After POR, data ready pulses are present at the pin with all the default conditions in the Configuration registers. In order to ensure a proper power-up sequence, the ramp rate of DVDD should not exceed 3V/µs when coming out of the POR state. Additionally, the user should try to lower the DVDD residual voltage as close to 0V as possible when the device is kept in a POR state (below DVDD POR threshold) for a long time to ensure a proper powerup sequence. The user can verify if the power-up sequence has been correctly performed by reading the default state of all the registers in the register map right after powering up the device. If one or more of the registers do not show the proper default settings when being read, a new power-up cycle should be launched to recover from this condition. Voltage (AVDD, DVDD) Any data read pulse occurring during this time can yield inaccurate output data. It is recommended to discard them. POR Threshold Up (2.0V typical) (1.8V typical) tPOR POR State Analog Biases Settling Time Power-up SINC Filter Settling Time Normal Operation POR State Time Biases are settled. Biases are Conversions started unsettled. here are accurate. Conversions started here may not be accurate FIGURE 5-7: DS20005227C-page 36 Power-on Reset Operation.  2013-2020 Microchip Technology Inc. MCP3913 5.8 Hard Reset Effect on Delta-Sigma Modulator/SINC Filter When the RESET pin is logic low, all ADCs will be in Reset and output code: 0x000000h. The RESET pin performs a Hard Reset (DC biases are still on, the part is ready to convert) and clears all charges contained in the Delta-Sigma modulators. The comparator’s output is ‘0011’ for each ADC. The SINC filters are all reset, as well as their double-output buffers. This pin is independent of the serial interface. It brings all the registers to the default state. When RESET is logic low, any write with the SPI interface will be disabled and will have no effect. All output pins (SDO, DR) are high-impedance. If an external clock (MCLK) is applied, the input structure is enabled and is properly biasing the substrate of the input transistors. In this case, the leakage current on the analog inputs is low if the analog input voltages are kept between -1V and +1V. If MCLK is not applied when in Reset mode, the leakage can be high if the analog inputs are below -0.6V, as referred to AGND. 5.9 Phase Delay Block The MCP3913 incorporates a phase delay generator, which ensures that each pair of ADCs (CH0/1, CH2/3, CH4/5) are converting the inputs with a fixed delay between them. The six ADCs are synchronously sampling, but the averaging of modulator outputs is delayed so that the SINC filter outputs (thus the ADC outputs) show a fixed phase delay as determined by the PHASE0/1 register setting. The odd channels (CH1,3,5) are the reference channels for the phase delays of each pair; they set the time reference. Typically, these channels can be the voltage channels for a polyphase energy metering application. These odd channels are synchronous at all times, so they become ready and output a data ready pulse at the same time. The even channels (CH0/2/4) are delayed compared to the time reference (CH1/3/5) by a fixed amount of time defined for each pair channel in the PHASE0/1 registers. The two PHASE0/1 registers are split into three 12-bit banks that represent the delay between each pair of channels. The equivalence is defined in Table 5-8. Each phase value (PHASEA/B/C) represents the delay of the even channel, with respect to the associated odd channel, with an 11-bit plus sign, MSB first, two’s complement code. This code indicates how many DMCLK periods there are between each channel in the pair. (see Equation 5-5). Since the odd channels are the time reference when PHASEX[11:0] are positive, the even channel of the pair is lagging and the odd channel is leading. When PHASEX[11:0] are negative, the even channel of the pair is leading and the odd channel is lagging. TABLE 5-8: Pair of Channels Phase Bank Register Map Position CH1/CH0 PHASEA[11:0] PHASE1[11:0] CH3/CH2 PHASEB[11:0] PHASE1[23:12] CH5/CH4 PHASEC[11:0] PHASE0[11:0] EQUATION 5-5: Total Delay = PHASEx[11:0] Decimal Code DMCLK Where: x = A/B/C The timing resolution of the phase delay is 1/DMCLK or 1 µs in the default configuration, with MCLK = 4 MHz. Given the definition of DMCLK, the phase delay is affected by a change in the prescaler settings (PRE[1:0]) and the MCLK frequency. The data ready signals are affected by the phase delay settings. Typically, the time difference between the data ready pulses of odd and even channels is equal to the associated phase delay setting. Each ADC conversion start, and therefore, each data ready pulse is delayed by a timing of OSR/2 x DMCLK periods (equal to half a DRCLK period). This timing allows for the odd channel’s data ready signals to be located at a fixed time reference (OSR/2 x DMCLK periods from the Reset), while the even channel can be leading or lagging around this time reference with the corresponding PHASEX[11:0] delay value. Note:  2013-2020 Microchip Technology Inc. PHASE DELAYS EQUIVALENCE For a detailed explanation of the Data Ready pin (DR) with phase delay, see Figure 5.11. DS20005227C-page 37 MCP3913 5.9.1 PHASE DELAY LIMITS The limits of the phase delays are determined by the OSR settings; the phase delays can only go from -OSR/2 to +OSR/2-1 DMCLK periods. TABLE 5-9: PHASE VALUES WITH MCLK = 4 MHz, OSR = 4096, PRE[1:0] = 00 PHASEX[11:0] for the Channel Pair CH[n/n+1] Delay (CH[n] relative to CH[n+1]) If larger delays between the two channels are needed, they can be implemented externally to the chip with an MCU. A FIFO in the MCU can save incoming data from the leading channel for a number N of DRCLK clocks. In this case, DRCLK would represent the coarse timing resolution and DMCLK the fine timing resolution. The total delay will then be equal to: 0 1 1 1 1 1 1 1 1 1 1 1 0x7FF + 2047 µs 0 1 1 1 1 1 1 1 1 1 1 0 0x7FE + 2046 µs 0 0 0 0 0 0 0 0 0 0 0 1 0x001 + 1 µs 0 0 0 0 0 0 0 0 0 0 0 0 0x000 0 µs EQUATION 5-6: 1 1 1 1 1 1 1 1 1 1 1 1 0xFFF – 1 µs 1 0 0 0 0 0 0 0 0 0 0 1 0x801 – 2047 µs 1 0 0 0 0 0 0 0 0 0 0 0 0x800 – 2048 µs Total Delay = N/DRCLK + PHASE/DMCLK Note: Rewriting the PHASE registers with the same value automatically resets and restarts all ADCs. The Phase Delay registers can be programmed once with the OSR = 4096 setting and will adjust the OSR automatically afterwards without the need to change the value of the PHASE registers. • OSR = 4096: The delay can go from -2048 to +2047. PHASEX[11] is the sign bit. PHASEX[10] is the MSB and PHASEX[0] the LSB. • OSR = 2048: The delay can go from -1024 to +1023. PHASEX[10] is the sign bit. PHASEX[9] is the MSB and PHASEX[0] the LSB. • OSR = 1024: The delay can go from -512 to +511. PHASEX[9] is the sign bit. PHASEX[8] is the MSB and PHASEX[0] the LSB. • OSR = 512: The delay can go from -256 to +255 PHASEX[8] is the sign bit. PHASEX[7] is the MSB and PHASEX[0] the LSB. • OSR = 256: The delay can go from -128 to +127. PHASEX[7] is the sign bit. PHASEX[6] is the MSB and PHASEX[0] the LSB. • OSR = 128: The delay can go from -64 to +63. PHASEX[6] is the sign bit. PHASEX[5] is the MSB and PHASEX[0] the LSB. • OSR = 64: The delay can go from -32 to +31. PHASEX[5] is the sign bit. PHASEX[4] is the MSB and PHASEX[0] the LSB. • OSR = 32: The delay can go from -16 to +15. PHASEX[4] is the sign bit. PHASEX[3] is the MSB and PHASEX[0] the LSB. DS20005227C-page 38 5.10 Hex Data Ready Link There are two modes defined with the DR_LINK bit in the STATUSCOM register that control the data ready pulses. The position of the data ready pulses varies with respect to this mode, to the OSR[2:0] and to the PHASE0/1 register settings. Section 5.11 “Data Ready Status Bits” represents the behavior of the Data Ready pin with the two DR_LINK configurations. • DR_LINK = 0: Data ready pulses from all enabled channels are output on the DR pin. • DR_LINK = 1 (Recommended and Default mode): Only the data ready pulses from the most lagging ADC between all the active ADCs are present on the DR pin. The lagging ADC data ready position depends on the PHASE0/1 registers, the PRE[1:0] and the OSR[2:0] bits settings. In this mode, the active ADCs are linked together, so their data are latched together when the lagging ADC output is ready. For power metering applications, DR_LINK = 1 is recommended (Default mode); it allows the host MCU to gather all channels synchronously within a unique interrupt pulse and it ensures that all channels have been latched at the same time, so that no data corruption is happening.  2013-2020 Microchip Technology Inc. MCP3913 5.11 Data Ready Status Bits 5.12 In addition to the Data Ready pin indicator, the MCP3913 device includes a separate data ready status bit for each channel. Each ADC channel CHn is associated to the corresponding DRSTATUS[n] that can be read at all times in the STATUSCOM register. These status bits can be used to synchronize the data retrieval in case the DR pin is not connected (see Section 6.8 “ADC Channels Latching and Synchronization”). The DRSTATUS[5:0] bits are not writable; writing on them has no effect. They have a default value of ‘1’, which indicates that the data of the corresponding ADC are not ready. This means that the ADC Output register has not been updated since the last reading (or since the last Reset). The DRSTATUS bits take the ‘0’ state once the ADC channel register is updated (which happens at a DRCLK rate). A simple read of the STATUSCOM register clears all the DRSTATUS bits to their default value (‘1’). In the case of DR_LINK = 1, the DRSTATUS[5:0] bits are all updated synchronously with the most lagging channel at the same time the DR pulse is generated. In case of DR_LINK = 0, each DRSTATUS bit is updated independently and synchronously with its corresponding channel. PHASE < 0 Crystal Oscillator The MCP3913 includes a Pierce-type crystal oscillator with very high stability and ensures very low tempco and jitter for the clock generation. This oscillator can handle crystal frequencies up to 20 MHz, provided proper load capacitances and quartz quality factors are used. The crystal oscillator is enabled when CLKEXT = 0 in the CONFIG1 register. For a proper start-up, the load capacitors of the crystal should be connected between OSC1 and DGND, and between OSC2 and DGND. They should also respect Equation 5-7. EQUATION 5-7: 2 6 1 R M < 1.6  10   ------------------------  f  CLOAD Where: f = Crystal frequency in MHz CLOAD = Load capacitance in pF including parasitics from the PCB RM = Motional resistance in ohms of the quartz When CLKEXT = 1, the crystal oscillator is bypassed by a digital buffer to allow direct clock input for an external clock (see Figure 4-1). In this case, the OSC2 pin is pulled down internally to DGND and should be connected to DGND externally for better EMI/EMC immunity. PHASE > 0 DR DR_LINK = 0 All Channels’ Data Ready are Present Data Ready Pulse from Odd Channels (reference) PHASE = 0 Data Ready Pulse from Most Lagging ADC Channel Data Ready Pulse from Odd Channels (reference) PHASE = 0 Data Ready Pulse from Most Lagging ADC Channel DR DR_LINK = 1 Only the Most Lagging Data Ready is Present All Channels are Latched Together at DR Falling Edge FIGURE 5-8: One DRCLK Period (OSR times DMCLK periods) DR_LINK Configurations. The external clock should not be higher than 20 MHz before prescaling (MCLK < 20 MHz) for proper operation.  2013-2020 Microchip Technology Inc. Note: In addition to the conditions defining the maximum MCLK input frequency range, the AMCLK frequency should be maintained inferior to the maximum limits, defined in Table 5-2, to ensure the accuracy of the ADCs. If these limits are exceeded, it is recommended to choose either a larger OSR or a larger prescaler value so that AMCLK can respect these limits. DS20005227C-page 39 MCP3913 5.13 Digital System Offset and Gain Calibration Registers The MCP3913 incorporates two sets of additional registers per channel to perform system digital offset and gain error calibration. Each channel has its own set of associated registers that will modify the output result of the channel if calibration is enabled. The gain and offset calibrations can be enabled or disabled through two CONFIG0 bits (EN_OFFCAL and EN_GAINCAL). These two bits enable or disable system calibration on all channels at the same time. When both calibrations are enabled, the output of the ADC is modified per Section 5.13.1 “Digital Offset Error Calibration”. 5.13.1 DIGITAL OFFSET ERROR CALIBRATION The OFFCAL_CHn registers are 23-bit plus two’s complement registers, and whose LSB value is the same as the channel ADC data. These registers are added, bit by bit, to the ADC output codes if the EN_OFFCAL bit is enabled. Enabling the EN_OFFCAL bit does not create a pipeline delay; the offset addition is instantaneous. For low OSR values, only the significant digits are added to the output (up to the resolution of the ADC; for example, at OSR = 32, only the 17 first bits are added). The offset is not added when the corresponding channel is in Reset or Shutdown mode. The corresponding input voltage offset value added by each LSB in these 24-bit registers is: OFFSET(1LSB) = VREF/(PGA_CHn x 1.5 x 8388608) 5.13.2 DIGITAL GAIN ERROR CALIBRATION These registers are signed 24-bit MSB first registers coded with a range of -1x to +(1 – 2-23)x (from 0x800000 to 0x7FFFFF). The gain calibration adds 1x to this register and multiplies it to the output code of the channel, bit by bit, after offset calibration. The range of the gain calibration is thus from 0x to 1.9999999x (from 0x800000 to 0x7FFFFF). The LSB corresponds to a 2-23 increment in the multiplier. Enabling EN_GAINCAL creates a pipeline delay of 24 DMCLK periods on all channels. All data ready pulses are delayed by 24 DMCLK periods, starting from the data ready following the command enabling the EN_GAINCAL bit. The gain calibration is effective on the next data ready following the command enabling the EN_GAINCAL bit. The digital gain calibration does not function when the corresponding channel is in Reset or Shutdown mode. The gain multiplier value for an LSB in these 24-bit registers is: GAIN (1 LSB) = 1/8388608 This register is a “Don’t Care” if EN_GAINCAL = 0 (offset calibration disabled), but its value is not cleared by the EN_GAINCAL bit. The output data on each channel are kept to either 7FFF or 8000 (16-bit mode), or 7FFFFF or 800000 (24-bit mode) if the output results are out of bounds after all calibrations are performed. This registers are a “Don’t Care” if EN_OFFCAL = 0 (offset calibration disabled), but their value is not cleared by the EN_OFFCAL bit. EQUATION 5-8: DIGITAL OFFSET AND GAIN ERROR CALIBRATION REGISTERS CALCULATIONS DATA_CHn  post – cal  =  DATA_CHn  pre – cal  + OFFCAL_CHn    1 + GAINCAL_CHn  DS20005227C-page 40  2013-2020 Microchip Technology Inc. MCP3913 6.0 SPI SERIAL INTERFACE DESCRIPTION 6.1 Overview The MCP3913 device includes a four-wire (CS, SCK, SDI, SDO) digital serial interface that is compatible with SPI Modes 0,0 and 1,1. Data are clocked out of the MCP3913 on the falling edge of SCK and data are clocked into the MCP3913 on the rising edge of SCK. In these modes, the SCK clock can Idle either high (1,1) or low (0,0). The digital interface is asynchronous with the MCLK clock that controls the ADC sampling and digital filtering. All the digital input pins are Schmitt triggered to avoid system noise perturbations on the communications. Each SPI communication starts with a CS falling edge and stops with the CS rising edge. Each SPI communication is independent. When CS is logic high, SDO is in high-impedance, and transitions on SCK and SDI have no effect. Changing from an SPI Mode 1,1 to an SPI Mode 0,0 and vice versa is possible, and can be done while the CS pin is logic high. Any CS rising edge clears the communication and resets the SPI digital interface. Additional control pins (RESET, DR) are also provided on separate pins for advanced communication features. The Data Ready pin (DR) outputs pulses when new ADC channel data are available for reading, which can be used as an interrupt for an MCU. The Master Reset pin (RESET) acts like a Hard Reset and can reset the part to its default power-up configuration (equivalent to a POR state). The MCP3913 interface has a simple command structure. Every command is either a READ command from a register or a WRITE command to a register. The MCP3913 device includes 32 registers defined in the register map (Table 8-1). The first byte (8-bit wide) transmitted is always the control byte that defines the address of the register and the type of command (READ or WRITE). It is followed by the register itself, which can be in a 16, 24 or 32-bit format, depending on the multiple format settings defined in the STATUSCOM register. The MCP3913 is compatible with multiple formats that help reduce overhead in the data handling for most MCUs and processors available on the market (8, 16 or 32-bit MCUs) and improve MCU code compaction and efficiency. The MCP3913 digital interface is capable of handling various continuous Read and Write modes, which allow it to perform ADC data streaming or full register map writing within only one communication (and therefore, with only one unique control byte). The internal registers can be grouped together with various configurations through the READ[1:0] and WRITE bits. The internal address counter of the serial interface can be automatically incremented, with no additional control byte needed, in order to loop through the various groups of registers within the register map. The groups are defined in Table 8-2.  2013-2020 Microchip Technology Inc. The MCP3913 device also includes advanced security features. These features secure each communication, to avoid unwanted WRITE commands being processed to change the desired configuration and to alert the user in case of a change in the desired configuration. Each SPI read communication can be secured through a selectable CRC-16 checksum provided on the SDO pin at the end of every communication sequence. This CRC-16 computation is compatible with the DMA CRC hardware of the PIC24 and PIC32 MCUs, resulting in no additional overhead for the added security. For securing the entire configuration of the device, the MCP3913 includes an 8-bit lock code (LOCK[7:0]), which blocks all WRITE commands to the full register map if the value of the LOCK[7:0] bits are not equal to a defined password (0xA5). The user can protect its configuration by changing the LOCK[7:0] value to 0x00 after the full programming, so that any unwanted WRITE command will not result in a change to the configuration (because the LOCK[7:0] bits are different than the password 0xA5). An additional CRC-16 calculation is also running continuously in the background to ensure the integrity of the full register map. All writable registers of the register map (except the MOD register) are processed through a CRC-16 calculation engine and give a CRC-16 checksum that depends on the configuration. This checksum is readable on the LOCK/CRC register and updated at all times. If a change in this checksum happens, a selectable interrupt can give a flag on the DR pin (DR pin becomes logic low) to warn the user that the configuration is corrupted. 6.2 Control Byte The control byte of the MCP3913 contains two device Address bits (A[6:5]), five register Address bits (A[4:0]) and a Read/Write bit (R/W). The first byte transmitted to the MCP3913 in any communication is always the control byte. During the control byte transfer, the SDO pin is always in a high-impedance state. The MCP3913 interface is device-addressable (through A[6:5]), so that multiple chips can be present on the same SPI bus with no data bus contention. Even if they use the same CS pin, they use a provided half-duplex SPI interface with a different address identifier. This functionality enables, for example, a serial EEPROM, such as 24AAXXX/24LCXXX or 24FCXXX and the MCP3913, to share all the SPI pins and consume less I/O pins in the application processor, since all these serial EEPROM circuits use A[6:5] = 00. . A[6] A[5] Device Address FIGURE 6-1: A[4] A[3] A[2] A[1] Register Address A[0] R/W Read/ Write Control Byte. DS20005227C-page 41 MCP3913 The default device Address bits are A[6:5] = 01 (contact the Microchip factory for other available device Address bits). For more information, see the Product Identification System section. The register map is defined in Table 8-1. 6.3 Four different Read mode configurations can be defined through the READ[1:0] bits in the STATUSCOM register for the address increment (see Section 6.5 “Continuous Communications, Looping on Register Sets” and Table 8-2). The data on SDO are clocked out of the MCP3913 on the falling edge of SCK. The reading format for each register is defined in Section 6.5 “Continuous Communications, Looping on Register Sets”. Reading from the Device The first register read on the SDO pin is the one defined by the address (A[4:0]) given in the control byte. After this first register is fully transmitted, if the CS pin is maintained logic low, the communication continues without an additional control byte and the SDO pin transmits another register with the address automatically incremented or not, depending on the READ[1:0] bits setting. CS Device latches SDI on rising edge Device latches SDO on falling edge DATA[ 1] DATA[ 2] DATA[ 3] DATA[ 4] DATA[ 5] DATA[ 6] DATA[ 7] DATA[ 8] DATA[ 9] DATA[ 10] DATA[ 12] DATA[ 13] DATA[ 14] DATA[ 15] DATA[ 16] DATA[ 17] DATA[ 18] DATA[ 19] DATA[ 20] DATA[ 22] DATA[ 21] DATA[ 23] High-Z SDO Don’t care R/W DATA[ 11] A[ 0] A[ 1] A[ 2] A[ 4] A[ 3] Don’t care A[ 5] SDI A[ 6] SCK DATA[ 0] High-Z Read Communication (SPI Mode 1,1) FIGURE 6-2: SPI Mode 1,1). Read on a Single Register with 24-Bit Format (WIDTH_DATA[1:0] = 01, CS Device latches SDI on rising edge Device latches SDO on falling edge DATA[ 0] DATA[ 1] DATA[ 2] DATA[ 3] DATA[ 4] DATA[ 5] DATA[ 6] DATA[ 7] DATA[ 8] DATA[ 9] DATA[ 10] DATA[ 11] DATA[ 12] DATA[ 13] DATA[ 14] DATA[ 15] DATA[ 16] DATA[ 17] DATA[ 18] DATA[ 19] DATA[ 20] A[ 0] A[ 1] A[ 2] A[ 3] R/W DATA[ 23] DATA[ 21] High-Z Don’t care DATA[ 22] SDO A[ 4] Don’t care A[ 5] SDI A[ 6] SCK Don’t care High-Z Read Communication (SPI Mode 0,0) FIGURE 6-3: SPI Mode 0,0). DS20005227C-page 42 Read on a Single Register with 24-Bit Format (WIDTH_DATA[1:0] = 01,  2013-2020 Microchip Technology Inc. MCP3913 6.4 Two different Write mode configurations for the address increment can be defined through the WRITE bit in the STATUSCOM register (see Section 6.5, Continuous Communications, Looping on Register Sets and Table 8-2). The SDO pin stays in a high-impedance state during a write communication. The data on SDI are clocked into the MCP3913 on the rising edge of SCK. The writing format for each register is defined in Section 6.5, Continuous Communications, Looping on Register Sets. A write on an undefined or nonwritable address, such as the ADC channel’s register addresses, will have no effect and also will not increment the address counter. Writing to the Device The first register written from the SDI pin to the device is the one defined by the address (A[4:0]) given in the control byte. After this first register is fully transmitted, if the CS pin is maintained logic low, the communication continues without an additional control byte and the SDI pin transmits another register with the address automatically incremented or not, depending on the WRITE bit setting. CS Device latches SDI on rising edge DATA[ 3] DATA[ 2] DATA[ 2] DATA[ 1] DATA[ 4] DATA[ 3] DATA[ 5] DATA[ 4] DATA[ 6] DATA[ 7] DATA[ 8] DATA[ 9] DATA[ 10] DATA[ 11] DATA[ 12] DATA[ 13] DATA[ 14] DATA[ 15] DATA[ 16] DATA[ 18] DATA[ 17] DATA[ 19] DATA[ 20] DATA[ 21] DATA[ 22] R/W DATA[ 23] A[ 0] A[ 1] A[ 2] A[ 3] A[ 4] Don’t care A[ 5] SDI A[ 6] SCK DATA[ 0] Don’t care High-Z SDO Write Communication (SPI Mode 1,1) FIGURE 6-4: Write to a Single Register with 24-Bit Format (SPI Mode 1,1). CS Device latches SDI on rising edge DATA[ 0] DATA[ 1] DATA[ 5] DATA[ 6] DATA[ 7] DATA[ 8] DATA[ 9] DATA[ 10] DATA[ 11] DATA[ 12] DATA[ 13] DATA[ 14] DATA[ 15] DATA[ 16] DATA[ 17] DATA[ 18] DATA[ 19] DATA[ 20] DATA[ 21] DATA[ 23] DATA[ 22] R/W A[ 0] A[ 1] A[ 2] A[ 3] A[ 4] Don’t care A[ 5] SDI A[ 6] SCK Don’t care High-Z SDO Write Communication (SPI Mode 0,0) FIGURE 6-5: Write to a Single Register with 24-Bit Format (SPI Mode 0,0).  2013-2020 Microchip Technology Inc. DS20005227C-page 43 MCP3913 6.5 high. The SPI internal Register Address Pointer starts by transmitting/receiving the address defined in the control byte. After this first transmission/reception, the SPI internal Register Address Pointer automatically increments to the next available address in the register set for each transmission/reception. When it reaches the last address of the set, the communication sequence is finished. The Address Pointer automatically loops back to the first address of the defined set and restarts a new sequence with auto-increment (see Table 6-6). The internal Address Pointer automatic selection allows the following functionality: Continuous Communications, Looping on Register Sets The MCP3913 digital interface can process communications in Continuous mode, without having to enter an SPI command between each read or write to a register. This feature allows the user to reduce communication overhead to the strict minimum, which diminishes EMI emissions and reduces switching noise in the system. The registers can be grouped into multiple sets for continuous communications. The grouping of the registers in the different sets is defined by the READ[1:0] and WRITE bits that control the internal SPI Communication Address Pointer. For a graphical representation of the register map sets in function of the READ[1:0] and WRITE bits, please see Table 8-2. • Read one ADC channel data, pairs of ADC channels or all ADC channels continuously • Continuously read the entire register map • Continuously read or write each separate register • Continuously read or write all Configuration registers In the case of a continuous communication, there is only one control byte on SDI to start the communication after a CS pin falling edge. The part stays within the same communication loop until the CS pin returns logic CS ADDRESS SET SCK 8x SDI CONTROL BYTE 24x 24x ... 24x 24x 24x ... 24x ADDR ADDR + 1 Don’t care Don’t care ... Starts Read Sequence at Address ADDR High-Z SDO Complete Read Sequence ADDR + n Rollover ADDR ADDR + 1 ... ADDR + n ADDR ADDR + 1 Complete Read Sequence ... ADDR + n Complete Read Sequence Continuous Read Communication (24-bit format) CS ADDRESS SET SCK 8x 24x 24x ... 24x 24x 24x ... 24x ADDR ADDR + 1 SDI Don’t care CONTROL BYTE Starts Write Sequence at Address ADDR SDO ADDR ADDR + 1 ... ADDR + n ADDR ADDR + 1 Complete Write Sequence ... Complete Write Sequence ADDR + n ... Complete Write Sequence ADDR + n Rollover High-Z Continuous Write Communication (24-bit format) FIGURE 6-6: DS20005227C-page 44 Continuous Communication Sequences.  2013-2020 Microchip Technology Inc. MCP3913 6.5.1 CONTINUOUS READ with the default settings (DR_LINK = 1, READ[1:0] = 10, WIDTH_DATA[1:0] = 01) in the case of the SPI Mode 0,0 (Figure 6-7) and SPI Mode 1,1 (Figure 6-8). The STATUSCOM register contains the read communication loop settings for the internal Register Address Pointer (READ[1:0] bits). For Continuous Read modes, the address selection can take the following four values: TABLE 6-1: For continuous reading of ADC data in SPI Mode 0,0 (see Figure 6-7), once the data have been completely read after a data ready, the SDO pin will take the MSB value of the previous data at the end of the reading (falling edge of the last SCK clock). If SCK stays Idle at logic low (by definition of Mode 0,0), the SDO pin will be updated at the falling edge of the next data ready pulse (synchronously with the DR pin falling edge with an output timing of tDODR) with the new MSB of the data corresponding to the data ready pulse. This mechanism allows the MCP3913 to continuously read ADC data outputs seamlessly, even in SPI Mode (0,0). Note: ADDRESS SELECTION IN CONTINUOUS READ Register Address Set Grouping for Continuous Read Communications READ[1:0] 00 Static (no incrementation) 01 Groups 10 Types (default) 11 Full Register Map Any SDI data coming after the control byte are not considered during a continuous read communication. The following figures represent a typical, continuous read communication on all six ADC channels in Types mode In SPI Mode (1,1), the SDO pin stays in the last state (LSB of previous data) after a complete reading, which also allows seamless continuous Read mode (see Figure 6-8). CS SCK SDI 8x Don’t care 24x 24x ... 24x 24x 24x ... DATA_CH0 DATA_CH1 ... 24x Don’t care 0x01 Starts Read Sequence at Address 00000 High-Z SDO DATA_CH0 DATA_CH1 ... DATA_CH5 DATA_CH0[23] DATA_CH0[23] Old Data New Data Complete Read Sequence on ADC Output Channels 0 to 5 DATA_CH5 Complete Read Sequence on New ADC Output Channels 0 to 5 DR FIGURE 6-7: Typical Continuous Read Communication (WIDTH_DATA[1:0] = 01, SPI Mode 0,0). CS SCK SDI 8x Don’t care 24x 24x ... 24x 24x 24x ... 24x DATA_CH0 DATA_CH1 ... DATA_CH5 Don’t care 0x01 Starts Read Sequence at Address 00000 SDO High-Z DATA_CH0 DATA_CH1 ... DATA_CH5 Complete Read Sequence on ADC Output Channels 0 to 5 Stays at DATA_CH5[0] Complete Read Sequence on New ADC Output Channels 0 to 5 DR FIGURE 6-8: Typical Continuous Read Communication (WIDTH_DATA[1:0] = 01, SPI Mode 1,1).  2013-2020 Microchip Technology Inc. DS20005227C-page 45 MCP3913 6.5.2 CONTINUOUS WRITE The STATUSCOM register contains the write loop settings for the internal Register Address Pointer (WRITE). For a continuous write, the address selection can take the following two values: TABLE 6-2: WRITE ADDRESS SELECTION IN CONTINUOUS WRITE Register Address Set Grouping for Continuous Read Communications 0 Static (no incrementation) 1 Types (default) SDO is always in a high-impedance state during a continuous write communication. Writing to a non-writable address (such as addresses 0x00 to 0x07) has no effect and does not increment the Address Pointer. In this case, the user needs to stop the communication and restart a communication with a control byte pointing to a writable address (0x08 to 0x1F). Note: 6.6 When the LOCK[7:0] bits are different than 0xA5, all the addresses, except 0x1F, become non-writable (see Section 4.13 “MCP3913 Delta-Sigma Architecture”). Situations that Reset and Restart Active ADCs Immediately after the following actions, the active ADCs (the ones not in Soft Reset or Shutdown modes) are reset and automatically restarted in order to provide proper operation: 1. 2. 3. 4. 5. 6. Change in PHASE0/1 registers. Overwrite of the same PHASE0/1 register value. Change in the OSR[2:0] settings. Change in the PRE[1:0] settings. Change in the CLKEXT setting. Change in the VREFEXT setting. After these temporary Resets, the ADCs go back to normal operation, with no need for an additional command. Each ADC Data Output register is cleared during this process. The PHASE0/1 registers can be used to serially soft reset the ADCs, without using the RESET[5:0] bits in the Configuration register, if the same value is written in one of the PHASE0/1 registers. DS20005227C-page 46 6.7 Data Ready Pin (DR) To communicate when channel data are ready for transmission, the data ready signal is available on the Data Ready (DR) pin at the end of a channel conversion. The Data Ready pin outputs an active-low pulse with a pulse width equal to half a DMCLK clock period. After a data ready pulse falling edge has occurred, the ADC output data are updated within the tDODR timing and can then be read through SPI communication. The first data ready pulse after a Hard or Soft Reset is located after the settling time of the SINC filter (see Table 5-3) plus the phase delay of the corresponding channel (see Section 5.9 “Phase Delay Block”). Each subsequent pulse is then periodic and the period is equal to a DRCLK clock period (see Equation 4-3 and Figure 1-3). The data ready pulse is always synchronous with the internal DRCLK clock. The DR pin can be used as an interrupt pin when connected to an MCU or DSP, which will synchronize the readings of the ADC data outputs. When not activelow, this pin can either be in high-impedance (when DR_HIZ = 0) or in a defined logic high state (when DR_HIZ = 1). This is controlled through the STATUSCOM register. This allows multiple devices to share the same Data Ready pin (with a pull-up resistor connected between DR and DVDD). If only the MCP3913 device is connected on the interrupt bus, the DR pin does not require a pull-up resistor, and therefore, it is recommended to use DR_HIZ = 1 configuration for such applications. The CS pin has no effect over the DR pin, which means even if the CS pin is logic high, the data ready pulses coming from the active ADC channels will still be provided; the DR pin behavior is independent from the SPI interface. While the RESET pin is logic low, the DR pin is not active. The DR pin is latched in the logic low state when the interrupt flag on the CRCREG is present to signal that the desired registers’ configuration has been corrupted (see Section 6.11 “Detecting Configuration Change Through CRC-16 Checksum on Register Map and its Associated Interrupt Flag”).  2013-2020 Microchip Technology Inc. MCP3913 6.8 ADC Channels Latching and Synchronization The ADC Channel Data Output registers (addresses 0x00 to 0x05) have a double-buffer output structure. The two sets of latches in series are triggered by the data ready signal and an internal signal indicating the beginning of a read communication sequence (read start). The first set of latches holds each ADC Channel Data Output register when the data are ready and latches all active outputs together when DR_LINK = 1. This behavior is synchronous with the DMCLK clock. The second set of latches ensures that when reading starts on an ADC output, the corresponding data are latched, so that no data corruption can occur within a read. This behavior is synchronous with the SCK clock. If an ADC read has started, in order to read the following ADC output, the current reading needs to be fully completed (all bits must be read on the SDO pin from the ADC Output Data registers). Since the double-output buffer structure is triggered with two events that depend on two asynchronous clocks (data ready with DMCLK and read start with SCK), one of the three following methods on the MCU or processor should be implemented in order to synchronize the reading of the channels: 1. 2. 3. The first method is the preferred one, as it can be used without adding additional MCU code space, but requires connecting the DR pin to an I/O pin of the MCU. The last two methods require more MCU code space and execution time, but they allow synchronized reading of the channels without connecting the DR pin, which saves one I/O pin on the MCU. 6.9 Securing Read Communications Through CRC-16 Checksum Since power/energy metering systems can generate or receive large EMI/EMC interferences and large transient spikes, it is helpful to secure SPI communications as much as possible to maintain data integrity and desired configurations during the lifetime of the application. The communication data on the SDO pin can be secured through the insertion of a Cyclic Redundancy Check (CRC) checksum at the end of each continuous reading sequence. The CRC checksum on communications can be enabled or disabled through the EN_CRCCOM bit in the STATUSCOM register. The CRC message ensures the integrity of the read sequence bits transmitted on the SDO pin, and the CRC checksum is inserted in between each read sequence (see Figure 6-9). Use the Data Ready pin pulses as an interrupt: Once a falling edge occurs on the DR pin, the data are available for reading on the ADC Output registers after the tDODR timing. If this timing is not respected, data corruption can occur. Use a timer clocked with MCLK as a synchronization event: Since the Data Ready pin is synchronous with DMCLK, the user can calculate the position of the Data Ready pin depending on the PHASE0/1 registers, the OSR[2:0] and the PRE[1:0] bits settings for each channel. Again, the tDODR timing needs to be added to this calculation, to avoid data corruption. Poll the DRSTATUS[5:0] bits in the STATUSCOM register: This method consists of continuously reading the STATUSCOM register and waiting for the DRSTATUS bits to be equal to ‘0’. When this event happens, the user can start a new communication to read the desired ADC data. In this case, no additional timing is required.  2013-2020 Microchip Technology Inc. DS20005227C-page 47 MCP3913 CS ADDRESS SET SCK 8x 16x/24x/32x Depending on Data Format 16x/24x/32x Depending on Data Format ... 16x/24x/32x Depending on Data Format 16x/24x/32x Depending on Data Format 16x/24x/32x Depending on Data Format 16x/24x/32x Depending on Data Format ... ADDR ADDR + 1 SDI CONTROL BYTE Don’t care Don’t care ... Starts Read Sequence at Address ADDR ADDR + n* Rollover High-Z SDO Complete Read Sequence ADDR ADDR + 1 ... ADDR + n ADDR Complete Read Sequence ADDR + 1 ... ADDR + n Complete Read Sequence Continuous Read Communication without CRC Checksum (EN_CRCCOM = 0) CS ADDRESS SET SCK 8x 16x/24x/32x Depending on Data Format 16x/24x/32x Depending on Data Format ... 16x/24x/32x Depending on Data Format 16x or 32x 16x/24x/32x Depending on Depending on CRC Format Data Format 16x/24x/32x Depending on Data Format ... 16x/24x/32x Depending on Data Format 16x or 32x Depending on CRC Format ADDR ADDR + 1 SDI CONTROL BYTE Don’t care Don’t care ... Starts Read Sequence at Address ADDR SDO Complete Read Sequence ADDR + n* High-Z ADDR ADDR + 1 ... ADDR + n CRC Checksum ADDR ADDR + 1 ... ADDR + n CRC Checksum CRC Checksum (not part of register map) Rollover Complete Read Sequence = Message for CRC Calculation Checksum New Message New Checksum Continuous Read Communication with CRC Checksum (EN_CRCCOM = 1) * n depends on the READ[1:0] bits. FIGURE 6-9: Continuous Read Sequences with and without CRC Checksum Enabled. The CRC checksum in the MCP3913 device uses the 16-bit CRC-16 ANSI polynomial, as defined in the IEEE 802.3 standard: x16 + x15 + x2 + 1. This polynomial can also be noted as 0x8005. CRC-16 detects all single and double-bit errors, all errors with an odd number of bits, all burst errors of length 16 or less and most errors for longer bursts. This allows an excellent coverage of the SPI communication errors that can happen in the system, and heavily reduces the risk of a miscommunication, even under noisy environments. The CRC-16 format displayed on the SDO pin depends on the WIDTH_CRC bit in the STATUSCOM register (see Figure 6-10). It can be either 16-bit or 32-bit format, to be compatible with both 16-bit and 32-bit MCUs. The CRCCOM[15:0] bits, calculated by the MCP3913 device, are not dependent on the format (the device always calculates only a 16-bit CRC checksum). If a 32-bit MCU is used in the application, it is recommended to use 32-bit formats (WIDTH_CRC = 1) only. WIDTH_DATA[1] = 0 16-Bit Format 15 WIDTH_DATA[1] = 1 32-Bit Format 31 FIGURE 6-10: DS20005227C-page 48 The CRC calculation computed by the MCP3913 device is fully compatible with CRC hardware contained in the Direct Memory Access (DMA) of the PIC24 and PIC32 MCU product lines. The CRC message that should be considered in the PIC® device DMA is the concatenation of the read sequence and its associated checksum. When the DMA CRC hardware computes this extended message, the resulted checksum should be 0x0000. Any other result indicates that a miscommunication has happened and that the current communication sequence should be stopped and restarted. Note: The CRC will be generated only at the end of the selected address set, before the rollover of the Address Pointer occurs (see Figure 6-9). 0 CRCCOM CRCCOM [15:8] [7:0] CRCCOM CRCCOM [15:8] [7:0] 0 0x00 0x00 CRC Checksum Format.  2013-2020 Microchip Technology Inc. MCP3913 6.10 Locking/Unlocking Register Map Write Access The MCP3913 digital interface includes an advanced security feature that permits locking or unlocking the register map write access. This feature prevents the miscommunications that can corrupt the desired configuration of the device, especially an SPI read becoming an SPI write because of the noisy environment. The last register address of the register map (0x1F: LOCK/CRC) contains the LOCK[7:0] bits. If these bits are equal to the password value (which is equal to the default value of 0xA5), the register map write access is not locked. Any write can take place and the communications are not protected. When the LOCK[7:0] bits are different than 0xA5, the register map write access is locked. The register map, and therefore, the full device configuration, is writeprotected. Any write to an address other than 0x1F will yield no result. All the register addresses, except the address 0x1F, become read-only. In this case, if the user wants to change the configuration, the LOCK[7:0] bits have to be reprogrammed back to 0xA5 before sending the desired WRITE command. The LOCK[7:0] bits are located in the last register, so the user can program the whole register map, starting from 0x09 to 0x1E, within one continuous write sequence and then lock the configuration at the end of the sequence by writing all zeros in the address 0x1F, for example. 6.11 Detecting Configuration Change Through CRC-16 Checksum on Register Map and its Associated Interrupt Flag In order to prevent internal corruption of the register and to provide additional security on the register map configuration, the MCP3913 device includes an automatic and continuous CRC checksum calculation on the full register map Configuration bits. This calculation is not the same as the communication CRC checksum described in Section 6.9 “Securing Read Communications Through CRC-16 Checksum”. This calculation takes the full register map as the CRC message and outputs a checksum on the CRCREG[15:0] bits located in the LOCK/CRC register (address 0x1F).  2013-2020 Microchip Technology Inc. Since this feature is intended for protecting the configuration of the device, this calculation is run continuously only when the register map is locked (LOCK[7:0] bits are different than 0xA5, see Section 6.10, Locking/Unlocking Register Map Write Access). If the register map is unlocked, the CRCREG[15:0] bits are cleared and no CRC is calculated. The calculation is fully completed in 21 DMCLK periods and refreshed every 21 DMCLK periods continuously. The CRCREG[15:0] bits are reset when a POR or a Hard Reset occurs. All the bits contained in the registers, from addresses 0x09-0x1F, are processed by the CRC engine to give the CRCREG[15:0] bits. The DRSTATUS[5:0] bits are set to ‘1’ (default) and the CRCREG[15:0] bits are set to ‘0’ (default) for this calculation engine, as they could vary during the calculation. An interrupt flag can be enabled through the EN_INT bit in the STATUSCOM register and provided on the DR pin when the configuration has changed without a WRITE command being processed. This interrupt is a logic low state. This interrupt is cleared when the register map is unlocked (since the CRC calculation is not processed). At power-up, the interrupt is not present and the register map is unlocked. As soon as the user finishes writing its configuration, the user needs to lock the register map (writing 0x00, for example, in the LOCK bits) to be able to use the interrupt flag. The CRCREG[15:0] bits will be calculated for the first time in 21 DMCLK periods. This first value will then be the reference checksum value and will be latched internally until a Hard Reset, a POR, or an unlocking of the register map happens. The CRCREG[15:0] bits will then be calculated continuously and checked against the reference checksum. If the CRCREG[15:0] bits are different than the reference, the interrupt sends a flag by setting the DR pin to a logic low state until it is cleared. DS20005227C-page 49 MCP3913 NOTES: DS20005227C-page 50  2013-2020 Microchip Technology Inc. MCP3913 7.0 BASIC APPLICATION RECOMMENDATIONS 7.1 Typical Application Examples For power strip power metering applications, such as the MCP3914 application referenced in Figure 7-1, it can be used as a starting point for MCP3913 applications.The most common solution is to use one channel for voltage measurement and the rest of the channels for current measurement. Since all current lines are at the same potential, shunts can be used as current sensors, even if they do not provide any galvanic isolation. Since all channels are identical in the MCP3913, any channel can be chosen as the voltage channel (preferably CH0 or CH5 since they are on the edges and can lead to a cleaner layout). For polyphase metering applications, such as threephase meters, it is recommended to use a current sensor that provides galvanic isolations: Current Transformers, Rogowski coils, Hall sensors, etc. MCP3914 40-Lead UQFN FIGURE 7-1: MCP3914 Power Strip Application Example Schematic (may be used as starting point for MCP3913 applications).  2013-2020 Microchip Technology Inc. DS20005227C-page 51 MCP3913 7.2 Power Supply Design and Bypassing The MCP3913 device was designed to measure positive and negative voltages that might be generated by a current-sensing device. This current-sensing device, with a Common-mode voltage close to 0V, is referred to as AGND, which is a shunt or Current Transformer (CT) with burden resistors attached to ground. The high performance and good flexibility that characterize this ADC enables them to be used in other applications, as long as the absolute voltage on each pin, referred to AGND, stays in the -1V to +1V interval. In any system, the analog ICs (such as references or operational amplifiers) are always connected to the analog ground plane. The MCP3913 should also be considered as a sensitive analog component and connected to the analog ground plane. The ADC features two pairs of pins: AGND and AVDD, DGND and DVDD. For best performance, it is recommended to keep the two pairs connected to two different networks (Figure 7-2). This way, the design will feature two ground traces and two power supplies (Figure 7-3). This means the analog circuitry (including MCP3913) and the digital circuitry (MCU) should have separate power supplies and return paths to the external ground reference, as described in Figure 7-2. An example of a typical power supply circuit, with different lines for analog and digital power, is shown in Figure 7-3. A possible split example is shown in Figure 7-4, where the ground star connection can be done at the bottom of the device with the exposed pad. The split here between analog and digital can be done under the device, and AVDD and DVDD can be connected together with lines coming under the ground plane. Another possibility, sometimes easier to implement in terms of PCB layout, is to consider the MCP3913 as an analog component, and therefore, connect both AVDD and DVDD together, and AGND and DGND together, with a star connection. In this scheme, the decoupling capacitors may be larger due to the ripple on the digital power supply (caused by the digital filters and the SPI interface of the MCP3913) now causing glitches on the analog power supply. ID IA 0.1 μF 0.1 μF MCU C VA AVDD DVDD MCP39XX AGND DGND VD IA ID “Star” Point D-= A-= FIGURE 7-2: All Analog and Digital Return Paths Need to Stay Separate with Proper Bypass Capacitors. FIGURE 7-3: Power Supply with Separate Lines for Analog and Digital Sections. Note the “Net Tie” Object NT2 that Represents the Start Ground Connection. DS20005227C-page 52  2013-2020 Microchip Technology Inc. MCP3913 7.3 SPI Interface Digital Crosstalk The MCP3913 incorporates a high-speed 20 MHz SPI digital interface. This interface can induce a crosstalk, especially with the outer channels (CH0, for example), if it is running at its full speed without any precautions. The crosstalk is caused by the switching noise created by the digital SPI signals (also called ground bouncing). This crosstalk would negatively impact the SNR in this case. The noise is attenuated if a proper separation between the analog and digital power supplies is put in place (see Section 7.2 “Power Supply Design and Bypassing”). FIGURE 7-4: Separation of Analog and Digital Circuits on Layout. Figure 7-5 shows a more detailed example with a direct connection to a high-voltage line (e.g., a two-wire 120V or 220V system). A current-sensing shunt is used for current measurement on the high side/line side that also supplies the ground for the system. This is necessary as the shunt is directly connected to the channel input pins of the MCP3913. To reduce sensitivity to external influences, such as EMI, these two wires should form a twisted pair, as noted in Figure 7-5. The power supply and MCU are separated on the right side of the PCB, surrounded by the digital ground plane. The MCP3913 is kept on the left side, surrounded by the analog ground plane. There are two separate power supplies going to the digital section of the system and the analog section, including the MCP3913. With this placement, there are two separate current supply paths and current return paths, IA and ID. Analog Ground Plane IA Digital Ground Plane ID MCU MCP3913 IA ID VD VA Power Supply Circuitry In order to further remove the influence of the SPI communication on measurement accuracy, it is recommended to add series resistors on the SPI lines to reduce the current spikes caused by the digital switching noise (see Figure 7-5 where these resistors have been implemented). The resistors also help to keep the level of electromagnetic emissions low. The measurement graphs provided in this MCP3913 data sheet have been performed with 100 series resistors connected on each SPI I/O pin. Measurement accuracy disturbances have not been observed, even at the full speed of 20 MHz interfacing. The crosstalk performance is dependent on the package choice due to the difference in the pin arrangement (dual in-line or quad) and is improved in the 40-lead UQFN package. 7.4 Sampling Speed and Bandwidth If ADC power consumption is not a concern in the design, the BOOST settings can be increased for best performance so that the OSR is always kept at the maximum settings to improve the SINAD performance (see Table 7-1). If the MCU cannot generate a clock fast enough, it is possible to tap the OSC1/OSC2 pins of the MCP3913 crystal oscillator directly to the crystal of the microcontroller. When the sampling frequency is enlarged, the phase resolution is improved, and with the OSR increased, the phase compensation range can be kept in the same range as the default settings. TABLE 7-1: “Star” Point Twisted Pair LINE SHUNT MCLK (MHz) NEUTRAL FIGURE 7-5: Connection Diagram. The ferrite bead between the digital and analog ground planes helps keep high-frequency noise from entering the device. This ferrite bead is recommended to be low resistance; most often it is a THT component. Ferrite beads are typically placed on the shunt inputs and into the power supply circuit for additional protection.  2013-2020 Microchip Technology Inc. SAMPLING SPEED vs. MCLK AND OSR, ADC PRESCALE 1:1 BOOST[1:0] OSR Sampling Speed (ksps) 16 11 1024 3.91 14 11 1024 3.42 12 11 1024 2.93 10 10 1024 2.44 8 10 512 3.91 6 01 512 2.93 4 01 256 3.91 DS20005227C-page 53 MCP3913 7.5 Differential Inputs Anti-Aliasing Filter Due to the nature of the ADCs used in the MCP3913 (oversampling converters), each differential input of the ADC channels requires an anti-aliasing filter so that the oversampling frequency (DMCLK) is largely attenuated and does not generate any disturbances on the ADC accuracy. This anti-aliasing filter also needs to have a gain close to one in the signal bandwidth of interest. Typically for 50/60 Hz measurement and default settings (DMCLK = 1 MHz), a simple RC filter with 1 k and 100 nF can be used. The anti-aliasing filter used for the measurement graphs is a first-order RC filter with 1 k and 15 nF. The typical schematic for connecting a Current Transformer to the ADC is shown in Figure 7-6. If wires are involved, twisting them is also recommended. The MCP3913 is highly recommended in applications using di/dt as current sensors because of the extremely low noise floor at low frequencies. In such applications, a Low-Pass Filter (LPF) with a cutoff frequency much lower than the signal frequency (50-60 Hz for metering) is used to compensate for the 90-degree shift and for the 20 db/decade attenuation induced by the di/dt sensor. Because of this filter, the SNR will be decreased, since the signal will attenuate by a few orders of magnitude, while the low-frequency noise will not be attenuated. Usually, a high-order High-Pass Filter (HPF) is used to attenuate the low-frequency noise in order to prevent a dramatic degradation of the SNR, which can be very important in other parts. A high-order filter will also consume a significant portion of the computation power of the MCU. When using the MCP3913, such a highorder HPF is not required, since this part has a low noise floor at low frequencies. A first-order HPF is enough to achieve very good accuracy. 7.6 Energy Measurement Error Considerations The measurement error is a typical representation of the nonlinearity of a pair of ADCs (see Section 4.0 “Terminology and Formulas” for the definition of measurement error). The measurement error is dependent on the THD and on the noise floor of the ADCs. FIGURE 7-6: First-Order Anti-Aliasing Filter for CT-Based Designs. The di/dt current sensors, such as Rogowski coils, can be an alternative to Current Transformers. Since these sensing elements are highly sensitive to highfrequency electromagnetic fields, using a second-order anti-aliasing filter is recommended to increase the attenuation of potential perturbing RF signals. FIGURE 7-7: Second-Order Anti-Aliasing Filter for Rogowski Coil-Based Designs. DS20005227C-page 54 Improving the measurement error specification on the MCP3913 can be realized by increasing the OSR (to get a better SINAD and THD performance), and to some extent, the BOOST settings (if the bandwidth of the measurements is too limited by the bandwidth of the amplifiers in the Delta-Sigma ADCs). In most of the energy metering AC applications, High-Pass Filters are used to cancel the offset on each ADC channel (current and voltage channels), and therefore, a single point calibration is necessary to calibrate the system for active energy measurement. This calibration is a system gain calibration, and the user can utilize the EN_GAINCAL bit and the GAINCAL_CHn registers to perform this digital calibration. After such calibration, typical measurement error curves, such as shown in Figure 2-7, can be generated by sweeping the current channel amplitude and measuring the energy at the outputs (the energy calculations here are being realized off-chip). The error is measured using a gain of 1x, as it is commonly used in most CT-based applications.  2013-2020 Microchip Technology Inc. MCP3913 At low signal amplitude values (typically 1000:1 dynamic range and higher), the crosstalk between channels, mainly caused by the PCB, becomes a significant part of the perturbation as the measurement error increases. The 1-point measurement error curves in Figure 2-5 have been performed with a full-scale sine wave on all the inputs that are not measured, which means that these channels induce a maximum amount of crosstalk on the measurement error curve. In order to avoid such behavior, a 2-point calibration can be put in place in the calculation section.  2013-2020 Microchip Technology Inc. This 2-point calibration can be a simple linear interpolation between two calibration points (one at high amplitudes, one at low amplitudes at each end of the dynamic range) and helps to significantly lower the effect of crosstalk between channels. A 2-point calibration is very effective in maintaining the measurement error close to zero on the whole dynamic range, since the nonlinearity and distortion of the MCP3913 is very low. Figure 2-6 shows the measurement error curves obtained with the same ADC data taken for Figure 2-5, but where a 2-point calibration has been applied. The difference is significant only at the low end of the dynamic range, where all the perturbing factors are a bigger part of the ADC output signals. These curves show extremely tight measurement error across the full dynamic range (here, typically 10,000:1), which is required in high-accuracy class meters. DS20005227C-page 55 MCP3913 NOTES: DS20005227C-page 56  2013-2020 Microchip Technology Inc. MCP3913 8.0 MCP3913 INTERNAL REGISTERS The addresses associated with the internal registers are listed in Table 8-1. This section also describes the registers in detail. All registers are 24-bit long registers, which can be addressed and read separately. TABLE 8-1: The format of the data registers (0x00 to 0x05) can be changed with the WIDTH_DATA[1:0] bits in the STATUSCOM register. The READ[1:0] and WRITE bits define the groups and types of registers for continuous read/write communication or looping on address sets, as shown in Table 8-2. MCP3913 REGISTER MAP Address Name Bits R/W Description 0x00 CHANNEL0 24 R Channel 0 ADC Data[23:0], MSB first 0x01 CHANNEL1 24 R Channel 1 ADC Data[23:0], MSB first 0x02 CHANNEL2 24 R Channel 2 ADC Data[23:0], MSB first 0x03 CHANNEL3 24 R Channel 3 ADC Data[23:0], MSB first 0x04 CHANNEL4 24 R Channel 4 ADC Data[23:0], MSB first 0x05 CHANNEL5 24 R Channel 5 ADC Data[23:0], MSB first 0x06 Unused 24 U Unused 0x07 Unused 24 U Unused 0x08 MOD 24 R/W Delta-Sigma Modulators Output Value 0x09 PHASE0 24 R/W Phase Delay Configuration Register – Channel Pairs 4/5 0x0A PHASE1 24 R/W Phase Delay Configuration Register – Channel Pairs 0/1 and 2/3 0x0B GAIN 24 R/W Gain Configuration Register 0x0C STATUSCOM 24 R/W Status and Communication Register 0x0D CONFIG0 24 R/W Configuration Register 0x0E CONFIG1 24 R/W Configuration Register 0x0F OFFCAL_CH0 24 R/W Offset Correction Register – Channel 0 0x10 GAINCAL_CH0 24 R/W Gain Correction Register – Channel 0 0x11 OFFCAL_CH1 24 R/W Offset Correction Register – Channel 1 0x12 GAINCAL_CH1 24 R/W Gain Correction Register – Channel 1 0x13 OFFCAL_CH2 24 R/W Offset Correction Register – Channel 2 0x14 GAINCAL_CH2 24 R/W Gain Correction Register – Channel 2 0x15 OFFCAL_CH3 24 R/W Offset Correction Register – Channel 3 0x16 GAINCAL_CH3 24 R/W Gain Correction Register – Channel 3 0x17 OFFCAL_CH4 24 R/W Offset Correction Register – Channel 4 0x18 GAINCAL_CH4 24 R/W Gain Correction Register – Channel 4 0x19 OFFCAL_CH5 24 R/W Offset Correction Register – Channel 5 0x1A GAINCAL_CH5 24 R/W Gain Correction Register – Channel 5 0x1B Unused 24 U Unused 0x1C Unused 24 U Unused 0x1D Unused 24 U Unused 0x1E Unused 24 U Unused 0x1F LOCK/CRC 24 R/W  2013-2020 Microchip Technology Inc. Security Register (Password and CRC-16 on Register Map) DS20005227C-page 57 MCP3913 TABLE 8-2: REGISTER MAP GROUPING FOR ALL CONTINUOUS READ/WRITE MODES READ[1:0] 0x02 CHANNEL 3 0x03 CHANNEL 4 0x04 CHANNEL 5 0x05 MOD 0x08 PHASE0 0x09 PHASE1 0x0A GAIN 0x0B STATUSCOM 0x0C CONFIG0 0x0D CONFIG1 0x0E OFFCAL_CH0 0x0F GAINCAL_CH0 0x10 OFFCAL_CH1 0x11 GAINCAL_CH1 0x12 OFFCAL_CH2 0x13 GAINCAL_CH2 0x14 OFFCAL_CH3 0x15 GAINCAL_CH3 0x16 OFFCAL_CH4 0x17 GAINCAL_CH4 0x18 OFFCAL_CH5 0x19 GAINCAL_CH5 0x1A LOCK/CRC 0x1F = 00 =1 =0 GROUP Static Not Writable (Address undefined for Write access) CHANNEL 2 = 01 Not Writable (Address undefined for Write access) 0x01 Static TYPE 0x00 GROUP Static GROUP Static GROUP Static Static Static Static Static Static LOOP ENTIRE REGISTER MAP CHANNEL 0 CHANNEL 1 = 10 GROUP Static Static Static Static Static Static Static GROUP Static Static LOOP ONLY ON WRITABLE REGISTERS = 11 DS20005227C-page 58 WRITE Address TYPE Function Static Static Static Static Static GROUP Static GROUP Static GROUP Static GROUP Static Static Static GROUP Static Static Static Static Static Static Static Static Static GROUP Static Static Static Static Static Static Static  2013-2020 Microchip Technology Inc. MCP3913 8.1 The ADC Channel Data Output registers always contain the most recent A/D conversion data for each channel. These registers are read-only. They can be accessed independently or linked together (with the READ[1:0] bits). These registers are latched when an ADC read communication occurs. When a data ready event occurs during a read communication, the most current ADC data are also latched to avoid data corruption issues. These registers are updated and latched together if DR_LINK = 1 synchronously with the data ready pulse (toggling on the most lagging ADC channel data ready event). CHANNEL Registers – ADC Channel Data Output Registers Name Bits Address Cof. CHANNEL0 24 0x00 R CHANNEL1 24 0x01 R CHANNEL2 24 0x02 R CHANNEL3 24 0x03 R CHANNEL4 24 0x04 R CHANNEL5 24 0x05 R REGISTER 8-1: R-0 (MSB) MCP3913 CHANNEL REGISTERS R-0 R-0 R-0 R-0 R-0 R-0 R-0 DATA_CHn[23:16] (MSB) bit 23 bit 16 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DATA_CHn[15:8] bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DATA_CHn[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-0 x = Bit is unknown DATA_CHn[23:0]: Output Code from ADC Channel n bits These data are post-calibration if the EN_OFFCAL or EN_GAINCAL bits are enabled. These data can be formatted in 16-/24-/32-bit modes, depending on the WIDTH_DATA[1:0] bits setting (see Section 5.5 “ADC Output Coding”).  2013-2020 Microchip Technology Inc. DS20005227C-page 59 MCP3913 8.2 MOD Register – Modulators Output Register Name Bits Address Cof. MOD 24 0x08 R/W The MOD register contains the most recent modulator data output and is updated at a DMCLK rate. The default value corresponds to an equivalent input of 0V on all ADCs. Each bit in this register corresponds to one comparator output on one of the channels. Do not write to this register to ensure the accuracy of each ADC. . REGISTER 8-2: R/W-0 MOD REGISTER R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 COMP3_CH5 COMP2_CH5 COMP1_CH5 COMP0_CH5 COMP3_CH4 COMP2_CH4 COMP1_CH4 COMP0_CH4 bit 23 bit 16 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 COMP3_CH3 COMP2_CH3 COMP1_CH3 COMP0_CH3 COMP3_CH2 COMP2_CH2 COMP1_CH2 COMP0_CH2 bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 COMP3_CH1 COMP2_CH1 COMP1_CH1 COMP0_CH1 COMP3_CH0 COMP2_CH0 COMP1_CH0 COMP0_CH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-20 COMPn_CH5: Comparator Outputs from ADC Channel 5 bits bit 19-16 COMPn_CH4: Comparator Outputs from ADC Channel 4 bits bit 15-12 COMPn_CH3: Comparator Outputs from ADC Channel 3 bits bit 11-8 COMPn_CH2: Comparator Outputs from ADC Channel 2 bits bit 7-4 COMPn_CH1: Comparator Outputs from ADC Channel 1 bits bit 3-0 COMPn_CH0: Comparator Outputs from ADC Channel 0 bits DS20005227C-page 60 x = Bit is unknown  2013-2020 Microchip Technology Inc. MCP3913 8.3 PHASE0 Register – Phase Configuration Register for Channel Pair 4/5 Name Bits Address Cof. PHASE0 24 0x09 R/W Any write to this register automatically resets and restarts all active ADCs. REGISTER 8-3: PHASE0 REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 R/W-0 R/W-0 PHASEC[11:8] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEC[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-12 Unimplemented: Read as ‘0’ bit 11-0 PHASEC[11:0]: Phase Delay Between Channels CH4 and CH5 (reference) bits Delay = PHASEC[11:0] decimal code/DMCLK.  2013-2020 Microchip Technology Inc. DS20005227C-page 61 MCP3913 8.4 PHASE1 Register – Phase Configuration Register for Channel Pairs 2/3 and 0/1 Name Bits Address Cof. PHASE1 24 0x0A R/W Any write to this register automatically resets and restarts all active ADCs. REGISTER 8-4: PHASE1 REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEB[11] PHASEB[10] PHASEB[9] PHASEB[8] PHASEB[7] PHASEB[6] PHASEB[5] PHASEB[4] bit 23 bit 16 R/W-0 R/W-0 R/W-0 PHASEB[3] PHASEB[2] PHASEB[1] R/W-0 R/W-0 R/W-0 PHASEB[0] PHASEA[11] PHASEA[10] R/W-0 R/W-0 PHASEA[9] PHASEA[8] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEA[7] PHASEA[6] PHASEA[5] PHASEA[4] PHASEA[3] PHASEA[2] PHASEA[1] PHASEA[0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-12 PHASEB[11:0]: Phase Delay Between Channels CH2 and CH3 (reference) bits Delay = PHASEB[11:0] decimal code/DMCLK. bit 11-0 PHASEA[11:0]: Phase Delay Between Channels CH0 and CH1(reference) bits Delay = PHASEA[11:0] decimal code/DMCLK. DS20005227C-page 62  2013-2020 Microchip Technology Inc. MCP3913 8.5 GAIN Register – PGA Gain Configuration Register Name Bits Address Cof. GAIN 24 0x0B R/W REGISTER 8-5: GAIN REGISTER U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-0 R/W-0 PGA_CH5[2] PGA_CH5[1] bit 23 bit 16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PGA_CH5[0] PGA_CH4[2] PGA_CH4[1] PGA_CH4[0] PGA_CH3[2] PGA_CH3[1] PGA_CH3[0] PGA_CH2[2] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PGA_CH2[1] PGA_CH2[0] PGA_CH1[2] PGA_CH1[1] PGA_CH1[0] PGA_CH0[2] PGA_CH0[1] PGA_CH0[0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-18 Unimplemented: Read as 0 bit 17-0 PGA_CHn[2:0]: PGA Setting for Channel n bits 111 = Reserved (Gain = 1) 110 = Reserved (Gain = 1) 101 = Gain is 32 100 = Gain is 16 011 = Gain is 8 010 = Gain is 4 001 = Gain is 2 000 = Gain is 1 (default)  2013-2020 Microchip Technology Inc. x = Bit is unknown DS20005227C-page 63 MCP3913 8.6 STATUSCOM Register – Status and Communication Register Name Bits Address Cof. STATUSCOM 24 0x0C R/W REGISTER 8-6: STATUSCOM REGISTER R/W-1 R/W-0 READ[1:0] R/W-1 R/W-0 R/W-1 R/W-0 WRITE DR_HIZ DR_LINK WIDTH_ CRC R/W-0 R/W-1 WIDTH_ DATA[1:0] bit 23 bit 16 R/W-0 R/W-0 r-0 r-0 U-0 U-0 U-0 U-0 EN_CRCCOM EN_INT — — — — — — bit 15 bit 8 U-0 U-0 — — R-1 R-1 R-1 R-1 R-1 R-1 DRSTATUS[5:0] bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-22 READ[1:0]: Address Counter Increment Setting for Read Communication bits 11 = Address counter auto-increments, loops on the entire register map 10 = Address counter auto-increments, loops on register TYPES (default) 01 = Address counter auto-increments, loops on register GROUPS 00 = Address not incremented, continually reads the same single register address bit 21 WRITE: Address Counter Increment Setting for Write Communication bit 1 = Address counter auto-increments and loops on writable part of the register map (default) 0 = Address counter not incremented, continually writes to the same single register address bit 20 DR_HIZ: Data Ready Pin Inactive State Control bit 1 = The DR pin state is a logic high when data are NOT ready 0 = The DR pin state is high-impedance when data are NOT ready (default) bit 19 DR_LINK: Data Ready Link Control bit 1 = Data ready link enabled; only one pulse is generated on the DR pin for all ADC channels, corresponding to the data ready pulse of the most lagging ADC 0 = Data ready link disabled; each ADC produces its own data ready pulse on the DR pin bit 18 WIDTH_CRC: CRC-16 Format on Communications bit 1 = 32-bit (CRC-16 code is followed by sixteen zeros); this coding is compatible with CRC implementation in most 32-bit MCUs (including PIC32 MCUs) 0 = 16-bit (default) bit 17-16 WIDTH_DATA[1:0]: ADC Data Format Settings for all ADCs bits (see Section 5.5 “ADC Output Coding”) 11 = 32-bit with sign extension 10 = 32-bit with zeros padding 01 = 24-bit (default) 00 = 16-bit (with rounding) DS20005227C-page 64  2013-2020 Microchip Technology Inc. MCP3913 REGISTER 8-6: STATUSCOM REGISTER (CONTINUED) bit 15 EN_CRCCOM: CRC-16 Checksum on Serial Communications Enable bit 1 = CRC-16 checksum is provided at the end of each communication sequence (therefore, each communication is longer); the CRC-16 message is the complete communication sequence (see Section 6.9 “Securing Read Communications Through CRC-16 Checksum” for more details) 0 = Disabled (default) bit 14 EN_INT: CRCREG Interrupt Function Enable bit 1 = The interrupt flag for the CRCREG checksum verification is enabled. The Data Ready pin (DR) will become logic low and stays logic low if a CRCREG checksum error happens. This interrupt is cleared if the LOCK[7:0] value is made equal to the password value (0xA5). 0 = The interrupt flag for the CRCREG checksum verification is disabled. The CRCREG[15:0] bits are still calculated properly and can still be read in this mode. No interrupt is generated, even when a CRCREG checksum error happens (default). bit 13-12 Reserved: Keep equal to ‘0’ at all times bit 11-6 Unimplemented: Read as ‘0’ bit 5-0 DRSTATUS[5:0]: Individual ADC Channel Data Ready Status bits DRSTATUS[n] = 1 – Channel CHn data are not ready (default) DRSTATUS[n] = 0 – Channel CHn data are ready. The status bit is set back to ‘1’ after reading the STATUSCOM register. The status bit is not set back to ‘1’ by the read of the corresponding channel ADC data.  2013-2020 Microchip Technology Inc. DS20005227C-page 65 MCP3913 8.7 CONFIG0 Register – Configuration Register 0 Name Bits Address Cof. CONFIG0 24 0x0D R/W REGISTER 8-7: CONFIG0 REGISTER R/W-0 R/W-0 R/W-1 EN_OFFCAL EN_GAINCAL DITHER[1] R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 DITHER[0] BOOST[1] BOOST[0] PRE[1] PRE[0] bit 23 bit 16 R/W-0 R/W-1 R/W-1 U-0 U-0 U-0 U-0 U-0 OSR[2] OSR[1] OSR[0] — — — — — bit 15 bit 8 R/W-0 VREFCAL[7] R/W-1 R/W-0 R/W-1 R/W-0 VREFCAL[6] VREFCAL[5] VREFCAL[4] VREFCAL[3] R/W-0 R/W-0 R/W-0 VREFCAL[2] VREFCAL[1] VREFCAL[0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23 EN_OFFCAL: 24-Bit Digital Offset Error Calibration on All Channels Enable bit 1 = Enabled; this mode does not add any group delay to the ADC data 0 = Disabled (default) bit 22 EN_GAINCAL: 24-Bit Digital Gain Error Calibration on All Channels Enable/Disable bit 1 = Enabled; this mode adds a group delay on all channels of 24 DMCLK periods, all data ready pulses are delayed by 24 DMCLK clock periods compared to the mode with EN_GAINCAL = 0. 0 = Disabled (default) bit 21-20 DITHER[1:0]: Dithering Circuit for Idle Tone’s Cancellation and Improved THD on All Channels Control bits 11 = Dithering on, Strength = Maximum (default) 10 = Dithering on, Strength = Medium 01 = Dithering on, Strength = Minimum 00 = Dithering is turned off bit 19-18 BOOST[1:0]: Bias Current Selection for all ADCs bits (impacts achievable maximum sampling speed, see Table 5-2) 11 = All channels have current x 2 10 = All channels have current x 1 (default) 01 = All channels have current x 0.66 00 = All channels have current x 0.5 bit 17-16 PRE[1:0]: Analog Master Clock (AMCLK) Prescaler Value bits 11 = AMCLK = MCLK/8 10 = AMCLK = MCLK/4 01 = AMCLK = MCLK/2 00 = AMCLK = MCLK (default) DS20005227C-page 66  2013-2020 Microchip Technology Inc. MCP3913 REGISTER 8-7: CONFIG0 REGISTER (CONTINUED) bit 15-13 OSR[2:0]: Oversampling Ratio for Delta-Sigma A/D Conversion bits (all channels, fd/fS) 111 = 4096 (fd = 244 sps for MCLK = 4 MHz, fs = AMCLK = 1 MHz) 110 = 2048 (fd = 488 sps for MCLK = 4 MHz, fs = AMCLK = 1 MHz) 101 = 1024 (fd = 976 sps for MCLK = 4 MHz, fs = AMCLK = 1 MHz) 100 = 512 (fd = 1.953 ksps for MCLK = 4 MHz, fs = AMCLK = 1 MHz) 011 = 256 (fd = 3.90625 ksps for MCLK = 4 MHz, fs = AMCLK = 1 MHz) (default) 010 = 128 (fd = 7.8125 ksps for MCLK = 4 MHz, fs = AMCLK = 1 MHz) 001 = 64 (fd = 15.625 ksps for MCLK = 4 MHz, fs = AMCLK = 1 MHz) 000 = 32 (fd = 31.25 ksps for MCLK = 4 MHz, fs = AMCLK = 1 MHz) bit 12-8 Unimplemented: Read as ‘0’ bit 7-0 VREFCAL[7:0]: Internal Voltage Temperature Coefficient VREFCAL[7:0] Value bits See Section 5.6.3 “Temperature Compensation (VREFCAL[7:0])” for complete description.  2013-2020 Microchip Technology Inc. DS20005227C-page 67 MCP3913 8.8 CONFIG1 Register – Configuration Register 1 Name Bits Address Cof. CONFIG1 24 0x0F R/W REGISTER 8-8: CONFIG1 REGISTER U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RESET[5:0] bit 23 bit 16 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SHUTDOWN[5:0] bit 15 bit 8 R/W-0 R/W-1 U-0 U-0 U-0 U-0 U-0 U-0 VREFEXT CLKEXT — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-22 Unimplemented: Read as ‘0’ bit 21-16 RESET[5:0]: Each Individual ADC Soft Reset Mode Setting bits RESET[n] = 1: Channel CHn is in Soft Reset mode RESET[n] = 0: Channel CHn is not in Soft Reset mode bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 SHUTDOWN[5:0]: Each Individual ADC Shutdown Mode Setting bits SHUTDOWN[n] = 1: ADC Channel CHn is in Shutdown mode SHUTDOWN[n] = 0: ADC Channel CHn is not in Shutdown mode bit 7 VREFEXT: Internal Voltage Reference selection bit 1 = Internal Voltage Reference Disabled: An external reference voltage needs to be applied across the REFIN+/- pins; the analog power consumption (AIDD) is slightly diminished in this mode since the internal voltage reference is placed into Shutdown mode 0 = Internal Reference Enabled: For optimal accuracy, the REFIN+/OUT pin needs proper decoupling capacitors; REFIN- pin should be connected to AGND when in this mode bit 6 CLKEXT: Internal Clock Selection bit 1 = MCLK is generated externally and should be provided on the OSC1 pin; the crystal oscillator is disabled and consumes no current (default) 0 = Crystal oscillator is enabled; a crystal must be placed between OSC1 and OSC2 with proper decoupling capacitors, the digital power consumption (DIDD) is increased in this mode due to the oscillator bit 5-0 Unimplemented: Read as ‘0’ DS20005227C-page 68  2013-2020 Microchip Technology Inc. MCP3913 8.9 OFFCAL_CHn and GAINCAL_CHn Registers – Digital Offset and Gain Error Calibration Registers Name Bits Address Cof. OFFCAL_CH0 24 0x0F R/W GAINCAL_CH0 24 0x10 R/W OFFCAL_CH1 24 0x11 R/W GAINCAL_CH1 24 0x12 R/W OFFCAL_CH2 24 0x13 R/W GAINCAL_CH2 24 0x14 R/W OFFCAL_CH3 24 0x15 R/W GAINCAL_CH3 24 0x16 R/W OFFCAL_CH4 24 0x17 R/W GAINCAL_CH4 24 0x18 R/W OFFCAL_CH5 24 0x19 R/W GAINCAL_CH5 24 0x1A R/W REGISTER 8-9: R/W-0 OFFCAL_CHn REGISTERS R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OFFCAL_CHn[23:16] bit 23 bit 16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OFFCAL_CHn[15:8] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OFFCAL_CHn[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-0 x = Bit is unknown OFFCAL_CHn[23:0]: Corresponding Channel CHn Digital Offset Calibration Value bits This register is simply added to the output code of the channel, bit-by-bit. This register is a 24-bit two’s complement MSB first coding register. CHn Output Code = OFFCAL_CHn + ADC CHn Output Code. This register is a Don’t Care if EN_OFFCAL = 0 (offset calibration disabled), but its value is not cleared by the EN_OFFCAL bit.  2013-2020 Microchip Technology Inc. DS20005227C-page 69 MCP3913 REGISTER 8-10: R/W-0 GAINCAL_CHn REGISTERS R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GAINCAL_CHn[23:16] bit 23 bit 16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GAINCAL_CHn[15:8] bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GAINCAL_CHn[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-0 x = Bit is unknown GAINCAL_CHn: Corresponding Channel CHn Digital Gain Error Calibration Value bits This register is a 24-bit signed MSB first coding with a range of -1x to +0.9999999x (from 0x800000 to 0x7FFFFF). The gain calibration adds 1x to this register and multiplies it to the output code of the channel, bit-by-bit, after offset calibration. The range of the gain calibration is thus from 0x to 1.9999999x (from 0x800000 to 0x7FFFFF). The LSB corresponds to a 2-23 increment in the multiplier. CHn Output Code = (GAINCAL_CHn + 1) * ADC CHn Output Code. This register is a Don’t Care if EN_GAINCAL = 0 (gain calibration disabled), but its value is not cleared by the EN_GAINCAL bit. DS20005227C-page 70  2013-2020 Microchip Technology Inc. MCP3913 8.10 SECURITY Register – Password and CRC-16 on Register Map Name Bits Address Cof. LOCK/CRC 24 0x1F R/W REGISTER 8-11: R/W-1 LOCK/CRC REGISTER R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 LOCK[7:0] bit 23 bit 16 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CRCREG[15:8] bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CRCREG[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23-16 LOCK[7:0]: Lock Code for Writable Part of Register Map bits LOCK[7:0] = Password = 0xA5 (default value): The entire register map is writable. The CRCREG[15:0] bits and the CRC interrupt are cleared. No CRC-16 checksum on register map is calculated. LOCK[7:0] Bits are Different than 0xA5: The only writable register is the LOCK/CRC register. All other registers will appear as undefined while in this mode. The CRCREG checksum is calculated continuously and can generate interrupts if the CRC interrupt EN_INT bit has been enabled. If a write to a register needs to be performed, the user needs to unlock the register map beforehand by writing 0xA5 to the LOCK[7:0] bits. bit 15-0 CRCREG[15:0]: CRC-16 Checksum Calculated with Writable Part of Register Map as a Message bits This is a read-only 16-bit code. This checksum is continuously recalculated and updated every 21 DMCLK periods. It is reset to its default value (0x0000) when LOCK[7:0] = 0xA5.  2013-2020 Microchip Technology Inc. DS20005227C-page 71 MCP3913 NOTES: DS20005227C-page 72  2013-2020 Microchip Technology Inc. MCP3913 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 28-Lead SSOP (5.30 mm) Example XXXXXXXXXXXX XXXXXXXXXXXX MCP3913A1 E/SS e3 YYWWNNN 1927256 40-Lead UQFN (5x5x0.5 mm) PIN 1 Example PIN 1 XXXXXXX XXXXXXX XXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: MCP3913 A1 E/MV e 1927256 3 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2013-2020 Microchip Technology Inc. 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