MCP47FEB12A1-E/ST

MCP47FEBXX 8-/10-/12-Bit Single/Dual Voltage Output Nonvolatile Digital-to-Analog Converters with I²C™ Interface Features • Operating Voltage Range: - 2.7V to 5.5V - Full Specifications - 1.8V to 2.7V - Reduced Device Specifications • Output Voltage Resolutions: - 8-bit: MCP47FEB0X (256 Steps) - 10-bit: MCP47FEB1X (1024 Steps) - 12-bit: MCP47FEB2X (4096 Steps) • Rail-to-Rail Output • Fast Settling Time of 6 µs (typical) • DAC Voltage Reference Source Options: - Device VDD - External VREF pin (buffered or unbuffered) - Internal Band Gap (1.22V typical) • Output Gain Options: - Unity (1x) - 2x (when not using internal VDD as voltage source) • Nonvolatile Memory (EEPROM): - User-programmed Power-on Reset (POR)/Brown-out Reset (BOR) output setting recall and device configuration bits - Auto Recall of Saved DAC register setting - Auto Recall of Saved Device Configuration (Voltage Reference, Gain, Power-Down) • Power-on/Brown-out Reset Protection • Nonvolatile Memory Write Protect (WP) Bit • Power-Down Modes: - Disconnects output buffer (High Impedance) - Selection of VOUT pull-down resistors (100 k or 1 k) • Low Power Consumption: - Normal operation: VDD, VI > VPP on HV pins) .......................................................................... ±20 mA Output clamp current, IOK (VO < 0 or VO > VDD)...................................................................................................±20 mA Maximum current out of VSS pin (Single) ..........................................................................................................50 mA (Dual)...........................................................................................................100 mA Maximum current into VDD pin (Single) ..........................................................................................................50 mA (Dual)...........................................................................................................100 mA Maximum current sourced by the VOUT pin ............................................................................................................20 mA Maximum current sunk by the VOUT pin..................................................................................................................20 mA Maximum current sunk by the VREF pin .................................................................................................................125 µA Maximum input current source/sunk by SDA, SCL pins ..........................................................................................2 mA Maximum output current sunk by SDA Output pin .................................................................................................25 mA Total power dissipation (1) ....................................................................................................................................400 mW Package power dissipation (TA = +50°C, TJ = +150°C) TSSOP-8...................................................................................................................................................700 mW ESD protection on all pins ±4 kV (HBM) ±400V (MM) ±2 kV (CDM) Latch-Up (per JEDEC JESD78A) @ +125°C ..................................................................................................... ±100 mA Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature with power applied ...............................................................................................-55°C to +125°C Soldering temperature of leads (10 seconds) ....................................................................................................... +300°C Maximum Junction Temperature (TJ) .................................................................................................................... +150°C † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD -  IOH} +  {(VDD – VOH) x IOH} + (VOL x IOL)  2015 Microchip Technology Inc. DS20005375A-page 5 MCP47FEBXX DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  TA  +125°C (Extended) All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V, Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF. Typical specifications represent values for VDD = 5.5V, TA = +25°C. DC Characteristics Parameters Supply Voltage Sym. Min. Typ. Max. Units Conditions VDD 2.7 — 5.5 V 1.8 — 2.7 V DAC operation (reduced analog specifications) and Serial Interface — — 1.7 V RAM retention voltage (VRAM) < VPOR VDD voltages greater than VPOR/BOR limit ensure that device is out of reset. VDD Voltage (rising) to ensure device Power-on Reset VPOR/BOR VDD Rise Rate to ensure Power-on Reset VDDRR High-Voltage Commands Voltage Range (HVC pin) VHV VSS — 12.5 V The HVC pin will be at one of three input levels (VIL, VIH or VIHH) (1) High-Voltage Input Entry Voltage VIHHEN 9.0 — — V Threshold for Entry into WiperLock™ Technology High-Voltage Input Exit Voltage VIHHEX — — VDD + 0.8V V (Note 1) Power-on Reset to Output-Driven Delay TPORD — 25 50 µs VDD rising, VDD > VPOR (Note 3) V/ms Note 1 This parameter is ensured by design. Note 3 POR/BOR voltage trip point is not slope dependent. Hysteresis implemented with time delay. DS20005375A-page 6  2015 Microchip Technology Inc. MCP47FEBXX DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  TA  +125°C (Extended) All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V, Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF. Typical specifications represent values for VDD = 5.5V, TA = +25°C. DC Characteristics Parameters Supply Current Power-Down Current Sym. IDD IDDP Min. Typ. Max. Units Conditions — — 500 µA Single — — 700 µA Dual Serial Interface Active (Not High-Voltage Command), VRxB:VRxA = ‘01’ (6), VOUT is unloaded, VDD = 5.5V volatile DAC Register = 000h I2C™: FSCL = 3.4 MHz — — 400 µA Single — — 550 µA Dual — — 180 µA Single — — 380 µA Dual — — 180 µA Single — — 380 µA Dual — — 1.9 mA EE Write Current VREF = VDD = 5.5V (after write, Serial Interface is Inactive), write all 0’s to nonvolatile DAC 0 (address 10h), VOUT pins are unloaded. Serial Interface Active (2) (Not High-Voltage Command), VRxB:VRxA = ‘10’ (4), VOUT is unloaded, VREF = VDD = 5.5V volatile DAC Register = 000h I2C: FSCL = 3.4 MHz Serial Interface Inactive (2) (Not High-Voltage Command), VRxB:VRxA = ‘00’, SCL = SDA = VSS, VOUT is unloaded, volatile DAC Register = 000h Serial Interface Inactive (2) (Not High-Voltage Command), VRxB:VRxA = ‘11’, VREF = VDD, SCL = SDA = VSS, VOUT is unloaded, volatile DAC Register = 000h — 145 180 µA Single — 260 400 µA Dual HVC = 12.5V (High-Voltage Command), Serial Interface Inactive VREF = VDD = 5.5V, LAT/HVC = VIHH, DAC registers = 000h, VOUT pins are unloaded. — 0.65 3.8 µA PDxB:PDxA = ‘01’ (5), VOUT not connected Note 2 This parameter is ensured by characterization. Note 4 Supply current is independent of current through the resistor ladder in mode VRxB:VRxA = ‘10’. Note 5 The PDxB:PDxA = ‘01’, ‘10’, and ‘11’ configurations should have the same current. Note 6 By design, this is worst-case current mode.  2015 Microchip Technology Inc. DS20005375A-page 7 MCP47FEBXX DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  TA  +125°C (Extended) All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V, Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF. Typical specifications represent values for VDD = 5.5V, TA = +25°C. DC Characteristics Parameters Sym. Min. Typ. Max. Units Resistor Ladder Resistance Resolution (# of Resistors and # of Taps) (see C.1 “Resolution”) Nominal VOUT Match (12) RL 100 140 180 k N |VOUT - VOUTMEAN| /VOUTMEAN 256 1024 4096 — — — 0.5 — 15 Taps Taps Taps 1.0 1.2 — Conditions 1.8V  VDD  5.5V, VREF  1.0V(7) 8-bit No Missing Codes 10-bit No Missing Codes 12-bit No Missing Codes % 2.7V  VDD  5.5V(2) % 1.8V(2) ppm/°C Code = Mid-scale (7Fh, 1FFh or 7FFh) VOUT/T VOUT Tempco (see C.19 “VOUT Temperature Coefficient”) VREF pin Input VREF VSS — VDD V 1.8V  VDD  5.5V(1) Voltage Range Note 1 This parameter is ensured by design. Note 2 This parameter is ensured by characterization. Note 7 Resistance is defined as the resistance between the VREF pin (mode VRxB:VRxA = ‘10’) to VSS pin. For dual-channel devices (MCP47FEBX2), this is the effective resistance of the each resistor ladder. The resistance measurement is of the two resistor ladders measured in parallel. Note 12 Variation of one output voltage to mean output voltage. DS20005375A-page 8  2015 Microchip Technology Inc. MCP47FEBXX DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  TA  +125°C (Extended) All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V, Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF. Typical specifications represent values for VDD = 5.5V, TA = +25°C. DC Characteristics Parameters Zero-Scale Error (see C.5 “Zero-Scale Error (EZS)”) (Code = 000h) Sym. Min. Typ. Max. Units EZS — — 0.75 LSb See Section 2.0 “Typical Performance Curves” (2) See Section 2.0 “Typical Performance Curves” (2) See Section 2.0 “Typical Performance Curves” (2) See Section 2.0 “Typical Performance Curves” (2) — — 3 LSb  2015 Microchip Technology Inc. 8-bit VRxB:VRxA = ‘11’, Gx = ‘0’, VREF = VDD, No Load VRxB:VRxA = ‘00’, Gx = ‘0’, VDD = 5.5V, No Load VDD = 1.8V, VREF = 1.0V VRxB:VRxA = ‘10’, Gx = ‘0’. No Load VDD = 1.8V, VREF = 1.0V VRxB:VRxA = ‘11’, Gx = ‘0’. No Load VRxB:VRxA = ‘01’, Gx = ‘0’, No Load 10-bit VRxB:VRxA = ‘11’, Gx = ‘0’, VREF = VDD, No Load VRxB:VRxA = ‘00’, Gx = ‘0’, VDD = 5.5V, No Load VDD = 1.8V, VREF = 1.0V VRxB:VRxA = ‘10’, Gx = ‘0’. No Load VDD = 1.8V, VREF = 1.0V VRxB:VRxA = ‘11’, Gx = ‘0’. No Load VRxB:VRxA = ‘01’, Gx = ‘0’, No Load 12-bit VRxB:VRxA = ‘11’, Gx = ‘0’, VREF = VDD, No Load VRxB:VRxA = ‘00’, Gx = ‘0’, VDD = 5.5V, No Load VDD = 1.8V, VREF = 1.0V VRxB:VRxA = ‘10’, Gx = ‘0’. No Load VDD = 1.8V, VREF = 1.0V VRxB:VRxA = ‘11’, Gx = ‘0’. No Load VRxB:VRxA = ‘01’, Gx = ‘0’, No Load LSb LSb LSb LSb See Section 2.0 “Typical Performance Curves” (2) See Section 2.0 “Typical Performance Curves” (2) See Section 2.0 “Typical Performance Curves” (2) See Section 2.0 “Typical Performance Curves” (2) — — 12 LSb See Section 2.0 “Typical Performance Curves” (2) See Section 2.0 “Typical Performance Curves” (2) See Section 2.0 “Typical Performance Curves” (2) See Section 2.0 “Typical Performance Curves” (2) -15 ±1.5 +15 LSb Offset Error EOS (see C.7 “Offset Error (EOS)”) Offset Voltage VOSTC — ±10 — Temperature Coefficient Note 2 This parameter is ensured by characterization. Conditions LSb LSb LSb LSb LSb LSb LSb mV VRxB:VRxA = ‘00’, Gx = ‘0’, No Load µV/°C DS20005375A-page 9 MCP47FEBXX DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  TA  +125°C (Extended) DC Characteristics All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V, Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF. Typical specifications represent values for VDD = 5.5V, TA = +25°C. Parameters Sym. Min. Typ. Max. Units Full-Scale Error (see C.4 “Full-Scale Error (EFS)”) EFS — — 4.5 LSb See Section 2.0 “Typical Performance Curves” (2) See Section 2.0 “Typical Performance Curves” (2) See Section 2.0 “Typical Performance Curves” (2) — — 18 LSb Note 2 8-bit LSb LSb LSb See Section 2.0 “Typical Performance Curves” (2) See Section 2.0 “Typical Performance Curves” (2) See Section 2.0 “Typical Performance Curves” (2) — — 70 LSb See Section 2.0 “Typical Performance Curves” (2) See Section 2.0 “Typical Performance Curves” (2) See Section 2.0 “Typical Performance Curves” (2) This parameter is ensured by characterization. LSb DS20005375A-page 10 Conditions 10-bit LSb LSb LSb LSb LSb 12-bit Code = FFh, VRxB:VRxA = ‘11’, Gx = ‘0’, VREF = 2.048V, No Load Code = FFh, VRxB:VRxA = ‘10’, Gx = ‘0’, VREF = 2.048V, No Load Code = FFh, VRxB:VRxA = ‘01’, Gx = ‘0’, VREF = 2.048V, No Load Code = FFh, VRxB:VRxA = ‘00’, No Load Code = 3FFh, VRxB:VRxA = ‘11’, Gx = ‘0’, VREF = 2.048V, No Load Code = 3FFh, VRxB:VRxA = ‘10’, Gx = ‘0’, VREF = 2.048V, No Load Code = 3FFh, VRxB:VRxA = ‘01’, Gx = ‘0’, VREF = 2.048V, No Load Code = 3FFh, VRxB:VRxA = ‘00’, No Load Code = FFFh, VRxB:VRxA = ‘11’, Gx = ‘0’, VREF = 2.048V, No Load Code = FFFh, VRxB:VRxA = ‘10’, Gx = ‘0’, VREF = 2.048V, No Load Code = FFFh, VRxB:VRxA = ‘01’, Gx = ‘0’, VREF = 2.048V, No Load Code = FFFh, VRxB:VRxA = ‘00’, No Load  2015 Microchip Technology Inc. MCP47FEBXX DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  TA  +125°C (Extended) All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V, Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF. Typical specifications represent values for VDD = 5.5V, TA = +25°C. DC Characteristics Parameters Gain Error (see C.9 “Gain Error (EG)”)(9) Sym. Min. Typ. Max. EG -1.0 ±0.1 +1.0 -1.0 ±0.1 +1.0 -1.0 ±0.1 +1.0 — -3 — -2.5 — +0.5 Gain-Error Drift (see C.10 G/°C “Gain-Error Drift (EGD)”) ET Total Unadjusted Error (see C.6 “Total Unadjusted Error (ET)”)(2) See Section 2.0 “Typical Performance Curves” -10.0 — +2.0 See Section 2.0 “Typical Performance Curves” -40.0 — +8.0 See Section 2.0 “Typical Performance Curves” Note 2 Note 9 Units Conditions % of 8-bit FSR % of 10-bit FSR % of 12-bit FSR ppm/°C LSb 8-bit LSb LSb 10-bit LSb LSb LSb 12-bit Code = 250, No Load VRxB:VRxA = ‘00’, Gx = ‘0’ Code = 1000, No Load VRxB:VRxA = ‘00’, Gx = ‘0’ Code = 4000, No Load VRxB:VRxA = ‘00’, Gx = ‘0’ VRxB:VRxA = ‘00’. No Load. VDD = 1.8V, VRxB:VRxA = ‘11’, Gx = ‘0’, VREF = 1.0V, No Load. VRxB:VRxA = ‘00’. No Load. VDD = 1.8V, VRxB:VRxA = ‘11’, Gx = ‘0’, VREF = 1.0V, No Load. VRxB:VRxA = ‘00’. No Load. VDD = 1.8V, VRxB:VRxA = ‘11’, Gx = ‘0’, VREF = 1.0V, No Load. This parameter is ensured by characterization. This gain error does not include offset error.  2015 Microchip Technology Inc. DS20005375A-page 11 MCP47FEBXX DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  TA  +125°C (Extended) All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V, Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF. Typical specifications represent values for VDD = 5.5V, TA = +25°C. DC Characteristics Parameters Sym. Min. Typ. Max. Units Integral Nonlinearity (see C.11 “Integral Nonlinearity (INL)”)(8, 11) INL -0.5 ±0.1 +0.5 LSb See Section 2.0 “Typical Performance Curves”(2) See Section 2.0 “Typical Performance Curves”(2) See Section 2.0 “Typical Performance Curves”(2) See Section 2.0 “Typical Performance Curves”(2) -1.5 ±0.4 +1.5 LSb See Section 2.0 “Typical Performance Curves”(2) See Section 2.0 “Typical Performance Curves”(2) See Section 2.0 “Typical Performance Curves”(2) See Section 2.0 “Typical Performance Curves”(2) -6 ±1.5 +6 LSb Note 2 Note 8 Note 11 LSb LSb LSb LSb LSb LSb LSb LSb Conditions 8-bit VRxB:VRxA = ‘10’ (codes: 6 to 250), VDD = VREF = 5.5V. VRxB:VRxA = ‘00’, ‘01’, ‘11’. VRxB:VRxA = ‘01’, VDD = 5.5V, Gx = ‘1’. VRxB:VRxA = ‘10’, ‘11’, VREF = 1.0V, Gx = ‘1’. VDD = 1.8V, VREF = 1.0V 10-bit VRxB:VRxA = ‘10’ (codes: 25 to 1000), VDD = VREF = 5.5V. VRxB:VRxA = ‘00’, ‘01’, ‘11’. VRxB:VRxA = ‘01’, VDD = 5.5V, Gx = ‘1’. VRxB:VRxA = ‘10’, ‘11’, VREF = 1.0V, Gx = ‘1’. VDD = 1.8V, VREF = 1.0V. 12-bit VRxB:VRxA = ‘10’ (codes: 100 to 4000), VDD = VREF = 5.5V. VRxB:VRxA = ‘00’, ‘01’, ‘11’. See Section 2.0 “Typical LSb Performance Curves”(2) See Section 2.0 “Typical LSb VRxB:VRxA = ‘01’, Performance Curves”(2) VDD = 5.5V, Gx = ‘1’. See Section 2.0 “Typical LSb VRxB:VRxA = ‘10’, ‘11’, Performance Curves”(2) VREF = 1.0V, Gx = ‘1’. See Section 2.0 “Typical LSb VDD = 1.8V, VREF = 1.0V. Performance Curves”(2) This parameter is ensured by characterization. INL and DNL are measured at VOUT with VRL = VDD (VRxB:VRxA = ‘00’). Code Range dependent on resolution: 8-bit, codes 6 to 250; 10-bit, codes 25 to 1000; 12-bit, 100 to 4000. DS20005375A-page 12  2015 Microchip Technology Inc. MCP47FEBXX DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  TA  +125°C (Extended) All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V, Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF. Typical specifications represent values for VDD = 5.5V, TA = +25°C. DC Characteristics Parameters Differential Nonlinearity (see C.12 “Differential Nonlinearity (DNL)”)(8, 11) Sym. Min. Typ. Max. Units DNL -0.25 ±0.0125 +0.25 LSb See Section 2.0 “Typical Performance Curves” (2) See Section 2.0 “Typical Performance Curves” (2) See Section 2.0 “Typical Performance Curves” (2) See Section 2.0 “Typical Performance Curves” (2) -0.5 ±0.05 +0.5 LSb See Section 2.0 “Typical Performance Curves” (2) See Section 2.0 “Typical Performance Curves” (2) See Section 2.0 “Typical Performance Curves” (2) See Section 2.0 “Typical Performance Curves” (2) -1.0 ±0.2 +1.0 Note 2 Note 8 Note 11 LSb LSb LSb LSb LSb LSb LSb LSb LSb Conditions 8-bit VRxB:VRxA = ‘10’ (codes: 6 to 250), VDD = VREF = 5.5V. Char: VRxB:VRxA = ‘00’, ‘01’, ‘11’. Char: VRxB:VRxA = ‘01’, VDD = 5.5V, Gx = ‘1’. Char: VRxB:VRxA = ‘10’, ‘11’, VREF = 1.0V, Gx = ‘1’. VDD = 1.8V 10-bit VRxB:VRxA = ‘10’ (codes: 25 to 1000), VDD = VREF = 5.5V. Char: VRxB:VRxA = ‘00’, ‘01’, ‘11’. Char: VRxB:VRxA = ‘01’, VDD = 5.5V, Gx = ‘1’. Char: VRxB:VRxA = ‘10’, ‘11’, VREF = 1.0V, Gx = ‘1’. VDD = 1.8V 12-bit VRxB:VRxA = ‘10’ (codes: 100 to 4000), VDD = VREF = 5.5V. Char: VRxB:VRxA = ‘00’, ‘01’, ‘11’. See Section 2.0 “Typical LSb Performance Curves” (2) See Section 2.0 “Typical LSb Char: VRxB:VRxA = ‘01’, Performance Curves” (2) VDD = 5.5V, Gx = ‘1’. See Section 2.0 “Typical LSb Char: VRxB:VRxA = ‘10’, ‘11’, Performance Curves” (2) VREF = 1.0V, Gx = ‘1’. See Section 2.0 “Typical LSb VDD = 1.8V Performance Curves” (2) This parameter is ensured by characterization. INL and DNL are measured at VOUT with VRL = VDD (VRxB:VRxA = ‘00’). Code Range dependent on resolution: 8-bit, codes 6 to 250; 10-bit, codes 25 to 1000; 12-bit, 100 to 4000.  2015 Microchip Technology Inc. DS20005375A-page 13 MCP47FEBXX DC CHARACTERISTICS (CONTINUED) Standard Operating Conditions (unless otherwise specified) Operating Temperature –40°C  TA  +125°C (Extended) All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, VREF = +2.048V to VDD, VSS = 0V, Gx = ‘0’, RL = 5 k from VOUT to GND, CL = 100 pF. Typical specifications represent values for VDD = 5.5V, TA = +25°C. DC Characteristics Parameters Sym. Min. Typ. Max. Units -3 dB Bandwidth (see C.16 “-3 dB Bandwidth”) BW — 86.5 — kHz — 67.7 — kHz VOUT(MIN) — 0.01 — VOUT(MAX) — — PM — VDD – 0.04 66 — SR ISC — 3 0.44 9 — 14 VBG VBGTC 1.18 — 1.22 15 1.26 — V ppm/°C 2.0 2.2 — — 5.5 5.5 V V VREF pin voltage stable VOUT output linear VSS VSS — — — — 1 -64 VDD – 0.04 VDD — — V V pF dB VRxB:VRxA = ‘11’ (buffered mode) VRxB:VRxA = ‘10’ (unbuffered mode) VRxB:VRxA = ‘10’ (unbuffered mode) VREF = 2.048V ± 0.1V, VRxB:VRxA = ‘10’, Gx = ‘0’, Frequency = 1 kHz Output Amplifier Minimum Output Voltage Maximum Output Voltage Phase Margin Slew Rate (10) Short-Circuit Current Internal Band Gap Band Gap Voltage Band Gap Voltage Temperature Coefficient Operating Range (VDD) External Reference (VREF) Input Range (1) VREF Input Capacitance Total Harmonic Distortion (1) CREF THD Conditions VREF = 2.048V ± 0.1V, VRxB:VRxA = ‘10’, Gx = ‘0’ VREF = 2.048V ± 0.1V, VRxB:VRxA = ‘10’, Gx = ‘1’ 1.8V  VDD  5.5V, Output Amplifier’s minimum drive V 1.8V  VDD  5.5V, Output Amplifier’s maximum drive Degree CL = 400 pF, RL =  (°) V/µs RL = 5 k mA DAC code = Full Scale V Dynamic Performance Major Code — 45 — nV-s 1 LSb change around major carry Transition Glitch (see (7FFh to 800h) C.14 “Major-Code Transition Glitch”) Digital Feedthrough — VPOR VOUT driven to VOUT disabled Power-Down Output Disable Time Delay TPDD — 10.5 — µs PDxB:PDxA = ‘11’, ‘10’, or ‘01’ -> “00” started from falling edge of the SCL at the end of the 8th clock cycle. Volatile DAC Register = FFh, VOUT = 10 mV. VOUT not connected. Power-Down Output Enable Time Delay TPDE — 1 — µs PDxB:PDxA = “00”  ‘11’, ‘10’, or ‘01’ started from falling edge of the SCL at the end of the 8th clock cycle. VOUT = VOUT - 10 mV. VOUT not connected.  2015 Microchip Technology Inc. Max. Units Conditions DS20005375A-page 19 MCP47FEBXX SCL 91 90 93 92 SDA Start Condition 96 94 95 ACK/ACK Pulse Stop Condition 96 LAT I2C™ Bus Start/Stop Bits Timing Waveforms. FIGURE 1-4: VIH SCL 93 91 90 92 111 SDA VIL Start Condition FIGURE 1-5: DS20005375A-page 20 Stop Condition I2C™ Bus Start/Stop Bits Timing Waveforms.  2015 Microchip Technology Inc. MCP47FEBXX I2C BUS START/STOP BITS AND LAT REQUIREMENTS TABLE 1-3: I2C™ AC Characteristics Param. Symbol No. Standard Operating Conditions (unless otherwise specified) Operating Temperature –40C  TA  +125C (Extended) Operating Voltage range is described in DC Characteristics Characteristic 90 91 92 93 Cb TSU:STA THD:STA TSU:STO THD:STO Max. Units 0 100 kHz Cb = 400 pF, 1.8V - 5.5V(2) Fast Mode 0 400 kHz Cb = 400 pF, 2.7V - 5.5V High-Speed 1.7 0 1.7 MHz Cb = 400 pF, 4.5V - 5.5V Cb = 100 pF, 4.5V - 5.5V Standard Mode FSCL D102 Min. Bus Capacitive Loading Start Condition Setup Time (Only relevant for repeated Start condition) Start Condition Hold time (After this period the first clock pulse is generated) Stop Condition Setup Time Stop Condition Hold Time High-Speed 3.4 0 3.4 MHz 100 kHz mode — 400 pF 400 kHz mode — 400 pF 1.7 MHz mode — 400 pF 3.4 MHz mode — 100 pF 100 kHz mode 4700 — ns 400 kHz mode 600 — ns 1.7 MHz mode 160 — ns 3.4 MHz mode 160 — ns 100 kHz mode 4000 — ns 400 kHz mode 600 — ns 1.7 MHz mode 160 — ns 3.4 MHz mode 160 — ns 100 kHz mode 4000 — ns 400 kHz mode 600 — ns 1.7 MHz mode 160 — ns 3.4 MHz mode 160 — ns 100 kHz mode 4000 — ns 400 kHz mode 600 — ns 1.7 MHz mode 160 — ns 3.4 MHz mode Conditions Note 2 Note 2 Note 2 Note 2 160 — ns 94 TLATSU LAT ↑ to SCL↑ (write data ACK bit) Setup Time 10 — ns Write Data delayed(3) 95 TLATHD SCL ↑ to LAT↑ (write data ACK bit) Hold Time 250 — ns Write Data delayed(3) 96 TLAT LAT High or Low Time 50 — ns 97 THVCSU HVC High to SCL High (of Start condition) - Setup Time 25 — µs High-Voltage Commands 98 THVCHD SCL Low (of Stop condition) to HVC Low - Hold Time 25 — µs High-Voltage Commands Note 2 Not Tested. This parameter ensured by characterization. Note 3 The transition of the LAT signal between 10 ns before the rising edge (Spec 94) and 250 ns after the rising edge (Spec 95) of the SCL signal is indeterminate whether the change in VOUT is delayed or not.  2015 Microchip Technology Inc. DS20005375A-page 21 MCP47FEBXX 103 102 100 101 SCL 90 106 91 92 107 SDA In 110 109 109 SDA Out I2C™ Bus Timing Waveforms. FIGURE 1-6: TABLE 1-4: I2C BUS REQUIREMENTS (SLAVE MODE) I2C™ AC Characteristics Param. No. Sym. 100 THIGH 101 102A (2) 102B(2) Note 2 TLOW TRSCL TRSDA Standard Operating Conditions (unless otherwise specified) Operating Temperature –40C  TA  +125C (Extended) Operating Voltage range is described in DC Characteristics Characteristic Clock high time Clock low time SCL rise time SDA rise time Min. Max. Units Conditions 100 kHz mode 4000 — ns 1.8V-5.5V(2) 400 kHz mode 600 — ns 2.7V-5.5V 1.7 MHz mode 120 — ns 4.5V-5.5V 3.4 MHz mode 60 — ns 4.5V-5.5V 100 kHz mode 4700 — ns 1.8V-5.5V(2) 400 kHz mode 1300 — ns 2.7V-5.5V 1.7 MHz mode 320 — ns 4.5V-5.5V 3.4 MHz mode 160 — ns 4.5V-5.5V 100 kHz mode — 1000 ns Cb is specified to be from 10 to 400 pF (100 pF maximum for 3.4 MHz mode) 400 kHz mode 20 + 0.1Cb 300 ns 1.7 MHz mode 20 80 ns 1.7 MHz mode 20 160 ns 3.4 MHz mode 10 40 ns 3.4 MHz mode 10 80 ns After a Repeated Start condition or an Acknowledge bit Cb is specified to be from 10 to 400 pF (100 pF maximum for 3.4 MHz mode) 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1Cb 300 ns 1.7 MHz mode 20 160 ns 3.4 MHz mode 10 80 ns After a Repeated Start condition or an Acknowledge bit Not Tested. This parameter ensured by characterization. DS20005375A-page 22  2015 Microchip Technology Inc. MCP47FEBXX TABLE 1-5: I2C BUS REQUIREMENTS (SLAVE MODE) (CONTINUED) I2C™ AC Characteristics Param. No. Sym. 103A(2) TFSCL 103B (2) 106 107 109 TFSDA THD:DAT TSU:DAT TAA Standard Operating Conditions (unless otherwise specified) Operating Temperature –40C  TA  +125C (Extended) Operating Voltage range is described in DC Characteristics Characteristic SCL fall time SDA fall time Data input hold time Data input setup time Output valid from clock 111 TBUF TSP Bus free time Input filter spike suppression (SDA and SCL) Max. Units 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1Cb 300 ns 1.7 MHz mode 20 80 ns 3.4 MHz mode 10 40 ns 100 kHz mode — 300 ns Conditions Cb is specified to be from 10 to 400 pF (100 pF maximum for 3.4 MHz mode)(4) Cb is specified to be from 10 to 400 pF (100 pF maximum for 3.4 MHz mode)(4) 400 kHz mode 20 + 0.1Cb 300 ns 1.7 MHz mode 20 160 ns 3.4 MHz mode 10 80 ns 100 kHz mode 0 — ns 1.8V-5.5V(2, 5) 400 kHz mode 0 — ns 2.7V-5.5V(5) 1.7 MHz mode 0 — ns 4.5V-5.5V(5) 3.4 MHz mode 0 — ns 4.5V-5.5V(5) 100 kHz mode 250 — ns Note 2, Note 6 Note 6 400 kHz mode 100 — ns 1.7 MHz mode 10 — ns 3.4 MHz mode 10 — ns 100 kHz mode — 3450 ns 400 kHz mode — 900 ns Note 7 1.7 MHz mode — 150 ns Cb = 100 pF(7, 8) — 310 ns Cb = 400 pF(2, 7) — 150 ns Cb = 100 pF(7) Time the bus must be free before a new transmission can start(2) 3.4 MHz mode 110 Min. Note 2, Note 7 100 kHz mode 4700 — ns 400 kHz mode 1300 — ns 1.7 MHz mode N.A. — ns 3.4 MHz mode N.A. — ns 100 kHz mode — 50 ns 400 kHz mode — 50 ns 1.7 MHz mode — 10 ns Spike suppression 3.4 MHz mode — 10 ns Spike suppression NXP Spec states N.A.(2) Note 2 Not Tested. This parameter ensured by characterization. Note 4 Use Cb in pF for the calculations. Note 5 A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. Note 6 A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tSU;DAT  250 ns must then be met. This will automatically be the case if the device does not stretch the Low period of the SCL signal. If such a device does stretch the Low period of the SCL signal, it must output the next data bit to the SDA line TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. Note 7 As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. Note 8 Ensured by the TAA 3.4 MHz specification test.  2015 Microchip Technology Inc. DS20005375A-page 23 MCP47FEBXX Timing Table Notes: 1. 2. 3. 4. 5. 6. 7. 8. Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12- bit device). Not Tested. This parameter ensured by characterization. The transition of the LAT signal between 10 ns before the rising edge (Spec 94) and 250 ns after the rising edge (Spec 95) of the SCL signal is indeterminate whether the change in VOUT is delayed or not. Use Cb in pF for the calculations. A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement tSU;DAT  250 ns must then be met. This will automatically be the case if the device does not stretch the Low period of the SCL signal. If such a device does stretch the Low period of the SCL signal, it must output the next data bit to the SDA line TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. Ensured by the TAA 3.4 MHz specification test. DS20005375A-page 24  2015 Microchip Technology Inc. MCP47FEBXX TEMPERATURE SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND. Parameters Symbol Min. Typical Max. Units Specified Temperature Range TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C JA — 139 — °C/W Conditions Temperature Ranges Note 1 Thermal Package Resistances Thermal Resistance, 8L-TSSOP Note 1: The MCP47FEBXX devices operate over this extended temperature range, but with reduced performance. Operation in this range must not cause TJ to exceed the Maximum Junction Temperature of +150°C.  2015 Microchip Technology Inc. DS20005375A-page 25 MCP47FEBXX NOTES: DS20005375A-page 26  2015 Microchip Technology Inc. MCP47FEBXX 2.0 Note: TYPICAL PERFORMANCE CURVES The device Performance Curves are available in a separate document. This is done to keep the file size of this PDF document less than the 10 MB file attachment limit of many mail servers. The MCP47FXBXX Performance Curves document is literature number DS20005378, and can be found on the Microchip website. Look at the MCP47FEBXX product page under “Documentation and Software”, in the Data Sheets category.  2015 Microchip Technology Inc. DS20005375A-page 27 MCP47FEBXX NOTES: DS20005375A-page 28  2015 Microchip Technology Inc. MCP47FEBXX 3.0 PIN DESCRIPTIONS Overviews of the pin functions are provided in Sections 3.1 “Positive Power Supply Input (VDD)” through Section 3.8 “I2C - Serial Data Pin (SDA)”. The descriptions of the pins for the single-DAC output device are listed in Table 3-1, and descriptions for the dual-DAC output device are listed in Table 3-2. TABLE 3-1: MCP47FEBX1 (SINGLE-DAC) PINOUT DESCRIPTION Pin TSSOP-8L Symbol I/O Buffer Type Standard Function 1 VDD — P Supply Voltage Pin 2 VREF0 A Analog Voltage Reference Input Pin 3 VOUT0 A Analog Buffered analog voltage output pin 4 NC — — Not Internally Connected 5 VSS — P Ground reference pin for all circuitries on the device 6 LAT0/HVC I HV ST 7 SCL I ST I2C™ Serial Clock Pin 8 SDA I/O ST I2C Serial Data Pin Legend: TABLE 3-2: A = Analog I = Input DAC Register Latch/High-Voltage Command Pin. Latch Pin allows the value in the Serial Shift Register to transfer to the volatile DAC register. High-Voltage Command allows User Configuration bits to be written. ST = Schmitt Trigger O = Output I/O = Input/Output P = Power MCP47FEBX2 (DUAL-DAC) PINOUT DESCRIPTION Pin TSSOP-8 Symbol I/O Buffer Type Standard Function 1 VDD — P Supply Voltage Pin 2 VREF A Analog Voltage Reference Input Pin (for DAC0 or DAC0 and DAC1) 3 VOUT0 A Analog Buffered analog voltage output 0 pin (DAC0 output) 4 VOUT1 A Analog Buffered analog voltage output 1 pin (DAC1 output) 5 VSS — P Ground reference pin for all circuitries on the device 6 LAT/HVC I HV ST 7 SCL I ST I2C™ Serial Clock Pin 8 SDA I/O ST I2C Serial Data Pin Legend: A = Analog I = Input  2015 Microchip Technology Inc. DAC Register Latch/High-Voltage Command Pin. Latch Pin allows the value in the Serial Shift Register to transfer to the volatile DAC register(s) (for DAC0 or DAC0 and DAC1). High-Voltage Command allows User Configuration bits to be written. ST = Schmitt Trigger O = Output I/O = Input/Output P = Power DS20005375A-page 29 MCP47FEBXX 3.1 Positive Power Supply Input (VDD) VDD is the positive supply voltage input pin. The input supply voltage is relative to VSS. The power supply at the VDD pin should be as clean as possible for a good DAC performance. It is recommended to use an appropriate bypass capacitor of about 0.1 µF (ceramic) to ground. An additional 10 µF capacitor (tantalum) in parallel is also recommended to further attenuate noise present in application boards. 3.2 Voltage Reference Pin (VREF) The VREF pin is either an input or an output. When the DAC’s voltage reference is configured as the VREF pin, the pin is an input. When the DAC’s voltage reference is configured as the internal band gap, the pin is an output. When the DAC’s voltage reference is configured as the VREF pin, there are two options for this voltage input: VREF pin voltage buffered or unbuffered. The buffered option is offered in cases where the external reference voltage does not have sufficient current capability to not drop it’s voltage when connected to the internal resistor ladder circuit. When the DAC’s voltage reference is configured as the device VDD, the VREF pin is disconnected from the internal circuit. When the DAC’s voltage reference is configured as the internal band gap, the VREF pin’s drive capability is minimal, so the output signal should be buffered. See Section 5.2 “Voltage Reference Selection” and Register 4-2 for more details on the Configuration bits. 3.3 Analog Output Voltage Pin (VOUT) VOUT is the DAC analog voltage output pin. The DAC output has an output amplifier. The DAC output range is dependent on the selection of the voltage reference source (and potential Output Gain selection). These are: • Device VDD - The full-scale range of the DAC output is from VSS to approximately VDD. • VREF pin - The full-scale range of the DAC output is from VSS to G  VRL, where G is the gain selection option (1x or 2x). • Internal Band Gap - The full-scale range of the DAC output is from VSS to G  (2  VBG), where G is the gain selection option (1x or 2x). 3.5 Ground (VSS) The VSS pin is the device ground reference. The user must connect the VSS pin to a ground plane through a low-impedance connection. If an analog ground path is available in the application PCB (printed circuit board), it is highly recommended that the VSS pin be tied to the analog ground path or isolated within an analog ground plane of the circuit board. 3.6 Latch Pin (LAT)/High-Voltage Command (HVC) The LAT pin is used to force the transfer of the DAC register’s shift register to the DAC output register. This allows DAC outputs to be updated at the same time. The update of the VRxB:VRxA, PDxB:PDxA, Gx bits are also controlled by the LAT pin state. The HVC pin allows the device’s nonvolatile user configuration bits to be programmed when the HVC pin is greater than the VIHH entry voltage. 3.7 I2C - Serial Clock Pin (SCL) The SCL pin is the serial clock pin of the I2C interface. The MCP47FEBXX’s I2C interface only acts as a slave and the SCL pin accepts only external serial clocks. The input data from the Master device is shifted into the SDA pin on the rising edges of the SCL clock and output from the device occurs at the falling edges of the SCL clock. The SCL pin is an open-drain N-channel driver. Therefore, it needs an external pull-up resistor from the VDD line to the SCL pin. Refer to Section 6.0 “I2C Serial Interface Module” for more details of I2C Serial Interface communication. 3.8 I2C - Serial Data Pin (SDA) The SDA pin is the serial data pin of the I2C interface. The SDA pin is used to write or read the DAC registers and Configuration bits. The SDA pin is an open-drain N-channel driver. Therefore, it needs an external pull-up resistor from the VDD line to the SDA pin. Except for Start and Stop conditions, the data on the SDA pin must be stable during the high period of the clock. The high or low state of the SDA pin can only change when the clock signal on the SCL pin is low. Refer to Section 6.0 “I2C Serial Interface Module” for more details of I2C Serial Interface communication. In Normal mode, the DC impedance of the output pin is about 1. In Power-Down mode, the output pin is internally connected to a known pull-down resistor of 1 k, 100 k, or open. The Power-Down selection bits settings are shown Register 4-3 (Table 5-5). 3.4 No Connect (NC) The NC pin is not connected to the device. DS20005375A-page 30  2015 Microchip Technology Inc. MCP47FEBXX 4.0 GENERAL DESCRIPTION The MCP47FEBX1 (MCP47FEB01, MCP47FEB11, and MCP47FEB21) devices are single-channel voltage output devices. MCP47FEBX2 (MCP47FEB02, MCP47FEB12, and MCP47FEB22) devices are dualchannel voltage output devices. These devices are offered with 8-bit (MCP47FEB0X), 10-bit (MCP47FEB1X) and 12-bit (MCP47FEB2X) resolution and include nonvolatile memory (EEPROM), an I2C serial interface and a write latch (LAT) pin to control the update of the written DAC value to the DAC output pin. The devices use a resistor ladder architecture. The resistor ladder DAC is driven from a softwareselectable voltage reference source. The source can be either the device’s internal VDD, an external VREF pin voltage (buffered or unbuffered) or an internal band gap voltage source. The DAC output is buffered with a low power and precision output amplifier (op amp). This output amplifier provides a rail-to-rail output with low offset voltage and low noise. The gain (1x or 2x) of the output buffer is software configurable. 4.1 Power-on Reset/Brown-out Reset (POR/BOR) The internal Power-on Reset (POR)/Brown-out Reset (BOR) circuit monitors the power supply voltage (VDD) during operation. This circuit ensures correct device start-up at system power-up and power-down events. The device’s RAM retention voltage (VRAM) is lower than the POR/BOR voltage trip point (VPOR/VBOR). The maximum VPOR/VBOR voltage is less than 1.8V. POR occurs as the voltage is rising (typically from 0V), while BOR occurs as the voltage is falling (typically from VDD(MIN) or higher). The POR and BOR trip points are at the same voltage, and the condition is determined by whether the VDD voltage is rising or falling (see Figure 4-1). What occurs is different depending on if the reset is a POR or BOR reset. the electrical When VPOR/VBOR < VDD < 2.7V, performance may not meet the data sheet specifications. In this region, the device is capable of reading and writing to its EEPROM and reading and writing to its volatile memory if the proper serial command is executed. This device also has user-programmable nonvolatile memory (EEPROM), which allows the user to save the desired POR/BOR value of the DAC register and device configuration bits. High Voltage lock bits can be used to ensure that the devices output settings are not accidentally modified. The devices operates from a single supply voltage. This voltage is specified from 2.7V to 5.5V for full specified operation, and from 1.8V to 5.5V for digital operation. The device operates between 1.8V and 2.7V, but some device parameters are not specified. The main functional blocks are: • • • • • • Power-on Reset/Brown-out Reset (POR/BOR) Device Memory Resistor Ladder Output Buffer/VOUT Operation Internal Band Gap (Voltage Reference) I2C Serial Interface Module  2015 Microchip Technology Inc. DS20005375A-page 31 MCP47FEBXX 4.1.1 POWER-ON RESET 4.1.2 The Power-on Reset is the case where the device VDD is having power applied to it from the VSS voltage level. As the device powers-up, the VOUT pin will float to an unknown value. When the device’s VDD is above the transistor threshold voltage of the device, the output will start being pulled low. After the VDD is above the POR/BOR trip point (VBOR/VPOR), the resistor network’s wiper will be loaded with the POR value (mid-scale). The volatile memory determines the analog output (VOUT) pin voltage. After the device is powered-up, the user can update the device memory. When the rising VDD voltage crosses the VPOR trip point, the following occurs: • Nonvolatile DAC register value latched into volatile DAC register • Nonvolatile Configuration bit values latched into volatile Configuration bits • POR Status bit is set (‘1’) • The Reset Delay Timer (tPORD) starts; when the reset delay timer (tPORD) times out, the I2C serial interface is operational. During this delay time, the I2C interface will not accept commands. • The Device Memory Address pointer is forced to 00h. BROWN-OUT RESET The Brown-out Reset occurs when a device had power applied to it, and that power (voltage) drops below the specified range. When the falling VDD voltage crosses the VPOR trip point (BOR event), the following occurs: • Serial Interface is disabled • EEPROM Writes are disabled • Device is forced into a power-down state (PDxB:PDxA = ‘11’). Analog circuitry is turned off. • Volatile DAC Register is forced to 000h • Volatile configuration bits VRxB:VRxA and Gx are forced to ‘0’ If the VDD voltage decreases below the VRAM voltage, all volatile memory may become corrupted. As the voltage recovers above the VPOR/VBOR voltage see Section 4.1.1 “Power-on Reset”. Serial commands not completed due to a brown-out condition may cause the memory location (volatile and nonvolatile) to become corrupted. Figure 4-1 illustrates the conditions for power-up and power-down events under typical conditions. The analog output (VOUT) state will be determined by the state of the volatile Configuration bits and the DAC register. This is called a Power-on Reset (event). Figure 4-1 illustrates the conditions for power-up and power-down events under typical conditions. Volatile memory POR starts Reset Delay Timer. retains data value When timer times out, I2C™ interface can operate (if VDD  VDD(MIN)) Volatile memory becomes corrupted VDD(MIN) TPORD (20 µs max.) VPOR VBOR VRAM Normal Operation Device in unknown state Device in POR state POR reset forced active FIGURE 4-1: DS20005375A-page 32 EEPROM data latched into volatile configuration bits and DAC register. POR status bit is set (‘1’) Below minimum operating voltage Device Device in in power unknown down state state BOR reset, volatile DAC Register = 000h volatile VRxB:VRxA = 00 volatile Gx = 0 volatile PDxB:PDxA = 11 Power-on Reset Operation.  2015 Microchip Technology Inc. MCP47FEBXX 4.2 Device Memory 4.2.2 User memory includes three types of memory: This memory can be grouped into two uses of nonvolatile memory. These are the DAC Output Value and Configuration registers: • Volatile Register Memory (RAM) • Nonvolatile Register Memory • Device Configuration Memory Each memory address is 16 bits wide. There are five nonvolatile user-control bits that do not reside in memory mapped register space (see Section 4.2.3 “Device Configuration Memory”). 4.2.1 VOLATILE REGISTER MEMORY (RAM) DAC0 and DAC1 Output Value Registers VREF Select Register Power-Down Configuration Register Gain and Status Register WiperLock Technology Status Register The device starts writing the EEPROM memory location at the completion of the serial interface command. For the I2C interface, this is the acknowledge pulse of the EEPROM write command. The volatile memory starts functioning when the device VDD is at (or above) the RAM retention voltage (VRAM). The volatile memory will be loaded with the default device values when the VDD rises across the VPOR/VBOR voltage trip point. Note: When the nonvolatile memory is written, the corresponding volatile memory is not modified. The nonvolatile DAC registers enables stand-alone operation of the device (without Microcontroller control) after being programmed to the desired value. MEMORY MAP (x16) Address CL0 10h Nonvolatile DAC0 Register DL0 CL1 11h Nonvolatile DAC1 Register DL1 — 12h Reserved — Reserved — 13h Reserved — Reserved — 14h Reserved — 05h Reserved — 15h Reserved — 06h Reserved — 16h Reserved — 07h Reserved — 17h Reserved — 08h VREF Register — 18h Nonvolatile VREF Register — Function 00h Volatile DAC0 Register 01h Volatile DAC1 Register 02h Reserved 03h 04h Config Bit (1) Config Bit (1) Address TABLE 4-1: • Nonvolatile DAC0 and DAC1 Output Value Registers • Nonvolatile VREF Select Register • Nonvolatile Power Down Configuration Register • Nonvolatile Gain and I2C Slave Address The nonvolatile memory starts functioning below the device’s VPOR/VBOR trip point and is loaded into the corresponding volatile registers whenever the device rises above the POR/BOR voltage trip point. There are up to six Volatile Memory locations: • • • • • NONVOLATILE REGISTER MEMORY Function 09h Power-Down Register — 19h Nonvolatile Power-Down Register 0Ah Gain and Status Register — 1Ah NV Gain and I2C™ 7-bits Slave Address — SALCK 0Bh WiperLock Technology Status Register — 1Bh Reserved — 0Ch Reserved — 1Ch Reserved — 0Dh Reserved — 1Dh Reserved — 0Eh Reserved — 1Eh Reserved — 0Fh Reserved — 1Fh Reserved — Volatile Memory address range Nonvolatile Memory address range Note 1:Device Configuration Memory bits requires a High-Voltage Enable or Disable Command (LAT/LAT0 = VIHH, or CS = VIHH) to modify the bit value.  2015 Microchip Technology Inc. DS20005375A-page 33 MCP47FEBXX 4.2.3 DEVICE CONFIGURATION MEMORY 4.2.5 UNIMPLEMENTED (RESERVED) LOCATIONS There are up to five nonvolatile user bits that are not directly mapped into the address space. These nonvolatile device configuration bits control the following functions: Normal (Voltage) Commands (Read or Write) to any unimplemented memory address (Reserved) will result in a Command Error condition (NACK). Read Commands of a reserved location will read bits as ‘1’. • DAC Register and Configuration WiperLock Technology (2 bits per DAC) • I2C Slave Address Write Protect (Lock) High-Voltage Commands (Enable or Disable) to any unimplemented Configuration bits will result in a Command Error condition (NACK). The Status register shows the states of the device WiperLock Technology configuration bits. The STATUS register is described in Register 4-6. 4.2.5.1 The operation of WiperLock Technology is discussed in Section 4.2.6 “WiperLock Technology” while I2C Slave Address Write Protect is discussed in Section 4.2.7 “I2C Slave Address Write Protect”. 4.2.4 Table 4-2 shows the default factory POR initialization of the device memory map for the 8-, 10- and 12-bit devices. Note: UNIMPLEMENTED REGISTER BITS Read Commands of a valid location will read unimplemented bits as ‘0’. POR/BOR Value Address The Volatile memory locations will be determined by the nonvolatile memory states (registers and device configuration bits). FACTORY DEFAULT POR / BOR VALUES POR/BOR Value 10-bit 12-bit 8-bit 10-bit 12-bit Function 8-bit Function Address TABLE 4-2: Default Factory POR Memory State of Nonvolatile Memory (EEPROM) 00h Volatile DAC0 Register 7Fh 1FFh 7FFh 10h Nonvolatile DAC0 Register 7Fh 1FFh 7FFh 01h Volatile DAC1 Register 7Fh 1FFh 7FFh 11h Nonvolatile DAC1 Register 7Fh 1FFh 7FFh 12h Reserved (2) FFh 3FFh FFFh 13h Reserved (2) FFh 3FFh FFFh 14h Reserved (2) FFh 3FFh FFFh 15h Reserved (2) FFh 3FFh FFFh 16h Reserved (2) FFh 3FFh FFFh 17h Reserved (2) FFh 3FFh FFFh 02h Reserved (2) 03h Reserved (2) 04h Reserved (2) 05h Reserved (2) 06h Reserved (2) 07h Reserved (2) FFh FFh FFh FFh FFh FFh 3FFh 3FFh 3FFh 3FFh 3FFh 3FFh FFFh FFFh FFFh FFFh FFFh FFFh 08h VREF Register 0000h 0000h 0000h 18h Nonvolatile VREF Register 0000h 0000h 0000h 09h Power-Down Register 0000h 0000h 0000h 19h Nonvolatile Power-Down Register 0000h 0000h 0000h 0Ah Gain and Status Register 0080h 0080h 0080h 1Ah NV Gain and I2C™ 7-bit Slave Address (1) 00E0h 00E0h 00E0h 0Bh WiperLock Technology Status Register 0000h 0000h 0000h (1 ) (1 ) (1 ) 1Bh Reserved (2) FFh 3FFh FFFh 0Ch Reserved (2) FFh 3FFh FFFh 1Ch Reserved (2) FFh 3FFh FFFh 0Dh Reserved (2) FFh 3FFh FFFh 1Dh Reserved (2) FFh 3FFh FFFh (2) FFh 3FFh FFFh FFh 3FFh FFFh (2) FFh 3FFh FFFh 1Eh Reserved 0Fh Reserved (2) FFh 3FFh FFFh 1Fh Reserved (2) 0Eh Reserved Volatile Memory address range Note 1: 2: Nonvolatile Memory address range A0 I2C 7-bit Slave Address option is ’110 0000’ and the Slave Address Lock (SALCK) bit is enabled (‘1’). Reading a reserved memory location will result in the I2C command to Not ACK the command byte. The device data bits will output all ‘1’s. A Start condition will reset the I2C interface. DS20005375A-page 34  2015 Microchip Technology Inc. MCP47FEBXX 4.2.6 WIPERLOCK TECHNOLOGY The MCP47FEBXX device’s WiperLock technology allows application-specific device settings (DAC register and configuration) to be secured without requiring the use of an additional write-protect pin. There are two configuration bits (DLx:CLx) for each DAC (DAC0 and DAC1). Please refer to the Section 7.5 “Enable Configuration Bit (High-Voltage)” and Section 7.6 “Disable Configuration Bit (High-Voltage)” commands for operation. Note: Dependent on the state of the DLx:CLx configuration bits, WiperLock technology prevents the serial commands from the following actions on the DACx registers and bits: • Writing to the specified volatile DACx Register memory location • Writing to the specified nonvolatile DACx Register memory location • Writing to the specified volatile DACx configuration bits • Writing to the specified nonvolatile DACx configuration bits 4.2.6.1 POR/BOR Operation when WiperLock Technology Enabled The WiperLock Technology state is not affected by a POR/BOR event. A POR/BOR event will load the Volatile DAC0 (DAC1) register values with the Nonvolatile DAC0 (DAC1) register values. 4.2.7 Each pair of these configuration bits control one of four modes. These modes are shown in Table 4-4. The addresses for the configuration bits are shown in Table 4-1. To modify the configuration bits, the HVC pin must be forced to the VIHH state and then receive an Enable or Disable command on the desired pair of DAC Register addresses. Note: During device communication, if the Device Address/Command combination is invalid or an unimplemented Address is specified, then the MCP47FEBXX will NACK that byte. To reset the I2C state machine, the I2C communication must detect a Start bit. To modify the CL0 bit, the Enable or Disable command specifies address 00h, while to modify the DL0 bit, the Enable or Disable command specifies address 10h. I2C SLAVE ADDRESS WRITE PROTECT The MCP47FEBXX device’s I2C Slave Address is stored in the EEPROM memory. This allows the address to be modified to the applications requirement. To ensure that the I2C Slave Address is not unintentionally modified, the memory has a high voltage write protect bit. This configurations bit is shown in Table 4-3. Note: To modify the SALCK bit, the Enable or Disable command specifies address 1Ah. TABLE 4-3: SALCK FUNCTIONAL DESCRIPTION SALCK Operation The nonvolatile I2C™ Slave Address bits (ADD6:ADD0) are locked 0 The nonvolatile I2C Slave Address bits (ADD6:ADD0) are unlocked WIPERLOCK TECHNOLOGY CONFIGURATION BITS FUNCTIONAL DESCRIPTION DLx:CLx (2) TABLE 4-4: 1 Volatile Nonvolatile 11 Locked 10 Locked 01 Register / Bits DACx 00 Note 1: 2: DACx Configuration (1) Comments Volatile Nonvolatile Locked Locked Locked All DACx registers are locked Locked Unlocked Locked All DACx registers are locked except volatile DACx Configuration registers. This allows operation of power-down modes Unlocked Locked Unlocked Locked Volatile DACx registers unlocked, nonvolatile DACx registers locked Unlocked Unlocked Unlocked Unlocked All DACx registers are unlocked DAC Configuration bits include Voltage Reference Control bits (VRxB:VRxA), Power-Down Control bits (PDxB:PDxA), and Output Gain bits (Gx). The state of these configuration bits (DLx:CLx) are reflected in WLxB:WLxA bits as shown in Register 4-6.  2015 Microchip Technology Inc. DS20005375A-page 35 MCP47FEBXX 4.2.8 DEVICE REGISTERS Register 4-1 shows the format of the DAC Output Value registers for both the volatile memory locations and the nonvolatile memory locations. These registers will be either 8 bits, 10 bits, or 12 bits wide. The values are right justified. REGISTER 4-1: 12-bit DAC0 AND DAC1 REGISTERS (VOLATILE AND NONVOLATILE) U-0 U-0 U-0 U-0 — — — — D11 D10 (1) (1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 10-bit — — — — — — 8-bit — — — — —(1) —(1) D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00 —(1) —(1) D07 D06 D05 D04 D03 D02 D01 D00 bit 15 bit 0 Legend: R = Readable bit -n = Value at POR = 12-bit device 12-bit 10-bit W = Writable bit ‘1’ = Bit is set = 10-bit device U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared = 8-bit device 8-bit bit 15-12 bit 15-10 bit 15-8 Unimplemented: Read as ‘0’ bit 11-0 — — D11-D00: DAC Output value - 12-bit devices FFFh = Full-Scale output value 7FFh = Mid-Scale output value 000h =Zero-Scale output value — bit 9-0 — D09-D00: DAC Output value - 10-bit devices 3FFh = Full-Scale output value 1FFh = Mid-Scale output value 000h =Zero-Scale output value — — bit 7-0 D07-D00: DAC Output value - 8-bit devices FFh = Full-Scale output value 7Fh = Mid-Scale output value 000h =Zero-Scale output value Note 1: Unimplemented bit, read as ‘0’. DS20005375A-page 36 x = Bit is unknown  2015 Microchip Technology Inc. MCP47FEBXX Register 4-2 shows the format of the Voltage Reference Control Register. Each DAC has two bits to control the source of the voltage reference of the DAC. This register is for both the volatile memory locations and the nonvolatile memory locations. The width of this register is 2 times the number of DACs for the device. REGISTER 4-2: VOLTAGE REFERENCE (VREF) CONTROL REGISTER (VOLATILE AND NONVOLATILE) (ADDRESSES 08h AND 18h) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 Single — — — — — — — — — — — — Dual — — — — — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 —(1) —(1) VR0B VR0A VR1B VR1A VR0B VR0A bit 15 bit 0 Legend: R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set = Single-channel device U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared = Dual-channel device x = Bit is unknown Single Dual bit 15-2 bit 15-4 Unimplemented: Read as ‘0’ bit 1-0 bit 3-0 VRxB-VRxA: DAC Voltage Reference Control bits 11 = VREF pin (Buffered); VREF buffer enabled. 10 = VREF pin (Unbuffered); VREF buffer disabled. 01 = Internal Band Gap (1.22V typical); VREF buffer enabled. VREF voltage driven when powered-down. 00 = VDD (Unbuffered); VREF buffer disabled. Use this state with Power-down bits for lowest current. Note 1: Unimplemented bit, read as ‘0’.  2015 Microchip Technology Inc. DS20005375A-page 37 MCP47FEBXX Register 4-3 shows the format of the Power-Down Control Register. Each DAC has two bits to control the Power-Down state of the DAC. This register is for both the volatile memory locations and the nonvolatile memory locations. The width of this register is 2 times the number of DACs for the device. REGISTER 4-3: POWER-DOWN CONTROL REGISTER (VOLATILE AND NONVOLATILE) (ADDRESSES 09h, 19h) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 Single — — — — — — — — — — — — —(1) Dual — — — — — — — — — — — — PB1B PB1A PB0B PB0A R/W-0 R/W-0 R/W-0 R/W-0 —(1) PB0B PB0A bit 15 bit 0 Legend: R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set = Single-channel device U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared = Dual-channel device x = Bit is unknown Single Dual bit 15-2 bit 15-4 Unimplemented: Read as ‘0’ bit 1-0 bit 3-0 PBxB-PBxA: DAC Power-Down Control bits(2) 11 = Powered Down - VOUT is open circuit. 10 = Powered Down - VOUT is loaded with a 100 k resistor to ground. 01 = Powered Down - VOUT is loaded with a 1 k resistor to ground. 00 = Normal Operation (Not powered-down). Note 1: 2: Unimplemented bit, read as ‘0’. See Table 5-5 and Figure 5-10 for more details. DS20005375A-page 38  2015 Microchip Technology Inc. MCP47FEBXX Register 4-4 shows the format of the Gain Control and System Status Register. Each DAC has one bit to control the gain of the DAC and three Status bits. This register is for both the volatile memory locations and the nonvolatile memory locations. REGISTER 4-4: U-0 U-0 U-0 GAIN CONTROL AND SYSTEM STATUS REGISTER (VOLATILE) (ADDRESS 0Ah) U-0 U-0 U-0 Single — — — — — — Dual — — — — — — R/W-0 R/W-0 R/C-1 (1) — G1 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 G0 POR EEWA — — — — — — G0 POR EEWA — — — — — — bit 15 bit 0 Legend: R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set = Single-channel device C = Clear-able bit ‘0’ = Bit is cleared = Dual-channel device U = Unimplemented bit, read as ‘0’ x = Bit is unknown Single Dual bit 15-9 bit 15-10 Unimplemented: Read as ‘0’ — bit 9 G1: DAC1 Output Driver Gain control bits (Dual-Channel Device only) 1 = 2x Gain. Not applicable when VDD is used as VRL. 0 = 1x Gain. bit 8 bit 8 G0: DAC0 Output Driver Gain control bits 1 = 2x Gain. Not applicable when VDD is used as VRL. 0 = 1x Gain. bit 7 bit 7 POR: Power-on Reset (Brown-out Reset) Status bit This bit indicates if a Power-on Reset (POR) or Brown-out Reset (BOR) event has occurred since the last read command of this register. Reading this register clears the state of the POR Status bit. 1 = A POR (BOR) event occurred since the last read of this register. Reading this register clears this bit. 0 = A POR (BOR) event has not occurred since the last read of this register. bit 6 bit 6 EEWA: EEPROM Write Active Status bit This bit indicates if the EEPROM Write Cycle is occurring 1 = An EEPROM Write Cycle is currently occurring. Only serial commands to the volatile memory are allowed. 0 = An EEPROM Write Cycle is NOT currently occurring. bit 5-0 bit 5-0 Unimplemented: Read as ‘0’ Note 1: Unimplemented bit, read as ‘0’.  2015 Microchip Technology Inc. DS20005375A-page 39 MCP47FEBXX Register 4-5 shows the format of the Nonvolatile Gain Control and Slave Address Register. Each DAC has one bit to control the gain of the DAC. I2C devices also have eight bits that are the I2C Slave Address and the status of the I2C Address Lock bit. REGISTER 4-5: U-0 U-0 U-0 GAIN CONTROL AND SLAVE ADDRESS REGISTER (NONVOLATILE) (ADDRESS 1Ah) U-0 U-0 Single — — — — — Dual — — — — — R/W-0 R/W-0 (1) — G1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 G0 ADLCK EEWA ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 G0 ADLCK EEWA ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 bit 15 bit 0 Legend: R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set = Single-channel device U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared = Dual-channel device x = Bit is unknown Single Dual bit 15-9 bit 15-10 Unimplemented: Read as ‘0’ — bit 9 G1: DAC1 Output Driver Gain control bits (Dual-Channel Device only)(2) 1 = 2x Gain. Not applicable when VDD is used as VRL. 0 = 1x Gain. bit 8 bit 8 G0: DAC0 Output Driver Gain control bits(3) 1 = 2x Gain. Not applicable when VDD is used as VRL. 0 = 1x Gain. bit 7 bit 7 ADLCK: I2C Address Lock Status bit (Read-Only bit; reflects the state of the SALCK configuration bit). 1 = I2C Slave Address is Locked (requires HV command to disable, so I2C address can be changed) 0 = I2C Slave Address is NOT Lock, the nonvolatile I2C slave address can be changed. bit 6-0 bit 6-0 ADD6-ADD0: I2C 7-bit Slave Address Bits. Note 1: 2: 3: Unimplemented bit, read as ‘0’. If VR1B:VR1A = ‘00’; the device uses a gain of 1 only, regardless of the state of this bit (G1). If VR0B:VR0A = ‘00’; the device uses a gain of 1 only, regardless of the state of this bit (G0). DS20005375A-page 40  2015 Microchip Technology Inc. MCP47FEBXX Register 4-6 shows the format of the DAC WiperLock Technology Status Register. The width of this register is 2 times the number of DACs for the device. REGISTER 4-6: Single Dual DAC WIPERLOCK TECHNOLOGY STATUS REGISTER (VOLATILE) (ADDRESS 0BH) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0(2) R-0(2) R-0(2) R-0(2) — — — — — — — — — — — — —(1) —(1) WL0B WL0A — — — — — — — — — — — — WL1B WL1A WL0B WL0A bit 15 bit 0 Legend: R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set = Single-channel device U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared = Dual-channel device x = Bit is unknown Single Dual bit 15-2 bit 15-4 Unimplemented: Read as ‘0’ bit 1-0 bit 3-0 WLxB-WLxA: WiperLock Technology Status bits: These bits reflect the state of the DLx:CLx nonvolatile configuration bits 11 = DAC wiper and DAC Configuration (volatile and nonvolatile registers) are locked (DLx = CLx = Enabled) 10 = DAC wiper (volatile and nonvolatile) and DAC Configuration (nonvolatile registers) are locked (DLx = Enabled; CLx = Disabled). 01 = DAC wiper (nonvolatile) and DAC Configuration (nonvolatile registers) are locked (DLx = Disabled; CLx = Enabled) 00 = DAC wiper and DAC Configuration are unlocked (DLx = CLx = Disabled). Note 1: 2: Unimplemented bit, read as ‘0’. POR Value dependent on the programmed values of the DLx:CLx configuration bits. The devices are shipped with a default DLx:CLx configuration bit state of ‘0’.  2015 Microchip Technology Inc. DS20005375A-page 41 MCP47FEBXX NOTES: DS20005375A-page 42  2015 Microchip Technology Inc. MCP47FEBXX 5.0 DAC CIRCUITRY The functional blocks of the DAC include: • • • • • • The Digital to Analog Converter circuitry converts a digital value into its analog representation. The description describes the functional operation of the device. The DAC Circuit uses a resistor ladder implementation. Devices have up to two DACs. Figure 5-1 shows the functional block diagram for the MCP47FEBXX DAC circuitry. Power-Down Operation PD1:PD0 and VREF1:VREF0 VDD Voltage Reference Selection Resistor Ladder Voltage Reference Selection Output Buffer/VOUT Operation Internal Band Gap (as a voltage reference) Latch Pin (LAT) Power-Down Operation VREF + - VDD VDD VREF1:VREF0 PD1:PD0 and BGEN Band Gap (1.22V typical) VREF1:VREF0 PD1:PD0 VDD A (RL) RS(2n) DAC Output Selection Power-Down Operation PD1:PD0 VW VOUT + RS(2n - 1) - Output Buffer/VOUT Operation RRL RS(2n - 3) (~140 k) 100 k PD1:PD0 Gain (1x or 2x) RS(2n - 2) 1 k VRL Internal Band Gap Power-Down Operation DAC Register Value V W = ----------------------------------------------------------------------  V RL # Resistor in Resistor Ladder RS(2) Where: # Resistors in Resistor Ladder = 256 (MCP47FEB0X) Resistor Ladder 1024 (MCP47FEB1X) RS(1) 4096 (MCP47FEB2X) B FIGURE 5-1: MCP47FEBXX DAC Module Block Diagram.  2015 Microchip Technology Inc. DS20005375A-page 43 MCP47FEBXX 5.1 Resistor Ladder PD1:PD0 The Resistor Ladder is a digital potentiometer with the B Terminal internally grounded and the A Terminal connected to the selected reference voltage (see Figure 5-2). The volatile DAC register controls the wiper position. The wiper voltage (VW) is proportional to the DAC register value divided by the number of resistor elements (RS) in the ladder (256, 1024 or 4096) related to the VRL voltage. The output of the resistor network will drive the input of an output buffer. VRL DAC Register RS(2n) 2n - 1 RW (1) RS(2n - 1) RRL 2n - 2 RW (1) RS(2n - 2) The Resistor Network is made up of these three parts: VW • Resistor Ladder (string of RS elements) • Wiper switches • DAC Register decode The resistor ladder (RRL) has a typical impedance of approximately 140 k. This resistor ladder resistance (RRL) may vary from device to device up to ±20%. Since this is a voltage divider configuration, the actual RRL resistance does not affect the output given a fixed voltage at VRL. Equation 5-1 shows the calculation for the step resistance. Note: The maximum wiper position is 2n – 1, while the number of resistors in the resistor ladder is 2n. This means that when the DAC register is at full scale, there is one resistor element (RS) between the wiper and the VRL voltage. If the unbuffered VREF pin is used as the VRL voltage source, this voltage source should have a low output impedance. When the DAC is powered-down, the resistor ladder is disconnected from the selected reference voltage. DS20005375A-page 44 1 RW RS(1) (1) 0 (1) RW Analog Mux DAC Register Value V W = ----------------------------------------------------------------------  V RL # Resistor in Resistor Ladder Where: # Resistors in R-Ladder = 256 (MCP47FEB0X) 1024 (MCP47FEB1X) 4096 (MCP47FEB2X) Note 1: The analog switch resistance (RW) does not affect performance due to the voltage divider configuration. FIGURE 5-2: Block Diagram. Resistor Ladder Model EQUATION 5-1: RS CALCULATION RRL R S = ------------ 256  8-bit Device R RL R S = --------------- 1024  10-bit Device R RL R S = --------------- 4096  12-bit Device  2015 Microchip Technology Inc. MCP47FEBXX Voltage Reference Selection The resistor ladder has up to four sources for the reference voltage. Two user control bits (VREF1:VREF0) are used to control the selection, with the selection connected to the VRL node (see Figures 5-3 and 5-4). The four voltage source options for the Resistor Ladder are: 1. 2. 3. 4. VDD pin voltage Internal Voltage Reference (VBG) VREF pin voltage unbuffered VREF pin voltage internally buffered The selection of the voltage is specified with the volatile VREF1:VREF0 configuration bits (see Register 4-2). There are nonvolatile and volatile VREF1:VREF0 configuration bits. On a POR/BOR event, the state of the nonvolatile VREF1:VREF0 configuration bits is latched into the volatile VREF1:VREF0 configuration bits. VREF1:VREF0 VREF VDD Band Gap Reference Selection 5.2 VRL Buffer FIGURE 5-3: Resistor Ladder Reference Voltage Selection Block Diagram. VDD PD1:PD0 and VREF1:VREF0 When the user selects the VDD as reference, the VREF pin voltage is not connected to the resistor ladder. VREF + VRL - If the VREF pin is selected, then one needs to select between the buffered or unbuffered mode. 5.2.1 UNBUFFERED MODE VDD The VREF pin voltage may be from VSS to VDD. Note 1: The voltage source should have a low output impedance. If the voltage source has a high output impedance, then the voltage on the VREF’s pin would be lower than expected. The resistor ladder has a typical impedance of 140 k and a typical capacitance of 29 pF. 2: If the VREF pin is tied to the VDD voltage, VDD mode (VREF1:VREF0 = ‘00’) is recommended. 5.2.2 BUFFERED MODE The VREF pin voltage may be from 0.01V to VDD 0.04V. The input buffer (amplifier) provides low offset voltage, low noise, and a very high input impedance, with only minor limitations on the input range and frequency response. Note 1: Any variation or noises on the reference source can directly affect the DAC output. The reference voltage needs to be as clean as possible for accurate DAC performance. 2: If the VREF pin is tied to the VDD voltage, VDD mode (VREF1:VREF0 = ‘00’) is recommended.  2015 Microchip Technology Inc. VDD VREF1:VREF0 VREF1:VREF0 PD1:PD0 and BGEN Band Gap (1) (1.22V typical) Note 1: The Band Gap voltage (VBG) is 1.22V typical. The band gap output goes through the buffer with a 2x gain to create the VRL voltage. See Section 5.4 “Internal Band Gap” for addition information on the band gap circuit. FIGURE 5-4: Reference Voltage Selection Implementation Block Diagram. 5.2.3 BANDGAP MODE If the Internal Band Gap is selected, then the external VREF pin should not be driven and only use high-impedance loads. Decoupling capacitors are recommended for optimal operation. The band gap output is buffered, but the internal switches limit the current that the output should source to the VREF pin. The resistor ladder buffer is used to drive the Band Gap voltage for the cases of multiple DAC outputs. This ensures that the resistor ladders are always properly sourced when the band gap is selected. DS20005375A-page 45 MCP47FEBXX 5.3 Output Buffer/VOUT Operation TABLE 5-1: The Output Driver buffers the wiper voltage (VW) of the Resistor Ladder. The DAC output is buffered with a low power and precision output amplifier (op amp). This amplifier provides a rail-to-rail output with low offset voltage and low noise. The amplifier’s output can drive the resistive and high-capacitive loads without oscillation. The amplifier provides a maximum load current which is enough for most programmable voltage reference applications. Refer to Section 1.0 “Electrical Characteristics” for the specifications of the output amplifier. Note: The load resistance must keep higher than 5 k for the stable and expected analog output (to meet electrical specifications). Figure 5-5 shows a block diagram of the output driver circuit. OUTPUT DRIVER GAIN Gain Bit Gain 0 1 1 2 5.3.1 Comment Limits VREF pin voltages relative to device VDD voltage. PROGRAMMABLE GAIN The amplifier’s gain is controlled by the Gain (G) configuration bit (see Register 4-5) and the VRL reference selection. When the VRL reference selection is the device’s VDD voltage, the G bit is ignored and a gain of 1 is used. The volatile G bit value can be modified by: • POR event • BOR event • I2C Write commands • I2C General Call Reset command The user can select the output gain of the output amplifier. Gain options are: a) b) Gain of 1, with either VDD or VREF pin used as reference voltage. Gain of 2, only when VREF pin or Internal Band Gap is used as reference voltage. The VREF pin voltage should be limited to VDD/2. Power-down logic also controls the output buffer operation (see Section 5.6 “Power-Down Operation” for additional information on Power-down). In any of the three Power-Down modes, the op amp is powereddown and its output becomes a high impedance to the VOUT pin. Table 5-1 shows the gain bit operation. When the reference voltage selection (VRL) is the device’s VDD voltage, the G bit is ignored and a gain of 1 is used. VDD PD1:PD0 VW VOUT + - 1 k 100 k PD1:PD0 Gain(1) Note 1: Gain options are 1x and 2x. FIGURE 5-5: DS20005375A-page 46 Output Driver Block Diagram.  2015 Microchip Technology Inc. MCP47FEBXX 5.3.2 OUTPUT VOLTAGE The volatile DAC Register values along with the device’s configuration bits control the analog VOUT voltage. The volatile DAC Register’s value is unsigned binary. The formula for the output voltage is given in Equation 5-2. Table 5-3 shows examples of volatile DAC register values and the corresponding theoretical VOUT voltage for the MCP47FEBXX devices. EQUATION 5-2: CALCULATING OUTPUT VOLTAGE (VOUT) V RL  DAC Register Value VOUT = ----------------------------------------------------------------------  Gain # Resistor in Resistor Ladder 5.3.3 STEP VOLTAGE (VS) The Step Voltage is dependent on the device resolution and the calculated output voltage range. One LSb is defined as the ideal voltage difference between two successive codes. The step voltage can easily be calculated by using Equation 5-3 (DAC Register Value is equal to 1). Theoretical Step Voltages are shown in Table 5-2 for several VREF voltages. EQUATION 5-3: VS CALCULATION V RL VS = ----------------------------------------------------------------------  Gain # Resistor in Resistor Ladder Where: Where: # Resistors in R-Ladder = 4096 (MCP47FEB2X) # Resistors in R-Ladder = 4096 (12-bit) 1024 (10-bit) 1024 (MCP47FEB1X) 256 (8-bit) 256 (MCP47FEB0X) Note: When Gain = 2 (VRL = VREF), if VREF > VDD / 2, the VOUT voltage will be limited to VDD. So if VREF = VDD, then the VOUT voltage will not change for volatile DAC Register values mid-scale and greater, since the op amp is at full-scale output. The following events update the DAC register value and therefore the analog voltage output (VOUT): • Power-on Reset • Brown-out Reset • I2C Write Command, Falling edge of the acknowledge pulse of the last write command byte. • I2C General Call Reset command, Output is updated with POR data (EEPROM). TABLE 5-2: THEORETICAL STEP VOLTAGE (VS) (1) VREF 5.0 2.7 1.8 1.5 1.0 1.22mV 659uV 439uV 366uV 244uV 12-bit 977uV 10-bit VS 4.88mV 2.64mV 1.76mV 1.46mV 19.5mV 10.5mV 7.03mV 5.86mV 3.91mV 8-bit Note 1: When Gain = 1x, VFS = VRL, and VZS = 0V. Then the VOUT voltage will start driving to the new value after the event has occurred.  2015 Microchip Technology Inc. DS20005375A-page 47 MCP47FEBXX 5.3.4 OUTPUT SLEW RATE Figure 5-6 shows an example of the slew rate of the VOUT pin. The slew rate can be affected by the characteristics of the circuit connected to the VOUT pin. VOUT(B) DACx = A DACx= B Time V OUT  B  – V OUT  A  Slew Rate = -------------------------------------------------T FIGURE 5-6: 5.3.4.1 VOUT pin Slew Rate. Small Capacitive Load With a small capacitive load, the output buffer’s current is not affected by the capacitive load (CL). But still, the VOUT pin’s voltage is not a step transition from one output value (DAC register value) to the next output value. The change of the VOUT voltage is limited by the output buffer’s characteristics, so the VOUT pin voltage will have a slope from the old voltage to the new voltage. This slope is fixed for the output buffer, and is referred to as the buffer slew rate (SRBUF). 5.3.4.2 DRIVING RESISTIVE AND CAPACITIVE LOADS The VOUT pin can drive up to 100 pF of capacitive load in parallel with a 5 k resistive load (to meet electrical specifications). A VOUT vs. Resistive Load characterization graph can be seen in the Char Data for this device (DS20005378). VOUT drops slowly as the load resistance decreases after about 3.5 k. It is recommended to use a load with RL greater than 5 k. VOUT VOUT(A) 5.3.5 Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop’s phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response with overshoot and ringing in the step response. That is, since the VOUT pin’s voltage does not quickly follow the buffer’s input voltage (due to the large capacitive load), the output buffer will overshoot the desired target voltage. Once the driver detects this overshoot, it compensates by forcing it to a voltage below the target. This causes voltage ringing on the VOUT pin. So, when driving large capacitive loads with the output buffer, a small series resistor (RISO) at the output (see Figure 5-7) improves the output buffer’s stability (feedback loop’s phase margin) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. Large Capacitive Load With a larger capacitive load, the slew rate is determined by two factors: • The output buffer’s short-circuit current (ISC) • The VOUT pin’s external load IOUT cannot exceed the output buffer’s short-circuit current (ISC), which fixes the output buffer slew rate (SRBUF). The voltage on the capacitive load (CL), VCL, changes at a rate proportional to IOUT, which fixes a capacitive load slew rate (SRCL). So the VCL voltage slew rate is limited to the slower of the output buffer’s internally set slew rate (SRBUF) and the capacitive load slew rate (SRCL). VW Op Amp VOUT VCL RISO RL CL FIGURE 5-7: Circuit to Stabilize Output Buffer for Large Capacitive Loads (CL). The RISO resistor value for your circuit needs to be selected. The resulting frequency response peaking and step response overshoot for this RISO resistor value should be verified on the bench. Modify the RISO’s resistance value until the output characteristics meet your requirements. A method to evaluate the system’s performance is to inject a step voltage on the VREF pin and observe the VOUT pin’s characteristics. Note: DS20005375A-page 48 Additional insight into circuit design for driving capacitive loads can be found in AN884 – “Driving Capacitive Loads With Op Amps” (DS00000884).  2015 Microchip Technology Inc. MCP47FEBXX TABLE 5-3: Device DAC INPUT CODE VS. CALCULATED ANALOG OUTPUT (VOUT) (VDD = 5.0V) Volatile DAC Register Value 1111 1111 1111 VRL (1) LSb Gain Selection Equation µV 5.0V 5.0V/4096 1,220.7 1x VRL  (4095/4096)  1 4.998779 2.5V 2.5V/4096 610.4 1x VRL  (4095/4096)  1 2.499390 (2) MCP47FEB2X (12-bit) 0011 1111 1111 5.0V 5.0V/4096 1,220.7 2.5V 2.5V/4096 610.4 MCP47FEB1X (10-bit) 11 1111 1111 01 1111 1111 00 1111 1111 00 0000 0000 MCP47FEB0X (8-bit) 1111 1111 0111 1111 0011 1111 0000 0000 Note 1: 2: 3: V VRL  (4095/4096)  2) 4.998779 VRL  (2047/4096)  1) 2.498779 1x VRL  (2047/4096)  1) 1.249390 2x(2) VRL  (2047/4096)  2) 2.498779 5.0V 5.0V/4096 1,220.7 1x VRL  (1023/4096)  1) 1.248779 2.5V 2.5V/4096 610.4 1x VRL  (1023/4096)  1) 0.624390 VRL  (1023/4096)  2) 1.248779 2x 0000 0000 0000 (2) Equation 1x 2x 0111 1111 1111 VOUT(3) 5.0V 5.0V/4096 1,220.7 2.5V 2.5V/4096 610.4 (2) 1x VRL  (0/4096) * 1) 1x VRL  (0/4096) * 1) 0 2x(2) VRL  (0/4096) * 2) 0 0 5.0V 5.0V/1024 4,882.8 1x VRL  (1023/1024)  1 4.995117 2.5V 2.5V/1024 2,441.4 1x VRL  (1023/1024)  1 2.497559 2x(2) 5.0V 5.0V/1024 4,882.8 2.5V 2.5V/1024 2,441.4 VRL  (1023/1024)  2 4.995117 1x VRL  (511/1024)  1 2.495117 1x VRL  (511/1024)  1 1.247559 2x(2) VRL  (511/1024)  2 2.495117 VRL  (255/1024)  1 1.245117 5.0V 5.0V/1024 4,882.8 1x 2.5V 2.5V/1024 2,441.4 1x VRL  (255/1024)  1 0.622559 2x(2) VRL  (255/1024)  2 1.245117 5.0V 5.0V/1024 4,882.8 2.5V 2.5V/1024 2,441.4 1x VRL  (0/1024)  1 0 1x VRL  (0/1024)  1 0 2x(2) VRL  (0/1024)  1 0 5.0V 5.0V/256 19,531.3 1x VRL  (255/256)  1 4.980469 2.5V 2.5V/256 9,765.6 1x VRL  (255/256)  1 2.490234 2x(2) VRL  (255/256)  2 4.980469 1x VRL  (127/256)  1 2.480469 5.0V 5.0V/256 19,531.3 2.5V 2.5V/256 9,765.6 1x VRL  (127/256)  1 1.240234 2x(2) VRL  (127/256)  2 2.480469 5.0V 5.0V/256 19,531.3 1x VRL  (63/256)  1 1.230469 2.5V 2.5V/256 9,765.6 1x VRL  (63/256)  1 0.615234 2x(2) VRL  (63/256)  2 1.230469 1x VRL  (0/256)  1 0 1x VRL  (0/256)  1 0 2x(2) VRL  (0/256)  2 0 5.0V 5.0V/256 19,531.3 2.5V 2.5V/256 9,765.6 VRL is the resistor ladder’s reference voltage. It is independent of VREF1:VREF0 selection. Gain selection of 2x (Gx = ‘1‘) requires voltage reference source to come from VREF pin (VREF1:VREF0 = ‘10‘ or ‘11’) and requires VREF pin voltage (or VRL) ≤ VDD/2 or from the internal band gap (VREF1:VREF0 = ‘01’). These theoretical calculations do not take into account the Offset, Gain and nonlinearity errors.  2015 Microchip Technology Inc. DS20005375A-page 49 MCP47FEBXX 5.4 Internal Band Gap The internal band gap is designed to drive the Resistor Ladder Buffer. The resistance of a resistor ladder (RRL) is targeted to be 140 k (40 k), which means a minimum resistance of 100 k. The band gap selection can be used across the VDD voltages while maximizing the VOUT voltage ranges. For VDD voltages below the 2  Gain  VBG voltage, the output for the upper codes will be clipped to the VDD voltage. Table 5-4 shows the maximum DAC register code given device VDD and Gain bit setting. 5.5 2.7 2.0(4) DAC Gain VDD TABLE 5-4: VOUT USING BAND GAP Max DAC Code (1) 12bit 10-bit 8-bit 1 FFFh 3FFh 2 FFFh 3FFh 1 FFFh 3FFh Comment FFh VOUT(max) = 2.44V(3) FFh VOUT(max) = 4.88V(3) FFh VOUT(max) = 2.44V(3) 2 8DAh 236h 8Dh ~ 0 to 55% range 1 D1Dh 347h D1h ~ 0 to 82% range 68Eh 1A3h 68h 2(2) Note 1: 2: 3: 4: ~ 0 to 41% range Without the VOUT pin voltage being clipped. Recommended to use Gain = 1 setting. When VBG = 1.22V typical. Band gap performance achieves full performance starting from a VDD of 2.0V. DS20005375A-page 50  2015 Microchip Technology Inc. MCP47FEBXX 5.5 Latch Pin (LAT) The Latch pin controls when the volatile DAC Register value is transferred to the DAC wiper. This is useful for applications that need to synchronize the wiper(s) updates to an external event, such as zero crossing or updates to the other wipers on the device. The LAT pin is asynchronous to the serial interface operation. Serial Shift Reg Register Address Write Command 16 Clocks Vol. DAC Register x LAT Transfer SYNC Data (internal signal) DAC wiper x When the LAT pin is high, transfers from the volatile DAC register to the DAC wiper are inhibited. The volatile DAC register value(s) can be continued to be updated. When the LAT pin is low, the volatile DAC register value is transferred to the DAC wiper. Note: This allows both the volatile DAC0 and DAC1 Registers to be updated while the LAT pin is high, and to have outputs synchronously updated as the LAT pin is driven low. Figure 5-8 shows the interaction of the LAT pin and the loading of the DAC wiper x (from the volatile DAC Register x). The transfers are level driven. If the LAT pin is held low, the corresponding DAC wiper is updated as soon as the volatile DAC Register value is updated. LAT SYNC Transfer Data Comment 1 1 0 No Transfer 1 0 0 No Transfer 0 1 1 Vol. DAC Register x  DAC wiper x 0 0 0 No Transfer FIGURE 5-8: LAT and DAC Interaction. The LAT pin allows the DAC wiper to be updated to an external event as well as have multiple DAC channels/devices update at a common event. Since the DAC wiper x is updated from the Volatile DAC Register x, all DACs that are associated with a given LAT pin can be updated synchronously. If the application does not require synchronization, then this signal should be tied low. Figure 5-9 shows two cases of using the LAT pin to control when the wiper register is updated relative to the value of a sine wave signal. Case 1: Zero Crossing of Sine Wave to update volatile DAC0 register (using LAT pin) Case 2: Fixed point Crossing of Sine Wave to update volatile DAC0 register (using LAT pin) Indicates where LAT pin pulses active (volatile DAC0 register updated) FIGURE 5-9: Example use of LAT pin operation.  2015 Microchip Technology Inc. DS20005375A-page 51 MCP47FEBXX Power-Down Operation To allow the application to conserve power when the DAC operation is not required, three power-down modes are available. The Power-Down configuration bits (PD1:PD0) control the power-down operation (Figure 5-10 and Table 5-5). On devices with multiple DACs, each DACs power-down mode is individually controllable. All power-down modes do the following: • Turn off most the DAC module’s internal circuits (output op amp, resistor ladder,...) • Op amp output becomes high-impedance to the VOUT pin • Disconnects resistor ladder from reference voltage (VRL) • Retains the value of the volatile DAC register and configuration bits, and the nonvolatile (EEPROM) DAC register and configuration bits VW V OUT + PD1:PD0 1k (1) Note 1: Gain options are 1x and 2x. • VOUT pin is switched to one of two resistive pulldowns (See Table 5-5) - 100 k (typical) - 1 k (typical) • Op amp is powered-down and the VOUT pin is high-impedance. There is a delay (TPDE) between the PD1:PD0 bits changing from ‘00’ to either ‘01’, ‘10’ or ‘11’ and the op amp no longer driving the VOUT output and the pulldown resistors sinking current. In any of the power-down modes where the VOUT pin is not externally connected (sinking or sourcing current), the power-down current will typically be ~650 nA for a single-DAC device. As the number of DACs increases, the device’s power-down current will also increase. The power-down bits are modified by using a Write command to the volatile Power-Down register, or a POR event which transfers the nonvolatile Power-Down register to the volatile Power-Down register. 2C Section 7.0 “Device Commands” describes the I commands for writing the power-down bits. The commands that can update the volatile PD1:PD0 bits are: Write Command (Normal and High-Voltage) Read Command (Normal and High-Voltage) Enable Configuration Bit (High-Voltage) Disable Configuration Bit (High-Voltage) General Call Reset General Call Wake-up Note: PD1:PD0 Gain Depending on the selected power-down mode, the following will occur: • • • • • • V DD 100 k 5.6 FIGURE 5-10: Diagram. VOUT Power-Down Block TABLE 5-5: PD1 PD0 0 0 POWER-DOWN BITS AND OUTPUT RESISTIVE LOAD Function Normal operation 0 1 1 k resistor to ground 1 0 100 k resistor to ground 1 1 Open Circuit Table 5-6 shows the current sources for the DAC based on the selected source of the DAC’s reference voltage and if the device is in normal operating mode or one of the power-down modes. TABLE 5-6: Device VDD Current Source DAC CURRENT SOURCES PD1:0  ‘00’, VREF1:0 = PD1:0 = ‘00’, VREF1:0 = 00 01 10 11 00 01 10 11 Output Op Amp Y Y Y Y N N N N Resistor Ladder Y Y N (1) Y N N N (1) N RL Op Amp N Y N Y N N N N Band Gap N Y N N N Y N N Note 1: Current is sourced from the VREF pin, not the device VDD. The I2C serial interface circuit is not affected by the Power-Down mode. This circuit remains active in order to receive any command that might come from the I2C master device. DS20005375A-page 52  2015 Microchip Technology Inc. MCP47FEBXX 5.6.1 EXITING POWER-DOWN When the device exits the power-down mode the following occurs: • Disabled circuits (op amp, resistor ladder, ...) are turned on • Resistor ladder is connected to selected reference voltage (VRL) • Selected pull-down resistor is disconnected • The VOUT output will be driven to the voltage represented by the volatile DAC Register’s value and configuration bits The VOUT output signal will require time as these circuits are powered-up and the output voltage is driven to the specified value as determined by the volatile DAC register and configuration bits. Note: Since the op amp and resistor ladder were powered-off (0V), the op amp’s input voltage (VW) can be considered 0V. There is a delay (TPDD) between the PD1:PD0 bits updating to ‘00’ and the op amp driving the VOUT output. The op amp’s settling time (from 0V) needs to be taken into account to ensure the VOUT voltage reflects the selected value. The following events will change the PD1:PD0 bits to ‘00’ and therefore exit the Power-Down mode. These are: • Any I2C write command where the PD1:PD0 bits are ‘00’. • I2C General Call Wake-up Command. • I2C General Call Reset Command. (if nonvolatile PD1:PD0 bits are ‘00’). 5.6.2 RESET COMMANDS When the MCP47FEBXX is in the valid operating voltage, the I2C General Call Reset command will force a Reset event. This is similar to the Power-on Reset, except that the Reset delay timer is not started. 5.7 DAC Registers, Configuration Bits, and Status Bits The MCP47FEBXX devices have both volatile and nonvolatile (EEPROM) memory. Table 4-2 shows the volatile and nonvolatile memory and their interaction due to a POR event. There are five configuration bits in both the volatile and nonvolatile memory, the DAC registers in both the volatile and nonvolatile memory, and two volatile status bits. The DAC registers (volatile and nonvolatile) will be either 12 bits (MCP47FEB2X), 10 bits (MCP47FEB1X), or 8 bits (MCP47FEB0X) wide. When the device is first powered-up, it automatically uploads the EEPROM memory values to the volatile memory. The volatile memory determines the analog output (VOUT) pin voltage. After the device is poweredup, the user can update the device memory. The I2C interface is how this memory is read and written. Refer to Section 6.0 “I2C Serial Interface Module” and Section 7.0 “Device Commands” for more details on reading and writing the device’s memory. When the nonvolatile memory is written, the device starts writing the EEPROM cell at the Acknowledge pulse of the Write command. Register 4-4 shows the operation of the device status bits, Table 4-3 and Table 4-4 show the operation of the device configuration bits, and Table 4-2 shows the factory default value of a POR/BOR event for the device configuration bits. There are two status bits. These are only in volatile memory and give indication on the status of the device. The POR bit indicates if the device VDD is above or below the POR trip point. During normal operation, this bit should be ‘1’. The RDY/BSY bit indicates if an EEPROM write cycle is in progress. While the RDY/BSY bit is low (during the EEPROM writing), all commands are ignored, except for the Read command. If the I2C interface bus does not seem to be responsive, the technique shown in Section 8.9 “Software I2C Interface Reset Sequence” can be used to force the I2C interface to be reset.  2015 Microchip Technology Inc. DS20005375A-page 53 MCP47FEBXX I2C SERIAL INTERFACE MODULE 6.0 The MCP47FEBXX’s I2C Serial Interface Module supports the I2C serial protocol specification. This I2C interface is a two-wire interface (clock and data). Figure 6-1 shows a typical I2C interface connection. 2 The I C specification only defines the field types, field lengths, timings, etc. of a frame. The frame content defines the behavior of the device. The frame content (Commands) for the MCP47FEBXX is defined in Section 7.0 “Device Commands”. An overview of the I2C protocol is available in Section Appendix B: “I2C Serial Interface”. MCP47FEBXX (Slave) SDA 6.1 POR/BOR On a POR/BOR event, the I2C Serial Interface Module state machine is reset, which includes that the Device’s Memory Address pointer is forced to 00h. SDA The memory address is the 5-bit value that specifies the location in the device’s memory that the specified command will operate on. Typical I2C Interface. Overview The following sections discuss some of these devicespecific characteristics. Interface Pins (SCL and SDA) Communication Data Rates POR/BOR Device Memory Address General Call Commands Device I2C Slave Addressing Entering High-Speed (HS) Mode 6.2 A description on how to enter High-Speed mode is described in Section 6.9 “Entering High-Speed (HS) Mode”. 6.5 This sections discusses some of the specific characteristics of the MCP47FEBXX’s I2C Serial Interface Module. This is to assist in the development of your application. • • • • • • • • Standard mode: up to 100 kHz (kbit/s) • Fast mode: up to 400 kHz (kbit/s) • High-Speed mode (HS mode): up to 3.4 MHz (Mbit/s) SCL Other Devices FIGURE 6-1: Communication Data Rates The I2C interface specifies different communication bit rates. These are referred to as Standard, Fast or HighSpeed modes. The MCP47FEBXX supports these three modes. The clock rates (bit rate) of these modes are: 6.4 Typical I2C™ Interface Connections Host Controller (Master) SCL 6.3 Interface Pins (SCL and SDA) The MCP47FEBXX I2C’s module SCL pin does not generate the serial clock since the device operates in Slave mode. Also, the MCP47FEBXX will not stretch the clock signal (SCL) since memory read access occurs fast enough. Device Memory Address On a POR/BOR event, the Device’s Memory Address pointer is forced to 00h. The MCP47FEBXX retains the last “Device Memory Address” that it has received. That is, the MCP47FEBXX does not “corrupt” the “Device Memory Address” after Repeated Start or Stop conditions. 6.6 General Call Commands The General Call commands utilize the I2C specification reserved General Call command address and command codes. The MCP47FEBXX also implements a non-standard General Call command. The General Call commands are • General Call Reset • General Call Wake-up (MCP47FEBXX defined) The General Call Wake-up command will cause all the MCP47FEBXX devices to exit their power-down state. 6.7 Multi-Master Systems The MCP47FEBXX is not a Master device (generate the interface clock), but can be used in multi-master applications. The MCP47FEBXX I2C’s module implements slope control on the SDA pin output driver. DS20005375A-page 54  2015 Microchip Technology Inc. MCP47FEBXX Device I2C Slave Addressing 6.8 The MCP47FEBXX implements 7-bit slave addressing. The address byte is the first byte received following the Start condition from the master device (see Figure 6-2). The slave address is implemented in a nonvolatile register (Register 4-5) which is protected from accidental register writes via the Slave Address Lock (SALCK) configuration bit. The SALCK configuration bit requires a high voltage (VIHH) to be modified. The SALCK configuration bit must be disabled (see Section 7.6 “Disable Configuration Bit (High-Voltage)”) before a write to the nonvolatile Slave Addresses register can modify the value. Note: After modifying the nonvolatile Slave Address value (Register 4-5), it is strongly recommended that the SALCK configuration bit is enabled (see Section 7.5 “Enable Configuration Bit (High-Voltage)”). Acknowledge bit Start bit Read/Write bit R/W ACK Slave Address Address Byte Slave Address (7-bits) 1 1 A6 A5 0 0 A4 A3 0 0 A2 A1 0 A0 Address A0 (1) Table 6-1 shows the four standard order-able I2C slave addresses and their respective device order code. TABLE 6-1: 7-bit I2C™ Address ‘1100000’ (2) ‘1100001’ (2) ‘1100010’ (2) ‘1100011’ (2) Note 1: 2: 6.8.0.1 I2C ADDRESS/ORDER CODE Device Order Code(1) Comment MCP47FEBXXA0-E/ST MCP47FEBXXA0T-E/ST Tape and Reel MCP47FEBXXA1-E/ST MCP47FEBXXA1T-E/ST Tape and Reel MCP47FEBXXA2-E/ST MCP47FEBXXA2T-E/ST Tape and Reel MCP47FEBXXA3-E/ST MCP47FEBXXA3T-E/ST Tape and Reel ‘xx’ in the order code indicates the resolution and number of output channels for the device. The devices I2C Slave Address can be reprogrammed by the end user. Custom I2C Slave Address Options Custom I2C Slave Address options can be requested. Customers can request the custom I2C Slave Address via the Non-Standard Customer Authorization Request (NSCAR) process. Note 1: Non-Recurring Engineering (NRE) charges and minimum ordering requirements for custom orders. Please contact Microchip sales for additional information. 2: A custom device will be assigned custom device marking. Note 1: Address Bits (A6:A0) can be reprogrammed by the customer (nonvolatile device), but must unlock the Slave Address with a High-Voltage command. FIGURE 6-2: I2C Control Byte. Note: Slave Address Bits in the The I2C 10-bit Addressing mode is not supported.  2015 Microchip Technology Inc. DS20005375A-page 55 MCP47FEBXX 6.9 Entering High-Speed (HS) Mode The I2C specification requires that a High-Speed mode device must be ‘activated’ to operate in High-Speed (3.4 Mbit/s) mode. This is done by the master sending a special address byte following the Start bit. This byte is referred to as the High-Speed Master Mode Code (HSMMC). The device can now communicate at up to 3.4 Mbit/s on SDA and SCL lines. The device will switch out of the HS mode on the next Stop condition. The master code is sent as follows: 1. 2. 3. Start condition (S) High-Speed Master Mode Code (0000 1XXX), The XXX bits are unique to the High-Speed (HS) mode master. No Acknowledge (A) The MCP47FEBXX device does not acknowledge the HS Select byte. However, upon receiving this command, the device switches to HS mode. See Figure 6-3 for illustration of HS mode command sequence. For more information on the HS mode, or other I2C modes, please refer to the NXP I2C specification. 6.9.1 SLOPE CONTROL The slope control on the SDA output is different between the Fast/Standard Speed and the High-Speed clock modes of the interface. 6.9.2 PULSE GOBBLER The pulse gobbler on the SCL pin is automatically adjusted to suppress spikes VIHH (~9.0V) on the HVC pin puts the device into High-Voltage mode. High Voltage commands allow the device’s WiperLock Technology and write-protect features to be enabled and disabled. Note 1: There is a required delay after the HVC pin is driven to the VIHH level to the 1st edge of the SCL pin. 2: The command sequence can go from an increment to any other valid command for the specified address. Issuing an increment or decrement to a nonvolatile location will cause an error condition (A will be generated). ACK bit (1, 2) Write bit ACK bit (1, 2) (1) ACK bit Stop bit (2) 2 (1) I C™ Slave Address Memory Address Command Memory Address Command Start bit SA SA SA SA SA SA SA AD AD AD AD AD S 6 5 4 3 2 1 0 0 A 4 3 2 1 0 1 0 Control Byte Enable Command AD AD AD AD AD X A 4 3 2 1 0 1 0 X A P Enable Command (3) Note 1: The Slave address is determined by the NV Gain and I2C 7-bit Slave Address Register. The default factory address is ‘110 0000b’ (C0h for Control byte with write, C1h for Control byte with read). 2: This command sequence does not need to terminate (using the Stop bit) and can change to any other desired command sequence (Disable, Read or Write). 3: This command byte is not required and the Stop bit may occur immediately after the 2nd ACK bit in this sequence. FIGURE 7-11: I2C Enable Command Sequence.  2015 Microchip Technology Inc. DS20005375A-page 67 MCP47FEBXX 7.6 Disable Configuration Bit (High-Voltage) 7.6.1 The High Voltage Command (HVC) signal is used to indicate that the command, or sequence of commands, are in the High-Voltage mode. Signals >VIHH (~9.0V) on the HVC pin puts MCP47FEBXX devices into HighVoltage mode. High Voltage commands allow the device’s WiperLock Technology and write protect features to be enabled and disabled. Figure 7-12 (Disable) shows the formats for a single Modify Write Protect or Wiper-Lock Technology command. A Modify Write Protect or Wiper-Lock Technology command will only start an EEPROM write cycle (twc) after a properly formatted command has been received and the Stop condition occurs. Note 1: There is a required delay after the HVC pin is driven to the VIHH level to the 1st edge of the SCL pin. During an EEPROM write cycle, only serial commands to volatile memory are accepted. All other serial commands are ignored until the EEPROM write cycle (twc) completes. This allows the Host Controller to operate on the volatile DAC, the volatile VREF, Power-down, Gain and Status, and WiperLock Technology Status registers. The EEWA bit in the Status register indicates the status of an EEPROM Write Cycle. 2: The command sequence can go from an increment to any other valid command for the specified address. Issuing an increment or decrement to a nonvolatile location will cause an error condition (A will be generated). ACK bit (1, 2) Start bit Write bit ACK bit (1) 2 (1) I C™ Slave Address Address Command AD AD AD AD AD SA SA SA SA SA SA SA S 6 5 4 3 2 1 0 0 A 4 3 2 1 0 0 1 Control Byte THE HIGH-VOLTAGE COMMAND (HVC) SIGNAL Disable Command Address ACK bit (1, 2) Stop bit (2) Command AD AD AD AD AD X A 4 3 2 1 0 0 1 X A P Disable Command(3) Note 1: The Slave address is determined by the NV Gain and I2C 7-bits Slave Address Register. The default factory address is ‘110 0000b’ (C0h for Control byte with write, C1h for Control byte with read). 2: This command sequence does not need to terminate (using the Stop bit) and can change to any other desired command sequence (Enable, Read or Write). 3: This command byte is not required and the Stop bit may occur immediately after the 2nd ACK bit in this sequence. FIGURE 7-12: DS20005375A-page 68 I2C Disable Command Sequence.  2015 Microchip Technology Inc. MCP47FEBXX Write bit I2C™ Slave Address (1) S 1 1 0 0 0 0 Address 0 A 0 Control Byte 0 0 0 0 Address 1 1 0 1 Enable Command 0 1 0 X A 1 Enable Command 0 1 0 X A 1 Address 0 0 0 Enable Command 0 Address 1 0 1 1 0 X A DAC 0 (CL:DL) Enable Command 1 1 0 X A P SALCK Note 1: The two command bits may either specify the Enable Command or the Disable Command. FIGURE 7-13: Configuring All User Configuration Bits Command Sequence (MCP47FEBX1). Write bit I2C™ Slave Address (1) S 1 1 0 0 0 0 0 Control Byte Address 0 A 0 0 0 0 Address 0 0 0 0 Address 1 1 0 1 Enable Command 0 1 0 X A 1 Enable Command 1 1 0 X A 1 Enable Command 0 1 0 X A 1 Address 0 0 0 Enable Command 0 Address 0 0 0 0 1 X A DAC 0 (CL:DL) Enable Command 1 Address 1 1 0 1 0 X A DAC 1 (CL:DL) Enable Command 1 1 0 X A P SALCK Note 1: The two command bits may either specify the Enable command or the Disable command. FIGURE 7-14: Configuring All User Configuration Bits Command Sequence (MCP47FEBX2).  2015 Microchip Technology Inc. DS20005375A-page 69 MCP47FEBXX NOTES: DS20005375A-page 70  2015 Microchip Technology Inc. MCP47FEBXX TYPICAL APPLICATIONS The MCP47FEBXX family of devices are general purpose, single/dual-channel voltage output DACs for various applications where a precision operation with low-power and nonvolatile EEPROM memory is needed. Since the devices include a nonvolatile EEPROM memory, the user can utilize these devices for applications that require the output to return to the previous set-up value on subsequent power-ups. 8.1.1 The user can test the presence of the device on the I2C bus line using a simple I2C command. This test can be achieved by checking an acknowledge response from the device after sending a Read or Write command. Figure 8-1 shows an example with a Read command. The steps are: 1. 2. Applications generally suited for the devices are: • • • • Set Point or Offset Trimming Sensor Calibration Portable Instrumentation (Battery-Powered) Motor Control 8.1 Connecting to I2C BUS using Pull-Up Resistors The SCL and SDA pins of the MCP47FEBXX devices are open-drain configurations. These pins require a pull-up resistor, as shown in Figure 8-2. The pull-up resistor values (R1 and R2) for SCL and SDA pins depend on the operating speed (standard, fast and high-speed) and loading capacitance of the I2C bus line. A higher value of the pull-up resistor consumes less power, but increases the signal transition time (higher RC time constant) on the bus line. Therefore, it can limit the bus operating speed. The lower resistor value, on the other hand, consumes higher power, but allows higher operating speed. If the bus line has higher capacitance due to long metal traces or multiple device connections to the bus line, a smaller pull-up resistor is needed to compensate the long RC time constant. The pull-up resistor is typically chosen between 1 k and 10 kranges for Standard and Fast modes, and less than 1 kfor High-Speed mode.  2015 Microchip Technology Inc. DEVICE CONNECTION TEST 3. Set the R/W bit “High” in the device’s address byte. Check the ACK bit of the address byte. If the device acknowledges (ACK = 0) the command, then the device is connected. Otherwise, it is not connected. Send Stop bit. Address Byte SCL 1 2 3 4 5 6 7 8 SDA A6 A5 A4 A3 A2 A1 A0 1 Start Bit 9 ACK 8.0 Stop Bit Address bits R/W Device Response FIGURE 8-1: I2C Bus Connection Test. DS20005375A-page 71 MCP47FEBXX 8.2 Power Supply Considerations The power source should be as clean as possible. The power supply to the device is also used for the DAC voltage reference internally if the internal VDD is selected as the resistor ladder’s reference voltage (VRxB:VRxA = ’00’). Any noise induced on the VDD line can affect the DAC performance. Typical applications will require a bypass capacitor in order to filter out high-frequency noise on the VDD line. The noise can be induced onto the power supply’s traces or as a result of changes on the DAC output. The bypass capacitor helps to minimize the effect of these noise sources on signal integrity. Figure 8-2 shows an example of using two bypass capacitors (a 10 µF tantalum capacitor and a 0.1 µF ceramic capacitor) in parallel on the VDD line. These capacitors should be placed as close to the VDD pin as possible (within 4 mm). If the application circuit has separate digital and analog power supplies, the VDD and VSS pins of the device should reside on the analog plane. VDD R1 VDD C1 REF 2 8 SDA 7 SCL VOUT0 3 6 LAT/HVC 4 5 V SS C2 V Analog Output VOUT1 C3 1 R2 To MCU MCP47FEBX2 C4 Optional (a) Circuit when VDD is selected as reference (Note: VDD is connected to the reference circuit internally.) VDD C1 C2 R1 VDD VREF C5 1 VREF 2 VOUT0 3 VOUT1 4 C6 Optional Analog Output 8 SDA 7 SCL To MCU 6 LAT/HVC 5 MCP47FEBX2 C3 R2 VSS C4 Optional (b) Circuit when external reference is used. R1 and R2 are I2C™ pull-up resistors: R1 and R2: 5 k - 10 k for fSCL = 100 kHz to 400 kHz ~700 for fSCL = 3.4 MHz C1 : 0.1 µF capacitor C2 : 10 µF capacitor Tantalum C3 : ~ 0.1 µF Optional to reduce noise in VOUT pin. C4 : 0.1 µF capacitor Ceramic C5 : 10 µF capacitor Tantalum C6 : 0.1 µF capacitor Ceramic FIGURE 8-2: DS20005375A-page 72 Ceramic Example Circuit.  2015 Microchip Technology Inc. MCP47FEBXX 8.3 Application Examples The MCP47FEBXX devices are rail-to-rail output DACs designed to operate with a VDD range of 2.7V to 5.5V. The internal output op amplifier is robust enough to drive common, small-signal loads directly, thus eliminating the cost and size of external buffers for most applications. The user can use gain of 1 or 2 of the output op amplifier by setting the Configuration register bits. Also, the user can use internal VDD as the reference or use external reference. Various user options and easy-to-use features make the devices suitable for various modern DAC applications. Application examples include: • • • • • • • • • • Decreasing Output Step Size Building a “Window” DAC Bipolar Operation Selectable Gain and Offset Bipolar Voltage Output Designing a Double-Precision DAC Building Programmable Current Source Serial Interface Communication Times Software I2C Interface Reset Sequence Power Supply Considerations Layout Considerations 8.3.1 8.3.1.1 Decreasing Output Step Size If the application is calibrating the bias voltage of a diode or transistor, a bias voltage range of 0.8V may be desired with about 200 µV resolution per step. Two common methods to achieve small step size are using lower VREF pin voltage or using a voltage divider on the DAC’s output. Using an external voltage reference (VREF) is an option if the external reference is available with the desired output voltage range. However, occasionally, when using a low-voltage reference voltage, the noise floor causes a SNR error that is intolerable. Using a voltage divider method is another option, and provides some advantages when external voltage reference needs to be very low, or when the desired output voltage is not available. In this case, a larger value reference voltage is used, while two resistors scale the output range down to the precise desired level. Figure 8-3 illustrates this concept. A bypass capacitor on the output of the voltage divider plays a critical function in attenuating the output noise of the DAC and the induced noise from the environment. VDD DC SET POINT OR CALIBRATION A common application for the devices is a digitally-controlled set point and/or calibration of variable parameters, such as sensor offset or slope. For example, the MCP47FEB2X provides 4096 output steps. If voltage reference is 4.096V (where Gx = ‘0’), the LSb size is 1 mV. If a smaller output step size is desired, a lower external voltage reference is needed. Optional VREF VDD RSENSE MCP47FEBXX VCC+ R1 VTRIP Comp. VO C1 R2 I2C™ VOUT VCC– 2-wire FIGURE 8-3: Example Circuit Of Set Point or Threshold Calibration. EQUATION 8-1: VOUT AND VTRIP CALCULATIONS VOUT = VREF • G • DAC Register Value 2N  R2  V trip = V OUT  --------------------  R 1 + R 2  2015 Microchip Technology Inc. DS20005375A-page 73 MCP47FEBXX 8.3.1.2 8.4 Building a “Window” DAC When calibrating a set point or threshold of a sensor, typically only a small portion of the DAC output range is utilized. If the LSb size is adequate enough to meet the application’s accuracy needs, the unused range is sacrificed without consequences. If greater accuracy is needed, then the output range will need to be reduced to increase the resolution around the desired threshold. If the threshold is not near VREF, 2 • VREF, or VSS, then creating a “window” around the threshold has several advantages. One simple method to create this “window” is to use a voltage divider network with a pull-up and pull-down resistor. Figure 8-4 and Figure 8-6 illustrate this concept. Bipolar Operation Bipolar operation is achievable by utilizing an external operational amplifier. This configuration is desirable due to the wide variety and availability of op amps. This allows a general purpose DAC, with its cost and availability advantages, to meet almost any desired output voltage range, power and noise performance. Figure 8-5 illustrates a simple bipolar voltage source configuration. R1 and R2 allow the gain to be selected, while R3 and R4 shift the DAC's output to a selected offset. Note that R4 can be tied to VDD instead of VSS if a higher offset is desired. Optional VREF VDD Optional VREF VDD VCC+ RSENSE MCP47FEBXX R1 R3 VTRIP Comp. VOUT I2C™ 2-wire MCP47FEBXX VCC+ C1 R2 VO VCC+ R3 VOUT I2C™ VOA+ VO C1 R4 VCC– 2-wire VCC– R2 VIN R1 VCC– FIGURE 8-4: DAC. Single-Supply “Window” FIGURE 8-5: Digitally-Controlled Bipolar Voltage Source Example Circuit. EQUATION 8-2: VOUT AND VTRIP CALCULATIONS EQUATION 8-3: VOUT = VREF • G • DAC Register Value VOUT = VREF • G • 2N V OUT R23 + V 23 R1 V TRIP = --------------------------------------------R 1 + R23 Thevenin Equivalent VOA+ = R2R3 R23 = ------------------R2 + R3 DAC Register Value 2N VOUT • R4 R3 + R4 VO = VOA+ • (1 +  VCC+ R2  +  V CC- R 3  V23 = -----------------------------------------------------R 2 + R3 VOUT VOUT, VOA+, AND VO CALCULATIONS R2 R1 ) - VDD • ( R2 R1 ) R1 VTRIP R23 V23 DS20005375A-page 74  2015 Microchip Technology Inc. MCP47FEBXX 8.5 Selectable Gain and Offset Bipolar Voltage Output In some applications, precision digital control of the output range is desirable. Figure 8-6 illustrates how to use the DAC devices to achieve this in a bipolar or single-supply application. This circuit is typically used for linearizing a sensor whose slope and offset varies. The equation to design a bipolar “window” DAC would be utilized if R3, R4 and R5 are populated. 8.5.1 BIPOLAR DAC EXAMPLE Optional VCC+ Optional VREF VDD R5 MCP47FEBXX VO I2C™ 2-wire Since = 4096, 12-bit resolution is desired. The equation can be simplified to: R2 FIGURE 8-6: Bipolar Voltage Source with Selectable Gain and Offset. EQUATION 8-6: VOUT, VOA+, AND VO CALCULATIONS VOUT = VREF • G • VOA+ = DAC Register Value R3 + R4 EQUATION 8-5: R4 2 2.05V +  0.5  4.096V  ------------------------ = ------------------------------------------------------- = -- R3 + R 4  1.5  4.096V 3 If R4 = 20 k, then R3 = 10 k R2 R1 ) - VIN • ( Offset Adjust EQUATION 8-7: If R1 = 20 k and R2 = 10 k, the gain will be 0.5. Step 4: Next, solve for R3 and R4 by setting the DAC to 4096, knowing that the output needs to be +2.05V. 2N VOUT • R4 + VCC- • R5 VO = VOA+ • ( 1 + R2 1 ------ = --R1 2 VCC– C1 = 0.1 µF EQUATION 8-4: – R2 – 2.05 --------- = ----------------R1 4.096V C1 R4 R1 Step 2: Calculate the resolution needed: Step 3: The amplifier gain (R2/R1), multiplied by full-scale VOUT (4.096V), must be equal to the desired minimum output to achieve bipolar operation. Since any gain can be realized by choosing resistor values (R1 + R2), the VREF value must be selected first. If a VREF of 4.096V is used, solve for the amplifier’s gain by setting the DAC to 0, knowing that the output needs to be -2.05V. VOUT VIN Step 1: Calculate the range: +2.05V – (-2.05V) = 4.1V. 212 VOA+ VCC– An output step size of 1 mV, with an output range of ±2.05V, is desired for a particular application. 4.1V/1 mV = 4100 VCC+ R3 Thevenin Equivalent R2 R1 ) Gain Adjust BIPOLAR “WINDOW” DAC USING R4 AND R5 V CC+ R 4 + VCC- R5 V 45 = --------------------------------------------R 4 + R5 VOUT R 45 + V 45 R 3 VIN+ = --------------------------------------------R3 + R 45 R4R5 R45 = ------------------R4 + R5 R2 R2 V O = V IN+  1 + ------ – V A  ------ R1 R1 Offset Adjust Gain Adjust  2015 Microchip Technology Inc. DS20005375A-page 75 MCP47FEBXX 8.6 Designing a Double-Precision DAC 8.7 Building Programmable Current Source Figure 8-7 shows an example design of a single-supply voltage output capable of up to 24-bit resolution. This requires two 12-bit DACs. This design is simply a voltage divider with a buffered output. Figure 8-8 shows an example of building a programmable current source using a voltage follower. The current sensor resistor is used to convert the DAC voltage output into a digitally-selectable current source. As an example, if a similar application to the one developed in Section 8.5.1 “Bipolar DAC Example” required a resolution of 1 µV instead of 1 mV, and a range of 0V to 4.1V, then 12-bit resolution would not be adequate. The smaller RSENSE is, the less power dissipated across it. However, this also reduces the resolution that the current can be controlled. Step 1: Calculate the resolution needed: VDD (or VREF) Optional 4.1V/1 µV = 4.1 x 106. Since 222 = 4.2 x 106, 22-bit resolution is desired. Since DNL = ±1.0 LSb, this design can be attempted with the 12-bit DAC. Step 2: Since DAC1’s VOUT1 has a resolution of 1 mV, its output only needs to be “pulled” 1/1000 to meet the 1 µV target. Dividing VOUT0 by 1000 would allow the application to compensate for DAC1’s DNL error. Step 3: If R2 is 100, then R1 needs to be 100 k. Step 4: The resulting transfer function is shown in the equation of Example 8-8. VREF VDD VOUT MCP47FEBXX Load VCC+ IL Ib VCC– I2C™ 2-wire IL Ib = ---- RSENSE  V OUT  I L = ---------------  ------------R sense  + 1 where Common-Emitter Current Gain Optional VDD VREF MCP47FEBX2 (DAC0) I2C™ 2-wire FIGURE 8-8: Source. VOUT0 R1 Digitally-Controlled Current VCC+ VOUT Optional VREF VDD 0.1 µF R2 MCP47FEBX2 (DAC1) VCC– VOUT1 I2C 2-wire FIGURE 8-7: Simple Double Precision DAC using MCP47FEBX2. EQUATION 8-8: VOUT = VOUT CALCULATION VOUT0 * R2 + VOUT1 * R1 R1 + R2 Where: VOUT0 = (VREF  G  DAC0 Register Value)/4096 VOUT1 = (VREF  G  DAC1 Register Value)/4096 Gx = Selected Op Amp Gain DS20005375A-page 76  2015 Microchip Technology Inc. MCP47FEBXX 8.8 Serial Interface Communication Times Table 8-1 shows time/frequency of the supported operations of the I2C serial interface for the different serial interface operational frequencies. This, along with the VOUT output performance (such as slew rate), would be used to determine your application’s volatile DAC register update rate. TABLE 8-1: SERIAL INTERFACE TIMES / FREQUENCIES Command Code Operation HV Mode(6) C 1 C 0 Write Command (Normal and HighVoltage) 0 0 (3) Single 0 0 (3) Continuous Read Command (Normal and HighVoltage) (2) 1 1 (3) Random 1 1 (3) Continuous 1 1 (3) General Call Reset Command — — General Call Wake-up Command — — Enable Configuration Bit (High-Voltage) Command 1 0 Yes Single 1 0 Yes Continuous Disable Configuration Bit (High-Voltage) Command 0 1 Yes Single 0 1 Yes Continuous Note 1: 2: 3: 4: 5: 6: # of Bit Clocks (1) Data Update Rate (8-bit/10-bit/12-bit) (Data Words/Second) Comments 100 kHz 400 kHz 3.4 MHz(5) 38 2,632 10,526 89,474 27n + 11 3,559 14,235 120,996 48 2,083 8,333 70,833 18n + 11 4,762 19,048 161,905 Last Address 29 3,448 13,793 117,241 (3) Single 20 5,000 20,000 170,000 Note 4 (3) Single 20 5,000 20,000 170,000 Note 4 20 5,000 20,000 170,000 9n + 11 9,901 39,604 336,634 20 5,000 20,000 170,000 9n + 11 9,901 39,604 336,634 For 10 data words For 10 data words For 10 data words For 10 data words “n” indicates the number of times the command operation is to be repeated. This command is useful to determine when an EEPROM programming cycle has completed. This command can be either normal voltage or high voltage. Determined by General Call command byte after the I2C General Call address. There is a minimal overhead to enter into 3.4 MHz mode. Nonvolatile Registers can only use the “Single” mode.  2015 Microchip Technology Inc. DS20005375A-page 77 MCP47FEBXX Software I2C Interface Reset Sequence This technique is documented in AN1028. At times, it may become necessary to perform a Software Reset Sequence to ensure the MCP47FEBXX device is in a correct and known I2C interface state. This technique only resets the I2C state machine. This is useful if the MCP47FEBXX device powers-up in an incorrect state (due to excessive bus noise, etc), or if the master device is reset during communication. Figure 8-9 shows the communication sequence to software reset the device. S ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ S P Nine bits of ‘1’ Start bit Stop bit Start bit FIGURE 8-9: Format. Software Reset Sequence The 1st Start bit will cause the device to reset from a state in which it is expecting to receive data from the master device. In this mode, the device is monitoring the data bus in Receive mode and can detect if the Start bit forces an internal Reset. 8.10 Design Considerations In the design of a system with the MCP47FEBXX devices, the following considerations should be taken into account: • Power Supply Considerations • Layout Considerations 8.10.1 The typical application will require a bypass capacitor in order to filter high-frequency noise, which can be induced onto the power supply's traces. The bypass capacitor helps to minimize the effect of these noise sources on signal integrity. Figure 8-10 illustrates an appropriate bypass strategy. In this example, the recommended bypass capacitor value is 0.1 µF. This capacitor should be placed as close (within 4 mm) to the device power pin (VDD) as possible. The power source supplying these devices should be as clean as possible. If the application circuit has separate digital and analog power supplies, VDD and VSS should reside on the analog plane. The nine bits of ‘1’ are used to force a Reset of those devices that could not be reset by the previous Start bit. This occurs only if the MCP47FEBXX is driving an A bit on the I2C bus, or is in Output mode (from a Read command) and is driving a data bit of ‘0’ onto the I2C bus. In both of these cases, the previous Start bit could not be generated due to the MCP47FEBXX holding the bus low. By sending out nine ‘1’ bits, it is ensured that the device will see an A bit (the master device does not drive the I2C bus low to acknowledge the data sent by the MCP47FEBXX), which also forces the MCP47FEBXX to reset. The 2nd Start bit is sent to address the rare possibility of an erroneous write. This could occur if the master device was reset while sending a Write command to the MCP47FEBXX, AND then as the master device returns to normal operation and issues a Start condition, while the MCP47FEBXX is issuing an acknowledge. In this case, if the 2nd Start bit is not sent (and the Stop bit was sent) the MCP47FEBXX could initiate a write cycle. Note: The potential for this erroneous write ONLY occurs if the master device is reset while sending a Write command to the MCP47FEBxx. The Stop bit terminates the current I2C bus activity. The MCP47FEBXX waits to detect the next Start condition. DS20005375A-page 78 POWER SUPPLY CONSIDERATIONS VDD 0.1 µF VDD 0.1 µF VREF VOUT VSS FIGURE 8-10: Connections. SCL SDA PIC® Microcontroller Note: This sequence does not affect any other I2C devices which may be on the bus, as they should disregard this as an invalid command. MCP47FEBXX 8.9 VSS Typical Microcontroller  2015 Microchip Technology Inc. MCP47FEBXX LAYOUT CONSIDERATIONS Several layout considerations may be applicable to your application. These may include: • Noise • PCB Area Requirements 8.10.2.1 8.10.2.2 PACKAGE FOOTPRINT(1) TABLE 8-2: Package Noise Inductively-coupled AC transients and digital switching noise can degrade the input and output signal integrity, potentially masking the MCP47FEBXX’s performance. Careful board layout minimizes these effects and increases the Signal-to-Noise Ratio (SNR). Multi-layer boards utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the silicon is capable of providing. Particularly harsh environments may require shielding of critical signals. PCB Area Requirements In some applications, PCB area is a criteria for device selection. Table 8-2 shows the typical package dimensions and area for the different package options. Pins 8.10.2 8 Type Package Footprint Code Dimensions (mm) Area (mm2) Length Width TSSOP Note 1: ST 3.00 4.40 13.20 Does not include recommended land pattern dimensions. Dimensions are typical values. Separate digital and analog ground planes are recommended. In this case, the VSS pin and the ground pins of the VDD capacitors should be terminated to the analog ground plane. Note: Breadboards and wire-wrapped boards are not recommended.  2015 Microchip Technology Inc. DS20005375A-page 79 MCP47FEBXX NOTES: DS20005375A-page 80  2015 Microchip Technology Inc. MCP47FEBXX 9.0 DEVELOPMENT SUPPORT 9.2 Several additional technical documents are available to assist you in your design and development. These technical documents include Application Notes, Technical Briefs, and Design Guides. Table 9-2 shows some of these documents. Development support can be classified into two groups. These are: • Development Tools • Technical Documentation 9.1 Technical Documentation Development Tools Several development tools are available to assist in your design and evaluation of the MCP47FEBXX devices. The currently available tools are shown in Table 9-1. Figure 9-1 shows how the TSSOP20EV bond-out PCB can be populated to easily evaluate the MCP47FEBXX devices. The 8-pin and 20-pin TSSOP packages have the same pin pitch (0.65 mm BSC) and package width (4.40 mm typ.), and the 8-pin TSSOP package can be placed on the 20-pin TSSOP footprint. Device evaluation can use the PICkit™ Serial Analyzer to control the DAC output registers and state of the configuration, control and status register. The TSSOP20EV boards may be purchased directly from the Microchip web site at www.microchip.com. TABLE 9-1: DEVELOPMENT TOOLS (Note 1) Board Name Part # Comment 20-Pin TSSOP and SSOP Evaluation Board TSSOP20EV 14-pin SOIC/TSSOP/DIP Evaluation Board SOIC14EV SOIC-8 Evaluation Board SOIC8EV Note 1: Most Flexible option - Recommended Bond-out PCB Supports the PICkit™ Serial Analyzer. See the User’s Guide for additional information and requirements. TABLE 9-2: TECHNICAL DOCUMENTATION Application Note Number Title Literature # AN1326 Using the MCP4728 12-Bit DAC for LDMOS Amplifier Bias Control Applications DS01326 — Signal Chain Design Guide DS21825 — Analog Solutions for Automotive Applications Design Guide DS01005  2015 Microchip Technology Inc. DS20005375A-page 81 MCP47FEBXX MCP47FEBXX-A0E/ST installed in U3 (bottom 8 pins of TSSOP-20 footprint) Connected to Digital Ground (DGND) Plane Connected to Digital Power (VL) Plane 47FEB 1.0 µF VDD 0 4.7k  4.7k  VREF NC/VOUT1 0 Two blue wire jumpers to connect PICkit™ Serial interface (I2C™) to device pins DS20005375A-page 82 SCL LAT/HVC VOUT0 FIGURE 9-1: SDA VSS 1x6 male header, with 90° right angle MCP47FEBXX Evaluation Board Circuit Using TSSOP20EV.  2015 Microchip Technology Inc. MCP47FEBXX 10.0 PACKAGING INFORMATION 10.1 Package Marking Information 8-Lead TSSOP (4.4 mm) Example AAAG E449 256 XYWW Device Number Code Device Number Code MCP47FEB01A0-E/ST AAAG MCP47FEB12A0-E/ST AAAL MCP47FEB01A0T-E/ST AAAG MCP47FEB12A0T-E/ST AAAL MCP47FEB01A1-E/ST AAAU MCP47FEB12A1-E/ST AABG MCP47FEB01A1T-E/ST AAAU MCP47FEB12A1T-E/ST AABG MCP47FEB01A2-E/ST AAAV MCP47FEB12A2-E/ST AABH MCP47FEB01A2T-E/ST AAAV MCP47FEB12A2T-E/ST AABH MCP47FEB01A3-E/ST AAAW MCP47FEB12A3-E/ST AABJ MCP47FEB01A3T-E/ST AAAW MCP47FEB12A3T-E/ST AABJ MCP47FEB02A0-E/ST AAAK MCP47FEB21A0-E/ST AAAJ MCP47FEB02A0T-E/ST AAAK MCP47FEB21A0T-E/ST AAAJ MCP47FEB02A1-E/ST AABD MCP47FEB21A1-E/ST AABA MCP47FEB02A1T-E/ST AABD MCP47FEB21A1T-E/ST AABA MCP47FEB02A2-E/ST AABE MCP47FEB21A2-E/ST AABB MCP47FEB02A2T-E/ST AABE MCP47FEB21A2T-E/ST AABB MCP47FEB02A3-E/ST AABF MCP47FEB21A3-E/ST AABC MCP47FEB02A3T-E/ST AABF MCP47FEB21A3T-E/ST AABC MCP47FEB11A0-E/ST AAAH MCP47FEB22A0-E/ST AAAM MCP47FEB11A0T-E/ST AAAH MCP47FEB22A0T-E/ST AAAM MCP47FEB11A1-E/ST AAAX MCP47FEB22A1-E/ST AABK MCP47FEB11A1T-E/ST AAAX MCP47FEB22A1T-E/ST AABK MCP47FEB11A2-E/ST AAAY MCP47FEB22A2-E/ST AABL MCP47FEB11A2T-E/ST AAAY MCP47FEB22A2T-E/ST AABL MCP47FEB11A3-E/ST AAAZ MCP47FEB22A3-E/ST AABM MCP47FEB11A3T-E/ST AAAZ MCP47FEB22A3T-E/ST AABM Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2015 Microchip Technology Inc. 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