MCP48CXBXX
8/10/12-Bit Digital-to-Analog Converters, 1 LSb INL
Single/Dual Voltage Outputs with SPI Interface
MCP48CXBX1 (Single)
MSOP-10, DFN-10 (3 x 3)
VDD 1
10 SDI
CS 2
9 SCK
VREF 3
8 SDO
VOUT 4
7 VSS
NC 5
6 LAT/HVC
CS 1
VREF 2
13 SDI
14 NC
12 SCK
11 SDO
17 EP(1)
VOUT 3
10 VSS
9 LAT/HVC
NC 8
NC 7
NC 6
NC 5
NC 4
MCP48CXBX2 (Dual)
MSOP-10, DFN-10 (3 x 3)
VDD 1
CS 2
10 SDI
9 SCK
VREF 3
8 SDO
VOUT0 4
7 VSS
VOUT1 5
6 LAT/HVC(2)
13 SDI
14 NC
15 NC
16 VDD
QFN-16 (3 x 3)
CS 1
VREF0 2
VOUT0 3
12 SCK
11 SDO
17 EP(1)
10 VSS
9 LAT0/HVC
2:
NC 7
LAT1 8
VREF1 4
Note 1:
2019 Microchip Technology Inc.
15 NC
16 VDD
QFN-16 (3 x 3)
VOUT1 5
• Memory Options:
- Volatile Memory: MCP48CVBXX
- Nonvolatile Memory: MCP48CMBXX
• Operating Voltage Range:
- 2.7V to 5.5V – Full specifications
- 1.8V to 2.7V – Reduced device specifications
• Output Voltage Resolutions:
- 8-Bit: MCP48CXB0X (256 steps)
- 10-Bit: MCP48CXB1X (1024 steps)
- 12-Bit: MCP48CXB2X (4096 steps)
• Nonvolatile Memory (MTP) Size: 32 Locations
• 1 LSb Integral Nonlinearity (INL) Specification
• DAC Voltage Reference Source Options:
- Device VDD
- External VREF pin (buffered or unbuffered)
- Internal band gap (1.214V typical)
• Output Gain Options:
- 1x (Unity)
- 2x (available when not using internal VDD as
voltage source)
• Power-on/Brown-out Reset (POR/BOR)
Protection
• Power-Down Modes:
- Disconnects output buffer (High-Impedance)
- Selection of VOUT pull-down resistors
(100 k or 1 k)
• SPI Interface:
- Supports ‘00’ and ‘11’ modes
- 50 MHz write speed
- 25 MHz read speed
• Package Types:
- Dual: 16-lead 3 x 3 QFN, 10-lead MSOP,
10-lead 3 x 3 DFN
- Single: 16-lead 3 x 3 QFN, 10-lead MSOP,
10-lead 3 x 3 DFN
• Extended Temperature Range: -40°C to +125°C
Package Types
NC 6
Features
Exposed pad (substrate paddle).
This pin’s signal can be connected to DAC0
and/or DAC1.
DS20006160A-page 1
MCP48CXBXX
General Description
The MCP48CXBXX are single and dual-channel 8-bit,
10-bit, and 12-bit buffered voltage output
Digital-to-Analog Converters (DAC), with volatile or
MTP memory and an SPI serial interface.
The MTP memory can be written by the user up to 32
times, for each specific register. It requires a
high-voltage level on the HVC pin, typically 7.5V, in
order to successfully program the desired memory
location. The nonvolatile memory includes power-up
output values, device configuration registers and
general purpose memory.
The VREF pin, the device VDD or the internal band gap
voltage can be selected as the DAC’s reference
voltage. When VDD is selected, VDD is internally
connected to the DAC reference circuit.
When the VREF pin is used with an external voltage
reference, the user can select between a gain of 1 or 2
and can have the reference buffer enabled or disabled.
When the gain is 2, the VREF pin voltage should be
limited to a maximum of VDD/2.
These devices have a four-wire SPI-compatible serial
interface with speeds up to 50 MHz for write and
25 MHz for read operations.
Applications
•
•
•
•
•
Set Point or Offset Trimming
Sensor Calibration
Low-Power Portable Instrumentation
PC Peripherals
Data Acquisition Systems
MCP48CVBX1 Block Diagram (Single-Channel Output)
VDD
VSS
SCK
SDI
SDO
Memory
Power-up/Brown-out Control
VOLATILE (4 x 16)
DAC0
VREF
POWER-DOWN
GAIN
STATUS
SPI Serial Interface Module
and Control Logic
(WiperLock™ Technology)
CS
NONVOLATILE (13 x 16)
VIHH
LAT/HVC
LAT0
VDD
DAC0
VREF
POWER-DOWN
GAIN
WIPERLOCK™
PD1:PD0 and
VREF1:VREF0
Band gap
1.214V
VBG
GAIN
VREF1:VREF0
VOUT0
PD1:PD0
1 k
Resistor
Ladder
VDD
100 k
OPAMP
VREF0
VREF1:VREF0
Note 1: Available only on specific packages.
DS20006160A-page 2
2019 Microchip Technology Inc.
MCP48CXBXX
MCP48CVBX2 Block Diagram (Dual-Channel Output)
VDD
VSS
SCK
SDI
SDO
Memory
Power-up/Brown-out Control
VOLATILE (5 x 16)
DAC0 and DAC1
VREF
POWER-DOWN
GAIN
STATUS
SPI Serial Interface Module
and Control Logic
(WiperLock™ Technology)
CS
NONVOLATILE (14 x 16)
VIHH
LAT0/HVC
LAT0
VDD
DAC0 and DAC1
VREF
POWER-DOWN
GAIN
WIPERLOCK™
PD1:PD0 and
VREF1:VREF0
Band gap
1.214V
VBG
GAIN
VREF1:VREF0
VOUT0
PD1:PD0
1 k
Resistor
Ladder
VDD
100 k
OPAMP
VREF0(3)
VREF1:VREF0
LAT1(2)
LAT0(2)
VDD
PD1:PD0 and
VREF1:VREF0
GAIN
VBG
VREF1:VREF0
VOUT1
PD1:PD0
1 k
Resistor
Ladder
VDD
100 k
OPAMP
VREF1(3)
VREF1:VREF0
Note 1: Available only on specific packages.
2: On dual output devices, except those in a QFN16 package, the LAT0 pin is internally connected to LAT1
input of DAC1.
3: On dual output devices, except those in a QFN16 package, the VREF0 pin is internally connected to
VREF1 input of DAC1.
2019 Microchip Technology Inc.
DS20006160A-page 3
MCP48CXBXX
# of LAT Inputs(3)
Memory(2)
GP MTP Locations
MSOP, QFN, DFN
1
8
7Fh
1
1
RAM
—
MCP48CVB11
MSOP, QFN, DFN
1
10
1FFh
1
1
RAM
—
MCP48CVB21
MSOP, QFN, DFN
1
12
7FFh
1
1
RAM
—
QFN
2
8
7Fh
2
2
RAM
—
MSOP, DFN
2
8
7Fh
1
1
RAM
—
QFN
2
10
1FFh
2
2
RAM
—
MSOP, DFN
2
10
1FFh
1
1
RAM
—
QFN
2
12
7FFh
2
2
RAM
—
MCP48CVB02
MCP48CVB12
MCP48CVB22
Package Type
Resolution (bits)
MCP48CVB01
Device
# of Channels
# of VREF Inputs
Family Device Features
DAC Output
POR/BOR
Setting(1)
MSOP, DFN
2
12
7FFh
1
1
RAM
—
MCP48CMB01
MSOP, QFN, DFN
1
8
7Fh
1
1
MTP
8
MCP48CMB11
MSOP, QFN, DFN
1
10
1FFh
1
1
MTP
8
MCP48CMB21
MSOP, QFN, DFN
1
12
7FFh
1
1
MTP
8
QFN
2
8
7Fh
2
2
MTP
8
MSOP, DFN
2
8
7Fh
1
1
MTP
8
QFN
2
10
1FFh
2
2
MTP
8
MSOP, DFN
2
10
1FFh
1
1
MTP
8
QFN
2
12
7FFh
2
2
MTP
8
MSOP, DFN
2
12
7FFh
1
1
MTP
8
MCP48CMB02
MCP48CMB12
MCP48CMB22
Note 1:
2:
3:
The factory default value.
Each nonvolatile memory location can be written 32 times. For subsequent writes to the MTP, the device
will ignore the commands and the memory will not be modified.
If the product is a dual device and the package has only one LAT pin, it is associated with both DAC0 and
DAC1.
DS20006160A-page 4
2019 Microchip Technology Inc.
MCP48CXBXX
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
Voltage on VDD with respect to VSS ......................................................................................................... -0.6V to +6.5V
Voltage on all pins with respect to VSS ............................................................................................... -0.6V to VDD+0.3V
Input Clamp Current, IIK (VI < 0, VI > VDD, VI > VPP on HV pins) ........................................................................ ±20 mA
Output Clamp Current, IOK (VO < 0 or VO > VDD) ................................................................................................. ±20 mA
Maximum Current out of VSS pin
(Single) ..........................................................................................................50 mA
(Dual)...........................................................................................................100 mA
Maximum Current into VDD pin
(Single) ..........................................................................................................50 mA
(Dual)...........................................................................................................100 mA
Maximum Current sourced by the VOUT pin............................................................................................................20 mA
Maximum Current sunk by the VOUT pin.................................................................................................................20 mA
Maximum Current source/sunk by the VREF(0) pin (in Band Gap mode) ................................................................20 mA
Maximum Current sunk by the VREFx pin (when VREF is in Unbuffered mode) .....................................................175 µA
Maximum Current sourced by the VREFx pin............................................................................................................20 µA
Maximum Current sunk by the VREF pin ................................................................................................................125 µA
Maximum Output Current sunk by SDO Output pin ................................................................................................25 mA
Maximum Output Current sourced by SDO Output pin...........................................................................................25 mA
Total Power Dissipation(1) ....................................................................................................................................400 mW
ESD Protection on all pins ±6 kV (HBM)
±400V (MM)
±2 kV (CDM)
Latch-Up (per JEDEC JESD78A) at +125°C ..................................................................................................... ±100 mA
Storage Temperature ..............................................................................................................................-65°C to +150°C
Ambient Temperature with power applied ..............................................................................................-55°C to +125°C
Soldering Temperature of leads (10 seconds) ...................................................................................................... +300°C
Maximum Junction Temperature (TJ) .................................................................................................................... +150°C
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in the
operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
Note 1: Power dissipation is calculated as follows:
PDIS = VDD x {IDD - IOH} + {(VDD – VOH) x IOH} + (VOL x IOL)
2019 Microchip Technology Inc.
DS20006160A-page 5
MCP48CXBXX
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +1.000V to VDD, VSS = 0V, RL = 2 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Supply Voltage
Sym.
VDD
Min.
Typ.
Max.
Units
Conditions
2.7
—
5.5
V
1.8
—
2.7
V
DAC operation (reduced analog
specifications) and Serial Interface
VDD Voltage
(rising) to ensure device
Power-on Reset
VPOR
—
—
1.75
V
RAM retention voltage (VRAM) < VPOR
VDD voltages greater than the VPOR limit
ensure that the device is out of reset.
VDD Voltage
(falling) to ensure device
Brown-out Reset
VBOR
VRAM
—
1.61
V
RAM retention voltage (VRAM) < VBOR
VDD Rise Rate to ensure
Power-on Reset
VDDRR
Power-on Reset to
Output-Driven Delay
(Note 2)
TPOR2OD
(Note 3)
V/ms
—
—
130
µs
VDD rising, VDD > VPOR
Single Output
—
—
145
µs
VDD rising, VDD > VPOR
Dual Output
Note 2
This parameter is ensured by characterization.
Note 3
POR/BOR voltage trip point is not slope dependent. Hysteresis implemented with time delay.
DS20006160A-page 6
2019 Microchip Technology Inc.
MCP48CXBXX
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +1.000V to VDD, VSS = 0V,
RL = 2 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Supply Current
LAT/HVC Pin
Write Current(2)
Power-Down
Current
Note 2
Sym.
Min.
Typ.
Max.
Units
IDD
—
—
250
µA
Conditions
—
—
700
—
—
2300
—
—
350
—
—
800
Serial Interface Active
VRxB:VRxA = ‘10’(4),
10 MHz
VOUT is unloaded,
50 MHz(2) VREF = VDD = 5.5V
Volatile DAC
1 MHz
register = Midscale
(2)
10 MHz
—
—
2400
50 MHz(2)
—
—
160
µA
—
—
280
µA
IDD(MTP_WR)
—
—
6.40
mA
—
Serial Interface Inactive
(MTP Write Active),
VRxB:VRxA = ‘10’ (valid for all modes)
VDD = 5.5V, LAT/HVC = VIHH,
Write all ‘1’s to nonvolatile DAC0,
VOUT pins are unloaded.
IDDP
—
0.56
3.80
µA
—
PDxB:PDxA = ‘01’(5),
VRxB:VRxA = ‘10’,
VOUT not connected
Single 1 MHz
(2)
µA
Dual
Single Serial Interface Inactive
VRxB:VRxA = ‘10’, VREF = VDD = 5.5V
Dual
SCK = SDI = VSS,
VOUT is unloaded,
Volatile DAC register = Midscale
This parameter is ensured by characterization.
Note 4
Supply current is independent of current through the resistor ladder in mode VRxB:VRxA = ‘10’.
Note 5
The PDxB:PDxA = ‘01’, ‘10’, and ‘11’ configurations should have the same current.
2019 Microchip Technology Inc.
DS20006160A-page 7
MCP48CXBXX
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +1.000V to VDD, VSS = 0V,
RL = 2 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
Resistor Ladder
Resistance(6)
RL
63.9
71
78.1
k
Resolution
(# of Resistors and
# of Taps)
(see B.1 “Resolution”)
N
Nominal VOUT
Match(10)
VOUT Tempco(2)
(see B.19 “VOUT
Temperature
Coefficient”)
VREF Pin
Input Voltage Range
Conditions
VRxB:VRxA = ‘10’,
VREF = VDD
256
Taps
8-bit No Missing Codes
1024
Taps
10-bit No Missing Codes
4096
Taps
12-bit No Missing Codes
|VOUT - VOUTMEAN|
/VOUTMEAN
—
0.016
0.3
VOUT/T
—
3
—
VREF
VSS
—
VDD
%
1.8V VDD 5.5V(2)
ppm/°C Code = Mid-scale
(7Fh, 1FFh or 7FFh),
VRxB:VRxA =
‘00’, ‘10’, and ‘11’
V
1.8V VDD 5.5V(1)
Note 1
This parameter is ensured by design.
Note 2
This parameter is ensured by characterization.
Note 6
Resistance is defined as the resistance between the VREF pin (mode VRxB:VRxA = ‘10’) to VSS pin. For
dual-channel devices (MCP48CXBX2), this is the effective resistance of each resistor ladder. The
resistance measurement is one of the two resistor ladders measured in parallel.
Note 10
Variation of one output voltage to mean output voltage for dual devices only.
DS20006160A-page 8
2019 Microchip Technology Inc.
MCP48CXBXX
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +1.000V to VDD, VSS = 0V,
RL = 2 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
Zero-Scale Error
(Code = 000h)
(see B.5
“Zero-Scale
Error (EZS)”)
EZS
—
—
0.375
LSb
8-bit
VRxB:VRxA = ‘10’, G = ‘0’,
VREF = VDD, No Load.
—
—
1.5
LSb
10-bit
VRxB:VRxA = ‘10’, G = ‘0’,
VREF = VDD, No Load.
—
—
6
LSb
12-bit
VRxB:VRxA = ‘10’, G = ‘0’,
VREF = VDD, No Load.
Offset Error
(see B.7 “Offset
Error (EOS)”)
Conditions
See Section 2.0 “Typical
Performance Curves”(2)
LSb
VRxB:VRxA = ‘10’, G = ‘1’,
VREF = 0.5 X VDD, No Load.
See Section 2.0 “Typical
Performance Curves”(2)
LSb
VRxB:VRxA = ‘01’, G = ‘0’, G = ‘1’,
VDD = 1.8-5.5V, No Load.
EOS
-6
±0.7
+6
mV
Offset Voltage
Temperature
Coefficient(2, 9)
VOSTC
—
±5
—
µV/°C
Full-Scale Error
(see B.4
“Full-Scale
Error (EFS)”)
EFS
—
—
2.5
LSb
8-bit
VRxB:VRxA = ‘10’, G = ‘0’,
VREF = VDD, No Load.
—
—
9
LSb
10-bit
VRxB:VRxA = ‘10’, G = ‘0’,
VREF = VDD, No Load.
—
—
35
LSb
12-bit
VRxB:VRxA = ‘10’, G = ‘0’,
VREF = VDD, No Load.
Gain Error
(see B.9 “Gain
Error (EG)”)(7)
EG
See Section 2.0 “Typical
Performance Curves”(2)
LSb
VRxB:VRxA = ‘10’, G = ‘1’,
VREF = 0.5 X VDD, No Load.
See Section 2.0 “Typical
Performance Curves”(2)
LSb
VRxB:VRxA = ‘01’, G = ‘0’, G = ‘1’,
VDD = 1.8-5.5V, No Load.
-1
-1
-1
Gain-Error Drift(2) G/°C
(see B.10 “Gain
Error Drift
(EGD)”)(9)
VRxB:VRxA = ‘10’, Gx = ‘0’, No Load
8-bit: Code = 4; 10-bit: Code = 16;
12-bit: Code = 64
—
±0.1
±0.1
±0.1
-6
+1
+1
+1
—
% of
FSR
8-bit
VRxB:VRxA = ‘10’, G = ‘0’,
Code = 252,
VREF = VDD, No Load
% of
FSR
10-bit
VRxB:VRxA = ‘10’, G = ‘0’,
Code = 1008,
VREF = VDD, No Load
% of
FSR
12-bit
VRxB:VRxA = ‘10’, G = ‘0’,
Code = 4032,
VREF = VDD, No Load
ppm/°C
Note 2
This parameter is ensured by characterization.
Note 7
This gain error does not include the offset error.
Note 9
Code range dependent on resolution: 8-bit, codes 4 to 252; 10-bit, codes 16 to 1008; 12-bit, codes 64 to 4032.
2019 Microchip Technology Inc.
DS20006160A-page 9
MCP48CXBXX
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +1.000V to VDD, VSS = 0V,
RL = 2 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
Total Unadjusted Error
(see B.6 “Total
Unadjusted Error
(ET)”)(2, 9)
ET
-2.5
—
0.75
LSb
8-bit
VRxB:VRxA = ‘10’, G = ‘0’,
VREF = VDD, No Load.
-9
—
3
LSb
10-bit
VRxB:VRxA = ‘10’, G = ‘0’,
VREF = VDD, No Load.
-35
—
12
LSb
12-bit
VRxB:VRxA = ‘10’, G = ‘0’,
VREF = VDD, No Load.
See Section 2.0 “Typical
Performance Curves”
LSb
VRxB:VRxA = ‘10’, G = ‘1’,
VREF = 0.5 X VDD, No Load.
See Section 2.0 “Typical
Performance Curves”
LSb
VRxB:VRxA = ‘01’, G = ‘0’, G = ‘1’,
VDD = 1.8-5.5V, No Load.
Integral
Nonlinearity
(see B.11 “Integral
Nonlinearity
(INL)”)(9)
Differential
Nonlinearity
(see B.12
“Differential
Nonlinearity
(DNL)”)(9)
INL
DNL
Conditions
-0.10
—
+0.10
LSb
8-bit
VRxB:VRxA = ‘10’, G = ‘0’,
VREF = VDD, No Load.
-0.25
—
+0.25
LSb
10-bit
VRxB:VRxA = ‘10’, G = ‘0’,
VREF = VDD, No Load.
-1
—
+1
LSb
12-bit
VRxB:VRxA = ‘10’, G = ‘0’,
VREF = VDD, No Load.
See Section 2.0 “Typical
Performance Curves”(2)
LSb
VRxB:VRxA = ‘10’, G = ‘1’,
VREF = 0.5 X VDD, No Load.
See Section 2.0 “Typical
Performance Curves”(2)
LSb
VRxB:VRxA = ‘01’, G = ‘0’, G = ‘1’,
VDD = 1.8-5.5V, No Load.
-0.1
—
+0.1
LSb
8-bit
VRxB:VRxA = ‘10’, G = ‘0’,
VREF = VDD, No Load.
-0.25
—
+0.25
LSb
10-bit
VRxB:VRxA = ‘10’, G = ‘0’,
VREF = VDD, No Load.
-1.0
—
+1.0
LSb
12-bit
VRxB:VRxA = ‘10’, G = ‘0’,
VREF = VDD, No Load.
See Section 2.0 “Typical
Performance Curves”(2)
LSb
VRxB:VRxA = ‘10’, G = ‘1’,
VREF = 0.5 X VDD, No Load.
See Section 2.0 “Typical
Performance Curves”(2)
LSb
VRxB:VRxA = ‘01’, G = ‘0’, G = ‘1’,
VDD = 1.8-5.5V, No Load.
Note 2 This parameter is ensured by characterization.
Note 9 Code range dependent on resolution: 8-bit, codes 4 to 252; 10-bit, codes 16 to 1008; 12-bit, codes 64 to 4032.
DS20006160A-page 10
2019 Microchip Technology Inc.
MCP48CXBXX
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +1.000V to VDD, VSS = 0V,
RL = 2 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
-3 dB Bandwidth
(see B.16 “-3 dB
Bandwidth”)
BW
—
60
—
kHz
VREF = 3.0V+/-2V,
VRxB:VRxA = ‘10’, Gx = ‘0’
—
35
—
kHz
VREF = 3.5V+/-1.5V,
VRxB:VRxA = ‘10’, Gx = ‘1’
°C
Output Amplifier (Op Amp)
Phase Margin(1)
PM
—
58
—
Slew Rate
SR
—
0.15
—
Load Regulation
—
—
130
—
—
320
—
6
10
14
mA
Short to
VSS
DAC code = Full Scale
6
10
14
mA
Short to
VDD
DAC code = Zero Scale
tSETTLING
—
16
—
µs
RL = 2 k
1.8 < VDD < 5.5V
Short-Circuit Current
Settling Time(8)
ISC_OA
V/µs
RL =
RL = 2 k
µV/mA 1 mA < I < 6 mA
VDD = 5.5V,
µV/mA -6 mA < I < -1 mA DAC code =
Midscale
Internal Band Gap
VBG
1.180
1.214
1.260
V
Short Circuit Current
Band Gap Voltage
ISC_BG
6
10
14
mA
Short to VSS
6
10
14
mA
Short to VDD
Band Gap Voltage
Temperature
Coefficient
VBGTC
—
16
—
ppm/°C 1.8V VDD 5.5V
IBG
—
30
—
μV/mA 1 mA < I < 6 mA
—
390
—
Band Gap mode VREF
pin load regulation
VDD = 5.5V,
DAC
code = MidμV/mA -6 mA < I < -1 mA
scale
Note 1
This parameter is ensured by design.
Note 8
Within 1/2 LSb of the final value, when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in a
12-bit device.)
2019 Microchip Technology Inc.
DS20006160A-page 11
MCP48CXBXX
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +1.000V to VDD, VSS = 0V,
RL = 2 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
External Reference (VREF)
Input Range(1)
VREF
VSS
—
VDD – 0.04
V
VRxB:VRxA = ‘10’
(Unbuffered mode)
Input Capacitance
CREF
—
29
—
pF
VRxB:VRxA = ‘10’
(Unbuffered mode)
Input Impedance
RL
k
2.7V
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