MCP6033T-E/SN

MCP6031/2/3/4 0.9 µA, High-Precision Op Amps Features Description • • • • • • • • The Microchip Technology Inc. MCP6031/2/3/4 family of operational amplifiers (op amps) operates with a single-supply voltage as low as 1.8V, while drawing ultra-low quiescent current per amplifier (0.9 µA, typical). This family also has low input offset voltage (150 µV, maximum) and rail-to-rail input and output operation. This combination of features supports battery-powered and portable applications. Rail-to-Rail Input and Output Low Offset Voltage: 150 µV (maximum) Ultra-Low Quiescent Current: 0.9 µA (typical) Wide Power Supply Voltage: 1.8V to 5.5V Gain Bandwidth Product: 10 kHz (typical) Unity Gain Stable Chip Select (CS) capability: MCP6033 Extended Temperature Range: - -40°C to +125°C • No Phase Reversal Applications The MCP6031/2/3/4 family is offered in single (MCP6031), single with power-saving Chip Select (CS) input (MCP6033), dual (MCP6032) and quad (MCP6034) configurations. Toll Booth Tags Wearable Products Battery Current Monitoring Sensor Conditioning Battery Powered The MCP6031/2/3/4 family is designed with Microchip’s advanced CMOS process. All devices are available in the extended temperature range, with a power supply range of 1.8V to 5.5V. SPICE Macro Models FilterLab® Software Mindi™ Circuit Designer and Simulator MAPS (Microchip Advanced Part Selector) Analog Demonstration and Evaluation Boards Application Notes Package Types MCP6031 DFN, SOIC, MSOP NC 1 VIN- 2 VIN+ 3 IDD + MCP6031 VOUT VOUT 1 VSS 2 VIN+ 3 7 VDD 6 VOUT + VSS 4 5 NC 5 VDD VOUTA 1 4 VIN- VINA+ 3 VINA- 2 14 VOUTD 11 VSS VINA+ 3 VSS 4 – + VINB- 6 8 VDD V OUTB 7 7 VOUTB – + High-Side Battery Current Sensor VOUTA 1 VINA- 2 VINB+ 5 – + VDD – VOUT = ----------------------------------------- 10 V/V    10   MCP6032 SOIC, MSOP 13 VIND12 VIND+ VDD 4 1 M  2007-2019 Microchip Technology Inc. 8 CS – MCP6034 SOIC, TSSOP – I DD NC 1 VIN- 2 VIN+ 3 – + 100 k 6 VOUT 5 NC MCP6031 SOT-23 VDD 10 + VSS 4 Typical Application 1.4V to 5.5V 8 NC 7 VDD – MCP6033 DFN, SOIC, MSOP – + • • • • • • – + Design Aids + – • • • • • The MCP6031/2/3/4 family is unity gain stable and has a gain bandwidth product of 10 kHz (typical). These specifications make these op amps appropriate for low-frequency applications, such as battery current monitoring and sensor conditioning. 10 VINC+ 9 VINC8 VOUTC 6 VINB5 VINB+ DS20002041C-page 1 MCP6031/2/3/4 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† VDD – VSS ........................................................................7.0V Current at Input Pins .....................................................±2 mA Analog Inputs (VIN+, VIN-)†† .......... VSS – 1.0V to VDD + 1.0V All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V Difference Input Voltage ...................................... |VDD – VSS| Output Short-Circuit Current .................................continuous Current at Output and Supply Pins ............................±30 mA Storage Temperature.....................................-65°C to +150°C Maximum Junction Temperature (TJ) .......................... +150°C ESD Protection on All Pins (HBM; MM)   4 kV; 400V † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. †† See Section 4.1.2 “Input Voltage and Current Limits”. DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated: VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 1 Mto VL and CS is tied low. (Refer to Figure 1-2 and Figure 1-3.) Parameters Sym Min VOS Typ Max Units Conditions Input Offset -150 — +150 Input Offset Drift with Temperature VOS/TA — ±3.0 — Power Supply Rejection Ratio PSRR 70 88 — dB IB — ±1.0 100 pA IB — 60 — pA TA = +85°C IB — 2000 5000 pA TA = +125°C Input Offset Voltage µV VDD = 3.0V, VCM = VDD/3 µV/°C TA = -40°C to +125°C, VDD = 3.0V, VCM = VDD/3 VCM = VSS Input Bias Current and Impedance Input Bias Current Input Offset Current IOS — ±1.0 — pA Common-mode Input Impedance ZCM — 1013||6 — ||pF Differential Input Impedance ZDIFF — 1013||6 — ||pF Common-mode Input Voltage Range VCMR VSS –0.3 — VDD + 0.3 V Common-mode Rejection Ratio CMRR 70 95 — dB VCM = -0.3V to 2.1V, VDD = 1.8V 72 93 — dB VCM = -0.3V to 5.8V, VDD = 5.5V 70 89 — dB VCM = 2.75V to 5.8V, VDD = 5.5V 72 93 — dB VCM = -0.3V to 2.75V, VDD = 5.5V 95 115 — dB 0.2V < VOUT < (VDD – 0.2V), RL = 50 k to VL Common-mode Open-Loop Gain DC Open-Loop Gain (Large Signal) DS20002041C-page 2 AOL  2007-2019 Microchip Technology Inc. MCP6031/2/3/4 DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise indicated: VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 1 Mto VL and CS is tied low. (Refer to Figure 1-2 and Figure 1-3.) Parameters Sym Min Typ Max Units — VDD – 10 mV Conditions Output Maximum Output Voltage Swing Output Short-Circuit Current VOL, VOH VSS + 10 ISC RL = 50 k to VL, 0.5V input overdrive — ±5 — mA VDD = 1.8V — ±23 — mA VDD = 5.5V VDD 1.8 — 5.5 V IQ 0.4 0.9 1.35 µA Power Supply Supply Voltage Quiescent Current per Amplifier IO = 0, VCM = VDD, VDD = 5.5V AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated: TA = +25°C, VDD = +1.8 to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, CL = 60 pF, RL = 1 Mto VL and CS is tied low. (Refer to Figure 1-2 and Figure 1-3.) Parameters Sym Min Typ Max Units Conditions AC Response Gain Bandwidth Product GBWP — 10 — kHz Phase Margin PM — 65 — ° Slew Rate SR — 4.0 — V/ms Input Noise Voltage Eni — 3.9 — µVp-p f = 0.1 Hz to 10 Hz Input Noise Voltage Density eni — 165 — nV/Hz f = 1 kHz Input Noise Current Density ini — 0.6 — fA/Hz f = 1 kHz G = +1 V/V Noise  2007-2019 Microchip Technology Inc. DS20002041C-page 3 MCP6031/2/3/4 MCP6033 CHIP SELECT ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +1.8V to +5.5V, VSS =GND, TA = +25°C, VCM = VDD/2, VOUT = VDD/2, VL = VDD/2, CL = 60 pF, RL = 1 Mto VL and CS is tied low (Refer to Figure 1-1). Parameters Sym Min Typ Max Units Conditions CS Logic Threshold, Low VIL VSS — 0.2 VDD V CS Input Current, Low ICSL — -10 — pA CS Logic Threshold, High VIH 0.8 VDD — VDD V CS Input Current, High ICSH — 10 — pA CS = VDD ISS — -400 — pA CS = VDD IO(LEAK) — 10 — pA CS = VDD CS Low to Amplifier Output Turn-on Time tON — 4 100 ms CS  0.2 VDD to VOUT = 0.9 VDD/2, G = +1 V/V, VIN = VDD/2, RL = 50 kto VL = VSS CS High to Amplifier Output High-Z tOFF — 10 — µs CS  0.8 VDD to VOUT = 0.1 VDD/2, G = +1 V/V, VIN = VDD/2, RL = 50 kto VL = VSS VHYST — 0.3 VDD — V CS Low Specifications CS = VSS CS High Specifications GND Current Amplifier Output Leakage CS Dynamic Specifications CS Hysteresis CS VIL VIH tON VOUT High-Z High-Z ISS -400 pA (typical) ICS tOFF -0.9 µA (typical) -400 pA (typical) 10 pA (typical) FIGURE 1-1: Timing Diagram for the CS Pin on the MCP6033. DS20002041C-page 4  2007-2019 Microchip Technology Inc. MCP6031/2/3/4 TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated: VDD = +1.8V to +5.5V and VSS = GND. Parameters Sym Min Typ Max Units Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Thermal Resistance, 5-Lead SOT-23 JA — 256 — °C/W Thermal Resistance, 8-Lead DFN JA — 84 — °C/W Thermal Resistance, 8-Lead SOIC JA — 163 — °C/W Thermal Resistance, 8-Lead MSOP JA — 206 — °C/W Thermal Resistance, 14-Lead SOIC JA — 120 — °C/W Thermal Resistance, 14-Lead TSSOP JA — 100 — °C/W Conditions Temperature Ranges Note 1 Thermal Package Resistances Note 1: 1.1 The internal junction temperature (TJ) must not exceed the absolute maximum specification of +150°C. Test Circuits The test circuits used for the DC and AC tests are shown in Figure 1-2 and Figure 1-3. The bypass capacitors are laid out according to the rules discussed in Section 4.6 “Supply Bypass”. VDD 2.2 µF VDD/2 VDD RN 2.2 µF VIN RN + VOUT CL – VDD/2 RG VOUT MCP603X CL – 0.1 µF MCP603X + 0.1 µF RL VL VIN RG RL VL RF FIGURE 1-3: AC and DC Test Circuit for Most Inverting Gain Conditions. RF FIGURE 1-2: AC and DC Test Circuit for Most Noninverting Gain Conditions.  2007-2019 Microchip Technology Inc. DS20002041C-page 5 MCP6031/2/3/4 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated: TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 1 Mto VL, CL = 60 pF and CS is tied low. 400 -300 200 100 -300 8% 6% 4% 2% 0% 0 6 12 18 24 30 250 200 150 100 50 0 -50 -100 -150 -200 -250 VDD = 3.0V DS20002041C-page 6 2.2 2.0 1.8 1.4 1.2 1.0 0.8 0.6 0.4 VDD = 5.5V VDD = 1.8V 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Input Offset Drift with Temperature (μV/°C) FIGURE 2-3: Input Offset Voltage Drift with VDD = 3.0V and TA  +85°C. 0.2 VDD = 1.8V -0.4 Input Offset Voltage (μV) 640 Samples VDD = 3.0V VCM = VDD/3 TA = +85°C to +125°C -6 6.0 -200 FIGURE 2-5: Input Offset Voltage vs. Common-mode Input Voltage with VDD = 1.8V. 14% -30 -24 -18 -12 5.5 0 -100 Common Mode Input Voltage (V) FIGURE 2-2: Input Offset Voltage Drift with VDD = 3.0V and TA  +85°C. 10% 5.0 TA = -40°C TA = +25°C TA = +85°C TA = +125°C 300 -400 12% 4.5 4.0 400 640 Samples VDD = 3.0V VCM = VDD/3 TA = -40°C to +85°C -20 -16 -12 -8 -4 0 4 8 12 16 20 Input Offset Drift with Temperature (μV/°C) Percentage of Occurences 3.5 FIGURE 2-4: Input Offset Voltage vs. Common-mode Input Voltage with VDD = 5.5V. Input Offset Voltage (μV) 22% 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% Input Offset Voltage with Common Mode Input Voltage (V) 1.6 FIGURE 2-1: VDD = 3.0V. 3.0 -0.5 -150 -120 -90 -60 -30 0 30 60 90 120 150 Input Offset Voltage (μV) 2.5 VDD = 5.5V -400 0% Percentage of Occurences -200 2.0 2% 1.5 4% 0 -100 1.0 6% 100 0.5 8% 200 0.0 10% TA = -40°C TA = +25°C TA = +85°C TA = +125°C 300 -0.2 12% 0.0 640 Samples VDD = 3.0V VCM = VDD/3 Input Offset Voltage (μV) Percentage of Occurences 14% Output Voltage (V) FIGURE 2-6: Output Voltage. Input Offset Voltage vs.  2007-2019 Microchip Technology Inc. MCP6031/2/3/4 Note: Unless otherwise indicated: TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 1 Mto VL, CL = 60 pF and CS is tied low. PSRR, CMRR (dB) Input Noise Voltage Density (nV/ Hz) 1,000 100 0.1 1E-1 1 1E+0 10 1E+1 100 1E+2 1k 1E+3 10k 1E+4 100k 1E+5 110 105 100 95 90 85 80 75 70 65 60 10000 Input Bias and Offset Currents (pA) 175 150 125 100 75 50 f = 1 kHz VDD = 5.5V 25 10 CMRR, PSRR (dB) Input Bias Current (pA) VDD = 5.5V Input Offset Current 45 65 85 105 Ambient Temperature (°C) 125 FIGURE 2-11: Input Bias, Offset Currents vs. Ambient Temperature. 10000 CMRR 125 Input Bias Current 100 25 PSRR- PSRR+ 100 VDD = 5.5V VCM = VDD 1 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 FIGURE 2-8: Input Noise Voltage Density vs. Common-mode Input Voltage. 0 25 50 75 Ambient Temperature (°C) 1000 Common Mode Input Voltage (V) 100 90 80 70 60 50 40 30 20 10 0 -25 FIGURE 2-10: Common-mode Rejection Ratio, Power Supply Rejection Ratio vs. Ambient Temperature. 200 -0.5 Input Noise Voltage Density (nV/Hz) Input Noise Voltage Density CMRR (VDD = 5.5V, VCM = -0.3V to 5.8V) PSRR (VDD = 1.8V to 5.5V, VCM = VSS) -50 Frequency (Hz) FIGURE 2-7: vs. Frequency. CMRR (VDD = 1.8V, VCM = -0.3V to 2.1V) 1000 VDD = 5.5V TA = +125°C 100 TA = +85°C 10 0.1 1 10 Frequency (Hz) 100 1000 FIGURE 2-9: Common-mode Rejection Ratio, Power Supply Rejection Ratio vs. Frequency.  2007-2019 Microchip Technology Inc. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Input Voltage (V) FIGURE 2-12: Input Bias Current vs. Common-mode Input Voltage. DS20002041C-page 7 MCP6031/2/3/4 VDD = 5.5V @ VCM = VDD VDD = 1.8V @ VCM = VDD VDD = 5.5V @ VCM = VSS VDD = 1.8V @ VCM = VSS -50 -25 0 25 50 75 100 Open-Loop Gain 100 80 Open-Loop Phase -90 40 -120 20 -150 0 -180 VDD = 5.5V Ambient Temperature (°C) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 FIGURE 2-16: Frequency. DC Open-Loop Gain (dB) VCM = VDD 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 TA = +125°C TA = +85°C TA = +25°C TA = -40°C 0.0 Quiescent Current (μA/Amplifier) FIGURE 2-13: Quiescent Current vs Ambient Temperature. DC Open-Loop Gain (dB) Power Supply Voltage (V) FIGURE 2-15: Quiescent Current vs. Power Supply Voltage with VCM = VSS. 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 TA = +125°C TA = +85°C TA = +25°C TA = -40°C 0.0 Quiescent Current (μA/Amplifier) 10 Open-Loop Gain, Phase vs. RL = 50 kΩ VSS + 0.2V < VOUT < VDD - 0.2V 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 FIGURE 2-17: DC Open-Loop Gain vs. Power Supply Voltage. VCM = VSS DS20002041C-page 8 -210 1k 10k 100 100 100 100k 1E+ 00 05 Frequency (Hz) 0 1 Power Supply Voltage VDD (V) FIGURE 2-14: Quiescent Current vs. Power Supply Voltage with VCM = VDD. 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 130 125 120 115 110 105 100 95 90 85 80 1.5 Power Supply Voltage (V) -60 60 -20 0.001 0.01 0.1 0 0.01 125 -30 Open-Loop Phase (°) 0 120 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 Open-Loop Gain (V/V) Quiescent Current (μA/Amplifier) Note: Unless otherwise indicated: TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 1 Mto VL, CL = 60 pF and CS is tied low. 130 125 VDD = 5.5V 120 115 110 105 VDD = 1.8V 100 95 90 Large Signal AOL 85 RL = 50 kΩ 80 0.00 0.05 0.10 0.15 0.20 0.25 Output Voltage Headroom VDD - VOUT or VOUT - VSS (V) FIGURE 2-18: DC Open-Loop Gain vs. Output Voltage Headroom.  2007-2019 Microchip Technology Inc. MCP6031/2/3/4 Gain Bandwidth Product (kHz) 120 110 100 90 80 70 Input Referred 60 100 1,000 Frequency (Hz) Gain Bandwidth Product Phase Margin VDD = 5.5V G = +1 V/V 60 50 Gain Bandwidth Product VDD = 5.5V G = +1 V/V -50 40 30 20 10 0 -25 0 25 50 75 100 125 Ambient Temperature (°C) FIGURE 2-21: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature.  2007-2019 Microchip Technology Inc. -25 0 25 50 75 100 Ambient Temperature (°C) 30 TA = -40°C TA = +25°C TA = +85°C TA = +125°C 25 20 15 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) FIGURE 2-23: Ouput Short-Circuit Current vs. Power Supply Voltage. Output Voltage Swing (V 80 70 VDD = 1.8V G = +1 V/V FIGURE 2-22: Gain Bandwidth Product, Phase Margin vs. Ambient Temperature. P-P ) 90 Phase Margin (°) Gain Bandwidth Product (kHz) FIGURE 2-20: Gain Bandwidth Product, Phase Margin vs. Common-mode Input Voltage. Phase Margin Gain Bandwidth Product -50 Common Mode Input Voltage (V) 20 18 16 14 12 10 8 6 4 2 0 Phase Margin 90 80 70 60 50 40 30 20 10 0 125 35 Phase Margin (°) 180 160 140 120 100 80 60 40 20 0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Gain Bandwidth Product (kHz) FIGURE 2-19: Channel-to-Channel Separation vs. Frequency ( MCP6032/4 only). 20 18 16 14 12 10 8 6 4 2 0 20 18 16 14 12 10 8 6 4 2 0 10,000 Output Short Circuit Current (mA) Channel-to-Channel Seperation (dB) 130 Phase Margin (°) Note: Unless otherwise indicated: TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 1 Mto VL, CL = 60 pF and CS is tied low. 10 VDD = 5.5V VDD = 3.0V VDD = 1.8V 1 0.1 10 FIGURE 2-24: Frequency. 1K 100 1000 Frequency (Hz) 10K 10000 Output Voltage Swing vs. DS20002041C-page 9 MCP6031/2/3/4 Note: Unless otherwise indicated: TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 1 Mto VL, CL = 60 pF and CS is tied low. VDD - VOH @ VDD = 1.8V VOL - VSS @ VDD = 1.8V 100 10 VDD - VOH @ VDD = 5.5V VOL - VSS @ VDD = 5.5V 1 10μ 1m 100µ Output Current (A) Time (100 μs/Div) VDD - VOH VSS - VOL -25 FIGURE 2-28: Pulse Response. Output Voltage (20 mV/div) Output Voltage Headroom VDD - V OH or V SS - V OL (mV) VDD = 5.5V RL = 50 kΩ -50 0 25 50 75 100 Ambient Temperature (°C) FIGURE 2-29: Response. Output Voltage (V) Slew Rate (V/ms) Falling Edge, VDD = 5.5V Falling Edge, VDD = 1.8V 5.0 4.0 3.0 Rising Edge, VDD = 5.5V Rising Edge, VDD = 1.8V 1.0 -50 -25 0 25 50 75 Ambient Temperature (°C) FIGURE 2-27: Temperature. DS20002041C-page 10 100 VDD = 5.5V G = -1 V/V Time (100 μs/Div) 7.0 2.0 Small-Signal Noninverting 125 FIGURE 2-26: Output Voltage Headroom vs. Ambient Temperature. 6.0 VDD = 5.5V G = +1 V/V 10m FIGURE 2-25: Output Voltage Headroom vs. Output Current. 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Output Voltage (20 mV/div) Output Voltage Headroom VDD - V OH, V OL - V SS (mV) 1000 125 Slew Rate vs. Ambient Small-Signal Inverting Pulse 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 VDD = 5.5V G = +1 V/V Time (0.5 ms/div) FIGURE 2-30: Pulse Response. Large-Signal Noninverting  2007-2019 Microchip Technology Inc. MCP6031/2/3/4 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Internal CS Switch Ouptut (V) Output Voltage (V) Note: Unless otherwise indicated: TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 1 Mto VL, CL = 60 pF and CS is tied low. VDD = 5.5V G = -1 V/V 4.0 2.5 1.5 0.5 VDD = 3.0V 1.8 VOUT Ouptut Voltage (V) Output Voltage (V) Output High-Z 0.0 3.0 2.0 1.0 VDD = 5.0V G = +2 V/V Output On 1.5 Hysteresis 1.2 0.9 CS Input High to Low 0.6 CS Input Low to High 0.3 Output High-Z 0.0 -1.0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 Chip Select Voltage (V) Time (2 ms/div) FIGURE 2-32: The MCP6031/2/3/4 Family Shows No Phase Reversal. 6.0 1.2 VDD = 5.5V G = +1 V/V RL = 50 kΩ to VSS 4.0 Output On Output High-Z 3.0 2.0 Output High-Z 1.0 0.0 Time (1 ms/div) FIGURE 2-33: Chip Select (CS) to Amplifier Output Response Time (MCP6033 only).  2007-2019 Microchip Technology Inc. Ouptut Voltage (V) 1.5 5.0 Chip Select FIGURE 2-35: Chip Select (CS) Hysteresis (MCP6033 only) with VDD = 3.0V. 7.0 Output Voltage (V) Chip Select Voltage (V) CS Input Low to High 2.1 4.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 -1.0 -2.0 -3.0 -4.0 -5.0 -6.0 -7.0 -8.0 CS Input High to Low 1.0 FIGURE 2-34: Chip Select (CS) Hysteresis (MCP6033 only) with VDD = 5.5V. VIN 5.0 0.0 Hysteresis 2.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Chip Select Voltage (V) Large-Signal Inverting Pulse 6.0 Output On 3.0 Time (0.5 ms/div) FIGURE 2-31: Response. VDD = 5.5V 3.5 VDD = 1.8V Output On 0.9 Hysteresis 0.6 CS Input High to Low CS Input Low to High 0.3 Output High-Z 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 Chip Select Voltage (V) 1.6 1.8 FIGURE 2-36: Chip Select (CS) Hysteresis (MCP6033 only) with VDD = 1.8V. DS20002041C-page 11 MCP6031/2/3/4 Note: Unless otherwise indicated: TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, VL = VDD/2, RL = 1 Mto VL, CL = 60 pF and CS is tied low. 10k 10000 1k 1000 GN: 101 V/V 11 V/V 1 V/V 100 100 10 10 11 1 10 100 1k 1000 10k 10000 Frequency (Hz) FIGURE 2-37: Closed-Loop Output Impedance vs. Frequency. DS20002041C-page 12 10m 1.00E-02 1m 1.00E-03 100µ 1.00E-04 10µ 1.00E-05 1µ 1.00E-06 100n 1.00E-07 10n 1.00E-08 1n 1.00E-09 100p 1.00E-10 10p 1.00E-11 1p 1.00E-12 -IIN (A) Closed Loop Output Impedance (Ω) 100000 100k 100k 100000 +125°C +85°C +25°C -40°C -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 VIN (V) FIGURE 2-38: Measured Input Current vs. Input Voltage (below VSS).  2007-2019 Microchip Technology Inc. MCP6031/2/3/4 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE MCP6031 MCP6032 MCP6033 MCP6034 SOT-23 DFN, MSOP, SOIC MSOP, SOIC DFN, MSOP, SOIC SOIC, TSSOP Symbol 1 6 1 6 1 VOUT, VOUTA Analog Output (Op Amp A) 4 2 2 2 2 VIN-, VINA- Inverting Input (Op Amp A) 3 3 3 3 3 VIN+, VINA+ Noninverting Input (Op Amp A) 5 7 8 7 4 VDD — — 5 — 5 VINB+ 3.1 Noninverting Input (Op Amp B) — — 6 — 6 VINB- Inverting Input (Op Amp B) — 7 — 7 VOUTB Analog Output (Op Amp B) — — — — 8 VOUTC Analog Output (Op Amp C) — — — — 9 VINC- Inverting Input (Op Amp C) — — — — 10 VINC+ Noninverting Input (Op Amp C) 2 4 4 4 11 VSS Negative Power Supply — — — — 12 VIND+ Noninverting Input (Op Amp D) — — — — 13 VIND- Inverting Input (Op Amp D) — — — — 14 VOUTD Analog Output (Op Amp D) — — — 8 — CS Chip Select — 1, 5, 8 — 1, 5 — NC No Internal Connection Analog Outputs Analog Inputs The noninverting and inverting inputs are high-impedance CMOS inputs with low bias currents. 3.3 Positive Power Supply — The output pins are low-impedance voltage sources. 3.2 Description Chip Select Digital Input 3.4 Power Supply Pins The positive power supply (VDD) is 1.8V to 5.5V higher than the negative power supply (VSS). For normal operation, the other pins are at voltages between VSS and VDD. Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need bypass capacitors. This is a CMOS, Schmitt-trigerred input that places the device into a Low-Power mode of operation.  2007-2019 Microchip Technology Inc. DS20002041C-page 13 MCP6031/2/3/4 4.0 APPLICATION INFORMATION VDD The MCP6031/2/3/4 family of op amps is manufactured using Microchip’s state-of-the-art CMOS process and is specifically designed for low-power, high-precision applications. 4.1 D1 V1 4.1.1 V2 PHASE REVERASAL R3 VSS – (minimum expected V1) 2 mA VSS – (minimum expected V2) R2 > 2 mA R1 > INPUT VOLTAGE AND CURRENT LIMITS The ESD protection on the inputs can be depicted as shown in Figure 4-1. This structure was chosen to protect the input transistors and to minimize input bias current (IB). The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltage that goes too far above VDD. Their breakdown voltage is high enough to allow normal operation and low enough to bypass ESD events within the specified limits. VDD VIN+ Bond Pad Input Stage Bond V IN Pad VSS Bond Pad FIGURE 4-1: Structures. FIGURE 4-2: Simplified Analog Input ESD Protecting the Analog Inputs. It is also possible to connect the diodes to the left of the resistors, R1 and R2. In this case, the currents through the diodes, D1 and D2, need to be limited by some other mechanism. The resistors then serve as inrush current limiters; the DC currents into the input pins (VIN+ and VIN-) should be very small. A significant amount of current can flow out of the inputs when the Common-mode voltage (VCM) is below ground (VSS). 4.1.3 Bond Pad MCP603X – R2 The MCP6031/2/3/4 op amps are designed to prevent phase reversal when the input pins exceed the supply voltages. Figure 2-32 shows the input voltage exceeding the supply voltage without any phase reversal. 4.1.2 + R1 Rail-to-Rail Input D2 NORMAL OPERATION The input stage of the MCP6031/2/3/4 op amps uses two differential input stages in parallel. One operates at a low Common-mode input voltage (VCM), while the other operates at a high VCM. With this topology, the device operates with a VCM up to 300 mV above VDD and 300 mV below VSS. The input offset voltage is measured at VCM = VSS – 0.3V and VDD + 0.3V to ensure proper operation. There are two transitions in input behavior as VCM is changed. The first occurs, when VCM is near VSS + 0.4V, and the second occurs when VCM is near VDD – 0.5V. For the best distortion performance with noninverting gains, avoid these regions of operation. In order to prevent damage and/or improper operation of these op amps, the circuit they are in must limit the voltages and currents at the VIN+ and VIN- pins (see “Absolute Maximum Ratings†” at the beginning of Section 1.0 “Electrical Characteristics”). Figure 4-2 shows the recommended approach to protecting these inputs. The internal ESD diodes prevent the input pins (VIN+ and VIN-) from going too far below ground, and the resistors, R1 and R2, limit the possible current drawn out of the input pins. Diodes, D1 and D2, prevent the input pins (VIN+ and VIN-) from going too far above VDD. When implemented as shown, resistors, R1 and R2, also limit the current through D1 and D2. DS20002041C-page 14  2007-2019 Microchip Technology Inc. MCP6031/2/3/4 Rail-to-Rail Output The output voltage range of the MCP6031/2/3/4 op amps is VSS + 10 mV (minimum) and VDD – 10 mV (maximum) when RL = 50 k is connected to VDD/2 and VDD = 5.5V. Refer to Figures 2-25 and 2-26 for more information. 4.3 – VOUT CL Output Loads and Battery Life The MCP6031/2/3/4 op amp family has outstanding quiescent current, which supports battery-powered applications. There is minimal quiescent current glitching when Chip Select (CS) is raised or lowered. This prevents excessive current draw and reduced battery life when the part is turned off or on. Heavy resistive loads at the output can cause excessive battery drain. Driving a DC voltage of 2.5V across a 100 k load resistor will cause the supply current to increase by 25 µA, depleting the battery 28 times as fast as IQ (0.9 µA, typical) alone. High-frequency signals (fast edge rate) across capacitive loads will also significantly increase supply current. For instance, a 0.1 µF capacitor at the output presents an AC impedance of 15.9 k (1/2fC) to a 100 Hz sinewave. It can be shown that the average power drawn from the battery by a 5.0 Vp-p sinewave (1.77 Vrms) under these conditions is FIGURE 4-3: Output Resistor, RISO, Stabilizes Large Capacitive Loads. Figure 4-4 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit’s noise gain. For noninverting gains, GN and the Signal Gain are equal. For inverting gains, GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V). 1M 1000000 PSupply = (VDD – VSS) (IQ + VL(p-p) f CL ) = (5V)(0.9 µA + 5.0 Vp-p · 100 Hz · 0.1 µF) = 4.5 µW + 50 µW This will drain the battery about 12 times as fast as IQ alone. Capacitive Loads Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop’s phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. While a unity gain buffer (G = +1) is the most sensitive to capacitive loads, all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., >100 pF when G = +1), a small series resistor at the output (RISO in Figure 4-3) improves the feedback loop’s phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitance load.  2007-2019 Microchip Technology Inc. 100k 100000 10k 10000 GN: 1 V/V 2 V/V 5 V/V 1k 1000 10p 100p 1.E-09 1n 10n 100n 1µ 1.E-11 1.E-10 1.E-08 1.E-07 1.E-06 Normalized Load Capacitance; CL/GN (F) EQUATION 4-1: 4.4 RISO MCP603X + VIN Recommended R ISO (Ω) 4.2 FIGURE 4-4: Recommended RISO Values for Capacitive Loads. After selecting RISO for your circuit, double-check the resulting frequency response peaking and step response overshoot. Modify RISO’s value until the response is reasonable. Bench evaluation and simulations with the MCP6031/2/3/4 SPICE macro model are very helpful. 4.5 MCP6033 Chip Select The MCP6033 is a single op amp with Chip Select (CS). When CS is pulled high, the supply current drops to 0.4 nA (typical) and flows through the CS pin to VSS. When this happens, the amplifier output is put into a high-impedance state. By pulling CS low, the amplifier is enabled. If the CS pin is left floating, the amplifier will not operate properly. Figure 1-1 shows the output voltage and supply current response to a CS pulse. DS20002041C-page 15 MCP6031/2/3/4 4.6 Supply Bypass With this family of operational amplifiers, the power supply pin (VDD for single supply) should have a local bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good high-frequency performance. It can use a bulk capacitor (i.e., 1 µF or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with other analog parts. 4.7 Unused Op Amps An unused op amp in a quad package (MCP6034) should be configured as shown in Figure 4-5. These circuits prevent the output from toggling and causing crosstalk. Circuit A sets the op amp at its minimum noise gain. The resistor divider produces any desired reference voltage within the output voltage range of the op amp; the op amp buffers that reference voltage. Circuit B uses the minimum number of components and operates as a comparator, but it may draw more current. ¼ MCP6034 (A) ¼ MCP6034 (B) VDD VDD VDD R1 + R2 + VREF – – Guard Ring FIGURE 4-6: for Inverting Gain. 1. 2. VIN- VIN+ VSS Example Guard Ring Layout Noninverting Gain and Unity Gain Buffer: a) Connect the noninverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b) Connect the guard ring to the inverting input pin (VIN-). This biases the guard ring to the Common-mode input voltage. Inverting Gain and Transimpedance Gain Amplifiers (convert current to voltage, such as photo detectors): a) Connect the guard ring to the noninverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b) Connect the inverting pin (VIN-) to the input with a wire that does not touch the PCB surface. R2 V REF = V DD  -----------------R 1 + R2 FIGURE 4-5: 4.8 Unused Op Amps. PCB Surface Leakage In applications where low input bias current is critical, Printed Circuit Board (PCB) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would cause 5 pA of current to flow, which is greater than the MCP6031/2/3/4 family’s bias current at +25°C (±1.0 pA, typical). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 4-6. DS20002041C-page 16  2007-2019 Microchip Technology Inc. MCP6031/2/3/4 4.9 4.9.1 Application Circuits 4.9.2 BATTERY CURRENT SENSING The MCP6031/2/3/4 op amps’ Common-mode input range, which goes 0.3V beyond both supply rails, supports their use in high-side and low-side battery current sensing applications. The ultra-low quiescent current (0.9 µA, typical) helps prolong battery life and the rail-to-rail output supports detection of low currents. Figure 4-7 shows a high-side battery current sensor circuit. The 10 resistor is sized to minimize power losses. The battery current (IDD) through the 10 resistor causes its top terminal to be more negative than the bottom terminal. This keeps the Common-mode input voltage of the op amp below VDD, which is within its allowed range. The output of the op amp will also be below VDD, which is within its maximum output voltage swing specification. IDD 1.4V to 5.5V VDD 10 100 k + MCP6031 VOUT – 1 M V DD – VOUT I DD = ----------------------------------------- 10 V/V    10   FIGURE 4-7: Sensor. High-Side Battery Current PRECISION COMPARATOR Use high gain before a comparator to improve the latter’s input offset performance. Figure 4-8 shows a gain of 11 V/V placed before a comparator. The reference voltage, VREF, can be any value between the supply rails. VIN + MCP6031 – + 100 k 1 M FIGURE 4-8: Comparator. – Precision, Noninverting DRIVING MCP3421  A/D CONVERTER 4.9.3 A RSH and CSH snubber reduces the output impedance of the MCP6031 op amp, which reduces the gain error caused by switching transients, which occur at the MCP3421 ADC’s sampling rate. The snubber also maintains feedback stability, and avoids AC response peaking and step response overshoot and ringing (caused by the op amp’s inductive output impedance resonating with the ADC’s input capacitance). The cost for this improvement is low. Best of all, using an op amp with higher supply current is avoided (see Figure 4-9). This figure also includes a resistor to balance the impedance at the ADC’s inputs (RBAL) at the sampling frequency; it may not be needed in all designs. MCP6031 VIN + 1.00 k ZIND 2.25 M MCP3421 + – FIGURE 4-9: an R-C Snubber.  2007-2019 Microchip Technology Inc. VREF VOUT MCP6541 RSH 1.00 k CSH 2.2 µF –  RBAL 1.00 k Driving the MCP3421 Using DS20002041C-page 17 MCP6031/2/3/4 5.0 DESIGN AIDS Microchip provides the basic design tools needed for the MCP6031/2/3/4 family of op amps. 5.1 SPICE Macro Model The latest SPICE macro model for the MCP6031/2/3/4 op amps is available on the Microchip website at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp’s linear region of operation over the temperature range. See the model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 ® FilterLab Software Microchip’s FilterLab® software is an innovative software tool that simplifies analog active filter (using op amps) design. Available at no cost from the Microchip website at www.microchip.com/filterlab, the FilterLab design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. 5.3 Mindi™ Circuit Designer and Simulator Microchip’s Mindi™ Circuit Designer and Simulator aids in the design of various circuits useful for active filter, amplifier and power management applications. It is a free online circuit designer and simulator available from the Microchip website at www.microchip.com/mindi. This interactive circuit designer and simulator enables designers to quickly generate circuit diagrams and simulate circuits. Circuits developed using the Mindi Circuit Designer and Simulator can be downloaded to a personal computer or workstation. 5.4 5.5 Analog Demonstration and Evaluation Boards Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to help you achieve faster time to market. For a complete listing of these boards and their corresponding user’s guides and technical information, visit the Microchip website at www.microchip.com/analogtools. Two of our boards that are especially useful are: • P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board • P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP Evaluation Board 5.6 Application Notes The following Microchip Analog Design Note and Application Notes are available on the Microchip website at www.microchip.com/appnotes and are recommended as supplemental reference resources. ADN003: “Select the Right Operational Amplifier for your Filtering Circuits”, DS21821 AN722: “Operational Amplifier Topologies and DC Specifications”, DS00722 AN723: “Operational Amplifier AC Specifications and Applications”, DS00723 AN884: “Driving Capacitive Loads With Op Amps”, DS00884 AN990: “Analog Sensor Conditioning Circuits – An Overview”, DS00990 These application notes and others are listed in the design guide: “Signal Chain Design Guide”, DS21825 MAPS (Microchip Advanced Part Selector) MAPS is a software tool that helps semiconductor professionals efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip website at www.microchip.com/ maps, the MAPS is an overall selection tool for Microchip’s product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for Data Sheets, Purchase and Sampling of Microchip parts. DS20002041C-page 18  2007-2019 Microchip Technology Inc. MCP6031/2/3/4 6.0 PACKAGING INFORMATION 6.1 Package Marking Information Example: 5-Lead SOT-23 (MCP6031) Device XXNN MCP6031T-E/OT E-Temp Code EANN 8-Lead 2x3 mm DFN (MCP6031 and MCP6033) XXX YWW NN Example: XXXXXX YWWNNN 6031E 909256 8-Lead SOIC (3.90 mm) XXXXXXXX XXXXYYWW NNN e3 * Note: Example: ABV 809 25 8-Lead MSOP Legend: XX...X Y YY WW NNN EA25 Example: MCP6033E e3 SN^^1909 256 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2007-2019 Microchip Technology Inc. DS20002041C-page 19 MCP6031/2/3/4 Package Marking Information (Continued) 14-Lead SOIC (3.90 mm) (MCP6034) Example: XXXXXXXXXX XXXXXXXXXX YYWWNNN 14-Lead TSSOP (MCP6034) MCP6034 E/SL e3 1911256 Example: XXXXXXXX YYWW 6034EST 1911 NNN 256 DS20002041C-page 20  2007-2019 Microchip Technology Inc. MCP6031/2/3/4 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 0.20 C 2X D e1 A D N E/2 E1/2 E1 E (DATUM D) (DATUM A-B) 0.15 C D 2X NOTE 1 1 2 e B NX b 0.20 C A-B D TOP VIEW A A A2 0.20 C SEATING PLANE A SEE SHEET 2 A1 C SIDE VIEW Microchip Technology Drawing C04-091-OT Rev F Sheet 1 of 2  2007-2019 Microchip Technology Inc. DS20002041C-page 21 MCP6031/2/3/4 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging c T L L1 VIEW A-A SHEET 1 Units Dimension Limits N Number of Pins e Pitch e1 Outside lead pitch A Overall Height A2 Molded Package Thickness Standoff A1 Overall Width E Molded Package Width E1 Overall Length D Foot Length L Footprint L1 I Foot Angle c Lead Thickness b Lead Width MIN 0.90 0.89 - 0.30 0° 0.08 0.20 MILLIMETERS NOM 5 0.95 BSC 1.90 BSC 2.80 BSC 1.60 BSC 2.90 BSC 0.60 REF - MAX 1.45 1.30 0.15 0.60 10° 0.26 0.51 Notes: 1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm per side. 2. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-091-OT Rev F Sheet 2 of 2 DS20002041C-page 22  2007-2019 Microchip Technology Inc. MCP6031/2/3/4 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging X SILK SCREEN 5 Y Z C G 1 2 E GX RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch C Contact Pad Spacing X Contact Pad Width (X5) Contact Pad Length (X5) Y Distance Between Pads G Distance Between Pads GX Overall Width Z MIN MILLIMETERS NOM 0.95 BSC 2.80 MAX 0.60 1.10 1.70 0.35 3.90 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2091-OT Rev F  2007-2019 Microchip Technology Inc. DS20002041C-page 23 MCP6031/2/3/4       !""#$%& ' -      $#  *... e D b N N L K E2 E EXPOSED PAD NOTE 1 NOTE 1 2 1 2 1 D2 BOTTOM VIEW TOP VIEW A A3 A1 NOTE 2 / ! 1 2  $0110$%+%,# $02 2 23$ $"4 5   37 " 656 686 66 #  " 666 66 66' )+ " 66,%- 31 ! 66(#) 39  % %   1 ! 6 : %   9  % '6 : ;'  66 6' 66 )1 1 66 6 6 6'6 )