MCP6231T-E/MC

MCP6231/1R/1U/2/4 20 µA, 300 kHz Rail-to-Rail Op Amp Features Description • • • • • • The Microchip Technology Inc. MCP6231/1R/1U/2/4 operational amplifiers (op amps) provide wide bandwidth for the quiescent current. The MCP6231/1R/1U/2/4 family has a 300 kHz gain bandwidth product and 65°C (typical) phase margin. This family operates from a single supply voltage as low as 1.8V, while drawing 20 µA (typical) quiescent current. In addition, the MCP6231/1R/1U/2/4 family supports rail-to-rail input and output swing, with a Common-mode input voltage range of VDD + 300 mV to VSS – 300 mV. These op amps are designed in one of Microchip’s advanced CMOS processes. Gain Bandwidth Product: 300 kHz (typical) Supply Current: IQ = 20 µA (typical) Supply Voltage: 1.8V to 6.0V Rail-to-Rail Input/Output Extended Temperature Range: -40°C to +125°C Available in 5-Pin SC70 and SOT-23 packages Applications • • • • • • Automotive Portable Equipment Transimpedance Amplifiers Analog Filters Notebooks and PDAs Battery-Powered Systems Package Types SOT-23-5 5 VDD VOUT 1 Design Aids • • • • • • 2 SPICE Macro Models FilterLab® Software Mindi™ Circuit Designer and Simulator Microchip Advanced Part Selector (MAPS) Analog Demonstration and Evaluation Boards Application Notes + – VIN+ 3 4 VIN- MCP6231R SOT-23-5 VOUT 1 VDD 2 RG2 – 7 VDD VIN+ 3 + 6 VOUT VSS 4 5 NC MCP6232 MSOP, PDIP, SOIC VOUTA 1 4 VIN- VINA+ 3 8 VDD VINA- 2 MCP6231U SC70-5, SOT-23-5 RG1 VIN1 + RZ + VSS 2 – VIN- 3 – MCP6231 5 VDD VIN+ 1 RF RX 8 NC 7 VOUTB –+ +– VSS 4 VIN2 VDD NC 1 VIN- 2 5 VSS + – VIN+ 3 Typical Application RY MCP6231 MSOP, PDIP, SOIC MCP6231 VOUT MCP6231 DFN* NC 1 VIN- 2 VIN+ 3 Summing Amplifier Circuit 4 VOUT VSS 4 EP 9 6 VINB5 VINB+ MCP6232 2x3 TDFN* VOUTA 1 VINA- 2 VINA+ 3 VSS 4 8 VDD EP 9 7 VOUTB 6 VINB5 VINB+ MCP6234 PDIP, SOIC, TSSOP 8 NC VOUTA 1 7 VDD VINA- 2 - + + - 13 VIND- VINA+ 3 12 VIND+ 6 VOUT 5 NC VDD 4 14 VOUTD 11 VSS VINB+ 5 10 VINC+ VINB- 6 VOUTB 7 -+ + - 9 V INC 8 VOUTC * Includes Exposed Thermal Pad (EP); see Table 3-1.  2004-2020 Microchip Technology Inc. DS20001881G-page 1 MCP6231/1R/1U/2/4 NOTES: DS20001881G-page 2  2004-2020 Microchip Technology Inc. MCP6231/1R/1U/2/4 1.0 ELECTRICAL CHARACTERISTICS VDD – VSS ........................................................................7.0V † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Current at Analog Input Pins (VIN+, VIN-)......................±2 mA †† See Section 4.1.2 “Input Voltage and Current Limits”. Absolute Maximum Ratings† Analog Inputs (VIN+, VIN-)†† .......... VSS – 1.0V to VDD + 1.0V All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V Difference Input Voltage ...................................... |VDD – VSS| Output Short-Circuit Current ................................ Continuous Current at Output and Supply Pins ............................±30 mA Storage Temperature ....................................-65°C to +150°C Maximum Junction Temperature (TJ)......................... .+150°C ESD Protection on All Pins (HBM; MM)   4 kV; 300V DC ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, RL = 100 kto VDD/2 and VOUT  VDD/2. Parameters Sym Min Typ Max Units Conditions Input Offset Voltage VOS -5.0 — +5.0 mV VCM = VSS Extended Temperature VOS -7.0 — +7.0 mV TA = -40°C to +125°C, VCM = VSS (Note 1) VOS/TA — ±3.0 — µV/°C TA= -40°C to +125°C, VCM = VSS PSRR — 83 — dB Input Bias Current: IB — ±1.0 — pA At Temperature IB — 20 — pA TA = +85°C TA = +125°C Input Offset Input Offset Drift with Temperature Power Supply Rejection Ratio VCM = VSS Input Bias Current and Impedance IB — 1100 — pA Input Offset Current IOS — ±1.0 — pA Common-Mode Input Impedance ZCM — 1013||6 — ||pF Differential Input Impedance ZDIFF — 1013||3 — ||pF Common-Mode Input Range VCMR VSS –0.3 — VDD + 0.3 V Common-Mode Rejection Ratio CMRR 61 75 — dB VCM = -0.3V to 5.3V, VDD = 5V AOL 90 110 — dB VOUT = 0.3V to VDD – 0.3V, VCM = VSS VOL, VOH VSS + 35 — VDD – 35 mV RL =10 k0.5V Input Overdrive ISC — ±6 — mA VDD = 1.8V ISC — ±23 — mA VDD = 5.5V VDD 1.8 — 6.0 V IQ 10 20 30 µA At Temperature Common-Mode Open-Loop Gain DC Open-Loop Gain (large signal) Output Maximum Output Voltage Swing Output Short-Circuit Current Power Supply Supply Voltage Quiescent Current per Amplifier Note 1: 2: IO = 0, VCM = VDD – 0.5V The SC70 package is only tested at +25°C. All parts with date codes of February 2007 and later have been screened to ensure operation at VDD = 6.0V. However, the other minimum and maximum specifications are measured at 1.8V and 5.5V.  2004-2020 Microchip Technology Inc. DS20001881G-page 3 MCP6231/1R/1U/2/4 AC ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8 to 5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, RL = 100 k to VDD/2 and CL = 60 pF. Parameters Sym Min Typ Max Units Conditions GBWP — 300 — kHz Phase Margin PM — 65 — ° Slew Rate SR — 0.15 — V/µs Input Noise Voltage Eni — 6.0 — µVP-P Input Noise Voltage Density eni — 52 — nV/Hz f = 1 kHz Input Noise Current Density ini — 0.6 — fA/Hz f = 1 kHz AC Response Gain Bandwidth Product G = +1 V/V Noise f = 0.1 Hz to 10 Hz TEMPERATURE CHARACTERISTICS Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V and VSS = GND. Parameters Sym Min Typ Max Units Extended Temperature Range TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Conditions Temperature Ranges Note 1 Thermal Package Resistances Thermal Resistance, 5L-SC70 JA — 331 — °C/W Thermal Resistance, 5L-SOT-23 JA — 256 — °C/W Thermal Resistance, 8L-DFN JA — 84.5 — °C/W Thermal Resistance, 8L-MSOP JA — 206 — °C/W Thermal Resistance, 8L-TDFN JA — 41 — °C/W Thermal Resistance, 8L-PDIP JA — 85 — °C/W Thermal Resistance, 8L-SOIC JA — 163 — °C/W Thermal Resistance, 14L-PDIP JA — 70 — °C/W Thermal Resistance, 14L-SOIC JA — 120 — °C/W Thermal Resistance, 14L-TSSOP JA — 100 — °C/W Note 1: The internal Junction Temperature (TJ) must not exceed the absolute maximum specification of +150°C. DS20001881G-page 4  2004-2020 Microchip Technology Inc. MCP6231/1R/1U/2/4 1.1 Test Circuits The test circuits used for the DC and AC tests are shown in Figure 1-1 and Figure 1-2. The bypass capacitors are laid out according to the rules discussed in Section 4.6 “PCB Surface Leakage”. VDD VIN RN 0.1 µF VOUT MCP623X CL RN RL RF VL FIGURE 1-1: AC and DC Test Circuit for Most Noninverting Gain Conditions.  2004-2020 Microchip Technology Inc. VDD VDD/2 + – VDD/2 RG 1 µF 0.1 µF + VOUT MCP623X CL – VIN RG 1 µF RL RF VL FIGURE 1-2: AC and DC Test Circuit for Most Inverting Gain Conditions. DS20001881G-page 5 MCP6231/1R/1U/2/4 NOTES: DS20001881G-page 6  2004-2020 Microchip Technology Inc. MCP6231/1R/1U/2/4 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% 90 CMRR, PSRR (dB) 630 Samples VCM = VSS 85 PSRR (VCM = VSS) 80 75 CMRR (VCM = -0.3V to +5.3V, VDD = 5.0V) -25 0 25 50 75 Ambient Temperature (°C) Input Offset Voltage (mV) FIGURE 2-4: Temperature. 100 120 30 1.E+01 1.E+02 10 1.E+03 100 1.E+04 1k 100k Frequency (Hz) PSRR, CMRR vs. -120 20 -150 0 -180 30% 25% 20% 15% 10% 5% 0% Input Bias Current (pA) FIGURE 2-3: Input Bias Current at +85°C.  2004-2020 Microchip Technology Inc. Open-Loop Gain, Phase vs. 632 Samples VCM = VDD/2 TA = +125°C 0.0 Percentage of Occurrences 42 36 30 24 18 12 40 FIGURE 2-5: Frequency. 630 Samples VCM = VDD/2 TA = +85°C 6 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% 0 Percentage of Occurrences FIGURE 2-2: Frequency. -90 -20 -210 0.1 1.E+ 1 1.E+ 10 1.E+ 100 1.E+ 1k 1.E+ 10k 100k 1M 1.E+ 10M 1.E1.E+ 1.E+ 01 00 01 Frequency 02 03 (Hz) 04 05 06 07 1.E+05 10k -60 Phase 0.6 20 -30 2.0 40 0 1.8 PSRR+ 50 60 0.4 60 80 1.6 CMRR Gain 0.2 70 RL = 10 kΩ VCM = VDD/2 1.0 80 100 0.8 PSRR- Open-Loop Gain (dB) PSRR, CMRR (dB) 90 125 CMRR, PSRR vs. Ambient 1.4 Input Offset Voltage. 1.2 FIGURE 2-1: 100 Open-Loop Phase (°) -50 5 4 3 2 1 0 -1 -2 -3 -4 70 -5 Percentage of Occurrences Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, RL = 100 kto VDD/2 and CL = 60 pF. Input Bias Current (nA) FIGURE 2-6: Input Bias Current at +125°C. DS20001881G-page 7 MCP6231/1R/1U/2/4 Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, RL = 100 kto VDD/2 and CL = 60 pF. FIGURE 2-7: vs. Frequency. VDD = 1.8V TA = -40°C TA = +25°C TA = +85°C TA = +125°C 450 350 250 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 150 FIGURE 2-10: 50 0 -50 -100 -150 Common Mode Input Voltage (V) FIGURE 2-9: Input Offset Voltage vs. Common-Mode Input Voltage at VDD = 5.5V. 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -200 DS20001881G-page 8 12 10 8 6 4 2 0 -50 -100 VDD = 5.5V -150 -200 VDD = 1.8V -250 -300 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Short-Circuit Current (mA) TA = +125°C TA = +85°C TA = +25°C TA = -40°C 100 0 VCM = VSS 50 FIGURE 2-11: Output Voltage. VDD = 5.5 V 150 -2 Input Offset Voltage Drift. Output Voltage (V) FIGURE 2-8: Input Offset Voltage vs. Common-Mode Input Voltage at VDD = 1.8V. 200 -4 Input Offset Voltage Drift (µV/°C) Common Mode Input Voltage (V) Input Offset Voltage (µV) -6 -8 -10 628 Samples VCM = VSS TA = -40°C to +125°C 100 550 Input Offset Voltage (µV) Input Noise Voltage Density 20% 18% 16% 14% 12% 10% 8% 6% 4% 2% 0% -12 10 0.1 1.E+0 1 10 100 1.E+0 1k 10k 1.E+0 100k 1.E-01 1.E+0 1.E+0 1.E+0 0 1Frequency 2 (Hz)3 4 5 Percentage of Occurrences 100 Input Offset Voltage (µV) Input Noise Voltage Density (nV/Hz) 1,000 30 25 20 15 10 5 0 -5 -10 -15 -20 -25 -30 Input Offset Voltage vs. +ISC TA = +125°C TA = +85°C TA = +25°C TA = -40°C -ISC 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) FIGURE 2-12: Output Short-Circuit Current vs. Ambient Temperature.  2004-2020 Microchip Technology Inc. MCP6231/1R/1U/2/4 Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, RL = 100 kto VDD/2 and CL = 60 pF. VDD = 5.5V 0.25 Falling Edge 0.20 0.15 0.10 Rising Edge VDD = 1.8V 0.05 -50 -25 0 25 50 75 100 Ambient Temperature (°C) FIGURE 2-13: Temperature. 125 Slew Rate vs. Ambient Time (2 µs/div) FIGURE 2-16: Pulse Response. 1,000 VDD = 5.0V G = +1 V/V 4.5 100 VDD – VOH VOL – VSS 10 1 10µ 1.E-02 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 100µ 1m 1.E-01 1.E+00 Output Current Magnitude (A) 10m 1.E+01 0.0 Time (20 µs/div) FIGURE 2-14: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-17: Pulse Response. 30 10 VDD = 5.5V 1 Quiescent Current per Amplifier (µA) Max. Output Voltage Swing (VP-P ) Small-Signal, Noninverting 5.0 Output Voltage (V) Output Voltage Headroom (mV) G = +1 V/V RL = 10 kΩ Output Voltage (10 mV/div) Slew Rate (V/µs) 0.30 VDD = 1.8V 0.1 1k 1.E+03 Large-Signal, Noninverting VCM = 0.9VDD 25 20 15 10 5 TA = +125°C TA = +85°C TA = +25°C TA = -40°C 0 10k 100k 1.E+04 1.E+05 Frequency (Hz) 1M 1.E+06 FIGURE 2-15: Maximum Output Voltage Swing vs. Frequency.  2004-2020 Microchip Technology Inc. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) FIGURE 2-18: Quiescent Current vs. Power Supply Voltage. DS20001881G-page 9 MCP6231/1R/1U/2/4 Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT  VDD/2, RL = 100 kto VDD/2 and CL = 60 pF. 6.0 +125°C +85°C +25°C -40°C -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Input Voltage (V) FIGURE 2-19: Measured Input Current vs. Input Voltage (below VSS). DS20001881G-page 10 Input, Output Voltages (V) Input Current Magnitude (A) 1.E-02 10m 1.E-03 1m 1.E-04 100µ 1.E-05 10µ 1.E-06 1µ 100n 1.E-07 10n 1.E-08 1n 1.E-09 100p 1.E-10 10p 1.E-11 1p 1.E-12 VOUT 5.0 4.0 VDD = 5.0V G = +2 V/V VIN 3.0 2.0 1.0 0.0 -1.0 Time (1 ms/div) FIGURE 2-20: The MCP6231/1R/1U/2/4 Show No Phase Reversal.  2004-2020 Microchip Technology Inc. MCP6231/1R/1U/2/4 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps). TABLE 3-1: PIN FUNCTION TABLE FOR SINGLE OP AMPS MCP6231 MCP6231R MCP6231U DFN, MSOP, PDIP, SOIC SOT-23-5 SOT-23-5 SOT-23-5 SC70 Symbol 6 1 1 4 VOUT Analog Output 2 4 4 3 VIN- Inverting Input 3 3 3 1 VIN+ Noninverting Input 7 5 2 5 VDD Positive Power Supply 4 2 5 2 VSS Negative Power Supply 1, 5, 8 — — — NC No Internal Connection 9 — — — EP Exposed Thermal Pad (EP); must be connected to VSS. TABLE 3-2: Description PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS MCP6232 MCP6234 MSOP, PDIP, SOIC, TDFN PDIP, SOIC, TSSOP 1 1 VOUTA Analog Output (Op Amp A) 2 2 VINA- Inverting Input (Op Amp A) 3 3 VINA+ Noninverting Input (Op Amp A) 8 4 VDD 5 5 VINB+ Noninverting Input (Op Amp B) Symbol Description Positive Power Supply 6 6 VINB- Inverting Input (Op Amp B) 7 7 VOUTB Analog Output (Op Amp B) — 8 VOUTC Analog Output (Op Amp C) Inverting Input (Op Amp C) — 9 VINC- — 10 VINC+ 4 11 VSS Noninverting Input (Op Amp C) Negative Power Supply — 12 VIND+ Noninverting Input (Op Amp D) — 13 VIND- Inverting Input (Op Amp D) — 14 VOUTD Analog Output (Op Amp D) 9 — —  2004-2020 Microchip Technology Inc. Exposed Thermal Pad (EP); must be connected to VSS. DS20001881G-page 11 MCP6231/1R/1U/2/4 3.1 Analog Outputs The output pins are low-impedance voltage sources. 3.2 Analog Inputs The noninverting and inverting inputs are high-impedance CMOS inputs with low bias currents. 3.3 3.4 Exposed Thermal Pad (EP) There is an internal electrical connection between the Exposed Thermal Pad (EP) and the VSS pin; they must be connected to the same potential on the Printed Circuit Board (PCB). Power Supply (VSS and VDD) The positive power supply (VDD) is 1.8V to 6.0V higher than the negative power supply (VSS). For normal operation, the other pins are between VSS and VDD. Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need bypass capacitors. DS20001881G-page 12  2004-2020 Microchip Technology Inc. MCP6231/1R/1U/2/4 4.0 APPLICATION INFORMATION The MCP6231/1R/1U/2/4 family of op amps is manufactured using Microchip’s state-of-the-art CMOS process and is specifically designed for low-cost, low-power and general purpose applications. The low supply voltage, low quiescent current and wide bandwidth makes the MCP6231/1R/1U/2/4 ideal for battery-powered applications. 4.1 Rail-to-Rail Inputs 4.1.1 The MCP6231/1R/1U/2/4 op amp is designed to prevent phase reversal when the input pins exceed the supply voltages. Figure 4-1 shows the input voltage exceeding the supply voltage without any phase reversal. Input, Output Voltages (V) VOUT 5.0 4.0 VIN+ Bond Pad Bond V IN Pad Input Stage VSS Bond Pad PHASE REVERSAL 6.0 VDD Bond Pad VDD = 5.0V G = +2 V/V VIN 3.0 2.0 1.0 0.0 FIGURE 4-2: Structures. Simplified Analog Input ESD In order to prevent damage and/or improper operation of these op amps, the circuit they are in must limit the currents and voltages at the VIN+ and VIN- pins (see Absolute Maximum Ratings† at the beginning of Section 1.0 “Electrical Characteristics”). Figure 4-3 shows the recommended approach to protecting these inputs. The internal ESD diodes prevent the input pins (VIN+ and VIN-) from going too far below ground and the resistors, R1 and R2, limit the possible current drawn out of the input pins. Diodes D1 and D2 prevent the input pins (VIN+ and VIN-) from going too far above VDD and dump any currents onto VDD. When implemented as shown, resistors R1 and R2, also limit the current through D1 and D2. -1.0 Time (1 ms/div) VDD FIGURE 4-1: The MCP6231/1R/1U/2/4 Show No Phase Reversal. 4.1.2 INPUT VOLTAGE AND CURRENT LIMITS The ESD protection on the inputs can be depicted as shown in Figure 4-2. This structure was chosen to protect the input transistors and to minimize input bias current (IB). The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltages that go too far above VDD; their breakdown voltage is high enough to allow normal operation and low enough to bypass quick ESD events within the specified limits. D1 V1 D2 + R1 V2 MCP623X – R2 R3 VSS – (minimum expected V1) 2 mA VSS – (minimum expected V2) R2 > 2 mA R1 > FIGURE 4-3: Protecting the Analog Inputs. It is also possible to connect the diodes to the left of resistors, R1 and R2. In this case, current through the diodes, D1 and D2, needs to be limited by some other mechanism. The resistors then serve as in-rush current limiters; the DC current into the input pins (VIN+ and VIN-) should be very small.  2004-2020 Microchip Technology Inc. DS20001881G-page 13 MCP6231/1R/1U/2/4 4.1.3 NORMAL OPERATION 1k 1,000 The input stage of the MCP6231/1R/1U/2/4 op amps use two differential CMOS input stages in parallel. One operates at low Common-mode input voltage (VCM), while the other operates at high VCM. With this topology, the device operates with VCM up to 0.3V above VDD and 0.3V below VSS. 4.2 Capacitive Loads Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop’s phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. A unity gain buffer (G = +1) is the most sensitive to capacitive loads, but all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., >60 pF when G = +1), a small series resistor at the output (RISO in Figure 4-4) improves the feedback loop’s phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. — RISO VOUT MCP623X VIN + GN = 1 V/V GN = 2 V/V GN  4 V/V 100 100 10p 10 100p 1n 10n 100 1000 10000 Normalized Load Capacitance; CL/GN (F) FIGURE 4-5: Recommended RISO Values for Capacitive Loads. Rail-to-Rail Output The output voltage range of the MCP6231/1R/1U/2/4 op amps is VDD – 35 mV (maximum) and VSS + 35 mV (minimum) when RL = 10 k is connected to VDD/2 and VDD = 5.5V. Refer to Figure 2-14 for more information. 4.3 10,000 10k Recommended RISO (Ω) A significant amount of current can flow out of the inputs when the Common-mode voltage (VCM) is below ground (VSS); see Figure 2-19. Applications that are high-impedance may need to limit the usable voltage range. After selecting RISO for your circuit, double-check the resulting frequency response peaking and step response overshoot. Evaluation on the bench and simulations with the MCP6231/1R/1U/2/4 SPICE macro model are very helpful. Modify RISO’s value until the response is reasonable. 4.4 Supply Bypass With this op amp, the power supply pin (VDD for single-supply) should have a local bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good high-frequency performance. It can use a bulk capacitor (i.e., 1 µF or larger) within 100 mm to provide large, slow currents. This bulk capacitor can be shared with other nearby analog parts. 4.5 Unused Op Amps An unused op amp in a quad package (MCP6234) should be configured as shown in Figure 4-6. Both circuits prevent the output from toggling and causing crosstalk. Circuit A can use any reference voltage between the supplies, provides a buffered DC voltage and minimizes the supply current draw of the unused op amp. Circuit B minimizes the number of components, but may draw a little more supply current for the unused op amp. CL ¼ MCP6234 (A) ¼ MCP6234 (B) VDD FIGURE 4-4: Output Resistor, RISO, Stabilizes Large Capacitive Loads. Figure 4-5 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit’s noise gain. For noninverting gains, GN and the signal gain are equal. For inverting gains, GN is 1 + |Signal Gain| (e.g., –1 V/V gives GN = +2 V/V). R1 VDD + R2 – + VREF – R2 V REF = V DD  -------------------R1 + R2 FIGURE 4-6: DS20001881G-page 14 VDD Unused Op Amps.  2004-2020 Microchip Technology Inc. MCP6231/1R/1U/2/4 4.6 PCB Surface Leakage 4.7 In applications where low input bias current is critical, Printed Circuit Board (PCB) surface leakage effects need to be considered. Surface leakage is caused by humidity, dust or other contamination on the board. Under low humidity conditions, a typical resistance between nearby traces is 1012. A 5V difference would cause 5 pA of current to flow, which is greater than the MCP6231/1R/1U/2/4 family’s bias current at +25°C (1 pA, typical). The easiest way to reduce surface leakage is to use a guard ring around sensitive pins (or traces). The guard ring is biased at the same voltage as the sensitive pin. An example of this type of layout is shown in Figure 4-7. VIN– VIN+ Application Circuits 4.7.1 MATCHING THE IMPEDANCE AT THE INPUTS To minimize the effect of input bias current in an amplifier circuit (this is important for very high source impedance applications, such as pH meters and transimpedance amplifiers), the impedances at the inverting and noninverting inputs need to be matched. This is done by choosing the circuit resistor values so that the total resistance at each input is the same. Figure 4-8 shows a summing amplifier circuit. RG2 VIN2 RG1 VIN1 VSS RF VDD – RX MCP623X RY Guard Ring FIGURE 4-7: for Inverting Gain. 1. 2. Example Guard Ring Layout Noninverting Gain and Unity-Gain Buffer: a) Connect the noninverting pin (VIN+) to the input with a wire that does not touch the PCB surface. b) Connect the guard ring to the inverting input pin (VIN-). This biases the guard ring to the Common-mode input voltage. Inverting Gain and Transimpedance Amplifiers (convert current to voltage, such as photo detectors): a) Connect the guard ring to the noninverting input pin (VIN+). This biases the guard ring to the same reference voltage as the op amp (e.g., VDD/2 or ground). b) Connect the inverting pin (VIN-) to the input with a wire that does not touch the PCB surface. RZ FIGURE 4-8: VOUT + Summing Amplifier Circuit. To match the inputs, set all voltage sources to ground and calculate the total resistance at the input nodes. In this summing amplifier circuit, the resistance at the inverting input is calculated by setting VIN1, VIN2 and VOUT to ground. In this case, RG1, RG2 and RF are in parallel. The total resistance at the inverting input is: EQUATION 4-1: RVIN- = 1 1 1 1  + + RG1 RG2 RF Where: RVIN- = Total Resistance at the Inverting Input At the noninverting input, VDD is the only voltage source. When VDD is set to ground, both RX and RY are in parallel. The total resistance at the noninverting input is: EQUATION 4-2: Where: 1 R VIN + = ------------------------- + RZ 1- 1- + ---- ----R R Y X RVIN+ = Total Resistance at the Inverting Input  2004-2020 Microchip Technology Inc. DS20001881G-page 15 MCP6231/1R/1U/2/4 To minimize output offset voltage and increase circuit accuracy, the resistor values need to meet the conditions: + VAC MCP623X EQUATION 4-3: VOUT – RVIN+ = RVIN- RG RF CPARA CF VDC 4.7.2 COMPENSATING FOR THE PARASITIC CAPACITANCE In analog circuit design, the PCB parasitic capacitance can compromise the circuit behavior; Figure 4-9 shows a typical scenario. If the input of an amplifier sees parasitic capacitance of several picofarad (CPARA, which includes the Common-mode capacitance of 6 pF, typical), as well as large RF and RG, the frequency response of the circuit will include a zero. This parasitic zero introduces gain peaking and can cause circuit instability. DS20001881G-page 16 RG C F = C PARA  ------RF FIGURE 4-9: Effect of Parasitic Capacitance at the Input. One solution is to use smaller resistor values to push the zero to a higher frequency. Another solution is to compensate by introducing a pole at the point at which the zero occurs. This can be done by adding CF in parallel with the feedback resistor (RF). CF needs to be selected so that the ratio, CPARA:CF, is equal to the ratio of RF:RG.  2004-2020 Microchip Technology Inc. MCP6231/1R/1U/2/4 5.0 DESIGN AIDS Microchip provides the basic design tools needed for the MCP6231/1R/1U/2/4 family of op amps. 5.1 SPICE Macro Model The latest SPICE macro model for the MCP6231/1R/1U/2/4 op amps is available on the Microchip website at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp’s linear region of operation over the temperature range. See the model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 FilterLab® Software FilterLab® Microchip’s software is an innovative software tool that simplifies analog active filter (using op amps) design. Available at no cost from the Microchip website at www.microchip.com/filterlab, the FilterLab design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. 5.3 Mindi™ Circuit Designer and Simulator Microchip’s Mindi™ Circuit Designer and Simulator aids in the design of various circuits useful for active filter, amplifier and power management applications. It is a free online circuit designer and simulator available from the Microchip website at www.microchip.com/mindi. This interactive circuit designer and simulator enables designers to quickly generate circuit diagrams, and simulate circuits. Circuits developed using the Mindi Circuit Designer and Simulator can be downloaded to a personal computer or workstation. 5.4 5.5 Analog Demonstration and Evaluation Boards Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to help you achieve faster time to market. For a complete listing of these boards and their corresponding user’s guides and technical information, visit the Microchip website at: www.microchip.com/analogtools Two of our boards that are especially useful are: • P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board • P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP Evaluation Board 5.6 Application Notes The following Microchip Application Notes are available on the Microchip website at www.microchip. com/ appnotes and are recommended as supplemental reference resources. • ADN003: “Select the Right Operational Amplifier for your Filtering Circuits,” DS21821 • AN722: “Operational Amplifier Topologies and DC Specifications,” DS00722 • AN723: “Operational Amplifier AC Specifications and Applications,” DS00723 • AN884: “Driving Capacitive Loads With Op Amps,” DS00884 • AN990: “Analog Sensor Conditioning Circuits – An Overview,” DS00990 These application notes and others are listed in the design guide: • “Signal Chain Design Guide,” DS21825 Microchip Advanced Part Selector (MAPS) MAPS is a software tool that helps semiconductor professionals efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip website at www.microchip.com/ maps, MAPS is an overall selection tool for Microchip’s product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool you can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for data sheets, purchase and sampling of Microchip parts.  2004-2020 Microchip Technology Inc. DS20001881G-page 17 MCP6231/1R/1U/2/4 NOTES: DS20001881G-page 18  2004-2020 Microchip Technology Inc. MCP6231/1R/1U/2/4 6.0 PACKAGING INFORMATION 6.1 Package Marking Information 5-Lead SC70 (MCP6231U Only) Example: XXNN AS25 5-Lead SOT-23 5 Device 4 XXNN 1 2 MCP6231 BJNN MCP6231R BKNN MCP6231U BLNN Note: 3 Code Applies to 5-Lead SOT-23. 5 4 BJ25 1 2 3 Example: 8-Lead DFN (2 x 3 mm) (MCP6231) XXX YWW NNN AER 929 256 Example: 8-Lead TDFN (2 x 3 mm) (MCP6232) AAE 929 256 XXX YWW NNN Example: 8-Lead MSOP 6231E 929256 Legend: XX...X Y YY WW NNN e3 * Note: Example: 6232E 929256 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2004-2020 Microchip Technology Inc. DS20001881G-page 19 MCP6231/1R/1U/2/4 Package Marking Information (Continued) 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN 14-Lead PDIP (300 mil) (MCP6234) Example: MCP6232 E/P256 0929 MCP6232 E/P e3 256 0929 OR Example: MCP6232 E/SN0929 256 MCP6232E SN e3 0929 256 OR Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 14-Lead SOIC (150 mil) (MCP6234) MCP6234 e3 E/P^^ 0929256 Example: MCP6234 e3 E/SL^^ 0929256 XXXXXXXXXX XXXXXXXXXX YYWWNNN 14-Lead TSSOP (MCP6234) Example: XXXXXXXX YYWW 6234E 0929 NNN 256 DS20001881G-page 20  2004-2020 Microchip Technology Inc. MCP6231/1R/1U/2/4 5-Lead Plastic Small Outline Transistor (LT) [SC70] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A e e 3 B 1 E1 E 2X 0.15 C 4 N 5X TIPS 0.30 C NOTE 1 2X 0.15 C 5X b 0.10 C A B TOP VIEW C c A2 A SEATING PLANE A1 L SIDE VIEW END VIEW Microchip Technology Drawing C04-061-LT Rev E Sheet 1 of 2  2004-2020 Microchip Technology Inc. DS20001881G-page 21 MCP6231/1R/1U/2/4 5-Lead Plastic Small Outline Transistor (LT) [SC70] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch Overall Height A Standoff A1 A2 Molded Package Thickness Overall Length D Overall Width E Molded Package Width E1 b Terminal Width Terminal Length L c Lead Thickness MIN 0.80 0.00 0.80 0.15 0.10 0.08 MILLIMETERS NOM 5 0.65 BSC 2.00 BSC 2.10 BSC 1.25 BSC 0.20 - MAX 1.10 0.10 1.00 0.40 0.46 0.26 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-061-LT Rev E Sheet 2 of 2 DS20001881G-page 22  2004-2020 Microchip Technology Inc. MCP6231/1R/1U/2/4 5-Lead Plastic Small Outline Transistor (LT) [SC70] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E Gx SILK SCREEN 3 2 1 C G 4 5 Y X RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Contact Pad Spacing C Contact Pad Width X Contact Pad Length Y Distance Between Pads G Distance Between Pads Gx MIN MILLIMETERS NOM 0.65 BSC 2.20 MAX 0.45 0.95 1.25 0.20 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2061-LT Rev E  2004-2020 Microchip Technology Inc. DS20001881G-page 23 MCP6231/1R/1U/2/4 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 0.20 C 2X D e1 A D N E/2 E1/2 E1 E (DATUM D) (DATUM A-B) 0.15 C D 2X NOTE 1 1 2 e B NX b 0.20 C A-B D TOP VIEW A A A2 0.20 C SEATING PLANE A SEE SHEET 2 A1 C SIDE VIEW Microchip Technology Drawing C04-091-OT Rev F Sheet 1 of 2 DS20001881G-page 24  2004-2020 Microchip Technology Inc. MCP6231/1R/1U/2/4 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging c T L L1 VIEW A-A SHEET 1 Units Dimension Limits N Number of Pins e Pitch e1 Outside lead pitch A Overall Height A2 Molded Package Thickness Standoff A1 Overall Width E Molded Package Width E1 Overall Length D Foot Length L Footprint L1 I Foot Angle c Lead Thickness b Lead Width MIN 0.90 0.89 - 0.30 0° 0.08 0.20 MILLIMETERS NOM 5 0.95 BSC 1.90 BSC 2.80 BSC 1.60 BSC 2.90 BSC 0.60 REF - MAX 1.45 1.30 0.15 0.60 10° 0.26 0.51 Notes: 1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25mm per side. 2. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-091-OT Rev F Sheet 2 of 2  2004-2020 Microchip Technology Inc. DS20001881G-page 25 MCP6231/1R/1U/2/4 5-Lead Plastic Small Outline Transistor (OT) [SOT23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging X SILK SCREEN 5 Y Z C G 1 2 E GX RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch C Contact Pad Spacing X Contact Pad Width (X5) Contact Pad Length (X5) Y Distance Between Pads G Distance Between Pads GX Overall Width Z MIN MILLIMETERS NOM 0.95 BSC 2.80 MAX 0.60 1.10 1.70 0.35 3.90 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing No. C04-2091-OT Rev F DS20001881G-page 26  2004-2020 Microchip Technology Inc. MCP6231/1R/1U/2/4       !""#$%& ' -      $#  *... e D b N N L K E2 E EXPOSED PAD NOTE 1 NOTE 1 2 1 2 1 D2 BOTTOM VIEW TOP VIEW A A3 A1 NOTE 2 / ! 1 2  $0110$%+%,# $02 2 23$ $"4 5   37 " 656 686 66 #  " 666 66 66' )+ " 66,%- 31 ! 66(#) 39  % %   1 ! 6 : %   9  % '6 : ;'  66 6' 66 )1 1 66 6 6 6'6 )