MCP6N16
Zero-Drift Instrumentation Amplifier
Features:
Description:
• High DC Precision:
- VOS: ±17 µV (maximum, GMIN = 100)
- TC1: ±60 nV/°C (maximum, GMIN = 100)
- CMRR: 112 dB (minimum, GMIN = 100,
VDD = 5.5V)
- PSRR: 110 dB (minimum, GMIN = 100,
VDD = 5.5V)
- gE: ±0.15% (maximum, GMIN = 10, 100)
• Flexible:
- Minimum Gain (GMIN) Options:
1, 10 and 100 V/V
- Rail-to-Rail Input and Output
- Gain Set by Two External Resistors
• Bandwidth: 500 kHz (typical, Gain = GMIN = 1, 10)
• Power Supply:
- VDD: 1.8V to 5.5V
- IQ: 1.1 mA (typical)
- Power Savings (Enable) Pin: EN
• Enhanced EMI Protection:
- Electromagnetic Interference Rejection Ratio
(EMIRR): 111 dB at 2.4 GHz
• Extended Temperature Range: -40°C to +125°C
Microchip Technology Inc. offers the single Zero-Drift
MCP6N16 instrumentation amplifier (INA) with Enable
pin (EN) and three minimum gain options (GMIN). The
internal offset correction gives high DC precision: it has
very low offset and offset drift, and negligible 1/f noise.
Two external resistors set the gain, minimizing gain
error and drift over temperature. The reference voltage
(VREF) shifts the output voltage (VOUT).
The MCP6N16 is designed for single-supply operation,
with rail-to-rail input (no common mode crossover
distortion) and output performance. The supply voltage
range (1.8V to 5.5V) is low enough to support many
portable applications. All devices are fully specified
from -40°C to +125°C. Each part has EMI filters at the
input pins, for good EMI rejection (EMIRR).
These parts have three minimum gain options (1, 10
and 100 V/V). This allows the user to optimize the input
offset voltage and input noise for different applications.
Typical Application Circuit
VDD
RTD Temperature Sensor
2.49 kΩ
10 µF
Typical Applications:
•
•
•
•
High-Side Current Sensor
Wheatstone Bridge Sensors
Difference Amplifier with Level Shifting
Power Control Loops
Design Aids:
• SPICE Macro Model
• Microchip Advanced Part Selector (MAPS)
• Application Notes
EN
4.99 kΩ
4.99 kΩ
68.1Ω
RTD
100Ω
MCP6N16-100
VOUT
20 kΩ
100Ω
4.99 kΩ
100Ω
Package Types
MCP6N16
MSOP
MCP6N16
3×3 DFN *
EN 1
8 VDD
EN 1
VIM 2
7 VOUT
VIM 2
VIP 3
VSS 4
6 VFG
5 VREF
VSS 4
VIP 3
8 VDD
EP
9
7 VOUT
6 VFG
5 VREF
* Includes Exposed Thermal Pad (EP); see Table 3-1.
2014 Microchip Technology Inc.
DS20005318A-page 1
MCP6N16
Minimum Gain Options
Table 1 shows key specifications that differentiate
between the different minimum gain (GMIN) options.
See Section 1.0 “Electrical Characteristics”,
Section 6.0 “Packaging Information” and Product
Identification System for further information on GMIN.
TABLE 1:
KEY DIFFERENTIATING SPECIFICATIONS
GMIN VOS
(V/V) (±μV)
Nom. Max.
Part No.
MCP6N16-001
1
CMRR
eni
TC1
Eni
PSRR VDMH GBWP
(±nV/°C)
(dB)
(μVP-P)
(nV/√Hz)
(V)
(MHz)
(dB)
Max.
Min.
Typ.
Typ.
Min. Min.
Typ.
TA = -40 to +125°C VDD = 5.5V
f = 0.1 to 10 Hz f < 500 Hz
85
1800
89
91
2.7
0.50
19
900
MCP6N16-010
10
22
180
103
104
0.27
5.0
2.2
105
MCP6N16-100
100
17
60
112
110
0.027
35
0.93
45
GMIN is the minimum stable gain (GDM), for a given part option. In other words, GDM ≥ GMIN.
Figures 1 to 3 show input offset voltage versus
temperature for the three gain options (GMIN = 1, 10,
100 V/V).
40
Input O
Offset Voltage (µV)
30
20
10
0
4
3
Input Offset
O
V
Voltage
e (µV)
Note 1:
2
1
0
-1
GMIN = 100
28 Samples
VDD = 5.5V
5 5V
VCM = VDD/2
NPBW = 3 mHz
-2
-3
-10
0
-4
4
GMIN = 1
28 Samples
VDD = 5.5V
VCM = VDD/2
NPBW = 3 mHz
-20
-30
-50
-40
-50
-25
0
25
50
75
Ambient Temperature (°C)
100
125
-25
0
25
50
75
Ambient Temperature (°C)
100
125
FIGURE 3:
Input Offset Voltage vs.
Temperature, with GMIN = 100.
FIGURE 1:
Input Offset Voltage vs.
Temperature, with GMIN = 1.
4
Input Offset
O
V
Voltage
e (µV)
3
2
1
0
-1
GMIN = 10
28 Samples
VDD = 5.5V
5 5V
VCM = VDD/2
NPBW = 3 mHz
-2
-3
-4
4
-50
-25
0
25
50
75
Ambient Temperature (°C)
100
125
FIGURE 2:
Input Offset Voltage vs.
Temperature, with GMIN = 10.
DS20005318A-page 2
2014 Microchip Technology Inc.
2014 Microchip Technology Inc.
1.0
ELECTRICAL CHARACTERISTICS
1.1
Absolute Maximum Ratings †
VDD – VSS ............................................................................................................................................................................................................................................ 6.5V
Current at Input Pins (Note 1) ........................................................................................................................................................................................................... ±2 mA
Analog Inputs (VIP and VIM) (Note 1) .................................................................................................................................................................. VSS – 1.0V to VDD + 1.0V
All Other Inputs and Outputs ............................................................................................................................................................................... VSS – 0.3V to VDD + 0.3V
Difference Input Voltage ............................................................................................................................................................................................................. |VDD – VSS|
Output Short-Circuit Current ...................................................................................................................................................................................................... Continuous
Current at Output and Supply Pins .................................................................................................................................................................................................. ±30 mA
Storage Temperature ......................................................................................................................................................................................................... -65°C to +150°C
Maximum Junction Temperature ......................................................................................................................................................................................................+150°C
ESD protection on all pins (HBM, MM)..................................................................................................................................................................................... ≥ 4 kV, 400V
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
Note 1: See Section 4.3.1.2 “Input Voltage Limits” and Section 4.3.1.3 “Input Current Limits”.
MCP6N16
DS20005318A-page 3
Specifications
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 kΩ
to VL, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8 (Note 1).
Parameters
Sym.
Min.
Typ.
Max.
Units
VOS
-85
—
+85
µV
-22
—
+22
GMIN
Conditions
Input Offset
Input Offset Voltage
Input Offset Voltage Drift –
Linear Temp. Co.
TC1
Input Offset Voltage Drift –
Quadratic Temp. Co.
TC2
Input Offset Aging
Power Supply Rejection Ratio
∆VOS
PSRR
-17
—
+17
-1800
—
+1800
-180
—
+180
-60
—
+60
—
±560
—
—
±63
—
—
±69
—
—
±1.0
—
—
±0.8
—
1
TA = +25°C
10
100
nV/°C
1
TA = -40°C to +125°C (Note 2)
10
100
pV/°C2
1
TA = -40°C to +125°C
10
100
µV
1
10
—
±0.7
—
91
109
—
104
122
—
10
110
128
—
100
408 hr Life Test at +150°C,
measured at +25°C
100
dB
1
Output Offset
Output Offset Voltage
0
VOSO
µV
all
pA
all
Input Current and Impedance (Note 3)
2014 Microchip Technology Inc.
-100
±2
+100
Across Temperature
—
20
—
TA = +85°C
Across Temperature
0
250
2000
TA = +125°C
Input Bias Current
Note 1:
2:
3:
4:
5:
6:
IB
VCM = (VIP + VIM)/2, VDM = (VIP – VIM) and GDM = 1 + RF/RG.
For Design Guidance only; not tested.
These specifications apply to the VIP, VIM input pair (use VCM) and to the VREF, VFG input pair (use VREF instead).
This specification applies to the VIP, VIM, VREF and VFG pins individually.
Figures 2-52 and 2-53 show the VIVL, VIVH, VDML and VDMH variation over temperature.
See Section 1.5 “Explanation of DC Error Specifications”.
MCP6N16
DS20005318A-page 4
1.2
2014 Microchip Technology Inc.
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 kΩ
to VL, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8 (Note 1).
Parameters
Conditions
Sym.
Min.
Typ.
Max.
Units
GMIN
IOS
-800
±300
+800
pA
all
Across Temperature
—
±320
—
TA = +85°C
Across Temperature
-1500
±350
+1500
TA = +125°C
Input Offset Current
Common Mode Input Impedance
ZCM
—
1013||10
—
Differential Input Impedance
ZDIFF
—
1013||4
—
VIVL
—
VSS – 0.25
VSS – 0.15
VIVH
VDD + 0.15
VDD + 0.30
—
CMRR
80
98
—
Ω||pF
Input Common Mode Voltage (VCM or VREF) (Note 3)
Input Voltage Range (Note 4, Note 5)
Common Mode Rejection Ratio
Common Mode Rejection Ratio at VREF
all
dB
1
94
112
—
10
103
121
—
100
89
107
—
1
103
121
—
10
112
130
—
83
101
—
VCM = VIVL to VIVH, VDD = 1.8V
VCM = VIVL to VIVH, VDD = 5.5V
100
dB
1
98
116
—
10
102
120
—
100
94
112
—
1
109
127
—
10
115
133
—
100
VCM = (VIP + VIM)/2, VDM = (VIP – VIM) and GDM = 1 + RF/RG.
For Design Guidance only; not tested.
These specifications apply to the VIP, VIM input pair (use VCM) and to the VREF, VFG input pair (use VREF instead).
This specification applies to the VIP, VIM, VREF and VFG pins individually.
Figures 2-52 and 2-53 show the VIVL, VIVH, VDML and VDMH variation over temperature.
See Section 1.5 “Explanation of DC Error Specifications”.
VREF = 0.2V to VDD – 0.2V,
VDD = 1.8V
VREF = 0.2V to VDD – 0.2V,
VDD = 5.5V
MCP6N16
DS20005318A-page 5
Note 1:
2:
3:
4:
5:
6:
CMRR2
V
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 kΩ
to VL, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8 (Note 1).
Parameters
Common Mode Nonlinearity (Note 6)
Sym.
Min.
Typ.
Max.
Units
INLCM
GMIN
-550
—
+550
ppm
-75
—
+75
10
1
-20
—
+20
100
-310
—
+310
1
-35
—
+35
10
-10
—
+10
100
VDML
—
-3.4/GMIN
-2.7/GMIN
VDMH
+2.7/GMIN
+3.4/GMIN
—
gE
—
±0.03
—
%
—
±0.02
—
%
—
±0.03
—
—
±0.02
—
Conditions
VCM = VIVL to VIVH, VDD = 1.8V
VCM = VIVL to VIVH, VDD = 5.5V
Input Differential Voltage (VDM) (Note 3)
Differential Input Voltage Range (Note 5)
Differential Gain Error (Note 6)
2014 Microchip Technology Inc.
Note 1:
2:
3:
4:
5:
6:
V
all
VDD ≥ 2.9V, VREF = VDD,
VOUT within ±0.2%
VDD ≥ 2.9V, VREF = 0V,
VOUT within ±0.2%
1
VDD = 1.8V, VREF = VDD/2,
10, 100 VDM = ±(0.7V)/GMIN
1
VDD = 5.5V, VREF = VDD/2,
10, 100 VDM = ±(2.55V)/GMIN
-0.25
±0.04
+0.25
%
-0.15
±0.02
+0.15
%
-0.25
±0.04
+0.25
%
-0.15
±0.02
+0.15
%
1
VDD = 5.5V, VREF = 0.2V,
10, 100 VDM = 0 to (2.7V)/GMIN
1
VDD = 5.5V, VREF = 5.3V,
10, 100 VDM = 0 to (-2.7V)/GMIN
VCM = (VIP + VIM)/2, VDM = (VIP – VIM) and GDM = 1 + RF/RG.
For Design Guidance only; not tested.
These specifications apply to the VIP, VIM input pair (use VCM) and to the VREF, VFG input pair (use VREF instead).
This specification applies to the VIP, VIM, VREF and VFG pins individually.
Figures 2-52 and 2-53 show the VIVL, VIVH, VDML and VDMH variation over temperature.
See Section 1.5 “Explanation of DC Error Specifications”.
MCP6N16
DS20005318A-page 6
TABLE 1-1:
2014 Microchip Technology Inc.
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 kΩ
to VL, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8 (Note 1).
Parameters
Differential Gain Drift (Note 6)
Differential Nonlinearity (Note 6)
DC Open-Loop Gain
Min.
Typ.
Max.
Units
GMIN
∆gE/∆TA
—
±3
—
ppm/°C
all
—
±4
—
VDD = 5.5V, VREF = VDD/2,
VDM = ±(2.55V)/GMIN
—
±4
—
VDD = 5.5V, VREF = 0.2V,
VDM = 0 to (2.7V)/GMIN
—
±3
—
VDD = 5.5V, VREF = 5.3V,
VDM = 0 to (-2.7V)/GMIN
—
±300
—
—
±150
—
VDD = 5.5V, VREF = VDD/2,
VDM = ±(2.55V)/GMIN
—
±300
—
VDD = 5.5V, VREF = 0.2V,
VDM = 0 to (2.7V)/GMIN
—
±300
—
VDD = 5.5V, VREF = 5.3V,
VDM = 0 to (-2.7V)/GMIN
84
102
—
100
118
—
10
108
126
—
100
INLDM
AOL
ppm
all
dB
1
95
113
—
1
111
129
—
10
119
137
—
100
VCM = (VIP + VIM)/2, VDM = (VIP – VIM) and GDM = 1 + RF/RG.
For Design Guidance only; not tested.
These specifications apply to the VIP, VIM input pair (use VCM) and to the VREF, VFG input pair (use VREF instead).
This specification applies to the VIP, VIM, VREF and VFG pins individually.
Figures 2-52 and 2-53 show the VIVL, VIVH, VDML and VDMH variation over temperature.
See Section 1.5 “Explanation of DC Error Specifications”.
VDD = 1.8V, VREF = VDD/2,
VDM = ±(0.7V)/GMIN
VDD = 1.8V, VREF = VDD/2,
VDM = ±(0.7V)/GMIN
VDD = 1.8V,
VOUT = 0.2V to 1.6V
VDD = 5.5V,
VOUT = 0.2V to 5.3V
MCP6N16
DS20005318A-page 7
Note 1:
2:
3:
4:
5:
6:
Conditions
Sym.
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2, RL = 10 kΩ
to VL, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8 (Note 1).
Parameters
Conditions
Sym.
Min.
Typ.
Max.
Units
GMIN
VOL
—
VSS + 3
—
mV
all
—
VSS + 6
—
RL = 10 kΩ, VDD = 5.5V,
VDM = -VDD/(2GMIN),
VREF = VDD/2 – 1V
—
VSS + 60
VSS + 250
RL = 1 kΩ, VDD = 5.5V,
VDM = -VDD/(2GMIN),
VREF = VDD/2 – 1V
—
VDD – 3
—
—
VDD – 6
—
RL = 10 kΩ, VDD = 5.5V,
VDM = VDD/(2GMIN),
VREF = VDD/2 + 1V
VDD – 250
VDD – 60
—
RL = 1 kΩ, VDD = 5.5V,
VDM = VDD/(2GMIN),
VREF = VDD/2 + 1V
—
±10
—
—
±35
—
Output
Minimum Output Voltage Swing
Maximum Output Voltage Swing
Output Short-Circuit Current
VOH
ISC
mV
RL = 10 kΩ, VDD = 1.8V,
VDM = -VDD/(2GMIN),
VREF = VDD/2 – 0.9V
RL = 10 kΩ, VDD = 1.8V,
VDM = VDD/(2GMIN),
VREF = VDD/2 + 0.9V
mA
VDD = 1.8V
VDD = 5.5V
Power Supply
Supply Voltage
2014 Microchip Technology Inc.
Quiescent Current per Amplifier
POR Trip Voltage
Note 1:
2:
3:
4:
5:
6:
VDD
1.8
—
5.5
V
IQ
0.5
1.1
1.6
mA
VPRL
0.9
1.27
—
V
VPRH
—
1.33
1.6
V
VCM = (VIP + VIM)/2, VDM = (VIP – VIM) and GDM = 1 + RF/RG.
For Design Guidance only; not tested.
These specifications apply to the VIP, VIM input pair (use VCM) and to the VREF, VFG input pair (use VREF instead).
This specification applies to the VIP, VIM, VREF and VFG pins individually.
Figures 2-52 and 2-53 show the VIVL, VIVH, VDML and VDMH variation over temperature.
See Section 1.5 “Explanation of DC Error Specifications”.
all
IO = 0
MCP6N16
DS20005318A-page 8
TABLE 1-1:
2014 Microchip Technology Inc.
TABLE 1-2:
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2,
RL = 10 kΩ to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.
Parameters
Sym.
Min.
Typ.
Max.
Units
MHz
GMIN
Conditions
AC Response
Gain-Bandwidth Product
Phase Margin
GBWP
PM
—
0.5
—
—
5
—
—
35
—
—
70
—
°
100
Open-Loop Output Impedance
ROL
—
1.6
—
kΩ
Power Supply Rejection Ratio
PSRR
—
80
—
dB
Common Mode Rejection Ratio
at VCM and VREF
CMRR, CMRR2
1
10
all
1
—
98
—
10
—
123
—
100
—
83
—
—
80
—
dB
10
1
—
140
—
100
f = 1 kHz
f = 10 kHz
Step Response (see Section 4.1.4 “AC Performance”)
Slew Rate
SR
Start-Up Time
tSTR
Note 1
V/µs
all
ms
1
—
2
—
—
0.3
—
10
—
0.2
—
100
tIRC
—
1
—
Overdrive Recovery,
Input Differential Mode
tIRD
—
10
—
GMINVDM = GMINVDMH + 0.5V to 0V (or GMINVDML – 0.5V to 0V),
VREF = 1V (or VDD – 1V), 90% of VOUT change (Note 4)
Overdrive Recovery, Output
tOR
—
180
—
GDMVDM = 1.5V to 0V (or -1.5V to 0V),
VREF = VDD – 1V (or 1V), 90% of VOUT change (Note 4)
DS20005318A-page 9
3:
4:
all
VIP =VIM = VIVH + 0.5V to VDD – 1V (or VIVL – 0.5V to 1V),
90% of VOUT change (IB ≤ 2 mA) (Note 4)
The slew rate is limited by the GBWP; the large signal step response is dominated by the small signal bandwidth.
These parameters were characterized using the circuit in Figure 1-8. In Figures 2-75 and 2-76, there is an IMD tone at DC, a residual tone at 100 Hz and
other IMD tones and clock tones.
High gains behave differently; see Section 4.4.4 “Offset at Power-Up”.
tSTR, tSTL, tIRC, tIRD and tOR include some uncertainty due to clock edge timing.
MCP6N16
Overdrive Recovery,
Input Common Mode
Note 1:
2:
µs
GDM = 1000, VDD power up to 0.1% VOUT settling (Note 3, Note 4)
AC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2,
RL = 10 kΩ to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.
Parameters
Sym.
Min.
Typ.
Max.
Units
GMIN
eni
—
900
—
nV/√Hz
1
—
105
—
10
—
45
—
100
—
19
—
—
2.2
—
10
—
0.93
—
100
—
5.9
—
1
—
0.69
—
10
—
0.30
—
100
—
7
—
Conditions
Noise
Input Noise Voltage Density
Input Noise Voltage
Eni
µVP-P
fA/√Hz
Input Current Noise Density
ini
Output Noise Voltage Density
eno
0
nV/√Hz
Output Noise Voltage
Eno
0
µVP-P
1
f = 500 Hz
f = 0.1 Hz to 10 Hz
f = 0.01 Hz to 1 Hz
all
f = 1 kHz
Amplifier Distortion (Note 2)
Intermodulation Distortion (AC)
IMD
—
5
—
µVPK
all
VCM tone = 100 mVPK at 100 Hz
dB
all
VIN = 0.1 VPK, f = 400 MHz
EMI Protection
EMI Rejection Ratio
2014 Microchip Technology Inc.
Note 1:
2:
3:
4:
EMIRR
—
103
—
—
106
—
VIN = 0.1 VPK, f = 900 MHz
—
106
—
VIN = 0.1 VPK, f = 1800 MHz
—
111
—
VIN = 0.1 VPK, f = 2400 MHz
The slew rate is limited by the GBWP; the large signal step response is dominated by the small signal bandwidth.
These parameters were characterized using the circuit in Figure 1-8. In Figures 2-75 and 2-76, there is an IMD tone at DC, a residual tone at 100 Hz and
other IMD tones and clock tones.
High gains behave differently; see Section 4.4.4 “Offset at Power-Up”.
tSTR, tSTL, tIRC, tIRD and tOR include some uncertainty due to clock edge timing.
MCP6N16
DS20005318A-page 10
TABLE 1-2:
2014 Microchip Technology Inc.
TABLE 1-3:
DIGITAL ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V, VREF = VDD/2, VL = VDD/2,
RL = 10 kΩ to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.
Parameters
Sym.
Min.
Typ.
Max.
Units GMIN
EN Logic Threshold, Low
VIL
—
—
0.2VDD
V
EN Input Current, Low
IENL
—
-10
—
pA
EN = 0V
GND Current
ISS
-8
-2
—
µA
EN = 0V, VDD = 5.5V
IO(LEAK)
—
-1
—
nA
EN = 0V
EN Logic Threshold, High
VIH
0.8VDD
—
—
V
EN Input Current, High
IENH
—
10
—
pA
VHYST
—
0.16VDD
—
V
EN Input Resistance
RPD
—
1013
—
Ω
EN Low to Amplifier Output High Z Turn-Off Time
tOFF
—
0.1
2
µs
EN High to Amplifier Output On Time
tON
—
12
100
VDD = 1.8V, EN = 0.8VDD to VOUT = 0.9(VDD/2), VL = 0V
—
30
100
VDD = 5.5V, EN = 0.8VDD to VOUT = 0.9(VDD/2), VL = 0V
Conditions
EN Low Specifications
Amplifier Output Leakage
all
EN High Specifications
all
EN = VDD
EN Dynamic Specifications
EN Input Hysteresis
all
EN = 0.2VDD to VOUT = 0.1(VDD/2), VL = 0V
EN Low to EN High hold time
tENLH
50
—
—
Minimum time before releasing EN (Note 1)
EN High to EN Low setup time
tENHL
50
—
—
Minimum time before exerting EN (Note 1)
VDD ↓ to Output Off
tPHL
—
10
—
VDD ↑ to Output On
tPLH
—
100
—
POR Dynamic Specifications
For design guidance only; not tested.
all
VL = 0V, VDD = 1.8V to VPRL – 0.1V step, 90% of VOUT change
VL = 0V, VDD = 0V to VPRH + 0.1V step, 90% of VOUT change
DS20005318A-page 11
MCP6N16
Note 1:
µs
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = 1.8V to 5.5V, VSS = GND.
Parameters
Sym.
Min.
Typ.
Max.
Units
Specified Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
Storage Temperature Range
TA
-65
—
+150
Thermal Resistance, 8L-DFN (3×3)
θJA
—
57
—
Thermal Resistance, 8L-MSOP
θJA
—
211
—
Conditions
Temperature Ranges
Note 1
Thermal Package Resistances
Note 1:
Operation must not cause TJ to exceed the Absolute Maximum Junction Temperature specification (+150°C).
°C/W
MCP6N16
DS20005318A-page 12
TABLE 1-4:
2014 Microchip Technology Inc.
MCP6N16
1.3
Timing Diagrams
1.8V to 5.5V
1.8V
VDD 0V
tSTR
1.001 VREF
VOUT
0.999 VREF
FIGURE 1-1:
VCM
Amplifier Start-Up Timing Diagram.
VDD – 1V
VIVH + 0.5V
tIRC
VOUT
1V
VDD – 1V
0V
GMINVDMH + 0.5V
tIRD
VREF
VOH
FIGURE 1-3:
tIRD
VOL
VDD – 1V
GMINVDM
1.5V
VOUT
VOH
VREF
1V
0V
0V
-1.5V
tOR
FIGURE 1-4:
VREF
tOR
VOL
VREF
Output Overdrive Recovery Timing Diagram.
VPRH + 0.1V
VPRL – 0.1V
1.8V
tPHL
0V
High Z
VOUT
FIGURE 1-5:
0V
GMINVDML – 0.5V
Differential Mode Input Overdrive Recovery Timing Diagram.
VREF
VDD
VREF
Common Mode Input Overdrive Recovery Timing Diagram.
VREF
GDMVDM
tIRC
VREF
VOUT
FIGURE 1-2:
1V
VIVL – 0.5V
tPLH
High Z
POR Timing Diagram.
EN
tENHL
tENLH
tOFF
High Z
VOUT
FIGURE 1-6:
tON
High Z
EN Timing Diagram.
2014 Microchip Technology Inc.
DS20005318A-page 13
MCP6N16
1.4
DC Test Circuits
1.4.1
1.4.2
INPUT OFFSET TEST CIRCUIT
Figure 1-7 is a simple circuit that can test the INA’s
input offset errors and input voltage range (VE, VIVL and
VIVH; see Section 1.5.1 “Input Offset Related
Errors” and Section 1.5.2 “Input Offset Common
Mode Nonlinearity”). U2 is part of a control loop that
forces VOUT to equal VCNT; U1 can be set to any bias
point.
VDD
Figure 1-8 is a simple circuit that can test the INA’s
differential gain error, nonlinearity and input voltage
range (gE, INLDM, VDML and VDMH; see Section 1.5.3
“Differential Gain Error and Nonlinearity”). RF and
RG are 0.01% for accurate gain error measurements.
The output voltages are (where VE is the sum of input
offset errors and gE is the gain error):
EQUATION 1-2:
G DM = 1 + RF RG
VL
V OUT = VREF + G DM 1 + g E V DM + VE
100 nF
2.2 µF
VM = V REF + G DM 1 + g E V DM + V E
RL
100Ω
VCM
DIFFERENTIAL GAIN TEST CIRCUIT
VOUT
U1
VDD
MCP6N16
100Ω
VREF
RG
100Ω
VL
VCM + VDM/2
RF
100Ω
MCP6N16
U2
MCP6H01
10 µF
CCNT
2.2 nF
RCNT
31.6 kΩ
VOUT
RF
100Ω
31.6 kΩ
31.6 kΩ
RL
100 nF
U1
2.2 nF
VM
2.2 µF
VCNT
VCM – VDM/2
VM
63.4 kΩ
1.0 µF
RG
VREF
FIGURE 1-7:
Simple Test Circuit for
Common Mode (Input Offset).
FIGURE 1-8:
Differential Mode.
When MCP6N16 is in its normal range of operation, the
DC output voltages are (where VE is the sum of input
offset errors and gE is the gain error):
For different values of VREF, VDM sweeps over different
ranges to keep VREF, VFG and VOUT within their ranges.
EQUATION 1-1:
V OUT = V CNT
VM = V REF + G DM 1 + g E V E
Table 1-5 shows the resulting behavior for different
GMIN options.
TABLE 1-5:
GMIN
(V/V)
Nom.
RESULTS
RF
GDM
(kΩ) (kV/V)
Typ. Typ.
GDMVOS
(±mV)
Max.
BW
(Hz)
Typ.
at VM
0.50
1
100
1.00
85
0.50
402
4.02
88
1.2
68
8.7
DS20005318A-page 14
SELECTING RF AND RG
GMIN
(V/V)
Nom.
RF
(kΩ)
Nom.
RG
(kΩ)
Nom.
GDM
(V/V)
Nom.
1
0
Open
1.0000
10
10.0 || 90.9
1.00
10.009
100
10.0 || 1000
100
100.01
1.4.3
BW
(kHz)
Typ.
at VOUT
10
100
Table 1-6 shows the recommended RF and RG; they
produce a 10 kΩ load. VL can usually be left open.
TABLE 1-6:
G DM = 1 + RF RG
Simple Test Circuit for
DYNAMIC TESTING OF INPUT
BEHAVIOR
The circuit in Figure 1-8 can test the input’s dynamic
behavior (i.e., IMD, tSTR, tSTL, tIRC, tIRD and tOR);
measure the output at VOUT, instead of at VM.
2014 Microchip Technology Inc.
MCP6N16
1.5
1.5.1
Explanation of DC Error
Specifications
VE, VE_LIN (V)
INPUT OFFSET RELATED ERRORS
The input offset error (VE) is extracted from input offset
measurements (see Section 1.4.1 “Input Offset Test
Circuit”), based on Equation 1-1:
VE_LIN
V3
VE
V2
EQUATION 1-3:
V E = V M – V REF G DM 1 + g E
VE has several terms, which assume a linear response
to changes in VDD, VSS, VCM, VOUT and TA (all of which
are in their specified ranges):
EQUATION 1-4:
V DD – V SS
V CM
V REF
V E = V OS + --------------------------------- + ----------------- + -------------------PSRR
CMRR CMRR2
V OUT
+ ----------------- + T A TC 1
A OL
Where:
PSRR, CMRR, CMRR2 and AOL are in
units of V/V
∆TA is in units of °C
TC1 is in units of V/°C
VDM = 0
Equation 1-2 shows how VE affects VOUT.
1.5.2
INPUT OFFSET COMMON MODE
NONLINEARITY
The input offset error (VE) changes nonlinearly with
VCM. Figure 1-9 shows VE vs. VCM, as well as a linear
fit line (VE_LIN) based on VOS and CMRR. The INA is in
standard conditions (∆VOUT = 0, VDM = 0, etc.). VCM is
swept from VIVL to VIVH. The test circuit is in
Section 1.4.1 “Input Offset Test Circuit” and VE is
calculated using Equation 1-3.
V1
VE
VIVL
VCM (V)
VDD/2
VIVH
FIGURE 1-9:
Input Offset Error vs.
Common Mode Input Voltage.
Based on the measured VE data, we obtain the
following linear fit:
EQUATION 1-5:
V E_LIN = V OS + VCM – V DD 2 CMRR
Where:
V OS = V2
1 CMRR = V3 – V 1 V IVH – V IVL
The remaining error (∆VE) is described by the Common
Mode Nonlinearity spec:
EQUATION 1-6:
INL CMH = max VE V IVH – VIVL
INL CML = min V E VIVH – V IVL
INL CM = INL CMH
INL CMH INL CML
= INL CML
otherwise
Where:
V E = V E – V E_LIN
The same common mode behavior applies to VE when
VREF is swept, instead of VCM, since both input stages
are designed the same:
EQUATION 1-7:
VE_LIN2
INL CMH2
INL CML2
INL CM2
=
=
=
=
=
VOS + V REF – V DD 2 CMRR2
max V E2 V IVH – V IVL
min V E2 VIVH – V IVL
INL CMH2
INL CMH2 INL CML2
INL CML2 otherwise
Where:
V E2 = V E – VE_LIN2
2014 Microchip Technology Inc.
DS20005318A-page 15
MCP6N16
1.5.3
DIFFERENTIAL GAIN ERROR AND
NONLINEARITY
The differential errors are extracted from differential
gain measurements (see Section 1.4.2 “Differential
Gain Test Circuit”), based on Equation 1-2. These
errors are the differential gain error (gE) and the input
offset error (VE, which changes nonlinearly with VDM):
EQUATION 1-11:
INL DMH = max VED VDMH – VDML
INL DML = min VED V DMH – V DML
INL DM = INL DMH
INL DMH INL DML
= INL DML otherwise
Where:
V ED = V ED – VED_LIN
EQUATION 1-8:
G DM = 1 + RF R G
VM = G DM 1 + g E V DM + V E
These errors are adjusted for the expected output, then
referred back to the input, giving the differential input
error (VED) as a function of VDM:
EQUATION 1-9:
VED = V M GDM – V DM
Figure 1-10 shows VED vs. VDM, as well as a linear fit
line (VED_LIN) based on VED and gE. The INA is in
standard conditions (∆VOUT = 0, etc.). VDM is swept
from VDML to VDMH.
VED, VED_LIN (V)
VED_LIN
V3
VED
V2
V1
VED
VDML
VDM (V)
0
VDMH
FIGURE 1-10:
Differential Input Error vs.
Differential Input Voltage.
Based on the measured VED data, we obtain the
following linear fit:
EQUATION 1-10:
V ED_LIN = 1 + g E V E + g E VDM
Where:
g E = V 3 – V1 V DMH – V DML – 1
VE = V2 1 + gE
Note that the VE value measured here is not as
accurate as the one obtained in Section 1.5.1 “Input
Offset Related Errors”.
The remaining error (∆VED) is described by the
Differential Nonlinearity spec:
DS20005318A-page 16
2014 Microchip Technology Inc.
MCP6N16
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.
2.1
DC Precision
40%
GMIN = 1
28 Samples
TA = +25°C
NPBW = 3 mHz
25%
20%
VDD = 1.8V
1 8V
VDD = 5.5V
15%
10%
5%
Pe
ercenta
age of O
Occurrrences
s
Pe
ercenta
age of O
Occurrrences
s
30%
0%
-6 -4 -2 0 2 4 6
Input Offset Voltage (µV)
FIGURE 2-1:
GMIN = 1.
8
Input Offset Voltage, with
15%
%
10%
5%
25%
20%
VDD = 1.8V
15%
VDD = 5.5V
10%
5%
FIGURE 2-4:
with GMIN = 1.
0%
35%
30%
600
Input Offset Voltage Drift,
GMIN = 10
28 Samples
TA = -40 to +125°C
NPBW = 3 mHz
25%
VDD = 5.5V
VDD = 1.8V
1 8V
20%
15%
%
10%
5%
0%
-2.0 -1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0
Input Offset Voltage (µV)
FIGURE 2-2:
GMIN = 10.
Input Offset Voltage, with
-40
-30 -20 -10
0
10
20
30
Input Offset Voltage Drift; TC1 (nV/°C)
FIGURE 2-5:
with GMIN = 10.
60%
40
Input Offset Voltage Drift,
40%
GMIN = 100
28 Samples
TA = +25°C
NPBW = 3 mHz
40%
30%
VDD = 5.5V
VDD = 1.8V
20%
10%
0%
Pe
ercenta
age of O
Occurrrences
s
Percentage of Occurrences
-400
-200
0
200
400
Input Offset Voltage Drift; TC1 (nV/°C)
40%
GMIN = 10
28 Samples
TA = +25°C
NPBW = 3 mHz
30%
50%
VDD = 1.8V
VDD = 5.5V
5 5V
20%
-600
Pe
ercenta
age of O
Occurrrences
s
Percentage of Occurrences
25%
10 12
45%
35%
30%
GMIN = 1
28 Samples
TA = -40 to +125°C
NPBW = 3 mHz
0%
-12 -10 -8
40%
35%
35%
30%
GMIN = 100
28 Samples
TA = -40 to +125°C
NPBW = 3 mHz
25%
20%
VDD = 1.8V
VDD = 5.5V
15%
%
10%
5%
0%
-1.0 -0.6 -0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0
Input Offset Voltage (µV)
FIGURE 2-3:
GMIN = 100.
Input Offset Voltage, with
2014 Microchip Technology Inc.
-16
-12
-8
-4
0
4
8
12
Input Offset Voltage Drift; TC1 (nV/°C)
FIGURE 2-6:
with GMIN = 100.
16
Input Offset Voltage Drift,
DS20005318A-page 17
MCP6N16
55%
50%
45%
40%
35%
30%
25%
20%
15%
10%
5%
0%
GMIN = 1
28 Samples
TA = -40 to +125°C
NPBW = 3 mHz
In
nput O
Offset V
Voltage
e (µV)
Percent
P
tage off Occurrence
es
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.
VDD = 1.8V
VDD = 5.5V
5 5V
-1200
1200
-800
800
-400
400
0
400
800
Quadratic Input Offset Voltage Drift;
2
TC2 (pV/°C )
1200
In
nput O
Offset V
Voltage
e (µV)
Percent
P
tage off Occurrence
es
GMIN = 10
28 Samples
TA = -40 to +125°C
NPBW = 3 mHz
20%
VDD = 1.8V
VDD = 5.5V
10%
5%
0%
-160
160 -120
120 -80
80 -40
40
0
40
80 120
Quadratic Input Offset Voltage Drift;
2
TC2 (pV/°C )
160
35%
GMIN = 100
p
28 Samples
TA = -40 to +125°C
NPBW = 3 mHz
30%
25%
VDD = 5.5V
VDD = 1.8V
20%
15%
10%
5%
0%
-120
120 -100
100 -80
80 -60
60 -40
40 -20
20
0
20
Quadratic Input Offset Voltage Drift;
TC2 (pV/°C2)
FIGURE 2-9:
Quadratic Input Offset
Voltage Drift, with GMIN = 100.
DS20005318A-page 18
30
25
20
15
10
5
0
-5
-10
-15
20
-20
-25
-30
30
Representative Part
GMIN = 10
NPBW = 2 Hz
VDD = 5.5V
VDD = 1.8V
FIGURE 2-11:
Input Offset Voltage vs.
Output Voltage, with GMIN = 10.
In
nput O
Offset V
Voltage
e (µV)
Percent
P
tage off Occurrence
es
40%
VDD = 5.5V
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
FIGURE 2-8:
Quadratic Input Offset
Voltage Drift, with GMIN = 10.
45%
VDD = 1.8V
FIGURE 2-10:
Input Offset Voltage vs.
Output Voltage, with GMIN = 1.
30%
15%
Representative Part
GMIN = 1
NPBW = 2 Hz
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
FIGURE 2-7:
Quadratic Input Offset
Voltage Drift, with GMIN = 1.
25%
30
25
20
15
10
5
0
-5
-10
-15
20
-20
-25
-30
30
40
30
25
20
15
10
5
0
-5
-10
-15
20
-20
-25
-30
30
Representative Part
GMIN = 100
NPBW = 2 Hz
VDD = 1.8V
VDD = 5.5V
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
FIGURE 2-12:
Input Offset Voltage vs.
Output Voltage, with GMIN = 100.
2014 Microchip Technology Inc.
MCP6N16
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.
Input O
Offset Voltage (µV)
40
30
50
Representative Part
VCM = VSS
GMIN = 1
NPBW = 2 Hz
20
10
0
-10
-20
+125°C
+85°C
+25°C
-40°C
-30
-40
30
20
10
0
-10
-20
-50
50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Power Supply Voltage (V)
FIGURE 2-13:
Input Offset Voltage vs.
Power Supply Voltage, with VCM = 0V and
GMIN = 1.
Representative Part
VCM = VSS
GMIN = 10
NPBW = 2 Hz
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Power Supply Voltage (V)
FIGURE 2-16:
Input Offset Voltage vs.
Power Supply Voltage, with VCM = VDD and
GMIN = 1.
Input O
Offset V
Voltage
e (µV)
Input O
Offset V
Voltage
e (µV)
+125°C
+85°C
+25°C
-40°C
-30
-40
-50
30
25
20
15
10
5
0
-5
10
-10
-15
20
-20
-25
-30
30
Representative Part
VCM = VDD
GMIN = 1
NPBW = 2 Hz
40
Input O
Offset V
Voltage
e (µV)
50
+125°C
85 C
+85°C
+25°C
-40°C
30
25
20
15
10
5
0
-5
10
-10
-15
20
-20
-25
-30
30
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Power Supply Voltage (V)
30
25
20
15
10
5
0
-5
10
-10
-15
20
-20
-25
-30
30
Representative Part
VCM = VSS
GMIN = 100
NPBW = 2 Hz
+125°C
85 C
+85°C
+25°C
-40°C
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Power Supply Voltage (V)
FIGURE 2-15:
Input Offset Voltage vs.
Power Supply Voltage, with VCM = 0V and
GMIN = 100.
2014 Microchip Technology Inc.
+125°C
+85°C
+25°C
-40°C
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Power Supply Voltage (V)
FIGURE 2-17:
Input Offset Voltage vs.
Power Supply Voltage, with VCM = VDD and
GMIN = 10.
Input O
Offset V
Voltage
e (µV)
Input O
Offset V
Voltage
e (µV)
FIGURE 2-14:
Input Offset Voltage vs.
Power Supply Voltage, with VCM = 0V and
GMIN = 10.
Representative Part
VCM = VDD
GMIN = 10
NPBW = 2 Hz
30
25
20
15
10
5
0
-5
10
-10
-15
20
-20
-25
-30
30
Representative Part
VCM = VDD
GMIN = 100
NPBW = 2 Hz
+125°C
+85°C
+25°C
-40°C
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Power Supply Voltage (V)
FIGURE 2-18:
Input Offset Voltage vs.
Power Supply Voltage, with VCM = VDD and
GMIN = 100.
DS20005318A-page 19
MCP6N16
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.
50
50
30
Representative Part
VDD = 1.8V
GMIN = 1
NPBW = 2 Hz
40
Input O
Offset V
Voltage
e (µV)
Input O
Offset Voltage (µV)
40
20
10
0
-10
-20
+125°C
+85°C
+25°C
-40°C
-30
-40
-50
-0.5
30
Representative Part
VDD = 5.5V
GMIN = 1
NPBW = 2 Hz
20
10
0
-10
-20
+125°C
85 C
+85°C
+25°C
-40°C
-30
-40
2.5
-50
50
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Input Common Mode Voltage (V)
FIGURE 2-19:
Input Offset Voltage vs.
Common Mode Voltage, with VDD = 1.8V and
GMIN = 1.
FIGURE 2-22:
Input Offset Voltage vs.
Common Mode Voltage, with VDD = 5.5V and
GMIN = 1.
0.0
0.5
1.0
1.5
2.0
Input Common Mode Voltage (V)
50
30
50
Representative Part
VDD = 1.8V
8
GMIN = 10
NPBW = 2 Hz
40
Input O
Offset V
Voltage
e (µV)
Input O
Offset V
Voltage
e (µV)
40
20
10
0
-10
-20
+125°C
+85°C
+85
C
+25°C
-40°C
-30
-40
-50
50
-0.5
30
Representative Part
VDD = 5.5V
GMIN = 10
NPBW = 2 Hz
20
10
0
-10
-20
+125°C
+85
C
+85°C
+25°C
-40°C
-30
-40
2.5
-50
50
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Input Common Mode Voltage (V)
FIGURE 2-20:
Input Offset Voltage vs.
Common Mode Voltage, with VDD = 1.8V and
GMIN = 10.
FIGURE 2-23:
Input Offset Voltage vs.
Common Mode Voltage, with VDD = 5.5V and
GMIN = 10.
0.0
0.5
1.0
1.5
2.0
Input Common Mode Voltage (V)
50
30
50
Representative Part
VDD = 1.8V
8
GMIN = 100
NPBW = 2 Hz
40
Input O
Offset V
Voltage
e (µV)
Input O
Offset V
Voltage
e (µV)
40
20
10
0
-10
-20
+125°C
+85°C
+85
C
+25°C
-40°C
-30
-40
-50
50
-0.5
30
Representative Part
VDD = 5.5V
GMIN = 100
NPBW = 2 Hz
20
10
0
-10
-20
-30
-40
+125°C
85 C
+85°C
+25°C
-40°C
2.5
-50
50
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Input Common Mode Voltage (V)
FIGURE 2-21:
Input Offset Voltage vs.
Common Mode Voltage, with VDD = 1.8V and
GMIN = 100.
FIGURE 2-24:
Input Offset Voltage vs.
Common Mode Voltage, with VDD = 5.5V and
GMIN = 100.
0.0
0.5
1.0
1.5
2.0
Input Common Mode Voltage (V)
DS20005318A-page 20
2014 Microchip Technology Inc.
MCP6N16
Input Offset Voltage (µV)
FIGURE 2-25:
Input Offset Voltage vs.
Reference Voltage, with GMIN = 1.
30
Representative Part
25
GMIN = 10
TA = +25°C
20
NPBW = 2 Hz
15
10
5
0
-5
-10
VDD = 1.8V
VDD = 5.5V
-15
-20
-25
-30
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Reference Voltage (V)
Input Offset Voltage (µV)
FIGURE 2-26:
Input Offset Voltage vs.
Reference Voltage, with GMIN = 10.
30
Representative Part
25
GMIN = 100
TA = +25°C
20
NPBW = 2 Hz
15
10
5
0
-5
-10
VDD = 1.8V
VDD = 5.5V
-15
-20
-25
-30
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Reference Voltage (V)
FIGURE 2-27:
Input Offset Voltage vs.
Reference Voltage, with GMIN = 100.
2014 Microchip Technology Inc.
Percentage of Occurrences
60%
55%
50%
45%
40%
35%
30%
25%
20%
15%
10%
5%
0%
410 Samples
TA = +25°C
GMIN = 1
NPBW = 2.5 Hz
VDD = 5.5V
VDD = 1.8V
-12
-8
-4
0
4
1/CMRR (µV/V)
8
12
CMRR, with GMIN = 1.
FIGURE 2-28:
50%
Percentage of Occurrences
30
Representative Part
25
GMIN = 1
TA = +25°C
20
NPBW = 2 Hz
15
10
5
0
-5
-10
VDD = 1.8V
VDD = 5.5V
-15
-20
-25
-30
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Reference Voltage (V)
45%
40%
310 Samples
TA = +25°C
GMIN = 10
NPBW = 2.5 Hz
35%
VDD = 5.5V
30%
25%
20%
VDD = 1.8V
15%
10%
5%
0%
-5
-4
-3
FIGURE 2-29:
Percentage of Occurrences
Input Offset Voltage (µV)
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.
70%
65%
60%
55%
50%
45%
40%
35%
30%
25%
20%
15%
10%
5%
0%
-2
-1 0
1
2
1/CMRR (µV/V)
3
4
5
CMRR, with GMIN = 10.
410 Samples
TA = +25°C
GMIN = 100
NPBW = 2.5 Hz
VDD = 5.5V
VDD = 1.8V
-2.0 -1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0
1/CMRR (µV/V)
FIGURE 2-30:
CMRR, with GMIN = 100.
DS20005318A-page 21
MCP6N16
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.
50%
45%
40%
20%
410 Samples
TA = +25°C
GMIN = 1
NPBW = 2.5 Hz
18%
Pe
ercenta
age of O
Occurrrences
Percentage of Occurrences
55%
16%
14%
VDD = 5.5V
35%
12%
30%
10%
25%
20%
15%
VDD = 1.8V
10%
5%
0%
-8
-6
-4
FIGURE 2-31:
-2 0
2
4
1/CMRR2 (µV/V)
6
8
CMRR2, with GMIN = 1.
18%
16%
15%
VDD = 1.8V
-1
0
1
2
1/PSRR (µV/V)
3
4
5
PSRR, with GMIN = 1.
310 Samples
+25°C
TA = +25
C
VDD = 1.8V to 5.5V
GMIN = 10
NPBW = 2.5 Hz
8%
6%
4%
%
2%
0%
0%
-0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
1/PSRR (µV/V)
-1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8
1/CMRR2 (µV/V)
FIGURE 2-32:
CMRR2, with GMIN = 10.
90%
FIGURE 2-35:
PSRR, with GMIN = 10.
22%
410 Samples
TA = +25
+25°C
C
GMIN = 100
NPBW = 2.5 Hz
20%
Pe
ercenta
age of O
Occurrrences
Pe
ercenta
age of O
Occurrrences
-2
12%
20%
70%
-3
10%
VDD = 5.5V
25%
80%
-4
FIGURE 2-34:
14%
30%
5%
2%
20%
310 Samples
TA = +25
+25°C
C
GMIN = 10
NPBW = 2.5 Hz
35%
10%
4%
%
-5
Pe
ercenta
age of O
Occurrrences
Pe
ercenta
age of O
Occurrrences
40%
%
6%
10
55%
45%
8%
0%
-10
50%
410 Samples
+25°C
TA = +25
C
VDD = 1.8V to 5.5V
GMIN = 1
NPBW = 2.5 Hz
18%
16%
60%
410 Samples
+25°C
TA = +25
C
VDD = 1.8V to 5.5V
GMIN = 100
NPBW = 2.5 Hz
14%
50%
12%
VDD = 5.5V
40%
10%
30%
20%
VDD = 1.8V
1 8V
10%
8%
6%
4%
2%
0%
0%
-1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8
1/CMRR2 (µV/V)
FIGURE 2-33:
DS20005318A-page 22
CMRR2, with GMIN = 100.
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
1/PSRR (µV/V)
FIGURE 2-36:
PSRR, with GMIN = 100.
2014 Microchip Technology Inc.
MCP6N16
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.
50%
45%
40%
150
145
140
135
130
125
120
115
110
105
100
95
90
410 Samples
TA = +25°C
GMIN = 1
NPBW = 2.5 Hz
VDD = 5.5V
35%
30%
25%
20%
15%
VDD = 1.8V
10%
5%
0%
-10
-8
-6
-4
FIGURE 2-37:
GMIN = 1.
-2 0
2
1/AOL (µV/V)
4
6
8
10
DC Open-Loop Gain, with
45%
40%
%
35%
30%
VDD = 5.5V
25%
20%
15%
10%
5%
-50
VDD = 1.8V
0%
DC Open-Loop Gain, with
70%
410 Samples
TA = +25°C
+25 C
GMIN = 100
NPBW = 2.5 Hz
60%
50%
VDD = 5.5V
40%
30%
20%
VDD = 1.8V
1 8V
10%
0%
-1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8
1/AOL (µV/V)
FIGURE 2-39:
GMIN = 100.
0
25
50
75
Ambient Temperature (°C)
100
125
CMRR vs. Ambient
DC Open-Loop Gain, with
2014 Microchip Technology Inc.
GMIN = 10, VDD = 5.5V
VDD = 1.8V
-25
FIGURE 2-41:
Temperature.
150
145
140
135
130
125
120
115
110
105
100
95
90
GMIN = 1, VDD = 5.5V
VDD = 1.8V
0
25
50
75
Ambient Temperature (°C)
100
125
CMRR2 vs. Ambient
GMIN = 100
GMIN = 10
PSRR (dB)
Pe
ercenta
age of O
Occurrrences
90%
80%
GMIN = 1, VDD = 5.5V
VDD = 1.8V
GMIN = 100, VDD = 5.5V
VDD = 1.8V
-50
-1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8
1/AOL (µV/V)
FIGURE 2-38:
GMIN = 10.
-25
FIGURE 2-40:
Temperature.
150
145
140
135
130
125
120
115
110
105
100
95
90
310 Samples
TA = +25°C
+25 C
GMIN = 10
NPBW = 2.5 Hz
GMIN = 10, VDD = 5.5V
VDD = 1.8V
CMRR2
C
2 (dB)
Pe
ercenta
age of O
Occurrrences
55%
50%
GMIN = 100, VDD = 5.5V
VDD = 1.8V
8
CMRR
C
(dB)
Percentage of Occurrences
55%
GMIN = 1
VDD = 1.8V to 5.5V
-50
-25
FIGURE 2-42:
Temperature.
0
25
50
75
Ambient Temperature (°C)
100
125
PSRR vs. Ambient
DS20005318A-page 23
MCP6N16
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.
GMIN = 100, VDD = 5.5V
VDD = 1.8V
GMIN = 10, VDD = 5.5V
VDD = 1.8V
-50
-25
GMIN = 1, VDD = 5.5V
VDD = 1.8V
0
25
50
75
Ambient Temperature (°C)
100
Input Bias, Offsett Curre
ents (pA
A)
10
25
IB
IOS
FIGURE 2-44:
Input Bias and Offset
Currents vs. Common Mode Input Voltage, with
TA = +85°C.
125
100µ
1.E-4
10µ
1.E-5
1.E-6
1µ
1.E-7
100n
1.E-8
10n
1.E-9
1n
1.E-11
10p
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
FIGURE 2-47:
Input Bias Current
Magnitude vs. Input Voltage (below VSS).
0.10
Representative Part
TA = +125°C
125 C
VDD = 5.5V
Representative Parts
0.08
0.06
400
IB
200
-40°C
+25°C
+85°C
+125°C
1.E-10
100p
0
Ga
ain Errror (%)
Input Bias, Offsett Curre
ents (pA
A)
65
85
105
Ambient Temperature (°C)
FIGURE 2-46:
Input Bias and Offset
Currents vs. Ambient Temperature, with
VDD = 5.5V.
1,000
600
45
1m
1.E-3
Representative Part
TA = +85°C
85 C
VDD = 5.5V
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Common Mode Input Voltage (V)
800
IB
1
125
FIGURE 2-43:
DC Open-Loop Gain vs.
Ambient Temperature.
600
500
400
300
200
100
0
-100
-200
-300
-400
400
-500
-600
600
| IOS |
100
Input Bias Current Magnitude (A)
DC Open-Loop Gain; AOL (dB)
Input Bias, Offsett Curre
ents (pA
A)
1000
150
145
140
135
130
125
120
115
110
105
100
95
90
GMIN = 100;
VDD = 1.8V
VDD = 5.5V
0 04
0.04
0.02
0.00
-0.02
-200
-0.04
-400
IOS
-600
600
-0.06
0.06
GMIN = 1;
VDD = 1.8V
VDD = 5.5V
-0.08
-800
-0.10
0 10
-1,000
1 000
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Common Mode Input Voltage (V)
FIGURE 2-45:
Input Bias and Offset
Currents vs. Common Mode Input Voltage, with
TA = +125°C.
DS20005318A-page 24
-50
-25
FIGURE 2-48:
Temperature.
GMIN = 10;
VDD = 1.8V
VDD = 5.5V
0
25
50
75
Ambient Temperature (°C)
100
125
Gain Error vs. Ambient
2014 Microchip Technology Inc.
MCP6N16
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.
Percenttage off Occurrence
P
es
16%
14%
405 Samples
GMIN = 1
VDD = 1.8V
12%
VDD = 5.5V
10%
8%
6%
4%
2%
0.14
4
2
0.12
0.10
0.08
0.06
0.04
4
2
0.02
0.00
-0.02
4
-0.04
-0.06
-0.08
-0.10
-0.12
-0.14
4
0%
Gain Error (%)
FIGURE 2-49:
18%
Percenttage off Occurrence
P
es
16%
Gain Error, with GMIN = 1.
306 Samples
GMIN = 10
14%
12%
10%
8%
6%
VDD = 1.8V
4%
VDD = 5.5V
2%
0.14
4
0.12
0.10
0.08
0.06
0.04
4
0.02
0.00
-0.02
4
-0.04
-0.06
-0.08
-0.10
-0.12
-0.14
4
0%
Gain Error (%)
Gain Error, with GMIN = 10.
FIGURE 2-50:
18%
Percenttage off Occurrence
P
es
16%
386 Samples
GMIN = 100
14%
12%
10%
8%
6%
VDD = 1.8V
4%
VDD = 5.5V
2%
0.14
4
2
0.12
0.10
0.08
0.06
0.04
4
2
0.02
0.00
-0.02
4
-0.04
-0.06
-0.08
-0.10
-0.12
-0.14
4
0%
Gain Error (%)
FIGURE 2-51:
Gain Error, with GMIN = 100.
2014 Microchip Technology Inc.
DS20005318A-page 25
MCP6N16
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.
2.2
Other DC Voltages and Currents
100
1st Wafer Lot
Outp
put Volltage H
Headroo
om (mV
V)
Inpu
ut Volta
age Ran
nge He
eadroo
om
(V))
0.4
03
0.3
VIVH – VDD
0.2
0.1
0.0
-0.1
VIVL – VSS
-0.2
-0.3
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
80
VDD – VOH
70
60
50
VOL – VSS
40
30
20
10
-50
125
4.2
3.8
Supply Currrent (m
mA)
1st Wafer Lot
GMINVDMH = -G
GMINVDML
RTO
4.0
36
3.6
3.4
GMIN = 1,, 10,, 100
3.2
3.0
2.8
2.6
2.4
22
2.2
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
125
FIGURE 2-53:
Normalized Differential Input
Voltage Range vs. Ambient Temperature.
100
VOL – VSS
1
1
Output Current Magnitude (mA)
10
FIGURE 2-54:
Output Voltage Headroom
vs. Output Current Magnitude.
DS20005318A-page 26
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
02
0.2
0.1
0.0
00
100
125
+125°C
+85°C
+25°C
-40
40°C
C
FIGURE 2-56:
Supply Voltage.
Supp
ply Current (m
mA)
VDD = 5.5V
10
0.1
0
25
50
75
Ambient Temperature (°C)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Power Supply Voltage (V)
VDD = 1.8V
VDD – VOH
-25
FIGURE 2-55:
Output Voltage Headroom
vs. Ambient Temperature.
FIGURE 2-52:
Input Voltage Range
Headroom vs. Ambient Temperature.
Normalize
ed Diffferentia
al Inpu
ut
Vo
oltage R
Range;; GMINVDMH (V))
VDD = 5.5V
RL = 1 k
0
-0.4
04
Outp
put Volltage H
Headroo
om (mV
V)
90
Supply Current vs. Power
1.2
1.1
VDD = 5.5V
1.0
VDD = 1.8V
0.9
0.8
0.7
0.6
0.5
04
0.4
0.3
02
0.2
0.1
0.0
00
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Common Mode Input Voltage (V)
FIGURE 2-57:
Supply Current vs. Common
Mode Input Voltage.
2014 Microchip Technology Inc.
MCP6N16
Outpu
ut Shorrt-Circu
uit Currrent (m
mA)
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.
50
40
30
20
10
+125°C
+85°C
+85
C
+25°C
-40°C
0
-10
-20
-30
30
-40
-50
50
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Power Supply Voltage (V)
FIGURE 2-58:
Output Short-Circuit Current
vs. Power Supply Voltage.
Percenttage of Occurrences
50%
45%
40%
103 Samples
1 Wafer Lot
TA = +25°C
35%
30%
VPRL
25%
VPRH
20%
15%
10%
5%
1.40
1.38
1.36
1.34
1.32
1.30
1.28
1.26
1.24
1.22
1.20
0%
Power-On Reset Trip Voltages (V)
Powe
er-On R
Reset T
Trip Voltages (V)
FIGURE 2-59:
Voltages.
1.60
1.55
1 50
1.50
1.45
1.40
1.35
1.30
1.25
1.20
1 15
1.15
1.10
1.05
1.00
0.95
0.90
0 90
Power-On Reset Trip
1 Wafer Lot
VPRH
VPRL
-50
-25
0
25
50
75
Ambient Temperature (°C)
100
125
FIGURE 2-60:
Power-On Reset Trip
Voltages vs. Temperature.
2014 Microchip Technology Inc.
DS20005318A-page 27
MCP6N16
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.
Frequency Response
130
120
110
100
90
80
70
60
0
50
40
30
20
10
1.E+04
10k
500
No
ormaliz
zed Gaiin Band
dwidth
h
Prroductt; GBW
WP/GMINN (kHz)
CMRR
C
(dB)
400
350
300
250
GMIN = 100
GMIN = 10
GMIN = 1
VDD = 5.5V
Pha
ase Ma
argin (°°)
PSRR (dB)
75
70
65
PSRR vs. Frequency.
-120
60
-150
40
-180
-210
AOL;
GMIN = 100
GMIN = 10
GMIN = 1
240
-240
|AOL|;
GMIN = 100
GMIN = 10
GMIN = 1
10k
100k
1M
1.E+4
1.E+5
1.E+6
Frequency (Hz)
FIGURE 2-63:
Frequency.
DS20005318A-page 28
-270
-300
-330
10M
1.E+7
Open-Loop Gain vs.
-25
FIGURE 2-65:
Temperature.
1.E+4
10k
Open-Loop
p Gain Phase; AOL (°)
80
GMIN = 1
GMIN = 10
GMIN = 100
VDD = 1.8V
-50
1.E+06
1M
-90
Open-Loo
op Gain Magnitude;
|AOL| (dB)
125
FIGURE 2-64:
Normalized Gain-Bandwidth
Product vs. Ambient Temperature.
55
1.E+04
1.E+05
10k
100k
Frequency (Hz)
-60
-60
1k
1.E+3
0
25
50
75
100
Ambient Temperature (°C)
60
100
-40
VDD = 1.8V
80
120
-20
-25
85
FIGURE 2-62:
0
-50
1.E+06
1M
CMRR vs. Frequency.
120
110
100
90
80
70
60
50
40
30
GMIN = 100
20
GMIN = 10
10
GMIN = 1
0
1.E+03
1k
GMIN = 1
GMIN = 10
GMIN = 100
200
1.E+05
100k
Frequency (Hz)
FIGURE 2-61:
20
VDD = 5.5V
450
0
25
50
75
Ambient Temperature (°C)
100
125
Phase Margin vs. Ambient
GMIN = 1, 10, 100
Close
ed-Loop Output
Im
mpedance ()
2.3
1.E+3
1k
1.E+2
100
10
1.E+1
1k
1.E+3
GDM/GMIN = 1
GDM/GMIN = 10
GDM/GMIN = 100
10k
100k
1.E+4
1.E+5
Frequency (Hz)
1M
1.E+6
FIGURE 2-66:
Closed-Loop Output
Impedance vs. Frequency.
2014 Microchip Technology Inc.
MCP6N16
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.
10
140
9
130
120
GMIN = 1
GDM = 1
7
6
GMIN = 10
GDM = 10
= 20
= 50
5
GMIN = 100
GDM = 100
= 200
= 500
4
3
2
E
EMIRR
R (dB)
Gain
n Peaking (dB
B)
8
at VIP
110
100
90
80
GMIN = 1
GMIN = 10
GMIN = 100
70
at VREF
60
1
50
0.01
0
10
100
1,000
Normalized Capacitive Load; CL GMIN/GDM (pF)
FIGURE 2-67:
Gain Peaking vs.
Normalized Capacitive Load.
130
1
2
EMIRR vs. Input Voltage,
140
VIN = 100 mVPK, at VIP or VREF
VDD = 5
5.5V
5
130
120
110
110
E
EMIRR
R (dB)
120
100
90
GMIN = 1
GMIN = 10
GMIN = 100
80
80
60
60
100M
1G
1.E+08
1.E+09
Frequency (Hz)
FIGURE 2-68:
VIN = 100 mVPK.
GMIN = 1
GMIN = 10
GMIN = 100
50
0.01
10G
1.E+10
EMIRR vs. Frequency, with
at VREF
90
70
50
10M
1.E+07
f = 1800 MHz
VDD = 5.5V
100
70
at VIP
0.1
Input Voltage (VPK)
1
2
FIGURE 2-71:
EMIRR vs. Input Voltage,
with f = 1800 MHz.
140
130
0.1
Input Voltage (VPK)
FIGURE 2-70:
with f = 900 MHz.
140
E
EMIRR
R (dB)
f = 900 MHz
VDD = 5.5V
140
f = 400 MHz
VDD = 5.5V
130
120
f = 2400 MHz
VDD = 5.5V
at VREF
120
E
EMIRR
R (dB)
E
EMIRR
R (dB)
at VREF
110
100
90
80
70
GMIN = 1
GMIN = 10
GMIN = 100
at VIP
FIGURE 2-69:
with f = 400 MHz.
100
90
60
0.1
Input Voltage (VPK)
1
2
EMIRR vs. Input Voltage,
2014 Microchip Technology Inc.
att VIP
80
70
60
50
0.01
110
50
0.01
GMIN = 1
GMIN = 10
GMIN = 100
0.1
Input Voltage (VPK)
1
2
FIGURE 2-72:
EMIRR vs. Input Voltage,
with f = 2400 MHz.
DS20005318A-page 29
MCP6N16
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.
Noise
Input Noise Voltage Density
(V/¥Hz)
1.E+3
1µ
eni;
GMIN = 1
GMIN = 10
GMIN = 100
20m
10m
1.E+6
Eni(0 Hz to f);
GMIN = 1
GMIN = 10
GMIN = 100
1m
1.E+5
100µ
1.E+4
100n
1.E+2
10µ
10n
1.E+1
1.E+3
0.1 1.E+0
1 1.E+1
10 1.E+2
100 1.E+3
1k 1.E+4
10k 1.E+5
100k
1.E-1
Frequency (Hz)
FIGURE 2-73:
Input Noise Voltage Density
and Integrated Input Noise Voltage vs.
Frequency.
100
IM
MD Spe
ectrum
m, RTI ((µVPK)
20µ
1.E+4
10µ
Integrated
d Input Noise Voltage
(VP-P)
2.4
Residual
R
id l
100 Hz
Tone
IMD
Tone
at DC
GMIN = 1
10
GMIN = 10
1
GMIN = 100
0.1
01
1.E+0
1
1.E+1
10
1.E+2
1.E+3
100
1k
Frequency (Hz)
1.E+4
10k
1.E+5
100k
FIGURE 2-76:
Intermodulation Distortion
vs. Frequency with VDD Disturbance
(see Figure 1-8).
1µ
1E+3
GMIN = 1
f = 100 Hz
GMIN = 1
GMIN = 10
GMIN = 100
100n
1E+2
Input No
oise Voltage; eni(t)
(5 µV/div)
Inp
put Noise Volltage D
Density
y
(V/¥H
Hz)
VDD tone = 100 mVPK, f = 100 Hz
NPBW = 10 Hz
NPBW = 1 Hz
10n
1E+1
-0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Common Mode Input Voltage (V)
FIGURE 2-74:
Input Noise Voltage Density
vs. Input Common Mode Voltage.
Residual
100 Hz
Tone
0.1
1.E+0
1
60 Hz
Harmonics
GMIN = 1
GMIN = 10
1.E+2
1.E+3
100
1k
Frequency (Hz)
NPBW = 1 Hz
1.E+4
10k
1.E+5
100k
FIGURE 2-75:
Intermodulation Distortion
vs. Frequency with VCM Disturbance (see
Figure 1-8).
DS20005318A-page 30
80 100 120 140 160 180 200
Time (s)
NPBW = 10 Hz
GMIN = 100
1.E+1
10
60
GMIN = 10
10
1
40
FIGURE 2-77:
Input Noise Voltage vs.
Time, with 1 Hz and 10 Hz Filters and GMIN = 1.
VCM tone = 100 mVPK, f = 100 Hz
IMD
Tone
at DC
20
In
nput Noise Vo
Voltage;; eni(t)
(0.5 µV
V/div)
IMD Spe
ectrum, RTI (µVPK)
100
0
0
20
40
60
80 100 120 140 160 180 200
Time (s)
FIGURE 2-78:
Input Noise Voltage vs.
Time, with 1 Hz and 10 Hz Filters and GMIN = 10.
2014 Microchip Technology Inc.
MCP6N16
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.
Inp
put Noise Volltage; eni(t)
(0
0.2 µV/d
div)
GMIN = 100
NPBW = 10 Hz
NPBW = 1 Hz
0
20
40
60
80 100 120 140 160 180 200
Time (s)
FIGURE 2-79:
Input Noise Voltage vs.
Time, with 1 Hz and 10 Hz Filters and
GMIN = 100.
2014 Microchip Technology Inc.
DS20005318A-page 31
MCP6N16
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.
Time Response
0
20
40
60
50
VOS
0
5
-50
0
-100
1.0
1.5
2.0
Time (ms)
2.5
2.9
3
2.8
2
2.7
1
2.6
VOUT;
GMIN = 1
GMIN = 10
GMIN = 100
Outp
put Voltage (V)
Common M
Mode Input Voltage (V)
VCM
4
2.5
-1
2.4
0
1
2
3
4
5
6
Time (ms)
7
8
9
10
FIGURE 2-82:
The MCP6N16 Shows No
Phase Reversal vs. Common Mode Input
Overdrive, with VDD = 5.5V.
DS20005318A-page 32
7
8
9
10
2.0
1.8
GDMVDM
1.6
VOUT;
GMIN = 1
GMIN = 10
GMIN = 100
-1.0
1.4
12
1.2
1.0
-1 2
-1.2
08
0.8
-1.4
0.6
-1.6
16
0.4
04
-1.8
0.2
00
0.0
1
2
3
4 5 6
Time (ms)
7
8
9
10
FIGURE 2-84:
The MCP6N16 Shows No
Phase Reversal vs. Output Overdrive to VSS.
3.1
3.0
4
5
6
Time (ms)
2.2
0
5
3
0.8
8
-0
3.2
VDD = 5.5V
2
-0.6
3.0
6
0
-1
1
1
-2.0
20
FIGURE 2-81:
Input Offset Voltage vs.
Time at Power-Up.
7
0
-0.4
Norma
alized D
Differential
In
nput Vo
oltage;; GDMVDDM (V)
0.5
1
VOUT;
GMIN = 1
GMIN = 10
GMIN = 100
-0.2
-150
150
0.0
2
0.0
VDD
-5
5
3
0
0.2
Norma
N
alized D
Differen
ntial
In
nput Vo
oltage; GDMVDDM (V)
100
10
1
FIGURE 2-83:
The MCP6N16 Shows No
Phase Reversal vs. Differential Input Overdrive,
with VDD = 5.5V.
Input O
Offset V
Voltage
e (µV)
Power S
P
Supply
y Voltag
ge (V)
150
15
4
0
200
20
2
-3
3
GDM = 1000
GMIN = 1
GMIN = 10
GMIN = 100
5
-2
FIGURE 2-80:
Input Offset Voltage vs.
Time with Temperature Change.
25
6
VDM
3
-1
80 100 120 140 160 180
Time (s)
30
4
Outp
put Volltage (V
V)
VOS
7
VDD = 5.5V
Outp
put Volltage (V
V)
In
nput O
Offset V
Voltage
e (µV)
TSEN
GMIN = 1
GMIN = 10
GMIN = 100
5
2.0
5.5
1.8
5.3
1.6
5.1
1.4
4.9
1.2
4.7
1.0
4.5
VOUT;
GMIN = 1
GMIN = 10
GMIN = 100
0.8
06
0.6
4.3
41
4.1
0.4
3.9
02
0.2
Outp
put Voltage (V
V)
125
100
75
50
25
0
-25
-50
-75
-100
125
-125
-150
-175
175
NPBW = 1.3 Hz
Norrmalize
ed Diffe
erentia
al Mode
e
In
nput Vo
oltage; GDMVDDM (V)
100
90
80
70
60
50
40
30
20
10
0
-10
-20
20
Sensorr Tempe
S
erature
e (°C)
2.5
37
3.7
GDMVDM
0.0
3.5
-0.2
02
33
3.3
0
1
2
3
4 5 6
Time (ms)
7
8
9
10
FIGURE 2-85:
The MCP6N16 Shows No
Phase Reversal vs. Output Overdrive to VDD.
2014 Microchip Technology Inc.
MCP6N16
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.
Differential Input Overdrive
Recovery Time (µs)
Ou
utput Voltage
V
e (10 mV/div)
1000
GMIN = 1
GMIN = 10
GMIN = 100
VDD = 5.5V
GMIN = 1
GMIN = 10
GMIN = 100
100
10
1
0
5
10
15
20 25 30
Time (µs)
40
45
Small Signal Step
FIGURE 2-89:
Differential Input Overdrive
Recovery Time vs. Normalized Gain.
5.5
5.0
5.0
4.5
4.5
Outp
put Volltage (V
V)
5.5
4.0
3.5
GMIN = 1
GMIN = 10
GMIN = 100
3.0
2.5
10
Normalized Gain; GDM/GMIN
20
2.0
1.5
4.0
3.5
GMIN = 1
GMIN = 10
GMIN = 100
3.0
2.5
20
2.0
1.5
10
1.0
10
1.0
0.5
0.5
0.0
00
0.0
00
0
5
10
FIGURE 2-87:
Response.
15
20 25 30
Time (µs)
35
40
45
50
Large Signal Step
0
50 100 150 200 250 300 350 400 450 500 550 600
Time (µs)
FIGURE 2-90:
vs. Time.
1000
5.5
5.0
VDD = 5.5V
4.5
Outp
put Voltage (V)
1
50
4.0
GMIN = 1
GMIN = 10
GMIN = 100
3.5
3.0
2.5
20
2.0
1.5
1.0
Output Overdrive Recovery
VDD = 5.5V
Recovery from VSS and VDD
Output Overdrive Recovery
Time (µs)
Outp
put Volltage (V
V)
FIGURE 2-86:
Response.
35
GMIN = 1
GMIN = 10
GMIN = 100
0.5
100
0.0
0
50
100
150
Time (µs)
200
250
FIGURE 2-88:
Differential Input Overdrive
Recovery vs. Time.
2014 Microchip Technology Inc.
1
10
Normalized Gain; GDM/GMIN
FIGURE 2-91:
Output Overdrive Recovery
Time vs. Normalized Gain.
DS20005318A-page 33
MCP6N16
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.
Powe
er Supp
ply, Ou
utput Vo
oltage (V)
2.0
VL = 0V
1.8
1.6
1.4
GMIN = 1
GMIN = 10
GMIN = 100
1.2
1.0
0.8
06
0.6
On
VDD
0.4
VOUT
02
0.2
0.0
Off
-0.2
02
0
20
40
60
Off
80 100 120 140 160 180 200
Time (ms)
FIGURE 2-92:
Power Supply On and Off
and Output Voltage vs. Time.
DS20005318A-page 34
2014 Microchip Technology Inc.
MCP6N16
Note: Unless otherwise indicated, TA = +25°C, VDD = 1.8V to 5.5V, VSS = GND, VCM = VDD/2, VDM = 0V,
VREF = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF, GDM = GMIN and EN = VDD; see Figures 1-7 and 1-8.
2.6
Enable Response
50
VDD = 1.8V
VL = 0V
1.8
45
Enable Turn-On Time (µs)
En
nable, Output
O
t Voltag
ges (V))
2.0
1.6
INA
turns on
1.4
INA
turns off
1.2
1.0
VOUT
EN
0.8
GMIN = 100
GMIN = 10
GMIN = 1
0.6
0.4
02
0.2
GMIN = 1
GMIN = 10
GMIN = 100
35
30
25
20
VDD = 5.5V
15
GMIN = 1
GMIN = 10
GMIN = 100
10
5
0.0
0
-0.2
02
0
20
40
60
6.0
5.5
5.0
4.5
40
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
05
-50
80 100 120 140 160 180 200
Time (µs)
FIGURE 2-93:
Enable and Output Voltages
vs. Time, with VDD = 1.8V.
-25
0
25
50
75
Ambient Temperature (°C)
100
125
FIGURE 2-96:
Enable Turn-On Time vs.
Ambient Temperature.
2.5
EN = 0V
2.0
INA
turns on
Powerr Supp
ply Current
In Shutdo
S
own (µA
A)
En
nable, Output
O
t Voltag
ges (V))
VDD = 5.5V
VL = 0V
INA
turns off
EN
VOUT
GMIN = 1
GMIN = 10
GMIN = 100
1.5
10
1.0
IDD
0.5
-40°C
+25 C
+25°C
+85°C
+125°C
0.0
-0.5
ISS
-1.0
-1.5
-2.0
-2.5
25
0
20
40
60
80 100 120 140 160 180 200
Time (µs)
FIGURE 2-94:
Enable and Output Voltages
vs. Time, with VDD = 5.5V.
0.7
05
0.5
VIL_TRIP/VDD
0.3
FIGURE 2-97:
Power Supply Current in
Shutdown vs. Power Supply Voltage.
1.E-7
100n
VDD = 1.8V
VIH_TRIP/VDD
06
0.6
0.4
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Power Supply Voltage (V)
Ou
utput Leakage
L
e Curre
ent (A))
Normallized Enable Input
N
Trip a
and Hys
steresiis Volta
ages (V
V/V)
VDD = 1.8V
40
1.E-8
10n
1.E-9
1n
EN = 0V
VDD = 5.5V
+125°C
+85°C
1.E-10
100p
VHYST/VDD
0.2
1.E-11
10p
p
0.1
VDD = 5.5V
00
0.0
-50
-25
0
25
50
75
Ambient Temperature (°C)
100
125
FIGURE 2-95:
Normalized Enable Input
Trip and Hysteresis Voltages vs. Ambient
Temperature.
2014 Microchip Technology Inc.
+25°C
1.E-12
1
E 12
1p
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Output Voltage (V)
FIGURE 2-98:
Output Leakage Current in
Shutdown vs. Output Voltage.
DS20005318A-page 35
MCP6N16
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
MCP6N16
MSOP
DFN
1
1
3.1
Symbol
Description
EN
Enable Input
2
2
VIM
Inverting Input
3
3
VIP
Non-inverting Input
4
4
VSS
Negative Power Supply
5
5
VREF
Reference Input
6
6
VFG
Feedback Input
7
7
VOUT
Output
8
8
VDD
Positive Power Supply
—
9
EP
Exposed Thermal Pad (EP); must be connected to VSS.
Digital Enable Input (EN)
3.5
Analog Feedback Input (VFG)
This input (EN) is a CMOS, Schmitt-triggered input.
When it is low, it puts the part in a low-power state.
When high, the part operates normally. The EN pin
must not be left floating.
The analog feedback input (VFG) is the inverting input
of the second input stage. The external feedback
components (RF and RG) are connected to this pin. It is
a high-impedance CMOS input with low bias current.
3.2
3.6
Analog Signal Inputs (VIP, VIM)
The non-inverting and inverting inputs (VIP and VIM) are
high-impedance CMOS inputs with low bias currents.
3.3
Power Supply Pins (VSS, VDD)
The positive power supply (VDD) is 1.8V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD.
Analog Output (VOUT)
The analog output (VOUT) is a low impedance voltage
output. It represents the differential input voltage
(VDM = VIP – VIM), with gain GDM and is shifted by
VREF. The external feedback resistor (RF) is connected
to this pin.
3.7
Exposed Thermal Pad (EP)
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply; VDD will
need bypass capacitors.
There is an internal connection between the exposed
thermal pad (EP) and the VSS pin; they must be
connected to the same potential on the printed circuit
board (PCB).
3.4
This pad can be connected to a PCB ground (VSS)
plane region to provide a larger heat sink. This
improves the package thermal resistance (θJA).
Analog Reference Input (VREF)
The analog reference input (VREF) is the non-inverting
input of the second input stage; it shifts VOUT to its
desired range. The external gain resistor (RG) is
connected to this pin. It is a high-impedance CMOS
input with low bias current.
DS20005318A-page 36
2014 Microchip Technology Inc.
MCP6N16
4.0
APPLICATIONS
EQUATION 4-2:
VIP = V CM + VDM 2
The MCP6N16 instrumentation amplifier (INA) is
manufactured using Microchip’s state of the art CMOS
process. Its low cost, low power and high speed make
it ideal for battery-powered applications.
4.1
Basic Performance
4.1.1
STANDARD CIRCUIT
Figure 4-1 shows the standard circuit configuration for
these INAs. When the inputs and output are in their
specified ranges, the output voltage is approximately:
V IM = V CM – V DM 2
V CM = VIP + VIM 2
VDM = V IP – V IM
The negative feedback loop includes GM2, RM4, RF and
RG. These blocks set the DC open-loop gain (AOL) and
the nominal differential gain (GDM):
EQUATION 4-3:
A OL = G M2 RM4
EQUATION 4-1:
G DM = 1 + RF R G
VOUT VREF + GDMVDM
AOL is very high, so I4 is very small and I1 + I2 ≈ 0. This
makes the differential inputs to GM1 and GM2 equal in
magnitude and opposite in polarity. Ideally, this gives:
Where:
GDM = 1 + RF / RG
EQUATION 4-4:
VDD
U1
V FG – VREF = VDM
MCP6N16
VIP
V OUT = V DM GDM + V REF
VOUT
VIM
VFG
RF
For an ideal part, changing VCM, VSS or VDD produces
no change in VOUT. VREF shifts VOUT as needed.
The different GMIN options change GM1, GM2 and the
internal compensation capacitor. This results in the
performance trade-offs shown in Table 1.
RG
VREF
FIGURE 4-1:
Standard Circuit.
4.1.3
For normal operation, keep:
• VIP, VIM, VREF and VFG between VIVL and VIVH
• VIP – VIM (i.e., VDM) between VDML and VDMH
• VOUT between VOL and VOH
4.1.2
DC ERRORS
Section 1.5
“Explanation
of
DC
Error
Specifications” defines some of the DC error
specifications. These errors are internal to the INA, and
can be summarized as follows:
EQUATION 4-5:
ANALOG ARCHITECTURE
Figure 4-2 shows the block diagram for these INAs,
without details on chopper-stabilized operation.
V OUT = V REF + G DM 1 + g E V DM + V ED
+ G DM 1 + g E V E + VE
Where:
VDD VSS EN
VIP
VIM
I4
VIP GM1
VIM
RM4
I1
GM2 V
FG
Σ
I2
MCP6N16
FIGURE 4-2:
VOUT
VOUT
RF
VED INLDM V DMH – V DML
VE INLCM V IVH – VIVL
RG
VREF
RR
VREF
MCP6N16 Block Diagram.
The input signal is applied to GM1. Equation 4-2 shows
the relationships between the input voltages (VIP and
VIM) and the common mode and differential voltages
(VCM and VDM).
2014 Microchip Technology Inc.
V DD – VSS V CM
VREF
VE = V OS + --------------------------------- + ----------------- + -------------------PSRR
CMRR CMRR2
V OUT
+ ----------------- + T A TC 1
A OL
Where:
PSRR, CMRR, CMRR2 and AOL are in
units of V/V
∆TA is in units of °C
TC1 is in units of V/°C
VDM = 0
DS20005318A-page 37
MCP6N16
The nonlinearity specifications (INLCM and INLDM)
describe errors that are nonlinear functions of VCM and
VDM, respectively. They give the maximum excursion
from linear response over the entire common mode
and differential ranges.
The input bias current and offset current specifications
(IB and IOS), together with a circuit’s external input
resistances, give an additional DC error. Figure 4-3
shows the resistors that set the DC bias point.
IBP
VIP
RIP
VDD
U1
MCP6N16
VOUT
VIM
IBM
IBF
RIM
RF
IBR
RG
VREF
FIGURE 4-3:
V REF = – I BR R R = – I B2 + I OS2 2 R R
due to high AOL
V FG VREF
V OUT I B2 RF – G DM R R + IOS2 R F + GDM R R 2
Where:
IB2 meets the IB specification
IOS2 meets the IOS specification
IB2 ≠ IB, in general
IOS2 ≠ IOS, in general
The change in VREF (∆VREF) can affect the input range,
for large RR or RF. The best design results when
GDMRR and RF are equal (i.e., RR = RF||RG) and small:
EQUATION 4-9:
VFG
RR
EQUATION 4-8:
V OUT 2I B2 RTOL + IOS2 RF
Where:
GDMRR = RF
RTOL = tolerance of RR, RF and RG
DC Bias Resistors.
The resistors at the main input (RIP and RIM) and its
input bias currents (IBP and IBM) give the following
changes in the INA’s bias voltages:
EQUATION 4-6:
VIP = – I BP R IP = – I B + I OS 2 R IP
VIM = – IBM R IM = – I B – IOS 2 R IM
VCM = V IP + V IM 2
= – I B RIP + R IM 2 – I OS R IP – R IM 4
VDM = V IP – V IM
= – IB RIP – RIM – I OS R IP + R IM 2
VOUT = G DM V DM + V CM CMRR
Where:
CMRR is in units of V/V
The change in VCM (∆VCM) can affect the input range,
for large RIP or RIM. The best design results when RIP
and RIM are equal and small:
4.1.4
AC PERFORMANCE
The bandwidth of these amplifiers depends on GDM
and GMIN:
EQUATION 4-10:
f BW fGBWP G DM
0.50 MHz G MIN G DM ,
0.35 MHz G MIN G DM ,
Where:
Where:
RIP = RIM
GMIN = 100
fBW = -3 dB bandwidth
fGBWP = Gain-Bandwidth product
The bandwidth at the maximum output swing is called
the Full Power Bandwidth (fFPBW). It is limited by the
Slew Rate (SR) for many amplifiers, but is close to fBW
for these parts:
EQUATION 4-11:
EQUATION 4-7:
V OUT G DM V DM
G DM 2I B RTOL – I OS R IP
GMIN = 1, 10
Where:
f FPBW SR V O
fBW , for these parts
VO = Maximum output voltage swing
VOH – VOL
RTOL = tolerance of RIP and RIM
The resistors at the feedback input (RR, RF and RG)
and its input bias currents (IBR and IBF) give the
following changes in the INA’s bias voltages:
DS20005318A-page 38
2014 Microchip Technology Inc.
MCP6N16
4.1.5
4.2
NOISE PERFORMANCE
As shown in Figure 2-73, the noise density is white at
low frequencies; the 1/f noise is negligible for almost all
applications. As a result, the time domain data in
Figures 2-77, 2-78 and 2-79 is well behaved.
Overview of Zero-Drift Operation
Figure 4-4 shows a simplified diagram of the MCP6N16
zero-drift INAs. This diagram will be used to explain
how low voltage errors are reduced in this architecture
(much better VOS, TC1 (∆VOS/∆TA), CMRR, CMRR2,
PSRR, AOL and 1/f noise).
VIP
VIM
GM1
Chopper
Input
Switches
GA1
Chopper
Output
Switches
Low-Pass
Filter
RM4
Chopper
Input
Switches
POR
VOUT
Digital Control
GA2
Oscillator
VREF
GM2
VFG
FIGURE 4-4:
4.2.1
Simplified Zero-Drift INA Functional Diagram.
BUILDING BLOCKS
The Main Amplifiers (GM1 and GM2) are designed for
high gain and bandwidth, with a differential topology.
The main input pairs (+ and - pins at the top left) are for
the higher frequency portion of the input signal. The
auxiliary input pair (+ and - pins at the bottom left of
GM1) is for the low frequency portion of the input signal
and corrects the INA’s input offset voltage. Both inputs
are added together internally.
The Auxiliary Amplifiers (GA1 and GA2), the Chopper
Input Switches and the Chopper Output Switches
provide a high DC gain to the input signal. DC errors
are modulated to higher frequencies and white noise to
low frequencies.
4.2.2
CHOPPING ACTION
Figure 4-5 shows the amplifier connections for the first
phase of the Chopping Clock and Figure 4-6 shows
them for the second phase. The slow voltage errors
alternate in polarity, making the average error small.
VIP
VIM
GA1
Low-Pass
Filter
The Low-Pass Filter reduces high-frequency content,
including harmonics of the Chopping Clock.
The Output Buffer (RM4) converts current to voltage
and drives external loads at the VOUT pin.
The Oscillator runs at fCLK = 200 kHz. Its output is
divided by 8, to produce the Chopping Clock rate of
fCHOP = 25 kHz.
The internal POR part starts the part in a known good
state, protecting against power supply brown-outs. The
Digital Control block outputs clocks and POR events.
2014 Microchip Technology Inc.
GA2
VREF
VFG
FIGURE 4-5:
First Chopping Clock Phase;
Simplified Diagram.
DS20005318A-page 39
MCP6N16
4.3
VIP
Other Functional Blocks
4.3.1
VIM
Each input stage uses one PMOS differential pair at the
input. The output of each differential pair is processed
using current mode circuitry. The inputs show no
crossover distortion vs. common mode voltage.
GA1
Low-Pass
Filter
GA2
With this topology, the inputs (VIP and VIM) operate
normally down to VSS – 0.15V and up to VDD + 0.15V
at room temperature (see Figure 2-52). The input offset
voltage (VOS) is measured at VCM = VSS – 0.15V and
VDD + 0.15V (at +25°C) to ensure proper operation.
4.3.1.1
Phase Reversal
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-82 shows an input voltage
exceeding both supplies with no phase inversion.
VREF
VFG
FIGURE 4-6:
Second Chopping Clock
Phase; Simplified Diagram.
4.2.3
RAIL-TO-RAIL INPUTS
INTERMODULATION DISTORTION
(IMD)
These INAs will show intermodulation distortion (IMD)
products when an AC signal is present.
The signal and clock can be decomposed into sine
wave tones (Fourier series components). These tones
interact with the zero-drift circuitry’s nonlinear response
to produce IMD tones at sum and difference
frequencies. Each of the square wave clock’s
harmonics has a series of IMD tones centered on it.
See Figures 2-75 and 2-76.
The input devices also do not exhibit phase inversion
when the differential input voltage exceeds its limits;
see Figure 2-83.
4.3.1.2
Input Voltage Limits
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the voltages at
the input pins (see Section 1.1 “Absolute Maximum
Ratings †”). This requirement is independent of the
current limits discussed later on.
The ESD protection on the inputs can be depicted as
shown in Figure 4-7. This structure was chosen to
protect the input transistors against many (but not all)
overvoltage conditions, and to minimize input bias
current (IB).
VDD
Bond
Pad
VIP Bond
Pad
Input
Stage
of
INA Input
Bond V
IM
Pad
VSS Bond
Pad
FIGURE 4-7:
Structures.
Simplified Analog Input ESD
The input ESD diodes clamp the inputs when they try
to go more than one diode drop below VSS. They also
clamp any voltages that go too far above VDD; their
breakdown voltage is high enough to allow normal
operation, but not low enough to protect against slow
over-voltage (beyond VDD) events. Very fast ESD
events (that meet the specification) are limited so that
damage does not occur.
DS20005318A-page 40
2014 Microchip Technology Inc.
MCP6N16
Input Current Limits
VC
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
into the input pins (see Section 1.1 “Absolute
Maximum Ratings †”). This requirement is
independent of the voltage limits previously discussed.
VIP
VIVH
VDD
M
=
Figure 4-9 shows one approach to protecting these
inputs. The resistors R1 and R2 limit the possible
current in or out of the input pins (and into D1 and D2).
The diode currents will dump onto VDD.
0
M
=
/2
D
VD
V
D
M
L
4.3.1.3
=
V
D
FIGURE 4-8:
Protecting the Analog Inputs
Against High Voltages.
H
V2
The input voltage range specifications (VIVL and VIVH)
change with the supply voltages (VSS and VDD,
respectively). The differential input range specifications
(VDML and VDMH) change with minimum gain (GMIN).
Temperature also affects these specifications.
D
M
D2
For normal operation, VIP and VIM must be kept within
the region surrounded by the thick blue lines. The
horizontal and vertical blue lines show the limits on the
individual inputs. The blue lines with a slope of +1 show
the limits on VDM; the larger GMIN is, the closer they are
to the VDM = 0 line.
V
MCP6N16
V1
Figure 4-10 shows possible input voltage values
(VSS = 0V). Lines with a slope of +1 have constant VDM
(e.g., the VDM = 0 line). Lines with a slope of -1 have
constant VCM (e.g., the VCM = VDD/2 line).
=
U1
D1
Input Voltage Ranges
DM
VDD
4.3.1.4
V
In some applications, it may be necessary to prevent
excessive voltages from reaching the INA inputs.
Figure 4-8 shows one approach to protecting these
inputs. D1 and D2 may be small signal silicon diodes,
Schottky diodes for lower clamping voltages or
diode-connected FETs for low leakage.
R1
D2
V2
R2
VSS – min(V1, V2)
2 mA
max(V1, V2) – VDD
min(R1, R2) >
2 mA
min(R1, R2) >
DM
VIVL
FIGURE 4-10:
VIVH
VDD
MCP6N16
V1
0
0
VIVL
U1
D1
VIM
V
VDD
Input Voltage Ranges.
To take full advantage of VDML and VDMH, set VREF
(see Figures 1-7 and 1-8) so that the output (VOUT) is
centered between the supplies (VSS and VDD). Also set
the gain (GDM) to keep VOUT within its range.
FIGURE 4-9:
Protecting the Analog Inputs
Against High Currents.
It is also possible to connect the diodes to the left of the
resistor R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIP and VIM)
should be very small.
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the common
mode voltage (VCM) is below ground (VSS); see
Figure 2-47.
2014 Microchip Technology Inc.
DS20005318A-page 41
MCP6N16
4.3.2
ENABLE
4.4.3
This input (EN) is a CMOS, Schmitt-triggered input.
When it is low, it puts the part in a low-power state and
the output is put into a high-impedance state. When
high, the part operates normally.
If the EN pin is left floating, the amplifier will not operate
properly.
4.3.3
RAIL-TO-RAIL OUTPUT
The Minimum Output Voltage (VOL) and Maximum
Output Voltage (VOH) specifications describe the
widest output swing that can be achieved under the
specified load conditions.
The output can also be limited when VIP or VIM exceeds
VIVL or VIVH or when VDM exceeds VDML or VDMH.
4.4
4.4.1
INPUT OFFSET VOLTAGE OVER
TEMPERATURE
Table 1 gives both the linear and quadratic temperature
coefficients (TC1 and TC2) of input offset voltage. The
input offset voltage can be estimated as follows:
EQUATION 4-12:
V OS T A = VOS + TC 1 T + TC2 T
2
Where:
TA = -40°C to +125°C
∆T = TA – 25°C
VOS(TA) = Input offset voltage at TA
VOS = Input offset voltage at +25°C
TC1 = Linear temperature coefficient
TC2 = Quadratic temperature coefficient
These specifications show these INA’s intrinsic
performance. The plots of input offset voltage versus
temperature on the second page (Figures 1 to 3) show
the typical behavior for a few parts from the first wafer
lot.
In most designs, other effects will dominate the circuit
temperature performance; see Section 4.4.13 “PCB
Design for DC Precision” for more details.
4.4.2
NOISE EFFECT ON OFFSET
VOLTAGE
The input noise (eni) makes measured offset values
(VOS) vary in a random manner. Lower noise requires
a lower noise power bandwidth (NPBW; see AN1228,
mentioned in 5.3 “Application Notes”), which
increases measurement time. In the offset-related
specifications (AOL, CMRR, CMRR2 and PSRR) and
plots, the various values of NPBW were chosen to
trade off time versus accuracy of results.
DS20005318A-page 42
Figures 2-28 to 2-39 are histograms of the reciprocals
(in units of µV/V) of CMRR, PSRR and AOL,
respectively. They represent the change in input offset
voltage (VOS) with a change in common mode input
voltage (VCM), power supply voltage (VDD) and output
voltage (VOUT).
The 1/AOL histogram is centered near 0 µV/V because
the measurements are dominated by the INA’s input
noise. The negative values shown represent noise and
tester limitations, not unstable behavior. Production
tests make multiple VOS measurements, which
validates an INA's stability; an unstable part would
show greater VOS variability, or the output would stick
at one of the supply rails.
4.4.4
Applications Tips
DC GAIN PLOTS
OFFSET AT POWER-UP
When these parts power up, the input offset (VOS)
starts at its uncorrected value (usually less than
±10 mV). Circuits with high DC gain can cause the
output to reach one of the two rails. In this case, the
time to a valid output is delayed by an output overdrive
time (like tODR), in addition to a start-up time (like tSTR).
It can be simple to avoid this extra start-up time.
Reducing the gain is one method. Adding a capacitor
across the feedback resistor (RF) is another method.
4.4.5
SOURCE RESISTANCES
The input bias currents have two significant
components: switching glitches that dominate at room
temperature and below, and input ESD diode leakage
currents that dominate at +85°C and above.
Make the resistances seen by the inputs small and
equal. This minimizes the output offset caused by the
input bias currents.
The inputs should see a resistance on the order of 10Ω
to 1 kΩ at high frequencies (i.e., above 1 MHz). This
helps minimize the impact of switching glitches, which
are very fast, on overall performance. In some cases, it
may be necessary to add resistors in series with the
inputs to achieve this improvement in performance.
Small input resistances at the inputs may be needed for
high gains. Without them, parasitic capacitances might
cause positive feedback and instability.
4.4.6
SOURCE CAPACITANCE
The capacitances seen by the inputs should be small.
Large input capacitances and source resistances,
together with high gain, can lead to positive feedback
and instability.
2014 Microchip Technology Inc.
MCP6N16
MINIMUM STABLE GAIN
There are three options for different Minimum Stable
Gains (1, 10 and 100 V/V; see Table 1). The differential
gain (GDM) needs to be greater than or equal to GMIN
in order to maintain stability.
Picking a part with higher GMIN has the advantages of
lower input noise voltage density (eni), lower input
offset voltage (VOS) and increased gain-bandwidth
product (GBWP). The differential input voltage range
(VDML and VDMH) is lower for higher GMIN, but supports
a reasonable output voltage range.
4.4.8
2k
Recom
mmend
ded RISO
O ()
4.4.7
1k
1,000
100
10p
10p
100p
1n
10n
10
100
1,000
10,000
Normalized Load Capacitance; CL GMIN/GDM (F)
CAPACITIVE LOADS
Driving large capacitive loads can cause stability
problems for voltage amplifiers. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth
reduces. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. Lower gains (GDM) exhibit greater sensitivity
to capacitive loads.
When driving large capacitive loads with these
instrumentation amps (e.g., > 80 pF), a small series
resistor at the output (RISO in Figure 4-11) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
VDD
V1
After selecting RISO for the circuit, double check the
resulting frequency response peaking and step
response overshoot on the bench. Modify RISO’s value
until the response is reasonable.
4.4.9
GAIN RESISTORS
Figure 4-13 shows a simple gain circuit with the INA’s
input capacitances at the feedback inputs (VREF and
VFG). These capacitances interact with RG and RF to
modify the gain at high frequencies. The equivalent
capacitance acting in parallel to RG is CG = CDM + CCM
plus any board capacitance in parallel to RG. CG will
cause an increase in GDM at high frequencies, which
reduces the phase margin of the feedback loop (i.e.,
reduce the feedback loop’s stability).
U1
MCP6N16 RISO
VOUT
V2
FIGURE 4-12:
Recommended RISO Values
for Capacitive Loads.
VFG
RF CL
VREF
FIGURE 4-11:
Output Resistor, RISO
Stabilizes Large Capacitive Loads.
Figure 4-12 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL GMIN/GDM), where
GDM is the circuit’s differential gain (1 + RF/RG) and
GMIN is the minimum stable gain.
U1
MCP6N16
V1
VOUT
V2
RG
2014 Microchip Technology Inc.
VDD
RF
VFG
CCM
CDM
CCM
RG
VREF
FIGURE 4-13:
Simple Gain Circuit with
Parasitic Capacitances.
DS20005318A-page 43
MCP6N16
In this data sheet, RF + RG = 10 kΩ for most gains (0Ω
for GDM = 1); see Table 1-6. This choice gives good
phase margin. In general, RF (Figure 4-13) needs to
meet the following limits to maintain stability:
EQUATION 4-13:
For GDM = 1:
RF = 0
For GDM > 1:
2
G DM
R F -----------------------------2 f GBWP C G
Where:
GDM GMIN
fGBWP = Gain-Bandwidth Product
CG = CDM + CCM + (PCB stray capacitance)
EMI REJECTION RATIO (EMIRR)
Electromagnetic interference (EMI) can be coupled to
an INA through electromagnetic induction or radiation,
or by conduction. INAs are most sensitive to EMI at
their input pins.
EMIRR describes an INA’s EMI robustness. Internal
passive filters in these parts improve the EMIRR, when
good PCB layout techniques are used. EMIRR is
defined to be:
EQUATION 4-14:
VRF
EMIRR dB = 20 log -------------
V OS
Where:
VRF = Peak Input Voltage of EMI (VPK)
∆VOS = Input Offset Voltage Shift (V)
4.4.11
REDUCING UNDESIRED NOISE
AND SIGNALS
Reduce undesired noise and signals with:
• Low bandwidth signal filters:
- Minimizes random analog noise
- Reduces interfering signals
• Good PCB layout techniques:
- Minimizes crosstalk
- Minimizes parasitic capacitances and
inductances that interact with fast switching
edges
• Good power supply design:
- Isolation from other parts
- Filtering of interference on supply line(s)
DS20005318A-page 44
SUPPLY BYPASS
With these INAs, the Power Supply pin (VDD for single
supply) should have a local bypass capacitor (i.e.,
0.01 µF to 0.1 µF) within 2 mm for good high-frequency
performance. Surface mount, multilayer ceramic
capacitors, or their equivalent, should be used.
These INAs require a bulk capacitor (i.e., 1.0 µF or
larger) within 100 mm to provide large, slow currents.
This bulk capacitor can be shared with other nearby
analog parts as long as crosstalk through the supplies
does not prove to be a problem.
4.4.13
0.25
4.4.10
4.4.12
PCB DESIGN FOR DC PRECISION
In order to achieve DC precision on the order of ±1 µV,
many physical errors need to be minimized. The design
of the printed circuit board (PCB), the wiring, and the
thermal environment have a strong impact on the
precision achieved. A poor PCB design can easily be
more than 100 times worse than the MCP6N16 op
amps’ minimum and maximum specifications.
4.4.13.1
PCB Layout
Any time two dissimilar metals are joined together, a
temperature dependent voltage appears across the
junction (the Seebeck or thermojunction effect). This
effect is used in thermocouples to measure
temperature. The following are examples of
thermojunctions on a PCB:
• Components (resistors, INAs, …) soldered to a
copper pad
• Wires mechanically attached to the PCB
• Jumpers
• Solder joints
• PCB vias
Typical thermojunctions have temperature to voltage
conversion coefficients of 1 to 100 µV/°C (sometimes
higher).
Microchip’s AN1258 (“Op Amp Precision Design: PCB
Layout Techniques” – DS01258) contains in-depth
information on PCB layout techniques that minimize
thermojunction effects. It also discusses other effects,
such as crosstalk, impedances, mechanical stresses
and humidity.
4.4.13.2
Crosstalk
DC crosstalk causes offsets that appear as a larger
input offset voltage. Common causes include:
• Common mode noise (remote sensors)
• Ground loops (current return paths)
• Power supply coupling
Interference from the mains (usually 50 Hz or 60 Hz),
and other AC sources, can also affect the DC
performance. Nonlinear distortion can convert these
signals to multiple tones, including a DC shift in voltage.
2014 Microchip Technology Inc.
MCP6N16
When the signal is sampled by an ADC, these AC
signals can also be aliased to DC, causing an apparent
shift in offset.
4.5.2
To reduce interference:
Figure 4-15 uses the MCP6N16 INA as a difference
amplifier for signals with a very large common mode
component. The input resistor dividers (R1 and R2)
ensure that the INA’s inputs are within their normal
range of operation. The capacitors (C1 and C2) set the
same voltage division ratio for high-frequency signals
(e.g., a voltage step). C2 includes the INA’s CCM. R1
and R2’s tolerances affect CMRR.
-
Keep traces and wires as short as possible
Use shielding
Use ground plane (at least a star ground)
Place the input signal source near to the DUT
Use good PCB layout techniques
Use a separate power supply filter (bypass
capacitors) for these zero-drift INAs
4.4.13.3
V1
Miscellaneous Effects
Keep the resistances seen by the input pins as small
and as near to equal as possible, to minimize bias
current-related offsets.
DIFFERENCE AMPLIFIER FOR
VERY LARGE COMMON MODE
SIGNALS
R1
R2
C1
C2
VDD U
1
MCP6N16
Make the (trace) capacitances seen by the input pins
small and equal. This is helpful in minimizing switching
glitch-induced offset voltages.
Bending a coax cable with a radius that is too small
causes a small voltage drop to appear on the center
conductor (the triboelectric effect). Make sure the
bending radius is large enough to keep the conductors
and insulation in full contact.
VOUT
C1
C2
R1
R2
VFG
RF
RG
V2
VREF
Mechanical stresses can make some capacitor types
(such as some ceramics) output small voltages. Use
more appropriate capacitor types in the signal path and
minimize mechanical stresses and vibration.
FIGURE 4-15:
Difference Amplifier with
Very Large Common Mode Component.
Humidity can cause electrochemical potential voltages
to appear in a circuit. Proper PCB cleaning helps, as
does the use of encapsulants.
Figure 4-16 shows an RTD temperature sensor circuit,
which measures over the -55°C to +155°C range. The
sensor chosen changes from 78Ω to 159Ω over this
range. The 2.49 kΩ and 4.99 kΩ resistors set the
current through the RTD and 68.1Ω resistor. The INA
provides a high-differential gain. The 10 µF capacitor
filters common mode interference on the bridge.
4.5
4.5.1
Typical Applications
HIGH INPUT IMPEDANCE
DIFFERENCE AMPLIFIER
Figure 4-14 shows the MCP6N16 used as a difference
amplifier. The inputs are high-impedance and give
good CMRR performance.
VDD
VIP
4.5.3
RTD TEMPERATURE SENSOR
VDD
2.49 kΩ
10 µF
EN
U1
4.99 kΩ
4.99 kΩ
RF
68.1Ω
RTD
100Ω
RG
4.99 kΩ
MCP6N16
MCP6N16-100
VOUT
VIM
VFG
VREF
FIGURE 4-14:
VOUT
FIGURE 4-16:
20 kΩ
100Ω
100Ω
RTD Temperature Sensor.
Difference Amplifier.
2014 Microchip Technology Inc.
DS20005318A-page 45
MCP6N16
4.5.4
WHEATSTONE BRIDGE
Figure 4-17 shows the MCP6N16 INA used to
condition the signal from a Wheatstone bridge (e.g.,
strain gage). The overall INA gain is set at 1001 V/V.
The best GMIN option to pick, for this gain, is 100 V/V
(MCP6N16-100).
VDD
RW1
RW2
U1
10 µF
RW2
MCP6N16-100
RW1
VFG
RN
100Ω
VOUT
RF
100 kΩ
RG
100Ω
VREF
FIGURE 4-17:
Amplifier.
4.5.5
Wheatstone Bridge
HIGH SIDE CURRENT DETECTOR
Figure 4-18 shows the MCP6N16 INA used to detect
and amplify the high side current in a power supply
design. U1’s low offset voltage makes it possible to
reduce RSH, which saves power and minimizes
temperature effects. U1’s supply current is included in
the measurement. The INA’s gain is set at 101 V/V, so
VOUT changes 1.01V for every 1A change in IDD.
VPS
IDD
IPS
U1
MCP6N16-100
RSH
10 mΩ
VFG
IL
VL
RF
10.0 kΩ
VOUT
RG
100Ω
VREF
VPS = +1.8V to 5.5V
IPS = IL + IDD
IPS = (VPS – VL)/(10 mΩ)
= (VOUT – VREF)/((10 mΩ) (101 V/V))
FIGURE 4-18:
DS20005318A-page 46
High Side Current Detector.
2014 Microchip Technology Inc.
MCP6N16
5.0
DESIGN AIDS
Microchip provides the basic design aids needed for
the MCP6N16 instrumentation amplifiers.
5.1
Microchip Advanced Part Selector
(MAPS)
MAPS is a software tool that helps efficiently identify
Microchip devices that fit a particular design
requirement. Available at no cost from the Microchip
website at www.microchip.com/maps, the MAPS is an
overall selection tool for Microchip’s product portfolio
that includes Analog, Memory, MCUs and DSCs. Using
this tool, a customer can define a filter to sort features
for a parametric search of devices and export
side-by-side technical comparison reports. Helpful links
are also provided for Data sheets, Purchase and
Sampling of Microchip parts.
5.2
Analog Demonstration Board
Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help customers achieve faster time
to market. For a complete listing of these boards
and their corresponding user’s guides and technical
information, visit the Microchip web site at
www.microchip.com/analog tools.
5.3
Application Notes
The following Microchip Application Notes are
available on the Microchip web site at
www.microchip.com/appnotes and are recommended
as supplemental reference resources.
• AN884: “Driving Capacitive Loads With Op
Amps”, DS00884
• AN990: “Analog Sensor Conditioning Circuits –
An Overview”, DS00990
• AN1177: “Op Amp Precision Design: DC
Errors”, DS01177
• AN1228: “Op Amp Precision Design: Random
Noise”, DS01228
• AN1258: “Op Amp Precision Design: PCB Layout
Techniques”, DS01258
Some of these application notes, and others, are listed
in the design guide:
• “Signal Chain Design Guide”, DS21825
2014 Microchip Technology Inc.
DS20005318A-page 47
MCP6N16
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
8-Lead DFN (3x3 mm)
Example
Product Number
Code
MCP6N16-001E/MF
DADV
MCP6N16T-001E/MF
DADV
MCP6N16-010E/MF
DADW
MCP6N16T-010E/MF
DADW
MCP6N16-100E/MF
DADX
MCP6N16T-100E/MF
DADX
8-Lead MSOP (3x3 mm)
DADV
1423
256
Example
N16010
423256
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS20005318A-page 48
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2014 Microchip Technology Inc.
MCP6N16
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2014 Microchip Technology Inc.
DS20005318A-page 49
MCP6N16
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005318A-page 50
2014 Microchip Technology Inc.
MCP6N16
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2014 Microchip Technology Inc.
DS20005318A-page 51
MCP6N16
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005318A-page 52
2014 Microchip Technology Inc.
MCP6N16
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2014 Microchip Technology Inc.
DS20005318A-page 53
MCP6N16
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005318A-page 54
2014 Microchip Technology Inc.
MCP6N16
APPENDIX A:
REVISION HISTORY
Revision A (July 2014)
• Original Release of this Document.
2014 Microchip Technology Inc.
DS20005318A-page 55
MCP6N16
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
[X](1)
-XXX
Tape and Reel Gain
Option
Option
X
/XX
Temperature
Range
Package
Device:
MCP6N16
Single Instrumentation Amplifier
MCP6N16T Single Instrumentation Amplifier
(Tape and Reel)
Gain Option:
001 = Minimum gain of 1 V/V
010 = Minimum gain of 10 V/V
100 = Minimum gain of 100 V/V
Temperature Range: E
Package:
= -40°C to +125°C
MF = Plastic Dual Flat, no lead Package - 3×3x0.9 mm
Body, 8-lead (DFN)
MS = Plastic Micro Small Outline Package, 8-lead (MSOP)
DS20005318A-page 56
Examples:
a)
MCP6N16T-001E/MF:
b)
MCP6N16-010E/MS:
Note 1:
Tape and Reel,
Minimum gain = 1,
Extended temperature,
8LD 3×3 DFN
Minimum gain = 10,
Extended temperature,
8LD MSOP
Tape and Reel identifier only appears in the
catalog part number description. This identifier is used for ordering purposes and is not
printed on the device package. Check with
your Microchip Sales Office for package
availability with the Tape and Reel option.
2014 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2014, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
ISBN: 978-1-63276-377-8
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2014 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS20005318A-page 57
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DS20005318A-page 58
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03/25/14
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