MCP9902/3/4
Multi-Channel Low-Temperature Remote Diode Sensor
Features
Description
• Up to Three External Temperature Monitors
- ±1°C maximum accuracy
MCP9902: -40°C to +105°C
MCP9903/4: -40°C to +125°C
- ±2°C maximum accuracy
(+65°C < TDIODE < +125°C)
- 0.125°C resolution
• Internal Temperature Monitor
- ±1°C accuracy
- (-40°C to +65°C)
- 0.125°C resolution
• Supports up to 2.2 nF diode filter capacitor
• Up to 400 kHz clock rate
- Maskable with register control
• Programmable SMBus address
• Operating voltage: 3.0 to 3.6 (V)
• ESD protection: 2 kV HBM
• Temperature Range: -40°C to +125°C
• Available in a small 8-Lead 2x2 mm WDFN and
10-lead 3x3 mm VDFN packages
The MCP9902/3/4 is a high-accuracy, low-cost,
System Management Bus (SMBus) temperature
sensor. The MCP9902/3/4 monitors up to four
temperature channels. Advanced features such as
Resistance
Error
Correction
(REC),
Beta
Compensation and automatic diode-type detection
combine to provide a robust solution for complex
environmental monitoring applications.
Resistance Error Correction automatically eliminates
the temperature error caused by series resistance
allowing greater flexibility in routing thermal diodes.
Beta Compensation eliminates temperature errors
caused by low, variable beta transistors common in
today's fine geometry processors. The automatic beta
detection feature monitors the external diode/transistor
and determines the optimum sensor settings for
accurate temperature measurements regardless of
processor technology. This frees the user from
providing unique sensor configurations for each
temperature monitoring application. These advanced
features plus ±1°C measurement accuracy for both
external and internal diode temperatures provide a
low-cost, highly flexible and accurate solution for
critical temperature monitoring applications.
Typical Applications
•
•
•
•
•
General Purpose Temperature Sensing
Industrial Freezers and Refrigerators
Food Processing
Base Stations
Remote Radio Unit
Package Types
MCP9902
2 x 2 WDFN*
VDD 1
DP1 2
DN1 3
THERM/ADDR 4
MCP9903
3 x 3 VDFN*
8 SMCLK
EP
9
VDD 1
7 SMDATA
DP1 2
6 ALERT/THERM2
5 GND
DN1 3
DP2 4
MCP9904
3 x 3 VDFN*
VDD 1
DP1 2
DN1 3
DP2/DN3 4
DN2/DP3 5
DN2 5
10 SMCLK
EP
11
9
SMDATA
8
ALERT/THERM2
7
THERM/ADDR
6
GND
10 SMCLK
EP
11
9
SMDATA
8
ALERT/THERM2
7
THERM/ADDR
6
GND
* Includes Exposed Thermal Pad (EP); see Table 3-1.
2015-2016 Microchip Technology Inc.
DS20005382C-page 1
VDD
MCP990X
Conversion Rate Register
Switching
Current
Internal
Temp Diode
THERM/ADDR
THERM Limit Register
THERM Hysteresis Register
Internal
Temperature Register
Interupt Masking
Configuration Register
SMBus Address Decode
Status Registers
GND
Note 1: Second remote channel for MCP9903 and MCP9904.
2: Third remote channel for MCP9904.
SMBus Interface
DN2(1)/DP3(2)
External Temperature
Register(s)
High Limit Registers
Digital Mux
'6 ADC
Digital Mux
DN1
DP2(1)/DN3(2)
ALERT
SMCLK
Analog
Mux
Limit Comparator
DP1
Low Limit Registers
SMDATA
MCP9902/3/4
DS20005382C-page 2
MCP9902/3/4 Functional Block Diagram
2015-2016 Microchip Technology Inc.
MCP9902/3/4
1.0
ELECTRICAL CHARACTERISTICS
1.1
Electrical Specifications
Absolute Maximum Ratings(†)
Ambient Temperature under Bias...................................................................................................... -40°C to +125°C
Storage Temperature ....................................................................................................................... -65°C to +150°C
Voltage on VDD with respect to VSS ................................................................................................... -0.3V to +4.0V
Voltage on all other pins with respect to VSS ........................................................................... -0.3V to (VDD + 0.3V)
Total Power Dissipation( 1) ............................................................................................................................. 500 mW
Maximum Current out of VSS pin ..................................................................................................................... 20 mA
Maximum Current into VDD pin ........................................................................................................................ 20 mA
Clamp Current, IK (VPIN < 0 or VPIN > VDD)20 mA
ESD Rating, All pins HBM................................................................................................................................. 2000V
Input Current, any pin Except VDD 10 mA
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} +
(VOL x IOL). Rating up to +85°C.
1.2
DC Characteristics
Electrical Characteristics: Unless otherwise specified, 3.0 ≤ VDD ≤ 3.6V at -40°C ≤ TA ≤ +125°C
Characteristic
Sym.
Min.
Typ.
Max.
Units
Conditions
Supply Voltage
VDD
3.0
3.3
3.6
V
—
Supply Current
IDD
—
200
450
µA
0.0625 conversion/second, dynamic
averaging disabled
—
225
600
µA
1 conversion/second, dynamic
averaging enabled
—
450
850
µA
4 conversions/second, dynamic
averaging enabled
—
1120
1500
µA
> 16 conversions/second, dynamic
averaging enabled
Power Supply
One-Shot Supply
Current
IDD_OS
—
170
230
µA
Device in One-Shot state, no active
SMBus communications, ALERT and
THERM pins not asserted.
Standby Supply Current
IDD_SBY
—
170
230
µA
Device in Standby state, no SMBus
communications, ALERT and THERM
pins not asserted.
Power-on Reset
Voltage
POR_V
—
0.6
0.9
V
Pin states defined
Power-On Reset
Release Voltage
PORR
—
1.45
—
V
Rising VDD
Power-Up Timer
tPWRT
—
10
—
ms
VDD Rise Rate
VDD_RISE
0.05
—
—
V/ms
Supply Voltage
VDD
3.0
3.3
3.6
V
2015-2016 Microchip Technology Inc.
—
0 to 3V in 60 ms
—
DS20005382C-page 3
MCP9902/3/4
1.2
DC Characteristics (Continued)
Electrical Characteristics: Unless otherwise specified, 3.0 ≤ VDD ≤ 3.6V at -40°C ≤ TA ≤ +125°C
Characteristic
Sym.
Min.
Typ.
Max.
Units
Conditions
-1
±0.25
+1
°C
-40°C < TDIODE < +105°C,
-40°C < TA < +65°C
-2
±0.25
+2
°C
-40°C < TDIODE < +125°C
-40°C < TA < +125°C
-1
±0.25
+1
°C
-40°C < TDIODE < +125°C,
-40°C < TA < +65°C
-2
±0.25
+2
°C
+40°C < TDIODE < +125°C
-40°C < TA < +125°C
—
0.125
—
°C
—
±0.25
+1
°C
-40°C < TA < +65°C
External Temperature Monitor
Temperature Accuracy
(MCP9902)
—
Temperature Accuracy
(MCP9903, MCP9904)
—
Temperature
Resolution
—
Internal Temperature Monitor
Temperature Accuracy
—
-1
-2
±0.5
+2
°C
-40°C < TA < +125°C
Temperature
Resolution
—
—
0.125
—
°C
—
Timing and Capacitive Filter
Time to First
Communications
tINT_T
—
15
20
ms
Time after power up before ready to
begin communications and
measurement
Conversion Time All
Channels
(MCP9903, MCP9904)
tCONV
—
190
—
ms
Default settings
Conversion Time All
Channels
(MCP9902)
tCONV
—
150
—
ms
Default settings
Time to First
Conversion from
Standby
tCONV1
—
220
—
ms
Default settings
Capacitive Filter
CFILTER
—
2.2
2.7
nF
Connected across external diode
Output Low Voltage
VOL
0.4
—
—
V
ISINK = 8 mA
Leakage Current
ILEAK
—
—
±5
µA
ALERT and THERM pins
Device powered or
unpowered
TA < +85°C
pull-up voltage < 3.6V
ALERT and THERM Pins
1.3
Thermal Specifications
Electrical Characteristics: Unless otherwise specified, 3.0 VDD 3.6V at -40C TA +125C
Parameters
Sym.
Min.
Typ.
Max.
Units
Specified Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+125
°C
JA
—
141.3
—
°C/W
Test Conditions
Temperature Ranges
Thermal Package Resistances (Note 1)
Thermal Resistance, 8L-WDFN, 2x2
DS20005382C-page 4
2015-2016 Microchip Technology Inc.
MCP9902/3/4
1.3
Thermal Specifications
Electrical Characteristics: Unless otherwise specified, 3.0 VDD 3.6V at -40C TA +125C
Parameters
Sym.
Min.
Typ.
Max.
Units
Thermal Resistance, 10L-VDFN, 3x3
JA
—
78
—
°C/W
Test Conditions
Note 1: JEDEC 2s2p, board size 76.2 x 114.3 x 1.6 mm, 1 via, airflow = 0 m/s.
VDD
VPOR
VPORR
VSS
NPOR
POR REARM
VSS
TVLOW(2)
Note 1:
2:
3:
FIGURE 1-1:
TPOR(3)
When NPOR is low, the device is held in Reset.
TPOR 1 s typical.
TVLOW 2.7 s typical.
POR and POR Rearm With Slow Rising VDD.
2015-2016 Microchip Technology Inc.
DS20005382C-page 5
MCP9902/3/4
1.4
SMBUS Module Specifications
Operating Conditions (unless otherwise indicated): 3.0V ≤ VDD ≤ 3.6V at -40°C ≤ TA ≤ +85°C
Characteristic
Sym.
Min.
Typ.
Max.
Units
Conditions
—
VDD
V
—
0.8
V
—
±5
µA
Powered or unpowered
TA < +85°C
SMBus Interface
Input High Voltage
VIH
2.1
Input Low Voltage
VIL
-0.3
Leakage Current
ILEAK
—
—
—
0.1 VDD
—
mV
—
Input Capacitance
CIN
—
5
—
pF
—
Output Low Sink Current
IOL
8.2
—
15
mA
SMDATA = 0.2V
Hysteresis
SMBus Timing
fSMB
10
—
400
kHz
—
Spike Suppression
tSP
—
—
50
ns
—
Bus Free Time Stop to
Start
tBUF
1.3
—
—
µs
—
tHD:STA
0.6
—
—
µs
—
Setup Time: Start
tSU:STA
0.6
—
—
µs
—
Setup Time: Stop
tSU:STO
0.6
—
—
µs
—
Data Hold Time
tHD:DAT
0
—
—
µs
—
Data Hold Time
tHD:DAT
0.3
—
—
µs
When transmitting to the master
Data Setup Time
tSU:DAT
100
—
—
ns
When receiving from the master
Clock Low Period
tLOW
1.3
—
—
µs
—
Clock High Period
tHIGH
0.6
—
—
µs
—
Clock/Data Fall Time
tFALL
—
—
300
ns
—
Clock Frequency
Hold Time: Start
Clock/Data Rise Time
tRISE
—
—
300
ns
Min = 20+0.1 CLOAD ns
CLOAD
—
—
400
pF
Min = 20+0.1 CLOAD ns
Timeout
tTIME-
25
—
35
ms
Per bus line
Clock Frequency
fSMB
10
—
400
kHz
Disabled by default
Capacitive Load
OUT
T HIGH
T LOW
T HD:STA
T SU:STO
T FALL
SMCLK
T RISE
T HD:STA
T HD:DAT
T SU:DAT
T SU:STA
SMDATA
TBUF
P
S
FIGURE 1-2:
DS20005382C-page 6
S - Start Condition
S
P - Stop Condition
P
SMBus Timing Diagram.
2015-2016 Microchip Technology Inc.
MCP9902/3/4
2.0
TYPICAL OPERATING CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Note: Unless otherwise indicated 3.0 VDD 3.6V at -40C TA +125C.
4
Dynamic
Averaging
Disabled
Enabled
1
10
2
1
0
-1
-2
-3
-4
100
Conversion Rate (Hz)
Temperature (°C)
FIGURE 2-1:
Supply Current vs.
Conversion Rate (TA = +25°C, VDD = 3.3V).
250
VDD = 3.3V
TD = 25°C
30 Units
3
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
110
120
130
0.1
Temeprature Error (°C)
FIGURE 2-4:
Temperature Error vs.
Ambient Temperature (VDD = 3.3V, TD = +25°C,
16 Units, 2N3904).
Temeprature Error (°C)
Average of 5
devices
200
150
100
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
110
120
130
50
2.5
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
0
-40C -20C
0C
45C
65C
85C 105C 125C
IDD vs. Temperature.
Temperature (°C)
FIGURE 2-5:
Temperature Error vs.
Remote Temperature. (VDD = 3.3V, TD = +25°C,
16 Units, 2N3904).
0.25
0.2
0.15
0.1
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
Temperature Error (°C)
Temperature Error (°C)
FIGURE 2-2:
25C
0
1000
2000
3000
4000
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
120
REC
Disabled
100
Enabled
80
60
40
20
0
Filter Capacitance (pF)
50
100
150
Series Resistance (Ω)
FIGURE 2-3:
Temperature Error vs. Filter
Capacitor (VDD = 3.3V, TA = TD = +25°C, 2N3904).
FIGURE 2-6:
Temperature Error vs.
Series Resistance (TA = +25°C, VDD = 3.3V).
2015-2016 Microchip Technology Inc.
Temperaure Error (°C)
Supply Current (µA)
1300
1200
1100
1000
900
800
700
600
500
400
300
200
100
0
0.01
0
200
250
DS20005382C-page 7
MCP9902/3/4
3.0
PIN DESCRIPTIONS
The MCP9902/3/4 has two variants that include
features unique to each device. Refer to the table to
determine applicability of the pin descriptions.
The description of the pins is listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
MCP9902 MCP9903 MCP9904
WDFN
VDFN
VDFN
1
1
Pin
Type
1
VDD
P
Analog
Diode 1/2 Connection
Analog
Diode 1/2 Connection
4
DP2(1)
(2)
Analog
Diode 1/2 Connection
Analog
2
2
2
DP1
3
3
3
DN1
—
4
(/DN3)
Description
Power
—
5
5
DN2(1)(/DP3)(2)
5
6
6
GND
P
4
7
7
THERM/ADDR
OD
Non-Maskable THERM
6
8
8
ALERT/THERM2
OD
Maskable ALERT/THERM2
7
9
9
SMDATA
OD
SMBus Clock
8
10
10
SMCLK
OD
SMBus Data
11
EP
—
Exposed Thermal pad
9
11
Note 1:
2:
3:
3.1
Pin
Name
Diode 1/2 Connection
Ground
MCP9903 only.
MCP9904 only.
See Section 3.10 “Exposed Thermal Pad (EP)” for grounding recommendations.
Power Supply (VDD)
3.6
Ground (GND)
This pin is used to supply power to the device.
This pin is used for system ground for the device.
3.2
3.7
Diode 1 Pair (DN1/DP1)
Remote Diode 1 anode (DP1) and cathode (DN1) pins
for the MCP9902/3/4.
3.3
Diode 2 Pair (DN2/DP2)
Remote Diode 2 anode (DP2) and cathode (DN2) pins
for the MCP9903.
3.4
Anti-Parallel Diode Pair (DN3/DP2
and DN2/DP3) (MCP9904 only)
• DP2/DN3: DP2 anode and DN3 cathode
• DN2/DP3: DN2 cathode and DP3 anode
3.5
THERM LIMIT ALERT
(THERM/ADDR)
This pin asserts low when the hardware-set THERM
limit threshold is exceeded by one of the temperature
sensors. The assertion of this signal can’t be controlled
or masked by register setting. If enabled, the SMBus
slave address is set by the pull-up resistor on this pin.
DS20005382C-page 8
Maskable ALERT
(ALERT/THERM2)
This pin asserts when a diode temperature exceeds
the ALERT threshold. This pin may be masked by
register settings.
3.8
SMBus Data (SMDATA)
This is the open drain, bidirectional data pin for SMBus
communication.
3.9
SMBus Clock (SMCLK)
This is the SMBus input clock pin for SMBus
communication.
3.10
Exposed Thermal Pad (EP)
Not internally connected, but recommend grounding for
mechanical support.
2015-2016 Microchip Technology Inc.
MCP9902/3/4
4.0
FUNCTIONAL DESCRIPTION
Thermal management is performed in cooperation
with a host device. This consists of the host reading
the temperature data of both the external and internal
temperature diodes of the MCP9902/3/4 and using
that data to control the speed of one or more fans.
The MCP9902/3/4 has two levels of monitoring. The
first provides a maskable ALERT signal to the host
when the measured temperatures exceed user programmable limits. This allows the MCP9902/3/4 to be
used as an independent thermal watchdog to warn the
host of temperature hot spots without direct control by
the host. The second level of monitoring provides a
non-maskable interrupt on the THERM output if the
measured temperatures meet or exceed a second programmable limit.
4.2
The MCP9902/3/4 may be configured for different conversion rates based on the system requirements. The
default conversion rate is 4 conversions per second.
Other available conversion rates are shown in Table 4-1.
TABLE 4-1:
HEX
3
2
1
0
Conversions/
Second
0h
0
0
0
0
1/16
1h
0
0
0
1
1/8
2h
0
0
1
0
1/4
3h
0
0
1
1
1/2
VDD = 3.3V
3.3V – 5V
DP1 V
DD
Thermal
Junction
Host
DN1
SMCLK
MCP990X
Interface
Optional
Anti-parallel
diode
DP2/
DN3
THERM/ADDR
DN2/
DP3
Power
Control
GND
FIGURE 4-1:
Diagram.
4.1
MCP9902/3/4 System
Power States
The MCP9902/3/4 has two modes of operation:
• Active (Run) - In this mode of operation, the ADC
is converting on all temperature channels at the
programmed conversion rate. The temperature
data is updated at the end of every conversion
and the limits are checked. In Active mode, writing
to the one-shot register will do nothing.
• Standby (Stop) - In this mode of operation, the
majority of circuitry is powered down to reduce
supply current. The temperature data is not
updated and the limits are not checked. In this
mode of operation, the SMBus is fully active and
the part will return requested data. Writing to the
one-shot register will enable the device to update
all temperature channels. Once all the channels
are updated, the device will return to the Standby
mode.
2015-2016 Microchip Technology Inc.
0
1
0
0
1
0
1
0
1
2
6h
0
1
1
0
4 (default)
7h
0
1
1
1
8
8h
1
0
0
0
16
9h
1
0
0
1
32
Ah
1
0
1
0
64
All others
1
SMBus
ALERT
MCP9903/4 only
4h
5h
Bh - Fh
SMDATA
CONVERSION RATE
CONV
Figure 4-1 shows a system level block diagram of the
MCP9902/3/4.
CPU/GPU
Conversion Rates
4.3
Dynamic Averaging
Dynamic averaging allows the MCP9902/3/4 to
measure the external diode channel for an extended
time based on the selected conversion rate. This
functionality can be disabled for increased power
savings at the lower conversion rates (see
Register 5-6). When dynamic averaging is enabled,
the device will automatically adjust the sampling and
measurement time for the external diode channels.
This allows the device to average 2x or 16x longer
than the normal 11 bit operation (nominally 21 ms per
channel) while still maintaining the selected
conversion rate. The benefits of dynamic averaging
are improved noise rejection due to the longer
integration time as well as less random variation of the
temperature measurement.
When enabled, the dynamic averaging applies when a
one-shot command is issued. The device will perform
the desired averaging during the one-shot operation
according to the selected conversion rate.
When enabled, the dynamic averaging will affect the
typical supply current based on the chosen conversion
rate as shown in the power supply characteristics in
Table 1.2 "DC Characteristics".
DS20005382C-page 9
MCP9902/3/4
4.4
THERM Output
4.6
The THERM output is asserted independently of the
ALERT output and cannot be masked. Whenever any
of the measured temperatures exceed the user
programmed Therm Limit values for the programmed
number of consecutive measurements, the THERM
output is asserted. Once it has been asserted, it will
remain asserted until all measured temperatures drop
below the Therm Limit minus the Therm Hysteresis
(also programmable).
When the THERM output is asserted, the THERM
status bits will likewise be set. Reading these bits will
not clear them until the THERM output is deasserted.
Once the THERM output is deasserted, the THERM
status bits will be automatically cleared.
4.5
THERM Pin Address Decoding
The Address decode is performed by pulling known
currents from VDD through the external resistor
causing the pin voltage to drop based on the
respective current/resistor relationship. This pin
voltage is compared against a threshold that
determines the value of the pull-up resistor.
The MCP9902/3/4-A SMBus slave address is determined by the pull-up resistor on the THERM/ADDR pin
as shown in Table 4-2.
I2C/SMBUS ADDRESS
DECODE
TABLE 4-2:
Pull Up Resistor on
THERM pin (±5%)
SMBus Address
4.7 kΩ
1111_100 (r/w)b
6.8 kΩ
1011_100 (r/w)b
10 kΩ
1001_100 (r/w)b
15 kΩ
1101_100 (r/w)b
22 kΩ
0011_100 (r/w)b
33 kΩ
0111_100 (r/w)b
I2C/SMBus
The MCP9902-1
1001_100(r/w).
address is hard coded to
The MCP9902-2 I2C/SMBus address is hard coded to
1001_101(r/w).
The MCP9903-1 I2C/SMBus address is hard coded to
1001_100(r/w).
The MCP9903-2 I2C/SMBus address is hard coded to
1001_101(r/w).
The MCP9904-1 I2C/SMBus address is hard coded to
1001_100(r/w).
The MCP9904-2 I2C/SMBus address is hard coded to
1001_101(r/w).
DS20005382C-page 10
4.6.1
ALERT/THERM2 Output
ALERT/THERM2 PIN INTERRUPT
MODE
When configured to operate in interrupt mode, the
ALERT/THERM2 pin asserts low when an out-of-limit
measurement (> high limit or < low limit) is detected on
any diode or when an external diode fault is detected.
The ALERT/THERM2 pin will remain asserted as long
as an out-of-limit condition remains. Once the
out-of-limit condition has been removed, the
ALERT/THERM2 pin will remain asserted until the
appropriate status bits are cleared.
The ALERT/THERM2 pin can be masked by setting
the MASK_ALL bit. Once the ALERT/THERM2 pin has
been masked, it will be deasserted and remain deasserted until the MASK_ALL bit is cleared by the user.
Any interrupt conditions that occur while the
ALERT/THERM2 pin is masked will update the Status
Register normally. There are also individual channel
masks (see Register 5-20).
The ALERT/THERM2 pin is used as an interrupt signal
or as an SMBus Alert signal that allows an SMBus
slave to communicate an error condition to the master.
One or more ALERT/THERM2 Outputs can be
hard-wired together.
4.6.2
ALERT/THERM2 PIN IN THERM
MODE
When the ALERT/THERM2 pin is configured to operate in THERM mode, it will be asserted if any of the
measured temperatures exceeds the respective high
limit. The ALERT/THERM2 pin will remain asserted
until all temperatures drop below the corresponding
high limit minus the Therm Hysteresis value.
When the ALERT/THERM2 pin is asserted in THERM
mode, the corresponding high limit status bits will be
set. Reading these bits will not clear them until the
ALERT/THERM2 pin is deasserted. Once the
ALERT/THERM2 pin is deasserted, the status bits will
be automatically cleared.
The MASK_ALL bit will not block the ALERT/THERM2
pin in this mode; however, the individual channel
masks (see Register 5-20) will prevent the respective
channel from asserting the ALERT/THERM2 pin.
4.6.3
DEFAULT POWER UP CONDITIONS
On power-up, the ALERT/THERM2 is disabled and the
MASK ALL (MSKAL) bit in the CONFIG register (see
Register 5-6) is set. Additionally, an artificial fault has
been placed in the device, and is enabled at power up.
The FAULT TEST (FT_TST) bit in the Fault Status register (see Register 5-20) will allow the assertion of the
ALERT/THERM2 pin when this test mode is enabled
once MSKAL is cleared. To use the ALERT/THERM2
functions described in this section, the MSKAL bit must
be set to ‘0’, and the FT_TST bit to ‘1’ in order for the
pin to function properly.
2015-2016 Microchip Technology Inc.
MCP9902/3/4
4.7
Temperature Measurement
The MCP9902/3/4 can monitor the temperature of up
to three externally connected diodes.
The device contains programmable High, Low and
Therm limits for all measured temperature channels. If
the measured temperature goes below the Low limit or
above the High limit, the ALERT/THERM2 pin can be
asserted (based on user settings). If the measured
temperature meets or exceeds the Therm Limit, the
THERM pin is asserted unconditionally, providing two
tiers of temperature detection.
4.8
Beta Compensation
The MCP9902/3/4 is configured to monitor the
temperature of basic diodes (e.g., 2N3904) or CPU
thermal diodes. For the MCP9902/3/4, the External
Diode 1 channel automatically detects the type of
external diode and determines the optimal setting to
reduce temperature errors introduced by beta variation.
Compensating for this error is also known as
implementing the transistor or BJT model for
temperature measurement.
For discrete transistors configured with the collector and
base shorted together, the beta is generally sufficiently
high such that the percent change in beta variation is
very small. For example, a 10% variation in beta for two
forced emitter currents with a transistor whose ideal
beta is 50 would contribute approximately +0.25°C error
at +100°C. However, for substrate transistors where the
base-emitter junction is used for temperature measurement and the collector is tied to the substrate, the proportional beta variation will cause large error. For
example, a 10% variation in beta for two forced emitter
currents with a transistor whose ideal beta is 0.5 would
contribute approximately +8.25°C error at +100°C.
The MCP9904 does not support Beta Compensation on
External Diode 2 and External Diode 3 channels due to
the high beta of diode-connected transistors.
4.9
Resistance Error Correction (REC)
Parasitic resistance in series with the external diodes
will limit the accuracy obtainable from temperature
measurement devices. The voltage developed across
this resistance by the switching diode currents causes
the temperature measurement to read higher than the
true temperature. Contributors to series resistance are
PCB trace resistance, on die (i.e., on the processor)
metal resistance, bulk resistance in the base and emitter of the temperature transistor. Typically, the error
caused by series resistance is +0.7°C per ohm. The
MCP9902/3/4 automatically corrects up to 100 ohms
of series resistance.
4.10
Programmable External Diode
Ideality Factor
The MCP9902/3/4 is designed for external diodes with
an ideality factor of 1.008. Not all external diodes,
processor or discrete, will have this exact value. This
variation of the ideality factor introduces temperature
measurement errors which must be corrected. This
correction is typically done using programmable offset
registers. Since an ideality factor mismatch introduces
an error that is a function of temperature, this correction
is only accurate within a small range of temperatures.
To provide maximum flexibility to the user, the
MCP9902/3/4 provides a 6-bit register for each external
diode where the ideality factor of the diode used is
programmed to eliminate errors across all
temperatures.
These registers store the ideality factors that are
applied to the external diode. Table 4-3 defines each
setting and the corresponding ideality factor. Beta
Compensation and Resistance Error Correction
automatically correct for most diode ideality errors;
therefore, it is not recommended that these settings be
updated without consulting Microchip Technology Inc.
Care should be taken when setting the BETA bits if
the auto-detection circuitry is disabled. If the Beta
Compensation factor is set at a beta value that is higher
than the transistor beta, the circuit may introduce
measurement errors. When measuring a discrete
thermal diode (such as 2N3904) or a CPU diode that
functions like a discrete thermal diode (such as an AMD
processor diode), the BETA bits should be set to
‘111b’.
2015-2016 Microchip Technology Inc.
DS20005382C-page 11
MCP9902/3/4
TABLE 4-3:
IDEALITY FACTOR LOOK-UP
TABLE (DIODE MODEL)
Setting Factor Setting Factor Setting Factor
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
0.9949
0.9962
0.9975
0.9988
1.0001
1.0014
1.0027
1.0040
1.0053
1.0066
1.0080
1.0093
1.0106
1.0119
1.0133
1.0146
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
1.0159
1.0172
1.0185
1.0200
1.0212
1.0226
1.0239
1.0253
1.0267
1.0280
1.0293
1.0306
1.0319
1.0332
1.0345
1.0358
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
1.0371
1.0384
1.0397
1.0410
1.0423
1.0436
1.0449
1.0462
1.0475
1.0488
1.0501
1.0514
1.0527
1.0540
1.0553
1.0566
For CPU substrate transistors that require the BJT
transistor model, the ideality factor behaves slightly
differently than for discrete diode-connected
transistors. Refer to Table 4-4 when using a CPU
substrate transistor.
4.11
The MCP9902/3/4 detects several “diode fault” mechanisms, defined as one of the following: an open
between DP and DN, a short from VDD to DP, or a
short from VDD to DN. When each temperature measurement is made, the device checks for a diode fault
on the external diode channel(s). When a diode fault is
detected, the ALERT/THERM2 pin asserts (unless
masked, see Register 5-20) and the temperature data
reads 00h in the MSB and LSB registers (note: the low
limit will not be checked).
If a short occurs across DP and DN or a short occurs
from DP to GND, the low limit status bit is set and the
ALERT/THERM2 pin asserts (unless masked). This
condition is indistinguishable from a temperature
measurement of 0.000°C (-64°C in extended range)
resulting in temperature data of 00h in the MSB and LSB
registers.
If a short from DN to GND occurs (with a diode-connected transistor), temperature measurements will
continue as normal with no alerts.
The External Diode Fault Register (Register 5-19)
indicates which of the external diodes caused the
FAULT bit in the Status Register to be set. This
register is cleared when it is read.
4.12
TABLE 4-4:
SUBSTRATE DIODE IDEALITY
FACTOR LOOK-UP TABLE
(BJT MODEL)
Setting Factor Setting Factor Setting Factor
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
0.9869
0.9882
0.9895
0.9908
0.9921
0.9934
0.9947
0.9960
0.9973
0.9986
1.0000
1.0013
1.0026
1.0039
1.0053
1.0066
DS20005382C-page 12
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
1.0079
1.0092
1.0105
1.0120
1.0132
1.0146
1.0159
1.0173
1.0187
1.0200
1.0213
1.0226
1.0239
1.0252
1.0265
1.0278
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
1.0291
1.0304
1.0317
1.0330
1.0343
1.0356
1.0369
1.0382
1.0395
1.0408
1.0421
1.0434
1.0447
1.0460
1.0473
1.0486
Diode Faults
Consecutive Alerts
The MCP9902/3/4 contains multiple consecutive alert
counters. One set of counters applies to the
ALERT/THERM2 pin and the second set of counters
applies to the THERM pin. Each temperature measurement channel has a separate consecutive alert counter
for each of the ALERT/THERM2 and THERM pins. All
counters are user programmable and determine the
number of consecutive measurements that a temperature channel(s) must be out-of-limit or reporting a diode
fault before the corresponding pin is asserted.
The Consecutive Alert register determines how many
times an out-of-limit error or diode fault must be
detected in consecutive measurements before the
ALERT/THERM2 or THERM pin is asserted. Additionally, the Consecutive Alert register controls the SMBus
Time-out functionality.
An out-of-limit condition (i.e., HIGH, LOW or FAULT)
occurring on the same temperature channel in consecutive measurements will increment the consecutive
alert counter. The counters will also be reset if no
out-of-limit condition or diode fault condition occurs in a
consecutive reading.
When the ALERT/THERM2 pin is configured as an
interrupt, when the consecutive alert counter reaches
its programmed value, the following will occur: the
STATUS bit(s) for that channel and the last error
condition(s) (i.e., E1HIGH, or E2LOW and/or
2015-2016 Microchip Technology Inc.
MCP9902/3/4
E2FAULT) will be set to ‘1’, the ALERT/THERM2 pin
will be asserted, the consecutive alert counter will be
cleared and measurements will continue.
When the ALERT/THERM2 pin is configured as a
comparator, the consecutive alert counter will ignore
diode fault and low limit errors and only increment if the
measured temperature exceeds the High Limit.
Additionally, once the consecutive alert counter
reaches the programmed limit, the ALERT/THERM2
pin will be asserted, but the counter will not be reset. It
will remain set until the temperature drops below the
High Limit minus the Therm Hysteresis value.
For example, if the CALRT bits are set for four
consecutive alerts on an MCP9902/3/4 device, the high
limits are set at +70°C and none of the channels are
masked, then the ALERT/THERM2 pin will be asserted
after the following five measurements:
• The Internal Diode reads +71°C and both the
external diodes read +69°C. Consecutive alert
counter for INT is incremented to 1.
• Both the Internal Diode and the External Diode 1
read +71°C and External Diode 2 reads +68°C.
The consecutive alert counter for INT is incremented to 2 and the counter for EXT1 is set to 1.
• The External Diode 1 reads +71°C and both Internal Diode and External Diode 2 read +69°C. The
consecutive alert counters for INT and EXT2 are
cleared, and EXT1 is incremented to 2.
• The Internal Diode reads +71°C and both external
diodes read +71°C. The consecutive alert counter
for INT is set to 1, EXT2 is set to 1 and EXT1 is
incremented to 3.
• The Internal Diode reads +71°C and both external
diodes read +71°C. The consecutive alert counter
for INT is incremented to 2, EXT2 is set to 2 and
EXT1 is incremented to 4. The appropriate status
bits are set for EXT1 and the ALERT/THERM2 pin
is asserted. The EXT1 counter is reset to 0 and all
other counters hold the last value until the next
temperature measurement.
All temperature channels use this value to set the
respective counters. The consecutive Therm counter
is incremented whenever any measurement exceeds
the corresponding Therm Limit.
If the temperature drops below the Therm Limit, the
counter is reset. If a number of consecutive
measurements above the Therm Limit occurs, the
THERM pin is asserted low.
TABLE 4-5:
CONSECUTIVE ALERT/
THERM SETTINGS
2
1
0
0
0
0
0
0
0
1
1
1
1
1
1
4.13
Number of consecutive out of
limit measurements
1
(default for CALRT)
2
3
4
(default for CTHRM)
Limit Register Interaction
The various limit registers in the device interact based
on both external conditions present on the diode pins
as well as changes in register bits in the SMBus interface. The device contains both high and low limits for
all temperature channels. If the measured temperature
exceeds the high limit, then the corresponding status
bit is set and the ALERT/THERM2 pin is asserted.
Likewise, if the measured temperature is less than or
equal to the low limit, the corresponding status bit is
set and the ALERT/THERM2 pin is asserted.
The data format for the limits must match the selected
data format for the temperature so that if the extended
temperature range is used, the limits must be
programmed in the extended data format.
The limit registers with multiple addresses are fully
accessible at either address.
When the device is in Standby mode, updating the limit
registers will have no effect until the next conversion
cycle occurs. This can be initiated via a write to the
One Shot register (see Register 5-15) or by clearing
the RUN/STOP bit (see Register 5-6).
The THERM Limit Status register contains the status
bits that are set when a temperature channel Therm
Limit is exceeded. If any of these bits are set, the
THERM status bit in the Status register is set. Reading
from the THERM Limit Status register will not clear the
status bits. Once the temperature drops below the
THERM Limit minus the THERM Hysteresis, the corresponding status bits will be automatically cleared. The
THERM bit in the Status register will be cleared when
all individual channel THERM bits are cleared.
Once the THERM pin has been asserted, the
consecutive therm counter will not reset until the
corresponding temperature drops below the Therm
Limit minus the Therm Hysteresis value.
The default setting is one out-of-limit conversion and it is
set in Register 5-21.
2015-2016 Microchip Technology Inc.
DS20005382C-page 13
MCP9902/3/4
4.13.1
HIGH LIMIT REGISTER
4.14
Digital Filter
The High Limit Status register contains the status bits
that are set when a temperature channel high limit is
exceeded. If any of these bits are set, then the HIGH
status bit in the Status register is set. Reading from the
High Limit Status register will clear all bits. Reading
from the register will also clear the HIGH status bit in
the Status register.
To reduce the effect of noise and temperature spikes on
the reported temperature, the External Diode channel
uses a programmable digital filter. This filter can be configured as Level 1, Level 2, or Disabled (default). The
typical filter performance is shown in Figure 4-2 and
Figure 4-3. The Filter Configuration register controls the
digital filter on the External Diode 1 channel.
The ALERT/THERM2 pin will be set if the programmed number of consecutive alert counts have
been met and any of these status bits are set.
TABLE 4-6:
The status bits will remain set until read unless the
ALERT/THERM2 pin is configured as a comparator
output (see Section 4.6.2 “ALERT/THERM2 Pin In
THERM Mode”).
LOW LIMIT REGISTER
The ALERT/THERM2 pin will be set if the programmed number of consecutive alert counts have
been met and any of these status bits are set.
The status bits will remain set until read unless the
ALERT/THERM2 pin is configured as a comparator
output (see Section 4.6.2 “ALERT/THERM2 Pin In
THERM Mode”).
4.13.3
Unlike the ALERT/THERM2 pin, the THERM pin
cannot be masked. Additionally, the THERM pin will be
released once the temperature drops below the
corresponding threshold minus the Therm Hysteresis.
4.13.4
CHANNEL MASKING
The Channel Mask register (Register 5-20) controls
individual channel masking. When a channel is
masked, the ALERT/THERM2 pin will not be asserted
when the masked channel reads a diode fault or out of
limit error. The channel mask does not mask the
THERM pin.
8x
90
Disabled
80
Level 1
70
Level 2
60
50
40
30
20
10
0
0
2
4
FIGURE 4-2:
Response.
6
8
Samples
10
12
14
Temperature Filter Step
90
80
Disabled
70
60
50
Level 1
40
Level 2
30
20
10
0
0
2
FIGURE 4-3:
Response.
DS20005382C-page 14
Disabled (default)
Level 1
Level 1
Level 2
2: Filtering Level 2 corresponds to
attenuation of a temperature spike.
THERM LIMIT REGISTER
The Therm Limit registers are used to determine
whether a critical thermal event has occurred. If the
measured temperature exceeds the Therm Limit, the
THERM pin is asserted. The limit setting must match
the chosen data format of the temperature reading
registers.
Averaging
Note 1: Filtering Level 1 corresponds to 4x
attenuation of a temperature spike.
Temperature (°C)
The Low Limit Status register contains the status bits
that are set when a temperature channel drops below
the low limit. If any of these bits are set, then the LOW
status bit in the Status register is set. Reading from the
Low Limit Status register will clear all bits.
Temperature (°C)
4.13.2
FILTER SETTINGS
FILTER
1
0
0
0
0
1
1
0
1
1
4
6
8
Samples
10
12
14
Temperature Filter Impulse
2015-2016 Microchip Technology Inc.
MCP9902/3/4
4.15
Temperature Measurement
Results and Data
The temperature measurement results are stored in
the internal and external temperature registers. These
are then compared with the values stored in the high
and low limit registers. Both external and internal temperature measurements are stored in 11-bit format
with the eight (8) most significant bits stored in a high
byte register and the three (3) least significant bits
stored in the three (3) MSB positions of the low byte
register. All other bits of the low byte register are set to
zero.
The MCP9902/3/4 has two selectable temperature
ranges. The default range is from 0°C to +127°C and
the temperature is represented as binary number able
to report a temperature from 0°C to +127.875°C in
0.125°C steps.
The extended range is an extended temperature
range from -64°C to +191°C. The data format is a
binary number offset by +64°C. The extended range is
used to measure temperature diodes with a large
known offset (such as AMD processor diodes) where
the diode temperature plus the offset would be equivalent to a temperature higher than +127°C.
Table 4-7 shows the default and extended range
formats.
2015-2016 Microchip Technology Inc.
TABLE 4-7:
Temperature
(°C)
TEMPERATURE DATA
FORMAT
Default Range
0°C to +127°C
Extended Range
-64°C to +191°C
Diode Fault
-64
000 0000 0000 000 0000 0000
000 0000 0000 000 0000 0000
(Note 2)
-1
000 0000 0000 001 1111 1000
0
000 0000 0000 010 0000 0000
(Note 1)
0.125
000 0000 0001 010 0000 0001
1
000 0000 1000 010 0000 1000
64
010 0000 0000 100 0000 0000
65
010 0000 1000 100 0000 1000
127
011 1111 1000 101 1111 1000
127.875
011 1111 1111 101 1111 1111
128
011 1111 1111 110 0000 0000
(Note 3)
190
011 1111 1111 111 1111 0000
191
011 1111 1111 111 1111 1000
≥ 191.875 011 1111 1111 111 1111 1111
(Note 4)
Note 1: In default mode, all temperatures < 0°C
will be reported as 0°C
2: In the extended range, all temperatures
less than -64°C will be reported as -64°C.
3: For the default range, all temperatures
greater than +127.875°C will be reported
as +127.875°C.
4: For the extended range, all temperatures
greater than +191.875°C will be reported
as +191.875°C.
DS20005382C-page 15
MCP9902/3/4
5.0
COMMUNICATIONS
PROTOCOL
The MCP9902/3/4 communicates with a host
controller, such as an PIC MCU, through the SMBus.
The SMBus is a two-wire serial communication
protocol between a computer host and its peripheral
devices. A detailed timing diagram is shown in
Figure 4-1.
For the first 15 ms after power-up the device may not
respond to SMBus communications.
5.1
SMBus Control Bits
The interaction between clock and data creates special
function bits within the data stream.
5.1.1
SMBUS START BIT
The SMBus Start bit is defined as a transition of the
SMBus Data line from a logic ‘1’ state to a logic ‘0’
state while the SMBus Clock line is in a logic ‘1’ state.
5.1.2
SMBUS ADDRESS AND RD/WR BIT
The SMBus Address Byte consists of the 7-bit client
address followed by the RD/WR indicator bit. If this
RD/WR bit is a logic ‘0’, the SMBus Host is writing
data to the client device. If this RD/WR bit is a logic ‘1’,
the SMBus Host is reading data from the client device.
5.1.3
SMBUS DATA BYTES
All SMBus Data bytes are sent most significant bit first
and composed of 8-bits of information.
5.1.4
SMBUS ACK AND NACK BITS
The SMBus client will acknowledge all data bytes that
it receives. This is done by the client device pulling the
SMBus data line low after the 8th bit of each byte that
is transmitted. This applies to the Write Byte protocol.
The Host will NACK (not acknowledge) the last data
byte to be received from the client by holding the
SMBus data line high after the 8th data bit has been
sent.
5.1.5
SMBUS STOP BIT
The SMBus Stop bit is defined as a transition of the
SMBus Data line from a logic ‘0’ state to a logic ‘1’
state while the SMBus clock line is in a logic ‘1’ state.
When the device detects an SMBus Stop bit and it has
been communicating with the SMBus protocol, it will
reset its client interface and prepare to receive further
communications.
DS20005382C-page 16
5.2
SMBus Timeout
The MCP9902/3/4 supports SMBus Timeout. If the
clock line is held low for longer than tTIMEOUT, the
device will reset its SMBus protocol. This function can
be enabled by setting the TIMEOUT bit (see
Register 5-21).
5.3
SMBus and I2C Compatibility
The MCP9902/3/4 is compatible with SMBus and I2C.
The major differences between SMBus and I2C
devices are highlighted here. For more information,
refer to the SMBus 2.0 and I2C specifications. For
information on using the MCP9902/3/4 in an I2C system, refer to AN14.0 “Microchip Dedicated Slave
Devices in I2C Systems”, DS00001853.
• MCP9902/3/4 supports I2C fast mode at 400 kHz.
This covers the SMBus max time of 100 kHz.
• Minimum frequency for SMBus communications
is 10 kHz.
• The SMBus client protocol will reset if the clock is
held at a logic ‘0’ for longer than 30 ms. This timeout functionality is disabled by default in the
MCP9902/3/4 and can be enabled by writing to
the TIMEOUT bit. I2C does not have a timeout.
• I2C devices do not support the Alert Response
Address functionality (which is optional for
SMBus).
Attempting to communicate with the MCP9902/3/4
SMBus interface with an invalid slave address or
invalid protocol will result in no response from the
device and will not affect its register contents. Stretching of the SMCLK signal is supported, provided other
devices on the SMBus control the timing.
5.4
SMBus Protocols
The device supports Send Byte, Read Byte, Write
Byte, Receive Byte and the Alert Response Address
as valid protocols, as shown below.
All of the following protocols use the convention in
Table 5-1.
TABLE 5-1:
PROTOCOL FORMAT
Data Sent To Device
# of bits sent
Data Sent To The Host
# of bits sent
2015-2016 Microchip Technology Inc.
MCP9902/3/4
5.4.1
WRITE BYTE
The Write Byte is used to write one byte of data to the
registers, as shown in Table 5-2.
TABLE 5-2:
WRITE BYTE PROTOCOL
START
Slave Address
WR
ACK
Register
Address
ACK
Register
Data
ACK
STOP
1→0
YYYY_YYY
0
0
XXh
0
XXh
0
0→1
5.4.2
READ BYTE
The Read Byte protocol is used to read one byte of
data from the registers as shown in Table 5-3.
TABLE 5-3:
READ BYTE PROTOCOL
START
Slave Address
WR
ACK
Register Address
ACK
1→0
YYYY_YYY
0
0
XXh
0
START
Slave Address
RD
ACK
Register Data
NACK
STOP
1→0
YYYY_YYY
1
0
XXh
1
0→1
5.4.3
SEND BYTE
The Send Byte protocol is used to set the internal
address register pointer to the correct address
location. No data is transferred during the Send Byte
protocol as shown in Table 5-4.
TABLE 5-4:
SEND BYTE PROTOCOL
START
Slave Address
WR
ACK
Register
Address
ACK
STOP
1→0
YYYY_YYY
0
0
XXh
0
0→1
5.4.4
RECEIVE BYTE
The Receive Byte protocol is used to read data from a
register when the internal register address pointer is
known to be at the right location (e.g. set via Send
Byte). This is used for consecutive reads of the same
register as shown in Table 5-5.
TABLE 5-5:
RECEIVE BYTE PROTOCOL
START
Slave Address
RD
ACK
Register Data
NACK
STOP
1→0
YYYY_YYY
1
0
XXh
1
0→1
2015-2016 Microchip Technology Inc.
DS20005382C-page 17
MCP9902/3/4
5.5
Alert Response Address
The ALERT/THERM2 output can be used as a
processor interrupt or as an SMBus Alert.
When it detects that the ALERT/THERM2 pin is
asserted, the host will send the Alert Response
Address (ARA) to the general address of 0001_100xb.
All devices with active interrupts will respond with their
client address as shown in Table 5-6.
TABLE 5-6:
ALERT RESPONSE ADDRESS PROTOCOL
START
ALERT Response Address
RD
ACK
Device Address
NACK
STOP
1→0
0001_100
1
0
YYYY_YYY
1
0→1
The MCP9902/3/4 will respond to the ARA in the
following way:
• Send Slave Address and verify that full slave
address was sent (i.e. the SMBus communication
from the device was not prematurely stopped due
to a bus contention event).
• Set the MASK_ALL bit to clear the
ALERT/THERM2 pin.
The ARA does not clear the Status Register and if the
MASK_ALL bit is cleared prior to the Status Register
being cleared, the ALERT/THERM2 pin will be
reasserted.
DS20005382C-page 18
2015-2016 Microchip Technology Inc.
2015-2016 Microchip Technology Inc.
5.6
Register Description
TABLE 5-7:
REGISTER SET IN HEXADECIMAL ORDER
Register
Address
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Por Value
00h
INT TEMP HIGH BYTE
IHB7
IHB6
IHB5
IHB4
IHB3
IHB2
IHB1
IHB0
00h
01h
EXT1 TEMP HIGH BYTE
E1HB7
E1HB6
E1HB5
E1HB4
ETHB3
E1HB2
E1HB1
E1HB0
00h
02h
STATUS
BUSY
IHIGH
ILOW
EHIGH
ELOW
FAULT
ETHRM
ITHRM
00h
03h
CONFIG
MSKAL
R/S
AT/THM
RECD1
RECD2
RANGE
DA_DIS
APDD
00h
04h
CONVERT
SLEEP
—
—
—
CONV3
CONV2
CONV1
CONV0
06h
(4/sec)
05h
INT DIODE HI LIMIT TEMP
IDHL7
IDHL6
IDHL5
IDHL4
IDHL3
IDHL2
IDHL1
IDHL0
55h
(+85°C)
06h
INT DIODE LO LIMIT TEMP
IDLL7
IDLL6
IDLL5
IDLL4
IDLL3
IDLL2
IDLL1
IDLL0
00h
(0°C)
07h
EXT1 HI LIMIT TEMP HI BYTE
E1HLH7
E1HLH6
E1HLH5
E1HLH4
E1HLH3
E1HLH2
E1HLH1
E1HLH0
55h
(+85°C)
08h
EXT1 LO LIMIT TEMP HI BYTE
E1LLH7
E1LLH6
E1LLH5
E1LLH4
E1LLH3
E1LLH2
E1LLH1
E1LLH0
00h
(0°C)
CONFIG
MSKAL
R/S
AT/THM
RECD1
RECD2
RANGE
DA_DIS
APDD
00h
CONVERT
STOP
—
—
—
CONV3
CONV2
CONV1
CONV0
06h
(4/sec)
0Bh
INT DIODE HI LIMIT TEMP
IDHL7
IDHL6
IDHL5
IDHL4
IDHL3
IDHL2
IDHL1
IDHL0
55h
(+85°C)
0Ch
INT DIODE LO LIMIT TEMP
IDLL7
IDLL6
IDLL5
IDLL4
IDLL3
IDLL2
IDLL1
IDLL0
00h
(0°C)
0Dh
EXT1 HI LIMIT TEMP HI BYTE
E1HLH7
E1HLH6
E1HLH5
E1HLH4
E1HLH3
E1HLH2
E1HLH1
E1HLH0
55h
(+85°C)
0Eh
EXT1 LO LIMIT TEMP HI BYTE
E1LLH7
E1LLH6
E1LLH5
E1LLH4
E1LLH3
E1LLH2
E1LLH1
E1LLH0
00h
(0°C)
0Fh
ONE SHOT
ONSH7
ONSH6
ONSH5
ONSH4
ONSH3
ONSH2
ONSH1
ONSH0
00h
10h
EXT1 TEMP LO BYTE
E1LB2
E1LB1
E1LB0
—
—
—
—
—
00h
11h
SCRTCHPD1
SPD17
SPD16
SPD15
SPD14
SPD13
SPD12
SPD11
SPD10
00h
12h
SCRTCHPD2
SPD27
SPD26
SPD25
SPD24
SPD23
SPD22
SPD21
SPD20
00h
13h
EXT1 HI LIM TEMP LO BYTE
E1HLL2
E1HLL1
E1HLL0
—
—
—
—
—
00h
14h
EXT1 LO LIMIT TEMP LO BYTE
E1LLL2
E1LLL1
E1LLL0
—
—
—
—
—
00h
15h
EXT2 HI LIMIT TEMP HI BYTE
E2HLH7
E2HLH6
E2HLH5
E2HLH4
E2HLH3
E2HLH2
E2HLH1
E2HLH0
55h
(+85°C)
MCP9902/3/4
DS20005382C-page 19
09h
0Ah
REGISTER SET IN HEXADECIMAL ORDER (CONTINUED)
Register
Address
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Por Value
16h
EXT2 LO LIMIT TEMP HI BYTE
E2LLH7
E2LLH6
E2LLH5
E2LLH4
E2LLH3
E2LLH2
E2LLH1
E2LLH0
00h
(0°C)
17h
EXT2 HI LIMIT TEMP LO BYTE
E2HLL2
E2HLL1
E2HLL0
—
—
—
—
—
00h
18h
EXT2 LO LIMIT TEMP LO BYTE
E2LLL2
E2LLL1
E2LLL0
—
—
—
—
—
00h
19h
EXT1 THERM LIMIT
E1THL7
E1THL6
E1THL5
E1THL4
E1THL3
E1THL2
E1THL1
E1THL0
55h
(+85°C)
1Ah
EXT2 THERM LIMIT
E2THL7
E2THL6
E2THL5
E2THL4
E2THL3
E2THL2
E2THL1
E2THL0
55h
(+85°C)
1Bh
EXT DIODE FAULT STS
—
—
—
—
E3FLT
E2FLT
E1FLT
—
00h
1Fh
DIODE FAULT MASK
—
—
—
—
E3MSK
E2MSK
E1MSK
INTMSK
00h
20h
INT DIODE THERM LIMIT
IDTHL7
IDTHL6
IDTHL5
IDTHL4
IDTHL3
IDTHL2
IDTHL1
IDTHL0
55h
(+85°C)
21h
THRM HYS
THMH7
THMH6
THMH5
THMH4
THMH3
THMH2
THMH1
THMH0
0Ah
(+10°C)
22h
CONSEC ALRT
TMOUT
CTHM2
CTHM1
CTHM0
CALRT2
CALRT1
CALRT0
—
70h
23h
EXT2 TEMP HI BYTE
E2THB7
E2THB6
E2THB5
E2THB4
E2THB3
E2THB2
E2THB1
E2THB0
00h
24h
EXT2 TEMP LO BYTE
E2TLB2
E2TLB1
E2TLB0
—
—
—
—
—
00h
25h
EXT1 BETA CONFIG
—
—
—
—
ENBL1
BETA12
BETA11
BETA10
08h
26h
EXTD2 BETA CFG
—
—
—
—
ENBL2
BETA22
BETA21
BETA20
08h
27h
EXT1 IDEALITY FACTOR
—
—
IDEL15
IDEL14
IDEL13
IDEL12
IDEL11
IDEL10
12h
(1.008)
28h
EXT2 IDEALITY FACTOR
—
—
IDEL25
IDEL24
IDEL23
IDEL22
IDEL21
IDEL20
12h
(1.008)
2015-2016 Microchip Technology Inc.
29h
INT TEMP LO BYTE
ITLB2
ITLB1
ITLB0
—
—
—
—
—
00h
2Ah
EXT3 TEMP HI BYTE
E3THB7
E3THB6
E3THB5
E3THB4
E3THB3
E3THB2
E3THB1
E3THB0
00h
2Bh
EXT3 TEMP LO BYTE
E3TLB2
E3TLB1
E3TLB0
—
—
—
—
—
00h
2Ch
EXT3 HI LIMIT HI BYTE
E3HLH7
E3HLH6
E3HLH5
E3HLH4
E3HLH3
E3HLH2
E3HLH1
E3HLH0
55h
(+85°C)
2Dh
EXT3 LO LIMIT HI BYTE
E3LLH7
E3LLH6
E3LLH5
E3LLH4
E3LLH3
E3LLH2
E3LLH1
E3LLH0
00h
(0°C)
2Eh
EXT3 HI LIMIT LO BYTE
E3HLL2
E3HLL1
E3HLL0
—
—
—
—
—
00h
2Fh
EXTD3 LO LIMIT LO BYTE
E3LLL2
E3LLL1
E3LLL0
—
—
—
—
—
00h
30h
EXT3 THERM LIMIT
E3THL7
E3THL6
E3THL5
E3THL4
E3THL3
E3THL2
E3THL1
E3THL0
55h
(+85°C)
MCP9902/3/4
DS20005382C-page 20
TABLE 5-7:
2015-2016 Microchip Technology Inc.
TABLE 5-7:
REGISTER SET IN HEXADECIMAL ORDER (CONTINUED)
Register
Address
31h
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Por Value
EXT3 IDEALITY FACTOR
—
—
IDEL35
IDEL34
IDEL23
IDEL32
IDEL31
IDEL30
12h
(1.008)
35h
HI LIMIT STATUS
—
—
—
—
E3HIGH
E2HIGH
E1HIGH
IHIGH
00h
36h
LO LIMIT STATUS
—
—
—
—
E3LOW
E2LOW
E1LOW
ILOW
00h
37h
THRM LIMIT STATUS
—
—
—
—
E3THM
E2THM
E1THM
ITHM
00h
40h
FLTR SEL
—
—
—
—
—
—
FLTER1
FLTER0
00h
FDh
PRODUCT ID
(DECODER)
0
0
1
0
0
EXT2_APD_EN
0
EXT2_EN
MCP9903
MCP9904
20h
21h
25h
FEh
MANUFACTURER ID
5Dh
FFh
REVISION
00h
MCP9902/3/4
DS20005382C-page 21
MCP9902/3/4
5.7
Data Read Interlock
When any temperature channel high byte register is
read, the corresponding low byte is copied into an
internal ‘shadow’ register. The user is free to read the
low byte at any time and be guaranteed that it will
correspond to the previously read high byte.
Regardless if the low byte is read or not, reading from
the same high byte register again will automatically
refresh this stored low byte data.
REGISTER 5-1:
R-0
INT TEMP HI BYTE: INTERNAL DIODE HIGH BYTE TEMPERATURE DATA
REGISTER (ADDRESS 00H)
R-0
R-0
R-0
R-0
R-0
R-0
R-0
IHB
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
7-0
W = Writable bit
‘1’ = bit is set
U = Unimplemented bit, read as 0
‘0’ = Bit is cleared
x = Bit in unknown
IHB: 2’s complement integer value of the internal diode temperature reading
REGISTER 5-2:
R-0
INT TEMP LO BYTE: INTERNAL DIODE LOW BYTE TEMPERATURE DATA
REGISTER (ADDRESS 29H)
R-0
R-0
ILB
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
x = Bit in unknown
7-5
ILB: Fractional portion of the Internal Diode Temperature to be added to the value at register
00h
111 = 0.875°C
110 = 0.750°C
101 = 0.625°C
100 = 0.500°C
011 = 0.375°C
010 = 0.250°C
001 = 0.125°C
000 = 0.000°C
4-0
Unimplemented: Read as ‘0’
DS20005382C-page 22
2015-2016 Microchip Technology Inc.
MCP9902/3/4
REGISTER 5-3:
R-0
EXT(N) TEMP HI BYTE: EXTERNAL DIODE HIGH BYTE TEMPERATURE DATA
REGISTER (ADDRESSES 01H, 23H, 2AH)
R-0
R-0
R-0
R-0
R-0
R-0
R-0
EXT(N)_HB
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
7-0
x = Bit in unknown
EXT(N)_HB: 2’s complement integer value of the External Diode n temperature reading, where
n = 1 to 3, depending on the device
)
REGISTER 5-4:
R-0
EXT(N) TEMP LO BYTE: EXTERNAL DIODE LOW BYTE TEMPERATURE DATA
REGISTER (ADDRESSES 10H, 24H, 2BH)
R-0
R-0
EXT(N)_LB
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
x = Bit in unknown
7-5
EXT(N)_LB: Fractional portion of the Internal Diode Temperature to be added to the value at
register 00h
111 = 0.875°C
110 = 0.750°C
101 = 0.625°C
100 = 0.500°C
011 = 0.375°C
010 = 0.250°C
001 = 0.125°C
000 = 0.000°C
4-0
Unimplemented: Read as ‘0’
2015-2016 Microchip Technology Inc.
DS20005382C-page 23
MCP9902/3/4
REGISTER 5-5:
STATUS: STATUS REGISTER REPORTING STATE OF INTERNAL AND
EXTERNAL DIODES (ADDRESS 02H)
RC-0
RC-0
RC-0
RC-0
RC-0
RC-0
RC-0
RC-0
BUSY
IHIGH
ILOW
EHIGH
ELOW
FAULT
ETHRM
ITHRM
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
x = Bit in unknown
7
BUSY: This bit indicates that the ADC is currently converting. This bit does not cause either the
ALERT/THERM2 or THERM pin to be asserted.
1 = ADC is currently converting
0 = ADC is not converting
6
IHIGH: This bit indicates the Internal Diode channel exceeds its programmed high limit. When set, this
bit will assert the ALERT/THERM2 pin.
1 = Reported temperature above the high limit
0 = Reported temperature is not above the high limit
5
ILOW: This bit indicates the Internal Diode channel drops below its programmed low limit. When set,
this bit will assert the ALERT/THERM2 pin.
1 = Reported temperature below the low limit
0 = Reported temperature is not below the low limit
4
EHIGH: This bit indicates the External Diode channel exceeds its programmed high limit. When set,
this bit will assert the ALERT/THERM2 pin.
1 = Reported temperature above the high limit
0 = Reported temperature is not above the high limit
3
ELOW: This bit indicates the External Diode channel drops below its programmed low limit. When set,
this bit will assert the ALERT/THERM2 pin.
1 = Reported temperature below the low limit
0 = Reported temperature is not below the low limit
2
FAULT: This bit indicates when a diode fault is detected. When set, this bit will assert the
ALERT/THERM2 pin.
1 = Open circuit or short of a diode
0 = No fault reported
1
ETHRM: This bit indicates the External Diode channel exceeds the programmed Therm Limit. When
set, this bit will assert the THERM pin. This bit will remain set until the THERM pin is released at which
point it will be automatically cleared.
1 = Reported temperature above the high limit
0 = Reported temperature is not above the high limit
0
ITHRM: This bit is set when the Internal Diode channel exceeds the programmed Therm Limit. When
set, this bit will assert the THERM pin. This bit will remain set until the THERM pin is released at which
point it will be automatically cleared.
1 = Reported temperature above the high limit
0 = Reported temperature is not above the high limit
DS20005382C-page 24
2015-2016 Microchip Technology Inc.
MCP9902/3/4
REGISTER 5-6:
CONFIG: CONFIGURATION REGISTER (ADDRESSES 03H AND 09H)
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
MSKAL
R/S
AT/THM
RECD1
RECD2
RANGE
DA_DIS
APDD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
x = Bit in unknown
7
MSKAL: Masks the ALERT/THERM2 pin from asserting when the ALERT/THERM2 pin is in interrupt
mode. This bit has no effect when the ALERT/THERM2 pin is in comparator mode.
1 = The ALERT/THERM2 pin is masked and will not be asserted for any interrupt condition when the
ALERT/THERM2 pin is in interrupt mode. The Status Register will be updated normally.
0 = The ALERT/THERM2 pin is not masked. If any of the appropriate status bits are set, the
ALERT/THERM2 pin will be asserted.
6
R/S: Controls Active/Standby states
1 = The device is in Standby state and not converting (unless a one-shot has been commanded)
0 = The device is in Active state and converting on all channels
5
AT/THM: Controls the operation of the ALERT/THERM2 pin
1 = The ALERT/THERM2 pin acts in comparator mode as described in Section 4.6.2
“ALERT/THERM2 Pin In THERM Mode”. In this mode the MASK_ALL bit is ignored.
0 = The ALERT/THERM2 pin acts in interrupt mode as described in Section 4.6.1 “ALERT/THERM2
Pin Interrupt Mode”.
4
RECD1: Disables the Resistance Error Correction (REC) for the External Diode 1
1 = REC is disabled for the External Diode 1
0 = REC is enabled for the External Diode 1
3
RECD2: Disables the Resistance Error Correction (REC) for External Diode 2 and External Diode 3
1 = REC is disabled for External Diode 2 and External Diode 3
0 = REC is enabled for External Diode 2 and External Diode 3
2
RANGE: Configures the measurement range and data format of the temperature channels
1 = The temperature measurement range is -64°C to +191.875°C and the data format is offset binary
(see Table 4-7)
0 = The temperature measurement range is 0°C to +127.875°C and the data format is binary
1
DA_DIS: Disables the dynamic averaging feature on all temperature channels
1 = The dynamic averaging feature is disabled
0 = The dynamic averaging feature is enabled. All temperature channels will be converted with an
averaging factor that is based on the conversion rate as shown in Table 4-1.
0
APDD (MCP9904 only): Disables the anti-parallel diode operation
1= Anti-parallel diode mode is disabled. Only one external diode will be measured on the DP2 and
DN2 pins.
0 = Anti-parallel diode mode is enabled. Two external diodes will be measured on the DP2 and DN2 pins.
2015-2016 Microchip Technology Inc.
DS20005382C-page 25
MCP9902/3/4
REGISTER 5-7:
CONVERT: TEMPERATURE CONVERSION RATE REGISTER (ADDRESS 04H, 0AH)
RW-0
U-0
U-0
U-0
SLEEP
—
—
—
RW-0
RW-1
RW-1
RW-0
CONV
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
7
x = Bit in unknown
SLEEP
0 = Active Mode or Standby mode, as controlled by R/S bit in Register 02h
1 = SLEEP mode is enabled. This bit overrides R/S in Register 02h
6-4
Unimplemented: Read as ‘0’
3-0
CONV: The Conversion Rate Register controls how often the temperature measurement
channels are updated and compared against the limits. This register is fully accessible at either
address (04H, 0AH). Determines the conversion rate as shown in Table 4-1.
REGISTER 5-8:
RW-0
INT DIODE HI LIMIT TEMP: INTERNAL DIODE HIGH LIMIT TEMPERATURE
REGISTER (ADDRESSES 05H AND 0BH)
RW-1
RW-0
RW-1
RW-0
RW-1
RW-0
RW-1
IDHL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
7-0
x = Bit in unknown
IDHL: 2’s complement integer value of the Internal Diode n temperature reading
REGISTER 5-9:
R-0
INT DIODE LO LIM TEMP – INTERNAL DIODE LOW LIMIT TEMPERATURE
REGISTER (ADDRESSES 06H AND 0CH)
R-0
R-0
R-0
R-0
R-0
R-0
R-0
IDLL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
7-0
x = Bit in unknown
IDLL: Integer value of the Internal Diode temperature reading
DS20005382C-page 26
2015-2016 Microchip Technology Inc.
MCP9902/3/4
REGISTER 5-10:
RW-0
EXT(N) HI LIM TEMP HB – EXTERNAL DIODE N HIGH TEMPERATURE LIMIT,
HIGH BYTE REGISTER (ADDRESSES 07H AND 0DH, 15H, 2CH)
RW-1
RW-0
RW-1
RW-0
RW-1
RW-0
RW-1
EXT(N)_HLH
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
7-0
x = Bit in unknown
EXT(N)_HLH: Integer value of the External Diode n temperature reading, where N = 1 to 3
depending on device
REGISTER 5-11:
R-0
EXT(N) HI LIM LB – EXTERNAL DIODE N HIGH LIMIT TEMPERATURE, LOW
BYTE REGISTER (ADDRESSES 13H, 17H, 2EH)
R-0
R-0
EXT(N)_HLL
R-0
R-0
R-0
R-0
R-0
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
x = Bit in unknown
7-5
EXT(N)_HLL: Fractional portion of the High Limit Temperature to be added to the value at the
respective high byte registers
111 = 0.875°C
110 = 0.750°C
101 = 0.625°C
100 = 0.500°C
011 = 0.375°C
010 = 0.250°C
001 = 0.125°C
000 = 0.000°C
4-0
Unimplemented: Read as ‘0’
REGISTER 5-12:
RW-0
EXT(N) LO LIM HB – EXTERNAL DIODE N LOW LIMIT, HIGH BYTE
TEMPERATURE REGISTER (ADDRESSES 08H AND 0EH, 16H, 2DH)
RW-1
RW-0
RW-1
RW-0
RW-1
RW-0
RW-1
EXT(N)_LLHB
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
7-0
x = Bit in unknown
EXT(N)_LLHB: Integer portion of External Diode n Low temperature Limit, where n = 1 to 3
depending on device
2015-2016 Microchip Technology Inc.
DS20005382C-page 27
MCP9902/3/4
REGISTER 5-13:
R-0
EXT(N) LO LIM LB – EXTERNAL DIODE N LOW LIMIT, LOW BYTE
TEMPERATURE REGISTER (ADDRESSES 14H, 18H, 2FH)
R-0
R-0
EXT(N)_LLLB
R-0
R-0
R-0
R-0
R-0
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
x = Bit in unknown
7-5
EXT(N)_LLLB: Fractional portion of the Low Limit Temperature to be added to the value at the
respective high byte registers, where n = 1 to 3
111 = 0.875°C
110 = 0.750°C
101 = 0.625°C
100 = 0.500°C
011 = 0.375°C
010 = 0.250°C
001 = 0.125°C
000 = 0.000°C
4-0
Unimplemented: Read as ‘0’
REGISTER 5-14:
RW-0
SCRTCHPD(N): SCRATCHPAD REGISTER (ADDRESSES 11H AND 12H)
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
SPD(N)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
7-0
x = Bit in unknown
SPD(N): User temporary storage registers, where n = 1 to 2
REGISTER 5-15:
RW-0
ONE SHOT – ONE-SHOT TEMPERATURE CONVERSION INITIATION REGISTER
(ADDRESS 0FH)
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
ONSH
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
7-0
x = Bit in unknown
ONSH: When the device is in the Standby state, writing to the One-shot Register will initiate a
conversion cycle and update the temperature measurements. Writing to the One Shot Register while
the device is in the Active state or when the BUSY bit is set in the Status Register 02h will have no
effect.
DS20005382C-page 28
2015-2016 Microchip Technology Inc.
MCP9902/3/4
REGISTER 5-16:
RW-0
EXT(N) THRM LIM – EXTERNAL DIODE (N) THERM LIMIT REGISTER
(ADDRESSES 19H, 1AH AND 30H)
RW-1
RW-0
RW-1
RW-0
RW-1
RW-0
RW-1
EXT(N)_THL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
7-0
x = Bit in unknown
EXT(N)_THL: External Diode (n) THERM Limits, where n = 1 to 3
REGISTER 5-17:
RW-0
INTD THRM LIM – INTERNAL DIODE THERM LIMIT REGISTER (ADDRESS 20H)
RW-1
RW-0
RW-1
RW-0
RW-1
RW-0
RW-1
IDTHL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
7-0
x = Bit in unknown
IDTHL: Internal Diode THERM Limits
REGISTER 5-18:
RW-0
THRM HYS – THERM LIMIT HYSTERESIS REGISTER (ADDRESS 21H)
RW-0
RW-0
RW-0
RW-1
RW-0
RW-1
RW-0
THRMH
bit 7
bit 0
Legend:
R = Readable bit
W = Writeable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
7-0
x = Bit in unknown
THRMH: ITHERM Limit hysteresis
2015-2016 Microchip Technology Inc.
DS20005382C-page 29
MCP9902/3/4
REGISTER 5-19:
EXT FLT STS – EXTERNAL DIODE FAULT STATUS REGISTER (ADDRESS 1BH)
U-0
U-0
U-0
U-0
RC-0
RC-0
RC-0
U-0
—
—
—
—
E3FLT
E2FLT
E1FLT
—
bit 7
bit 0
Legend:
RC = Read-then-clear bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
x = Bit in unknown
7-4
Unimplemented: Read as ‘0’
3
E3FLT: This bit is set if the External Diode 3 channel reported a diode fault
1 = Diode Fault condition present
0 = No Diode Fault present
2
E2FLT: This bit is set if the External Diode 2 channel reported a diode fault
1 = Diode Fault condition present
0 = No Diode Fault present
1
E1FLT: This bit is set if the External Diode 2 channel reported a diode fault
1 = Diode Fault condition present
0 = No Diode Fault present
0
Unimplemented: Read as ‘0’
DS20005382C-page 30
2015-2016 Microchip Technology Inc.
MCP9902/3/4
REGISTER 5-20:
DIODE FAULT MASK – DIODE FAULT MASK REGISTER (ADDRESS 1FH)
U-0
U-0
U-0
U-0
RW-0
RW-0
RW-0
RW-0
—
—
—
—
E3MSK
E2MSK
E1MSK
INTMSK
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
x = Bit in unknown
7-4
Unimplemented: Read as ‘0’
3
E3MASK: Masks the ALERT/THERM2 pin from asserting when the External Diode 3 channel is out of
limit or reports a diode fault.
1 = The External Diode 3 channel will not cause the ALERT/THERM2 pin to be asserted if it is out of
limit or reports a diode fault.
0 = The External Diode 3 channel will cause the ALERT/THERM2 pin to be asserted if it is out of limit
or reports a diode fault.
2
E2MASK: Masks the ALERT/THERM2 pin from asserting when the External Diode 2 channel is out of
limit or reports a diode fault.
1 = The External Diode 2 channel will not cause the ALERT/THERM2 pin to be asserted if it is out of
limit or reports a diode fault.
0 = The External Diode 2 channel will cause the ALERT/THERM2 pin to be asserted if it is out of limit
or reports a diode fault.
1
E1MASK: Masks the ALERT/THERM2 pin from asserting when the External Diode 1 channel is out of
limit or reports a diode fault.
1 = The External Diode 1 channel will not cause the ALERT/THERM2 pin to be asserted if it is out of
limit or reports a diode fault.
0 = The External Diode 1 channel will cause the ALERT/THERM2 pin to be asserted if it is out of limit
or reports a diode fault.
0
INTMASK: Masks the ALERT/THERM2 pin from asserting when the Internal Diode temperature is out
of limit.
1 = The Internal Diode channel will not cause the ALERT/THERM2 pin to be asserted if it is out of
limit.
0 = The Internal Diode channel will cause the ALERT/THERM2 pin to be asserted if it is out of limit.
2015-2016 Microchip Technology Inc.
DS20005382C-page 31
MCP9902/3/4
REGISTER 5-21:
RW-0
CONSEC ALERT – CONSECUTIVE ALERT REGISTER (ADDRESS 22H)
RW-1
TMOUT
RW-1
CTHM
RW-1
RW-0
RW-0
RW-0
U-0
—
CALRT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
x = Bit in unknown
7
TMOUT: Enables the time-out and idle functionality of the I2C protocol
1 = The I2C time-out and idle functionality are enabled. The I2C interface will time-out if the clock line
is held low for longer than 30 ms. Likewise, it will reset if both the data and clock lines are held high for
longer than 200 µs.
0 = The I2C time-out and idle functionality are disabled. The I2C interface will not time-out if the clock
line is held low for longer than 30ms. Likewise, it will not reset if both the data and clock lines are held
high for longer than 200 µs. This is used for I2C compliance.
6-4
CTHM: Determines the number of consecutive measurements that must exceed the
corresponding Therm Limit before the THERM pin is asserted
000 = 1
001 = 2
011 = 3
111 = 4
3-1
CALRT: Determines the number of consecutive measurements that must exceed the
corresponding Therm Limit before the ALERT/THERM2 pin is asserted
000 = 1
001 = 2
011 = 3
111 = 4
0
Unimplemented: Read as ‘0’
DS20005382C-page 32
2015-2016 Microchip Technology Inc.
MCP9902/3/4
REGISTER 5-22:
EXT(N) BETA CFG – BETA COMPENSATION CONFIGURATION REGISTER
(ADDRESSES 25H AND 26H)
U-0
U-0
U-0
U-0
RW-1
—
—
—
—
ENBLx
RW-0
RW-0
RW-0
BETAx
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
7
x = Bit in unknown
Unimplemented: Read as ‘0’
6
Unimplemented: Read as ‘0’
5
Unimplemented: Read as ‘0’
4
Unimplemented: Read as ‘0’
3
ENBLx: Enables the Beta Compensation factor auto-detection function. X = 1 or 2, depending on the
device
1 = Auto-Beta detection for External Diode x is enabled
0 = Auto-Beta detection for External Diode x is disabled
2-0
BETAx: These bits always reflect the current beta configuration settings. If auto-detection
circuitry is enabled, these bits will be updated automatically and writing to these bits will have no
effect.
000 = 0.11
001 = 0.18
010 = 0.25
011 = 0.33
100 = 0.43
101 = 1.00
110 = 2.33
111 = disabled
REGISTER 5-23:
EXT (N) IDEALITY FACTOR – EXTERNAL DIODE N IDEALITY FACTOR
REGISTER (ADDRESSES 27H, 28H AND 31H)
U-0
U-0
—
—
RW-0
RW-1
RW-0
RW-0
RW-1
RW-0
IDEAL(n)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
x = Bit in unknown
7-6
Unimplemented: Read as ‘0’
5-0
IDEAL(n): External Diode n Ideality factor, where n = 1 to 3 depending on device
2015-2016 Microchip Technology Inc.
DS20005382C-page 33
MCP9902/3/4
REGISTER 5-24:
HI LIM STS – HIGH LIMIT STATUS REGISTER (ADDRESS 35H)
U-0
U-0
U-0
U-0
RC-0
RC-0
RC-0
RC-0
—
—
—
—
E3HIGH
E2HIGH
E1HIGH
IHIGH
bit 7
bit 0
Legend:
RC = Read-then-clear bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
x = Bit in unknown
7-4
Unimplemented: Read as ‘0’
3
E3HIGH: This bit is set when the External Diode 3 exceeds its programmed HIGH limit. Reading this
register will also clear the HIGH bit.
1 = High limit exceeded
0 = High limit not exceeded
2
E2HIGH: This bit is set when the External Diode 2 exceeds its programmed HIGH limit. Reading this
register will also clear the HIGH bit.
1 = High limit exceeded
0 = High limit not exceeded
1
E1HIGH: This bit is set when the External Diode 1 exceeds its programmed HIGH limit. Reading this
register will also clear the HIGH bit.
1 = High limit exceeded
0 = High limit not exceeded
0
IHIGH: This bit is set when the Internal Diode exceeds its programmed high limit. Reading this register
will also clear the HIGH bit.
1 = High limit exceeded
0 = High limit not exceeded
DS20005382C-page 34
2015-2016 Microchip Technology Inc.
MCP9902/3/4
REGISTER 5-25:
LO LIM STS – LOW LIMIT STATUS REGISTER (ADDRESS 36H)
U-0
U-0
U-0
U-0
RC-0
RC-0
RC-0
RC-0
—
—
—
—
E3LOW
E2LOW
E1LOW
ILOW
bit 7
bit 0
Legend:
RC = Read-then-clear bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
x = Bit in unknown
7-4
Unimplemented: Read as ‘0’
3
E3LOW: This bit is set when the External Diode 3 channel drops below its programmed low limit.
Reading from the register will also clear the LOW status bit in the Status Register.
1 = Low limit exceeded
0 = Low limit not exceeded
2
E2LOW: This bit is set when the External Diode 2 drops below its programmed low limit. Reading this
register will also clear the LOW bit.
1 = Low limit exceeded
0 = Low limit not exceeded
1
E1LOW: This bit is set when the External Diode 1 drops below its programmed low limit. Reading this
register will also clear the LOW bit.
1 = Low limit exceeded
0 = Low limit not exceeded
0
ILOW: This bit is set when the Internal Diode drops below its programmed low limit. Reading this
register will also clear the LOW bit.
1 = Low limit exceeded
0 = Low limit not exceeded
2015-2016 Microchip Technology Inc.
DS20005382C-page 35
MCP9902/3/4
REGISTER 5-26:
THRM LIM STS – HIGH LIMIT STATUS REGISTER (ADDRESS 37H)
U-0
U-0
U-0
U-0
RC-0
RC-0
RC-0
RC-0
—
—
—
—
E3THERM
E2THERM
E1THERM
ITHERM
bit 7
bit 0
Legend:
RC = Read-then-clear bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
x = Bit in unknown
7-4
Unimplemented: Read as ‘0’
3
E3THERM: This bit is set when the External Diode 3 channel exceeds its programmed Therm Limit.
When set, this bit will assert the THERM pin.
1 = THERM pin asserted
0 = THERM pin not asserted
2
E2THERM: This bit is set when the External Diode 2 channel exceeds its programmed Therm Limit.
When set, this bit will assert the THERM pin.
1 = THERM pin asserted
0 = THERM pin not asserted
1
E1THERM: This bit is set when the External Diode 1 channel exceeds its programmed Therm Limit.
When set, this bit will assert the THERM pin.
1 = THERM pin asserted
0 = THERM pin not asserted
0
ITHERM: This bit is set when the Internal Diode channel exceeds its programmed Therm Limit. When
set, this bit will assert the THERM pin.
1 = THERM pin asserted
0 = THERM pin not asserted
The Therm Limit Status Register contains the status
bits that are set when a temperature channel Therm
Limit is exceeded. If any of these bits are set, the
THERM status bit in the Status register is set. Reading
from the Therm Limit Status register will not clear the
status bits. Once the temperature drops below the
Therm Limit minus the Therm Hysteresis, the corresponding status bits will be automatically cleared. The
THERM bit in the Status register will be cleared when
all individual channel THERM bits are cleared.
REGISTER 5-27:
FLTR SEL: FILTER SELECTION REGISTER (ADDRESS 40H)
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
RC-0
RC-0
FLTER
bit 7
bit 0
Legend:
RC = Read-then-clear bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
x = Bit in unknown
7-2
Unimplemented: Read as ‘0’
1-0
FILTER: Control the level of digital filtering that is applied to the External Diode temperature measurement as shown in Table 4-6
DS20005382C-page 36
2015-2016 Microchip Technology Inc.
MCP9902/3/4
REGISTER 5-28:
PROD_ID – PRODUCT ID REGISTER (ADDRESS FDH)
R-0
R-1
R-1
R-0
R-0
R-0
R-0
R-0
—
—
—
—
—
EXT2_APD_EN
—
EXT2_EN
bit 7
bit 0
Legend:
RC = Read-then-clear bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
7
Hardwired as '0'
6-5
Hardwired as ‘1’
x = Bit in unknown
4-3
Hardwired as '0'
2
EXT2_APD_EN: Enables Channel 3 Anti-parallel diode
1 = APD2 is enabled for MCP9904
0 = APD2 is disabled for MCP9902 and MCP9903
1
Hardwired as ‘0’
0
EXT2_EN: Enable External Diode 2
1 = External Diode 2 channel active for MCP9903 and MCP9904
0 = External Diode 2 channel inactive for MCP9902
REGISTER 5-29:
R-0
MCHP_ID – MANUFACTURER ID REGISTER (ADDRESS FEH)
R-1
R-0
R-1
R-1
R-1
R-0
R-1
MCHP_ID
bit 7
bit 0
Legend:
RC = Read-then-clear bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
7-0
x = Bit in unknown
MCHP_ID: Unique manufacturer ID for Microchip
REGISTER 5-30:
R-0
REVISION – REVISION REGISTER (ADDRESS FFH)
R-0
R-0
R-1
R-0
R-0
R-0
R-0
REVISION
bit 7
bit 0
Legend:
RC = Read-then-clear bit
W = Writable bit
U = Unimplemented bit, read as 0
-n = Value at POR
‘1’ = bit is set
‘0’ = Bit is cleared
7-0
x = Bit in unknown
REVISION: DIE revision number
2015-2016 Microchip Technology Inc.
DS20005382C-page 37
MCP9902/3/4
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
8-Lead WDFN (2 x 2 x 0.9)
Example
Product Number
Code
MCP9902T-1E/RW
AAC
MCP9902T-2E/RW
AAD
MCP9902T-AE/RW
AAB
10-Lead VDFN (3 x 3 x 0.9)
Example
Product Number
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS20005382C-page 38
AAA
256
Code
MCP9903T-1E/9Q
9031
MCP9903T-2E/9Q
9032
MCP9903T-AE/9Q
903A
MCP9904T-1E/9Q
9041
MCP9904T-2E/9Q
9042
MCP9904T-AE/9Q
904A
9031
1506
256
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2015-2016 Microchip Technology Inc.
MCP9902/3/4
8-Lead Very, Very Thin Plastic Dual Flat, No Lead Package (RW) - 2x2 mm Body [WDFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
N
(DATUM A)
(DATUM B)
E
NOTE 1
2X
0.05 C
1
2X
2
TOP VIEW
0.05 C
0.05 C
C
(A3)
A
SEATING
PLANE
SIDE VIEW
A1
0.05 C
D2
2X CH
1
2
NOTE 1
0.05
C A B
E2
(K)
L
N
8X b
e
BOTTOM VIEW
0.10
0.05
C A B
C
Microchip Technology Drawing C04-261A Sheet 1 of 2
2015-2016 Microchip Technology Inc.
DS20005382C-page 39
MCP9902/3/4
8-Lead Very, Very Thin Plastic Dual Flat, No Lead Package (RW) - 2x2 mm Body [WDFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Terminals
N
e
Pitch
Overall Height
A
Standoff
A1
(A3)
Terminal Thickness
Overall Width
E
Exposed Pad Width
E2
Overall Length
D
Exposed Pad Length
D2
Exposed Pad Chamfer
CH
Terminal Width
b
Terminal Length
L
(K)
Terminal-to-Exposed-Pad
MIN
0.70
0.00
0.70
1.10
0.20
0.25
0.30
MILLIMETERS
NOM
8
0.50 BSC
0.75
0.02
0.10 REF
2.00 BSC
0.80
2.00 BSC
1.20
0.25
0.25
0.30
-
MAX
0.80
0.05
0.90
1.30
0.30
0.35
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-261A Sheet 2 of 2
DS20005382C-page 40
2015-2016 Microchip Technology Inc.
MCP9902/3/4
8-Lead Very, Very Thin Plastic Dual Flat, No Lead Package (RW) - 2x2 mm Body [WDFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C
2X CH
ØV
8
1
2
E
X2
X1
G
SILK SCREEN
(G2)
Y2
Y1
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Optional Center Pad Width
Y2
Optional Center Pad Length
X2
Contact Pad Spacing
C
Center Pad Chamfer
CH
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
Contact Pad to Contact Pad (X6)
G1
Contact Pad to Center Pad (X8)
G1
Thermal Via Diameter
V
MIN
MILLIMETERS
NOM
0.50 BSC
MAX
0.90
1.30
2.10
0.28
0.30
0.70
0.20
0.25 REF
0.30
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerances, for reference only.
Microchip Technology Drawing C04-2261A
2015-2016 Microchip Technology Inc.
DS20005382C-page 41
MCP9902/3/4
10-Lead Very Thin Plastic Dual Flat, No Lead Package (9Q) - 3x3 mm Body [VDFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
1
A
B
2
NOTE 1
E
(DATUM B)
(DATUM A)
2X
0.10 C
N
2X
TOP VIEW
0.10 C
0.10 C
A1
C
A
SEATING
PLANE
10X
(A3)
SIDE VIEW
0.05 C
D2
N
E2
NOTE 1
L
1
K
2
10X b
0.10
0.05
e
C A B
C
BOTTOM VIEW
Microchip Technology Drawing C04-206A Sheet 1 of 2
DS20005382C-page 42
2015-2016 Microchip Technology Inc.
MCP9902/3/4
10-Lead Very Thin Plastic Dual Flat, No Lead Package (9Q) - 3x3 mm Body [VDFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Terminals
N
e
Pitch
Overall Height
A
Standoff
A1
(A3)
Terminal Thickness
Overall Length
D
Exposed Pad Length
D2
Overall Width
E
Exposed Pad Width
E2
b
Terminal Width
Terminal Length
L
K
Terminal-to-Exposed-Pad
MIN
0.80
0.00
2.20
1.50
0.18
0.35
0.25
MILLIMETERS
NOM
10
0.50 BSC
0.85
0.02
0.20 REF
3.00 BSC
2.30
3.00 BSC
1.60
0.25
0.40
0.30
MAX
0.90
0.05
2.40
1.70
0.30
0.45
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-206A Sheet 2 of 2
2015-2016 Microchip Technology Inc.
DS20005382C-page 43
MCP9902/3/4
10-Lead Very Thin Plastic Dual Flat, No Lead Package (9Q) - 3x3 mm Body [VDFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C
2X CH
ØV
1
10
2
VX
X1
X2
E
G1
VY
SILK SCREEN
(G2)
Y2
Y1
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Optional Center Pad Width
Y2
Optional Center Pad Length
X2
Contact Pad Spacing
C
Center Pad Chamfer
CH
Contact Pad Width (X10)
X1
Contact Pad Length (X10)
Y1
Contact Pad to Contact Pad (X8)
G1
Contact Pad to Center Pad (X10)
G2
Thermal Via Diameter
V
Thermal Via Pitch
VX
Thermal Via Pitch
VY
MIN
MILLIMETERS
NOM
0.50 BSC
MAX
1.70
2.40
3.00
0.28
0.30
0.80
0.20
0.25 REF
0.30
1.00
1.00
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerances, for reference only.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-2206A
DS20005382C-page 44
2015-2016 Microchip Technology Inc.
MCP9902/3/4
APPENDIX A:
REVISION HISTORY
Revision C (July 2016)
• Updated Features section.
• Updated Temperature Accuracy parameters in
Table 1.2 "DC Characteristics".
Revision B (March 2016)
• Added MCP9903 and MCP9904 devices.
• Updated Section “Package Types” with
MCP9903 and MCP9904 devices.
• Updated Table 1.2 "DC Characteristics" and
Table 1.3 "Thermal Specifications".
• Updated Section 2.0 “Typical Operating
Curves”.
• Added pin description for MCP9903 and
MCP9904 devices in Section 3.0 “Pin
Descriptions”.
• Added information for MCP9903 and MCP9904
devices in Section 6.0 “Packaging
Information”.
• Added information for MCP9903 and MCP9904
devices in Section “Product Identification
System”.
Revision A (December 2015)
• Original release of this document.
2015-2016 Microchip Technology Inc.
DS20005382C-page 45
MCP9902/3/4
NOTES:
DS20005382C-page 46
2015-2016 Microchip Technology Inc.
MCP9902/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device
–X
X
/XX
SMBUS
Address
Temperature
Range
Package
X
PART NO.
Tape and Reel
Examples:
a)
b)
Device:
MCP9902:
MCP9903:
MCP9904:
Tape and Reel: T
High-Accuracy, Low-Cost, SMBus Temperature Sensor
High-Accuracy, Low-Cost, SMBus Temperature Sensor
High-Accuracy, Low-Cost, SMBus Temperature Sensor
c)
= Tape and Reel
a)
1
2
A
= 1001_100(r/w)
= 1000_101(r/w)
= Adjustable
Temperature
Range:
E
= -40°C to +125°C (Extended)
Package:
RW = 8-Lead Plastic Dual Flat, No Lead – 2x2x0.9 mm body
(WDFN)
9Q = 10-Lead Plastic Dual Flat, No Lead – 3x3x0.9 mm body
(VDFN)
SMBus
Address:
b)
a)
2015-2016 Microchip Technology Inc.
b)
MCP9902T-AE/RW:Tape and reel, Adjustable,
Extended temperature,
8L-WDFN package
MCP9902T-1E/RW:Tape and reel,
1001_100(r/w),
Extended temperature,
8L-WDFN package
MCP9902T-2E/RW:Tape and reel
1000_101(r/w),
Extended temperature,
8L-WDFN package
MCP9903T-2E/9Q:Tape and reel
1000_101(r/w),
Extended temperature,
10L-VDFN package
MCP9903T-AE/9Q:Tape and reel, Adjustable
Extended temperature,
10L-VDFN package
MCP9904T-1E/9Q:Tape and reel,
1001_100(r/w),
Extended temperature,
10L-VDFN package
MCP9904T-2E/9Q:Tape and reel,
1000_101(r/w),
Extended temperature,
10L-VDFN package
DS20005382C-page 47
MCP9902/3/4
NOTES:
DS20005382C-page 48
2015-2016 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,
KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,
MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,
RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O
are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
ETHERSYNCH, Hyper Speed Control, HyperLight Load,
IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,
BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,
EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,
Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2015-2016 Microchip Technology Inc.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2015-2016, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0746-1
DS20005382C-page 49
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06/23/16
DS20005382C-page 50
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