PolarFire® FPGA
Overview
This datasheet covers the electrical AC and DC specifications for four temperature grades of devices. AC and DC
electrical characteristics and parametric values, unless otherwise noted, apply to all temperature grade devices. For
example, worst-case STD speed grade applies to all temperature grade devices and –1 speed grade applies to
all temperature grade devices except Military. In addition, Low-Power (L) devices are equivalent in performance to
STD speed grade devices where offered. Users are expected to close timing using SmartTime for the speed and
temperate grade of the device chosen.
Table 1. PolarFire Minimum and Maximum Junction Temperatures by Temperature Grade
Temperature Grade
Minimum Junction Temperature
Maximum Junction Temperature
Extended Commercial (E)
0 °C
100 °C
Industrial (I)
–40 °C
100 °C
Automotive AECQ-100 (T2)
–40 °C
125 °C
Military (M)
–55 °C
125 °C
Table 2. PolarFire Speed Grade Options by Temperature Grade
Temperature Grade
Standard Speed Grade
–1 Speed Grade
Extended Commercial (E)
Available
Available
Industrial (I)
Available
Available
Automotive T2 (T2)
Available
Available
Military (M)
Available
Not Available
Table 3. PolarFire Package Ball Composition by Temperature Grade
Temperature Grade
Ball Material Composition Package Decoupling Capacitor Solder Paste (FC484,
FC784, FC1152)
Extended Commercial (E) RoHS
RoHS
Industrial (I)
RoHS
RoHS
Automotive T2 (T2)
RoHS
RoHS
Military (M)
Pb
Pb
PolarFire device programming functions (programming, verify, and digest check) are only allowed over the Industrial
temperature range regardless of the temperature grade of the device selected. Retention characteristics for each
temperature range explicitly describe the retention characteristics for that temperature-grade device. You cannot,
for example, use the retention characteristics at 110 °C and apply them to the Extended Commercial or Industrial
devices with a maximum TJ of 100 °C. Retention characteristics for Military-grade devices and Automotive-grade
devices at the absolute maximum junction temperature of 125 °C can be profiled using the PolarFire Retention
Calculator, which can be obtained by contacting technical support at www.microchip.com/support.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 1
Table of Contents
Overview........................................................................................................................................................ 1
1.
References..............................................................................................................................................3
2.
Device Offering........................................................................................................................................4
3.
Silicon and Libero Tool Status.................................................................................................................5
4.
DC Characteristics.................................................................................................................................. 7
4.1.
4.2.
4.3.
5.
AC Switching Characteristics................................................................................................................ 27
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
5.8.
5.9.
5.10.
5.11.
6.
Absolute Maximum Rating........................................................................................................... 7
Recommended Operating Conditions.......................................................................................... 8
Input and Output.........................................................................................................................17
I/O Standards Specifications...................................................................................................... 27
Clocking Specifications.............................................................................................................. 44
Fabric Specifications.................................................................................................................. 50
Transceiver Switching Characteristics........................................................................................53
Transceiver Protocol Characteristics..........................................................................................67
Non-Volatile Characteristics....................................................................................................... 75
System Services.........................................................................................................................84
Fabric Macros.............................................................................................................................85
Power-Up to Functional Timing.................................................................................................. 89
Dedicated Pins........................................................................................................................... 93
User Crypto................................................................................................................................ 96
Revision History.................................................................................................................................. 102
The Microchip Website...............................................................................................................................106
Product Change Notification Service..........................................................................................................106
Customer Support...................................................................................................................................... 106
Microchip Devices Code Protection Feature.............................................................................................. 106
Legal Notice............................................................................................................................................... 106
Trademarks................................................................................................................................................ 107
Quality Management System..................................................................................................................... 108
Worldwide Sales and Service.....................................................................................................................109
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 2
References
1.
References
The following documents are recommended references. For more information about PolarFire static and dynamic
power data, see the PolarFire Power Estimator Spreadsheet.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
PolarFire FPGA Product Overview
ER0217: PolarFire FPGA Pre-Production Device Errata
UG0722: PolarFire FPGA Packaging and Pin Descriptions User Guide
UG0726: PolarFire FPGA Board Design User Guide
PolarFire FPGA and PolarFire SoC FPGA User I/O User Guide
PolarFire FPGA and PolarFire SoC FPGA Fabric User Guide
PolarFire FPGA and PolarFire SoC FPGA Programming User Guide
PolarFire FPGA and PolarFire SoC FPGA Clocking Resources User Guide
UG0687: PolarFire FPGA 1G Ethernet Solutions User Guide
UG0727: PolarFire FPGA 10G Ethernet Solutions User Guide
UG0748: PolarFire FPGA Low Power User Guide
PolarFire FPGA and PolarFire SoC FPGA Memory Controller User Guide
UG0743: PolarFire FPGA Debugging User Guide
PolarFire FPGA and PolarFire SoC FPGA Power-Up and Resets User Guide
PolarFire FPGA and PolarFire SoC FPGA Transceiver User Guide
PolarFire FPGA and PolarFire SoC FPGA PCI Express User Guide
PolarFire FPGA and PolarFire SoC FPGA Security User Guide
UG0897: PolarFire and PolarFire SoC FPGA Power Estimator User Guide
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 3
Device Offering
2.
Device Offering
The following table lists the PolarFire FPGA device options using the MPF300T as an example. The MPF050T,
MPF100T, MPF200T, and MPF500T device densities have identical offerings.
Table 2-1. PolarFire FPGA Device Options
Device
Extended
Industrial
Options
Commercial
–40 °C–100 °C
STD
–1
Transceivers
Lower Static
Data
(T)
Power
Security
(L)
(S)
0 °C–100 °C
MPF300T
Yes
Yes
Yes
Yes
Yes
—
—
MPF300TL
Yes
Yes
Yes
—
Yes
Yes
—
MPF300TS
—
Yes
Yes
Yes
Yes
—
Yes
MPF300TLS
—
Yes
Yes
—
Yes
Yes
Yes
Table 2-2. Orderable Military (–55 °C TJ to 125 °C TJ) Device Part Numbers
STD Speed Grade
–1 Speed Grade
MPF200TS-FCS325M
N/A
MPF300TS-FC484M
N/A
MPF300TS-FCV484M
N/A
MPF300TS-FCS536M
N/A
MPF300TS-FC784M
N/A
MPF500TS-FC784M
N/A
MPF500TS-FC1152M
N/A
Table 2-3. Orderable Automotive (–40 °C TJ to 125 °C TJ) Device Part Numbers
STD Speed Grade
–1 Speed Grade
MPF100T-FCG484T2
MPF100T-1FCG484T2
MPF100T-FCVG484T2
MPF100T-1FCVG484T2
MPF100T-FCSG325T2
MPF100T-1FCSG325T2
MPF200T-FCG484T2
MPF200T-1FCG484T2
MPF200T-FCVG484T2
MPF200T-1FCVG484T2
MPF200T-FCSG325T2
MPF200T-1FCSG325T2
MPF200T-FCSG536T2
MPF200T-1FCSG536T2
MPF300T-FCVG484T2
MPF300T-1FCVG484T2
MPF300T-FCSG536T2
MPF300T-1FCSG536T2
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 4
Silicon and Libero Tool Status
3.
Silicon and Libero Tool Status
There are three status levels:
•
•
•
Advanced – Initial estimated information based on simulations.
Preliminary – Information based on simulation and/or initial characterization.
Production – Final production data.
The following tables list the status of the PolarFire FPGA silicon and Libero Timing and Power tool.
Table 3-1. PolarFire FPGA Silicon Status
Product
Silicon
MPF100T, TS, TL, TLS
Production – all temperature grades
MPF200T, TS, TL, TLS
Production – all temperature grades
MPF300T, TS, TL, TLS
Production – all temperature grades
MPF500T, TS, TL, TLS
Production – all temperature grades
Table 3-2. PolarFire FPGA Tool Status
Device
Status
Libero Version
Timing
Power
Extended
Commercial
Industrial
Extended
Commercial
Industrial
STD
–1
STD
–1
STD
–1
STD
–1
MPF050T,
TS, TL,
TLS
Preliminary VDD = 1.0V,
1.05V
2021.2
2021.2
2021.2
2021.2
2021.2
2021.2
2021.2
2021.2
MPF100T,
TS, TL,
TLS
Production VDD = 1.0V
12.1
12.1
12.1
12.1
12.1
12.1
12.1
12.1
Production VDD = 1.05V
12.2
12.2
12.2
12.2
12.2
12.2
12.2
12.2
MPF200T,
TS, TL,
TLS
Production VDD = 1.0V
12.1
12.1
12.1
12.1
12.1
12.1
12.1
12.1
Production VDD = 1.05V
12.2
12.2
12.2
12.2
12.2
12.2
12.2
12.2
MPF300T,
TS, TL,
TLS
Production VDD = 1.0V
12.1
12.0
12.1
12.1
12.1
12.1
12.1
12.1
Production VDD = 1.05V
12.2
12.2
12.2
12.2
12.2
12.2
12.2
12.2
MPF500T,
TS, TL,
TLS
Production VDD = 1.0V
12.2
12.2
12.2
12.2
12.2
12.2
12.2
12.2
Production VDD = 1.05V
12.2
12.2
12.2
12.2
12.2
12.2
12.2
12.2
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 5
Silicon and Libero Tool Status
Table 3-3. Military
Device
Status
MPF200TS
MPF300TS
MPF500TS
Libero Version
Timing
Power
Military
Military
STD
STD
Production VDD = 1.0V
12.5
12.5
Production VDD = 1.05V
12.5
12.5
Production VDD = 1.0V
12.3
12.3
Production VDD = 1.05V
12.5
12.5
Production VDD = 1.0V
12.5
12.5
Production VDD = 1.05V
12.5
12.5
Table 3-4. Automotive T2
Device
MPF100T
MPF200T
MPF300T
Status
Timing
Power
Automotive T2
Automotive T2
STD
–1
STD
–1
Production VDD = 1.0V
12.6
12.6
12.6
12.6
Production VDD = 1.05V
12.6
12.6
12.6
12.6
Production VDD = 1.0V
12.6
12.6
12.6
12.6
Production VDD = 1.05V
12.6
12.6
12.6
12.6
Production VDD = 1.0V
12.6
12.6
12.6
12.6
Production VDD = 1.05V
12.6
12.6
12.6
12.6
© 2021 Microchip Technology Inc.
and its subsidiaries
Libero Version
Datasheet
DS00003831B-page 6
DC Characteristics
4.
DC Characteristics
This section lists the DC characteristics of the PolarFire FPGA device.
4.1
Absolute Maximum Rating
The following table lists the absolute maximum ratings for PolarFire devices.
Table 4-1. Absolute Maximum Rating
Parameter
Symbol
Min
Max
Unit
FPGA core power supply
VDD
–0.5
1.13
V
Transceiver Tx and Rx lanes supply
VDDA
–0.5
1.13
V
Programming and HSIO receiver supply
VDD18
–0.5
2.0
V
FPGA core and FPGA PLL high-voltage supply
VDD25
–0.5
2.7
V
Transceiver PLL high-voltage supply
VDDA25
–0.5
2.7
V
Transceiver reference clock supply
VDD_XCVR_CLK
–0.5
3.6
V
Global VREF for transceiver reference clocks
XCVRVREF
–0.5
3.6
V
HSIO DC I/O supply2
VDDIx
–0.5
2.0
V
GPIO DC I/O supply2
VDDIx
–0.5
3.6
V
Dedicated I/O DC supply for JTAG and SPI
VDDI3
–0.5
3.6
V
GPIO auxiliary power supply for I/O bank x2
VDDAUXx
–0.5
3.6
V
Maximum DC input voltage on GPIO
VIN
–0.5
3.8
V
Maximum DC input voltage on HSIO
VIN
–0.5
2.2
V
Transceiver receiver absolute input voltage
Transceiver VIN
–0.5
1.26
V
Transceiver reference clock absolute input voltage
Transceiver REFCLK VIN
–0.5
3.6
V
Storage temperature (ambient)1
TSTG
–65
150
°C
Junction temperature1
TJ
–55
135
°C
Maximum soldering temperature RoHS
TSOLROHS
—
260
°C
1.
2.
3.
See Table 5-61. FPGA and μPROM Programming Cycles vs. Retention Characteristics for retention time vs.
temperature. The total time used in calculating the device retention includes the device operating temperature
time and temperature during storage time.
The power supplies for a given I/O bank x are shown as VDDIx and VDDAUXx.
Absolute maximum ratings are stress ratings only; functional operation of the device at these or any
other conditions beyond those listed under the recommended operating conditions specified in Table 4-2.
Recommended Operating Conditions is not implied. Stresses beyond those listed in the following table might
cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 7
DC Characteristics
4.2
Recommended Operating Conditions
The following table lists the recommended operating conditions.
Table 4-2. Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit Condition
FPGA core supply at 1.0V
mode1, 6
VDD
0.97
1.00
1.03
V
—
FPGA core supply at 1.05V
mode1, 6
VDD
1.02
1.05
1.08
V
—
Transceiver Tx and Rx lanes
supply (1.0V mode)6, 7
VDDA
0.97
1.00
1.03
V
When all lane rates are
10.3125 Gbps or less.1
Transceiver Tx and Rx lanes
supply (1.05V mode)6
VDDA
1.02
1.05
1.08
V
Must when any lane
rate is greater than
10.3125 Gbps. Lane
rates 10.3125 Gbps or
less may also be powered
in 1.05V mode.1
Programming and HSIO
receiver supply6
VDD18
1.71
1.80
1.89
V
—
FPGA core and FPGA PLL
high-voltage supply6
VDD25
2.425
2.50
2.575
V
—
Transceiver PLL high-voltage
supply6
VDDA25
2.425
2.50
2.575
V
—
Transceiver reference clock
supply6, 7
VDD_XCVR_CLK 3.135
3.3
3.465
V
3.3V nominal
2.375
2.5
2.625
V
2.5V nominal
Global VREF for transceiver
reference clocks3
XCVRVREF
Ground —
HSIO DC I/O supply6
VDDIx
1.14
Various 1.89
V
Allowed nominal options:
1.2V, 1.35V, 1.5V, and
1.8V4, 5
GPIO DC I/O supply6
VDDIx
1.14
Various 3.465
V
Allowed nominal options:
1.2V, 1.5V, 1.8V, 2.5V,
and 3.3V2, 4, 5
Dedicated I/O DC supply for
JTAG and SPI (GPIO Bank 3)6
VDDI3
1.71
Various 3.465
V
Allowed nominal options:
1.8V, 2.5V, and 3.3V
GPIO auxiliary supply6
VDDAUXx
3.135
3.3
3.465
V
For I/O bank x with VDDIx
= 3.3V nominal2, 4, 5
2.375
2.5
2.625
V
For I/O bank x with VDDIx
= 2.5V nominal or lower2,
VDD_XCVR_ CLK V
—
4, 5
Extended commercial
temperature range
© 2021 Microchip Technology Inc.
and its subsidiaries
TJ
0
—
Datasheet
100
°C
—
DS00003831B-page 8
DC Characteristics
...........continued
Parameter
Symbol
Min
Typ
Max
Unit Condition
Industrial temperature range
TJ
–40
—
100
°C
—
Automotive T2 temperature
range
TJ
–40
—
125
°C
—
Military temperature range
TJ
–55
—
125
°C
—
Extended commercial
programming temperature
range
TPRG
0
—
100
°C
—
Industrial programming
temperature range
TPRG
–40
—
100
°C
—
1.
2.
3.
4.
5.
6.
7.
4.2.1
VDD and VDDA can independently operate at 1.0V or 1.05V nominal. These supplies are not dynamically
adjustable.
For GPIO buffers where I/O bank is designated as bank number, if VDDIx is 2.5V nominal or 3.3V nominal,
VDDAUXx must be connected to the VDDIx supply for that bank. If VDDIx for a given GPIO bank is 50K
—
Ω
1.
Measured at VCM = 1.2V and VID = 350 mV.
Note: All pull-ups are disabled at power-up to allow hot plug capability.
The following tables describe the PolarFire transceiver user interface clocks.
Note: Until specified, all modes are non-deterministic. For more information, see UG0677: PolarFire FPGA
Transceiver User Guide.
–STD speed grade is offered for Extended Commercial (E), Industrial (I), Military (M), and Automotive (T2)
temperature grades.
–1 speed grade is offered for Extended Commercial (E), Industrial (I), and Automotive (T2) temperature grades only.
Table 5-32. Transceiver TX_CLK Range (Nondeterministic PCS Mode with Global or Regional Fabric Clocks)
Mode
STD Min STD Max
–1 Min –1 Max Unit
8-bit, max data rate = 1.6 Gbps
—
200
—
200
MHz
10-bit, max data rate = 1.6 Gbps
—
160
—
160
MHz
16-bit, max data rate = 4.8 Gbps
—
300
—
300
MHz
20-bit, max data rate = 6.0 Gbps
—
300
—
300
MHz
32-bit, max data rate = 10.3125 Gbps (–STD) / 12.7 Gbps (–1)1
—
325
—
325
MHz
40-bit, max data rate = 10.3125 Gbps (–STD) / 12.7 Gbps (–1)1
—
260
—
320
MHz
64-bit, max data rate = 10.3125 Gbps (–STD) / 12.7 Gbps (–1)1
—
165
—
200
MHz
80-bit, max data rate = 10.3125 Gbps (–STD) / 12.7 Gbps (–1)1
—
130
—
160
MHz
Fabric pipe mode 32-bit, max data rate = 6.0 Gbps
—
150
—
150
MHz
1.
For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05V mode. See supply tolerance in the
section Recommended Operating Conditions.
–STD speed grade is offered for Extended Commercial (E), Industrial (I), Military (M), and Automotive (T2)
temperature grades.
–1 speed grade is offered for Extended Commercial (E), Industrial (I), and Automotive (T2) temperature grades only.
Table 5-33. Transceiver RX_CLK Range (Non-Deterministic PCS Mode with Global or Regional Fabric Clocks)
Mode
STD Min STD Max
–1 Min –1 Max Unit
8-bit, max data rate = 1.6 Gbps
—
200
—
200
MHz
10-bit, max data rate = 1.6 Gbps
—
160
—
160
MHz
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 57
AC Switching Characteristics
...........continued
Mode
STD Min STD Max
–1 Min –1 Max Unit
16-bit, max data rate = 4.8 Gbps
—
300
—
300
MHz
20-bit, max data rate = 6.0 Gbps
—
300
—
300
MHz
32-bit, max data rate = 10.3125 Gbps
—
325
—
325
MHz
40-bit, max data rate = 10.3125 Gbps (–STD) / 12.7 Gbps (–1)1
—
260
—
320
MHz
64-bit, max data rate = 10.3125 Gbps (–STD) / 12.7 Gbps (–1)1
—
165
—
200
MHz
80-bit, max data rate = 10.3125 Gbps (–STD) / 12.7 Gbps (–1)1
—
130
—
160
MHz
Fabric pipe mode 32-bit, max data rate = 6.0 Gbps
—
150
—
150
MHz
1.
For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05V mode. See supply tolerance in the
section Recommended Operating Conditions.
–STD speed grade is offered for Extended Commercial (E), Industrial (I), Military (M), and Automotive (T2)
temperature grades.
–1 speed grade is offered for Extended Commercial (E), Industrial (I), and Automotive (T2) temperature grades only.
Table 5-34. Transceiver TX_CLK Range (Deterministic PCS Mode with Regional Fabric Clocks)
Mode
STD Min STD Max
–1 Min –1 Max Unit
8-bit, max data rate = 1.6 Gbps
—
200
—
200
MHz
10-bit, max data rate = 1.6 Gbps
—
160
—
160
MHz
16-bit, max data rate = 3.6 Gbps (–STD) / 4.25 Gbps (–1)
—
225
—
266
MHz
20-bit, max data rate = 4.5 Gbps (–STD) / 5.32 Gbps (–1)
—
225
—
266
MHz
32-bit, max data rate = 7.2 Gbps (–STD) / 8.5 Gbps (–1)
—
225
—
266
MHz
40-bit, max data rate = 9.0 Gbps (–STD) / 10.6 Gbps (–1)1
—
225
—
266
Mhz
64-bit, max data rate = 10.3125 Gbps (–STD) / 12.7 Gbps (–1)1
—
165
—
200
MHz
80-bit, max data rate = 10.3125 Gbps (–STD) / 12.7 Gbps (–1)1
—
130
—
160
MHz
1.
For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05V mode. See supply tolerance in the
section Recommended Operating Conditions.
–STD speed grade is offered for Extended Commercial (E), Industrial (I), Military (M), and Automotive (T2)
temperature grades.
–1 speed grade is offered for Extended Commercial (E), Industrial (I), and Automotive (T2) temperature grades only.
Table 5-35. Transceiver RX_CLK Range (Deterministic PCS Mode with Regional Fabric Clocks)
Mode
STD Min STD Max
–1 Min –1 Max Unit
8-bit, max data rate = 1.6 Gbps
—
200
—
200
MHz
10-bit, max data rate = 1.6 Gbps
—
160
—
160
MHz
16-bit, max data rate = 3.6 Gbps (–STD) / 4.25 Gbps (–1)
—
225
—
266
MHz
20-bit, max data rate = 4.5 Gbps (–STD) / 5.32 Gbps (–1)
—
225
—
266
MHz
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 58
AC Switching Characteristics
...........continued
Mode
STD Min STD Max
–1 Min –1 Max Unit
32-bit, max data rate = 7.2 Gbps (–STD) / 8.5 Gbps (–1)
—
225
—
266
MHz
40-bit, max data rate = 9.0 Gbps (–STD) / 10.6 Gbps (–1)1
—
225
—
266
MHz
64-bit, max data rate = 10.3125 Gbps (–STD) / 12.7 Gbps (–1)1
—
165
—
200
MHz
80-bit, max data rate = 10.3125 Gbps (–STD) / 12.7 Gbps (–1)1
—
130
—
160
MHz
1.
For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05V mode. See supply tolerance in the
section Recommended Operating Conditions.
Table 5-36. PolarFire Transceiver Transmitter Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Condition
Differential termination
VOTERM
68
85
102
Ω
85Ω setting
VOTERM
80
100
120
Ω
100Ω setting
VOTERM
120
150
180
Ω
150Ω setting
VOCM
0.44 ×
VDDA
0.525 ×
VDDA
0.59 × VDDA V
DC coupled 50% setting
VOCM
0.52 ×
VDDA
0.6 ×
VDDA
0.66 × VDDA V
DC coupled 60% setting
VOCM
0.61 ×
VDDA
0.7 ×
VDDA
0.75 × VDDA V
DC coupled 70% setting
VOCM
0.63 ×
VDDA
0.8 ×
VDDA
0.83 × VDDA V
DC coupled 80% setting
TTxRF
40
—
61
ps
20% to 80%
39
—
58
ps
80% to 20%
VODPP
1080
1140
1320
mV
1000 mV setting
VODPP
1010
1060
1220
mV
800 mV setting
VODPP
550
580
670
mV
500 mV setting
VODPP
465
490
560
mV
400 mV setting
VODPP
350
370
425
mV
300 mV setting
VODPP
250
260
300
mV
200 mV setting
VODPP
150
160
185
mV
100 mV setting
TOSKEW
—
8
15
ps
—
Common mode
voltage1
Rise time2 Fall time2
Differential peak-topeak amplitude
Transmit lane P to N
skew3
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 59
AC Switching Characteristics
...........continued
Parameter
Symbol
Min
Typ
Max
Unit
Condition
Lane to lane transmit
skew4
TLLSKEW
—
—
75
ps
Single PLL, 2–4 bonded
lanes, 8–40-bit fabric
width10
—
—
8
UI
Single PLL, 2–4 bonded
lanes, 64–80-bit fabric
width11
—
—
8 + Refclk
skew
UI
Multiple PLL, 2–4 bonded
lanes, 8–40-bit fabric
width11, 12
—
—
32 + Refclk
skew
UI
Multiple PLL, 2–4 bonded
lanes, 64–80-bit fabric
width11, 12
Electrical idle transition TTxEITrEntry —
entry time7
—
20
ns
—
Electrical idle transition TTxEITrExit
exit time7
—
—
19
ns
—
Electrical idle
amplitude
VTxEIpp
—
—
7
mV
—
TXPLL lock time
TTXLock
—
—
1600
PFD cycles
—
Digital PLL lock time8
TDPLLLock
—
—
75,000
REFCLK
UIs
Frequency lock
—
—
150,000
REFCLK
UIs
Phase lock
—
—
0.22
UI
0.1
UI
Data rate ≥10.3125 Gbps
to 12.7 Gbps9 (Tx VCO
rate 5.16 GHz to 6.35
GHz)
Total jitter5, 6, 13
Deterministic jitter5, 6
TJ
TDJ
TxPLL in integer mode
Total jitter5, 6, 13
Deterministic jitter5, 6
TJ
—
—
TDJ
0.28
UI
0.1
UI
Data rate ≥10.3125 to
12.7 Gbps9 (Tx VCO rate
5.16 GHz to 6.35 GHz)
TxPLL in fractional mode
Total jitter5, 6, 13
Deterministic jitter5, 6
TJ
—
—
TDJ
0.22
UI
0.09
UI
Data rate ≥8.5 Gbps to
10.3125 Gbps (Tx VCO
rate 4.25 GHz to 5.16
GHz)
TxPLL in integer mode
Total jitter5, 6, 13
Deterministic jitter5, 6
TJ
TDJ
—
—
0.28
UI
0.09
UI
Data rate ≥8.5 Gbps to
10.3125 Gbps (Tx VCO
rate 4.25 GHz to 5.16
GHz)
TxPLL in fractional mode
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 60
AC Switching Characteristics
...........continued
Parameter
Symbol
Min
Typ
Max
Unit
Condition
Total jitter5, 6, 13
Deterministic jitter5,6
TJ
—
—
0.21
UI
0.09
UI
Data rate ≥5.0 Gbps to
8.5 Gbps (Tx VCO rate 2.5
GHz to 4.25 GHz)
TDJ
TxPLL in integer mode
Total jitter5, 6, 13
Deterministic jitter5, 6
TJ
—
—
TDJ
0.25
UI
0.09
UI
Data rate ≥5.0 Gbps to
8.5 Gbps (Tx VCO rate 2.5
GHz to 4.25 GHz)
TxPLL in fractional mode
Total jitter5, 6, 13
Deterministic jitter5, 6
TJ
—
—
TDJ
0.17
UI
0.03
UI
Data rate ≥1.6 Gbps to
5.0 Gbps (Tx VCO rate 1.6
GHz to 2.5 GHz)
TxPLL in integer mode
Total jitter5, 6, 13
Deterministic jitter5, 6
TJ
—
—
TDJ
0.2
UI
0.03
UI
Data rate ≥1.6 Gbps to
5.0 Gbps (Tx VCO rate 1.6
GHz to 2.5 GHz)
TxPLL in fractional mode
Total jitter5, 6, 13
Deterministic jitter5, 6
TJ
—
—
TDJ
0.08
UI
0.02
UI
Data rate ≥ 800 Mbps to
1.6 Gbps (Tx VCO rate 1.6
GHz)
TxPLL in integer mode
Total jitter5, 6, 13
Deterministic jitter5, 6
TJ
—
—
TDJ
0.11
UI
0.02
UI
Data rate ≥ 800 Mbps to
1.6 Gbps (Tx VCO rate 1.6
GHz)
TxPLL in fractional mode
Total jitter5, 6, 13
Deterministic jitter5, 6
TJ
—
—
TDJ
0.05
UI
0.01
UI
Data rate = 250 Mbps to
800 Mbps (Tx VCO rate
1.48 GHz to 1.6 GHz)
TxPLL in integer mode
Total jitter5, 6, 13
Deterministic jitter5, 6
TJ
TDJ
—
—
0.06
UI
0.01
UI
Data rate = 250 Mbps to
800 Mbps (Tx VCO rate
1.48 GHz to 1.6 GHz)
TxPLL in fractional mode
1.
2.
3.
4.
5.
6.
7.
8.
Increased DC Common mode settings above 50% reduce allowed VOD output swing capabilities.
Adjustable through transmit emphasis.
With estimated package differences.
Single PLL applies to all four lanes in the same quad location with the same TxPLL. Multiple PLL applies to N
lanes using multiple TxPLLs from different quad locations.
Improved jitter characteristics for a specific industry standard are possible in many cases due to improved
reference clock or higher VCO rate used.
Tx jitter is specified with all transmitters on the device enabled, a 10–12-bit error rate (BER) and Tx data pattern
of PRBS7.
From the PMA mode, the TX_ELEC_IDLE port to the XVCR TXP/N pins.
FTxRefClk = 75 MHz with typical settings.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 61
AC Switching Characteristics
9.
10.
11.
12.
13.
14.
For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05V mode. See supply tolerance in the
section Recommended Operating Conditions.
Transmit alignment in this case will automatically align upon the Tx PLL obtaining lock. For details on transmit
alignment, see UG0677: PolarFire FPGA Transceiver User Guide.
In order to obtain the required alignment for these configurations, an FPGA fabric Tx alignment circuit must be
implemented. For details on transmit alignment, see UG0677: PolarFire FPGA Transceiver User Guide.
Refclk skew is the amount of skew between the reference clocks of the two PLL.
Jitter decomposition can be found in the protocol characterization reports.
Tx total jitter (Tj) is quoted for reference clock rise and fall times as specified in Table 5-30. PolarFire
Transceiver Reference Clock AC Requirements. If increased Tj is acceptable, the maximum reference clock
input rise/fall times may be increased beyond the maximum specification shown in Table 5-30. PolarFire
Transceiver Reference Clock AC Requirements when using single-ended configurations (LVCMOS and
LVTTL)
a.
b.
c.
5.4.5
Tj increases by 8% for 0.5 ns < TRISE/TFALL ≤ 2.0 ns
Tj increases by 25% for 2.0 ns < TRISE/TFALL ≤ 5.0 ns
Tj increases by 35% for 0.5 ns < TRISE/TFALL ≤ 5.0 ns
Receiver Performance
The following table describes performance of the receiver.
Table 5-37. PolarFire Transceiver Receiver Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Condition
Input voltage
range
VIN
0
—
VDDA + 0.3
V
—
Differential
peak-to-peak
amplitude
VIDPP
140
—
1250
mV
—
Differential
termination
VITERM
68
85
102
Ω
85Ω setting
80
100
120
Ω
100Ω setting
120
150
180
Ω
150Ω setting
Common
mode voltage
VICMDC 1
0.7 × VDDA
—
0.9 × VDDA
V
DC coupled
Exit electrical
idle detection
time
TEIDET
—
50
100
ns
—
Run length of
consecutive
identical digits
(CID)
CID
—
—
200
UI
—
CDR PPM
tolerance2
CDRPPM
—
—
1.17
%UI
—
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 62
AC Switching Characteristics
...........continued
Parameter
Symbol
Min
Typ
Max
Unit
Condition
CDR lock-todata time13
TLTD
512 *
CDRREFDIV
—
1024 *
CDRREFDIV
CDRREFCLK
cycles
Disabled:
Enhanced
Receiver
Management
14
(1900/TCDRREF —
+ (512 + (1020
*
(WXCVRFABRX/
CDRFBDIV)) *
CDRREFDIV)
(5200/TCDRREF —
+ (1024 +
(6380 *
(WXCVRFABRX/
CDRFBDIV)) *
CDRREFDIV)
Enabled:
Enhanced
Receiver
Management
14
CDR lock-toref time13
TLTF
(1000/
TCDRREF) +
(1024 *
CDRREFDIV)
—
(13000/
TCDRREF) +
(1536 *
CDRREFDIV)
CDRREFCLK
cycles
—
High-gain lock
time
THGLT
10.8
—
—
ns
For Burst
Mode Receiver
(BMR)
High-gain
state time12
THGSTATE
—
—
3264
ns
For Burst
Mode Receiver
(BMR)
Loss-of-signal
detect (peak
detect range
setting=
high)9,10
VDETHIGH
145
—
295
mV
Setting = 3
155
—
340
mV
Setting = 4
180
—
365
mV
Setting = 5
195
—
375
mV
Setting = 6
210
—
385
mV
Setting = 7
65
—
175
mV
Setting =
PCIe3, 7
95
—
190
mV
Setting =
SATA4, 8
75
—
170
mV
Setting = 1
95
—
185
mV
Setting = 2
100
—
190
mV
Setting = 3
140
—
210
mV
Setting = 4
155
—
240
mV
Setting = 5
165
—
245
mV
Setting = 6
170
—
250
mV
Setting = 7
Loss-of-signal
detect (peak
detect range
setting=
VDETLOW
low)9,10
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 63
AC Switching Characteristics
...........continued
Parameter
Symbol
Min
Typ
Max
Unit
Condition
Sinusoidal
jitter tolerance
TSJTOL
0.34
—
—
UI
>8.5 Gbps –
12.7 Gbps5, 11
0.43
—
—
UI
>8.0–8.5
Gbps5
0.45
—
—
UI
>3.2–8.0
Gbps5
0.45
—
—
UI
>1.6 to 3.2
Gbps5
0.42
—
—
UI
>0.8 to 1.6
Gbps5
0.41
—
—
UI
250 to 800
Mbps5
0.65
—
—
UI
3.125 Gbps5
0.65
—
—
UI
6.25 Gbps6
0.7
—
—
UI
10.3125 Gbps6
0.7
—
—
UI
12.7 Gbps6, 11
0.1
—
—
UI
3.125 Gbps5
0.05
—
—
UI
6.25 Gbps6
0.05
—
—
UI
10.3125 Gbps6
0.05
—
—
UI
12.7 Gbps6, 11
CTLE DC gain —
(all stages,
max settings)
0.1
—
10
dB
—
CTLE AC gain —
(all stages,
max settings)
0.05
—
16
dB
—
DFE AC gain
(per 5 stages,
max settings)
—
0.05
—
7.5
dB
—
Auto adaptive
calibration
time (CTLE)
TCTLE
12
—
45
ms
—
Auto adaptive
calibration
time
(CTLE+DFE)
TCTLE+DFE
—
1.4
—
s
—
Total jitter
tolerance with
stressed eye
Sinusoidal
jitter tolerance
with stressed
eye
TTJTOLSE
TSJTOLSE
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 64
AC Switching Characteristics
...........continued
Parameter
Symbol
Min
Typ
Max
Unit
Condition
Enhanced
receiver
management
control clock
input
(CTRL_CLK)
FERMCTRLCLK
38.4
40
41.6
MHz
—
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Valid at 3.2 Gbps and below.
Data vs Rx reference clock frequency.
Achieves compliance with PCIe electrical idle detection.
Achieves compliance with SATA OOB specification.
Rx jitter values based on bit error ratio (BER) of 10–12, AC-coupled input with 400 mV VID, all stages of Rx
CTLE enabled, DFE disabled, 80 MHz sinusoidal jitter injected to Rx data.
Rx jitter values based on bit error ratio (BER) of 10–12, AC-coupled input with 400 mV VID, all stages of Rx
CTLE enabled, DFE enabled, 80 MHz sinusoidal jitter injected to Rx data.
For PCIe: Low Threshold Setting = 0, High Threshold Setting = 2.
For SATA: Low Threshold Setting = 2, High Threshold Setting = 3.
Loss of signal is valid for data rates of 1 Gbps to 5 Gbps for PRBS7 (8B/10B) or PRBS31 (64b/6xb) data
formats. It is also valid for detection of SATA out-of-band signals at data rates up to 6 Gbps. If the default
settings for the low threshold (0x0) and high threshold (0x2) using the low range option for the peak detector
are used, then the Rx VAmplitude pk-pk (outside of data eye) at the receiver input package pins must be a
minimum of 300 mV for short reach (6.5 dB insertion loss at 5 GHz) applications, 350 mV for medium reach
(17.0 dB insertion loss at 5 GHz) applications, and 450 mV for long reach (25.0 dB insertion loss at 5 GHz)
applications—generally the settings are less limiting than what is required for good BER operation of the
SerDes. Note that if the option to force CDR Lock2Ref upon Rx Idle is set (default at data rates of 5 Gbps and
below), this minimum VAmplitude pk-pk must be enforced for proper CDR operation.
Detect values measured at 1.5 Gbps with PRBS7 data pattern.
For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05V mode. See supply tolerance in the
section Recommended Operating Conditions.
THGSTATE is based on the condition where the CDR was in lock (to reference or data) for at least 5.2 μs before
moving to the high-gain state. At this point, if the receive data is outside the ppm tolerance of the CDR, the
CDR will unlock after the time specified by the parameter.
The following definitions apply:
a. TCDRREF is the transceiver CDR reference clock period in nanoseconds.
b. WXCVRFABRX is the parallel interface width of the transceiver receive fabric interface.
c. CDRFBDIV is the feedback divider of the transceiver.
d. CDRCDRREFDIV is the reference divider of the transceiver CDR.
14. For details on the Enhanced Receiver Management feature, refer to the PolarFire FPGA and PolarFire SoC
FPGA Transceiver User Guide.
5.4.6
Transceiver and Receiver Return Loss Characteristics
This section describes transmitter and receiver return loss characteristics compliant with OIF-CEI-03.1.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 65
AC Switching Characteristics
Figure 5-4. Differential Return Loss
Table 5-38. Differential Return Loss
Parameter
Value
Unit
A0
–8
dB
f0
100
MHz
f1
(3/4) * T_Baud
Hz
f2
T_Baud
Hz
Slope
16.6
dB/dec
Figure 5-5. Common Mode Return Loss
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 66
AC Switching Characteristics
Table 5-39. Common Mode Return Loss
5.5
Parameter
Value
Unit
A0
–6
dB
f0
100
MHz
f1
(3/4) * T_Baud
Hz
Transceiver Protocol Characteristics
The following section describes transceiver protocol characteristics.
5.5.1
PCI Express
The following tables describe the PCI express.
Table 5-40. PCI Express Gen1
Parameter
Data Rate
Min
Max
Unit
Total transmit jitter
2.5 Gbps
—
0.25
UI
Receiver jitter tolerance
2.5 Gbps
0.4
—
UI
Note: With add-in card, as specified in PCI Express CEM Rev 2.0.
Table 5-41. PCI Express Gen2
Parameter
Data Rate
Min
Max
Unit
Total transmit jitter
5.0 Gbps
—
0.35
UI
Receiver jitter tolerance
5.0 Gbps
0.4
—
UI
Note: With add-in card as specified in PCI Express CEM Rev 2.0.
5.5.2
Interlaken
The following table describes Interlaken.
Table 5-42. Interlaken
Parameter
Data Rate
Min
Max
Unit
Total transmit jitter
6.375 Gbps
—
0.3
UI
10.3125 Gbps
—
0.3
UI
12.7 Gbps1, 2
—
0.3
UI
6.375 Gbps
0.6
—
UI
10.3125 Gbps
0.65
—
UI
12.7 Gbps1, 2
0.65
—
UI
Receiver jitter tolerance
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 67
AC Switching Characteristics
1.
2.
5.5.3
For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05V mode. See supply tolerance in the
section Recommended Operating Conditions.
Supported on –1 speed grade only.
10GbE (10GBASE-R and 10GBASE-KR)
The following table describes 10GbE (10GBASE-R).
Table 5-43. 10GbE (10GBASE-R)
Parameter
Data Rate
Min
Max
Unit
Total transmit jitter
10.3125 Gbps
—
0.28
UI
Receiver jitter tolerance
10.3125 Gbps
0.7
—
UI
The following table describes 10GbE (10GBASE-KR).
Table 5-44. 10GbE (10GBASE-KR)
Parameter
Data Rate
Min
Max
Unit
Total transmit jitter
10.3125 Gbps
—
0.28
UI
Receiver jitter tolerance (SJ)
10.3125 Gbps
0.115
—
UI
Receiver jitter tolerance (RJ)
10.3125 Gbps
0.13
—
UI
Receiver jitter tolerance (DCD)
10.3125 Gbps
0.035
—
UI
The following table describes 10GbE (XAUI).
Table 5-45. 10GbE (XAUI)
Parameter
Data Rate
Min
Max
Unit
Total transmit jitter (near end)
3.125 Gbps
—
0.35
UI
Total transmit jitter (far end)
—
—
0.55
UI
Receiver jitter tolerance
3.125 Gbps
0.65
—
UI
The following table describes 10GbE (RXAUI).
Table 5-46. 10GbE (RXAUI)
5.5.4
Parameter
Data Rate
Min
Max
Unit
Total transmit jitter (near-end)
6.25 Gbps
—
0.35
UI
Total transmit jitter (far-end)
6.25 Gbps
—
0.55
UI
Receiver jitter tolerance
6.25 Gbps
0.65
—
UI
1GbE (1000BASE-X)
The following table describes 1GbE (1000BASE-X).
Table 5-47. 1GbE (1000BASE-X)
Parameter
Data Rate
Min
Max
Unit
Total transmit jitter
1.25 Gbps
—
0.24
UI
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 68
AC Switching Characteristics
...........continued
5.5.5
Parameter
Data Rate
Min
Max
Unit
Receiver jitter tolerance
1.25 Gbps
0.749
—
UI
Parameter
Data Rate
Min
Max
Unit
Total transmit jitter
1.25 Gbps
—
0.24
UI
Receiver jitter tolerance
1.25 Gbps
0.749
—
UI
SGMII and QSGMII
The following table describes SGMII.
Table 5-48. SGMII
The following table describes QSGMII.
Table 5-49. QSGMII
5.5.6
Parameter
Data Rate
Min
Max
Unit
Total transmit jitter
5.0 Gbps
—
0.3
UI
Receiver jitter tolerance
5.0 Gbps
0.65
—
UI
CPRI
The following table describes CPRI.
Table 5-50. CPRI
Parameter
Data Rate
Min
Max
Unit
Total transmit jitter
0.6144 Gbps
—
0.35
UI
1.2288 Gbps
—
0.35
UI
2.4576 Gbps
—
0.35
UI
3.0720 Gbps
—
0.35
UI
4.9152 Gbps
—
0.3
UI
6.1440 Gbps
—
0.3
UI
8.11008 Gbps
—
0.335
UI
9.8304 Gbps
—
0.335
UI
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 69
AC Switching Characteristics
...........continued
5.5.7
Parameter
Data Rate
Min
Max
Unit
Receive jitter tolerance
0.6144 Gbps
0.75
—
UI
1.2288 Gbps
0.75
—
UI
2.4576 Gbps
0.75
—
UI
3.0720 Gbps
0.75
—
UI
4.9152 Gbps
0.7
—
UI
6.1440 Gbps
0.7
—
UI
8.11008 Gbps
0.7
—
UI
9.8304 Gbps
0.7
—
UI
JESD204B
The following table describes JESD204B.
Table 5-51. JESD204B
Parameter
Data Rate
Min
Max
Unit
Total transmit jitter
3.125 Gbps
—
0.35
UI
6.25 Gbps
—
0.3
UI
12.5 Gbps1, 2
—
0.3
UI
3.125 Gbps
0.56
—
UI
6.25 Gbps
0.6
—
UI
12.5 Gbps1, 2
0.7
—
UI
Receive jitter tolerance
1.
2.
5.5.8
For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05V mode. See supply tolerance in the
section Recommended Operating Conditions.
Supported on –1 speed grade only.
Display Port
The following table describes Display Port.
Table 5-52. Display Port
Parameter
Data Rate
Condition
Min
Max
Unit
Total transmit jitter
1.62 Gbps
Test point: TP2
—
0.27
UI
2.7 Gbps
Test point: TP2
—
0.42
UI
5.4 Gbps
Test point: TP3_EQ
—
0.621
UI
8.1 Gbps
Test point: TP3_CTLE
—
0.47
UI
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 70
AC Switching Characteristics
...........continued
Parameter
Data Rate
Condition
Min
Max
Unit
Total receive jitter tolerance
1.62 Gbps
SJ at 20 MHz
0.747
—
UI
2.7 Gbps
SJ at 100 MHz
0.491
—
UI
5.4 Gbps
SJ at 10 MHz
0.636
—
UI
SJ at 100 MHz
0.62
—
UI
SJ at 15 MHz
0.62
—
UI
8.1 Gbps
1.
5.5.9
Total transmit jitter includes 0.04 UI from cable crosstalk effect.
Serial RapidIO
The following table describes Serial RapidIO.
Table 5-53. Serial RapidIO
Parameter
Data Rate
Condition
Min
Max
Unit
Total transmit jitter
1.25 Gbps
—
—
0.35
UI
2.5 Gbps
—
—
0.35
UI
3.125 Gbps
—
—
0.35
UI
5.0 Gbps
—
—
0.3
UI
6.25 Gbps
—
—
0.3
UI
10.3125 Gbps
—
—
0.28
UI
1.25 Gbps
—
0.65
—
UI
2.5 Gbps
—
0.65
—
UI
3.125 Gbps
—
0.65
—
UI
5.0 Gbps
Short reach
0.6
—
UI
Long reach
0.95
—
UI
Short reach
0.6
—
UI
Long reach
0.95
—
UI
Short reach
0.62
—
UI
Receive jitter tolerance
6.25 Gbps
10.3125 Gbps
5.5.10
SDI
The following table describes SDI.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 71
AC Switching Characteristics
Table 5-54. SDI
Parameter
Data Rate
Condition
Min
Max
Unit
Total transmit
jitter
270 Mbps
Timing jitter (10
Hz–27 MHz)
—
0.2
UI
Alignment jitter (1 —
KHz–27 MHz)
0.2
UI
Timing jitter (10
Hz–148.5 MHz)
—
1.0
UI
Alignment jitter
(100 KHz–148.5
MHz)
—
0.2
UI
Timing jitter (10
Hz–297 MHz)
—
2.0
UI
Alignment jitter
(100 KHz–297
MHz)
—
0.3
UI
Timing jitter (10
Hz–594 MHz)
—
2.0
UI
Alignment jitter
(100 KHz–594
MHz)
—
0.3
UI
Timing jitter (10
Hz–1188 MHz)
—
2.0
UI
Alignment jitter
(100 KHz–1188
MHz)
—
0.3
UI
270 Mbps
Alignment jitter
0.2
—
UI
1.485 Gbps
Alignment jitter
0.2
—
UI
2.97 Gbps
Alignment jitter
0.3
—
UI
5.94 Gbps
Alignment jitter
0.3
—
UI
11.88 Gbps
Alignment jitter
0.3
—
UI
1.485 Gbps
2.97 Gbps
5.94 Gbps
11.88 Gbps
Receive jitter
tolerance
5.5.11
OTN
The following table describes OTN.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 72
AC Switching Characteristics
Table 5-55. OTN
Parameter
Data Rate
Condition
Min
Max
Unit
Total transmit jitter
2.66 Gbps
3 dB BW: 5 KHz to 20 MHz
—
0.3
UI
3 dB BW: 1 MHz to 20 MHz
—
0.1
UI
3 dB BW: 20 KHz to 80 MHz
—
0.3
UI
3 dB BW: 4 MHz to 80 MHz
—
0.1
UI
3 dB BW: 20 KHz to 80 MHz
—
0.3
UI
3 dB BW: 4 MHz to 80 MHz
—
0.1
UI
SJ at 5 KHz
1.5
—
UI
SJ at 20 MHz
0.15
—
UI
SJ at 20 KHz
1.5
—
UI
SJ at 80 MHz
0.15
—
UI
SJ at 20 KHz
1.5
—
UI
SJ at 80 MHz
0.15
—
UI
10.70 Gbps2
11.09 Gbps1
Receive jitter tolerance
2.66 Mbps
10.70 Gbps2
11.09 Gbps1, 2
1.
2.
5.5.12
For data rates greater than 10.3125 Gbps, VDDA must be set to 1.05V mode. See supply tolerance in the
section Recommended Operating Conditions.
Supported on –1 speed grade only.
Fiber Channel
The following table describes Fiber Channel.
Table 5-56. Fiber Channel
Parameter
Data Rate
Condition
Min
Max
Unit
Total transmit jitter
1.0625 Gbps
—
—
0.23
UI
2.125 Gbps
—
—
0.33
UI
4.25 Gbps
—
—
0.52
UI
8.5 Gbps
—
—
0.31
UI
1.0625 Gbps
0.68
—
—
UI
2.125 Gbps
0.62
—
—
UI
4.24 Gbps
0.62
—
—
UI
8.5 Gbps
0.71
—
—
UI
Receive jitter tolerance
5.5.13
HiGig and HiGig+
The following table describes HiGig and HiGig+.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 73
AC Switching Characteristics
Table 5-57. HiGig and HiGig+
Parameter
Data Rate
Condition
Min
Max
Unit
Total transmit jitter
3.75 Gbps
Near-end
—
0.35
UI
3.75 Gbps
Far-end
—
0.55
UI
3.75 Gbps
—
0.65
—
UI
Receive jitter tolerance
5.5.14
HiGig II
The following table describes HiGig II.
Table 5-58. HiGig II
Parameter
Data Rate
Condition
Min
Max
Unit
Total transmit jitter
6.875 Gbps
Near-end
—
0.35
UI
6.875 Gbps
Far-end
—
0.55
UI
6.875 Gbps
—
0.65
—
UI
Receive jitter tolerance
5.5.15
Firewire IEEE 1394
The following table describes FireWire IEEE 1394.
Table 5-59. FireWire IEEE 1394
Parameter
Data Rate
Condition
Min
Max
Unit
Total transmit jitter
196.608 Mbps
S200 Near-end1
—
200
ps
393.22 Mbps
S400 Near-end2
—
516
ps
786.43 Mbps
S800 Near-end2, 3
—
200
ps
196.608 Mbps
S2001
500
—
ps
393.22 Mbps
S4002
1025
—
ps
786.43 Mbps
S8002
375
—
ps
Receive jitter
tolerance
1.
2.
3.
5.5.16
DS mode.
Beta mode.
PolarFire complies with 1394 S800 electrical requirements with the exception of Tx eye requirement. Refer to
the FireWire characterization report on the PolarFire documentation page for more details.
SLVS-EC
The following table describes SLVS-EC.
Table 5-60. SLVS-EC
Parameter
Data Rate
Condition
Total transmit jitter
2.376 Gbps
—
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
Min
Max
Unit
0.4
ps
DS00003831B-page 74
AC Switching Characteristics
...........continued
5.6
Parameter
Data Rate
Condition
Min
Max
Unit
Receive jitter tolerance
2.376 Gbps
0.15 SJ at 2 MHz
0.5
—
ps
5.0 Gbps
0.15 SJ at 4 MHz
0.5
—
ps
Non-Volatile Characteristics
The following section describes non-volatile characteristics.
5.6.1
FPGA and μPROM Programming Cycle and Retention
The following table describes FPGA and μPROM programming cycle and retention characteristics. Programming,
zeroization, and verify operations all count as a programming cycle.
Retention characteristics for Military-grade devices and Automotive-grade devices at the absolute maximum junction
temperature of 125 °C can be profiled using the PolarFire Retention Calculator, which can be obtained through
technical support at www.microchip.com/support.
Table 5-61. FPGA and μPROM Programming Cycles vs. Retention Characteristics
Programming TJ
Programming Cycles, Max
Retention Years
Retention Years at TJ
0 °C to 85 °C
1000
20
85 °C
0 °C to 100 °C
500
20
100 °C
–20 °C to 100 °C
500
20
100 °C
–40 °C to 100 °C
500
20
100 °C
–40 °C to 85 °C
1000
16
100 °C
–40 °C to 55 °C
2000
12
100 °C
–40 °C to 100 °C
500
20
100 °C
–40 °C to 100 °C
500
10
110 °C
–40 °C to 100 °C
500
Note 2
125 °C
Notes:
1.
2.
5.6.2
Power supplied to the device must be valid during programming operations such as programming and verify.
Programming recovery mode is available only for in-application programming mode and requires an external
SPI Flash.
Contact technical support at www.microchip.com/support.
FPGA Programming Time
The following tables describe FPGA programming time. For allowable programming junction temperature (TJ), see
previous table FPGA and μPROM Programming Cycles vs. Retention Characteristics.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 75
AC Switching Characteristics
Table 5-62. SPI Initiator and Auto-Update Programming Time (IAP)
Parameter
Symbol
Devices
Typ
Max
Unit
Programming time
TPROG
MPF100T, TL, TS, TLS
17
25
s
MPF200T, TL, TS, TLS
17
25
s
MPF300T, TL, TS, TLS
26
32
s
MPF500T, TL, TS, TLS
31
37
s
Table 5-63. SPI Target Programming Time
Parameter
Symbol
Devices
Typ
Max
Unit
Programming time
TPROG
MPF100T, TL, TS, TLS1
27
33
s
MPF200T, TL, TS, TLS1
41
50
s
MPF300T, TL, TS, TLS1
50
60
s
MPF500T, TL, TS, TLS1
90
108
s
1.
2.
SmartFusion2 as SPI Initiator with MSS running at 100 MHz, MSS_SPI_0 port running at 6.67 MHz. Bitstream
stored in DDR. DirectC version 4.1.
Programmer: FlashPro5 with TCK 10 MHz. PC Configuration: Intel i7 at 3.6 GHz, 32 GB RAM, Windows 10.
Table 5-64. JTAG Programming Time
Parameter
Symbol
Devices
Typ
Max
Unit
Programming time
TPROG
MPF100T, TL, TS, TLS1
35
42
s
MPF200T, TL, TS, TLS1
56
68
s
MPF300T, TL, TS, TLS1
95
114
s
MPF500T, TL, TS, TLS1
122
147
s
1.
5.6.3
Programmer: FlashPro5 with TCK 10 MHz. PC Configuration: Intel i7 at 3.6 GHz, 32 GB RAM, Windows 10.
FPGA Bitstream Sizes
The following table describes FPGA bitstream sizes.
Table 5-65. Initialization Client Sizes
Device
Plaintext
Ciphertext
MPF100T, TL, TS, TLS
1580 KB
1630 KB
MPF200T, TL, TS, TLS
2916 KB
3006 KB
MPF300T, TL, TS, TLS
4265 KB
4403 KB
MPF500T, TL, TS, TLS
6835 KB
7045 KB
Note: Worst case initializing all fabric LSRAM, USRAM, and UPROM.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 76
AC Switching Characteristics
Table 5-66. Bitstream Sizes
5.6.4
File Devices
FPGA
Security SNVM (all
pages)
FPGA+
SNVM
FPGA+ Sec SNVM+ Sec FPGA+
SNVM+ Sec
SPI
MPF100T, TL,
TS, TLS
3.4 MB
3.5 KB
59.7 KB
3.5 MB
3.5 MB
62.2 KB
3.5 MB
DAT MPF100T, TL,
TS, TLS
3.4 MB
7.6 KB
61.2 KB
3.5 MB
3.4 MB
66.3 KB
3.5 MB
SPI
MPF200T, TL,
TS, TLS
5.9 MB
3.5 KB
59.7 KB
5.9 MB
5.9 MB
62.2 KB
6.0 MB
DAT MPF200T, TL,
TS, TLS
5.9 MB
7.6 KB
61.2 KB
6.0 MB
5.9 MB
66.3 KB
6.0 MB
SPI
MPF300T, TL,
TS, TLS
9.3 MB
3.5 KB
59.7 KB
9.6 MB
9.5 MB
62.2 KB
9.6 MB
DAT MPF300T, TL,
TS, TLS
9.3 MB
7.6 KB
61.2 KB
9.6 MB
9.5 MB
66.3 KB
9.6 MB
SPI
MPF500T, TL,
TS, TLS
14.3 MB 3.5 KB
59.7 KB
14.4 MB
14.3 MB
62.2 KB
14.4 MB
DAT MPF500T, TL,
TS, TLS
14.3 MB 7.6 KB
61.2 KB
14.4 MB
14.3 MB
66.3 KB
14.4 MB
Digest Cycles
Digests verify the integrity of the programmed non-volatile data. Digests are a cryptographic hash of various data
areas. Any digest that reports back an error raises the digest tamper flag. Digests are operational only from –40 °C to
100 °C.
Table 5-67. Maximum Number of Digest Cycles
Retention Since Programmed (N = Number Digests During that Time)1
Storage and N ≤300 N = 500
Operating
TJ
N = 1000
N = 1500
N = 2000
N = 4000
N = 6000
Unit
Retention
–40 to 100
20 ×
LF
17 × LF
12 × LF
10 × LF
8 × LF
4 × LF
2 × LF
°C
Years
0 to 100
20 ×
LF
17 × LF
12 × LF
10 × LF
8 × LF
4 × LF
2 × LF
°C
Years
–40 to 85
20 ×
LF
20 × LF
20 × LF
20 × LF
16 × LF
8 × LF
4 × LF
°C
Years
–40 to 55
20 ×
LF
20 × LF
20 × LF
20 × LF
20 × LF
20 × LF
20 × LF
°C
Years
–40 to 110
10 ×
LF
8.5 × LF
6 × LF
5 × LF
4 × LF
2 × LF
1 × LF
°C
Years
–40 to 125
Note 2
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 77
AC Switching Characteristics
...........continued
Retention Since Programmed (N = Number Digests During that Time)1
Storage and N ≤300 N = 500
Operating
TJ
N = 1000
N = 1500
N = 2000
N = 4000
N = 6000
Unit
Retention
–55 to 110
10 ×
LF
6 × LF
5 × LF
4 × LF
2 × LF
1 × LF
°C
Years
–55 to 125
Note 2
1.
2.
8.5 × LF
LF = Lifetime Factor as defined by the number of programming cycles the device has seen under the
conditions listed in the following table.
Contact technical support at www.microchip.com/support.
Table 5-68. FPGA Programming Cycles Lifetime Factor
Programming TJ
Programming Cycles
LF
–40 °C to 100 °C
500
1
–40 °C to 85 °C
1000
0.8
–40 °C to 55 °C
2000
0.6
Notes:
•
•
•
•
•
•
•
5.6.5
The maximum number of accumulated device digest cycles is 100K. The maximum number of digests is 10K
cycles between programming non-volatile data (fabric sNVM, user keys, user locks, and so on).
Digests are operational only over the –40 °C to 100 °C temperature range.
After a program cycle, an additional N digests cycles are allowed with the resultant retention characteristics for
the total operating and storage temperature shown.
Retention is specified for total device storage and operating temperature.
All temperatures are junction temperatures (TJ).
Example 1: 500 digests cycles are performed between programming cycles. N = 500. The operating conditions
are –40 °C to 85 °C TJ. 501 programming cycles have occurred. The retention under these operating conditions
is 20 × LF = 20 × .8 = 16 years.
Example 2: One programming cycle has occurred, N = 1500 digest cycles have occurred. Temperature range is
–40 °C to 100 °C. The resultant retention is 10 × LF or 10 years over the industrial temperature range.
Digest Time
The following table describes digest time.
Table 5-69. Digest Times
Parameter
Devices
Typ
Max
Unit
Setup time
All
2
—
μs
Fabric digest run time
MPF100T, TL, TS, TLS
880
910
ms
MPF200T, TL, TS, TLS
1005
1072
ms
MPF300T, TL, TS, TLS
1503.9
1582
ms
MPF500T, TL, TS, TLS
2085
2150
ms
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 78
AC Switching Characteristics
...........continued
Parameter
Devices
Typ
Max
Unit
UFS CC digest run time
MPF100T, TL, TS, TLS
33.5
35
μs
MPF200T, TL, TS, TLS
33.5
35
μs
MPF300T, TL, TS, TLS
33.5
35
μs
MPF500T, TL, TS, TLS
33.5
35
μs
MPF100T, TL, TS, TLS
4.5
5
ms
MPF200T, TL, TS, TLS
4.5
5
ms
MPF300T, TL, TS, TLS
4.5
5
ms
MPF500T, TL, TS, TLS
4.5
5
ms
MPF100T, TL, TS, TLS
47
49
μs
MPF200T, TL, TS, TLS
47
49
μs
MPF300T, TL, TS, TLS
47
49
μs
MPF500T, TL, TS, TLS
47
49
μs
MPF100T, TL, TS, TLS
526
544
μs
MPF200T, TL, TS, TLS
526
544
μs
MPF300T, TL, TS, TLS
526
544
μs
MPF500T, TL, TS, TLS
526
544
μs
MPF100T, TL, TS, TLS
33.2
35
μs
MPF200T, TL, TS, TLS
33.2
35
μs
MPF300T, TL, TS, TLS
33.2
35
μs
MPF500T, TL, TS, TLS
33.2
35
μs
MPF100T, TL, TS, TLS
494
511
μs
MPF200T, TL, TS, TLS
494
511
μs
MPF300T, TL, TS, TLS
494
511
μs
MPF500T, TL, TS, TLS
494
511
μs
sNVM digest run time1
UFS UL digest run time
User key digest run time2
UFS UPERM digest run time
Factory digest run time
1.
2.
The entire sNVM is used as ROM.
Valid for user key 0 through 6.
Note: These times do not include the power-up to functional timing overhead when using digest checks on power-up.
5.6.6
Zeroization Time
This section describes zeroization time. A zeroization operation counts as one programming cycle.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 79
AC Switching Characteristics
Table 5-70. Zeroization Times for MPF100T, TL, TS, and TLS Devices
Parameter
Typ Max Unit Conditions
Time to enter zeroization
8
Time to destroy the fabric data1
ms
Zip flag set
248 253
ms
Data erased
Time to destroy data in non-volatile memory (like new)1, 2
507 522
ms
One iteration of scrubbing
Time to destroy data in non-volatile memory (non-recoverable)1, 3
520 536
ms
One iteration of scrubbing
Time to scrub the fabric data1
0.8
0.9
s
Full scrubbing
Time to scrub the pNVM data (like new)1, 2
1.5
1.6
s
Full scrubbing
Time to scrub the fabric data pNVM data (non-recoverable)1, 3
1.7
1.8
s
Full scrubbing
Time to verify5
1.1
1.2
s
—
Total time to zeroize (like new)1, 2
2.8
2.9
s
—
Total time to zeroize (non-recoverable)1, 3
3.1
3.2
s
—
1.
2.
3.
4.
9
Total completion time after entering zeroization.
Like new mode—zeroizes user design security setting and sNVM content.
Non-recoverable mode—zeroizes user design security setting, sNVM and factory keys, and factory data
required for programming.
Time to verify after scrubbing completes.
Table 5-71. Zeroization Times for MPF200T, TL, TS, and TLS Devices
Parameter
Typ Max Unit Conditions
Time to enter zeroization
8
Time to destroy the fabric data1
ms
Zip flag set
250 255
ms
Data erased
Time to destroy data in non-volatile memory (like new)1, 2
507 522
ms
One iteration of scrubbing
Time to destroy data in non-volatile memory (non-recoverable)1, 3
520 536
ms
One iteration of scrubbing
Time to scrub the fabric data1
0.9
1.0
s
Full scrubbing
Time to scrub the pNVM data (like new)1, 2
1.5
1.6
s
Full scrubbing
Time to scrub the fabric data PNVM data (non-recoverable)1, 3
1.7
1.8
s
Full scrubbing
Time to verify5
1.4
1.5
s
—
Total time to zeroize (like new)1, 2
2.9
3.0
s
—
Total time to zeroize (non-recoverable)1, 3
3.1
3.2
s
—
1.
2.
3.
4.
9
Total completion time after interning zeroization.
Like new mode—zeroizes user design security setting and sNVM content.
Non-recoverable mode—zeroizes user design security setting, sNVM and factory keys, and factory data
required for programming.
Time to verify after scrubbing completes.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 80
AC Switching Characteristics
Table 5-72. Zeroization Times for MPF300T, TL, TS, and TLS Devices
Parameter
Typ Max Unit Conditions
Time to enter zeroization
8
Time to destroy the fabric data1
ms
Zip flag set
390 420
ms
One iteration of scrubbing
Time to destroy data in non-volatile memory (like new)1, 2
507 522
ms
One iteration of scrubbing
Time to destroy data in non-volatile memory (non- recoverable)1, 3
520 536
ms
One iteration of scrubbing
Time to scrub the fabric data1
1.3
1.4
s
Full scrubbing
Time to scrub the pNVM data (like new)1, 2
1.5
1.6
s
Full scrubbing
Time to scrub the fabric data pNVM data (non-recoverable)1, 3
1.7
1.8
s
Full scrubbing
Time to verify5
1.8
1.9
s
—
Total time to zeroize (like new)1, 2
3.7
3.8
s
—
Total time to zeroize (non-recoverable)1, 3
3.9
4
s
—
1.
2.
3.
4.
9
Total completion time after interning zeroization.
Like new mode—zeroizes user design security setting and sNVM content.
Non-recoverable mode—zeroizes user design security setting, sNVM and factory keys, and factory data
required for programming.
Time to verify after scrubbing completes.
Table 5-73. Zeroization Times for MPF500T, TL, TS, and TLS Devices
Parameter
Typ Max Unit Conditions
Time to enter zeroization
8
Time to destroy the fabric data1
ms
Zip flag set
392 422
ms
One iteration of scrubbing
Time to destroy data in non-volatile memory (like new)1, 2
507 522
ms
One iteration of scrubbing
Time to destroy data in non-volatile memory (non-recoverable)1, 3
520 536
ms
One iteration of scrubbing
Time to scrub the fabric data1
1.4
1.5
s
Full scrubbing
Time to scrub the pNVM data (like new)1, 2
1.5
1.6
s
Full scrubbing
Time to scrub the fabric data pNVM data (non-recoverable)1, 3
1.7
1.8
s
Full scrubbing
Time to verify5
1.9
2.0
s
—
Total time to zeroize (like new)1, 2
3.8
3.9
s
—
Total time to zeroize (non-recoverable)1, 3
4.0
4.1
s
—
1.
2.
3.
4.
9
Total completion time after entering zeroization.
Like new mode—zeroizes user design security setting and sNVM content.
Non-recoverable mode—zeroizes user design security setting, sNVM and factory keys, and factory data
required for programming.
Time to verify after scrubbing completes.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 81
AC Switching Characteristics
5.6.7
Verify Time
The following tables describe verify time.
Table 5-74. Standalone Fabric Verify Times
Parameter
Devices
Max
Unit
Standalone verification over JTAG
MPF100T, TL, TS, TLS1
33
s
MPF200T, TL, TS, TLS1
53
s
MPF300T, TL, TS, TLS1
90
s
MPF500T, TL, TS, TLS1
114
s
MPF100T, TL, TS, TLS2
24
s
MPF200T, TL, TS, TLS2
37
s
MPF300T, TL, TS, TLS2
55
s
MPF500T, TL, TS, TLS2
89
s
Standalone verification over SPI
1.
2.
Programmer: FlashPro5, TCK 10 MHz; PC configuration: Intel i7 at 3.6 GHz, 32 GB RAM, Windows 10.
SmartFusion2 with MSS running at 100 MHz, MSS_SPI_0 port running at 6.67 MHz. Bitstream stored in DDR.
DirectC version 4.1.
Notes:
•
•
•
•
Standalone verify is limited to 2,000 total verify hours over the industrial –40 °C to 100 °C temperature. For
example, 2000 hours = 7.2M seconds. The MPF300T device has a 90-second verify time over JTAG. This
equates to 80,000 verify operations for the life of the MPF300T device.
Use the digest system service for verify times greater than 2,000 hours.
Standalone verify checks the programming margin on both the P and N gates of the push-pull cell.
Digest checks only the P side of the push-pull gate. However, the push-pull gates work in tandem. Digest check
is recommended if users believe they will exceed the 2,000-hour verify time specification.
Table 5-75. Verify Time by Programming Hardware
Devices
IAP
FlashPro4
FlashPro5
BP
Silicon Sculptor
Units
MPF100T, TL, TS, TLS
6
42
33
—
—
s
MPF200T, TL, TS, TLS
9
67
53
—
—
s
MPF300T, TL, TS, TLS
14
95
90
—
—
s
MPF500T, TL, TS, TLS
15
169
114
—
—
s
Notes:
•
•
•
FlashPro4 4 MHz TCK.
FlashPro5 10 MHz TCK.
PC configuration: Intel i7 at 3.6 GHz, 32 GB RAM, Windows 10.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 82
AC Switching Characteristics
Table 5-76. Verify System Services
Parameter
Symbol
ServiceID
Devices
Typ
Max
Unit
In application verify by index
TIAP_Ver_Index
44H
MPF100T, TL, TS, TLS
5.9
6.2
s
MPF200T, TL, TS, TLS
8.2
9
s
MPF300T, TL, TS, TLS
12.4
13
s
MPF500T, TL, TS, TLS
13.4
14
s
MPF100T, TL, TS, TLS
5.9
6.2
s
MPF200T, TL, TS, TLS
8.2
9
s
MPF300T, TL, TS, TLS
12.4
13
s
MPF500T, TL, TS, TLS
13.4
14
s
In application verify by SPI address
5.6.8
TIAP_Ver_Addr
45H
Authentication Time
The following tables describe authentication system service time.
Table 5-77. Authentication Services
Parameter
Symbol
ServiceID
Devices
Typ
Max
Unit
Bitstream Authentication
TBIT_AUTH
22H
MPF100T, TL, TS, TLS
2.1
2.4
s
MPF200T, TL, TS, TLS
3.3
3.7
s
MPF300T, TL, TS, TLS
4.9
5.4
s
MPF500T, TL, TS, TLS
7.6
7.8
s
MPF100T, TL, TS, TLS
2.1
2.4
s
MPF200T, TL, TS, TLS
3.3
3.7
s
MPF300T, TL, TS, TLS
4.9
5.4
s
MPF500T, TL, TS, TLS
7.6
7.8
s
IAP Image Authentication
5.6.9
TIAP_AUTH
23H
Secure NVM Performance
The following table describes secure NVM performance.
Table 5-78. sNVM Read/Write Characteristics
Parameter
Symbol
Min Typ
Max Unit Conditions
Plain text programming
—
7.0
7.2
7.9
ms
—
Authenticated text programming
—
7.2
7.4
9.4
ms
—
Authenticated and encrypted text programming
—
7.2
7.4
9.4
ms
—
Authentication R/W 1st access from power-up overhead
TPUF_OVHD 10
13
111
ms
From TFAB_READY
Plain text read
—
8
8.5
9
μs
—
Authenticated text read
—
113 114.5 119
μs
—
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 83
AC Switching Characteristics
...........continued
Parameter
Symbol
Min Typ
Max Unit Conditions
Authenticated and decrypted text read
—
159 161
167
μs
—
Notes:
•
•
•
5.6.10
Page size = 256 bytes (non-authenticated), 236 bytes (authenticated).
Only page reads and writes allowed.
TPUF_OVHD is an additional time that occurs on the first R/W, after cold or warm boot, to sNVM using
authenticated or authenticated and encrypted text.
Secure NVM Programming Cycles
The following table describes secure NVM programming cycles.
Table 5-79. sNVM Programming Cycles vs. Retention Characteristics
Programming Temperature Programming Cycles per
Page, Max
Programming Cycles per
Block, Max
Retention Years
–40 °C to 100 °C
10,000
100,000
20
–40 °C to 85 °C
10,000
100,000
20
–40 °C to 55 °C
10,000
100,000
20
–40 °C to 125 °C
10,000
100,000
Note 2
–55 °C to 125 °C
10,000
100,000
Note 2
Notes:
1.
2.
5.7
Page size = 256 bytes. Block size = 56 KBytes.
Contact technical support at www.microchip.com/support.
System Services
This section describes system switching and throughput characteristics.
5.7.1
System Services Throughput Characteristics
The following table describes system services throughput characteristics.
Table 5-80. System Services Throughput Characteristics
Parameter
Symbol
Service ID
Typ Max
Unit
Conditions
Serial number
TSerial
00H
65
67
μs
—
User code
TUser
01H
0.8
1.2
μs
—
Design information
TDesign
02H
2.5
3
μs
—
Device certificate
TCert
03H
255
271
ms
—
Read digests
Tdigest_read
04H
201
215
μs
—
Query security locks
Tsec_Query
05H
15
17
μs
—
Read debug information
TRd_debug
06H
34
38
μs
—
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 84
AC Switching Characteristics
...........continued
Parameter
Symbol
Service ID
Typ Max
Unit
Conditions
Reserved
—
07H–0FH
—
—
—
—
Secure NVM write plain text
TSNVM_Wr_Plain
10H
—
—
—
Note 1
Secure NVM write authenticated plain text
TSNVM_Wr_Auth
11H
—
—
—
Note 1
Secure NVM write authenticated cipher text
TSNVM_Wr_Cipher
12H
—
—
—
Note 1
Reserved
—
13H–17H
—
—
—
—
Secure NVM read
TSNVM_Rd
18H
—
—
—
Note 1
Digital signature service raw
TSIG_RAW
19H
174
187
ms
—
Digital signature service DER
TSIG_DER
1AH
174
187
ms
—
Reserved
—
1BH–1FH
—
—
—
—
PUF emulation
TChallenge
20H
1.8
2.0
ms
—
Nonce service
TNonce
21H
1.2
1.5
ms
—
Bitstream authentication
TBIT_AUTH
22H
—
—
—
Note 4
IAP Image authentication
TIAP_AUTH
23H
—
—
—
Note 4
Reserved
—
26H–3FH
In-application programming by index
TIAP_Prg_Index
42H
—
—
—
Note 2
In-application programming by SPI address
TIAP_Prg_Addr
43H
—
—
—
Note 2
In-application verify by index
TIAP_Ver_Index
44H
—
—
—
Note 5
In-application verify by SPI address
TIAP_Ver_Addr
45H
—
—
—
Note 5
Auto update
TAutoUpdate
46H
—
—
—
Note 2
Digest check
Tdigest_chk
47H
—
—
—
Note 3
1.
2.
3.
4.
5.
6.
5.8
—
See Table 5-78. sNVM Read/Write Characteristics.
See Table 5-62. SPI Initiator and Auto-Update Programming Time (IAP).
See Table 5-69. Digest Times.
See Table 5-77. Authentication Services.
See Table 5-76. Verify System Services.
Throughputs described are measured from SS_REQ assertion to BUSY de-assertion.
Fabric Macros
This section describes switching characteristics of UJTAG, UJTAG_SEC, PF_SPI, system controller, and temper
detectors and dynamic reconfiguration.
5.8.1
UJTAG Switching Characteristics
The following section describes characteristics of UJTAG switching.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 85
AC Switching Characteristics
Table 5-81. UJTAG Performance Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Condition
TCK frequency
FTCK
—
—
25
MHz
—
Figure 5-6. UJTAG Timing Diagram
5.8.2
UJTAG_SEC Switching Characteristics
The following table describes characteristics of UJTAG_SEC switching.
Table 5-82. UJTAG Security Performance Characteristics
5.8.3
Parameter
Symbol
Min
Typ
Max
Unit
Condition
TCK frequency
FTCK
—
—
—
MHz
—
PF_SPI Initiator Programming Switching Characteristics
The following section describes characteristics of PF_SPI initiator programming switching.
Table 5-83. SPI Initiator Programming Performance Characteristics
5.8.4
Parameter
Symbol
Min
Typ
Max
Unit
Condition
SCK frequency
FSCK
—
—
20
MHz
—
Tamper Detectors
The following section describes tamper detectors.
Table 5-84. ADC Conversion Rate
Min Typ1
Parameter Description
Max Unit
TCONV1
Time from enable changing from zero to non-zero value to first conversion 350 —
completes. Minimum value applies when POWEROFF = 0.
470 μs
TCONVN
Time between subsequent channel conversions.
—
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
—
480
μs
DS00003831B-page 86
AC Switching Characteristics
...........continued
Parameter Description
Min Typ1
Max Unit
TSETUP
Data channel and output to valid asserted. Data is held until next
conversion completes, that is >480 μs.
0
—
—
ns
TVALID 2
Width of the valid pulse.
1.5
—
2.5
μs
TRATE
Time from start of first set of conversions to the start of the next set.
Can be considered as the conversion rate. Is set by the conversion rate
parameter.
—
Rate × 32 —
1.
2.
μs
Min, Typ, and Max refer to variation due to functional configuration and the raw TVS value. The actual internal
correction time will vary based on the raw TVS value.
The pulse width varies depending on the time taken to complete the internal calibration multiplication, this can
be up to 375 ns.
Note: Once the TVS block is active, the enable signal is sampled 25 ns before the falling edge of valid. The next
enabled channel in the sequence 0-1-2-3 is started; that is, if channel 0 has just completed and only channels 0 and
3 are enabled, the next channel will be 3. When all the enabled channels in the sequence 0-1-2-3 are completed,
the TVS waits for the conversion rate timer to expire. The enable signal may be changed at any time if it changes to
4’b0000 while valid is asserted (and 25 ns before valid is de-asserted), then no further conversions will be started.
Table 5-85. Temperature and Voltage Sensor Electrical Characteristics
Parameter
Min
Typ
Max
Unit
Condition
Temperature sensing range
–55
—
125
°C
—
Temperature sensing accuracy
–10
—
10
°C
—
Voltage sensing range
0.9
—
2.8
V
—
Voltage sensing accuracy
–3.0
—
3.0
%
—
Table 5-86. Tamper Macro Timing Characteristics—Flags and Clearing
Parameter
Symbol
Typ Max
Unit
From event detection to flag generation
TJTAG_ACTIVE 1
28
35
ns
TMESH_ERR 1
1.8
2.5
μs
TCLK_GLITCH 1
—
50
ns
TCLK_FREQ 1
—
4
μs
TLOW_VDD 1, 3
70
1000 μs
THIGH_VDD18 1, 3
85
1000 μs
THIGH_VDD25 1, 3
130 1000 μs
TSECDEC 1
—
5
ns
TDRI_ERR 1
14
18
μs
TWDOG 1
—
5
ns
TLOCK_ERR 1
—
5
ns
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 87
AC Switching Characteristics
...........continued
Parameter
Symbol
Typ Max
Unit
Time from system controller instruction execution to flag generation
TINST_BUF_ACCESS 1, 2
4
5
μs
TINST_DEBUG 1, 2
3.3
4
μs
TINST_CHK_DIGEST 1, 2
1.8
3
μs
TINST_EC_SETUP 1, 2
1.8
2
μs
TINST_FACT_PRIV 1, 2
3.8
5
μs
TINST_KEY_VAL 1, 2
2.5
3.5
μs
TINST_MISC 1, 2
1.5
2
μs
TINST_PASSCODE_MATCH 1, 2
2.5
3
μs
TINST_PASSCODE_SETUP 1, 2
4.2
5
μs
TINST_PROG 1, 2
3.8
4.5
μs
TINST_PUB_INFO 1, 2
4
4.5
μs
TINST_ZERO_RECO 1, 2
2.5
3
μs
TINST_PASSCODE_FAIL 1, 2
170 180
μs
TINST_KEY_VAL_FAIL 1, 2
92
110
μs
TINST_UNUSED 1, 2
4
5
μs
TCLEAR_FLAG
17
23
ns
Time from sending the CLEAR to deassertion on FLAG
1.
2.
3.
The timing does not impact the user design, but it is useful for security analysis.
System service requests from the fabric will interrupt the system controller delaying the generation of the flag.
Timing of these depends highly on supply ramp rate.
Table 5-87. Tamper Macro Response Timing Characteristics
5.8.5
Parameter
Symbol
Typ
Max Unit
Time from triggering the response to all I/Os disabled
TIO_DISABLE
45
63
ns
Time from negation of RESPONSE to all I/Os re-enabled
TCLR_IO_DISABLE
34
51
ns
Time from triggering the response to security locked
TLOCKDOWN
—
20
ns
Time from negation of RESPONSE to earlier security unlock condition
TCLR_LOCKDOWN
—
20
ns
Time from triggering the response to device enters RESET
Ttr_RESET
11.7 14
μs
Time from triggering the response to start of zeroization
Ttr_ZEROLISE
7.4
ms
8.2
System Controller Suspend Switching Characteristics
The following table describes the characteristics of system controller suspend switching.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 88
AC Switching Characteristics
Table 5-88. System Controller Suspend Entry and Exit Characteristics
Parameter
Symbol
Time from TRSTb falling edge to
SUSPEND_EN signal assertion
Tsuspend_Tr 1, 2 Suspend entry time from
TRST_N assertion
Time from TRSTb rising edge to ACTIVE signal Tsuspend_exit
assertion
1.
2.
5.8.6
Definition
Typ Max Unit
42
Suspend exit time from TRST_N
negation
44
ns
361 372 ns
ACTIVE indicates that the system controller is inactive or active regardless of the state of SUSPEND_EN.
ACTIVE signal must never be asserted with SUSPEND_EN is asserted.
Dynamic Reconfiguration Interface
The following table provides interface timing information for the DRI, which is an embedded APB target interface
within the FPGA fabric that does not use FPGA resources.
Table 5-89. Dynamic Reconfiguration Interface Timing Characteristics
5.8.7
Parameter
Symbol
Max
Unit
PCLK frequency
FPD _PCLK
200
MHz
User Voltage Detector Characteristics
The following table provides the electrical characteristics of the VDD (1.0V), VDD18, and VDD25 voltage detectors. For
proper operation of the voltage detectors, VDD must be set to 1.0V.
Table 5-90. User Voltage Detector Electrical Characteristics
5.9
Parameter
Min
Typ Max
Unit Condition
VDD_HIGH_DET
1.04
—
1.07
V
Temp= –40 ºC to 100 ºC; VDD18 = 1.8V ±5%; VDD25= 2.5V ±5%
VDD18_HIGH_DET
1.9
—
1.96
V
Temp= –40 ºC to 100 ºC; VDD = 1.0V ±3%; VDD25= 2.5V ±5%
VDD25_HIGH_DET
2.66
—
2.74
V
Temp= –40 ºC to 100 ºC; VDD = 1.0V ±3%; VDD18= 1.8V ±5%
VDD_LOW_DET
0.945
—
0.915
V
Temp= –40 ºC to 100 ºC; VDD18 = 1.8 ±5%; VDD25= 2.5V ±5%
VDD18_LOW_DET
1.62
—
1.57
V
Temp= –40 ºC to 100 ºC; VDD = 1.0 ±3%; VDD25= 2.5 V ±5%
VDD25_LOW_DET
2.31
—
2.21
V
Temp= –40 ºC to 100 ºC; VDD = 1.0 ±3%; VDD18= 1.8V ±5%
Power-Up to Functional Timing
Microchip non-volatile FPGA technology offers the fastest boot-time of any mid-range FPGA in the market. The
following tables describes both cold-boot (from power-on) and warm-boot (assertion of DEVRST_N pin or assertion
of reset from the tamper macro) timing. The power-up diagrams assume all power supplies to the device are stable.
5.9.1
Power-On (Cold) Reset Initialization Sequence
The following cold reset timing diagram shows the initialization sequencing of the device.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 89
AC Switching Characteristics
Figure 5-7. Cold Reset Timing
Notes:
•
•
•
•
5.9.2
Figure 5-7. Cold Reset Timing shows the case where VDDI/VDDAUX of I/O banks are powered either before
or sufficiently soon after VDD/VDD18/VDD25 that the I/O bank enable time is measured from the assertion time
of VDD/VDD18/VDD25 (that is, the PUFT specification). If VDDI/VDDAUX of I/O banks are powered sufficiently
after VDD/VDD18/VDD25, then the I/O bank enable time is measured from the assertion of VDDI/VDDAUX
and is not specified by the PUFT specification. In this case, I/O operation is indicated by the assertion of
BANK_i_VDDI_STATUS, rather than being measured relative to FABRIC_POR_N negation.
AUTOCALIB_DONE assertion indicates the completion of calibration for any I/O banks specified by the user
for auto-calibration. AUTOCALIB_DONE asserts independently of DEVICE_INIT_DONE. It may assert before or
after DEVICE_INIT_DONE and is determined by the following:
– How long after VDD/VDD18/VDD25 that VDDI/VDDAUX are powered ON. Note that if any of
the user-specified I/O banks are not powered ON within the auto-calibration timeout window, then
AUTOCALIB_DONE doesn't assert until after this timeout.
– The specified ramp times of VDDI of each I/O bank designated for auto-calibration.
– How much auto-initialization is to be performed for the PCIe, SERDES transceivers, and fabric LSRAMs.
If any of the I/O banks specified for auto-calibration do not have their VDDI/VDDAUX powered ON within
the auto-calibration timeout window, then it will be approximately auto-calibrated whenever VDDI/VDDAUX is
subsequently powered ON. To obtain an accurate calibration however, on such I/O banks, it is necessary to
initiate a re-calibration (using CALIB_START from fabric).
AVM_ACTIVE only asserts if avionics mode is being used. It is asserted when the later of DEVICE_INIT_DONE
or AUTOCALIB_DONE assert.
Warm Reset Initialization Sequence
The following warm reset timing diagram shows the initialization sequencing of the device when either DEVRST_N or
TAMPER_RESET_DEVICE signals are asserted.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 90
AC Switching Characteristics
Figure 5-8. Warm Reset Timing
5.9.3
Power-On Reset Voltages
The following sections describe the power-on reset voltages.
5.9.3.1
Main Supplies
The start of power-up to functional time (TPUFT) is defined as the point at which the latest of the main supplies
(VDD, VDD18, VDD25) reach the reference voltage levels specified in the following table. This starts the process of
releasing the reset of the device and powering ON the FPGA fabric and I/Os.
Table 5-91. POR Ref Voltages
5.9.3.2
Supply
Power-On Reset Start Point (V)
Note
VDD
0.95
Applies to both 1.0V and 1.05V operation.
VDD18
1.71
—
VDD25
2.25
—
I/O-Related Supplies
For the I/Os to become functional (for low speed, sub-400 MHz operation), the (per-bank) I/O supplies (VDDI,
VDDAUX) must reach the trip point voltage levels specified in the following table and the main supplies above must
also be powered ON.
Table 5-92. I/O-Related Supplies
Supply
I/O Power-Up Start Point (V)
VDDI
0.85
VDDAUX
1.6
There are no sequencing requirements for the power supplies. There are few sequences that can create temporary
glitches on GPIO during initialization. Refer to UG0726: PolarFire FPGA Board Design User Guide for more details.
In order for the device to start initialization, VDDI3 must be valid at the same time as the other main supplies (VDD,
VDD18, VDD25). The other I/O supplies (VDDI, VDDAUX) have no effect on power-up of FPGA fabric (that is, the
fabric still powers up even if the I/O supplies of I/O banks remain powered OFF, with the exception of VDDI3).
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 91
AC Switching Characteristics
5.9.4
User Design Dependence of Power-Up Times
Some phases of the device initialization are user design dependent, as the device automatically initializes certain
resources to user-specified configurations if those resources are used in the design. It is necessary to compute the
overall power-up to functional time by referencing the following tables and adding the relevant phases, according to
the design configuration. The following equation refers to timing parameters specified in the above timing diagrams.
Please note TPCIE , TXCVR, TLSRAM, and TUSRAM can be found in UG0725: PolarFire FPGA Device Power-Up and
Resets User Guide.
TPUFT = TFAB_READY(cold) + max((TPCIE + TXCVR + TLSRAM + TUSRAM), TCALIB)
TWRFT = TFAB_READY(warm) + max((TPCIE + TXCVR + TLSRAM + TUSRAM), TCALIB)
Note: TPCIE, TXCVR, TLSRAM, TUSRAM, and TCALIB are common to both cold and warm reset scenarios.
Auto-initialization of FPGA (if required) occurs in parallel with I/O calibration. The device may be considered fully
functional only when the later of these two activities has finished, which may be either one, depending on the
configuration, as may be calculated from the following tables. Note that I/O calibration may extend beyond TPUFT (as
I/O calibration process is independent of main device power-on and is instead dependent on I/O bank supply relative
power-on time and ramp times). The previous timing diagram for power-on initialization shows the earliest that I/Os
could be enabled, if the I/O power supplies are powered on before or at the same time as the main supplies.
5.9.5
Cold Reset to Fabric and I/Os (Low Speed) Functional
The following table specifies the minimum, typical, and maximum times from the power supplies reaching the above
trip point levels until the FPGA fabric is operational and the FPGA IOs are functional for low-speed (sub-400 MHz)
operation.
Table 5-93. Cold Boot
5.9.6
Power-On (Cold) Reset to Fabric and I/O Operational
Min
Typ
Max
Unit
Time when input pins start working – TIN_ACTIVE(cold)
0.92
4.38
7.84
ms
Time when weak pull-ups are enabled – TPU_PD_ACTIVE(cold)
0.92
4.38
7.84
ms
Time when fabric is operational – TFAB_READY(cold)
0.95
4.41
7.87
ms
Time when output pins start driving – TOUT_ACTIVE(cold)
0.97
4.43
7.89
ms
Warm Reset to Fabric and I/Os (Low Speed) Functional
The following table specifies the minimum, typical, and maximum times from the negation of the warm reset event
until the FPGA fabric is operational and the FPGA IOs are functional for low-speed (sub-400 MHz) operation.
Table 5-94. Warm Boot
5.9.7
Warm Reset to Fabric and I/O Operational
Min
Typ
Max
Unit
Time when input pins start working – TIN_ACTIVE(warm)
0.65
1.63
2.62
ms
Time when weak pull-ups/pull-downs are enabled – TPU_PD_ACTIVE(warm)
0.65
1.63
2.62
ms
Time when fabric is operational – TFAB_READY(warm)
0.68
1.66
2.65
ms
Time when output pins start driving – TOUT_ACTIVE(warm)
0.70
1.68
2.67
ms
Miscellaneous Initialization Parameters
In the following table, TFAB_READY refers to either TFAB_READY(cold) or TFAB_READY(warm) as specified in the previous
tables, depending on whether the initialization is occurring as a result of a cold or warm reset, respectively.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 92
AC Switching Characteristics
Table 5-95. Cold and Warm Boot
Parameter
Symbol
Min Typ
Max
Unit Condition
The time from TFAB_READY to ready to program
through JTAG/SPI-Target
—
0
0
0
ms
—
The time from TFAB_READY to auto-update start
—
—
TPUF_OVHD 1 TPUF_OVHD 1 ms
—
The time from TFAB_READY to programming
recovery start
—
—
TPUF_OVHD 1 TPUF_OVHD 1 ms
—
The time from TFAB_READY to the tamper flags
being available
TTAMPER_READY 0
0
0
ms
—
The time from TFAB_READY to the Athena Crypto TCRYPTO_READY 0
co-processor being available (for S devices
only)
0
0
ms
—
1.
5.9.8
Programming depends on the PUF to power-up. Refer to TPUF_OVHD at section Secure NVM Performance.
I/O Calibration
The following tables specify the initial I/O calibration time for the fastest and slowest supported VDDI ramp times of
0.2 ms to 50 ms, respectively. This only applies to I/O banks specified by the user to be auto-calibrated.
Table 5-96. I/O Initial Calibration Time (TCALIB)
Ramp Time
Min (ms)
Max (ms)
Condition
0.2 ms
0.98
2.63
Applies to HSIO and GPIO banks
50 ms
41.62
62.19
Applies to HSIO and GPIO banks
Notes:
•
•
The user may specify any VDDI ramp time in the range specified above. The nominal initial calibration time is
given by the specified VDDI ramp time plus 2 ms.
In order for I/O calibration to start, VDDI and VDDAUX of the I/O bank must be higher than the trip point levels
specified in section I/O-Related Supplies.
Table 5-97. I/O Fast Recalibration Time (TRECALIB)
I/O Type
Min (ms)
Typ (ms)
Max (ms)
Condition
GPIO bank
0.04
0.14
0.24
GPIO configured for 3.3V operation
HSIO bank
0.11
0.20
0.30
HSIO configured for 1.8V operation
Note: In order to obtain fast re-calibration, the user must assert the relevant clock request signal from the FPGA
fabric to the I/O bank controller.
5.10
Dedicated Pins
The following section describes the dedicated pins.
5.10.1
JTAG Switching Characteristics
The following table describes characteristics of JTAG switching.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 93
AC Switching Characteristics
Table 5-98. JTAG Electrical Characteristics
5.10.2
Symbol
Description
Min
Typ
Max
Unit
Condition
TDISU
TDI input setup time
0.0
—
—
ns
—
TDIHD
TDI input hold time
2.0
—
—
ns
—
TTMSSU
TMS input setup time
1.5
—
—
ns
—
TTMSHD
TMS input hold time
1.5
—
—
ns
—
FTCK
TCK frequency
—
—
25
MHz
—
TTCKDC
TCK duty cycle
40
—
60
%
—
TTDOCQ
TDO clock to Q out
—
—
8.4
ns
CLOAD = 40 pf
TRSTBCQ
TRSTB clock to Q out
—
—
23.5
ns
CLOAD = 40 pf
TRSTBPW
TRSTB min pulse width
50
—
—
ns
—
TRSTBREM
TRSTB removal time
0.0
—
—
ns
—
TRSTBREC
TRSTB recovery time
12.0
—
—
ns
—
CINTDI
TDI input pin capacitance
—
—
5.3
pf
—
CINTMS
TMS input pin capacitance
—
—
5.3
pf
—
CINTCK
TCK input pin capacitance
—
—
5.3
pf
—
CINTRSTB
TRSTB input pin capacitance
—
—
5.3
pf
—
SPI Switching Characteristics
The following tables describe characteristics of SPI switching.
Table 5-99. SPI Initiator Mode (PolarFire Initiator)
Parameter
Symbol Min
Typ Max Unit Condition
SCK frequency
sp1
—
—
20
MHz During Programming
40
Mhz During Initialization
SCK minimum pulse width high sp2
SCK_period/2
—
—
ns
—
SCK minimum pulse width low
sp3
SCK_period/2
—
—
ns
—
Rise and fall time
sp4
—
—
—
ns
Refer to PolarFire IBIS models3
sp5
SDO setup time
sp6m
(SCK_period/2) – 3.0 —
—
ns
—
SDO hold time
sp7m
(SCK_period/2) – 2.0 —
—
ns
—
SDI setup time
sp8m
10.0
—
—
ns
—
SDI hold time
sp9m
–1.0
—
—
ns
—
Notes:
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 94
AC Switching Characteristics
1.
2.
3.
Parameters are referenced to the active edge of SCK, which depends on the configured SPI protocol (for
example, Motorola SPI mode uses rising edge as active edge if SPO = 0).
SDI is clocked into SPI on active edge and clocked out on inactive edge. Therefore, SDO delay parameters
are dependent on SCK frequency (nominally SCK_period/2).
For specific rise/fall times, board design considerations, and detailed output buffer resistances, use the
corresponding IBIS models located online at IBIS Models: PolarFire.
Table 5-100. SPI Target Mode (PolarFire Target)
Parameter
Symbol Min
Typ Max Unit Condition
SCK frequency
sp1
—
—
80
MHz —
SCK minimum pulse width high sp2
SCK_period/2
—
—
ns
—
SCK minimum pulse width low
sp3
SCK_period/2
—
—
ns
—
Rise and fall time
sp4
—
—
—
ns
Refer to PolarFire IBIS models3
sp5
SDO setup time
sp6s
(SCK_period/2) – 8.0 —
—
ns
—
SDO hold time
sp7s
SCK_period/2
—
—
ns
—
SDI setup time
sp8s
4.0
—
—
ns
—
SDI hold time
sp9s
2.0
—
—
ns
—
Notes:
1.
2.
3.
Parameters are referenced to the active edge of SCK, which depends on the configured SPI protocol (for
example, Motorola SPI mode uses rising edge as active edge if SPO = 0).
SDI is clocked into SPI on active edge and clocked out on inactive edge. Therefore, SDO delay parameters
are dependent on SCK frequency (nominally SCK_period/2).
For specific rise/fall times, board design considerations, and detailed output buffer resistances, use the
corresponding IBIS models located online at IBIS Models: PolarFire.
Figure 5-9. SPI Timing for a Single Frame Transfer in Motorola Mode (SPH = 1)
5.10.3
SmartDebug Probe Switching Characteristics
The following table describes characteristics of SmartDebug probe switching.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 95
AC Switching Characteristics
Table 5-101. SmartDebug Probe Performance Characteristics
Parameter
5.10.4
Symbol
VDD = 1.0V
VDD = 1.0V
VDD = 1.05V
VDD = 1.05V
STD
–1
STD
–1
Unit
Maximum frequency of
probe signal
FMAX
100
100
100
100
MHz
Minimum delay of
probe signal
TMin_delay
—
—
—
—
ns
Maximum delay of
probe signal
TMax_delay
—
—
—
—
ns
DEVRST_N Switching Characteristics
The following table describes characteristics of DEVRST_N switching.
Table 5-102. DEVRST_N Electrical Characteristics
5.11
Parameter
Symbol
Min Typ Max Unit Condition
DEVRST_N ramp time
DRRAMP
—
10
—
μs
It must be a normal clean digital signal, with
typical rise and fall times.
DEVRST_N assert time
DRASSERT
1
—
—
μs
The minimum time for DEVRST_N assertion to be
recognized.
DEVRST_N de-assert
time
DRDEASSERT 2.75 —
—
ms
The minimum time DEVRST_N needs to be deasserted before assertion.
User Crypto
The following section describes user crypto.
5.11.1
TeraFire 5200B Switching Characteristics
The following table describes TeraFire 5200B switching characteristics.
Table 5-103. TeraFire F5200B Switching Characteristics
Parameter
5.11.2
Symbol
VDD =
VDD =
VDD =
VDD =
1.0V
1.0V
1.05V
1.05V
STD
–1
STD
–1
Unit
Condition
FMAX with DLL
FMAX_DLL
189
189
189
189
MHz
–40 °C to 100 °C
FMIN with DLL
FMIN_DLL
125
125
125
125
MHz
–40 °C to 100 °C
FMAX with DLL in bypass mode
FMAX_DLL_BYPASS
70
70
70
70
MHz
–40 °C to 100 °C
FMIN with DLL in bypass mode
FMIN_DLL_BYPASS
0
0
0
0
MHz
–40 °C to 100 °C
TeraFire 5200B Throughput Characteristics
The following tables for each algorithm describe the TeraFire 5200B throughput characteristics. Adding the 2 columns
clock counts on any given row will yield the expected performance for that algorithm and message size.
Note: Throughput cycle count collected with Athena TeraFire Core and a soft RISC-V CPU running at 70 MHz.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 96
AC Switching Characteristics
Table 5-104. AES
Modes
Message Size (Bits) Athena TeraFire
Crypto Core ClockCycles
RISC-V CPU
Clock-Cycles
AES-ECB-128 encrypt1
128
511
1011
64K
48109
927
128
557
1328
64K
48385
1282
128
527
1333
64K
56301
1303
128
589
1356
64K
56673
1410
128
588
1316
64K
58691
1286
128
617
1676
64K
56853
1730
AES-GCM-128 encrypt1, 128-bit tag, (full
message encrypted/authenticated)
128
1921
1701
64K
58022
1640
AES-GCM-256 encrypt1, 128-bit tag, (full
message encrypted/authenticated)
128
1969
1718
64K
58054
1803
AES-ECB-128 decrypt1
AES-ECB-256 encrypt1
AES-ECB-256 decrypt1
AES-CBC-256 encrypt1
AES-CBC-256 decrypt1
1.
With DPA counter measures.
Table 5-105. GMAC
Modes
Message Size
(Bits)
Athena TeraFire
Crypto Core ClockCycles
RISC-V CPU ClockCycles
AES-GCM-2561, 128-bit tag, (message is
only authenticated)
128
1859
1752
64K
47659
1854
1.
With DPA counter measures.
Table 5-106. HMAC
Modes
Message Size (Bits) Athena TeraFire Crypto Core
Clock-Cycles
HMAC-SHA-2561, 256-bit key 512
64K
© 2021 Microchip Technology Inc.
and its subsidiaries
RISC-V CPU Clock-Cycles
7461
1616
86319
1350
Datasheet
DS00003831B-page 97
AC Switching Characteristics
...........continued
Modes
Message Size (Bits) Athena TeraFire Crypto Core
Clock-Cycles
HMAC-SHA-3841, 384-bit key 1024
64K
1.
RISC-V CPU Clock-Cycles
13017
1438
104055
1438
With DPA counter measures.
Table 5-107. CMAC
Modes
Message Size (Bits) Athena TeraFire Crypto RISC-V CPU ClockCore Clock-Cycles
Cycles
AES-CMAC-2561 (message is only
authenticated)
128
446
8434
64K
45494
110209
1.
With DPA counter measures.
Table 5-108. KEY TREE
Modes
Message Size (Bits) Athena TeraFire Crypto Core
Clock-Cycles
RISC-V CPU Clock-Cycles
128-bit nonce + 8-bit optype —
102457
2173
256-bit nonce + 8-bit optype —
103218
2359
Table 5-109. SHA
Modes
Message Size (Bits)
Athena TeraFire Crypto Core Clock-Cycles
RISC-V CPU Clock-Cycles
SHA-11
512
2370
816
64K
75528
709
512
2500
656
64K
82704
656
1024
4122
712
64K
98174
656
1024
4122
652
64K
98174
653
SHA-2561
SHA-3841
SHA-5121
1.
With DPA counter measures.
Table 5-110. ECC
Modes
Message Size (Bits) Athena TeraFire Crypto
Core Clock-Cycles
ECDSA SigGen, P-384/SHA-3841 1024
8K
© 2021 Microchip Technology Inc.
and its subsidiaries
RISC-V CPU ClockCycles
12525647
5072
12540387
5072
Datasheet
DS00003831B-page 98
AC Switching Characteristics
...........continued
Modes
Message Size (Bits) Athena TeraFire Crypto
Core Clock-Cycles
RISC-V CPU ClockCycles
ECDSA SigGen, P-384/SHA-384
1024
5502896
5071
8K
5513718
5071
1024
6243821
4683
8K
6321110
4422
1024
6243821
4422
8K
6321110
4422
Key Agreement (KAS), P-384
—
5039125
10318
Point Multiply, P-2561
—
5177474
4434
Point Multiply, P-3841
—
12055519
5086
Point Multiply, P-5211
—
26889271
6470
Point Addition, P-384
—
3018067
5303
KeyGen (PKG), P-384
—
12052230
7909
Point Verification, P-384
—
5091
3354
ECDSA SigVer, P-384/SHA-3841
ECDSA SigVer, P-384/SHA-384
1.
With DPA counter measures.
Table 5-111. IFC (RSA)
Modes
Message
Size (Bits)
Athena TeraFire Crypto
Core Clock-Cycles
RISC-V CPU ClockCycles
Encrypt, RSA-2048, e=65537
2048
436972
8287
Encrypt, RSA-3072, e=65537
3072
962162
12063
Decrypt, RSA-20481, CRT
2048
26847616
15261
Decrypt, RSA-30721, CRT
3072
75168689
22488
Decrypt, RSA-4096, CRT
4096
88789629
23585
Decrypt, RSA-3072, CRT
3072
38202717
18838
SigGen, RSA-3072/SHA-3841 ,CRT, PKCS
#1 V 1 1.5
1024
75156973
19562
8K
75222026
18880
SigGen, RSA-3072/SHA-384, PKCS #1, V
1.5
1024
148092303
13622
8K
148102319
13622
SigVer, RSA-3072/SHA-384, e = 65537,
PKCS #1 V 1.5
1024
970959
11769
8K
981755
11769
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 99
AC Switching Characteristics
...........continued
Modes
Message
Size (Bits)
Athena TeraFire Crypto
Core Clock-Cycles
RISC-V CPU ClockCycles
SigVer, RSA-2048/SHA-256, e = 65537,
PKCS #1 V 1.5
1024
443593
8490
8K
452751
8443
SigGen, RSA-3072/SHA-384, ANSI X9.31
1024
147143879
13624
8K
147153109
13417
1024
972788
11268
8K
983643
11215
SigVer, RSA-3072/SHA-384, e = 65537,
ANSI X9.31
1.
With DPA counter measures.
Table 5-112. FFC (DH)
Modes
Message Size
(Bits)
Athena TeraFire
Crypto Core ClockCycles
RISC-V CPU
Clock-Cycles
SigGen, DSA-3072/SHA-3841
1024
27932434
13271
8K
27946636
13166
1024
12086324
13028
8K
12097138
12862
1024
24711796
14689
8K
24418930
14689
1024
9673222
10717
8K
9803028
10717
Key Agreement (KAS), DH-3072
(p=3072,security=256)
—
4920705
9519
Key Agreement (KAS), DH-3072
(p=3072,security=256)1
—
78871914
9495
SigGen, DSA-3072/SHA-384
SigVer, DSA-3072/SHA-384
SigVer, DSA-2048/SHA-256
1.
With DPA counter measures.
Table 5-113. NRBG
Modes
Message Size
(Bits)
Athena TeraFire
Crypto Core
Clock-Cycles
RISC-V CPU
Clock-Cycles
Instantiate: strength, s=256, 384-bit nonce, 384-bit
personalization string
—
18221
3076
Reseed: no additional input, s=256
—
13585
1056
Reseed: 384-bit additional input, s=256
—
15922
995
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 100
AC Switching Characteristics
...........continued
Modes
Message Size
(Bits)
Athena TeraFire
Crypto Core
Clock-Cycles
RISC-V CPU
Clock-Cycles
Generate: (no additional input), prediction resistance
enabled, s=256
128
15262
1672
8K
27169
7837
Generate: (no additional input), prediction resistance
disabled, s=256
128
2138
781
8K
14045
7837
Generate: (384-bit additional input), prediction
resistance enabled, s=256
128
21299
1620
8K
33206
8563
Generate: (384-bit additional input), prediction
resistance disabled, s=256
128
11657
1507
8K
23564
8563
Un-instantiate
—
761
502
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 101
Revision History
6.
Revision History
Revision
Date
B
10/2021
Description
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
A
02/2021
•
•
•
•
•
•
© 2021 Microchip Technology Inc.
and its subsidiaries
Added AECQ-100 to Table 1. PolarFire Minimum and Maximum Junction
Temperatures by Temperature Grade.
Added the MPF050 to Table 3-2. PolarFire FPGA Tool Status.
Added note 3 under Table 4-1. Absolute Maximum Rating.
Changed the name LVDS18 for GPIO to LVDS18G in Table 4-17. Differential DC
Input Levels.
Added a row for LVDS18G in Table 4-18. Differnetial DC Ouptut Level.
Added a LVDS18G row to Table 5-4. GPIO Maximum Input Buffer Speed.
Added a LVDS18G row to Table 5-6. GPIO Maximum Output Buffer Speed.
Removed DDR3L from the footnote under Table 5-7. Maximum PHY Rate for
Memory Interfaces IP for HSIO Banks.
Added a LVDS18G row to Table 5-14. I/O CDR Switching Characteristics.
Added footnote 8 under Table 5-30. PolarFire Transceiver Reference Clock AC
Requirements that relaxes the reference clock requirements if additional jitter is
acceptable.
Changed references from VDDSREF to XCVRVREF in section Transceiver Reference
Clock I/O Standards to align with Table 4-2. Recommended Operating Conditions.
Added footnote 14 under Table 5-36. PolarFire Transcevier Transmitter
Characteristics that relaxes the reference clock requirements if additional jitter is
acceptable
Clarified that programming, verify, and zeroization operations all count as a
programming cycle. For more information, see section FPGA and μPROM
Programming Cycle and Retention.
Table 5-62. SPI Initiator and Auto-Update Programming Time (IAP) was updated to
now reference auto-update programming times.
Clarified Notes section under Table 5-74. Standalone Fabric Verify Times.
Clarified table headers and notes in section User Crypto.
Clarified that μPROM NVM characteristics are the same as the FPGA fabric as the
μPROM is constructed from the same NVM switch. For more information, see section
FPGA and μPROM Programming Cycle and Retention.
Updated document to Microchip template.
Updated document number from DS51700141 to DS00003831.
Added automotive and military temperature-grade specifications.
Increased MIPI TX speeds from 800 Mbps to 1000 Mbps for STD speed grade.
Removed digest junction temperature from the table Maximum Number of Digest
Cycles as it has no effect on device retention.
Added SDI 6G and 12G rates.
Datasheet
DS00003831B-page 102
Revision History
...........continued
Revision
Date
1.8
11/2020
Description
•
•
•
•
•
•
•
– I/O Digital Receive Single-Data Rate Switching Characteristics 1
– I/O Digital Receive Double Data Rate Switching Characteristics 4
– I/O Digital Transmit Single Data Rate Switching Characteristics 2
– I/O Digital Transmit Double Data Rate Switching Characteristics
Included a +/- maximum specification in addition to the absolute maximum
specification for "PLL ouput period jitter" in PLL Electrical Characteristics.
Added footnote 11 to PLL Electrical Characteristics to direct customers to contact
technical support for protocol-specific jitter characteristics.
Updated values in LSRAM Performance Industrial Temperature Range (–55 °C to
125 °C) .
Added transceiver loopback rates and two footnotes to PolarFire Transceiver and
TXPLL Performance.
Updated transceiver refclk inputs from 156 MHz to 156.3 MHz in PolarFire
Transceiver Reference Clock AC Requirements.
Added min/max specifications to "Differential termination" in PolarFire Transceiver
Transmitter Characteristics and PolarFire Transceiver Receiver Characteristics.
Made the following updates to Display Port:
•
– Added 8.1 Gbps data rates.
– Clarified total receive jitter tolerance for 5.4 Gbps data rate.
– Added footnote to total transmit jitter for 5.4 Gbps data rate max.
Made the following updates to FireWire IEEE 1394:
•
•
•
•
•
•
•
•
•
•
© 2021 Microchip Technology Inc.
and its subsidiaries
Added footnote 3 to clarify mixed I/O receiver capability for DC Input Levels.
Clarified GPIO VICM and HSIO VICM rules in footnote 3 in Differential DC Input
Levels.
Added Input Hysteresis Characteristics over Recommended Operating Conditions.
Added minimum DDR memory data rates to Maximum PHY Rate for Memory
Interfaces IP for HSIO Banks and Maximum PHY Rate for Memory Interfaces IP
for GPIO Banks.
Corrected FMAX values for QDR memories from 113 MHz to 112.5 MHz in Maximum
PHY Rate for Memory Interfaces IP for GPIO Banks.
Added note to indicate which IOD delay setting was used to achieve the
specifications for the following tables:
– Added FireWire S200 specifications.
– Lowered FireWire S400 Tx jitter from 557 ps to 516 ps.
– Clarified FireWire S800 amplitude specification.
Added SLVS-EC.
Deleted Table 103 SPI Macro Interface Timing Characteristics and replaced with
PF_SPI Master Programming Switching Characteristics. To determine timing of the
user SPI macro from the fabric, please use SmartTime.
Updated the signal name AVM_ACTIVE to SUSPEND_EN in Cold Reset Timing and
Warm Reset Timing.
Clarified device behavior in description underneath I/O-Related Supplies.
Datasheet
DS00003831B-page 103
Revision History
...........continued
Revision
Date
1.7
12/2019
Description
•
•
•
•
•
•
•
•
•
1.6
06/2019
•
•
•
•
•
•
•
•
•
•
•
© 2021 Microchip Technology Inc.
and its subsidiaries
Updated table PolarFire FPGA Silicon Status. Libero 12.2 now contains production
timing and power for all devices.
Corrected footnote 5 in the table PolarFire Transceiver Reference Clock AC
Requirements.
Corrected footnote in the table sNVM Programming Cycles vs. Retention
Characteristics.
Added timing parameters to the table Master SPI Programming Time (IAP) and table
Slave SPI Programming Time.
Added 270 mbps rates to the section SDI.
Added FireWire section.
Added footnotes to the following tables:
– Recommended Operating Conditions
– I/O Digital Receive Double Data Rate Switching Characteristics
– I/O Digital Transmit Single Data Rate Switching Characteristics
– I/O Digital Transmit Double Data Rate Switching Characteristics
– HSIO Maximum Input Buffer Speed
– HSIO Maximum Output Buffer Speed
– GPIO Maximum Output Buffer Speed
– Programmable Delay
Added MIPI data rates to the following tables:
– GPIO Maximum Input Buffer Speed
– GPIO Maximum Output Buffer Speed
Updated MIPIE25 output DC specifications.
The parameter RX_DDRX_B_G_FA (for Video7 applications) was added. For
more information, see table I/O Digital Receive Double-Data Rate Switching
Characteristics.
I/O CDR switching characteristics were added. For more information, see table I/O
CDR Switching Characteristics.
High-speed I/O clock skew with bridging was added. For more information, see table
High-Speed I/O Clock Characteristics (–40 °C to 100 °C).
PCS and PMA minimum reset pulse widths were added. For more information, see
table PolarFire Transceiver and TXPLL Performance.
Auto adaptive calibration was added to CDR lock times, Burst Mode Receiver (BMR)
high-gain lock time, and BMR high-gain state time. For more information, see table
PolarFire Transceiver Receiver Characteristics.
Fiber channel rates were corrected. For more information, see table Fiber Channel.
HiGig and HiGig+ specifications were updated. For more information, see table HiGig
and HiGig+.
HiGig II specifications were updated. For more information, see table HiGigII.
The DEVRST_N parameter was correctly classified as ramp time. For more
information, see section Dedicated Pins.
Transmitter and receiver return loss characteristics were added. For more
information, see section Transceiver Switching Characteristics.
Voltage detector specifications were added and the voltage glitch detector was
removed. For more information, see section User Voltage Detector Characteristics.
Datasheet
DS00003831B-page 104
Revision History
...........continued
Revision
Date
1.5
Description
•
•
All tables have been reviewed and updated to reflect production silicon
characteristics for the 200T, 200TL, 200TS, 200TLS, 100T, 100TL, 100TS, and
100TLS devices in all packages, speed grades, and temperature grades.
The maximum transceiver reference clock input rate was changed from 800 MHz
to 400 MHz due to a typo in version 1.4. For more information, see table PolarFire
Transceiver Reference Clock AC Requirements.
1.4
09/2018
•
All tables have been reviewed and updated to reflect production silicon
characteristics for the 300T, 300TL, 300TS, and 300TLS devices in all packages,
speed grades, and temperature grades.
1.3
06/2018
•
•
•
•
The System Services section was updated.
The Non-Volatile Characteristics section was updated.
The Fabric Macros section was updated.
The Transceiver Switching Characteristics section was updated.
1.2
06/2018
•
The datasheet has moved to preliminary status. Every table has been updated.
1.1
08/2017
•
•
•
•
LVDS specifications changed to 1.25G.
LVDS18, LVDS25/LVDS33, and LVDS25 specifications changed to 800 Mbps.
A note was added indicting a zeroization cycle counts as a programming cycle.
A note was added defining power down conditions for programming recovery
conditions.
1.0
Initial Revision
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 105
The Microchip Website
Microchip provides online support via our website at www.microchip.com/. This website is used to make files and
information easily available to customers. Some of the content available includes:
•
•
•
Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online
discussion groups, Microchip design partner program member listing
Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of
seminars and events, listings of Microchip sales offices, distributors and factory representatives
Product Change Notification Service
Microchip’s product change notification service helps keep customers current on Microchip products. Subscribers will
receive email notification whenever there are changes, updates, revisions or errata related to a specified product
family or development tool of interest.
To register, go to www.microchip.com/pcn and follow the registration instructions.
Customer Support
Users of Microchip products can receive assistance through several channels:
•
•
•
•
Distributor or Representative
Local Sales Office
Embedded Solutions Engineer (ESE)
Technical Support
Customers should contact their distributor, representative or ESE for support. Local sales offices are also available to
help customers. A listing of sales offices and locations is included in this document.
Technical support is available through the website at: www.microchip.com/support
Microchip Devices Code Protection Feature
Note the following details of the code protection feature on Microchip products:
•
•
•
•
Microchip products meet the specifications contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is secure when used in the intended manner, within operating
specifications, and under normal conditions.
Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code
protection features of Microchip product is strictly prohibited and may violate the Digital Millennium Copyright
Act.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code
protection does not mean that we are guaranteeing the product is “unbreakable”. Code protection is constantly
evolving. Microchip is committed to continuously improving the code protection features of our products.
Legal Notice
This publication and the information herein may be used only with Microchip products, including to design, test,
and integrate Microchip products with your application. Use of this information in any other manner violates these
terms. Information regarding device applications is provided only for your convenience and may be superseded
by updates. It is your responsibility to ensure that your application meets with your specifications. Contact your
local Microchip sales office for additional support or, obtain additional support at www.microchip.com/en-us/support/
design-help/client-support-services.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 106
THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS
OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY
OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED
WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE,
OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE.
IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL, OR
CONSEQUENTIAL LOSS, DAMAGE, COST, OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW,
MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE
WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR
THE INFORMATION.
Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees
to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting
from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights
unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime,
BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity,
SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron,
and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed
Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC
Plus, ProASIC Plus logo, Quiet- Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra,
TimeProvider, TrueTime, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the
U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching,
BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController,
dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, GridTime,
IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip Connectivity,
JitterBlocker, Knob-on-Display, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified
logo, MPLIB, MPLINK, MultiTRAK, NetDetach, NVM Express, NVMe, Omniscient Code Generation, PICDEM,
PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAMICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-I.S., storClad, SQI, SuperSwitcher,
SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY,
ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, Symmcom, and Trusted Time are registered
trademarks of Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their respective companies.
©
2021, Microchip Technology Incorporated and its subsidiaries. All Rights Reserved.
ISBN: 978-1-5224-8384-7
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 107
Quality Management System
For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 108
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
www.microchip.com/support
Web Address:
www.microchip.com
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Austin, TX
Tel: 512-257-3370
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Tel: 951-273-7800
Raleigh, NC
Tel: 919-844-7510
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
Australia - Sydney
Tel: 61-2-9868-6733
China - Beijing
Tel: 86-10-8569-7000
China - Chengdu
Tel: 86-28-8665-5511
China - Chongqing
Tel: 86-23-8980-9588
China - Dongguan
Tel: 86-769-8702-9880
China - Guangzhou
Tel: 86-20-8755-8029
China - Hangzhou
Tel: 86-571-8792-8115
China - Hong Kong SAR
Tel: 852-2943-5100
China - Nanjing
Tel: 86-25-8473-2460
China - Qingdao
Tel: 86-532-8502-7355
China - Shanghai
Tel: 86-21-3326-8000
China - Shenyang
Tel: 86-24-2334-2829
China - Shenzhen
Tel: 86-755-8864-2200
China - Suzhou
Tel: 86-186-6233-1526
China - Wuhan
Tel: 86-27-5980-5300
China - Xian
Tel: 86-29-8833-7252
China - Xiamen
Tel: 86-592-2388138
China - Zhuhai
Tel: 86-756-3210040
India - Bangalore
Tel: 91-80-3090-4444
India - New Delhi
Tel: 91-11-4160-8631
India - Pune
Tel: 91-20-4121-0141
Japan - Osaka
Tel: 81-6-6152-7160
Japan - Tokyo
Tel: 81-3-6880- 3770
Korea - Daegu
Tel: 82-53-744-4301
Korea - Seoul
Tel: 82-2-554-7200
Malaysia - Kuala Lumpur
Tel: 60-3-7651-7906
Malaysia - Penang
Tel: 60-4-227-8870
Philippines - Manila
Tel: 63-2-634-9065
Singapore
Tel: 65-6334-8870
Taiwan - Hsin Chu
Tel: 886-3-577-8366
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Taiwan - Taipei
Tel: 886-2-2508-8600
Thailand - Bangkok
Tel: 66-2-694-1351
Vietnam - Ho Chi Minh
Tel: 84-28-5448-2100
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4485-5910
Fax: 45-4485-2829
Finland - Espoo
Tel: 358-9-4520-820
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Garching
Tel: 49-8931-9700
Germany - Haan
Tel: 49-2129-3766400
Germany - Heilbronn
Tel: 49-7131-72400
Germany - Karlsruhe
Tel: 49-721-625370
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Rosenheim
Tel: 49-8031-354-560
Israel - Ra’anana
Tel: 972-9-744-7705
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Padova
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Norway - Trondheim
Tel: 47-72884388
Poland - Warsaw
Tel: 48-22-3325737
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Gothenberg
Tel: 46-31-704-60-40
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
© 2021 Microchip Technology Inc.
and its subsidiaries
Datasheet
DS00003831B-page 109