PIC10(L)F320/322
6/8-Pin Flash-Based, 8-Bit Microcontrollers
High-Performance RISC CPU
• Only 35 Instructions to Learn:
- All single-cycle instructions, except branches
• Operating Speed:
- DC – 16 MHz clock input
- DC – 250 ns instruction cycle
• Eight-Level Deep Hardware Stack
• Interrupt Capability
• Processor Self-Write/Read access to Program
Memory
• Pinout Compatible to other 6-Pin PIC10FXXX
Microcontrollers
Memory
• Up to 512 Words of Flash Program Memory
• 64 Bytes Data Memory
• High-Endurance Flash Data Memory (HEF)
- 128B of nonvolatile data storage
- 100K erase/write cycles
Special Microcontroller Features
• Low-Power 16 MHz Internal Oscillator:
- Software selectable frequency range from
16 MHz to 31 kHz
- Factory calibrated to 1%, typical
• Wide Operating Range:
- 1.8V to 3.6V (PIC10LF320/322)
- 2.3V to 5.5V (PIC10F320/322)
• Power-on Reset (POR)
• Power-up Timer (PWRT)
• Brown-out Reset (BOR)
• Ultra Low-Power Sleep Regulator
• Extended Watchdog Timer (WDT)
• Programmable Code Protection
• Power-Saving Sleep mode
• Selectable Oscillator Options (EC mode or
Internal Oscillator)
• In-Circuit Serial Programming™ (ICSP™) (via
Two Pins)
• In-Circuit Debugger Support
• Fixed Voltage Reference (FVR) with 1.024V,
2.048V and 4.096V (‘F’ variant only) Output
Levels
• Integrated Temperature Indicator
• 40-year Flash Data Retention
2011-2021 Microchip Technology Inc.
eXtreme Low-Power (XLP) Features
(PIC10LF320/322)
• Sleep Current:
- 20 nA @ 1.8V, typical
• Operating Current:
- 25 A @ 1 MHz, 1.8V, typical
• Watchdog Timer Current:
- 500 nA @ 1.8V, typical
Peripheral Features
• Four I/O Pins:
- One input-only pin
- High current sink/source for LED drivers
- Individually selectable weak pull-ups
- Interrupt-on-Change
• Timer0: 8-Bit Timer/Counter with 8-Bit
Programmable Prescaler
• Timer2: 8-Bit Timer/Counter with 8-Bit Period
Register, Prescaler and Postscaler
• Two PWM Modules:
- 10-bit PWM, max. frequency 16 kHz
- Combined to single two-phase output
• A/D Converter:
- 8-bit resolution with three channels
• Configurable Logic Cell (CLC):
- Eight selectable input source signals
- Two inputs per module
- Software selectable logic functions including:
AND/OR/XOR/D Flop/D Latch/SR/JK
- External or internal inputs/outputs
- Operation while in Sleep
• Numerically Controlled Oscillator (NCO):
- 20-bit accumulator
- 16-bit increment
- Linear frequency control
- High-speed clock input
- Selectable Output modes
- Fixed Duty Cycle (FDC)
- Pulse Frequency (PF) mode
• Complementary Waveform Generator (CWG):
- Selectable falling and rising edge dead-band
control
- Polarity control
- Two auto-shutdown sources
- Multiple input sources: PWM, CLC, NCO
DS40001585E-page 1
PIC10(L)F320/322
Data Sheet Index:
1: DS40001585
Note:
Debug(1)
XLP
PIC10(L)F320 (1) 256
64
128 4
3
2
2
1
1
1
PIC10(L)F322 (1) 512
64
128 4
3
2
2
1
1
1
Note 1: I - Debugging, Integrated on Chip; H - Debugging, Available using Debug Header;
E - Emulation, Available using Emulation Header.
2: One pin is input-only.
Numerically Controlled
Oscillator (NCO)
Fixed Voltage
Reference (FVR)
Configurable Logic
Cell (CLC)
Complementary Wave
Generator (CWG)
PWM
Timers
(8-Bit)
8-Bit ADC (ch)
I/O’s(2)
High Endurance Flash (bytes)
Data SRAM
(bytes)
Program Memory
Flash (words)
Device
Data Sheet Index
PIC10(L)F320/322 Family Types
1
1
H
H
Y
Y
PIC10(L)F320/322 Data Sheet, 6/8 Pin High Performance, Flash Microcontrollers.
For other small form-factor package availability and marking information, please visit
http://www.microchip.com/packaging or contact your local sales office.
DS40001585E-page 2
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
FIGURE 1:
6-PIN DIAGRAM, PIC10(L)F320/322
SOT-23
ICSPDAT/RA0 1
PIC10(L)F320
PIC10(L)F322
VSS 2
ICSPCLK/RA1 3
FIGURE 2:
6
RA3/MCLR/VPP
5
VDD
4
RA2
8-PIN DIAGRAM, PIC10(L)F320/322
PDIP, DFN
N/C 1
RA2 3
ICSPCLK/RA1 4
TABLE 1:
I/O
8 RA3/MCLR/VPP
PIC10(L)F320
PIC10(L)F322
VDD 2
7 VSS
6 N/C
5 RA0/ICSPDAT
6 AND 8-PIN ALLOCATION TABLE, PIC10(L)F320/322
6-Pin 8-Pin Analog Timer
PWM
Interrupts Pull-ups
CWG
NCO
CLC
Basic
ICSP
RA0
1
5
AN0
—
PWM1
IOC0
Y
CWG1A
—
CLC1IN0
—
ICSPDAT
RA1
3
4
AN1
—
PWM2
IOC1
Y
CWG1B
NCO1CLK
CLC1
CLKIN
ICSPCLK
RA2
4
3
AN2
T0CKI
—
INT/IOC2
Y
CWG1FLT
NCO1
CLC1IN1
CLKR
RA3
6
8
—
—
—
IOC3
Y
—
—
—
MCLR
VPP
N/C
—
1
—
—
—
—
—
—
—
—
—
—
N/C
—
6
—
—
—
—
—
—
—
—
—
—
VDD
5
2
—
—
—
—
—
—
—
—
VDD
—
VSS
2
7
—
—
—
—
—
—
—
—
VSS
—
2011-2021 Microchip Technology Inc.
DS40001585E-page 3
PIC10(L)F320/322
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 6
2.0 Memory Organization ................................................................................................................................................................... 9
3.0 Device Configuration .................................................................................................................................................................. 19
4.0 Oscillator Module........................................................................................................................................................................ 24
5.0 Resets ........................................................................................................................................................................................ 28
6.0 Interrupts .................................................................................................................................................................................... 35
7.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 44
8.0 Watchdog Timer ......................................................................................................................................................................... 46
9.0 Flash Program Memory Control ................................................................................................................................................. 50
10.0 I/O Port ....................................................................................................................................................................................... 67
11.0 Interrupt-On-Change .................................................................................................................................................................. 73
12.0 Fixed Voltage Reference (FVR) ................................................................................................................................................. 77
13.0 Internal Voltage Regulator (IVR) ................................................................................................................................................ 79
14.0 Temperature Indicator Module ................................................................................................................................................... 81
15.0 Analog-to-Digital Converter (ADC) Module ................................................................................................................................ 83
16.0 Timer0 Module ........................................................................................................................................................................... 93
17.0 Timer2 Module ........................................................................................................................................................................... 96
18.0 Pulse-Width Modulation (PWM) Module .................................................................................................................................... 98
19.0 Configurable Logic Cell (CLC).................................................................................................................................................. 104
20.0 Numerically Controlled Oscillator (NCO) Module ..................................................................................................................... 119
21.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 129
22.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 144
23.0 Instruction Set Summary .......................................................................................................................................................... 147
24.0 Electrical Specifications............................................................................................................................................................ 156
25.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 176
26.0 Development Support............................................................................................................................................................... 177
27.0 Packaging Information.............................................................................................................................................................. 181
Appendix A: Data Sheet Revision History.......................................................................................................................................... 189
DS40001585E-page 4
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Website; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
Customer Notification System
Register on our website at www.microchip.com to receive the most current information on all of our products.
2011-2021 Microchip Technology Inc.
DS40001585E-page 5
PIC10(L)F320/322
1.0
DEVICE OVERVIEW
The PIC10(L)F320/322 are described within this data
sheet. They are available in 6/8-pin packages. Figure 1-1
shows a block diagram of the PIC10(L)F320/322
devices. Table 1-2 shows the pinout descriptions.
Reference Table 1-1 for peripherals available per
device.
Peripheral
PIC10(L)F322
DEVICE PERIPHERAL
SUMMARY
PIC10(L)F320
TABLE 1-1:
Analog-to-Digital Converter (ADC)
●
●
Configurable Logic Cell (CLC)
●
●
Complementary Wave Generator (CWG)
●
●
Fixed Voltage Reference (FVR)
●
●
Numerically Controlled Oscillator (NCO)
●
●
Temperature Indicator
●
●
PWM1
●
●
PWM2
●
●
Timer0
●
●
Timer2
●
●
PWM Modules
Timers
DS40001585E-page 6
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
FIGURE 1-1:
PIC10(L)F320/322 BLOCK DIAGRAM
Program
Flash Memory
RAM
CLKR
PORTA
Timing
Generation
CLKIN
CPU
INTRC
Oscillator
Figure 2-1
MCLR
Timer0
Temp.
Indicator
Note
1:
ADC
8-Bit
Timer2
FVR
PWM1
PWM2
NCO
CLC
CWG
See applicable chapters for more information on peripherals.
2011-2021 Microchip Technology Inc.
DS40001585E-page 7
PIC10(L)F320/322
TABLE 1-2:
PIC10(L)F320/322 PINOUT DESCRIPTION
Name
RA0/PWM1/CLC1IN0/CWG1A/
AN0/ICSPDAT
RA1/PWM2/CLC1/CWG1B/AN1/
CLKIN/ICSPCLK/NCO1CLK
RA2/INT/T0CKI/NCO1/CLC1IN1/
CLKR/AN2/CWG1FLT
RA3/MCLR/VPP
Function
Input
Type
RA0
TTL
PWM1
—
CLC1IN0
ST
CWG1A
—
Output
Type
Description
CMOS General purpose I/O with IOC and WPU.
CMOS PWM output.
—
CLC input.
CMOS CWG primary output.
AN0
AN
ICSPDAT
ST
CMOS ICSP™ Data I/O.
—
A/D Channel input.
CMOS General purpose I/O with IOC and WPU.
RA1
TTL
PWM2
—
CMOS PWM output.
CLC1
—
CMOS CLC output.
CWG1B
—
CMOS CWG complementary output.
AN1
AN
—
A/D Channel input.
CLKIN
ST
—
External Clock input (EC mode).
ICSPCLK
ST
—
ICSP™ Programming Clock.
NCO1CLK
ST
—
Numerical Controlled Oscillator external clock input.
RA2
TTL
INT
ST
—
External interrupt.
T0CKI
ST
—
Timer0 clock input.
NCO1
—
CLC1IN1
ST
CLKR
—
AN2
AN
—
A/D Channel input.
CWG1FLT
ST
—
Complementary Waveform Generator Fault 1 source input.
General purpose input.
CMOS General purpose I/O with IOC and WPU.
CMOS Numerically Controlled Oscillator output.
—
CLC input.
CMOS Clock Reference output.
RA3
TTL
—
MCLR
ST
—
Master Clear with internal pull-up.
VPP
HV
—
Programming voltage.
VDD
VDD
Power
—
Positive supply.
VSS
VSS
Power
—
Ground reference.
Legend: AN = Analog input or output
TTL = CMOS input with TTL levels
HV = High Voltage
DS40001585E-page 8
CMOS = CMOS compatible input or output
ST
= CMOS input with Schmitt Trigger levels
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
2.0
MEMORY ORGANIZATION
These devices contain the following types of memory:
• Program Memory
- Configuration Word
- Device ID
- User ID
- Flash Program Memory
• Data Memory
- Core Registers
- Special Function Registers
- General Purpose RAM
- Common RAM
2.1
Program Memory Organization
The mid-range core has a 13-bit program counter
capable of addressing 8K x 14 program memory space.
This device family only implements up to 512 words of
the 8K program memory space. Table 2-1 shows the
memory sizes implemented for the PIC10(L)F320/322
family. Accessing a location above these boundaries will
cause a wrap-around within the implemented memory
space. The Reset vector is at 0000h and the interrupt
vector is at 0004h (see Figures 2-1, and 2-2).
The following features are associated with access and
control of program memory and data memory:
• PCL and PCLATH
• Stack
• Indirect Addressing
TABLE 2-1:
DEVICE SIZES AND ADDRESSES
Program Memory
Space (Words)
Last Program Memory
Address
High-Endurance Flash
Memory Address Range (1)
PIC10(L)F320
256
00FFh
0080h-00FFh
PIC10(L)F322
512
01FFh
0180h-01FFh
Device
Note 1: High-endurance Flash applies to the low byte of each address in the range.
2011-2021 Microchip Technology Inc.
DS40001585E-page 9
PIC10(L)F320/322
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK FOR
PIC10(L)F320
FIGURE 2-2:
PROGRAM MEMORY MAP
AND STACK FOR
PIC10(L)F322
PC
PC
CALL,
RETURN, RETLW
RETFIE
CALL
RETURN, RETLW
RETFIE
13
13
Stack Level 0
Stack Level 1
Stack Level 0
Stack Level 1
Stack Level 8
Stack Level 8
Reset Vector
0000h
Reset Vector
0000h
Interrupt Vector
0004h
0005h
Interrupt Vector
0004h
0005h
On-chip
Program
Memory
Page 0
Rollover to Page 0
Wraps to Page 0
00FFh
0100h
On-chip
Program
Memory
Page 0
Wraps to Page 0
Rollover to Page 0
Wraps to Page 0
Wraps to Page 0
Wraps to Page 0
Rollover to Page 0
DS40001585E-page 10
FFFh
Rollover to Page 0
01FFh
0200h
FFFh
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
2.2
Data Memory Organization
The data memory is in one bank, which contains the
General Purpose Registers (GPR) and the Special
Function Registers (SFR). The RP bits of the
STATUS register are the bank select bits.
RP1
0
RP0
0
Bank 0 is selected
The bank extends up to 7Fh (128 bytes). The lower
locations of the bank are reserved for the Special Function Registers. Above the Special Function Registers
are the General Purpose Registers, implemented as
Static RAM.
2.2.1
GENERAL PURPOSE REGISTER
FILE
The register file is organized as 64 x 8 in the
PIC10(L)F320/322. Each register is accessed, either
directly or indirectly, through the File Select Register
(FSR) (see Section 2.4 “Indirect Addressing, INDF
and FSR Registers”).
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Table 2-3). These
registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral features
are described in the section of that peripheral feature.
2011-2021 Microchip Technology Inc.
DS40001585E-page 11
PIC10(L)F320/322
2.2.2.1
STATUS Register
The STATUS register, shown in Register 2-1, contains:
• the arithmetic status of the ALU
• the Reset status
• the bank select bits for data memory (SRAM)
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any Status bits. For other instructions not affecting any Status bits (see Section 23.0 “Instruction Set
Summary”).
Note 1: Bits IRP and RP1 of the STATUS register
are not used by the PIC10(L)F320 and
will be maintained as clear. Use of these
bits is not recommended, since this may
affect upward compatibility with future
products.
2: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction.
DS40001585E-page 12
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
REGISTER 2-1:
STATUS: STATUS REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R-1/q
R-1/q
R/W-x/u
R/W-x/u
R/W-x/u
IRP
RP1
RP0
TO
PD
Z
DC
C
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
IRP: Reserved(2)
bit 6-5
RP: Reserved(2)
bit 4
TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3
PD: Power-Down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0
C: Carry/Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of
the source register.
2: Maintain as ‘0’.
2011-2021 Microchip Technology Inc.
DS40001585E-page 13
PIC10(L)F320/322
2.2.3
DEVICE MEMORY MAPS
The memory maps for PIC10(L)F320/322 are as shown
in Table 2-2.
TABLE 2-2:
PIC10(L)F320/322 MEMORY MAP (BANK 0)
INDF(*)
00h
PMADRL
20h
TMR0
01h
PMADRH
21h
PCL
02h
PMDATL
22h
STATUS
03h
PMDATH
23h
FSR
04h
PMCON1
24h
PORTA
05h
PMCON2
25h
TRISA
06h
CLKRCON
26h
LATA
07h
NCO1ACCL
27h
ANSELA
08h
NCO1ACCH
28h
WPUA
09h
NCO1ACCU
29h
PCLATH
0Ah
NCO1INCL
2Ah
INTCON
0Bh
NCO1INCH
2Bh
PIR1
0Ch
Reserved
2Ch
PIE1
0Dh
NCO1CON
2Dh
OPTION_REG
0Eh
NCO1CLK
2Eh
2Fh
PCON
0Fh
Reserved
OSCCON
10h
WDTCON
30h
TMR2
11h
CLC1CON
31h
PR2
12h
CLC1SEL1
32h
T2CON
13h
CLC1SEL2
33h
PWM1DCL
14h
CLC1POL
34h
PWM1DCH
15h
CLC1GLS0
35h
PWM1CON
16h
CLC1GLS1
36h
PWM2DCL
17h
CLC1GLS2
37h
PWM2DCH
18h
CLC1GLS3
38h
PWM2CON
19h
CWG1CON0
39h
IOCAP
1Ah
CWG1CON1
3Ah
IOCAN
1Bh
CWG1CON2
3Bh
IOCAF
1Ch
CWG1DBR
3Ch
FVRCON
1Dh
CWG1DBF
3Dh
ADRES
1Eh
VREGCON
3Eh
1Fh
BORCON
3Fh
ADCON
Legend:
*
40h
60h
General
Purpose
Registers
General
Purpose
Registers
32 Bytes
32 Bytes
5Fh
7Fh
= Unimplemented data memory locations, read as ‘0’.
= Not a physical register.
DS40001585E-page 14
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
TABLE 2-3:
Address
SPECIAL FUNCTION REGISTER SUMMARY (BANK 0)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other resets
Bank 0
00h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
xxxx xxxx
xxxx xxxx
01h
TMR0
Timer0 Module Register
xxxx xxxx
uuuu uuuu
02h
PCL
Program Counter (PC) Least Significant Byte
0000 0000
0000 0000
03h
STATUS
0001 1xxx
000q quuu
04h
FSR
05h
PORTA
—
—
—
—
RA3
RA2
RA1
RA0
06h
TRISA
—
—
—
—
—(1)
TRISA2
TRISA1
TRISA0
---- 1111
---- 1111
07h
LATA
—
—
—
—
—
LATA2
LATA1
LATA0
---- -xxx
---- -uuu
08h
ANSELA
—
—
—
—
—
ANSA2
ANSA1
ANSA0
---- -111
---- -111
09h
WPUA
—
—
—
—
WPUA3
WPUA2
WPUA1
WPUA0
---- 1111
---- 1111
0Ah
PCLATH
—
—
—
—
—
—
—
PCLH0
---- ---0
---- ---0
0Bh
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
0000 0000
0000 000u
0Ch
PIR1
—
ADIF
—
NCO1IF
CLC1IF
—
TMR2IF
—
-0-0 0-0-
-0-0 0-0-
0Dh
PIE1
—
TMR2IE
—
0Eh
OPTION_REG
IRP
RP1
RP0
—
ADIE
—
NCO1IE
CLC1IE
WPUEN
INTEDG
T0CS
T0SE
PSA
—
—
—
PCON
—
10h
OSCCON
—
11h
TMR2
12h
PR2
13h
T2CON
14h
PWM1DCL
15h
PWM1DCH
16h
PWM1CON
17h
PWM2DCL
18h
PWM2DCH
19h
PWM2CON
1Ah
IOCAP
—
—
—
1Bh
IOCAN
—
—
1Ch
IOCAF
—
—
1Dh
FVRCON
FVREN
FVRRDY
1Eh
ADRES
ADCON
Legend:
Note
1:
PD
Z
DC
C
Indirect Data Memory Address Pointer
0Fh
1Fh
TO
—
—
POR
BOR
---- --qq
---- --uu
LFIOFR
HFIOFS
-110 0-00
-110 0-00
Timer2 Module Register
0000 0000
0000 0000
Timer2 Period Register
1111 1111
1111 1111
T2CKPS
-000 0000
-000 0000
—
xx-- ----
uu-- ----
—
TMR2ON
—
—
—
—
uuuu uuuu
—
—
—
0000 ----
0000 ----
—
—
—
—
xx-- ----
uu-- ----
xxxx xxxx
uuuu uuuu
—
—
—
—
0000 ----
0000 ----
—
IOCAP3
IOCAP2
IOCAP1
IOCAP0
---- 0000
---- 0000
—
—
IOCAN3
IOCAN2
IOCAN1
IOCAN0
---- 0000
---- 0000
—
—
IOCAF3
IOCAF2
IOCAF1
IOCAF0
---- 0000
---- 0000
TSEN
TSRNG
—
—
0x00 --00
0x00 --00
xxxx xxxx
uuuu uuuu
0000 0000
0000 0000
PWM2OE PWM2OUT PWM2POL
ADFVR
A/D Result Register
ADCS
xxxx xxxx
—
PWM2DCH
PWM2EN
-0-0 0-0uuuu uuuu
—
PWM1OE PWM1OUT PWM1POL
PWM2DCL
-0-0 0-01111 1111
—
PWM1DCH
PWM1EN
---- uuuu
—
TOUTPS
PWM1DCL
uuuu uuuu
---- xxxx
HFIOFR
IRCF
—
PS
xxxx xxxx
CHS
GO/
DONE
ADON
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Unimplemented, read as ‘1’.
2011-2021 Microchip Technology Inc.
DS40001585E-page 15
PIC10(L)F320/322
TABLE 2-3:
Address
SPECIAL FUNCTION REGISTER SUMMARY (BANK 0) (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
—
—
—
—
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other resets
0000 0000
0000 0000
—
—
PMADR8
---- ---0
---- ---0
Bank 0 (Continued)
20h
PMADRL
21h
PMADRH
22h
PMDATL
23h
PMDATH
—
—
24h
PMCON1
—
CFGS
25h
PMCON2
26h
CLKRCON
27h
NCO1ACCL
28h
NCO1ACCH
29h
NCO1ACCU
2Ah
NCO1INCL
2Bh
NCO1INCH
2Ch
—
2Dh
NCO1CON
2Eh
NCO1CLK
2Fh
PMADR
PMDAT
PMDAT
LWLO
FREE
WRERR
WREN
WR
RD
Program Memory Control Register 2 (not a physical register)
—
CLKROE
—
NCO1 Accumulator
0000 0000
0000 0000
NCO1 Accumulator
0000 0000
0000 0000
—
—
---- 0000
---- 0000
NCO1 Increment
0000 0001
0000 0001
NCO1 Increment
0000 0000
0000 0000
N1POL
—
N1PWS
—
—
—
—
—
N1PFM
N1CKS
Reserved
WDTCON
—
—
31h
CLC1CON
LC1EN
LC1OE
32h
CLC1SEL0
—
33h
CLC1SEL1
—
34h
CLC1POL
LC1POL
1000 q000
0000 0000
—
NCO1 Accumulator
N1OUT
1000 0000
-0-- ----
—
Unimplemented
N1OE
uuuu uuuu
--uu uuuu
-0-- ----
—
—
N1EN
xxxx xxxx
--xx xxxx
0000 0000
Reserved
30h
—
WDTPS
SWDTEN
—
—
0000 ---0
00x0 ---0
000- --00
000- --00
xxxx xxxx
uuuu uuuu
--01 0110
--01 0110
LC1INTN
LC1MODE
00x0 -000
00x0 -000
LC1D2S
—
LC1D1S
-xxx -xxx
-uuu -uuu
LC1D4S
—
LC1D3S
-xxx -xxx
-uuu -uuu
LC1OUT
LC1G2POL
LC1G1POL 0--- xxxx
0--- uuuu
CLC1GLS0
LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T
LC1G1D2N
LC1G1D1T
LC1G1D1N xxxx xxxx
uuuu uuuu
CLC1GLS1
LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T
LC1G2D2N
LC1G2D1T
LC1G2D1N xxxx xxxx
uuuu uuuu
CLC1GLS2
LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T
LC1G3D2N
LC1G3D1T
LC1G3D1N xxxx xxxx
uuuu uuuu
38h
CLC1GLS3
LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T
LC1G4D1N xxxx xxxx
uuuu uuuu
39h
CWG1CON0
35h
36h
37h
G1EN
—
G1OEB
G1ASDLB
—
LC1INTP
G1OEA
—
G1POLB
G1ASDLA
LC1G4POL LC1G3POL
LC1G4D2N
LC1G4D1T
G1POLA
—
—
—
—
—
—
G1CS0
3Ah
CWG1CON1
3Bh
CWG1CON2
G1ASE
G1ARSEN
3Ch
CWG1DBR
—
—
3Dh
CWG1DBF
—
—
3Eh
VREGCON
—
—
—
—
—
—
VREGPM1
3Fh
BORCON
SBOREN
BORFS
—
—
—
—
—
Legend:
Note
1:
—
—
G1IS
0000 0--0
0000 0--0
xxxx --xx
uuuu --uu
G1ASDCLC1 G1ASDFLT xx-- --xx
uu-- --uu
CWG1DBR
--xx xxxx
--uu uuuu
CWG1DBF
--xx xxxx
--uu uuuu
Reserved
---- --01
---- --01
BORRDY
10-- ---q
uu-- ---u
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Unimplemented, read as ‘1’.
DS40001585E-page 16
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
2.3
PCL and PCLATH
2.3.2
The Program Counter (PC) is 13 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC) is not directly
readable or writable and comes from PCLATH. On any
Reset, the PC is cleared. Figure 2-3 shows the two
situations for the loading of the PC. The upper example
in Figure 2-3 shows how the PC is loaded on a write to
PCL (PCLATH PCH). The lower example in
Figure 2-3 shows how the PC is loaded during a CALL or
GOTO instruction (PCLATH PCH).
FIGURE 2-3:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
PC
All devices have an 8-level x 13-bit wide hardware
stack (see Figure 2-1). The stack space is not part of
either program or data space and the Stack Pointer is
not readable or writable. The PC is PUSHed onto the
stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event
of a RETURN,
RETLW or a RETFIE instruction
execution. PCLATH is not affected by a PUSH or POP
operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
Note 1: There are no Status bits to indicate Stack
Overflow or Stack Underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
interrupt address.
8
PCLATH
5
Instruction with
PCL as
Destination
ALU Result
PCLATH
PCH
12
11 10
PCL
8
0
7
PC
GOTO, CALL
2
PCLATH
11
OPCODE
PCLATH
2.3.1
STACK
MODIFYING PCL
Executing any instruction with the PCL register as the
destination simultaneously causes the Program
Counter PC bits (PCH) to be replaced by the
contents of the PCLATH register. This allows the entire
contents of the program counter to be changed by
writing the desired upper five bits to the PCLATH
register. When the lower eight bits are written to the
PCL register, all 13 bits of the program counter will
change to the values contained in the PCLATH register
and those being written to the PCL register.
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). Care must be
exercised when jumping into a look-up table or
program branch table (computed GOTO) by modifying
the PCL register. Assuming that PCLATH is set to the
table start address, if the table length is greater than
255 instructions or if the lower eight bits of the memory
address rolls over from 0xFF to 0x00 in the middle of
the table, then PCLATH must be incremented for each
address rollover that occurs between the table
beginning and the target location within the table.
2.4
Indirect Addressing, INDF and
FSR Registers
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register
actually accesses data pointed to by the File Select
Register (FSR). Reading INDF itself indirectly will
produce 00h. Writing to the INDF register indirectly
results in a no operation (although Status bits may be
affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR and the IRP bit of the
STATUS register, as shown in Figure 2-4.
A simple program to clear RAM location 40h-7Fh using
indirect addressing is shown in Example 2-1.
EXAMPLE 2-1:
MOVLW
MOVWF
NEXT
CLRF
INCF
BTFSS
GOTO
CONTINUE
INDIRECT ADDRESSING
0x40
FSR
INDF
FSR
FSR,7
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
;yes continue
For more information refer to Application Note AN556,
“Implementing a Table Read” (DS00556).
2011-2021 Microchip Technology Inc.
DS40001585E-page 17
PIC10(L)F320/322
FIGURE 2-4:
DIRECT/INDIRECT ADDRESSING PIC10(L)F320/322
Direct Addressing
6
From Opcode
Indirect Addressing
0
7
File Select Register
0
Location Select
Location Select
00h
Data
Memory
7Fh
Bank 0
For memory map detail, see Figure 2-2.
DS40001585E-page 18
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
3.0
DEVICE CONFIGURATION
Device configuration consists of Configuration Word
and Device ID.
3.1
Configuration Word
There are several Configuration Word bits that allow
different oscillator and memory protection options.
These are implemented as Configuration Word at
2007h.
2011-2021 Microchip Technology Inc.
DS40001585E-page 19
PIC10(L)F320/322
3.2
Register Definitions: Configuration Word
REGISTER 3-1:
CONFIG: CONFIGURATION WORD
U-1
R/P-1/1
—
R/P-1/1
WRT
R/P-1/1
R/P-1/1
R/P-1/1
BORV
LPBOR
LVP
bit 13
R/P-1/1
R/P-1/1
R/P-1/1
CP
MCLRE
PWRTE
bit 8
R/P-1/1
R/P-1/1
R/P-1/1
WDTE
R/P-1/1
BOREN
bit 7
R/P-1/1
FOSC
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
P = Programmable bit
bit 13
Unimplemented: Read as ‘1’
bit 12-11
WRT: Flash Memory Self-Write Protection bits
256 W Flash memory: PIC10(L)F320:
11 =Write protection off
10 =000h to 03Fh write-protected, 040h to 0FFh may be modified by PMCON control
01 =000h to 07Fh write-protected, 080h to 0FFh may be modified by PMCON control
00 =000h to 0FFh write-protected, no addresses may be modified by PMCON control
512 W Flash memory: PIC10(L)F322:
11 =Write protection off
10 =000h to 07Fh write-protected, 080h to 1FFh may be modified by PMCON control
01 =000h to 0FFh write-protected, 100h to 1FFh may be modified by PMCON control
00 =000h to 1FFh write-protected, no addresses may be modified by PMCON control
bit 10
BORV: Brown-out Reset Voltage Selection bit
1 = Brown-out Reset voltage (VBOR), low trip point selected.
0 = Brown-out Reset voltage (VBOR), high trip point selected.
bit 9
LPBOR: Low-Power Brown-out Reset Enable bit
1 = Low-power Brown-out Reset is enabled
0 = Low-power Brown-out Reset is disabled
bit 8
LVP: Low-Voltage Programming Enable bit
1 = Low-Voltage Programming enabled. MCLR/VPP pin function is MCLR.
0 = High Voltage on MCLR/VPP must be used for programming
bit 7
CP: Code Protection bit(2)
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
bit 6
MCLRE: MCLR/VPP Pin Function Select bit
If LVP bit = 1:
This bit is ignored.
If LVP bit = 0:
1 = MCLR/VPP pin function is MCLR; Weak pull-up enabled.
0 = MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of
WPUA3 bit.
Note 1:
2:
3:
Enabling Brown-out Reset does not automatically enable Power-up Timer.
Once enabled, code-protect can only be disabled by bulk erasing the device.
See VBOR parameter for specific trip point voltages.
DS40001585E-page 20
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
REGISTER 3-1:
CONFIG: CONFIGURATION WORD (CONTINUED)
bit 5
PWRTE: Power-up Timer Enable bit(1)
1 = PWRT disabled
0 = PWRT enabled
bit 4-3
WDTE: Watchdog Timer Enable bit
11 = WDT enabled
10 = WDT enabled while running and disabled in Sleep
01 = WDT controlled by the SWDTEN bit in the WDTCON register
00 = WDT disabled
bit 2-1
BOREN: Brown-out Reset Enable bits
11 = Brown-out Reset enabled; SBOREN bit is ignored
10 = Brown-out Reset enabled while running, disabled in Sleep; SBOREN bit is ignored
01 = Brown-out Reset controlled by the SBOREN bit in the BORCON register
00 = Brown-out Reset disabled; SBOREN bit is ignored
bit 0
FOSC: Oscillator Selection bit
1 = EC on CLKIN pin
0 = INTOSC oscillator I/O function available on CLKIN pin
Note 1:
2:
3:
Enabling Brown-out Reset does not automatically enable Power-up Timer.
Once enabled, code-protect can only be disabled by bulk erasing the device.
See VBOR parameter for specific trip point voltages.
2011-2021 Microchip Technology Inc.
DS40001585E-page 21
PIC10(L)F320/322
3.3
Code Protection
Code protection allows the device to be protected from
unauthorized access. Program memory protection and
data memory protection are controlled independently.
Internal access to the program memory and data
memory are unaffected by any code protection setting.
3.3.1
PROGRAM MEMORY PROTECTION
The entire program memory space is protected from
external reads and writes by the CP bit in Configuration
Word. When CP = 0, external reads and writes of
program memory are inhibited and a read will return all
‘0’s. The CPU can continue to read program memory,
regardless of the protection bit settings. Writing the
program memory is dependent upon the write
protection
setting.
See
Section 3.4
“Write
Protection” for more information.
3.4
Write Protection
Write protection allows the device to be protected from
unintended self-writes. Applications, such as boot
loader software, can be protected while allowing other
regions of the program memory to be modified.
The WRT bits in Configuration Word define the
size of the program memory block that is protected.
3.5
User ID
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
readable and writable during normal execution. See
Section 3.6 “Device ID and Revision ID” for more
information on accessing these memory locations. For
more information on checksum calculation, see the
“PIC10(L)F320/322 Flash Memory Programming
Specification” (DS41572).
DS40001585E-page 22
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
3.6
Device ID and Revision ID
The memory location 2006h is where the Device ID and
Revision ID are stored. The upper nine bits hold the
Device ID. The lower five bits hold the Revision ID. See
Section 9.4 “User ID, Device ID and Configuration
Word Access” for more information on accessing
these memory locations.
Development tools, such as device programmers and
debuggers, may be used to read the Device ID and
Revision ID.
3.7
Register Definitions: Device and Revision
REGISTER 3-2:
DEVID: DEVICE ID REGISTER(1)
R
R
R
R
R
R
DEV
bit 13
R
R
bit 8
R
R
R
DEV
R
R
R
REV
bit 7
bit 0
Legend:
R = Readable bit
‘1’ = Bit is set
bit 13-5
‘0’ = Bit is cleared
DEV: Device ID bits
Device
bit 4-0
DEVID Values
DEV
REV
PIC10F320
10 1001 101
x xxxx
PIC10LF320
10 1001 111
x xxxx
PIC10F322
10 1001 100
x xxxx
PIC10LF322
10 1001 110
x xxxx
REV: Revision ID bits
These bits are used to identify the revision.
Note 1:
This location cannot be written.
2011-2021 Microchip Technology Inc.
DS40001585E-page 23
PIC10(L)F320/322
4.0
OSCILLATOR MODULE
4.1
Overview
The system can be configured to use an internal
calibrated high-frequency oscillator as clock source, with
a choice of selectable speeds via software.
The oscillator module has a variety of clock sources and
selection features that allow it to be used in a range of
applications while maximizing performance and
minimizing power consumption. Figure 4-1 illustrates a
block diagram of the oscillator module.
FIGURE 4-1:
Clock source modes are configured by the FOSC bit in
Configuration Word (CONFIG).
1.
2.
EC oscillator from CLKIN.
INTOSC oscillator, CLKIN not enabled.
PIC10(L)F320/322 CLOCK SOURCE BLOCK DIAGRAM
IRCF
3
HFINTOSC
16 MHz
HFIOFR(1)
HFIOFS(1)
LFIOFR(1)
111
110
101
100
011
010
250 kHz
31 kHz
001
000
MUX
Divider
LFINTOSC
31 kHz
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
INTOSC
FOSC
(Configuration
Word)
0
CLKIN
MUX
EC
1
System Clock
(CPU and
Peripherals)
CLKR
CLKROE
Note 1: HFIOFR, HFIOFS and LFIOFR are Status bits in the OSCCON register.
DS40001585E-page 24
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
4.2
Clock Source Modes
Clock source modes can be classified as external or
internal.
• Internal clock source (INTOSC) is contained
within the oscillator module, which has eight
selectable output frequencies, with a maximum
internal frequency of 16 MHz.
• The External Clock mode (EC) relies on an
external signal for the clock source.
The system clock can be selected between external or
internal clock sources via the FOSC bit of the
Configuration Word.
4.3
Internal Clock Modes
The internal clock sources are contained within the
oscillator module. The internal oscillator block has two
internal oscillators that are used to generate all internal
system clock sources: the 16 MHz High-Frequency
Internal Oscillator (HFINTOSC) and the 31 kHz
(LFINTOSC).
The HFINTOSC consists of a primary and secondary
clock. The secondary clock starts first with rapid startup time, but low accuracy. The secondary clock ready
signal is indicated with the HFIOFR bit of the OSCCON
register. The primary clock follows with slower start-up
time and higher accuracy. The primary clock is stable
when the HFIOFS bit of the OSCCON register bit goes
high.
4.3.1
4.3.2
FREQUENCY SELECT (IRCF) BITS
The output of the 16 MHz HFINTOSC is connected to
a divider and multiplexer (see Figure 4-1). The Internal
Oscillator Frequency Select (IRCF) bits of the
OSCCON register select the frequency output of the
internal oscillator:
• HFINTOSC
- 16 MHz
- 8 MHz (default after Reset)
- 4 MHz
- 2 MHz
- 1 MHz
- 500 kHz
- 250 kHz
• LFINTOSC
- 31 kHz
Note:
Following any Reset, the IRCF bits
of the OSCCON register are set to ‘110’
and the frequency selection is set to
8 MHz. The user can modify the IRCF bits
to select a different frequency.
There is no delay when switching between HFINTOSC
frequencies with the IRCF bits. This is because the
switch involves only a change to the frequency output
divider.
Start-up delay specifications are located
Section 24.0 “Electrical Specifications”.
in
INTOSC MODE
When the FOSC bit of the Configuration Word is
cleared, the INTOSC mode is selected. When INTOSC
is selected, CLKIN pin is available for general purpose
I/O. See Section 3.0 “Device Configuration” for
more information.
2011-2021 Microchip Technology Inc.
DS40001585E-page 25
PIC10(L)F320/322
4.4
Register Definitions: Reference Clock Control
REGISTER 4-1:
CLKRCON – REFERENCE CLOCK CONTROL REGISTER
U-0
R/W-0/0
U-0
U-0
U-0
U-0
U-0
U-0
—
CLKROE
—
—
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
q = Value depends on condition
bit 7
Unimplemented: Read as ‘0’
bit 6
CLKROE: Reference Clock Output Enable bit
1 = Reference Clock output (CLKR), regardless of TRIS
0 = Reference Clock output disabled
bit 5-0
Unimplemented: Read as ‘0’
4.5
Register Definitions: Oscillator Control
REGISTER 4-2:
U-0
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-1/1
—
R/W-1/1
R/W-0/0
IRCF
R-0/0
U-0
R-0/0
R-0/0
HFIOFR
—
LFIOFR
HFIOFS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IRCF: INTOSC (FOSC) Frequency Select bits
111 = 16 MHz
110 = 8 MHz (default value)
101 = 4 MHz
100 = 2 MHz
011 = 1 MHz
010 = 500 kHz
001 = 250 kHz
000 = 31 kHz (LFINTOSC)
bit 3
HFIOFR: High-Frequency Internal Oscillator Ready bit
1 = 16 MHz Internal Oscillator (HFINTOSC) is ready
0 = 16 MHz Internal Oscillator (HFINTOSC) is not ready
bit 2
Unimplemented: Read as ‘0’
bit 1
LFIOFR: Low-Frequency Internal Oscillator Ready bit
1 = 31 kHz Internal Oscillator (LFINTOSC) is ready
0 = 31 kHz Internal Oscillator (LFINTOSC) is not ready
bit 0
HFIOFS: High-Frequency Internal Oscillator Stable bit
1 = 16 MHz Internal Oscillator (HFINTOSC) is stable
0 = 16 MHz Internal Oscillator (HFINTOSC) is not stable
DS40001585E-page 26
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
4.6
External Clock Mode
4.6.1
EC MODE
The External Clock (EC) mode allows an externally
generated logic level as the system clock source. When
operating in this mode, an external clock source is
connected to the CLKIN input.
TABLE 4-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Bit 7
Bit 6
CLKRCON
—
CLKROE
OSCCON
—
Legend:
CONFIG
Legend:
Bit 4
—
—
Bit 3
IRCF
Bit 2
Bit 1
Bit 0
Register
on Page
—
—
—
—
26
HFIOFR
—
LFIOFR
HFIOFS
26
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by ECWG.
TABLE 4-2:
Name
Bit 5
Bits
SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
13:8
—
—
—
WRT
7:0
CP
MCLRE
PWRTE
WDTE
Bit 10/2
Bit 9/1
BORV
LPBOR
BOREN
Bit 8/0
LVP
FOSC
Register
on Page
20
— = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources.
2011-2021 Microchip Technology Inc.
DS40001585E-page 27
PIC10(L)F320/322
5.0
RESETS
There are multiple ways to reset this device:
•
•
•
•
•
•
Power-On Reset (POR)
Brown-Out Reset (BOR)
Low-Power Brown-Out Reset (LPBOR)
MCLR Reset
WDT Reset
Programming mode exit
To allow VDD to stabilize, an optional Power-up Timer
can be enabled to extend the Reset time after a BOR
or POR event.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 5-1.
FIGURE 5-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
IC SP™ Program m ing M ode Exit
M C LR E
Sleep
W DT
Tim e-out
D evice
R eset
Pow er-on
R eset
VDD
Brow n-out
R eset
R
PW R T
D one
LPBO R
R eset
PW R TE
LFIN TO SC
BO R
Active(1)
Note 1:
See Table 5-1 for BOR active conditions.
DS40001585E-page 28
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
5.1
Power-On Reset (POR)
5.2
Brown-Out Reset (BOR)
The POR circuit holds the device in Reset until VDD has
reached an acceptable level for minimum operation.
Slow rising VDD, fast operating speeds or analog
performance may require greater than minimum VDD.
The PWRT, BOR or MCLR features can be used to
extend the start-up period until all device operation
conditions have been met.
The BOR circuit holds the device in Reset when VDD
reaches a selectable minimum level. Between the
POR and BOR, complete voltage range coverage for
execution protection can be implemented.
5.1.1
•
•
•
•
POWER-UP TIMER (PWRT)
The Power-up Timer provides a nominal 64 ms timeout on POR or Brown-out Reset.
The device is held in Reset as long as PWRT is active.
The PWRT delay allows additional time for the VDD to
rise to an acceptable level. The Power-up Timer is
enabled by clearing the PWRTE bit in Configuration
Word.
The Power-up Timer starts after the release of the POR
and BOR.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
TABLE 5-1:
The Brown-out Reset module has four operating
modes controlled by the BOREN bits in Configuration Word. The four operating modes are:
BOR is always on
BOR is off when in Sleep
BOR is controlled by software
BOR is always off
Refer to Table 5-1 for more information.
The Brown-out Reset voltage level is selectable by
configuring the BORV bit in Register 3-1.
A VDD noise rejection filter prevents the BOR from triggering on small events. If VDD falls below VBOR for a
duration greater than parameter TBORDC, the device
will reset. See Figure 5-2 for more information.
BOR OPERATING MODES
BOREN
SBOREN
Device Mode
BOR Mode
11
X
X
Active
10
X
Awake
Active
Sleep
Disabled
1
X
Active
0
X
Disabled
X
X
Disabled
01
00
Device Operation upon:
Release of POR/Wake- up from Sleep
Waits for BOR ready(1) (BORRDY = 1)
Waits for BOR ready (BORRDY = 1)
Waits for BOR ready(1) (BORRDY = 1)
Begins immediately (BORRDY = x)
Note 1: In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR
ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR
circuit is forced on by the BOREN bits.
5.2.1
BOR IS ALWAYS ON
When the BOREN bits of Configuration Word are
programmed to ‘11’, the BOR is always on. The device
start-up will be delayed until the BOR is ready and VDD
is higher than the BOR threshold.
BOR protection is active during Sleep. The BOR does
not delay wake-up from Sleep.
5.2.2
BOR IS OFF IN SLEEP
When the BOREN bits of Configuration Word are
programmed to ‘10’, the BOR is on, except in Sleep.
The device start-up will be delayed until the BOR is
ready and VDD is higher than the BOR threshold.
5.2.3
BOR CONTROLLED BY SOFTWARE
When the BOREN bits of Configuration Word are
programmed to ‘01’, the BOR is controlled by the
SBOREN bit of the BORCON register. The device startup is not delayed by the BOR ready condition or the
VDD level.
BOR protection begins as soon as the BOR circuit is
ready. The status of the BOR circuit is reflected in the
BORRDY bit of the BORCON register.
BOR protection is unchanged by Sleep.
BOR protection is not active during Sleep. The device
wake-up will be delayed until the BOR is ready.
2011-2021 Microchip Technology Inc.
DS40001585E-page 29
PIC10(L)F320/322
FIGURE 5-2:
BROWN-OUT SITUATIONS
VDD
VBOR
Internal
Reset
TPWRT(1)
VDD
VBOR
Internal
Reset
< TPWRT
TPWRT(1)
VDD
VBOR
Internal
Reset
Note 1:
5.3
TPWRT(1)
TPWRT delay only if PWRTE bit is programmed to ‘0’.
Register Definition: BOR Control
REGISTER 5-1:
BORCON: BROWN-OUT RESET CONTROL REGISTER
R/W-1/u
R/W-0/u
U-0
U-0
U-0
U-0
U-0
R-q/u
SBOREN
BORFS(1)
—
—
—
—
—
BORRDY
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
SBOREN: Software Brown-out Reset Enable bit
If BOREN in Configuration Word 01:
SBOREN is read/write, but has no effect on the BOR.
If BOREN in Configuration Word = 01:
1 = BOR enabled
0 = BOR disabled
bit 6
BORFS: Brown-out Reset Fast Start bit(1)
If BOREN = 11 (Always on) or BOREN = 00 (Always off)
BORFS is Read/Write, but has no effect.
If BOREN = 10 (Disabled in Sleep) or BOREN = 01 (Under software control):
1 = Band gap is forced on always (covers Sleep/wake-up/operating cases)
0 = Band gap operates normally, and may turn off
bit 5-1
Unimplemented: Read as ‘0’
bit 0
BORRDY: Brown-out Reset Circuit Ready Status bit
1 = The Brown-out Reset circuit is active
0 = The Brown-out Reset circuit is inactive
Note 1:
BOREN bits are located in Configuration Word.
DS40001585E-page 30
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
5.4
Low-Power Brown-out Reset
(LPBOR)
The Low-Power Brown-Out Reset (LPBOR) is an
essential part of the Reset subsystem. Refer to
Figure 5-1 to see how the BOR interacts with other
modules.
The LPBOR is used to monitor the external VDD pin.
When too low of a voltage is detected, the device is
held in Reset. When this occurs, a register bit (BOR) is
changed to indicate that a BOR Reset has occurred.
The same bit is set for both the BOR and the LPBOR.
Refer to Register 5-2.
5.4.1
ENABLING LPBOR
5.6
Watchdog Timer (WDT) Reset
The Watchdog Timer generates a Reset if the firmware
does not issue a CLRWDT instruction within the time-out
period. The TO and PD bits in the STATUS register are
changed to indicate the WDT Reset. See Section 8.0
“Watchdog Timer” for more information.
5.7
Programming Mode ICSP Exit
Upon exit of Programming mode, the device will
behave as if a POR had just occurred.
5.8
Power-Up Timer
The LPBOR is controlled by the LPBOR bit of
Configuration Word. When the device is erased, the
LPBOR module defaults to enabled.
The Power-up Timer optionally delays device execution
after a BOR or POR event. This timer is typically used to
allow VDD to stabilize before allowing the device to start
running.
5.4.1.1
The Power-up Timer is controlled by the PWRTE bit of
Configuration Word.
LPBOR Module Output
The output of the LPBOR module is a signal indicating
whether or not a Reset is to be asserted. This signal is
OR’d together with the Reset signal of the BOR module to provide the generic BOR signal which goes to
the PCON register and to the power control block.
5.5
The MCLR is an optional external input that can reset
the device. The MCLR function is controlled by the
MCLRE and the LVP bit of Configuration Word (Table 52).
MCLR CONFIGURATION
MCLRE
LVP
MCLR
0
0
Disabled
1
0
Enabled
x
1
Enabled
5.5.1
Start-up Sequence
Upon the release of a POR or BOR, the following must
occur before the device will begin executing:
1.
2.
MCLR
TABLE 5-2:
5.9
Power-up Timer runs to completion (if enabled).
MCLR must be released (if enabled).
The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See
Section 4.0 “Oscillator Module” for more information.
The Power-up Timer runs independently of MCLR Reset.
If MCLR is kept low long enough, the Power-up Timer will
expire. Upon bringing MCLR high, the device will begin
execution after 10 FOSC cycles (see Figure 5-3). This is
useful for testing purposes or to synchronize more than
one device operating in parallel.
MCLR ENABLED
When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR pin is connected to
VDD through an internal weak pull-up.
The device has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
Note:
5.5.2
A Reset does not drive the MCLR pin low.
MCLR DISABLED
When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under
software control.
2011-2021 Microchip Technology Inc.
DS40001585E-page 31
PIC10(L)F320/322
FIGURE 5-3:
RESET START-UP SEQUENCE
VDD
Internal POR
TPWRT
Power-Up Timer
MCLR
TMCLR
Internal RESET
Oscillator Modes
Internal Oscillator
Oscillator
FOSC
External Clock (EC)
CLKIN
FOSC
DS40001585E-page 32
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
5.10
Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and
PCON registers are updated to indicate the cause of
the Reset. Table 5-3 and Table 5-4 show the Reset
conditions of these registers.
TABLE 5-3:
RESET STATUS BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
0
x
1
1
Power-on Reset
u
0
1
1
Brown-out Reset
u
u
0
u
WDT Reset
u
u
0
0
WDT Wake-up from Sleep
u
u
u
u
MCLR Reset during normal operation
u
u
1
0
MCLR Reset during Sleep
TABLE 5-4:
Condition
RESET CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Power-on Reset
0000h
0001 1000
---- --0x
MCLR Reset during normal operation
0000h
000u uuuu
---- --uu
MCLR Reset during Sleep
0000h
0001 0uuu
---- --uu
WDT Reset
0000h
0000 uuuu
---- --uu
WDT Wake-up from Sleep
PC + 1
0000 0uuu
---- --uu
Brown-out Reset
0000h
0001 1uuu
---- --u0
0001 0uuu
---- --uu
Condition
Interrupt Wake-up from Sleep
PC + 1
(1)
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Enable (GIE) bit is set, the return address is pushed on
the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
2011-2021 Microchip Technology Inc.
DS40001585E-page 33
PIC10(L)F320/322
5.11
Power Control (PCON) Register
The Power Control (PCON) register contains flag bits
to differentiate between a:
• Power-On Reset (POR)
• Brown-Out Reset (BOR)
The PCON register bits are shown in Register 5-2.
5.12
Register Definition: Power Control
REGISTER 5-2:
PCON: POWER CONTROL REGISTER
U-0
U-0
U-0
U-0
U-0
U-0
R/W/HC-q/u
R/W/HC-q/u
—
—
—
—
—
—
POR
BOR
bit 7
bit 0
Legend:
HC = Bit is cleared by hardware
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7-2
Unimplemented: Read as ‘0’
bit 1
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset
occurs)
TABLE 5-5:
SUMMARY OF REGISTERS ASSOCIATED WITH RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BORCON
SBOREN
BORFS
—
—
—
—
—
BORRDY
30
—
—
—
—
—
—
POR
BOR
34
IRP
RP1
RP0
TO
PD
Z
DC
C
13
—
—
SWDTEN
48
PCON
STATUS
WDTCON
WDTPS
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets.
TABLE 5-6:
Name
CONFIG
Bits
SUMMARY OF CONFIGURATION WORD WITH RESETS
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
13:8
—
—
—
WRT
7:0
CP
MCLRE
PWRTE
WDTE
Bit 10/2
Bit 9/1
BORV
LPBOR
BOREN
Bit 8/0
LVP
FOSC
Register
on Page
20
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Reset.
DS40001585E-page 34
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
6.0
INTERRUPTS
The interrupt feature allows certain events to preempt
normal program flow. Firmware is used to determine
the source of the interrupt and act accordingly. Some
interrupts can be configured to wake the MCU from
Sleep mode.
This chapter contains the following information for
Interrupts:
•
•
•
•
•
Operation
Interrupt Latency
Interrupts During Sleep
INT Pin
Context Saving during Interrupts
Many peripherals produce interrupts. Refer to the
corresponding chapters for details.
A block diagram of the interrupt logic is shown in
Figure 6-1.
FIGURE 6-1:
INTERRUPT LOGIC
Rev. 10-000010A
1/13/2014
TMR0IF
TMR0IE
Peripheral Interrupts
(TMR1IF) PIR1
(TMR1IE) PIE1
Wake-up
(If in Sleep mode)
INTF
INTE
IOCIF
IOCIE
Interrupt
to CPU
PEIE
PIRn
PIEn
2011-2021 Microchip Technology Inc.
GIE
DS40001585E-page 35
PIC10(L)F320/322
6.1
Operation
Interrupts are disabled upon any device Reset. They
are enabled by setting the following bits:
• GIE bit of the INTCON register
• Interrupt Enable bit(s) for the specific interrupt
event(s)
• PEIE bit of the INTCON register (if the Interrupt
Enable bit of the interrupt event is contained in the
PIE1 register)
6.2
Interrupt Latency
Interrupt latency is defined as the time from when the
interrupt event occurs to the time code execution at the
interrupt vector begins. The latency for synchronous
interrupts is three or four instruction cycles. For
asynchronous interrupts, the latency is three to five
instruction cycles, depending on when the interrupt
occurs. See Figure 6-2 and Section 6.3 “Interrupts
During Sleep” for more details.
The INTCON and PIR1 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set,
regardless of the status of the GIE, PEIE and individual
interrupt enable bits.
The following events happen when an interrupt event
occurs while the GIE bit is set:
• Current prefetched instruction is flushed
• GIE bit is cleared
• Current Program Counter (PC) is pushed onto the
stack
• PC is loaded with the interrupt vector 0004h
The firmware within the Interrupt Service Routine (ISR)
will determine the source of the interrupt by polling the
interrupt flag bits. The interrupt flag bits must be
cleared before exiting the ISR to avoid repeated
interrupts. Because the GIE bit is cleared, any interrupt
that occurs while executing the ISR will be recorded
through its interrupt flag, but will not cause the
processor to redirect to the interrupt vector.
The RETFIE instruction exits the ISR by popping the
previous address from the stack, and setting the GIE
bit.
For additional information on a specific interrupt’s
operation, refer to its peripheral chapter.
Note 1: Individual interrupt flag bits are set,
regardless of the state of any other
enable bits.
2: All interrupts will be ignored while the GIE
bit is cleared. Any interrupt occurring
while the GIE bit is clear will be serviced
when the GIE bit is set again.
DS40001585E-page 36
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
FIGURE 6-2:
INTERRUPT LATENCY
IN TO S C
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
C LK R
Interrupt S am pled
during Q 1
Interrupt
G IE
PC
E xecute
P C -1
PC
1 C ycle Instruction atP C
P C +1
0004h
0005h
Inst(P C )
NOP
NOP
Inst(0004h)
P C +1/FS R
AD D R
N ew P C /
P C +1
0004h
0005h
Interrupt
G IE
PC
E xecute
P C -1
PC
2 C ycle Instruction atP C
Inst(P C )
NOP
NOP
Inst(0004h)
FS R A D D R
P C +1
P C +2
0004h
0005h
NOP
NOP
NOP
Inst(0004h)
Inst(0005h)
0004h
0005h
NOP
Inst(0004h)
Interrupt
G IE
PC
E xecute
P C -1
PC
3 C ycle Instruction atP C
IN S T(P C )
Interrupt
G IE
PC
E xecute
P C -1
PC
3 C ycle Instruction atP C
2011-2021 Microchip Technology Inc.
FS R A D D R
IN S T(P C )
P C +1
NOP
P C +2
NOP
NOP
DS40001585E-page 37
PIC10(L)F320/322
FIGURE 6-3:
INT PIN INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
INTOSC
CLKR
(3)
INT pin
(1)
(1)
INTF
Interrupt Latency (2)
(4)
GIE
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Note 1:
PC
Inst (PC)
Inst (PC – 1)
PC + 1
Inst (PC + 1)
Inst (PC)
PC + 1
—
Forced NOP
0004h
0005h
Inst (0004h)
Inst (0005h)
Forced NOP
Inst (0004h)
INTF flag is sampled here (every Q1).
2:
Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3:
For minimum width of INT pulse, refer to AC specifications in Section 24.0 “Electrical Specifications”.
4:
INTF is enabled to be set any time during the Q4-Q1 cycles.
DS40001585E-page 38
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
6.3
Interrupts During Sleep
Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEP instruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to the Section 7.0 “PowerDown Mode (Sleep)” for more details.
6.4
INT Pin
The INT pin can be used to generate an asynchronous
edge-triggered interrupt. This interrupt is enabled by
setting the INTE bit of the INTCON register. The
INTEDG bit of the OPTION_REG register determines on
which edge the interrupt will occur. When the INTEDG
bit is set, the rising edge will cause the interrupt. When
the INTEDG bit is clear, the falling edge will cause the
interrupt. The INTF bit of the INTCON register will be set
when a valid edge appears on the INT pin. If the GIE and
INTE bits are also set, the processor will redirect
program execution to the interrupt vector.
EXAMPLE 6-1:
MOVWF
SWAPF
Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (e.g., W and STATUS
registers). This must be implemented in software.
Temporary
holding
registers
W_TEMP
and
STATUS_TEMP must be placed in the last 16 bytes of
GPR (see Table 1-2). This makes context save and
restore operations simpler. The code shown in
Example 6-1 can be used to:
•
•
•
•
•
Store the W register
Store the STATUS register
Execute the ISR code
Restore the Status (and Bank Select Bit register)
Restore the W register
Note:
These devices do not require saving the
PCLATH. However, if computed GOTOs
are used in both the ISR and the main
code, the PCLATH must be saved and
restored in the ISR.
SAVING STATUS AND W REGISTERS IN RAM
W_TEMP
STATUS,W
MOVWF
STATUS_TEMP
:
:(ISR)
:
SWAPF
STATUS_TEMP,W
MOVWF
SWAPF
SWAPF
6.5
STATUS
W_TEMP,F
W_TEMP,W
2011-2021 Microchip Technology Inc.
;Copy W to TEMP
;Swap status to
;Swaps are used
;Save status to
register
be saved into W
because they do not affect the status bits
bank zero STATUS_TEMP register
;Insert user code here
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
DS40001585E-page 39
PIC10(L)F320/322
6.6
Interrupt Control Registers
REGISTER 6-1:
INTCON: INTERRUPT CONTROL REGISTER
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-0/0
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all active interrupts
0 = Disables all interrupts
bit 6
PEIE: Peripheral Interrupt Enable bit
1 = Enables all active peripheral interrupts
0 = Disables all peripheral interrupts
bit 5
TMR0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4
INTE: INT External Interrupt Enable bit
1 = Enables the INT external interrupt
0 = Disables the INT external interrupt
bit 3
IOCIE: Interrupt-on-Change Interrupt Enable bit
1 = Enables the interrupt-on-change interrupt
0 = Disables the interrupt-on-change interrupt
bit 2
TMR0IF: Timer0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed
0 = TMR0 register did not overflow
bit 1
INTF: INT External Interrupt Flag bit
1 = The INT external interrupt occurred
0 = The INT external interrupt did not occur
bit 0
IOCIF: Interrupt-on-Change Interrupt Flag bit(1)
1 = When at least one of the interrupt-on-change pins changed state
0 = None of the interrupt-on-change pins have changed state
Note 1:
Note:
The IOCIF Flag bit is read-only and cleared when all the Interrupt-on-Change flags in the IOCAF register
have been cleared by software.
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE, of the INTCON
register. User software must ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
DS40001585E-page 40
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
REGISTER 6-2:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
U-0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
U-0
—
ADIE
—
NCO1IE
CLC1IE
—
TMR2IE
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
bit 5
Unimplemented: Read as ‘0’
bit 4
NCO1IE: Numerically Controlled Oscillator Interrupt Enable bit
1 = Enables the NCO overflow interrupt
0 = Disables the NCO overflow interrupt
bit 3
CLC1IE: Configurable Logic Block Interrupt Enable bit
1 = Enables the CLC interrupt
0 = Disables the CLC interrupt
bit 2
Unimplemented: Read as ‘0’
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 Match interrupt
0 = Disables the TMR2 to PR2 Match interrupt
bit 0
Unimplemented: Read as ‘0’
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
2011-2021 Microchip Technology Inc.
DS40001585E-page 41
PIC10(L)F320/322
REGISTER 6-3:
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
U-0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
U-0
—
ADIF
—
NCO1IF
CLC1IF
—
TMR2IF
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6
ADIF: A/D Converter Interrupt Flag bit
1 = The A/D conversion completed
0 = The A/D conversion is not complete
bit 5
Unimplemented: Read as ‘0’
bit 4
NCO1IF: Numerically Controlled Oscillator Interrupt Flag bit
1 = NCO1 overflow occurred (must be cleared in software)
0 = No NCO1 overflow
bit 3
CLC1IF: Configurable Logic Block Rising Edge Interrupt Flag bit
1 = CLC interrupt occurred (must be cleared in software)
0 = No CLC Interrupt
bit 2
Unimplemented: Read as ‘0’
bit 1
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match
Note: The match must occur the number of times specified by the TMR2 postscaler (Register 17-1).
bit 0
Unimplemented: Read as ‘0’
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE, of the INTCON
register. User software must ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
DS40001585E-page 42
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
TABLE 6-1:
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
40
IOCAF
—
—
—
—
IOCAF3
IOCAF2
IOCAF1
IOCAF0
76
IOCAN
—
—
—
—
IOCAN3
IOCAN2
IOCAN1
IOCAN0
75
IOCAP
—
—
—
—
IOCAP3
IOCAP2
IOCAP1
IOCAP0
75
Name
INTCON
OPTION_REG WPUEN
INTEDG
T0CS
T0SE
PSA
PIE1
—
ADIE
—
NCO1IE
CLC1IE
—
PS
TMR2IE
—
95
41
PIR1
—
ADIF
—
NCO1IF
CLC1IF
—
TMR2IF
—
42
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupts.
2011-2021 Microchip Technology Inc.
DS40001585E-page 43
PIC10(L)F320/322
7.0
POWER-DOWN MODE (SLEEP)
7.1
Wake-up from Sleep
The Power-Down mode is entered by executing a
SLEEP instruction.
The device can wake-up from Sleep through one of the
following events:
Upon entering Sleep mode, the following conditions
exist:
1.
2.
3.
4.
5.
6.
1.
2.
3.
4.
5.
6.
7.
8.
WDT will be cleared but keeps running, if
enabled for operation during Sleep.
PD bit of the STATUS register is cleared.
TO bit of the STATUS register is set.
CPU clock is disabled.
31 kHz LFINTOSC is unaffected and peripherals
that operate from it may continue operation in
Sleep.
ADC is unaffected, if the dedicated FRC clock is
selected.
I/O ports maintain the status they had before
SLEEP was executed (driving high, low or highimpedance).
Resets other than WDT are not affected by
Sleep mode.
Refer to individual chapters for more details on
peripheral operation during Sleep.
To minimize current consumption, the following conditions need to be considered:
•
•
•
•
•
•
I/O pins must not be floating
External circuitry sinking current from I/O pins
Internal circuitry sourcing current from I/O pins
Current draw from pins with internal weak pull-ups
Modules using 31 kHz LFINTOSC
CWG and NCO modules using HFINTOSC
I/O pins that are high-impedance inputs will be pulled to
VDD or VSS externally to avoid switching currents
caused by floating inputs.
Examples of internal circuitry that might be sourcing
current include the FVR module. See Section 12.0
“Fixed Voltage Reference (FVR)” for more information on these modules.
DS40001585E-page 44
External Reset input on MCLR pin, if enabled
BOR Reset, if enabled
POR Reset
Watchdog Timer, if enabled
Any external interrupt
Interrupts by peripherals capable of running
during Sleep (see individual peripheral for more
information)
The first three events will cause a device Reset. The
last three events are considered a continuation of program execution. To determine whether a device Reset
or wake-up event occurred, refer to Section 5.10
“Determining the Cause of a Reset”.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be enabled. Wake-up will
occur regardless of the state of the GIE bit. If the GIE
bit is disabled, the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
enabled, the device executes the instruction after the
SLEEP instruction, the device will then call the Interrupt
Service Routine. In cases where the execution of the
instruction following SLEEP is not desirable, the user
will have a NOP after the SLEEP instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
The Complementary Waveform Generator (CWG) and
the Numerically Controlled Oscillator (NCO) modules
can utilize the HFINTOSC oscillator as their respective
clock source. Under certain conditions, when the
HFINTOSC is selected for use with the CWG or NCO
modules, the HFINTOSC will remain active during
Sleep. This will have a direct effect on the Sleep mode
current. Please refer to 21.0 “Complementary Waveform Generator (CWG) Module” and 20.0 “Numerically Controlled Oscillator (NCO) Module” for more
information.
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
7.1.1
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction
- SLEEP instruction will execute as a NOP.
- WDT and WDT prescaler will not be cleared
- TO bit of the STATUS register will not be set
- PD bit of the STATUS register will not be
cleared.
FIGURE 7-1:
• If the interrupt occurs during or after the
execution of a SLEEP instruction
- SLEEP instruction will be completely
executed
- Device will immediately wake-up from Sleep
- WDT and WDT prescaler will be cleared
- TO bit of the STATUS register will be set
- PD bit of the STATUS register will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKIN(1)
TOST(3)
CLKOUT(2)
Interrupt Latency (4)
Interrupt flag
GIE bit
(INTCON reg.)
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
Note
1:
2:
3:
4:
Processor in
Sleep
PC
Inst(PC) = Sleep
Inst(PC - 1)
PC + 1
PC + 2
Inst(PC + 1)
Inst(PC + 2)
Sleep
Inst(PC + 1)
0005h
Inst(0004h)
Inst(0005h)
Forced NOP
Inst(0004h)
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
Name
Bit 7
Bit 6
Bit 5
Bit 4
STATUS
IRP
RP1
RP0
TO
—
—
Legend:
Forced NOP
0004h
External clock. High, Medium, Low mode assumed.
CLKOUT is shown here for timing reference.
TOST= 1024 TOSC; This delay does not apply to EC, RC and INTOSC Oscillator modes or Two-Speed Start-up (see Section 5.4 “LowPower Brown-out Reset (LPBOR)”.).
GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
TABLE 7-1:
WDTCON
PC + 2
PC + 2
Bit 3
Bit 2
Bit 1
PD
Z
DC
WDTPS
Bit 0
Register on
Page
C
13
SWDTEN
48
— = unimplemented location, read as ‘0’. Shaded cells are not used in Power-down mode.
2011-2021 Microchip Technology Inc.
DS40001585E-page 45
PIC10(L)F320/322
8.0
WATCHDOG TIMER
The Watchdog Timer is a system timer that generates
a Reset if the firmware does not issue a CLRWDT
instruction within the time-out period. The Watchdog
Timer is typically used to recover the system from
unexpected events.
The WDT has the following features:
• Independent clock source
• Multiple operating modes
- WDT is always on
- WDT is off when in Sleep
- WDT is controlled by software
- WDT is always off
• Configurable time-out period is from 1 ms to 256
seconds (typical)
• Multiple Reset conditions
• Operation during Sleep
FIGURE 8-1:
WATCHDOG TIMER BLOCK DIAGRAM
WDTE = 01
SWDTEN
WDTE = 11
LFINTOSC
23-bit Programmable
Prescaler WDT
WDT Time-out
WDTE = 10
Sleep
DS40001585E-page 46
WDTPS
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
8.1
Independent Clock Source
8.3
Time-Out Period
The WDT derives its time base from the 31 kHz
LFINTOSC internal oscillator. Time intervals in this
chapter are based on a nominal interval of 1ms. See
Section 24.0 “Electrical Specifications” for the
LFINTOSC tolerances.
The WDTPS bits of the WDTCON register set the timeout period from 1 ms to 256 seconds (nominal). After a
Reset, the default time-out period is 2 seconds.
8.2
The WDT is cleared when any of the following
conditions occur:
WDT Operating Modes
The Watchdog Timer module has four operating modes
controlled by the WDTE bits in Configuration
Word. See Table 8-1.
8.4
Clearing the WDT
When the WDTE bits of Configuration Word are set to
‘11’, the WDT is always on.
•
•
•
•
•
•
WDT protection is active during Sleep.
See Table 8-2 for more information.
8.2.2
8.5
8.2.1
WDT IS ALWAYS ON
WDT IS OFF IN SLEEP
When the WDTE bits of Configuration Word are set to
‘10’, the WDT is on, except in Sleep.
WDT protection is not active during Sleep.
8.2.3
WDT CONTROLLED BY SOFTWARE
When the WDTE bits of Configuration Word are set to
‘01’, the WDT is controlled by the SWDTEN bit of the
WDTCON register.
WDT protection is unchanged by Sleep. See Table 8-1
for more details.
TABLE 8-1:
WDT OPERATING MODES
WDTE
SWDTEN
Device
Mode
WDT
Mode
11
X
X
Active
10
X
Awake
Active
Sleep
Disabled
1
01
0
00
TABLE 8-2:
X
X
X
Any Reset
CLRWDT instruction is executed
Device enters Sleep
Device wakes up from Sleep
Oscillator fail
WDT is disabled
Operation During Sleep
When the device enters Sleep, the WDT is cleared. If
the WDT is enabled during Sleep, the WDT resumes
counting.
When the device exits Sleep, the WDT is cleared
again.
When a WDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device
wakes up and resumes operation. The TO and PD bits
in the STATUS register are changed to indicate the
event. See Section 2.0 “Memory Organization” and
Register 2-1 for more information.
Active
Disabled
Disabled
WDT CLEARING CONDITIONS
Conditions
WDT
WDTE = 00
WDTE = 01 and SWDTEN = 0
WDTE = 10 and enter Sleep
Cleared
CLRWDT Command
Exit Sleep
Change INTOSC divider (IRCF bits)
2011-2021 Microchip Technology Inc.
Unaffected
DS40001585E-page 47
PIC10(L)F320/322
8.6
Watchdog Control Register
REGISTER 8-1:
WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0
U-0
—
—
R/W-0/0
R/W-1/1
R/W-0/0
R/W-1/1
R/W-1/1
WDTPS
R/W-0/0
SWDTEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-1
WDTPS: Watchdog Timer Period Select bits(1)
Bit Value = Prescale Rate
11111 = Reserved. Results in minimum interval (1:32)
•
•
•
10011 = Reserved. Results in minimum interval (1:32)
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
bit 0
Note 1:
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
1:8388608 (223) (Interval 256s nominal)
1:4194304 (222) (Interval 128s nominal)
1:2097152 (221) (Interval 64s nominal)
1:1048576 (220) (Interval 32s nominal)
1:524288 (219) (Interval 16s nominal)
1:262144 (218) (Interval 8s nominal)
1:131072 (217) (Interval 4s nominal)
1:65536 (Interval 2s nominal) (Reset value)
1:32768 (Interval 1s nominal)
1:16384 (Interval 512 ms nominal)
1:8192 (Interval 256 ms nominal)
1:4096 (Interval 128 ms nominal)
1:2048 (Interval 64 ms nominal)
1:1024 (Interval 32 ms nominal)
1:512 (Interval 16 ms nominal)
1:256 (Interval 8 ms nominal)
1:128 (Interval 4 ms nominal)
1:64 (Interval 2 ms nominal)
1:32 (Interval 1 ms nominal)
SWDTEN: Software Enable/Disable for Watchdog Timer bit
If WDTE = 00:
This bit is ignored.
If WDTE = 01:
1 = WDT is turned on
0 = WDT is turned off
If WDTE = 1x:
This bit is ignored.
Times are approximate. WDT time is based on 31 kHz LFINTOSC.
DS40001585E-page 48
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
TABLE 8-3:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER
Bit 7
Bit 6
OSCCON
—
STATUS
IRP
RP1
—
—
WDTCON
Bit 5
Bit 4
IRCF
RP0
TO
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
HFIOFR
—
LFIOFR
HFIOFS
26
PD
Z
DC
C
13
SWDTEN
48
WDTPS
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
Watchdog Timer.
TABLE 8-4:
Name
CONFIG
Bits
SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
13:8
—
—
—
WRT
7:0
CP
MCLRE
PWRTE
WDTE
Bit 10/2
Bit 9/1
BORV
LPBOR
BOREN
Bit 8/0
LVP
FOSC
Register
on Page
20
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer.
2011-2021 Microchip Technology Inc.
DS40001585E-page 49
PIC10(L)F320/322
9.0
FLASH PROGRAM MEMORY
CONTROL
The Flash program memory is readable and writable
during normal operation over the full VDD range.
Program memory is indirectly addressed using Special
Function Registers (SFRs). The SFRs used to access
program memory are:
•
•
•
•
•
•
PMCON1
PMCON2
PMDATL
PMDATH
PMADRL
PMADRH
When accessing the program memory, the
PMDATH:PMDATL register pair forms a 2-byte word
that holds the 14-bit data for read/write, and the
PMADRH:PMADRL register pair forms a 2-byte word
that holds the 9-bit address of the program memory
location being read.
The write time is controlled by an on-chip timer. The write/
erase voltages are generated by an on-chip charge pump
rated to operate over the operating voltage range of the
device.
The Flash program memory can be protected in two
ways; by code protection (CP bit in Configuration Word)
and write protection (WRT bits in Configuration
Word).
Code protection (CP = 0)(1), disables access, reading
and writing, to the Flash program memory via external
device programmers. Code protection does not affect
the self-write and erase functionality. Code protection
can only be reset by a device programmer performing
a Bulk Erase to the device, clearing all Flash program
memory, Configuration bits and User IDs.
Write protection prohibits self-write and erase to a
portion or all of the Flash program memory as defined
by the bits WRT. Write protection does not affect
a device programmers ability to read, write or erase the
device.
Note 1: Code protection of the entire Flash
program memory array is enabled by
clearing the CP bit of Configuration Word.
9.1
PMADRL and PMADRH Registers
The PMADRH:PMADRL register pair can address up
to a maximum of 512 words of program memory. When
selecting a program address value, the MSB of the
address is written to the PMADRH register and the LSB
is written to the PMADRL register.
DS40001585E-page 50
9.1.1
PMCON1 AND PMCON2
REGISTERS
PMCON1 is the control register for Flash program
memory accesses.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared by hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bit, when set, will allow a write operation to
occur. On power-up, the WREN bit is clear. The
WRERR bit is set when a write operation is interrupted
by a Reset during normal operation. In these situations,
following Reset, the user can check the WRERR bit
and execute the appropriate error handling routine.
The PMCON2 register is a write-only register. Attempting
to read the PMCON2 register will return all ‘0’s.
To enable writes to the program memory, a specific
pattern (the unlock sequence), must be written to the
PMCON2 register. The required unlock sequence
prevents inadvertent writes to the program memory
write latches and Flash program memory.
9.2
Flash Program Memory Overview
It is important to understand the Flash program memory
structure for erase and programming operations. Flash
program memory is arranged in rows. A row consists of
a fixed number of 14-bit program memory words. A row
is the minimum size that can be erased by user software.
After a row has been erased, the user can reprogram
all or a portion of this row. Data to be written into the
program memory row is written to 14-bit wide data write
latches. These write latches are not directly accessible
to the user, but may be loaded via sequential writes to
the PMDATH:PMDATL register pair.
Note:
If the user wants to modify only a portion
of a previously programmed row, then the
contents of the entire row must be read
and saved in RAM prior to the erase.
Then, new data and retained data can be
written into the write latches to reprogram
the row of Flash program memory. However, any unprogrammed locations can be
written without first erasing the row. In this
case, it is not necessary to save and
rewrite the other previously programmed
locations.
See Table 9-1 for Erase Row size and the number of
write latches for Flash program memory.
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
TABLE 9-1:
FLASH MEMORY
ORGANIZATION BY DEVICE
Device
PIC10(L)F320
PIC10(L)F322
9.2.1
Row Erase
(words)
Write
Latches
(words)
16
16
READING THE FLASH PROGRAM
MEMORY
FIGURE 9-1:
FLASH PROGRAM
MEMORY READ
FLOWCHART
Start
R ead O peration
Select
Program orC onfiguration M em ory
(C FG S)
To read a program memory location, the user must:
1.
2.
3.
Write
the
desired
address
to
the
PMADRH:PMADRL register pair.
Clear the CFGS bit of the PMCON1 register.
Then, set control bit RD of the PMCON1 register.
Once the read control bit is set, the program memory
Flash controller will use the second instruction cycle to
read the data. This causes the second instruction
immediately following the “BSF PMCON1,RD” instruction
to be ignored. The data is available in the very next cycle,
in the PMDATH:PMDATL register pair; therefore, it can
be read as two bytes in the following instructions.
PMDATH:PMDATL register pair will hold this value until
another read or until it is written to by the user.
Note:
The two instructions following a program
memory read are required to be NOPs.
This prevents the user from executing a
2-cycle instruction on the next instruction
after the RD bit is set.
Select
W ord Address
(PM AD R H :PM AD R L)
Initiate R ead operation
(R D = 1)
Instruction Fetched ignored
NOP execution forced
Instruction Fetched ignored
NOP execution forced
D ata read now in
PM D ATH :PM D ATL
End
R ead O peration
2011-2015 Microchip Technology Inc.
DS40001585E-page 51
PIC10(L)F320/322
FIGURE 9-2:
FLASH PROGRAM MEMORY READ CYCLE EXECUTION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Flash ADDR
Flash Data
PC + 1
INSTR (PC)
INSTR(PC - 1)
executed here
PMADRH,PMADRL
INSTR (PC + 1)
BSF PMCON1,RD
executed here
PC
+3
PC+3
PMDATH,PMDATL
INSTR(PC + 1)
instruction ignored
Forced NOP
executed here
PC + 5
PC + 4
INSTR (PC + 3)
INSTR(PC + 2)
instruction ignored
Forced NOP
executed here
INSTR (PC + 4)
INSTR(PC + 3)
executed here
INSTR(PC + 4)
executed here
RD bit
PMDATH
PMDATL
Register
EXAMPLE 9-1:
FLASH PROGRAM MEMORY READ
* This code block will read 1 word of program
* memory at the memory address:
PROG_ADDR_HI: PROG_ADDR_LO
*
data will be returned in the variables;
*
PROG_DATA_HI, PROG_DATA_LO
BANKSEL
MOVLW
MOVWF
MOVLW
MOVWF
PMADRL
PROG_ADDR_LO
PMADRL
PROG_ADDR_HI
PMADRH
; not required on devices with 1 Bank of SFRs
;
; Store LSB of address
;
; Store MSB of address
BCF
BSF
NOP
NOP
PMCON1,CFGS
PMCON1,RD
;
;
;
;
Do not select Configuration Space
Initiate read
Ignored (Figure 9-2)
Ignored (Figure 9-2)
MOVF
MOVWF
MOVF
MOVWF
PMDATL,W
PROG_DATA_LO
PMDATH,W
PROG_DATA_HI
;
;
;
;
Get LSB of word
Store in user location
Get MSB of word
Store in user location
DS40001585E-page 52
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
9.2.2
Note:
FLASH MEMORY UNLOCK
SEQUENCE
A delay of at least 100 s is required after
Power-On Reset (POR) before executing
a Flash memory unlock sequence.
The unlock sequence is a mechanism that protects the
Flash program memory from unintended self-write programming or erasing. The sequence must be executed
and completed without interruption to successfully
complete any of the following operations:
• Row Erase
• Load program memory write latches
• Write of program memory write latches to
program memory
• Write of program memory write latches to User
IDs
The unlock sequence consists of the following steps:
FIGURE 9-3:
FLASH PROGRAM
MEMORY UNLOCK
SEQUENCE FLOWCHART
Start
U nlock Sequence
W rite 055h to
PM C O N 2
W rite 0AAh to
PM C O N 2
Initiate
W rite orErase operation
(W R = 1)
1. Write 55h to PMCON2
2. Write AAh to PMCON2
3. Set the WR bit in PMCON1
Instruction Fetched ignored
NOP execution forced
4. NOP instruction
5. NOP instruction
Once the WR bit is set, the processor will always force
two NOP instructions. When an Erase Row or Program
Row operation is being performed, the processor will stall
internal operations (typical 2 ms), until the operation is
complete and then resume with the next instruction.
When the operation is loading the program memory write
latches, the processor will always force the two NOP
instructions and continue uninterrupted with the next
instruction.
Instruction Fetched ignored
NOP execution forced
End
U nlock Sequence
Since the unlock sequence must not be interrupted,
global interrupts must be disabled prior to the unlock
sequence and re-enabled after the unlock sequence is
completed.
2011-2015 Microchip Technology Inc.
DS40001585E-page 53
PIC10(L)F320/322
9.2.3
ERASING FLASH PROGRAM
MEMORY
While executing code, program memory can only be
erased by rows. To erase a row:
1.
2.
3.
4.
5.
Load the PMADRH:PMADRL register pair with
any address within the row to be erased.
Clear the CFGS bit of the PMCON1 register.
Set the FREE and WREN bits of the PMCON1
register.
Write 55h, then AAh, to PMCON2 (Flash
programming unlock sequence).
Set control bit WR of the PMCON1 register to
begin the erase operation.
See Example 9-2.
After the “BSF PMCON1,WR” instruction, the processor
requires two cycles to set up the erase operation. The
user must place two NOP instructions after the WR bit is
set. The processor will halt internal operations for the
typical 2 ms erase time. This is not Sleep mode as the
clocks and peripherals will continue to run. After the
erase cycle, the processor will resume operation with
the third instruction after the PMCON1 write instruction.
FIGURE 9-4:
FLASH PROGRAM
MEMORY ERASE
FLOWCHART
Start
Erase O peration
D isable Interrupts
(G IE = 0)
Select
Program orC onfiguration M em ory
(C FG S)
SelectR ow Address
(PM AD R H :PM AD R L)
SelectErase O peration
(FR EE = 1)
Enable W rite/Erase O peration
(W R EN = 1)
U nlock Sequence
Figure
(FI
G U R E9-3
x-x)
C PU stalls w hile
ER ASE operation com pletes
(2m s typical)
D isable W rite/Erase O peration
(W R EN = 0)
R e-enable Interrupts
(G IE = 1)
End
Erase O peration
DS40001585E-page 54
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
EXAMPLE 9-2:
ERASING ONE ROW OF PROGRAM MEMORY
Required
Sequence
; This row erase routine assumes the following:
; 1. A valid address within the erase row is loaded in ADDRH:ADDRL
; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
BCF
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
BCF
BSF
BSF
INTCON,GIE
PMADRL
ADDRL,W
PMADRL
ADDRH,W
PMADRH
PMCON1,CFGS
PMCON1,FREE
PMCON1,WREN
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
BCF
BSF
PMCON1,WREN
INTCON,GIE
2011-2015 Microchip Technology Inc.
; Disable ints so required sequences will execute properly
; not required on devices with 1 Bank of SFRs
; Load lower 8 bits of erase address boundary
; Load upper 6 bits of erase address boundary
; Not configuration space
; Specify an erase operation
; Enable writes
;
;
;
;
;
;
;
;
;
;
Start of required sequence to initiate erase
Write 55h
Write AAh
Set WR bit to begin erase
NOP instructions are forced as processor starts
row erase of program memory.
The processor stalls until the erase process is complete
after erase processor continues with 3rd instruction
; Disable writes
; Enable interrupts
DS40001585E-page 55
PIC10(L)F320/322
9.2.4
WRITING TO FLASH PROGRAM
MEMORY
Program memory is programmed using the following
steps:
1.
2.
3.
4.
Load the address in PMADRH:PMADRL of the
row to be programmed.
Load each write latch with data.
Initiate a programming operation.
Repeat steps 1 through 3 until all data is written.
The following steps must be completed to load the write
latches and program a row of program memory. These
steps are divided into two parts. First, each write latch
is loaded with data from the PMDATH:PMDATL using
the unlock sequence with LWLO = 1. When the last
word to be loaded into the write latch is ready, the
LWLO bit is cleared and the unlock sequence
executed. This initiates the programming operation,
writing all the latches into Flash program memory.
Note:
Before writing to program memory, the word(s) to be
written must be erased or previously unwritten.
Program memory can only be erased one row at a time.
No automatic erase occurs upon the initiation of the
write.
Program memory can be written one or more words at
a time. The maximum number of words written at one
time is equal to the number of write latches. See
Figure 9-5 (row writes to program memory with 16 write
latches) for more details.
The write latches are aligned to the Flash row address
boundary defined by the upper ten bits of
PMADRH:PMADRL, (PMADRH:PMADRL)
with the lower five bits of PMADRL, (PMADRL)
determining the write latch being loaded. Write operations do not cross these boundaries. At the completion
of a program memory write operation, the data in the
write latches is reset to contain 0x3FFF.
The special unlock sequence is required
to load a write latch with data or initiate a
Flash programming operation. If the
unlock sequence is interrupted, writing to
the latches or program memory will not be
initiated.
1.
2.
3.
Set the WREN bit of the PMCON1 register.
Clear the CFGS bit of the PMCON1 register.
Set the LWLO bit of the PMCON1 register.
When the LWLO bit of the PMCON1 register is
‘1’, the write sequence will only load the write
latches and will not initiate the write to Flash
program memory.
4. Load the PMADRH:PMADRL register pair with
the address of the location to be written.
5. Load the PMDATH:PMDATL register pair with
the program memory data to be written.
6. Execute the unlock sequence (Section 9.2.2
“Flash Memory Unlock Sequence”). The write
latch is now loaded.
7. Increment the PMADRH:PMADRL register pair
to point to the next location.
8. Repeat steps 5 through 7 until all but the last
write latch has been loaded.
9. Clear the LWLO bit of the PMCON1 register.
When the LWLO bit of the PMCON1 register is
‘0’, the write sequence will initiate the write to
Flash program memory.
10. Load the PMDATH:PMDATL register pair with
the program memory data to be written.
11. Execute the unlock sequence (Section 9.2.2
“Flash Memory Unlock Sequence”). The
entire program memory latch content is now
written to Flash program memory.
Note:
The program memory write latches are
reset to the blank state (0x3FFF) at the
completion of every write or erase
operation. As a result, it is not necessary
to load all the program memory write
latches. Unloaded latches will remain in
the blank state.
An example of the complete write sequence is shown in
Example 9-3. The initial address is loaded into the
PMADRH:PMADRL register pair; the data is loaded
using indirect addressing.
DS40001585E-page 56
2011-2015 Microchip Technology Inc.
BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 16 WRITE LATCHES
7
1 0 7
4 3
PM AD R L
PM AD R H
-
-
-
-
-
-
-
r4
r3
r2
r1
r0
c3
0
7
-
c2
c1
c0
5
-
0
7
PM D ATH
6
0
PM D ATL
8
14
Program M em ory W rite Latches
4
14
W rite Latch #0
00h
PM AD R L
14
5
14
14
W rite Latch #1
01h
14
W rite Latch #14 W rite Latch #15
0Eh
0Fh
14
14
14
PM AD R H :
PM AD R L
R ow
Addr
Addr
Addr
Addr
000h
0000h
0001h
000Eh
000Fh
001h
0010h
0011h
001Eh
001Fh
002h
0020h
0021h
002Eh
002Fh
01Eh
01E0h
01E1h
01EEh
01EFh
01Fh
01F0h
01F1h
01FEh
01FFh
C FG S = 0
2011-2015 Microchip Technology Inc.
R ow
Address
D ecode
Flash Program M em ory
000h
2000h -2003h
U SER ID 0 -3
C FG S = 1
2004h -2005h
2006h
2007h
2008h
reserved
D EVIC EID
R EVID
C onfiguration
W ord
reserved
C onfiguration M em ory
PIC10(L)F320/322
DS40001585E-page 57
FIGURE 9-5:
PIC10(L)F320/322
FIGURE 9-6:
FLASH PROGRAM MEMORY WRITE FLOWCHART
Start
W rite O peration
D eterm ine num berofw ords
to be w ritten into Program or
C onfiguration M em ory.
The num berofw ords cannot
exceed the num berofw ords
per row .
(w ord_cnt)
D isable Interrupts
(G IE = 0)
Select
Program orC onfig.M em ory
(C FG S)
Enable W rite/Erase
O peration (W R EN = 1)
Load the value to w rite
(PM D ATH :PM D ATL)
U pdate the w ord counter
(w ord_cnt--)
Lastw ord to
w rite ?
Yes
No
SelectR ow Address
(PM AD R H :PM AD R L)
U nlock Sequence
(Figure9-3
x-x)
Figure
W rite Latches to Flash
(LW LO = 0)
U nlock Sequence
(Figure9-3
x-x)
Figure
C PU stalls w hile W rite
operation com pletes
(2m s typical)
SelectW rite O peration
(FR EE = 0)
N o delay w hen w riting to
Program M em ory Latches
D isable
W rite/Erase O peration
(W R EN = 0)
Load W rite Latches O nly
(LW LO = 1)
R e-enable Interrupts
(G IE = 1)
Increm entAddress
(PM AD R H :PM AD R L++)
End
W rite O peration
DS40001585E-page 58
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
EXAMPLE 9-3:
WRITING TO FLASH PROGRAM MEMORY
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; This write routine assumes the following:
;
A valid starting address (the least significant bits = '00')
;
is loaded in ADDRH:ADDRL
;
ADDRH, ADDRL and DATADDR are all located in data memory
;
BANKSEL
PMADRH
MOVF
ADDRH,W
;Load initial address
MOVWF
PMADRH
;
MOVF
ADDRL,W
;
MOVWF
PMADRL
;
MOVF
DATAADDR,W
;Load initial data address
MOVWF
FSR
;
LOOP MOVF INDF,W
;Load first data byte into lower
MOVWF
PMDATL
;
INCF
FSR,F
;Next byte
MOVF
INDF,W
;Load second data byte into upper
MOVWF
PMDATH
;
INCF
FSR,F
;
BANKSEL PMCON1
BSF
PMCON1,WREN ;Enable writes
BCF
INTCON,GIE
;Disable interrupts (if using)
BTFSC
INTCON,GIE
;See AN576
GOTO
$-2
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
Required Sequence
MOVLW
55h
;Start of required write sequence:
MOVWF
PMCON2
;Write 55h
MOVLW
0AAh
;
MOVWF
PMCON2
;Write 0AAh
BSF
PMCON1,WR
;Set WR bit to begin write
NOP
;Required to transfer data to the buffer
NOP
;registers
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
BCF
PMCON1,WREN ;Disable writes
BSF
INTCON,GIE
;Enable interrupts (comment out if not using interrupts)
BANKSEL PMADRL
MOVF
PMADRL, W
INCF
PMADRL,F
;Increment address
ANDLW
0x03
;Indicates when sixteen words have been programmed
SUBLW
0x03
;Change value for different size write blocks
;0x0F = 16 words
;0x0B = 12 words
;0x07 = 8 words
;0x03 = 4 words
BTFSS
STATUS,Z
;Exit on a match,
GOTO
LOOP
;Continue if more data needs to be written
2011-2015 Microchip Technology Inc.
DS40001585E-page 59
PIC10(L)F320/322
9.3
Modifying Flash Program Memory
When modifying existing data in a program memory
row, and data within that row must be preserved, it must
first be read and saved in a RAM image. Program
memory is modified using the following steps:
1.
2.
3.
4.
5.
6.
7.
Load the starting address of the row to be
modified.
Read the existing data from the row into a RAM
image.
Modify the RAM image to contain the new data
to be written into program memory.
Load the starting address of the row to be
rewritten.
Erase the program memory row.
Load the write latches with data from the RAM
image.
Initiate a programming operation.
FIGURE 9-7:
FLASH PROGRAM
MEMORY MODIFY
FLOWCHART
Start
M odify O peration
R ead O peration
(Figure9-2
x.x)
Figure
An im age ofthe entire row read
m ustbe stored in R AM
M odify Im age
The w ords to be m odified are
changed in the R AM im age
Erase O peration
(Figure9-4
x.x)
Figure
W rite O peration
use R AM im age
(Figure9-5
x.x)
Figure
End
M odify O peration
DS40001585E-page 60
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
9.4
User ID, Device ID and
Configuration Word Access
Instead of accessing program memory, the User ID’s,
Device ID/Revision ID and Configuration Word can be
accessed when CFGS = 1 in the PMCON1 register.
This is the region that would be pointed to by
PC = 1, but not all addresses are accessible.
Different access may exist for reads and writes. Refer
to Table 9-2.
When read access is initiated on an address outside
the
parameters
listed
in
Table 9-2,
the
PMDATH:PMDATL register pair is cleared, reading
back ‘0’s.
TABLE 9-2:
USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1)
Address
Function
Read Access
Write Access
2000h-2003h
2006h
2007h
User IDs
Device ID/Revision ID
Configuration Word
Yes
Yes
Yes
Yes
No
No
EXAMPLE 9-4:
CONFIGURATION WORD AND DEVICE ID ACCESS
* This code block will read 1 word of program memory at the memory address:
*
PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;
*
PROG_DATA_HI, PROG_DATA_LO
BANKSEL
MOVLW
MOVWF
CLRF
PMADRL
PROG_ADDR_LO
PMADRL
PMADRH
; not required on devices with 1 Bank of SFRs
;
; Store LSB of address
; Clear MSB of address
BSF
BCF
BSF
NOP
NOP
BSF
PMCON1,CFGS
INTCON,GIE
PMCON1,RD
INTCON,GIE
;
;
;
;
;
;
Select Configuration Space
Disable interrupts
Initiate read
Executed (See Figure 9-2)
Ignored (See Figure 9-2)
Restore interrupts
MOVF
MOVWF
MOVF
MOVWF
PMDATL,W
PROG_DATA_LO
PMDATH,W
PROG_DATA_HI
;
;
;
;
Get LSB of word
Store in user location
Get MSB of word
Store in user location
2011-2015 Microchip Technology Inc.
DS40001585E-page 61
PIC10(L)F320/322
9.5
Write Verify
It is considered good programming practice to verify that
program memory writes agree with the intended value.
Since program memory is stored as a full page then the
stored program memory contents are compared with the
intended data stored in RAM after the last write is
complete.
FIGURE 9-8:
FLASH PROGRAM
MEMORY VERIFY
FLOWCHART
Start
Verify O peration
This routine assum es thatthe lastrow
ofdata written w as from an im age
saved in R AM . This im age w illbe used
to verify the data currently stored in
Flash Program M em ory.
Read O peration
(Figur
e x.x)
Figure
9-2
PM DAT =
RAM im age
?
Yes
No
No
Fail
Verify O peration
Last
W ord ?
Yes
End
Verify O peration
DS40001585E-page 62
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
9.6
Flash Program Memory Control Registers
REGISTER 9-1:
R/W-x/u
PMDATL: PROGRAM MEMORY DATA LOW
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PMDAT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
PMDAT: The value of the program memory word pointed to by PMADRH and PMADRL after a
Program Memory Read command.
REGISTER 9-2:
PMDATH: PROGRAM MEMORY DATA HIGH
U-0
U-0
—
—
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PMDAT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
PMDAT: The value of the program memory word pointed to by PMADRH and PMADRL after a
Program Memory Read command.
2011-2015 Microchip Technology Inc.
DS40001585E-page 63
PIC10(L)F320/322
REGISTER 9-3:
R/W-0/0
PMADRL: PROGRAM MEMORY ADDRESS LOW
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PMADR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
PMADR: Program Memory Read Address low bits
REGISTER 9-4:
PMADRH: PROGRAM MEMORY ADDRESS HIGH
U-0
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0/0
—
—
—
—
—
—
—
PMADR8
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-1
Unimplemented: Read as ‘0’
bit 0
PMADR8: Program Memory Read Address High bit
DS40001585E-page 64
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
REGISTER 9-5:
PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER
U-1(1)
R/W-0/0
R/W-0/0
—
CFGS
LWLO
R/W/HC-0/0 R/W/HC-0/q(2)
FREE
WRERR
R/W-0/0
R/S/HC-0/0
R/S/HC-0/0
WREN
WR
RD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
S = Bit can only be set
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HC = Bit is cleared by hardware
bit 7
Unimplemented: Read as ‘1’
bit 6
CFGS: Configuration Select bit
1 = Access Configuration, User ID and Device ID Registers
0 = Access Flash program memory
bit 5
LWLO: Load Write Latches Only bit(3)
1 = Only the addressed program memory write latch is loaded/updated on the next WR command
0 = The addressed program memory write latch is loaded/updated and a write of all program memory
write latches will be initiated on the next WR command
bit 4
FREE: Program Flash Erase Enable bit
1 = Performs an erase operation on the next WR command (hardware cleared upon completion)
0 = Performs an write operation on the next WR command
bit 3
WRERR: Program/Erase Error Flag bit
1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set
automatically on any set attempt (write ‘1’) of the WR bit).
0 = The program or erase operation completed normally.
bit 2
WREN: Program/Erase Enable bit
1 = Allows program/erase cycles
0 = Inhibits programming/erasing of program Flash
bit 1
WR: Write Control bit
1 = Initiates a program Flash program/erase operation.
The operation is self-timed and the bit is cleared by hardware once operation is complete.
The WR bit can only be set (not cleared) in software.
0 = Program/erase operation to the Flash is complete and inactive.
bit 0
RD: Read Control bit
1 = Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can
only be set (not cleared) in software.
0 = Does not initiate a program Flash read.
Note 1:
2:
3:
Unimplemented bit, read as ‘1’.
The WRERR bit is automatically set by hardware when a program memory write or erase operation is started
(WR = 1).
The LWLO bit is ignored during a program memory erase operation (FREE = 1).
2011-2015 Microchip Technology Inc.
DS40001585E-page 65
PIC10(L)F320/322
REGISTER 9-6:
PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
Program Memory Control Register 2
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
S = Bit can only be set
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
Flash Memory Unlock Pattern bits
To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the
PMCON1 register. The value written to this register is used to unlock the writes. There are specific
timing requirements on these writes.
TABLE 9-3:
SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY
Register on
Page
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
40
PMCON1
—
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
65
PMCON2
Program Memory Control Register 2
66
PMADRL
PMADR
64
—
PMADRH
—
—
—
PMDATL
—
PMDATH
Legend:
CONFIG
Legend:
—
—
PMADR8
—
64
63
PMDAT
63
— = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory module.
TABLE 9-4:
Name
—
PMDAT
Bits
SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
13:8
—
—
—
WRT
7:0
CP
MCLR
PWRTE
WDTE
Bit 10/2
Bit 9/1
BORV
LPBOR
BOREN
Bit 8/0
LVP
FOSC
Register
on Page
20
— = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory.
DS40001585E-page 66
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
10.0
I/O PORT
FIGURE 10-1:
Depending on which peripherals are enabled, some or
all of the pins may not be available as general purpose
I/O. In general, when a peripheral is enabled on a port
pin, that pin cannot be used as a general purpose
output. However, the pin can still be read.
PORTA has three standard registers for its operation.
These registers are:
• TRISA register (data direction)
• PORTA register (reads the levels on the pins of
the device)
• LATA register (output latch)
Some ports may have one or more of the following
additional registers. These registers are:
• ANSELA (analog select)
• WPUA (weak pull-up)
I/O PORT OPERATION
Read LATA
D
Write LATA
Write PORTA
TRISA
Q
CK
VDD
Data Register
Data Bus
I/O pin
Read PORTA
To peripherals
ANSELA
VSS
The Data Latch (LATA) register is useful for readmodify-write operations on the value that the I/O pins
are driving.
A write operation to the LATA register has the same
effect as a write to the corresponding PORTA register.
A read of the LATA register reads of the values held in
the I/O PORT latches, while a read of the PORTA
register reads the actual I/O pin value.
Ports that support analog inputs have an associated
ANSELA register. When an ANSEL bit is set, the digital
input buffer associated with that bit is disabled.
Disabling the input buffer prevents analog signal levels
on the pin between a logic high and low from causing
excessive current in the logic input circuitry. A
simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 10-1.
EXAMPLE 10-1:
;
;
;
;
INITIALIZING PORTA
This code example illustrates
initializing the PORTA register. The
other ports are initialized in the same
manner.
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
PORTA
PORTA
LATA
LATA
ANSELA
ANSELA
TRISA
B'00000011'
TRISA
;not required on devices
;Init PORTA
;not required on devices
;
;not required on devices
;digital I/O
;not required on devices
;Set RA as inputs
;and set RA as
;outputs
2011-2021 Microchip Technology Inc.
with 1 Bank of SFRs
with 1 Bank of SFRs
with 1 Bank of SFRs
with 1 Bank of SFRs
DS40001585E-page 67
PIC10(L)F320/322
10.1
PORTA Registers
PORTA is a 8-bit wide, bidirectional port. The
corresponding data direction register is TRISA
(Register 10-2). Setting a TRISA bit (= 1) will make the
corresponding PORTA pin an input (i.e., disable the
output driver). Clearing a TRISA bit (= 0) will make the
corresponding PORTA pin an output (i.e., enables
output driver and puts the contents of the output latch
on the selected pin). Example 10-1 shows how to
initialize PORTA.
Reading the PORTA register (Register 10-1) reads the
status of the pins, whereas writing to it will write to the
PORT latch. All write operations are read-modify-write
operations. Therefore, a write to a port implies that the
port pins are read, this value is modified and then
written to the PORT data latch (LATA).
10.1.3
Each PORTA pin is multiplexed with other functions. The
pins, their combined functions and their output priorities
are shown in Table 10-1.
When multiple outputs are enabled, the actual pin
control goes to the peripheral with the highest priority.
Digital output functions may control the pin when it is in
Analog mode with the priority shown in Table 10-1.
TABLE 10-1:
Function Priority(1)
RA0
ICSPDAT
CWG1A
PWM1
RA0
RA1
CWG1B
PWM2
CLC1
RA1
RA2
NCO1
CLKR
RA2
RA3
None
WEAK PULL-UPS
Each of the PORTA pins has an individually configurable internal weak pull-up. Control bits WPUA
enable or disable each pull-up (see Register 10-5).
Each weak pull-up is automatically turned off when the
port pin is configured as an output. All pull-ups are disabled on a Power-on Reset by the WPUEN bit of the
OPTION_REG register.
10.1.2
PORTA OUTPUT PRIORITY
Pin Name
The TRISA register (Register 10-2) controls the
PORTA pin output drivers, even when they are being
used as analog inputs. The user will ensure the bits in
the TRISA register are maintained set when using them
as analog inputs. I/O pins configured as analog input
always read ‘0’.
10.1.1
PORTA FUNCTIONS AND OUTPUT
PRIORITIES
Note 1:
Priority listed from highest to lowest.
ANSELA REGISTER
The ANSELA register (Register 10-4) is used to
configure the Input mode of an I/O pin to analog.
Setting the appropriate ANSELA bit high will cause all
digital reads on the pin to be read as ‘0’ and allow
analog functions on the pin to operate correctly.
The state of the ANSELA bits has no effect on digital
output functions. A pin with TRIS clear and ANSEL set
will still operate as a digital output, but the Input mode
will be analog. This can cause unexpected behavior
when executing read-modify-write instructions on the
affected port.
Note:
The ANSELA bits default to the Analog
mode after Reset. To use any pins as
digital general purpose or peripheral
inputs, the corresponding ANSEL bits
must be initialized to ‘0’ by user software.
DS40001585E-page 68
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
10.2
Register Definitions: PORTA
REGISTER 10-1:
PORTA: PORTA REGISTER
U-0
U-0
U-0
U-0
R-x/x
R/W-x/x
R/W-x/x
R/W-x/x
—
—
—
—
RA3
RA2
RA1
RA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
RA: PORTA I/O Value bits (RA3 is read-only)
Note 1:
Writes to PORTx are actually written to the corresponding LATx register. Reads from PORTx register
return actual I/O pin values.
REGISTER 10-2:
TRISA: PORTA TRI-STATE REGISTER
U-0
U-0
U-0
U-0
U-1
R/W-1/1
R/W-1/1
R/W-1/1
—
—
—
—
—(1)
TRISA2
TRISA1
TRISA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘0’.
bit 3
Unimplemented: Read as ‘1’.
bit 2-0
TRISA: RA Port I/O Tri-State Control bits
1 = Port output driver is disabled
0 = Port output driver is enabled
Note 1:
Unimplemented, read as ‘1’.
2011-2021 Microchip Technology Inc.
DS40001585E-page 69
PIC10(L)F320/322
REGISTER 10-3:
LATA: PORTA DATA LATCH REGISTER
U-0
U-0
U-0
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
—
—
—
—
—
LATA2
LATA1
LATA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-3
Unimplemented: Read as ‘0’.
bit 2-0
LATA: RA Output Latch Value bits
Note 1:
Writes to PORTx are actually written to the corresponding LATx register. Reads from LATx register return
register values, not I/O pin values.
REGISTER 10-4:
ANSELA: PORTA ANALOG SELECT REGISTER
U-0
U-0
U-0
U-0
U-0
R/W-1/1
R/W-1/1
R/W-1/1
—
—
—
—
—
ANSA2
ANSA1
ANSA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-3
Unimplemented: Read as ‘0’.
bit 2-0
ANSA: Analog Select between Analog or Digital Function on Pins RA, respectively
1 = Analog input. Pin is assigned as analog input(1). Digital Input buffer disabled.
0 = Digital I/O. Pin is assigned to port or Digital special function.
Note 1:
Setting a pin to an analog input automatically disables the digital input circuitry. Weak pull-ups, if
available, are unaffected. The corresponding TRIS bit must be set to Input mode by the user in order to
allow external control of the voltage on the pin.
DS40001585E-page 70
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
REGISTER 10-5:
WPUA: WEAK PULL-UP PORTA REGISTER
U-0
U-0
U-0
U-0
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
—
—
—
—
WPUA3
WPUA2
WPUA1
WPUA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘0’.
bit 3-0
WPUA: Weak Pull-up PORTA Control bits
1 = Weak Pull-up enabled(1)
0 = Weak Pull-up disabled.
Note 1:
Enabling weak pull-ups also requires that the WPUEN bit of the OPTION_REG register be cleared
(Register 16-1).
2011-2021 Microchip Technology Inc.
DS40001585E-page 71
PIC10(L)F320/322
TABLE 10-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSELA
—
—
—
—
—
ANSA2
ANSA1
ANSA0
70
IOCAF
—
—
—
—
IOCAF3
IOCAF2
IOCAF1
IOCAF0
76
IOCAN
—
—
—
—
IOCAN3
IOCAN2
IOCAN1
IOCAN0
75
IOCAP
—
—
—
—
IOCAP3
IOCAP2
IOCAP1
IOCAP0
75
LATA
—
—
—
—
—
LATA2
LATA1
LATA0
70
PORTA
—
—
—
—
RA3
RA2
RA1
RA0
69
(1)
TRISA2
TRISA1
TRISA0
69
WPUA2
WPUA1
WPUA0
71
Name
TRISA
—
—
—
—
WPUA
—
—
—
—
—
WPUA3
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by
PORTA.
Note 1: Unimplemented, read as ‘1’.
DS40001585E-page 72
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
11.0
INTERRUPT-ON-CHANGE
The PORTA pins can be configured to operate as
Interrupt-On-Change (IOC) pins. An interrupt can be
generated by detecting a signal that has either a rising
edge or a falling edge. Any individual PORTA pin, or
combination of PORTA pins, can be configured to
generate an interrupt. The Interrupt-on-change module
has the following features:
•
•
•
•
Interrupt-on-Change enable (Main Switch)
Individual pin configuration
Rising and falling edge detection
Individual pin interrupt flags
Figure 11-1 is a block diagram of the IOC module.
11.1
Enabling the Module
To allow individual PORTA pins to generate an interrupt,
the IOCIE bit of the INTCON register must be set. If the
IOCIE bit is disabled, the edge detection on the pin will
still occur, but an interrupt will not be generated.
11.2
Individual Pin Configuration
For each PORTA pin, a rising edge detector and a falling
edge detector are present. To enable a pin to detect a
rising edge, the associated IOCAPx bit of the IOCAP
register is set. To enable a pin to detect a falling edge,
the associated IOCANx bit of the IOCAN register is set.
A pin can be configured to detect rising and falling
edges simultaneously by setting both the IOCAPx bit
and the IOCANx bit of the IOCAP and IOCAN registers,
respectively.
2011-2021 Microchip Technology Inc.
11.3
Interrupt Flags
The IOCAFx bits located in the IOCAF register are
status flags that correspond to the interrupt-on-change
pins of PORTA. If an expected edge is detected on an
appropriately enabled pin, then the status flag for that pin
will be set, and an interrupt will be generated if the IOCIE
bit is set. The IOCIF bit of the INTCON register reflects
the status of all IOCAFx bits.
11.4
Clearing Interrupt Flags
The individual status flags, (IOCAFx bits), can be
cleared by resetting them to zero. If another edge is
detected during this clearing operation, the associated
status flag will be set at the end of the sequence,
regardless of the value actually being written.
To ensure that no detected edge is lost while clearing
flags, only AND operations masking out known changed
bits must be performed. The following sequence is an
example of what must be performed.
EXAMPLE 11-1:
MOVLW
XORWF
ANDWF
11.5
CLEARING INTERRUPT
FLAGS
0xff
IOCAF, W
IOCAF, F
Operation in Sleep
The interrupt-on-change interrupt sequence will wake
the device from Sleep mode, if the IOCIE bit is set.
If an edge is detected while in Sleep mode, the IOCAF
register will be updated prior to the first instruction
executed out of Sleep.
DS40001585E-page 73
PIC10(L)F320/322
FIGURE 11-1:
INTERRUPT-ON-CHANGE BLOCK DIAGRAM
IOCANx
D
Q4Q1
Q
CK
Edge
Detect
R
RAx
IOCAPx
D
Data Bus =
0 or1
Q
D
S
Q
To Data Bus
IOCAFx
CK
CK
W rite IOCAFx
R
IOCIE
R
Q2
From allother
IOCAFx individual
pin detectors
Q1
Q2
Q3
DS40001585E-page 74
IOC Interrupt
to CPU Core
Q1
Q1
Q2
Q2
Q3
Q3
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
11.6
Interrupt-On-Change Registers
REGISTER 11-1:
IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
—
—
—
—
IOCAP3
IOCAP2
IOCAP1
IOCAP0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘0’.
bit 3-0
IOCAP: Interrupt-on-Change PORTA Positive Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and
interrupt flag will be set upon detecting an edge.( 1)
0 = Interrupt-on-Change disabled for the associated pin.
Note 1:
Interrupt-on-change also requires that the IOCIE bit of the INTCON register be set (Register 6-1).
REGISTER 11-2:
IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
—
—
—
—
IOCAN3
IOCAN2
IOCAN1
IOCAN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘0’.
bit 3-0
IOCAN: Interrupt-on-Change PORTA Negative Edge Enable bits
1 = Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and
interrupt flag will be set upon detecting an edge.( 1)
0 = Interrupt-on-Change disabled for the associated pin.
Note 1:
Interrupt-on-change also requires that the IOCIE bit of the INTCON register be set (Register 6-1).
2011-2021 Microchip Technology Inc.
DS40001585E-page 75
PIC10(L)F320/322
REGISTER 11-3:
IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
—
—
—
—
IOCAF3
IOCAF2
IOCAF1
IOCAF0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
HS - Bit is set in hardware
bit 7-4
Unimplemented: Read as ‘0’.
bit 3-0
IOCAF: Interrupt-on-Change PORTA Flag bits
1 = An enable change was detected on the associated pin.
Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling
edge was detected on RAx.( 1)
0 = No change was detected, or the user cleared the detected change.
Note 1:
Interrupt-on-change also requires that the IOCIE bit of the INTCON register be set (Register 6-1).
TABLE 11-1:
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
40
IOCAF
—
—
—
—
IOCAF3
IOCAF2
IOCAF1
IOCAF0
76
IOCAN
—
—
—
—
IOCAN3
IOCAN2
IOCAN1
IOCAN0
75
IOCAP
—
—
—
—
IOCAP3
IOCAP2
IOCAP1
IOCAP0
75
TRISA
—
—
—
—
—(1)
TRISA2
TRISA1
TRISA0
69
Name
INTCON
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupt-on-Change.
Note 1: Unimplemented, read as ‘1’.
DS40001585E-page 76
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
12.0
FIXED VOLTAGE REFERENCE
(FVR)
12.1
Independent Gain Amplifiers
The output of the FVR supplied to the ADC is routed
through an independent programmable gain amplifier.
The amplifier can be configured to amplify the
reference voltage by 1x, 2x or 4x, to produce the three
possible voltage levels.
The Fixed Voltage Reference, or FVR, is a stable
voltage reference, independent of VDD, with 1.024V,
2.048V or 4.096V selectable output levels. The output
of the FVR can be configured to supply a reference
voltage to the following:
The ADFVR bits of the FVRCON register are
used to enable and configure the gain amplifier settings
for the reference supplied to the ADC module. Reference Section 15.0 “Analog-to-Digital Converter
(ADC) Module” for additional information.
• ADC input channel
The FVR can be enabled by setting the FVREN bit of
the FVRCON register.
To minimize current consumption when the FVR is
disabled, the FVR buffers must be turned off by
clearing the ADFVR bits.
12.2
FVR Stabilization Period
When the Fixed Voltage Reference module is enabled, it
requires time for the reference and amplifier circuits to
stabilize. Once the circuits stabilize and are ready for use,
the FVRRDY bit of the FVRCON register will be set. See
Section 24.0 “Electrical Specifications” for the
minimum delay requirement.
FIGURE 12-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
ADFVR
2
x1
x2
x4
FVR
(To ADC M odule)
1.024V Fixed
Reference
+
FVREN
FVRRDY
-
Any peripheral requiring
the Fixed Reference
(See Table 12-1)
TABLE 12-1:
PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR)
Peripheral
HFINTOSC
BOR
IVR
Conditions
Description
FOSC = 1
EC on CLKIN pin.
BOREN = 11
BOR always enabled.
BOREN = 10 and BORFS = 1
BOR disabled in Sleep mode, BOR Fast Start enabled.
BOREN = 01 and BORFS = 1
BOR under software control, BOR Fast Start enabled.
All PIC10F320/322 devices, when
VREGPM1 = 1 and not in Sleep
The device runs off of the Power-Save mode regulator when
in Sleep mode.
2011-2021 Microchip Technology Inc.
DS40001585E-page 77
PIC10(L)F320/322
12.3
FVR Control Registers
REGISTER 12-1:
FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER
R/W-0/0
R-q/q
FVREN
FVRRDY(1)
R/W-0/0
TSEN
(3)
R/W-0/0
TSRNG
(3)
U-0
U-0
—
—
R/W-0/0
R/W-0/0
ADFVR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
q = Value depends on condition
bit 7
FVREN: Fixed Voltage Reference Enable bit
1 = Fixed Voltage Reference is enabled
0 = Fixed Voltage Reference is disabled
bit 6
FVRRDY: Fixed Voltage Reference Ready Flag bit(1)
1 = Fixed Voltage Reference output is ready for use
0 = Fixed Voltage Reference output is not ready or not enabled
bit 5
TSEN: Temperature Indicator Enable bit(3)
1 = Temperature Indicator is enabled
0 = Temperature Indicator is disabled
bit 4
TSRNG: Temperature Indicator Range Selection bit(3)
1 = VOUT = VDD - 4VT (High Range)
0 = VOUT = VDD - 2VT (Low Range)
bit 3-2
Unimplemented: Read as ‘0 ‘
bit 1-0
ADFVR: ADC Fixed Voltage Reference Selection bit
11 = ADC Fixed Voltage Reference Peripheral output is 4x (4.096V)(2)
10 = ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)(2)
01 = ADC Fixed Voltage Reference Peripheral output is 1x (1.024V)
00 = ADC Fixed Voltage Reference Peripheral output is off.
Note 1:
2:
3:
FVRRDY indicates the true state of the FVR.
Fixed Voltage Reference output cannot exceed VDD.
See Section 14.0 “Temperature Indicator Module” for additional information.
TABLE 12-2:
Name
FVRCON
SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
FVREN
FVRRDY
TSEN
TSRNG
—
—
Bit 1
Bit 0
ADFVR
Register
on page
78
Legend: Shaded cells are not used with the Fixed Voltage Reference.
DS40001585E-page 78
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
13.0
INTERNAL VOLTAGE
REGULATOR (IVR)
The Internal Voltage Regulator (IVR), which provides
operation above 3.6V is available on:
• PIC10F320
• PIC10F322
This circuit regulates a voltage for the internal device
logic while permitting the VDD and I/O pins to operate
at a higher voltage. When VDD approaches the
regulated voltage, the IVR output automatically tracks
the input voltage.
The IVR operates in one of three power modes based
on user configuration and peripheral selection. The
operating power modes are:
- High
- Low
- Power-Save Sleep mode
Power modes are selected automatically depending on
the device operation, as shown in Table 13-1. Tracking
mode is selected automatically when VDD drops below
the safe operating voltage of the core.
Note:
IVR is disabled in Tracking mode, but will
consume power. See Section 24.0
“Electrical Specifications” for more
information.
TABLE 13-1:
VREGPM1 Bit
IVR POWER MODES - REGULATED
Sleep Mode
Memory Bias Power Mode
EC Mode or INTOSC = 16 MHz (HP Bias)
INTOSC = 1 to 8 MHz (MP Bias)
INTOSC = 31 kHz to 500 kHz (LP Bias)
0
Yes
Don’t Care
No HFINTOSC
1
Yes
No Peripherals
Note 1: Forced to Low-Power mode by any of the following conditions:
• BOR is enabled
• HFINTOSC is an active peripheral source
• Self-write is active
• ADC is in an active conversion
x
No
2011-2021 Microchip Technology Inc.
IVR Power Mode
High
Low
Low
Power Save(1)
DS40001585E-page 79
PIC10(L)F320/322
REGISTER 13-1:
U-0
—
VREGCON: VOLTAGE REGULATOR CONTROL REGISTER
U-0
—
U-0
—
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U-0
—
U-0
—
U-0
—
R/W-0/0
VREGPM1
R/W-1/1
Reserved
bit 0
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-2
Unimplemented: Read as ‘0’.
bit 1
VREGPM1: Voltage Regulator Power Mode Selection bit
1 = Power-Save Sleep mode enabled in Sleep. Draws lowest current in Sleep, slower wake-up.
0 = Low-Power mode enabled in Sleep. Draws higher current in Sleep, faster wake-up.
bit 0
Reserved: Maintain this bit set.
DS40001585E-page 80
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
14.0
TEMPERATURE INDICATOR
MODULE
FIGURE 14-1:
This family of devices is equipped with a temperature
circuit designed to measure the operating temperature
of the silicon die. The circuit’s range of operating
temperature falls between of -40°C and +85°C. The
output is a voltage that is proportional to the device
temperature. The output of the temperature indicator is
internally connected to the device ADC.
Rev. 10-000069A
7/31/2013
VDD
TSEN
The circuit may be used as a temperature threshold
detector or a more accurate temperature indicator,
depending on the level of calibration performed. A onepoint calibration allows the circuit to indicate a
temperature closely surrounding that point. A two-point
calibration allows the circuit to sense the entire range
of temperature more accurately. Reference Application
Note AN1333, “Use and Calibration of the Internal
Temperature Indicator” (DS01333) for more details
regarding the calibration process.
14.1
TEMPERATURE CIRCUIT
DIAGRAM
TSRNG
VOUT
To ADC
Temp. Indicator
Circuit Operation
Figure 14-1 shows a simplified block diagram of the
temperature circuit. The proportional voltage output is
achieved by measuring the forward voltage drop across
multiple silicon junctions.
Equation 14-1 describes the output characteristics of
the temperature indicator.
14.2
Minimum Operating VDD vs.
Minimum Sensing Temperature
When the temperature circuit is operated in low range,
the device may be operated at any operating voltage
that is within specifications.
High Range: VOUT = VDD - 4VT
When the temperature circuit is operated in high range,
the device operating voltage, VDD, must be high
enough to ensure that the temperature circuit is
correctly biased.
Low Range: VOUT = VDD - 2VT
Table 14-1 shows the recommended minimum VDD vs.
range setting.
EQUATION 14-1:
VOUT RANGES
The temperature sense circuit is integrated with the
Fixed Voltage Reference (FVR) module. See
Section 12.0 “Fixed Voltage Reference (FVR)” for
more information.
The circuit is enabled by setting the TSEN bit of the
FVRCON register. When disabled, the circuit draws no
current.
TABLE 14-1:
RECOMMENDED VDD VS.
RANGE
Min. VDD, TSRNG = 1
Min. VDD, TSRNG = 0
3.6V
1.8V
14.3
Temperature Output
The circuit operates in either high or low range. The high
range, selected by setting the TSRNG bit of the
FVRCON register, provides a wider output voltage. This
provides more resolution over the temperature range,
but may be less consistent from part to part. This range
requires a higher bias voltage to operate and thus, a
higher VDD is needed.
The output of the circuit is measured using the internal
Analog-to-Digital Converter. A channel is reserved for
the temperature circuit output. Refer to Section 15.0
“Analog-to-Digital Converter (ADC) Module” for
detailed information.
The low range is selected by clearing the TSRNG bit of
the FVRCON0 register. The low range generates a
lower voltage drop and thus, a lower bias voltage is
needed to operate the circuit. The low range is provided
for low voltage operation.
To ensure accurate temperature measurements, the
user must wait at least 200 s after the ADC input
multiplexer is connected to the temperature indicator
output before the conversion is performed. In addition,
the user must wait 200 s between sequential
conversions of the temperature indicator output.
2011-2021 Microchip Technology Inc.
14.4
ADC Acquisition Time
DS40001585E-page 81
PIC10(L)F320/322
TABLE 14-2:
Name
FVRCON
SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
FVREN
FVRRDY
TSEN
TSRNG
—
—
ADCON
ADRES
ADCS
CHS
A/D Result Register
Bit 1
Bit 0
ADFVR
GO/
DONE
ADON
Register
on Page
78
88
89
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by the temperature indicator module.
DS40001585E-page 82
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
15.0
ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
The Analog-to-Digital Converter (ADC) converts an
analog input signal to an 8-bit binary representation of
that signal. This device uses three analog input
channels, which are multiplexed into a single sample
and hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates an 8-bit binary result via successive
approximation and stores the conversion result into the
ADC Result (ADRES) register. Figure 15-1 shows the
block diagram of the ADC.
The ADC voltage reference is software selectable to be
internally generated.
The ADC can generate an interrupt upon completion of
a conversion. This interrupt can be used to wake-up the
device from Sleep.
FIGURE 15-1:
ADC SIMPLIFIED BLOCK DIAGRAM
VREF- = Vss
AN0
000
AN1
001
AN2
010
Reserved
011
Reserved
Reserved
100
Temp Indicator
110
FVR
111
101
VREF+ = VDD
ADC
8
GO/DONE
ADRES
ADON(1)
CHS(2)
Note 1:
2:
VSS
When ADON = 0, all multiplexer inputs are disconnected.
See ADCON register (Register 15-1) for detailed analog channel selection per device.
2011-2015 Microchip Technology Inc.
DS40001585E-page 83
PIC10(L)F320/322
15.1
ADC Configuration
When configuring and using the ADC the following
functions must be considered:
•
•
•
•
Port configuration
Channel selection
ADC conversion clock source
Interrupt control
15.1.1
PORT CONFIGURATION
The ADC can be used to convert both analog and
digital signals. When converting analog signals, the I/O
pin must be configured for analog by setting the
associated TRIS and ANSEL bits. Refer to
Section 10.0 “I/O Port” for more information.
Note:
15.1.2
Analog voltages on any pin that is defined
as a digital input may cause the input buffer to conduct excess current.
CHANNEL SELECTION
There are up to five channel selections available:
• AN pins
• Temperature Indicator
• FVR (Fixed Voltage Reference) Output
Refer to Section 12.0 “Fixed Voltage Reference
(FVR)” and Section 14.0 “Temperature Indicator
Module” for more information on these channel selections.
15.1.4
CONVERSION CLOCK
The source of the conversion clock is software selectable via the ADCS bits of the ADCON register
(Register 15-1). There are seven possible clock
options:
•
•
•
•
•
•
•
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC (dedicated internal RC oscillator)
The time to complete one bit conversion is defined as
TAD. One full 8-bit conversion requires 9.5 TAD periods
as shown in Figure 15-2.
For correct conversion, the appropriate TAD specification must be met. Refer to the A/D conversion requirements in Section 24.0 “Electrical Specifications” for
more information. Table 15-1 gives examples of
appropriate ADC clock selections.
Note:
Unless using the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
The CHS bits of the ADCON register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 15.2
“ADC Operation” for more information.
15.1.3
ADC VOLTAGE REFERENCE
There is no external voltage reference connections to
the ADC. Only VDD can be used as a reference source.
The FVR is only available as an input channel and not
a VREF+ input to the ADC.
DS40001585E-page 84
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
TABLE 15-1:
ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES
ADC Clock Period (TAD)
Device Frequency (FOSC)
ADC
Clock Source
ADCS
16 MHz
8 MHz
4 MHz
1 MHz
FOSC/2
000
125 ns(1)
250 ns(1)
500 ns(1)
2.0 s
FOSC/4
100
250 ns
(1)
(1)
FOSC/8
001
0.5 s(1)
FOSC/16
101
1.0 s
FOSC/32
010
2.0 s
FOSC/64
110
4.0 s
FRC
x11
1.0-6.0 s(1,3)
Legend:
Note 1:
2:
3:
1.0 s
4.0 s
1.0 s
2.0 s
8.0 s(2)
2.0 s
4.0 s
16.0 s(2)
500 ns
4.0 s
8.0 s
(2)
32.0 s(2)
(2)
8.0 s
1.0-6.0 s(1,3)
(2)
64.0 s(2)
16.0 s
1.0-6.0 s(1,3)
1.0-6.0 s(1,3)
Shaded cells are outside of recommended range.
These values violate the minimum required TAD time.
For faster conversion times, the selection of another clock source is recommended.
The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the
system clock FOSC. However, the FRC clock source must be used when conversions are to be performed with the
device in Sleep mode.
FIGURE 15-2:
ANALOG-TO-DIGITAL CONVERSION TAD CYCLES
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9
b2
b4
b5
b0
b7
b6
b1
b3
Conversion starts
Holding capacitor is disconnected from analog input
(typically 100 ns)
Set GO bit
On the following cycle:
ADRES is loaded, GO bit is cleared,
ADIF bit is set, holding capacitor is
connected to analog input.
2011-2015 Microchip Technology Inc.
DS40001585E-page 85
PIC10(L)F320/322
15.1.5
INTERRUPTS
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC Interrupt Flag is the ADIF bit in
the PIR1 register. The ADC Interrupt Enable is the
ADIE bit in the PIE1 register. The ADIF bit must be
cleared in software.
Note:
The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to
wake-up from Sleep and resume in-line code execution, the GIE and PEIE bits of the INTCON register
must be disabled. If the GIE and PEIE bits of the
INTCON register are enabled, execution will switch to
the Interrupt Service Routine.
15.2
15.2.1
ADC Operation
STARTING A CONVERSION
To enable the ADC module, the ADON bit of the
ADCON register must be set to a ‘1’. Setting the GO/
DONE bit of the ADCON register to a ‘1’ will start the
Analog-to-Digital conversion.
Note:
15.2.2
The GO/DONE bit must not be set in the
same instruction that turns on the ADC.
Refer to Section 15.2.5 “A/D Conversion Procedure”.
COMPLETION OF A CONVERSION
When the conversion is complete, the ADC module will:
• Clear the GO/DONE bit
• Set the ADIF Interrupt Flag bit
• Update the ADRES register with new conversion
result
15.2.3
TERMINATING A CONVERSION
If a conversion must be terminated before completion,
the GO/DONE bit can be cleared in software. The
ADRES register will be updated with the partially complete Analog-to-Digital conversion sample. Incomplete
bits will match the last bit converted.
Note:
15.2.4
A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.
ADC OPERATION DURING SLEEP
The ADC module can operate during Sleep. This
requires the ADC clock source to be set to the FRC
option. When the FRC clock source is selected, the
ADC waits one additional instruction before starting the
conversion. This allows the SLEEP instruction to be
executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
will wake-up from Sleep when the conversion
completes. If the ADC interrupt is disabled, the ADC
module is turned off after the conversion completes,
although the ADON bit remains set.
When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off,
although the ADON bit remains set.
DS40001585E-page 86
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
15.2.5
A/D CONVERSION PROCEDURE
This is an example procedure for using the ADC to
perform an Analog-to-Digital conversion:
1.
2.
3.
4.
5.
6.
7.
8.
Configure Port:
• Disable pin output driver (Refer to the TRIS
register)
• Configure pin as analog (Refer to the ANSEL
register)
• Disable weak pull-ups either globally (Refer
to the OPTION_REG register) or individually
(Refer to the appropriate WPUX register)
Configure the ADC module:
• Select ADC conversion clock
• Select ADC input channel
• Turn on ADC module
Configure ADC interrupt (optional):
• Clear ADC interrupt flag
• Enable ADC interrupt
• Enable peripheral interrupt
• Enable global interrupt(1)
Wait the required acquisition time(2).
Start conversion by setting the GO/DONE bit.
Wait for ADC conversion to complete by one of
the following:
• Polling the GO/DONE bit
• Waiting for the ADC interrupt (interrupts
enabled)
Read ADC Result.
Clear the ADC interrupt flag (required if interrupt
is enabled).
Note 1: The global interrupt can be disabled if the
user is attempting to wake-up from Sleep
and resume in-line code execution.
2: Refer to Section 15.4 “A/D Acquisition
Requirements”.
2011-2015 Microchip Technology Inc.
DS40001585E-page 87
PIC10(L)F320/322
15.3
ADC Register Definitions
The following registers are used to control the
operation of the ADC.
REGISTER 15-1:
R/W-0/0
ADCON: A/D CONTROL REGISTER 0
R/W-0/0
R/W-0/0
R/W-0/0
ADCS
R/W-0/0
R/W-0/0
CHS
R/W-0/0
R/W-0/0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-5
ADCS: A/D Conversion Clock Select bits
111 = FRC
110 = FOSC/64
101 = FOSC/16
100 = FOSC/4
011 = FRC
010 = FOSC/32
001 = FOSC/8
000 = FOSC/2
bit 4-2
CHS: Analog Channel Select bits
111 = FVR (Fixed Voltage Reference) Buffer Output(2)
110 = Temperature Indicator(1)
101 = Reserved. No channel connected.
100 = Reserved. No channel connected.
011 = Reserved. No channel connected.
010 = AN2
001 = AN1
000 = AN0
bit 1
GO/DONE: A/D Conversion Status bit
If ADON = 1:
1 = A/D conversion in progress (Setting this bit starts the A/D conversion)
0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D
conversion is complete.)
If this bit is cleared while a conversion is in progress, the conversion will stop and the results of the
conversion up to this point will be transferred to the result registers, but the ADIF interrupt flag bit will
not be set.
If ADON = 0:
0 = A/D conversion not in progress
bit 0
Note 1:
2:
ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current
See Section 14.0 “Temperature Indicator Module” for more information.
See Section 12.0 “Fixed Voltage Reference (FVR)” for more information.
DS40001585E-page 88
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
REGISTER 15-2:
R/W-x/u
ADRES: ADC RESULT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
ADRES: ADC Result Register bits
8-bit result
2011-2015 Microchip Technology Inc.
DS40001585E-page 89
PIC10(L)F320/322
15.4
A/D Acquisition Requirements
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the input channel voltage level. The Analog
Input model is shown in Figure 15-3. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), refer
to Figure 15-3. The maximum recommended
impedance for analog sources is 10 k. As the
EQUATION 15-1:
Assumptions:
source impedance is decreased, the acquisition time
may be decreased. After the analog input channel is
selected (or changed), an A/D acquisition must be
done before the conversion can be started. To calculate
the minimum acquisition time, Equation 15-1 may be
used. This equation assumes that 1/2 LSb error is used
(511 steps for the ADC). The 1/2 LSb error is the
maximum error allowed for the ADC to meet its
specified resolution.
ACQUISITION TIME EXAMPLE
Tem perature = 50°C and externalim pedance of10k 5.0V V D D
TAC Q = Am plifier Settling Tim e + H old Capacitor Charging Tim e + Tem perature Coefficient
= TAM P + TC + TC O FF
= 2µs + TC + Tem perature -25°C 0.05µs/°C
The value for TC can be approximated with the following equations:
1
---------------- = V C H O LD
V AP P LIED 1 – ------n---+1
2
–1
;[1] VCHOLD charged to within 1/2 lsb
–TC
---------
RC
V AP P LIED 1 – e = V C H O LD
;[2] VCHOLD charge response to VAPPLIED
–Tc
--------
1
RC
V AP P LIED 1 – e = V A P PLIE D 1 – ------n------------------- ;combining [1] and [2]
+1
2
–1
Note: Where n = number of bits of the ADC.
Solving for TC:
TC = –C H O LD R IC + R SS + R S ln(1/511)
= –10pF 1k + 7k + 10k ln(0.001957)
= 1.12µs
Therefore:
TA C Q = 2µs + 1.12µs + 50°C-25°C 0.05µs/°C
= 4.37µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
DS40001585E-page 90
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
FIGURE 15-3:
ANALOG INPUT MODEL
VDD
Analog
Input
pin
Rs
VT 0.6V
CPIN
5 pF
VA
RIC 1k
Sampling
Switch
SS Rss
I LEAKAGE(1)
VT 0.6V
CHOLD = 10 pF
VSS/VREF-
Legend: CHOLD
CPIN
6V
5V
VDD 4V
3V
2V
= Sample/Hold Capacitance
= Input Capacitance
I LEAKAGE = Leakage current at the pin due to
various junctions
= Interconnect Resistance
RIC
= Resistance of Sampling Switch
RSS
SS
= Sampling Switch
VT
= Threshold Voltage
Note 1:
FIGURE 15-4:
RSS
5 6 7 8 9 10 11
Sampling Switch
(k)
Refer to Section 24.0 “Electrical Specifications”.
ADC TRANSFER FUNCTION
Full-Scale Range
FFh
FEh
ADC Output Code
FDh
FCh
FBh
03h
02h
01h
00h
Analog Input Voltage
0.5 LSB
VREF-
2011-2015 Microchip Technology Inc.
Zero-Scale
Transition
1.5 LSB
Full-Scale
Transition
VREF+
DS40001585E-page 91
PIC10(L)F320/322
TABLE 15-2:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH ADC
Bit 7
ADCON
Bit 6
Bit 5
Bit 4
ADCS
Bit 3
Bit 2
CHS
ADRES
Bit 1
Bit 0
Register
on Page
GO/DONE
ADON
88
ADRES
89
ANSELA
—
—
—
—
—
ANSA2
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
—
—
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
40
PIE1
—
ADIE
—
NCO1IE
CLC1IE
—
TMR2IE
—
41
PIR1
—
ADIF
—
NCO1IF
CLC1IF
—
TMR2IF
—
42
TRISA
—
—
—
—
—
TRISA2
TRISA1
TRISA0
69
Legend:
ANSA1
ANSA0
ADFVR
70
78
x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not
used for ADC module.
DS40001585E-page 92
2011-2015 Microchip Technology Inc.
PIC10(L)F320/322
16.0
TIMER0 MODULE
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
The Timer0 module is an 8-bit timer/counter with the
following features:
•
•
•
•
•
Note:
8-bit timer/counter register (TMR0)
8-bit prescaler (independent of Watchdog Timer)
Programmable internal or external clock source
Programmable external clock edge selection
Interrupt on overflow
16.1.2
The value written to the TMR0 register
can be adjusted, in order to account for
the two instruction cycle delay when
TMR0 is written.
8-BIT COUNTER MODE
Figure 16-1 is a block diagram of the Timer0 module.
In 8-Bit Counter mode, the Timer0 module will increment
on every rising or falling edge of the T0CKI pin.
16.1
8-Bit Counter mode using the T0CKI pin is selected by
setting the T0CS bit in the OPTION_REG register to ‘1’.
Timer0 Operation
The rising or falling transition of the incrementing edge
for the external input source is determined by the T0SE
bit in the OPTION_REG register.
The Timer0 module can be used as either an 8-bit timer
or an 8-bit counter.
16.1.1
8-BIT TIMER MODE
The Timer0 module will increment every instruction
cycle, if used without a prescaler. 8-Bit Timer mode is
selected by clearing the T0CS bit of the OPTION_REG
register.
FIGURE 16-1:
BLOCK DIAGRAM OF THE TIMER0 PRESCALER
FOSC/4
Data Bus
0
8
T0CKI
1
1
SYNC
2 TCY
TMR0
0
T0SE
T0CS
8-bit
Prescaler
PSA
Set Flag bit TMR0IF
on Overflow
8
PS
2011-2021 Microchip Technology Inc.
DS40001585E-page 93
PIC10(L)F320/322
16.1.3
SOFTWARE PROGRAMMABLE
PRESCALER
A single software programmable prescaler is available
for use with Timer0. The prescaler assignment is
controlled by the PSA bit of the OPTION_REG register.
To assign the prescaler to Timer0, the PSA bit must be
cleared to a ‘0’.
There are eight prescaler options for the Timer0
module ranging from 1:2 to 1:256. The prescale values
are selectable via the PS bits of the
OPTION_REG register.
The prescaler is not readable or writable. When
assigned to the Timer0 module, all instructions writing to
the TMR0 register will clear the prescaler.
16.1.4
TIMER0 INTERRUPT
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The TMR0IF
interrupt flag bit of the INTCON register is set every
time the TMR0 register overflows, regardless of
whether or not the Timer0 interrupt is enabled. The
TMR0IF bit can only be cleared in software. The Timer0
interrupt enable is the TMR0IE bit of the INTCON
register.
Note:
16.1.5
The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
8-BIT COUNTER MODE
SYNCHRONIZATION
When in 8-Bit Counter mode, the incrementing edge on
the T0CKI pin must be synchronized to the instruction
clock. Synchronization can be accomplished by
sampling the prescaler output on the Q2 and Q4 cycles
of the instruction clock. The high and low periods of the
external clocking source must meet the timing
requirements as shown in Section 24.0 “Electrical
Specifications”.
DS40001585E-page 94
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
REGISTER 16-1:
R/W-1/u
WPUEN
(1)
OPTION_REG: OPTION REGISTER
R/W-1/u
R/W-1/u
R/W-1/u
R/W-1/u
INTEDG
T0CS
T0SE
PSA
R/W-1/u
R/W-1/u
R/W-1/u
PS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
WPUEN: Weak Pull-up Enable bit(1)
1 = Weak pull-ups are disabled
0 = Weak pull-ups are enabled by individual PORT latch values
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is inactive and has no effect on the Timer 0 module
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS: Prescaler Rate Select bits
Bit Value
000
001
010
011
100
101
110
111
Note 1:
INTCON
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
WPUEN does not disable the pull-up for the MCLR input when MCLR = 1.
TABLE 16-1:
Name
TMR0 Rate
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
40
T0SE
PSA
OPTION_REG WPUEN INTEDG
T0CS
TMR0
TRISA
PS
95
Timer0 module Register
—
—
—
—
—
TRISA2
40
TRISA1
TRISA0
69
Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the
Timer0 module.
2011-2021 Microchip Technology Inc.
DS40001585E-page 95
PIC10(L)F320/322
17.0
TIMER2 MODULE
The Timer2 module is an 8-bit timer with the following
features:
•
•
•
•
8-bit timer register (TMR2)
8-bit period register (PR2)
Interrupt on TMR2 match with PR2
Software programmable prescaler (1:1, 1:4, 1:16,
1:64)
• Software programmable postscaler (1:1 to 1:16)
Timer2 is turned on by setting the TMR2ON bit in the
T2CON register to a ‘1’. Timer2 is turned off by clearing
the TMR2ON bit to a ‘0’.
The Timer2 prescaler is controlled by the T2CKPS bits
in the T2CON register. The Timer2 postscaler is
controlled by the TOUTPS bits in the T2CON register.
The prescaler and postscaler counters are cleared
when:
See Figure 17-1 for a block diagram of Timer2.
17.1
The TMR2 and PR2 registers are both fully readable
and writable. On any Reset, the TMR2 register is set to
00h and the PR2 register is set to FFh.
Timer2 Operation
The clock input to the Timer2 module is the system
instruction clock (FOSC/4). The clock is fed into the
Timer2 prescaler, which has prescale options of 1:1,
1:4 or 1:64. The output of the prescaler is then used to
increment the TMR2 register.
• A write to TMR2 occurs.
• A write to T2CON occurs.
• Any device Reset occurs (Power-on Reset, MCLR
Reset, Watchdog Timer Reset, or Brown-out
Reset).
Note:
TMR2 is not cleared when T2CON is
written.
The values of TMR2 and PR2 are constantly compared
to determine when they match. TMR2 will increment
from 00h until it matches the value in PR2. When a
match occurs, two things happen:
• TMR2 is reset to 00h on the next increment cycle.
• The Timer2 postscaler is incremented.
The match output of the Timer2/PR2 comparator is
then fed into the Timer2 postscaler. The postscaler has
postscale options of 1:1 to 1:16 inclusive. The output of
the Timer2 postscaler is used to set the TMR2IF
interrupt flag bit in the PIR1 register.
FIGURE 17-1:
TIMER2 BLOCK DIAGRAM
TMR2
Output
FOSC/4
Prescaler
1:1, 1:4, 1:16, 1:64
2
TMR2
Comparator
Sets Flag
bit TMR2IF
Reset
EQ
Postscaler
1:1 to 1:16
T2CKPS
PR2
4
TOUTPS
DS40001585E-page 96
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
REGISTER 17-1:
U-0
T2CON: TIMER2 CONTROL REGISTER
R/W-0/0
R/W-0/0
—
R/W-0/0
R/W-0/0
R/W-0/0
TOUTPS
R/W-0/0
TMR2ON
R/W-0/0
T2CKPS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-3
TOUTPS: Timer2 Output Postscaler Select bits
1111 = 1:16 Postscaler
1110 = 1:15 Postscaler
1101 = 1:14 Postscaler
1100 = 1:13 Postscaler
1011 = 1:12 Postscaler
1010 = 1:11 Postscaler
1001 = 1:10 Postscaler
1000 = 1:9 Postscaler
0111 = 1:8 Postscaler
0110 = 1:7 Postscaler
0101 = 1:6 Postscaler
0100 = 1:5 Postscaler
0011 = 1:4 Postscaler
0010 = 1:3 Postscaler
0001 = 1:2 Postscaler
0000 = 1:1 Postscaler
bit 2
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0
T2CKPS: Timer2 Clock Prescale Select bits
11 = Prescaler is 64
10 = Prescaler is 16
01 = Prescaler is 4
00 = Prescaler is 1
TABLE 17-1:
Name
Bit 7
INTCON
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
40
PIE1
—
ADIE
—
NCO1IE
CLC1IE
—
TMR2IE
—
41
PIR1
—
ADIF
—
NCO1IF
CLC1IF
—
TMR2IF
—
42
PR2
Timer2 module Period Register
TMR2
T2CON
Legend:
96
Timer2 module Register
—
TOUTPS
96
TMR2ON
T2CKPS
97
x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module.
2011-2021 Microchip Technology Inc.
DS40001585E-page 97
PIC10(L)F320/322
18.0
PULSE-WIDTH MODULATION
(PWM) MODULE
Figure 18-1 shows a simplified block diagram of PWM
operation.
Figure 18-2 shows a typical waveform of the PWM
signal.
The PWM module generates a Pulse-Width Modulated
signal determined by the duty cycle, period, and
resolution that are configured by the following registers:
•
•
•
•
•
PR2
T2CON
PWMxDCH
PWMxDCL
PWMxCON
FIGURE 18-1:
SIMPLIFIED PWM BLOCK DIAGRAM
Duty Cycle registers
PWMxDCL
PWMxDCH
PWMxOUT
to other peripherals: CLC and CWG
Latched
(Not visible to user)
Output Enable (PWMxOE)
TRIS Control
R
Comparator
Q
0
PWMx
S
Q
1
TMR2 Module
TMR2
(1)
Output Polarity (PWMxPOL)
Comparator
PR2
Clear Timer,
PWMx pin and
latch Duty Cycle
Note 1: 8-bit timer is concatenated with the two Least Significant bits of 1/FOSC adjusted by the Timer2
prescaler to create a 10-bit time base.
For a step-by-step procedure on how to set up this
module for PWM operation, refer to Section 18.1.9
“Setup for PWM Operation using PWMx Pins”.
FIGURE 18-2:
PWM OUTPUT
Period
Pulse Width
TMR2 = PR2
TMR2 =
PWMxDCH:PWMxDCL
TMR2 = 0
DS40001585E-page 98
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
18.1
PWMx Pin Configuration
All PWM outputs are multiplexed with the PORT data
latch. The user must configure the pins as outputs by
clearing the associated TRIS bits.
Note:
18.1.1
Clearing the PWMxOE bit will relinquish
control of the PWMx pin.
FUNDAMENTAL OPERATION
The PWM module produces a 10-bit resolution output.
Timer2 and PR2 set the period of the PWM. The
PWMxDCL and PWMxDCH registers configure the
duty cycle. The period is common to all PWM modules,
whereas the duty cycle is independently controlled.
Note: The Timer2 postscaler is not used in the
determination of the PWM frequency. The
postscaler could be used to have a servo
update rate at a different frequency than the
PWM output.
All PWM outputs associated with Timer2 are set when
TMR2 is cleared. Each PWMx is cleared when TMR2
is equal to the value specified in the corresponding
PWMxDCH (8 MSb) and PWMxDCL (2 LSb)
registers. When the value is greater than or equal to
PR2, the PWM output is never cleared (100% duty
cycle).
Note: The PWMxDCH and PWMxDCL registers
are double buffered. The buffers are updated
when Timer2 matches PR2. Care must be
taken to update both registers before the
timer match occurs.
18.1.2
PWM OUTPUT POLARITY
The output polarity is inverted by setting the PWMxPOL
bit of the PWMxCON register.
18.1.3
PWM PERIOD
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the
formula of Equation 18-1.
EQUATION 18-1:
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The PWM output is active. (Exception: When the
PWM duty cycle = 0%, the PWM output will
remain inactive.)
• The PWMxDCH and PWMxDCL register values
are latched into the buffers.
Note:
18.1.4
The Timer2 postscaler has no effect on the
PWM operation.
PWM DUTY CYCLE
The PWM duty cycle is specified by writing a 10-bit value
to the PWMxDCH and PWMxDCL register pair. The
PWMxDCH register contains the eight MSbs and the
PWMxDCL, the two LSbs. The PWMxDCH and
PWMxDCL registers can be written to at any time.
Equation 18-2 is used to calculate the PWM pulse
width.
Equation 18-3 is used to calculate the PWM duty cycle
ratio.
EQUATION 18-2:
PULSE WIDTH
Pulse W idth = PW M xD C H :PW M xD CL
T O SC (TM R2 Prescale Value)
Note: TOSC = 1/FOSC
EQUATION 18-3:
DUTY CYCLE RATIO
PW M xD C H :PW M xD CL
D uty Cycle Ratio = ---------------------------------------------------------------------------------4 PR2 + 1
The 8-bit timer TMR2 register is concatenated with the
two Least Significant bits of 1/FOSC, adjusted by the
Timer2 prescaler to create the 10-bit time base. The
system clock is used if the Timer2 prescaler is set to 1:1.
PWM PERIOD
PW M Period = PR2 + 1 4 TO SC
(TM R2 Prescale Value)
Note:
TOSC = 1/FOSC
2011-2021 Microchip Technology Inc.
DS40001585E-page 99
PIC10(L)F320/322
18.1.5
PWM RESOLUTION
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit resolution
will result in 1024 discrete duty cycles, whereas an 8-bit
resolution will result in 256 discrete duty cycles.
The maximum PWM resolution is ten bits when PR2 is
255. The resolution is a function of the PR2 register
value as shown by Equation 18-4.
EQUATION 18-4:
PWM RESOLUTION
log 4 PR2 + 1
Resolution = ----------------------------------------- bits
log 2
Note:
If the pulse-width value is greater than the
period the assigned PWM pin(s) will
remain unchanged.
TABLE 18-1:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
PWM Frequency
0.31 kHz
Timer Prescale (1, 4, 64)
PR2 Value
78.12 kHz
156.3 kHz
208.3 kHz
64
4
1
1
1
1
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
8
7
6.6
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)
PWM Frequency
0.31 kHz
Timer Prescale (1, 4, 64)
PR2 Value
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz
200.0 kHz
64
4
1
1
1
1
0x65
0x65
0x65
0x19
0x0C
0x09
8
8
8
6
5
5
Maximum Resolution (bits)
18.1.6
19.53 kHz
0xFF
Maximum Resolution (bits)
TABLE 18-2:
4.88 kHz
OPERATION IN SLEEP MODE
In Sleep mode, the TMR2 register will not increment
and the state of the module will not change. If the
PWMx pin is driving a value, it will continue to drive that
value. When the device wakes up, TMR2 will continue
from its previous state.
18.1.7
CHANGES IN SYSTEM CLOCK
FREQUENCY
The PWM frequency is derived from the system clock
frequency (FOSC). Any changes in the system clock
frequency will result in changes to the PWM frequency.
Refer to Section 4.0 “Oscillator Module” for
additional details.
18.1.8
EFFECTS OF RESET
Any Reset will force all ports to Input mode and the
PWM registers to their Reset states.
DS40001585E-page 100
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
18.1.9
SETUP FOR PWM OPERATION
USING PWMx PINS
The following steps must be taken when configuring
the module for PWM operation using the PWMx pins:
1.
2.
3.
4.
5.
6.
7.
8.
Disable the PWMx pin output driver(s) by setting
the associated TRIS bit(s).
Clear the PWMxCON register.
Load the PR2 register with the PWM period value.
Clear the PWMxDCH register and bits of
the PWMxDCL register.
Configure and start Timer2:
• Clear the TMR2IF interrupt flag bit of the
PIR1 register. See Note below.
• Configure the T2CKPS bits of the T2CON
register with the Timer2 prescale value.
• Enable Timer2 by setting the TMR2ON bit of
the T2CON register.
Enable PWM output pin and wait until Timer2
overflows, TMR2IF bit of the PIR1 register is set.
See Note below.
Enable the PWMx pin output driver(s) by clearing the associated TRIS bit(s) and setting the
PWMxOE bit of the PWMxCON register.
Configure the PWM module by loading the
PWMxCON register with the appropriate values.
Note 1: To send a complete duty cycle and period
on the first PWM output, the above steps
must be followed in the order given. If it is
not critical to start with a complete PWM
signal, then move Step 8 to replace Step
4.
2: For operation with other peripherals only,
disable PWMx pin outputs.
2011-2021 Microchip Technology Inc.
DS40001585E-page 101
PIC10(L)F320/322
18.2
PWM Register Definitions
REGISTER 18-1:
PWMxCON: PWM CONTROL REGISTER
R/W-0/0
R/W-0/0
R-0/0
R/W-0/0
U-0
U-0
U-0
U-0
PWMxEN
PWMxOE
PWMxOUT
PWMxPOL
—
—
—
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
PWMxEN: PWM Module Enable bit
1 = PWM module is enabled
0 = PWM module is disabled
bit 6
PWMxOE: PWM Module Output Enable bit
1 = Output to PWMx pin is enabled
0 = Output to PWMx pin is disabled
bit 5
PWMxOUT: PWM Module Output Value bit
bit 4
PWMxPOL: PWMx Output Polarity Select bit
1 = PWM output is active-low.
0 = PWM output is active-high.
bit 3-0
Unimplemented: Read as ‘0’
DS40001585E-page 102
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
REGISTER 18-2:
R/W-x/u
PWMxDCH: PWM DUTY CYCLE HIGH BITS
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PWMxDCH
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
PWMxDCH: PWM Duty Cycle Most Significant bits
These bits are the MSbs of the PWM duty cycle. The two LSbs are found in the PWMxDCL Register.
REGISTER 18-3:
R/W-x/u
PWMxDCL: PWM DUTY CYCLE LOW BITS
R/W-x/u
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
PWMxDCL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-6
PWMxDCL: PWM Duty Cycle Least Significant bits
These bits are the LSbs of the PWM duty cycle. The MSbs are found in the PWMxDCH Register.
bit 5-0
Unimplemented: Read as ‘0’
TABLE 18-3:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PWM
Register
on Page
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ANSELA
—
—
—
—
—
ANSA2
ANSA1
ANSA0
70
LATA
—
—
—
—
—
LATA2
LATA1
LATA0
70
PORTA
—
—
—
—
RA3
RA2
RA1
RA0
69
PR2
PWM1CON
Timer2 module Period Register
PWM1EN
PWM1OE
PWM1OUT
PWM1DCH
PWM1DCL
PWM2CON
T2CON
PWM1DCL
PWM2EN
PWM2OE
—
—
—
103
—
—
—
—
—
—
103
PWM2POL
—
—
—
—
102
—
—
—
103
T2CKPS
97
PWM2DCH
PWM2DCL
—
—
—
—
TOUTPS
103
TMR2ON
Timer2 module Register
—
—
102
PWM2OUT
TMR2
TRISA
—
PWM1DCH
PWM2DCH
PWM2DCL
PWM1POL
96
—
—
—
96
TRISA2
TRISA1
TRISA0
69
Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the PWM.
2011-2021 Microchip Technology Inc.
DS40001585E-page 103
PIC10(L)F320/322
19.0
CONFIGURABLE LOGIC CELL
(CLC)
The Configurable Logic Cell (CLCx) provides programmable logic that operates outside the speed limitations
of software execution. The logic cell selects any combination of the eight input signals and through the use of
configurable gates reduces the selected inputs to four
logic lines that drive one of eight selectable single-output logic functions.
Input sources are a combination of the following:
•
•
•
•
Two I/O pins
Internal clocks
Peripherals
Register bits
The output can be directed internally to peripherals and
to an output pin.
FIGURE 19-1:
Refer to Figure 19-1 for a simplified diagram showing
signal flow through the CLCx.
Possible configurations include:
• Combinatorial Logic
- AND
- NAND
- AND-OR
- AND-OR-INVERT
- OR-XOR
- OR-XNOR
• Latches
- S-R
- Clocked D with Set and Reset
- Transparent D with Set and Reset
- Clocked J-K with Reset
CLCx SIMPLIFIED BLOCK DIAGRAM
D
CLCxIN[0]
Q1
CLCxIN[1]
CLCxIN[3]
CLCxIN[4]
CLCxIN[5]
CLCxIN[6]
CLCxIN[7]
See Figure 19-3
Input Data Selection Gates
CLCxIN[2]
LCxOUT
LE
LCxOE
LCxEN
lcxg1
Q
TRIS Control
lcxg2
Logic
lcxg3
Function
lcxq
lcx_out
CLCx
lcxg4
LCxPOL
LCxMODE
Interrupt
det
LCxINTP
LCxINTN
See Figure 19-2
sets
CLCxIF
flag
Interrupt
det
DS40001585E-page 104
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
19.1
CLCx Setup
19.1.2
Programming the CLCx module is performed by
configuring the four stages in the logic signal flow. The
four stages are:
•
•
•
•
Data selection
Data gating
Logic function selection
Output polarity
19.1.1
DATA SELECTION
There are eight signals available as inputs to the
configurable logic. Four 8-input multiplexers are used
to select the inputs to pass on to the next stage.
Data inputs are selected with the CLCxSEL0 and
CLCxSEL1 registers (Register 19-3 and Register 19-4,
respectively).
Data selection is through four multiplexers as indicated
on the left side of Figure 19-2. Data inputs in the figure
are identified by a generic numbered input name.
Table 19-1 correlates the generic input name to the
actual signal for each CLC module. The columns
labeled lcxd1 through lcxd4 indicate the MUX output for
the selected data input. D1S through D4S are
abbreviations for the MUX select input codes:
LCxD1S through LCxD4S, respectively.
Selecting a data input in a column excludes all other
inputs in that column.
Note:
Outputs from the input multiplexers are directed to the
desired logic function input through the data gating
stage. Each data gate can direct any combination of the
four selected inputs.
Note:
Each stage is setup at run time by writing to the corresponding CLCx Special Function Registers. This has
the added advantage of permitting logic reconfiguration
on-the-fly during program execution.
CLCx DATA INPUT
SELECTION
Data Input
lcxd1
D1S
lcxd2
D2S
lcxd3
D3S
lcxd4
D4S
CLCxIN[0]
000
000
000
000
CLCx
CLCxIN[1]
001
001
001
001
CLCxIN1
CLCxIN[2]
010
010
010
010
CLCxIN2
CLCxIN[3]
011
011
011
011
PWM1
CLCxIN[4]
100
100
100
100
PWM2
CLCxIN[5]
101
101
101
101
NCOx
CLCxIN[6]
110
110
110
110
FOSC
CLCxIN[7]
111
111
111
111
LFINTOSC
CLC 1
Data gating is undefined at power-up.
The gate stage is more than just signal direction. The gate
can be configured to direct each input signal as inverted
or noninverted data. Directed signals are ANDed together
in each gate. The output of each gate can be inverted
before going on to the logic function stage.
The gating is in essence a 1-to-4 input AND/NAND/OR/
NOR gate. When every input is inverted and the output
is inverted, the gate is an OR of all enabled data inputs.
When the inputs and output are not inverted, the gate
is an AND or all enabled inputs.
Table 19-2 summarizes the basic logic that can be
obtained in gate 1 by using the gate logic select bits.
The table shows the logic of four input variables, but
each gate can be configured to use less than four. If no
inputs are selected, the output will be zero or one,
depending on the gate output polarity bit.
TABLE 19-2:
Data selections are undefined at power-up.
TABLE 19-1:
DATA GATING
DATA GATING LOGIC
CLCxGLS0
LCxGyPOL
Gate Logic
0x55
1
AND
0x55
0
NAND
0xAA
1
NOR
0xAA
0
OR
0x00
0
Logic 0
0x00
1
Logic 1
It is possible (but not recommended) to select both the
true and negated values of an input. When this is done,
the gate output is zero, regardless of the other inputs,
but may emit logic glitches (transient-induced pulses). If
the output of the channel must be zero or one, the
recommended method is to set all gate bits to zero and
use the gate polarity bit to set the desired level.
Data gating is configured with the logic gate select
registers as follows:
•
•
•
•
Gate 1: CLCxGLS0 (Register 19-5)
Gate 2: CLCxGLS1 (Register 19-6)
Gate 3: CLCxGLS2 (Register 19-7)
Gate 4: CLCxGLS3 (Register 19-8)
Register number suffixes are different than the gate
numbers because other variations of this module have
multiple gate selections in the same register.
Data gating is indicated in the right side of Figure 19-2.
Only one gate is shown in detail. The remaining three
gates are configured identically with the exception that
the data enables correspond to the enables for that gate.
2011-2021 Microchip Technology Inc.
DS40001585E-page 105
PIC10(L)F320/322
19.1.3
LOGIC FUNCTION
There are eight available logic functions including:
•
•
•
•
•
•
•
•
AND-OR
OR-XOR
AND
S-R Latch
D Flip-Flop with Set and Reset
D Flip-Flop with Reset
J-K Flip-Flop with Reset
Transparent Latch with Set and Reset
Logic functions are shown in Figure 19-3. Each logic
function has four inputs and one output. The four inputs
are the four data gate outputs of the previous stage. The
output is fed to the inversion stage and from there to other
peripherals, an output pin, and back to the CLCx itself.
19.1.4
OUTPUT POLARITY
The last stage in the configurable logic cell is the output
polarity. Setting the LCxPOL bit of the CLCxCON register inverts the output signal from the logic stage.
Changing the polarity while the interrupts are enabled
will cause an interrupt for the resulting output transition.
DS40001585E-page 106
19.1.5
CLCX SETUP STEPS
The following steps must be followed when setting up
the CLCx:
• Disable CLCx by clearing the LCxEN bit.
• Select desired inputs using CLCxSEL0 and
CLCxSEL1 registers (See Table 19-1).
• Clear any associated ANSEL bits.
• Set all TRIS bits associated with inputs.
• Clear all TRIS bits associated with outputs.
• Enable the chosen inputs through the four gates
using CLCxGLS0, CLCxGLS1, CLCxGLS2, and
CLCxGLS3 registers.
• Select the gate output polarities with the
LCxPOLy bits of the CLCxPOL register.
• Select the desired logic function with the
LCxMODE bits of the CLCxCON register.
• Select the desired polarity of the logic output with
the LCxPOL bit of the CLCxPOL register. (This
step may be combined with the previous gate
output polarity step).
• If driving the CLCx pin, set the LCxOE bit of the
CLCxCON register and also clear the TRIS bit
corresponding to that output.
• If interrupts are desired, configure the following
bits:
- Set the LCxINTP bit in the CLCxCON register
for rising event.
- Set the LCxINTN bit in the CLCxCON
register or falling event.
- Set the CLCxIE bit of the associated PIE
registers.
- Set the GIE and PEIE bits of the INTCON
register.
• Enable the CLCx by setting the LCxEN bit of the
CLCxCON register.
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
19.2
CLCx Interrupts
An interrupt will be generated upon a change in the
output value of the CLCx when the appropriate interrupt
enables are set. A rising edge detector and a falling
edge detector are present in each CLC for this purpose.
The CLCxIF bit of the associated PIR registers will be
set when either edge detector is triggered and its associated enable bit is set. The LCxINTP enables rising
edge interrupts and the LCxINTN bit enables falling
edge interrupts. Both are located in the CLCxCON
register.
To fully enable the interrupt, set the following bits:
• LCxON bit of the CLCxCON register
• CLCxIE bit of the associated PIE registers
• LCxINTP bit of the CLCxCON register (for a rising
edge detection)
• LCxINTN bit of the CLCxCON register (for a falling
edge detection)
• PEIE and GIE bits of the INTCON register
The CLCxIF bit of the associated PIR registers must be
cleared in software as part of the interrupt service. If
another edge is detected while this flag is being
cleared, the flag will still be set at the end of the
sequence.
19.3
Effects of a Reset
The CLCxCON register is cleared to zero as the result
of a Reset. All other selection and gating values remain
unchanged.
19.4
Operation During Sleep
The selection, gating, and logic functions are not
affected by Sleep. Operation will continue provided that
the source signals are also not affected by Sleep.
2011-2021 Microchip Technology Inc.
DS40001585E-page 107
PIC10(L)F320/322
FIGURE 19-2:
CLCxIN[0]
CLCxIN[1]
CLCxIN[2]
CLCxIN[3]
CLCxIN[4]
CLCxIN[5]
CLCxIN[6]
CLCxIN[7]
INPUT DATA SELECTION AND GATING
000
Data Selection
Data GATE 1
lcxd1T
LCxD1G1T
lcxd1N
LCxD1G1N
111
LCxD2G1T
LCxD1S
LCxD2G1N
CLCxIN[0]
CLCxIN[1]
CLCxIN[2]
CLCxIN[3]
CLCxIN[4]
CLCxIN[5]
CLCxIN[6]
CLCxIN[7]
LCxD3G1T
lcxd2T
LCxD3G1N
LCxD4G1T
111
LCxD4G1N
000
Data GATE 2
lcxg2
lcxd3T
(Same as Data GATE 1)
lcxd3N
Data GATE 3
111
lcxg3
LCxD3S
CLCxIN[0]
CLCxIN[1]
CLCxIN[2]
CLCxIN[3]
CLCxIN[4]
CLCxIN[5]
CLCxIN[6]
CLCxIN[7]
LCxG1POL
lcxd2N
LCxD2S
CLCxIN[0]
CLCxIN[1]
CLCxIN[2]
CLCxIN[3]
CLCxIN[4]
CLCxIN[5]
CLCxIN[6]
CLCxIN[7]
lcxg1
000
(Same as Data GATE 1)
Data GATE 4
000
lcxg4
lcxd4T
(Same as Data GATE 1)
lcxd4N
111
LCxD4S
Note:
DS40001585E-page 108
All controls are undefined at power-up.
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
FIGURE 19-3:
PROGRAMMABLE LOGIC FUNCTIONS
AND - OR
OR - XOR
lcxg1
lcxg1
lcxg2
lcxq
lcxg3
lcxg4
lcxg2
lcxq
lcxg3
lcxg4
LCxMODE= 000
LCxMODE= 001
4-Input AND
S-R Latch
lcxg1
lcxg1
lcxg2
lcxg2
lcxq
lcxg3
S
lcxg3
lcxg4
R
lcxg4
LCxMODE= 010
lcxq
Q
LCxMODE= 011
1-Input D Flip-Flop with S and R
2-Input D Flip-Flop with R
lcxg4
lcxg2
D
S
lcxg4
Q
lcxq
D
lcxg2
lcxg1
lcxg1
Q
lcxq
R
R
lcxg3
lcxg3
LCxMODE= 100
LCxMODE= 101
J-K Flip-Flop with R
1-Input Transparent Latch with S and R
lcxg4
lcxg2
J
Q
lcxg1
lcxg4
K
R
lcxq
lcxg2
D
lcxg1
LE
lcxg3
S
lcxq
Q
R
lcxg3
LCxMODE= 110
2011-2021 Microchip Technology Inc.
LCxMODE= 111
DS40001585E-page 109
PIC10(L)F320/322
19.5
CLC Control Registers
REGISTER 19-1:
CLCxCON: CONFIGURABLE LOGIC CELL CONTROL REGISTER
R/W-0/0
R/W-0/0
R-0/0
R/W-0/0
R/W-0/0
LCxEN
LCxOE
LCxOUT
LCxINTP
LCxINTN
R/W-0/0
R/W-0/0
R/W-0/0
LCxMODE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Reset
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
LCxEN: Configurable Logic Cell Enable bit
1 = Configurable Logic Cell is enabled and mixing input signals
0 = Configurable Logic Cell is disabled and has logic zero output
bit 6
LCxOE: Configurable Logic Cell Output Enable bit
1 = Configurable Logic Cell port pin output enabled
0 = Configurable Logic Cell port pin output disabled
bit 5
LCxOUT: Configurable Logic Cell Data Output bit
Read-only: logic cell output data, after LCxPOL; sampled from lcx_out wire.
bit 4
LCxINTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit
1 = CLCxIF will be set when a rising edge occurs on lcx_out
0 = CLCxIF will not be set
bit 3
LCxINTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit
1 = CLCxIF will be set when a falling edge occurs on lcx_out
0 = CLCxIF will not be set
bit 2-0
LCxMODE: Configurable Logic Cell Functional Mode bits
111 = Cell is 1-input transparent latch with S and R
110 = Cell is J-K Flip-Flop with R
101 = Cell is 2-input D Flip-Flop with R
100 = Cell is 1-input D Flip-Flop with S and R
011 = Cell is S-R latch
010 = Cell is 4-input AND
001 = Cell is OR-XOR
000 = Cell is AND-OR
DS40001585E-page 110
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
REGISTER 19-2:
CLCxPOL: SIGNAL POLARITY CONTROL REGISTER
R/W-x/u
U-0
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxPOL
—
—
—
LCxG4POL
LCxG3POL
LCxG2POL
LCxG1POL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Reset
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
LCxPOL: LCOUT Polarity Control bit
1 = The output of the logic cell is inverted
0 = The output of the logic cell is not inverted
bit 6-4
Unimplemented: Read as ‘0’
bit 3
LCxG4POL: Gate 4 Output Polarity Control bit
1 = The output of gate 4 is inverted when applied to the logic cell
0 = The output of gate 4 is not inverted
bit 2
LCxG3POL: Gate 3 Output Polarity Control bit
1 = The output of gate 3 is inverted when applied to the logic cell
0 = The output of gate 3 is not inverted
bit 1
LCxG2POL: Gate 2 Output Polarity Control bit
1 = The output of gate 2 is inverted when applied to the logic cell
0 = The output of gate 2 is not inverted
bit 0
LCxG1POL: Gate 1 Output Polarity Control bit
1 = The output of gate 1 is inverted when applied to the logic cell
0 = The output of gate 1 is not inverted
2011-2021 Microchip Technology Inc.
DS40001585E-page 111
PIC10(L)F320/322
REGISTER 19-3:
U-0
CLCxSEL0: MULTIPLEXER DATA 1 AND 2 SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
(1)
—
LCxD2S
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
(1)
LCxD1S
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-4
LCxD2S: Input Data 2 Selection Control bits(1)
111 = CLCxIN[7] is selected for lcxd2.
110 = CLCxIN[6] is selected for lcxd2.
101 = CLCxIN[5] is selected for lcxd2.
100 = CLCxIN[4] is selected for lcxd2.
011 = CLCxIN[3] is selected for lcxd2.
010 = CLCxIN[2] is selected for lcxd2.
001 = CLCxIN[1] is selected for lcxd2.
000 = CLCxIN[0] is selected for lcxd2.
bit 3
Unimplemented: Read as ‘0’
bit 2-0
LCxD1S: Input Data 1 Selection Control bits(1)
111 = CLCxIN[7] is selected for lcxd1.
110 = CLCxIN[6] is selected for lcxd1.
101 = CLCxIN[5] is selected for lcxd1.
100 = CLCxIN[4] is selected for lcxd1.
011 = CLCxIN[3] is selected for lcxd1.
010 = CLCxIN[2] is selected for lcxd1.
001 = CLCxIN[1] is selected for lcxd1.
000 = CLCxIN[0] is selected for lcxd1.
Note 1:
See Table 19-1 for signal names associated with inputs.
DS40001585E-page 112
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
REGISTER 19-4:
U-0
CLCxSEL1: MULTIPLEXER DATA 3 AND 4 SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
(1)
—
LCxD4S
U-0
—
R/W-x/u
R/W-x/u
R/W-x/u
(1)
LCxD3S
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
Unimplemented: Read as ‘0’
bit 6-4
LCxD4S: Input Data 4 Selection Control bits(1)
111 = CLCxIN[7] is selected for lcxd4.
110 = CLCxIN[6] is selected for lcxd4.
101 = CLCxIN[5] is selected for lcxd4
100 = CLCxIN[4] is selected for lcxd4.
011 = CLCxIN[3] is selected for lcxd4.
010 = CLCxIN[2] is selected for lcxd4.
001 = CLCxIN[1] is selected for lcxd4.
000 = CLCxIN[0] is selected for lcxd4.
bit 3
Unimplemented: Read as ‘0’
bit 2-0
LCxD3S: Input Data 3 Selection Control bits(1)
111 = CLCxIN[7] is selected for lcxd3.
110 = CLCxIN[6] is selected for lcxd3.
101 = CLCxIN[5] is selected for lcxd3.
100 = CLCxIN[4] is selected for lcxd3.
011 = CLCxIN[3] is selected for lcxd3.
010 = CLCxIN[2] is selected for lcxd3.
001 = CLCxIN[1] is selected for lcxd3.
000 = CLCxIN[0] is selected for lcxd3.
Note 1:
See Table 19-1 for signal names associated with inputs.
2011-2021 Microchip Technology Inc.
DS40001585E-page 113
PIC10(L)F320/322
REGISTER 19-5:
CLCxGLS0: GATE 1 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG1D4T
LCxG1D4N
LCxG1D3T
LCxG1D3N
LCxG1D2T
LCxG1D2N
LCxG1D1T
LCxG1D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
LCxG1D4T: Gate 1 Data 4 True (noninverted) bit
1 = lcxd4T is gated into lcxg1
0 = lcxd4T is not gated into lcxg1
bit 6
LCxG1D4N: Gate 1 Data 4 Negated (inverted) bit
1 = lcxd4N is gated into lcxg1
0 = lcxd4N is not gated into lcxg1
bit 5
LCxG1D3T: Gate 1 Data 3 True (noninverted) bit
1 = lcxd3T is gated into lcxg1
0 = lcxd3T is not gated into lcxg1
bit 4
LCxG1D3N: Gate 1 Data 3 Negated (inverted) bit
1 = lcxd3N is gated into lcxg1
0 = lcxd3N is not gated into lcxg1
bit 3
LCxG1D2T: Gate 1 Data 2 True (noninverted) bit
1 = lcxd2T is gated into lcxg1
0 = lcxd2T is not gated into lcxg1
bit 2
LCxG1D2N: Gate 1 Data 2 Negated (inverted) bit
1 = lcxd2N is gated into lcxg1
0 = lcxd2N is not gated into lcxg1
bit 1
LCxG1D1T: Gate 1 Data 1 True (noninverted) bit
1 = lcxd1T is gated into lcxg1
0 = lcxd1T is not gated into lcxg1
bit 0
LCxG1D1N: Gate 1 Data 1 Negated (inverted) bit
1 = lcxd1N is gated into lcxg1
0 = lcxd1N is not gated into lcxg1
DS40001585E-page 114
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
REGISTER 19-6:
CLCxGLS1: GATE 2 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG2D4T
LCxG2D4N
LCxG2D3T
LCxG2D3N
LCxG2D2T
LCxG2D2N
LCxG2D1T
LCxG2D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
LCxG2D4T: Gate 2 Data 4 True (noninverted) bit
1 = lcxd4T is gated into lcxg2
0 = lcxd4T is not gated into lcxg2
bit 6
LCxG2D4N: Gate 2 Data 4 Negated (inverted) bit
1 = lcxd4N is gated into lcxg2
0 = lcxd4N is not gated into lcxg2
bit 5
LCxG2D3T: Gate 2 Data 3 True (noninverted) bit
1 = lcxd3T is gated into lcxg2
0 = lcxd3T is not gated into lcxg2
bit 4
LCxG2D3N: Gate 2 Data 3 Negated (inverted) bit
1 = lcxd3N is gated into lcxg2
0 = lcxd3N is not gated into lcxg2
bit 3
LCxG2D2T: Gate 2 Data 2 True (noninverted) bit
1 = lcxd2T is gated into lcxg2
0 = lcxd2T is not gated into lcxg2
bit 2
LCxG2D2N: Gate 2 Data 2 Negated (inverted) bit
1 = lcxd2N is gated into lcxg2
0 = lcxd2N is not gated into lcxg2
bit 1
LCxG2D1T: Gate 2 Data 1 True (noninverted) bit
1 = lcxd1T is gated into lcxg2
0 = lcxd1T is not gated into lcxg2
bit 0
LCxG2D1N: Gate 2 Data 1 Negated (inverted) bit
1 = lcxd1N is gated into lcxg2
0 = lcxd1N is not gated into lcxg2
2011-2021 Microchip Technology Inc.
DS40001585E-page 115
PIC10(L)F320/322
REGISTER 19-7:
CLCxGLS2: GATE 3 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG3D4T
LCxG3D4N
LCxG3D3T
LCxG3D3N
LCxG3D2T
LCxG3D2N
LCxG3D1T
LCxG3D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
LCxG3D4T: Gate 3 Data 4 True (noninverted) bit
1 = lcxd4T is gated into lcxg3
0 = lcxd4T is not gated into lcxg3
bit 6
LCxG3D4N: Gate 3 Data 4 Negated (inverted) bit
1 = lcxd4N is gated into lcxg3
0 = lcxd4N is not gated into lcxg3
bit 5
LCxG3D3T: Gate 3 Data 3 True (noninverted) bit
1 = lcxd3T is gated into lcxg3
0 = lcxd3T is not gated into lcxg3
bit 4
LCxG3D3N: Gate 3 Data 3 Negated (inverted) bit
1 = lcxd3N is gated into lcxg3
0 = lcxd3N is not gated into lcxg3
bit 3
LCxG3D2T: Gate 3 Data 2 True (noninverted) bit
1 = lcxd2T is gated into lcxg3
0 = lcxd2T is not gated into lcxg3
bit 2
LCxG3D2N: Gate 3 Data 2 Negated (inverted) bit
1 = lcxd2N is gated into lcxg3
0 = lcxd2N is not gated into lcxg3
bit 1
LCxG3D1T: Gate 3 Data 1 True (noninverted) bit
1 = lcxd1T is gated into lcxg3
0 = lcxd1T is not gated into lcxg3
bit 0
LCxG3D1N: Gate 3 Data 1 Negated (inverted) bit
1 = lcxd1N is gated into lcxg3
0 = lcxd1N is not gated into lcxg3
DS40001585E-page 116
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
REGISTER 19-8:
CLCxGLS3: GATE 4 LOGIC SELECT REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
LCxG4D4T
LCxG4D4N
LCxG4D3T
LCxG4D3N
LCxG4D2T
LCxG4D2N
LCxG4D1T
LCxG4D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
LCxG4D4T: Gate 4 Data 4 True (noninverted) bit
1 = lcxd4T is gated into lcxg4
0 = lcxd4T is not gated into lcxg4
bit 6
LCxG4D4N: Gate 4 Data 4 Negated (inverted) bit
1 = lcxd4N is gated into lcxg4
0 = lcxd4N is not gated into lcxg4
bit 5
LCxG4D3T: Gate 4 Data 3 True (noninverted) bit
1 = lcxd3T is gated into lcxg4
0 = lcxd3T is not gated into lcxg4
bit 4
LCxG4D3N: Gate 4 Data 3 Negated (inverted) bit
1 = lcxd3N is gated into lcxg4
0 = lcxd3N is not gated into lcxg4
bit 3
LCxG4D2T: Gate 4 Data 2 True (noninverted) bit
1 = lcxd2T is gated into lcxg4
0 = lcxd2T is not gated into lcxg4
bit 2
LCxG4D2N: Gate 4 Data 2 Negated (inverted) bit
1 = lcxd2N is gated into lcxg4
0 = lcxd2N is not gated into lcxg4
bit 1
LCxG4D1T: Gate 4 Data 1 True (noninverted) bit
1 = lcxd1T is gated into lcxg4
0 = lcxd1T is not gated into lcxg4
bit 0
LCxG4D1N: Gate 4 Data 1 Negated (inverted) bit
1 = lcxd1N is gated into lcxg4
0 = lcxd1N is not gated into lcxg4
2011-2021 Microchip Technology Inc.
DS40001585E-page 117
PIC10(L)F320/322
TABLE 19-3:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH CLCx
Bit7
Bit6
Bit5
Bit4
BIt3
Bit2
Bit1
Bit0
LC1MODE
Register
on Page
CLC1CON
LC1EN
LC1OE
LC1OUT
LC1INTP
LC1INTN
CLC1GLS0
LC1G1D4T
LC1G1D4N
LC1G1D3T
LC1G1D3N
LC1G1D2T
LC1G1D2N
LC1G1D1T
LC1G1D1N
110
114
CLC1GLS1
LC1G2D4T
LC1G2D4N
LC1G2D3T
LC1G2D3N
LC1G2D2T
LC1G2D2N
LC1G2D1T
LC1G2D1N
115
CLC1GLS2
LC1G3D4T
LC1G3D4N
LC1G3D3T
LC1G3D3N
LC1G3D2T
LC1G3D2N
LC1G3D1T
LC1G3D1N
116
CLC1GLS3
LC1G4D4T
LC1G4D4N
LC1G4D3T
LC1G4D3N
LC1G4D2T
LC1G4D2N
LC1G4D1T
LC1G4D1N
117
CLC1POL
LC1POL
—
—
—
LC1G4POL
LC1G3POL
LC1G2POL
LC1G1POL
111
CLC1SEL0
—
LC1D2S
—
LC1D1S
112
CLC1SEL1
—
LC1D4S
—
LC1D3S
113
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
40
PIE1
—
ADIE
—
NCO1IE
CLC1IE
—
TMR2IE
—
41
PIR1
—
ADIF
—
NCO1IF
CLC1IF
—
TMR2IF
—
42
TRISA
—
—
—
—
—
TRISA2
TRISA1
TRISA0
69
Legend:
— = unimplemented read as ‘0’. Shaded cells are not used for CLC module.
DS40001585E-page 118
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
20.0
NUMERICALLY CONTROLLED
OSCILLATOR (NCO) MODULE
The Numerically Controlled Oscillator (NCOx) module
is a timer that uses the overflow from the addition of an
increment value to divide the input frequency. The
advantage of the addition method over simple counter
driven timer is that the resolution of division does not
vary with the divider value. The NCOx is most useful for
applications that requires frequency accuracy and fine
resolution at a fixed duty cycle.
Features of the NCOx include:
•
•
•
•
•
•
•
16-bit increment function
Fixed Duty Cycle (FDC) mode
Pulse Frequency (PF) mode
Output pulse width control
Multiple clock input sources
Output polarity control
Interrupt capability
Figure 20-1 is a simplified block diagram of the NCOx
module.
2011-2021 Microchip Technology Inc.
DS40001585E-page 119
NUMERICALLY CONTROLLED OSCILLATOR (NCOx) MODULE SIMPLIFIED BLOCK DIAGRAM
NCOxINCH NCOxINCL
Rev. 10-000028A
7/30/2013
16
(1)
INCBUFH
INCBUFL
16
NCO_overflow
HFINTOSC
00
FOSC
01
LCx_out
10
20
Adder
20
NCOx_clk
NCOxACCU NCOxACCH NCOxACCL
20
11
NCO1CLK
NxCKS
NCO_interrupt
set bit
NCOxIF
2
Fixed Duty
Cycle Mode
Circuitry
D
Q
D
Q
0
_
1
Q
NxPFM
NxOE
TRIS bit
NCOx
NxPOL
NCOx_out
2011-2021 Microchip Technology Inc.
EN
S
Q
Ripple
Counter
R
Q
R
3
NxPWS
Note 1:
D
_
Pulse
Frequency
Mode Circuitry
Q
To Peripherals
NxOUT
Q1
The increment registers are double-buffered to allow for value changes to be made without first disabling the NCO module. The full increment value is loaded into the buffer registers on the
second rising edge of the NCOx_clk signal that occurs immediately after a write to NCOxINCL register. The buffers are not user-accessible and are shown here for reference.
PIC10(L)F320/322
DS40001585E-page 120
FIGURE 20-1:
PIC10(L)F320/322
20.1
NCOx OPERATION
20.1.3
ADDER
The NCOx operates by repeatedly adding a fixed value
to an accumulator. Additions occur at the input clock
rate. The accumulator will overflow with a carry
periodically, which is the raw NCOx output. This
effectively reduces the input clock by the ratio of the
addition value to the maximum accumulator value. See
Equation 20-1.
The NCOx Adder is a full adder, which operates
asynchronously to the clock source selected. The
addition of the previous result and the increment value
replaces the accumulator value on the rising edge of
each input clock.
The NCOx output can be further modified by stretching
the pulse or toggling a flip-flop. The modified NCOx
output is then distributed internally to other peripherals
and optionally output to a pin. The accumulator overflow
also generates an interrupt.
The Increment value is stored in two 8-bit registers
making up a 16-bit increment. In order of LSB to MSB
they are:
The NCOx output creates an instantaneous frequency,
which may cause uncertainty. This output depends on
the ability of the receiving circuit (i.e., CWG or external
resonant converter circuitry) to average the
instantaneous frequency to reduce uncertainty.
Both of the registers are readable and writable. The
Increment registers are double-buffered to allow for
value changes to be made without first disabling the
NCOx module.
20.1.1
NCOx CLOCK SOURCES
Clock sources available to the NCOx include:
•
•
•
•
HFINTOSC
FOSC
LC1OUT
NCO1CLK pin
20.1.4
INCREMENT REGISTERS
• NCOxINCL
• NCOxINCH
The buffer loads are immediate when the module is
disabled. Writing to the MS register first is necessary
because then the buffer is loaded synchronously with
the NCOx operation after the write is executed on the
lower increment register.
Note: The increment buffer registers are not useraccessible.
The NCOx clock source is selected by configuring the
NxCKS bits in the NCOxCLK register.
20.1.2
ACCUMULATOR
The Accumulator is a 20-bit register. Read and write
access to the Accumulator is available through three
registers:
• NCOxACCL
• NCOxACCH
• NCOxACCU
EQUATION 20-1:
N C O C lock Frequency Increm ent Value
F O VERFLO W = ---------------------------------------------------------n-----------------------------------------------------2
n = Accumulator width in bits
2011-2021 Microchip Technology Inc.
DS40001585E-page 121
PIC10(L)F320/322
20.2
FIXED DUTY CYCLE (FDC) MODE
In Fixed Duty Cycle (FDC) mode, every time the
Accumulator overflows, the output is toggled. This
provides a 50% duty cycle, provided that the increment
value remains constant. For more information, see
Figure 20-2.
The FDC mode is selected by clearing the NxPFM bit
in the NCOxCON register.
20.3
PULSE FREQUENCY (PF) MODE
In Pulse Frequency (PF) mode, every time the Accumulator overflows, the output becomes active for one
or more clock periods. See Section 20.3.1 “OUTPUT
PULSE WIDTH CONTROL” for more information.
Once the clock period expires, the output returns to an
Inactive state. This provides a pulsed output.
The output becomes active on the rising clock edge
immediately following the overflow event. For more
information, see Figure 20-2.
The value of the Active and Inactive states depends on
the Polarity bit, NxPOL in the NCOxCON register.
The PF mode is selected by setting the NxPFM bit in
the NCOxCON register.
20.3.1
OUTPUT PULSE WIDTH CONTROL
When operating in PF mode, the Active state of the output can vary in width by multiple clock periods. Various
pulse widths are selected with the NxPWS bits in
the NCOxCLK register.
When the selected pulse width is greater than the
Accumulator overflow time frame, then NCOx
operation is undefined.
20.4
OUTPUT POLARITY CONTROL
The last stage in the NCOx module is the output polarity. The NxPOL bit in the NCOxCON register selects the
output polarity. Changing the polarity while the interrupts are enabled will cause an interrupt for the resulting output transition.
The NCOx output can be used internally by source
code or other peripherals. This is done by reading the
NxOUT (read-only) bit of the NCOxCON register.
DS40001585E-page 122
2011-2021 Microchip Technology Inc.
2011-2021 Microchip Technology Inc.
FIGURE 20-2:
NCO – FIXED DUTY CYCLE (FDC) AND PULSE FREQUENCY MODE (PFM) OUTPUT OPERATION DIAGRAM
Rev. 10-000029A
11/7/2013
NCOx
Clock
Source
NCOx
Increment
Value
NCOx
Accumulator
Value
4000h
00000h 04000h 08000h
4000h
FC000h 00000h 04000h 08000h
4000h
FC000h 00000h 04000h 08000h
NCO_overflow
NCO_interrupt
DS40001585E-page 123
NCOx Output
PF Mode
NCOxPWS =
000
NCOx Output
PF Mode
NCOxPWS =
001
PIC10(L)F320/322
NCOx Output
FDC Mode
PIC10(L)F320/322
20.5
Interrupts
When the Accumulator overflows, the NCOx Interrupt
Flag bit, NCOxIF, of the PIR1 register is set. To enable
this interrupt event, the following bits must be set:
•
•
•
•
NxEN bit of the NCOxCON register
NCOxIE bit of the PIE1 register
PEIE bit of the INTCON register
GIE bit of the INTCON register
The interrupt must be cleared by software by clearing
the NCOxIF bit in the Interrupt Service Routine.
20.6
Effects of a Reset
All of the NCOx registers are cleared to zero as the
result of a Reset.
20.7
Operation In Sleep
The NCO module operates independently from the
system clock and will continue to run during Sleep,
provided that the clock source selected remains active.
The HFINTOSC remains active during Sleep when the
NCO module is enabled and the HFINTOSC is
selected as the clock source, regardless of the system
clock source selected.
In other words, if the HFINTOSC is simultaneously
selected as the system clock and the NCO clock
source, when the NCO is enabled, the CPU will go idle
during Sleep, but the NCO will continue to operate and
the HFINTOSC will remain active.
This will have a direct effect on the Sleep mode current.
DS40001585E-page 124
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
20.8
NCOx Control Registers
REGISTER 20-1:
NCOxCON: NCOx CONTROL REGISTER
R/W-0/0
R/W-0/0
R-0/0
R/W-0/0
U-0
U-0
U-0
R/W-0/0
NxEN
NxOE
NxOUT
NxPOL
—
—
—
NxPFM
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7
NxEN: NCOx Enable bit
1 = NCOx module is enabled
0 = NCOx module is disabled
bit 6
NxOE: NCOx Output Enable bit
1 = NCOx output pin is enabled
0 = NCOx output pin is disabled
bit 5
NxOUT: NCOx Output bit
1 = NCOx output is high
0 = NCOx output is low
bit 4
NxPOL: NCOx Polarity bit
1 = NCOx output signal is active-low (inverted)
0 = NCOx output signal is active-high (noninverted)
bit 3-1
Unimplemented: Read as ‘0’.
bit 0
NxPFM: NCOx Pulse Frequency mode bit
1 = NCOx operates in Pulse Frequency mode
0 = NCOx operates in Fixed Duty Cycle mode
REGISTER 20-2:
R/W-0/0
NCOxCLK: NCOx INPUT CLOCK CONTROL REGISTER
R/W-0/0
R/W-0/0
NxPWS(1,2)
U-0
U-0
U-0
—
—
—
R/W-0/0
R/W-0/0
NxCKS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-5
NxPWS: NCOx Output Pulse Width Select bits(1, 2)
111 = 128 NCOx clock periods
110 = 64 NCOx clock periods
101 = 32 NCOx clock periods
100 = 16 NCOx clock periods
011 = 8 NCOx clock periods
010 = 4 NCOx clock periods
001 = 2 NCOx clock periods
000 = 1 NCOx clock periods
bit 4-2
Unimplemented: Read as ‘0’
bit 1-0
NxCKS: NCOx Clock Source Select bits
11 = LC1OUT
10 = HFINTOSC (16 MHz)
01 = FOSC
00 = NCO1CLK pin
Note 1: NxPWS applies only when operating in Pulse Frequency mode.
2: If NCOx pulse width is greater than NCOx overflow period, operation is undefined.
2011-2021 Microchip Technology Inc.
DS40001585E-page 125
PIC10(L)F320/322
REGISTER 20-3:
R/W-0/0
NCOxACCL: NCOx ACCUMULATOR REGISTER – LOW BYTE
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NCOxACC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
NCOxACC: NCOx Accumulator, low byte
Note 1: NxPWS applies only when operating in Pulse Frequency mode.
2: If NCOx pulse width is greater than NCOx overflow period, operation is undefined.
REGISTER 20-4:
R/W-0/0
NCOxACCH: NCOx ACCUMULATOR REGISTER – HIGH BYTE
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NCOxACC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
NCOxACC: NCOx Accumulator, high byte
REGISTER 20-5:
NCOxACCU: NCOx ACCUMULATOR REGISTER – UPPER BYTE
U-0
U-0
U-0
U-0
—
—
—
—
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NCOxACC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-4
Unimplemented: Read as ‘0’
bit 3-0
NCOxACC: NCOx Accumulator, upper byte
DS40001585E-page 126
2011-2021 Microchip Technology Inc.
PIC10(L)F320/322
REGISTER 20-6:
R/W-0/0
NCOxINCL: NCOx INCREMENT REGISTER – LOW BYTE
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-1/1
NCOxINC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
NCOxINC: NCOx Increment, low byte
REGISTER 20-7:
R/W-0/0
NCOxINCH: NCOx INCREMENT REGISTER – HIGH BYTE
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
NCOxINC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
u = Bit is unchanged
x = Bit is unknown
-n/n = Value at POR and BOR/Value at all other Resets
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7-0
NCOxINC: NCOx Increment, high byte
2011-2021 Microchip Technology Inc.
DS40001585E-page 127
PIC10(L)F320/322
TABLE 20-1:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH NCOx
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
LC1D2S1
LC1D2S0
—
LC1D1S2
LC1D1S1
LC1D1S0
112
LC1D4S1
LC1D4S0
—
LC1D3S2
LC1D3S1
LC1D3S0
113
Bit 7
Bit 6
Bit 5
CLC1SEL0
—
LC1D2S2
CLC1SEL1
—
LC1D4S2
CWG1CON1
G1ASDLB
INTCON
GIE
G1ASDLA
PEIE
TMR0IE
INTE
—
—
IOCIE
TMR0IF
G1IS
INTF
IOCIF
140
40
NCO1ACCH
NCO1ACCH
126
NCO1ACCL
NCO1ACCL
126
NCO1ACCU
—
NCO1CLK
NCO1CON
NCO1ACCU
工商网监
湘ICP备2023018690号
