PIC16CE62X
OTP 8-Bit CMOS MCU with EEPROM Data Memory
Devices included in this data sheet:
Pin Diagrams
• PIC16CE623
• PIC16CE624
• PIC16CE625
PDIP, SOIC, Windowed CERDIP
Device
Program
Memory
RAM
Data
Memory
EEPROM
Data
Memory
PIC16CE623
512x14
96x8
128x8
PIC16CE624
1Kx14
96x8
128x8
PIC16CE625
2Kx14
128x8
128x8
•
•
•
•
Interrupt capability
16 special function hardware registers
8-level deep hardware stack
Direct, Indirect and Relative addressing modes
•1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
RA1/AN1
RA0/AN0
OSC1/CLKIN
OSC2/CLKOUT
VDD
RB7
RB6
RB5
RB4
PIC16CE62X
• Only 35 instructions to learn
• All single-cycle instructions (200 ns), except for
program branches which are two-cycle
• Operating speed:
- DC - 20 MHz clock input
- DC - 200 ns instruction cycle
RA2/AN2/VREF
RA3/AN3
RA4/T0CKI
MCLR/VPP
VSS
RB0/INT
RB1
RB2
RB3
PIC16CE62X
High Performance RISC CPU:
20
19
18
17
16
15
14
13
12
11
RA1/AN1
RA0/AN0
OSC1/CLKIN
OSC2/CLKOUT
VDD
VDD
RB7
RB6
RB5
RB4
SSOP
RA2/AN2/VREF
RA3/AN3
RA4/T0CKI
MCLR/VPP
VSS
VSS
RB0/INT
RB1
RB2
RB3
•1
2
3
4
5
6
7
8
9
10
Peripheral Features:
Special Microcontroller Features (cont’d)
• 13 I/O pins with individual direction control
• High current sink/source for direct LED drive
• Analog comparator module with:
- Two analog comparators
- Programmable on-chip voltage reference
(VREF) module
- Programmable input multiplexing from device
inputs and internal voltage reference
- Comparator outputs can be output signals
• Timer0: 8-bit timer/counter with 8-bit
programmable prescaler
• 1,000,000 erase/write cycle EEPROM data
memory
• EEPROM data retention > 40 years
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options
• Four user programmable ID locations
Special Microcontroller Features:
• In-Circuit Serial Programming (ICSP™) (via two
pins)
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Brown-out Reset
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
1998-2013 Microchip Technology Inc.
CMOS Technology:
• Low-power, high-speed CMOS EPROM/EEPROM
technology
• Fully static design
• Wide operating voltage range
- 2.5V to 5.5V
• Commercial, industrial and extended temperature
range
• Low power consumption
- < 2.0 mA @ 5.0V, 4.0 MHz
- 15 A typical @ 3.0V, 32 kHz
- < 1.0 A typical standby current @ 3.0V
DS40182D-page 1
PIC16CE62X
Table of Contents
1.0 General Description ............................................................................................................................................... 3
2.0 PIC16CE62X Device Varieties .............................................................................................................................. 5
3.0 Architectural Overview........................................................................................................................................... 7
4.0 Memory Organization .......................................................................................................................................... 11
5.0 I/O Ports............................................................................................................................................................... 23
6.0 EEPROM Peripheral Operation ........................................................................................................................... 29
7.0 Timer0 Module..................................................................................................................................................... 35
8.0 Comparator Module ............................................................................................................................................. 41
9.0 Voltage Reference Module .................................................................................................................................. 47
10.0 Special Features of the CPU ............................................................................................................................... 49
11.0 Instruction Set Summary ..................................................................................................................................... 65
12.0 Development Support .......................................................................................................................................... 77
13.0 Electrical Specifications ....................................................................................................................................... 83
14.0 Packaging Information ......................................................................................................................................... 97
Appendix A: Code for Accessing EEPROM Data Memory ........................................................................................ 103
Index .......................................................................................................................................................................... 105
On Line Support .......................................................................................................................................................... 107
Reader Response ....................................................................................................................................................... 108
PIC16CE62X Product Identification System .............................................................................................................. 109
To Our Valued Customers
Most Current Data Sheet
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
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Errata
An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended
workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
Corrections to this Data Sheet
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure
that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing
or appears in error, please:
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We appreciate your assistance in making this a better document.
DS40182D-page 2
1998-2013 Microchip Technology Inc.
PIC16CE62X
1.0
GENERAL DESCRIPTION
The PIC16CE62X are 18 and 20-Pin EPROM-based
members of the versatile PIC® family of low-cost,
high-performance,
CMOS,
fully-static,
8-bit
microcontrollers with EEPROM data memory.
All PIC® microcontrollers employ an advanced RISC
architecture. The PIC16CE62X family has enhanced
core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate
instruction and data buses of the Harvard architecture
allow a 14-bit wide instruction word with separate 8-bit
wide data. The two-stage instruction pipeline allows all
instructions to execute in a single-cycle, except for program branches (which require two cycles). A total of 35
instructions (reduced instruction set) are available.
Additionally, a large register set gives some of the
architectural innovations used to achieve a very high
performance.
PIC16CE62X microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
The PIC16CE623 and PIC16CE624 have 96 bytes of
RAM. The PIC16CE625 has 128 bytes of RAM. Each
microcontroller contains a 128x8 EEPROM memory
array for storing non-volatile information, such as calibration data or security codes. This memory has an
endurance of 1,000,000 erase/write cycles and a retention of 40 plus years.
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software
lock- up.
A UV-erasable CERDIP-packaged version is ideal for
code development, while the cost-effective One-Time
Programmable (OTP) version is suitable for production
in any volume.
Table 1-1 shows the features of the PIC16CE62X
mid-range microcontroller families.
A simplified block diagram of the PIC16CE62X is
shown in Figure 3-1.
The PIC16CE62X series fits perfectly in applications
ranging from multi-pocket battery chargers to
low-power remote sensors. The EPROM technology
makes customization of application programs (detection levels, pulse generation, timers, etc.) extremely
fast and convenient. The small footprint packages
make this microcontroller series perfect for all applications with space limitations. Low-cost, low-power,
high-performance, ease of use and I/O flexibility make
the PIC16CE62X very versatile.
1.1
Development Support
The PIC16CE62X family is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a low-cost development programmer and a
full-featured programmer. A “C” compiler is also
available.
Each device has 13 I/O pins and an 8-bit timer/counter
with an 8-bit programmable prescaler. In addition, the
PIC16CE62X adds two analog comparators with a
programmable on-chip voltage reference module. The
comparator module is ideally suited for applications
requiring a low-cost analog interface (e.g., battery
chargers,
threshold
detectors,
white
goods
controllers, etc).
PIC16CE62X devices have special features to reduce
external components, thus reducing system cost,
enhancing system reliability and reducing power consumption. There are four oscillator options, of which the
single pin RC oscillator provides a low-cost solution,
the LP oscillator minimizes power consumption, XT is a
standard crystal, and the HS is for High Speed crystals.
The SLEEP (power-down) mode offers power savings.
The user can wake-up the chip from SLEEP through
several external and internal interrupts and reset.
1998-2013 Microchip Technology Inc.
DS40182D-page 3
PIC16CE62X
TABLE 1-1:
PIC16CE62X FAMILY OF DEVICES
PIC16CE623
Clock
Memory
Peripherals
Features
PIC16CE624
PIC16CE625
Maximum Frequency of Operation (MHz)
20
20
EPROM Program Memory (x14 words)
512
1K
20
2K
Data Memory (bytes)
96
96
128
EEPROM Data Memory (bytes)
128
128
128
Timer Module(s)
TMR0
TMR0
TMR0
Comparators(s)
2
2
2
Internal Reference Voltage
Yes
Yes
Yes
Interrupt Sources
4
4
4
I/O Pins
13
13
13
Voltage Range (Volts)
2.5-5.5
2.5-5.5
2.5-5.5
Brown-out Reset
Yes
Yes
Yes
Packages
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
All PIC® Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.
All PIC16CE62X Family devices use serial programming with clock pin RB6 and data pin RB7.
DS40182D-page 4
1998-2013 Microchip Technology Inc.
PIC16CE62X
2.0
PIC16CE62X DEVICE
VARIETIES
A variety of frequency ranges and packaging options are
available. Depending on application and production
requirements the proper device option can be selected
using the information in the PIC16CE62X Product
Identification System section at the end of this data
sheet. When placing orders, please use this page of the
data sheet to specify the correct part number.
2.1
UV Erasable Devices
The UV erasable version, offered in the CERDIP package is optimal for prototype development and pilot
programs. This version can be erased and
reprogrammed to any of the oscillator modes.
and
PRO MATE
Microchip's
PICSTART
programmers both support programming of the
PIC16CE62X.
2.2
One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications. In addition to
the program memory, the configuration bits must also
be programmed.
1998-2013 Microchip Technology Inc.
2.3
Quick-Turn-Programming (QTP)
Devices
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who chose not to program a medium
to high quantity of units and whose code patterns have
stabilized. The devices are identical to the OTP devices
but with all EPROM locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before
production shipments are available. Please contact
your Microchip Technology sales office for more details.
2.4
Serialized Quick-Turn-Programming
(SQTPSM) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password or ID number.
DS40182D-page 5
PIC16CE62X
NOTES:
DS40182D-page 6
1998-2013 Microchip Technology Inc.
PIC16CE62X
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16CE62X family can
be attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16CE62X uses a Harvard architecture in
which program and data are accessed from separate
memories using separate buses. This improves
bandwidth over traditional von Neumann architecture
where program and data are fetched from the same
memory. Separating program and data memory further
allows instructions to be sized differently than 8-bit wide
data word. Instruction opcodes are 14-bits wide making
it possible to have all single word instructions. A 14-bit
wide program memory access bus fetches a 14-bit
instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently,
all instructions (35) execute in a single-cycle (200 ns @
20 MHz) except for program branches.
The table below lists program memory (EPROM), data
memory (RAM) and non-volatile memory (EEPROM)
for each PIC16CE62X device.
Device
PIC16CE623
Program
Memory
RAM
Data
Memory
EEPROM
Data
Memory
512x14
96x8
128x8
PIC16CE624
1Kx14
96x8
128x8
PIC16CE625
2Kx14
128x8
128x8
The PIC16CE62X devices contain an 8-bit ALU and
working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.
The ALU is 8 bits wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the working register
(W register). The other operand is a file register or an
immediate constant. In single operand instructions, the
operand is either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a Borrow and Digit Borrow out bit
respectively, bit in subtraction. See the SUBLW and
SUBWF instructions for examples.
A simplified block diagram is shown in Figure 3-1, with
a description of the device pins in Table 3-1.
The PIC16CE62X can directly or indirectly address its
register files or data memory. All special function
registers including the program counter are mapped in
the data memory. The PIC16CE62X family has an
orthogonal (symmetrical) instruction set that makes it
possible to carry out any operation on any register
using any addressing mode. This symmetrical nature
and lack of ‘special optimal situations’ make programming with the PIC16CE62X simple yet efficient. In addition, the learning curve is reduced significantly.
1998-2013 Microchip Technology Inc.
DS40182D-page 7
PIC16CE62X
FIGURE 3-1:
BLOCK DIAGRAM
Device
Program Memory
PIC16CE623
PIC16CE624
PIC16CE625
512 x 14
1K x 14
2K x 14
Data Memory
(RAM)
96 x 8
96 x 8
128 x 8
EEPROM DATA
MEMORY
128 x 8
128 x 8
128 x 8
13
Program Counter
Voltage
Reference
8
Data Bus
EPROM
Program
Memory
Program
Bus
RAM
File
Registers
8 Level Stack
(13-bit)
14
RAM Addr (1)
9
Comparator
RA0/AN0
Addr MUX
Instruction reg
Direct Addr
7
8
Indirect
Addr
RA1/AN1
+
RA2/AN2/VREF
RA3/AN3
+
FSR reg
STATUS reg
TMR0
3
MUX
Power-up
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
Oscillator
Start-up Timer
Power-on
Reset
RA4/T0CKI
ALU
W reg
I/O Ports
Watchdog
Timer
Brown-out
Reset
PORTB
MCLR/VPP VDD, VSS
EEPROM
Data
Memory
128 x 8
EESCL
EESDA
EEVDD
EEINTF
Note 1: Higher order bits are from the STATUS register.
DS40182D-page 8
1998-2013 Microchip Technology Inc.
PIC16CE62X
TABLE 3-1:
Name
PIC16CE62X PINOUT DESCRIPTION
DIP/
SOIC
Pin #
SSOP
Pin #
I/O/P
Type
Buffer
Type
Description
OSC1/CLKIN
16
18
I
OSC2/CLKOUT
15
17
O
ST/CMOS Oscillator crystal input/external clock source input.
—
Oscillator crystal output. Connects to crystal or resonator
in crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and
denotes the instruction cycle rate.
MCLR/VPP
4
4
I/P
ST
Master clear (reset) input/programming voltage input.
This pin is an active low reset to the device.
PORTA is a bi-directional I/O port.
RA0/AN0
17
19
I/O
ST
RA1/AN1
18
20
I/O
ST
Analog comparator input
Analog comparator input
RA2/AN2/VREF
1
1
I/O
ST
Analog comparator input or VREF output
RA3/AN3
2
2
I/O
ST
Analog comparator input /output
RA4/T0CKI
3
3
I/O
ST
Can be selected to be the clock input to the Timer0
timer/counter or a comparator output. Output is open
drain type.
PORTB is a bi-directional I/O port. PORTB can be
software programmed for internal weak pull-up on all
inputs.
RB0/INT can also be selected as an external
interrupt pin.
RB0/INT
6
7
I/O
TTL/ST(1)
RB1
7
8
I/O
TTL
RB2
8
9
I/O
TTL
RB3
9
10
I/O
TTL
RB4
10
11
I/O
TTL
Interrupt on change pin.
RB5
11
12
I/O
TTL
Interrupt on change pin.
RB6
12
13
I/O
TTL/ST(2)
Interrupt on change pin. Serial programming clock.
RB7
13
14
I/O
TTL/ST(2)
Interrupt on change pin. Serial programming data.
VSS
5
5,6
P
—
Ground reference for logic and I/O pins.
VDD
14
15,16
P
—
Positive supply for logic and I/O pins.
Legend:
O = output
I/O = input/output
P = power
— = Not used
I = Input
ST = Schmitt Trigger input
TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
1998-2013 Microchip Technology Inc.
DS40182D-page 9
PIC16CE62X
3.1
Clocking Scheme/Instruction Cycle
3.2
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The
instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-2.
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (i.e., GOTO) then
two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q2
Q1
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
phase
clock
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
EXAMPLE 3-1:
PC
PC+1
Fetch INST (PC)
Execute INST (PC-1)
PC+2
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
INSTRUCTION PIPELINE FLOW
1. MOVLW 55h
2. MOVWF PORTB
3. CALL
SUB_1
4. BSF
PORTA, BIT3
5. Instruction @
address SUB_1
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1
Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed”
from the pipeline, while the new instruction is being fetched and then executed.
DS40182D-page 10
1998-2013 Microchip Technology Inc.
PIC16CE62X
4.0
MEMORY ORGANIZATION
4.1
Program Memory Organization
The PIC16CE62X has a 13-bit program counter capable of addressing an 8K x 14 program memory space.
Only the first 512 x 14 (0000h - 01FFh) for the
PIC16CE623, 1K x 14 (0000h - 03FFh) for the
PIC16CE624 and 2K x 14 (0000h - 07FFh) for the
PIC16CE625 are physically implemented. Accessing a
location above these boundaries will cause a
wrap-around within the first 512 x 14 space
(PIC16CE623) or 1K x 14 space (PIC16CE624) or 2K
x 14 space (PIC16CE625). The reset vector is at 0000h
and the interrupt vector is at 0004h (Figure 4-1,
Figure 4-2, Figure 4-3).
FIGURE 4-1:
FIGURE 4-2:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16CE624
PC
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 2
Stack Level 8
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16CE623
Reset Vector
000h
Interrupt Vector
0004
0005
PC
CALL, RETURN
RETFIE, RETLW
On-chip Program
Memory
13
03FFh
0400h
Stack Level 1
Stack Level 2
1FFFh
Stack Level 8
Reset Vector
FIGURE 4-3:
000h
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16CE625
PC
CALL, RETURN
RETFIE, RETLW
Interrupt Vector
0004
0005
On-chip Program
Memory
13
Stack Level 1
Stack Level 2
Stack Level 8
01FFh
0200h
Reset Vector
000h
Interrupt Vector
0004
0005
1FFFh
On-chip Program
Memory
07FFh
0800h
1FFFh
1998-2013 Microchip Technology Inc.
DS40182D-page 11
PIC16CE62X
4.2
Data Memory Organization
The data memory (Figure 4-4 and Figure 4-5) is
partitioned into two Banks which contain the General
Purpose Registers and the Special Function Registers.
Bank 0 is selected when the RP0 bit is cleared. Bank 1
is selected when the RP0 bit (STATUS ) is set. The
Special Function Registers are located in the first 32
locations of each Bank. Register locations 20-7Fh
(Bank0) on the PIC16CE623/624 and 20-7Fh (Bank0)
and A0-BFh (Bank1) on the PIC16CE625 are General
Purpose Registers implemented as static RAM. Some
special purpose registers are mapped in Bank 1. In all
three microcontrollers, address space F0h-FFh
(Bank1) is mapped to 70-7Fh (Bank0) as common
RAM.
DS40182D-page 12
4.2.1
GENERAL PURPOSE REGISTER FILE
The register file is organized as 96 x 8 in the
PIC16CE623/624 and 128 x 8 in the PIC16CE625.
Each is accessed either directly or indirectly through
the File Select Register FSR (Section 4.4).
1998-2013 Microchip Technology Inc.
PIC16CE62X
FIGURE 4-4:
DATA MEMORY MAP FOR
THE PIC16CE623/624
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
PCON
EEINTF
CMCON
VRCON
FIGURE 4-5:
File
Address
File
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
A0h
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
PCON
EEINTF
CMCON
VRCON
General
Purpose
Register
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
BFh
C0h
Accesses
70h-7Fh
EFh
F0h
FFh
Bank 0
File
Address
General
Purpose
Register
General
Purpose
Register
7Fh
DATA MEMORY MAP FOR
THE PIC16CE625
Bank 1
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
1998-2013 Microchip Technology Inc.
Accesses
70h-7Fh
7Fh
F0h
FFh
Bank 0
Bank 1
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
DS40182D-page 13
PIC16CE62X
4.2.2
SPECIAL FUNCTION REGISTERS
The special registers can be classified into two sets
(core and peripheral). The Special Function Registers
associated with the “core” functions are described in
this section. Those related to the operation of the
peripheral features are described in the section of that
peripheral feature.
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (Table 4-1). These
registers are static RAM.
TABLE 4-1:
SPECIAL REGISTERS FOR THE PIC16CE62X
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR Reset
Value on all
other
resets(1)
Bank 0
00h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical
register)
xxxx xxxx
xxxx xxxx
01h
TMR0
Timer0 Module’s Register
xxxx xxxx
uuuu uuuu
02h
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
0000 0000
000q quuu
IRP(2)
(2)
03h
STATUS
04h
FSR
05h
PORTA
—
—
—
RB7
RB6
RB5
RP1
RP0
PD
Z
DC
C
0001 1xxx
xxxx xxxx
uuuu uuuu
RA4
RA3
RA2
RA1
RA0
---x 0000
---u 0000
RB4
RB3
RB2
RB1
RB0
TO
Indirect data memory address pointer
06h
PORTB
xxxx xxxx
uuuu uuuu
07h
Unimplemented
—
—
08h
Unimplemented
—
—
09h
Unimplemented
—
—
0Ah
PCLATH
—
---0 0000
---0 0000
0Bh
INTCON
0Ch
PIR1
—
—
Write buffer for upper 5 bits of program counter
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
—
CMIF
—
—
—
—
—
—
-0-- ----
-0-- ----
—
—
C2OUT
C1OUT
—
—
CIS
CM2
CM1
CM0
00-- 0000
00-- 0000
xxxx xxxx
xxxx xxxx
1111 1111
1111 1111
0000 0000
0000 0000
0001 1xxx
000q quuu
0Dh-1Eh Unimplemented
1Fh
CMCON
Bank 1
80h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical
register)
81h
OPTION
82h
PCL
RBPU
83h
STATUS
84h
FSR
85h
TRISA
—
—
—
TRISA4
TRISA3
TRISA2
TRISA1
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter's (PC) Least Significant Byte
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
TRISA0
---1 1111
---1 1111
TRISB0
86h
TRISB
1111 1111
1111 1111
87h
Unimplemented
—
—
88h
Unimplemented
—
—
89h
Unimplemented
—
—
8Ah
PCLATH
—
---0 0000
---0 0000
8Bh
INTCON
8Ch
PIE1
8Dh
Unimplemented
8Eh
PCON
—
—
Write buffer for upper 5 bits of program counter
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
—
CMIE
—
—
—
—
—
—
-0-- ----
-0-- ----
—
—
—
—
—
—
—
—
POR
BOD
---- --0x
---- --uq
8Fh-9Eh
Unimplemented
—
—
90h
EEINTF
—
—
—
—
—
EESCL
EESDA
EEVDD
---- -111
---- -111
9Fh
VRCON
VREN
VROE
VRR
—
VR3
VR2
VR1
VR0
000- 0000
000- 0000
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1:
Other (non power-up) resets include MCLR reset, Brown-out Reset and Watchdog Timer Reset during normal
operation.
Note 2:
IRP & RPI bits are reserved; always maintain these bits clear.
DS40182D-page 14
1998-2013 Microchip Technology Inc.
PIC16CE62X
4.2.2.1
STATUS REGISTER
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any status bit. For other instructions, not affecting
any status bits, see the “Instruction Set Summary”.
The STATUS register, shown in Register 4-1, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
Note 1:
The IRP and RP1 bits (STATUS)
are not used by the PIC16CE62X and
should be programmed as ’0'. Use of
these bits as general purpose R/W bits
is NOT recommended, since this may
affect upward compatibility with future
products.
Note 2:
The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the status register as
000uu1uu (where u = unchanged).
REGISTER 4-1:
STATUS REGISTER (ADDRESS 03H OR 83H)
Reserved Reserved
IRP
RP1
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
RP0
TO
PD
Z
DC
C
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
-x = Unknown at POR reset
bit 7:
IRP: The IRP bit is reserved on the PIC16CE62X, always maintain this bit clear.
bit 6:5
RP: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes. The RP1 bit is reserved, always maintain this bit clear.
bit 4:
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3:
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2:
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1:
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0:
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
1998-2013 Microchip Technology Inc.
DS40182D-page 15
PIC16CE62X
4.2.2.2
OPTION REGISTER
Note: To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT
(PSA = 1).
The OPTION register is a readable and writable
register which contains various control bits to configure
the TMR0/WDT prescaler, the external RB0/INT
interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 4-2:
OPTION REGISTER (ADDRESS 81H)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit7
bit0
bit 7:
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6:
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5:
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4:
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3:
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
-x = Unknown at POR reset
bit 2-0: PS: Prescaler Rate Select bits
Bit Value
000
001
010
011
100
101
110
111
DS40182D-page 16
TMR0 Rate
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
WDT Rate
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1998-2013 Microchip Technology Inc.
PIC16CE62X
4.2.2.3
INTCON REGISTER
Note:
The INTCON register is a readable and writable
register which contains the various enable and flag bits
for all interrupt sources except the comparator module.
See Section 4.2.2.4 and Section 4.2.2.5 for a
description of the comparator enable and flag bits.
REGISTER 4-3:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON).
INTCON REGISTER (ADDRESS 0BH OR 8BH)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
-x = Unknown at POR reset
bit 7:
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6:
PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5:
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4:
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3:
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2:
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1:
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0:
RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB pins changed state (must be cleared in software)
0 = None of the RB pins have changed state
1998-2013 Microchip Technology Inc.
DS40182D-page 17
PIC16CE62X
4.2.2.4
PIE1 REGISTER
This register contains the individual enable bit for the
comparator interrupt.
REGISTER 4-4:
PIE1 REGISTER (ADDRESS 8CH)
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
—
CMIE
—
—
—
—
—
—
bit7
bit0
bit 7:
Unimplemented: Read as '0'
bit 6:
CMIE: Comparator Interrupt Enable bit
1 = Enables the Comparator interrupt
0 = Disables the Comparator interrupt
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
-x = Unknown at POR reset
bit 5-0: Unimplemented: Read as '0'
4.2.2.5
PIR1 REGISTER
This register contains the individual flag bit for the comparator interrupt.
Note:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
REGISTER 4-5:
PIR1 REGISTER (ADDRESS 0CH)
U-0
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
—
CMIF
—
—
—
—
—
—
bit7
bit0
bit 7:
Unimplemented: Read as '0'
bit 6:
CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed
0 = Comparator input has not changed
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
-x = Unknown at POR reset
bit 5-0: Unimplemented: Read as '0'
DS40182D-page 18
1998-2013 Microchip Technology Inc.
PIC16CE62X
4.2.2.6
PCON REGISTER
The PCON register contains flag bits to differentiate
between a Power-on Reset, an external MCLR reset,
WDT reset or a Brown-out Reset.
Note: BOD is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent resets to see if BOD is
cleared, indicating a brown-out has
occurred. The BOD status bit is a "don't
care" and is not necessarily predictable if
the brown-out circuit is disabled (by
programming
BODEN
bit
in
the
configuration word).
REGISTER 4-6:
PCON REGISTER (ADDRESS 8Eh)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
—
—
—
—
—
—
POR
BOD
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
-n = Value at POR reset
-x = Unknown at POR reset
bit 7-2: Unimplemented: Read as '0'
bit 1:
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0:
BOD: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
1998-2013 Microchip Technology Inc.
DS40182D-page 19
PIC16CE62X
4.3
4.3.2
PCL and PCLATH
The program counter (PC) is 13 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC) is not directly
readable or writable and comes from PCLATH. On any
reset, the PC is cleared. Figure 4-6 shows the two
situations for the loading of the PC. The upper example in
the figure shows how the PC is loaded on a write to PCL
(PCLATH PCH). The lower example in the figure
shows how the PC is loaded during a CALL or GOTO
instruction (PCLATH PCH).
FIGURE 4-6:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
8
7
0
PC
8
PCLATH
ALU result
PCH
11 10
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
PCL
8
0
7
PC
Note 1:
There are no STATUS bits to indicate
stack overflow or stack underflow
conditions.
Note 2:
There are no instruction/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
interrupt address.
Instruction with
PCL as
Destination
PCLATH
12
The PIC16CE62X family has an 8 level deep x 13-bit
wide hardware stack (Figure 4-2 and Figure 4-3). The
stack space is not part of either program or data
space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL
instruction is executed or an interrupt causes a
branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or POP operation.
PCL
12
5
STACK
GOTO, CALL
2
PCLATH
11
Opcode
PCLATH
4.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note, “Implementing a Table Read"
(AN556).
DS40182D-page 20
1998-2013 Microchip Technology Inc.
PIC16CE62X
4.4
Indirect Addressing, INDF and FSR
Registers
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 4-1.
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
EXAMPLE 4-1:
Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually
accesses data pointed to by the File Select Register
(FSR). Reading INDF itself indirectly will produce 00h.
Writing to the INDF register indirectly results in a
no-operation (although status bits may be affected). An
effective 9-bit address is obtained by concatenating the
8-bit FSR register and the IRP bit (STATUS), as
shown in Figure 4-7. However, IRP is not used in the
PIC16CE62X.
FIGURE 4-7:
NEXT
movlw
0x20
;initialize pointer
movwf
FSR
;to RAM
clrf
INDF
;clear INDF register
incf
FSR
;inc pointer
btfss
FSR,4
;all done?
goto
NEXT
;no clear next
;yes continue
CONTINUE:
DIRECT/INDIRECT ADDRESSING PIC16CE62X
Direct Addressing
RP1
RP0
(1)
bank select
INDIRECT ADDRESSING
6
from opcode
Indirect Addressing
IRP(1)
0
7
bank select
location select
00
01
10
FSR Register
0
location select
11
00h
180h
not used
Data
Memory
7Fh
1FFh
Bank 0
Bank 1
Bank 2
Bank 3
For memory map detail see Figure 4-4 and Figure 4-5.
Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.
1998-2013 Microchip Technology Inc.
DS40182D-page 21
PIC16CE62X
NOTES:
DS40182D-page 22
1998-2013 Microchip Technology Inc.
PIC16CE62X
5.0
I/O PORTS
Note:
The PIC16CE62X parts have two ports, PORTA and
PORTB. Some pins for these I/O ports are multiplexed
with an alternate function for the peripheral features on
the device. In general, when a peripheral is enabled,
that pin may not be used as a general purpose I/O pin.
5.1
PORTA and TRISA Registers
PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger input
and an open drain output. Port RA4 is multiplexed with the
T0CKI clock input. All other RA port pins have Schmitt
Trigger input levels and full CMOS output drivers. All pins
have data direction bits (TRIS registers), which can configure these pins as input or output.
A '1' in the TRISA register puts the corresponding output
driver in a hi- impedance mode. A '0' in the TRISA register
puts the contents of the output latch on the selected pin(s).
Reading the PORTA register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then this
value is modified and written to the port data latch.
The PORTA pins are multiplexed with comparator and
voltage reference functions. The operation of these
pins are selected by control bits in the CMCON
(Comparator Control Register) register and the
VRCON (Voltage Reference Control Register) register.
When selected as a comparator input, these pins will
read as '0's.
FIGURE 5-1:
Data
Bus
D
BLOCK DIAGRAM OF
RA PINS
CK
WR
TRISA
In one of the comparator modes defined by the
CMCON register, pins RA3 and RA4 become outputs
of the comparators. The TRISA bits must be
cleared to enable outputs to use this function.
EXAMPLE 5-1:
CLRF
Q
;Initialize PORTA by setting
;output data latches
MOVLW 0X07
;Turn comparators off and
MOVWF CMCON
;enable pins for I/O
;functions
BSF
STATUS, RP0 ;Select Bank1
MOVLW 0x1F
;Value used to initialize
;data direction
MOVWF TRISA
;Set RA as inputs
;TRISA are always
;read as '0'.
FIGURE 5-2:
D
BLOCK DIAGRAM OF RA2 PIN
Q
VDD VDD
CK
Q
D
WR
TRISA
I/O Pin
Q
N
CK
RD TRISA
VSS
Analog
Input Mode
RD TRISA
Schmitt Trigger
Input Buffer
Q
RD PORTA
VSS
Analog
Input Mode
Schmitt Trigger
Input Buffer
Q
D
EN
RA2 Pin
Q
TRIS Latch
Q
TRIS Latch
P
Data Latch
P
N
INITIALIZING PORTA
PORTA
VDD
Q
CK
The RA2 pin will also function as the output for the
voltage reference. When in this mode, the VREF pin is a
very high impedance output. The user must configure
TRISA bit as an input and use high impedance
loads.
WR
PortA
Data Latch
D
TRISA controls the direction of the RA pins, even when
they are being used as comparator inputs. The user
must make sure to keep the pins configured as inputs
when using them as comparator inputs.
Data
Bus
Q
VDD
WR
PortA
On reset, the TRISA register is set to all
inputs. The digital inputs are disabled and
the comparator inputs are forced to ground
to reduce excess current consumption.
D
EN
RD PORTA
To Comparator
VROE
To Comparator
VREF
1998-2013 Microchip Technology Inc.
DS40182D-page 23
PIC16CE62X
FIGURE 5-3:
Data
Bus
BLOCK DIAGRAM OF RA3 PIN
Comparator Mode = 110
D
Q
Comparator Output
WR
PORTA
VDD
Q
CK
Data Latch
D
VDD
P
Q
RA3 Pin
N
WR
TRISA
CK
Q
VSS
Analog
Input Mode
TRIS Latch
Schmitt Trigger
Input Buffer
RD TRISA
Q
D
EN
RD PORTA
To Comparator
FIGURE 5-4:
Data
Bus
BLOCK DIAGRAM OF RA4 PIN
Comparator Mode = 110
D
Q
Comparator Output
WR
PORTA
CK
Q
Data Latch
D
WR
TRISA
Q
N
CK
RA4 Pin
Q
VSS
TRIS Latch
Schmitt Trigger
Input Buffer
RD TRISA
Q
D
EN
RD PORTA
TMR0 Clock Input
DS40182D-page 24
1998-2013 Microchip Technology Inc.
PIC16CE62X
TABLE 5-1:
PORTA FUNCTIONS
Name
Bit #
Buffer
Type
RA0/AN0
RA1/AN1
RA2/AN2/VREF
RA3/AN3
RA4/T0CKI
bit0
bit1
bit2
bit3
bit4
ST
ST
ST
ST
ST
Function
Input/output or comparator input
Input/output or comparator input
Input/output or comparator input or VREF output
Input/output or comparator input/output
Input/output or external clock input for TMR0 or comparator output.
Output is open drain type.
Legend: ST = Schmitt Trigger input
TABLE 5-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR
Value on
All Other
Resets
05h
PORTA
—
—
—
RA4
RA3
RA2
RA1
RA0
---x 0000
---u 0000
85h
TRISA
—
—
—
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
---1 1111
---1 1111
1Fh
CMCON
C2OUT
C1OUT
—
—
CIS
CM2
CM1
CM0
00-- 0000
00-- 0000
9Fh
VRCON
VREN
VROE
VRR
—
VR3
VR2
VR1
VR0
000- 0000
000- 0000
Legend: — = Unimplemented locations, read as ‘0’, x = unknown, u = unchanged
Note:
Shaded bits are not used by PORTA.
1998-2013 Microchip Technology Inc.
DS40182D-page 25
PIC16CE62X
5.2
PORTB and TRISB Registers
PORTB is an 8-bit wide, bi-directional port. The
corresponding data direction register is TRISB. A '1' in
the TRISB register puts the corresponding output driver
in a high impedance mode. A '0' in the TRISB register
puts the contents of the output latch on the selected
pin(s).
Reading PORTB register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then
this value is modified and written to the port data latch.
Each of the PORTB pins has a weak internal pull-up
(200 A typical). A single control bit can turn on all the
pull-ups. This is done by clearing the RBPU
(OPTION) bit. The weak pull-up is automatically
turned off when the port pin is configured as an output.
The pull-ups are disabled on Power-on Reset.
Four of PORTB’s pins, RB, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB pin configured as an output is excluded from the interrupt on
change comparison). The input pins of RB are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB are
OR’ed together to generate the RBIF interrupt (flag
latched in INTCON).
FIGURE 5-5:
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
a)
b)
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
This interrupt on mismatch feature, together with
software configurable pull-ups on these four pins allow
easy interface to a key pad and make it possible for
wake-up on key-depression. (See AN552, “Implementing Wake-Up on Key Strokes”.)
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF interrupt flag may not get set.
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
FIGURE 5-6:
VDD
RBPU(1)
BLOCK DIAGRAM OF
RB PINS
P
RBPU(1)
P
Data Bus
WR PORTB
WR PORTB
weak
pull-up
weak
pull-up
Data Latch
D
Q
Data Bus
VDD
Data Latch
D
Q
BLOCK DIAGRAM OF
RB PINS
I/O pin
CK
I/O pin
D
CK
WR TRISB
Q
TTL
Input
Buffer
(1)
CK
TRIS Latch
D
Q
WR TRISB(1)
TTL
Input
Buffer
CK
RD TRISB
ST
Buffer
Q
RD PORTB
RD TRISB
D
EN
Latch
Q
D
RB0/INT
Set RBIF
EN
RD PORTB
From other
RB pins
Q
ST
Buffer
D
RD Port
Note 1: TRISB = 1 enables weak pull-up if RBPU = '0'
(OPTION).
EN
RD Port
RB in serial programming mode
Note 1: TRISB = 1 enables weak pull-up if RBPU = '0'
(OPTION).
DS40182D-page 26
1998-2013 Microchip Technology Inc.
PIC16CE62X
TABLE 5-3:
Name
PORTB FUNCTIONS
Bit #
Buffer Type
Function
Input/output or external interrupt input. Internal software programmable
RB0/INT
bit0
TTL/ST
weak pull-up.
RB1
bit1
TTL
Input/output pin. Internal software programmable weak pull-up.
RB2
bit2
TTL
Input/output pin. Internal software programmable weak pull-up.
RB3
bit3
TTL
Input/output pin. Internal software programmable weak pull-up.
RB4
bit4
TTL
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB5
bit5
TTL
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
Input/output pin (with interrupt on change). Internal software programmable
RB6
bit6
TTL/ST(2)
weak pull-up. Serial programming clock pin.
(2)
Input/output pin (with interrupt on change). Internal software programmable
RB7
bit7
TTL/ST
weak pull-up. Serial programming data pin.
Legend: ST = Schmitt Trigger, TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
(1)
TABLE 5-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR
Value on
All Other
Resets
06h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
86h
TRISB
TRISB7
TRISB6
TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111
1111 1111
81h
OPTION
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
Legend: u = unchanged, x = unknown
Note:
Shaded bits are not used by PORTB.
1998-2013 Microchip Technology Inc.
DS40182D-page 27
PIC16CE62X
5.3
I/O Programming Considerations
5.3.1
BI-DIRECTIONAL I/O PORTS
EXAMPLE 5-2:
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
Any instruction which writes, operates internally as a
read followed by a write operation. The BCF and BSF
instructions, for example, read the register into the
CPU, execute the bit operation and write the result back
to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSF operation on bit5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSF operation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bidirectional I/O pin
(i.e., bit0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and re-written to the data latch of this
particular pin, overwriting the previous content. As long
as the pin stays in the input mode, no problem occurs.
However, if bit0 is switched into output mode later on,
the content of the data latch may now be unknown.
; Initial PORT settings: PORTB Inputs
;
;
PORTB Outputs
; PORTB have external pull-up and are not
; connected to other circuitry
;
;
PORT latch PORT pins
;
---------- ----------
Reading the port register, reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read modify write instructions
(i.e., BCF, BSF, etc.) on a port, the value of the port pins
is read, the desired operation is done to this value, and
this value is then written to the port latch.
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle
(Figure 5-7). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should
allow the pin voltage to stabilize (load dependent)
before the next instruction causes that file to be read
into the CPU. Otherwise, the previous state of that pin
may be read into the CPU rather than the new state.
When in doubt, it is better to separate these instructions with an NOP or another instruction not accessing
this I/O port.
BCF
BCF
BSF
BCF
BCF
5.3.2
A pin actively outputting a Low or High should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage
the chip.
Q1
Q2
PC
fetched
Fetched
pppp
pppp
11pp pppp
11pp pppp
pppp
pppp
11pp pppp
10pp pppp
SUCCESSIVE OPERATIONS ON I/O PORTS
SUCCESSIVE I/O OPERATION
PC
Instruction
Instruction
; 01pp
; 10pp
;
; 10pp
; 10pp
;
; Note that the user may have expected the pin
; values to be 00pp pppp. The 2nd BCF caused
; RB7 to be latched as the pin value (High).
Example 5-2 shows the effect of two sequential
read-modify-write instructions (i.e., BCF, BSF, etc.) on
an I/O port.
FIGURE 5-7:
PORTB, 7
PORTB, 6
STATUS,RP0
TRISB, 7
TRISB, 6
Q3
Q4
PC
MOVWF PORTB
Write to
PORTB
Q1
Q2
Q3
Q4
PC + 1
MOVF PORTB, W
Read PORTB
Q1
Q2
Q3
Q4
Q1
Q2
Q3
PC + 2
PC + 3
NOP
NOP
Port pin
sampled here
This example shows write to PORTB
followed by a read from PORTB.
Note that:
Therefore, at higher clock frequencies,
a write followed by a read may be
problematic.
T PD
DS40182D-page 28
Note:
data setup time = (0.25 TCY - TPD)
where TCY = instruction cycle and
TPD = propagation delay of Q1 cycle
to output valid.
RB
RB
Execute
MOVWF
PORTB
Q4
Execute
MOVF
PORTB, W
Execute
NOP
1998-2013 Microchip Technology Inc.
PIC16CE62X
6.0
EEPROM PERIPHERAL
OPERATION
The PIC16CE623/624/625 each have 128 bytes of
EEPROM data memory. The EEPROM data memory
supports a bi-directional, 2-wire bus and data transmission protocol. These two-wires are serial data (SDA)
and serial clock (SCL), and are mapped to bit1 and bit2,
respectively, of the EEINTF register (SFR 90h). In addition, the power to the EEPROM can be controlled using
bit0 (EEVDD) of the EEINTF register. For most applications, all that is required is calls to the following functions:
; Byte_Write: Byte write routine
;
Inputs: EEPROM Address
EEADDR
;
EEPROM Data
EEDATA
;
Outputs:
Return 01 in W if OK, else
;
return 00 in W
;
; Read_Current: Read EEPROM at address
currently held by EE device.
;
Inputs: NONE
;
Outputs:
EEPROM Data
EEDATA
;
Return 01 in W if OK, else
;
return 00 in W
;
; Read_Random: Read EEPROM byte at supplied
; address
;
Inputs: EEPROM Address
EEADDR
;
Outputs:
EEPROM Data
EEDATA
;
Return 01 in W if OK,
;
else return 00 in W
The code for these functions is available on our web
site (www.microchip.com). The code will be accessed
by either including the source code FL62XINC.ASM or
by linking FLASH62X.ASM. FLASH62.IMC provides
external definition to the calling program.
6.0.1
SERIAL DATA
SDA is a bi-directional pin used to transfer addresses
and data into and data out of the memory.
For normal data transfer, SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP conditions.
6.0.2
SERIAL CLOCK
This SCL input is used to synchronize the data transfer
to and from the memory.
6.0.3
EEINTF REGISTER
The EEINTF register (SFR 90h) controls the access to
the EEPROM. Register 6-1 details the function of each
bit. User code must generate the clock and data signals.
REGISTER 6-1: EEINTF REGISTER (ADDRESS 90h)
U-0
U-0
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
EESCL
EESDA
EEVDD
bit7
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 7-3: Unimplemented: Read as '0'
bit 2:
EESCL: Clock line to the EEPROM
1 = Clock high
0 = Clock low
bit 1:
EESDA: Data line to EEPROM
1 = Data line is high (pin is tri-stated, line is pulled high by a pull-up resistor)
0 = Data line is low
bit 0:
EEVDD: VDD control bit for EEPROM
1 = VDD is turned on to EEPROM
0 = VDD is turned off to EEPROM (all pins are tri-stated and the EEPROM is powered down)
Note:
EESDA, EESCL and EEVDD will read ‘0’ if EEVDD is turned off.
1998-2013 Microchip Technology Inc.
DS40182D-page 29
PIC16CE62X
6.1
Bus Characteristics
In this section, the term “processor” refers to the portion
of the PIC16CE62X that interfaces to the EEPROM
through software manipulating the EEINTF register.
The following bus protocol is to be used with the
EEPROM data memory.
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted by the EEPROM as a START or STOP
condition.
Accordingly, the following bus conditions have been
defined (Figure 6-1).
6.1.1
BUS NOT BUSY (A)
Both data and clock lines remain HIGH.
6.1.2
6.1.5
ACKNOWLEDGE
The EEPROM will generate an acknowledge after the
reception of each byte. The processor must generate
an extra clock pulse which is associated with this
acknowledge bit.
Note:
Acknowledge bits are not generated if an
internal programming cycle is in progress.
When the EEPROM acknowledges, it pulls down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. The processor must signal an end of data to
the EEPROM by not generating an acknowledge bit on
the last byte that has been clocked out of the EEPROM.
In this case, the EEPROM must leave the data line
HIGH to enable the processor to generate the STOP
condition (Figure 6-2).
START DATA TRANSFER (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
6.1.3
STOP DATA TRANSFER (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
6.1.4
DATA VALID (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the processor and
is theoretically unlimited, although only the last sixteen
will be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first-in,
first-out fashion.
DS40182D-page 30
1998-2013 Microchip Technology Inc.
PIC16CE62X
FIGURE 6-1:
SCL
(A)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(B)
(C)
(D)
(C)
(A)
SDA
START
CONDITION
FIGURE 6-2:
STOP
CONDITION
ADDRESS OR
DATA
ACKNOWLEDGE ALLOWED
VALID
TO CHANGE
ACKNOWLEDGE TIMING
Acknowledge
Bit
SCL
1
2
SDA
3
4
5
6
7
8
9
1
Device Addressing
After generating a START condition, the processor
transmits a control byte consisting of a EEPROM
address and a Read/Write bit that indicates what type
of operation is to be performed. The EEPROM address
consists of a 4-bit device code (1010) followed by three
don't care bits.
The last bit of the control byte determines the operation
to be performed. When set to a one, a read operation
is selected, and when set to a zero, a write operation is
selected. (Figure 6-3). The bus is monitored for its corresponding EEPROM address all the time. It generates
an acknowledge bit if the EEPROM address was true
and it is not in a programming mode.
1998-2013 Microchip Technology Inc.
3
Data from transmitter
Data from transmitter
Receiver must release the SDA line at this
point so the Transmitter can continue
sending data.
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
6.2
2
FIGURE 6-3:
CONTROL BYTE FORMAT
Read/Write Bit
Device Select
Bits
S
1
0
1
Don’t Care
Bits
0
X
X
X
R/W ACK
EEPROM Address
Start Bit
Acknowledge Bit
DS40182D-page 31
PIC16CE62X
6.3
Write Operations
6.4
6.3.1
BYTE WRITE
Since the EEPROM will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write command has been issued from the processor, the
EEPROM initiates the internally timed write cycle. ACK
polling can be initiated immediately. This involves the
processor sending a start condition followed by the
control byte for a write command (R/W = 0). If the
device is still busy with the write cycle, then no ACK will
be returned. If no ACK is returned, then the start bit and
control byte must be re-sent. If the cycle is complete,
then the device will return the ACK and the processor
can then proceed with the next read or write command.
See Figure 6-4 for flow diagram.
Following the start signal from the processor, the
device code (4 bits), the don't care bits (3 bits), and the
R/W bit, which is a logic low, is placed onto the bus by
the processor. This indicates to the EEPROM that a
byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle.
Therefore, the next byte transmitted by the processor is
the word address and will be written into the address
pointer of the EEPROM. After receiving another
acknowledge signal from the EEPROM, the processor
will transmit the data word to be written into the
addressed memory location. The EEPROM acknowledges again and the processor generates a stop condition. This initiates the internal write cycle, and during
this time, the EEPROM will not generate acknowledge
signals (Figure 6-5).
6.3.2
Acknowledge Polling
FIGURE 6-4:
PAGE WRITE
ACKNOWLEDGE POLLING
FLOW
Send
Write Command
The write control byte, word address and the first data
byte are transmitted to the EEPROM in the same way
as in a byte write. But instead of generating a stop condition, the processor transmits up to eight data bytes to
the EEPROM, which are temporarily stored in the onchip page buffer and will be written into the memory
after the processor has transmitted a stop condition.
After the receipt of each word, the three lower order
address pointer bits are internally incremented by one.
The higher order five bits of the word address remains
constant. If the processor should transmit more than
eight words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received, an internal write cycle will begin (Figure 6-6).
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did EEPROM
Acknowledge
(ACK = 0)?
NO
YES
Next
Operation
FIGURE 6-5:
BYTE WRITE
BUS ACTIVITY
PROCESSOR
S
T
A
R
T
SDA LINE
S 1
BUS ACTIVITY
CONTROL
BYTE
0
1
0
X X
WORD
ADDRESS
X
S
T
O
P
DATA
P
X
0
A
C
K
A
C
K
A
C
K
X = Don’t Care Bit
DS40182D-page 32
1998-2013 Microchip Technology Inc.
PIC16CE62X
FIGURE 6-6:
BUS ACTIVITY
PROCESSOR
SDA LINE
PAGE WRITE
S
T
A
R
T
CONTROL
BYTE
A
C
K
Read Operation
Current Address Read
The EEPROM contains an address counter that maintains the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n, the
next current address read operation would access data
from address n + 1. Upon receipt of the EEPROM
address with R/W bit set to one, the EEPROM issues
an acknowledge and transmits the eight bit data word.
The processor will not acknowledge the transfer, but
does generate a stop condition and the EEPROM discontinues transmission (Figure 6-7).
6.7
S
T
O
P
DATAn + 7
DATAn + 1
P
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
EEPROM address is set to one. There are three basic
types of read operations: current address read, random
read, and sequential read.
6.6
DATAn
S
BUS ACTIVITY
6.5
WORD
ADDRESS (n)
Random Read
A
C
K
A
C
K
6.8
A
C
K
A
C
K
Sequential Read
Sequential reads are initiated in the same way as a random read except that after the EEPROM transmits the
first data byte, the processor issues an acknowledge as
opposed to a stop condition in a random read. This
directs the EEPROM to transmit the next sequentially
addressed 8-bit word (Figure 6-9).
To provide sequential reads, the EEPROM contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
6.9
Noise Protection
The EEPROM employs a VCC threshold detector circuit, which disables the internal erase/write logic if the
VCC is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt trigger and filter
circuits, which suppress noise spikes to assure proper
device operation even on a noisy bus.
Random read operations allow the processor to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
EEPROM as part of a write operation. After the word
address is sent, the processor generates a start condition following the acknowledge. This terminates the
write operation, but not before the internal address
pointer is set. Then the processor issues the control
byte again, but with the R/W bit set to a one. The
EEPROM will then issue an acknowledge and transmits the eight bit data word. The processor will not
acknowledge the transfer, but does generate a stop
condition and the EEPROM discontinues transmission
(Figure 6-8).
1998-2013 Microchip Technology Inc.
DS40182D-page 33
PIC16CE62X
FIGURE 6-7:
CURRENT ADDRESS READ
BUS ACTIVITY
PROCESSOR
S
T
A
R
T
SDA LINE
S
CONTROL
BYTE
S
T
O
P
DATAn
P
N
O
A
C
K
BUS ACTIVITY
A
C
K
FIGURE 6-8:
RANDOM READ
S
T
BUS ACTIVITY A
PROCESSOR R
T
CONTROL
BYTE
S
T
A
R
T
WORD
ADDRESS (n)
S
SDA LINE
CONTROL
BYTE
S
T
O
P
DATAn
P
S
A
C
K
BUS ACTIVITY
A
C
K
N
O
A
C
K
A
C
K
FIGURE 6-9:
SEQUENTIAL READ
BUS ACTIVITY
PROCESSOR
A
C
K
CONTROL
BYTE
A
C
K
S
T
O
P
A
C
K
SDA LINE
BUS ACTIVITY
P
A
C
K
DATAn
DATAn + 1
DATAn + 2
DATAn + X
N
O
A
C
K
DS40182D-page 34
1998-2013 Microchip Technology Inc.
PIC16CE62X
7.0
TIMER0 MODULE
bit (OPTION). Clearing the T0SE bit selects the
rising edge. Restrictions on the external clock input are
discussed in detail in Section 7.2.
The Timer0 module timer/counter has the following
features:
•
•
•
•
•
•
The prescaler is shared between the Timer0 module
and the Watchdog Timer. The prescaler assignment is
controlled in software by the control bit PSA
(OPTION). Clearing the PSA bit will assign the
prescaler to Timer0. The prescaler is not readable or
writable. When the prescaler is assigned to the Timer0
module, prescale value of 1:2, 1:4, ..., 1:256 are
selectable. Section 7.3 details the operation of the
prescaler.
8-bit timer/counter
Readable and writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt on overflow from FFh to 00h
Edge select for external clock
Figure 7-1 is a simplified block diagram of the Timer0
module.
7.1
Timer mode is selected by clearing the T0CS bit
(OPTION). In timer mode, the TMR0 will increment
every instruction cycle (without prescaler). If Timer0 is
written, the increment is inhibited for the following two
cycles (Figure 7-2 and Figure 7-3). The user can work
around this by writing an adjusted value to TMR0.
Timer0 interrupt is generated when the TMR0 register
timer/counter overflows from FFh to 00h. This overflow
sets the T0IF bit. The interrupt can be masked by
clearing the T0IE bit (INTCON). The T0IF bit
(INTCON) must be cleared in software by the
Timer0 module interrupt service routine before
re-enabling this interrupt. The Timer0 interrupt cannot
wake the processor from SLEEP since the timer is shut
off during SLEEP. See Figure 7-4 for Timer0 interrupt
timing.
Counter mode is selected by setting the T0CS bit. In
this mode Timer0 will increment either on every rising
or falling edge of pin RA4/T0CKI. The incrementing
edge is determined by the source edge (T0SE) control
FIGURE 7-1:
Timer0 Interrupt
TIMER0 BLOCK DIAGRAM
Data Bus
RA4/T0CKI
pin
FOSC/4
0
PSout
1
1
Programmable
Prescaler
0
TMR0
PSout
(2 TCY delay)
T0SE
PS
8
Sync with
Internal
clocks
Set Flag bit T0IF
on Overflow
PSA
T0CS
Note 1:
2:
Bits T0SE, T0CS, PS2, PS1, PS0 and PSA are located in the OPTION register.
The prescaler is shared with Watchdog Timer (Figure 7-6)
FIGURE 7-2:
PC
(Program
Counter)
Instruction
Fetch
TMR0
TIMER0 (TMR0) TIMING: INTERNAL CLOCK/NO PRESCALER
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1
PC
MOVWF TMR0
T0
T0+1
PC+1
PC+2
PC+3
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
T0+2
PC+4
MOVF TMR0,W
NT0
PC+5
PC+6
MOVF TMR0,W
NT0+1
NT0+2
T0
Instruction
Executed
Write TMR0
executed
1998-2013 Microchip Technology Inc.
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
Read TMR0
reads NT0 + 2
DS40182D-page 35
PIC16CE62X
FIGURE 7-3:
PC
(Program
Counter)
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1
Instruction
Fetch
TMR0
PC
PC+1
MOVWF TMR0
MOVF TMR0,W
T0
PC+2
PC+3
T0+1
Instruction
Execute
PC+4
MOVF TMR0,W MOVF TMR0,W
PC+5
MOVF TMR0,W
PC+6
MOVF TMR0,W
NT0+1
NT0
Write TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0 Read TMR0
executed
reads NT0 reads NT0 reads NT0 reads NT0
reads NT0 + 1
FIGURE 7-4:
TIMER0 INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT(3)
TMR0 timer
FEh
FFh
1
T0IF bit
(INTCON)
00h
01h
02h
1
GIE bit
(INTCON)
Interrupt Latency Time
INSTRUCTION FLOW
PC
PC
Instruction
fetched
Inst (PC)
Instruction
executed
Inst (PC-1)
PC +1
PC +1
Inst (PC+1)
Inst (PC)
Dummy cycle
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy cycle
Inst (0004h)
Note 1: T0IF interrupt flag is sampled here (every Q1).
2: Interrupt latency = 3TCY, where TCY = instruction cycle time.
3: CLKOUT is available only in RC oscillator mode.
DS40182D-page 36
1998-2013 Microchip Technology Inc.
PIC16CE62X
7.2
Using Timer0 with External Clock
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
7.2.1
EXTERNAL CLOCK SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 7-5). Therefore, it is necessary for T0CKI to be
high for at least 2TOSC (and a small RC delay of 20 ns)
and low for at least 2TOSC (and a small RC delay of
20 ns). Refer to the electrical specification of the
desired device.
FIGURE 7-5:
When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple-counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4TOSC (and a small RC delay of 40 ns)
divided by the prescaler value. The only requirement on
T0CKI high and low time is that they do not violate the
minimum pulse width requirement of 10 ns. Refer to
parameters 40, 41 and 42 in the electrical specification
of the desired device.
7.2.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the TMR0 is
actually incremented. Figure 7-5 shows the delay from
the external clock edge to the timer incrementing.
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
External Clock Input or
Prescaler output (2)
Q1 Q2 Q3 Q4
Small pulse
misses sampling
(1)
External Clock/Prescaler
Output after sampling
(3)
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3TOSC to 7TOSC. (Duration of Q = TOSC).
Therefore, the error in measuring the interval between two edges on Timer0 input = ±4TOSC max.
2: External clock if no prescaler selected; prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
1998-2013 Microchip Technology Inc.
DS40182D-page 37
PIC16CE62X
7.3
Prescaler
The PSA and PS bits (OPTION) determine
the prescaler assignment and prescale ratio.
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer, respectively (Figure 7-6). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. Note that there is only one prescaler
available which is mutually exclusive between the
Timer0 module and the Watchdog Timer. Thus, a
prescaler assignment for the Timer0 module means
that there is no prescaler for the Watchdog Timer and
vice-versa.
FIGURE 7-6:
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (i.e., CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer. The
prescaler is not readable or writable.
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
CLKOUT (= FOSC/4)
0
T0CKI
pin
8
M
U
X
1
M
U
X
0
1
SYNC
2
Cycles
TMR0 reg
T0SE
T0CS
0
Watchdog
Timer
1
M
U
X
Set flag bit T0IF
on Overflow
PSA
8-bit Prescaler
8
8-to-1MUX
PS
PSA
WDT Enable bit
1
0
MUX
PSA
WDT
Time-out
Note: T0SE, T0CS, PSA, PS are bits in the OPTION register.
DS40182D-page 38
1998-2013 Microchip Technology Inc.
PIC16CE62X
7.3.1
SWITCHING PRESCALER ASSIGNMENT
To change prescaler from the WDT to the TMR0
module, use the sequence shown in Example 7-2. This
precaution must be taken even if the WDT is disabled.
The prescaler assignment is fully under software
control (i.e., it can be changed “on-the-fly” during
program execution). To avoid an unintended device
RESET,
the
following
instruction
sequence
(Example 7-1) must be executed when changing the
prescaler assignment from Timer0 to WDT.
EXAMPLE 7-2:
CHANGING PRESCALER
(WDTTIMER0)
CLRWDT
EXAMPLE 7-1:
CHANGING PRESCALER
(TIMER0WDT)
1.BCF
STATUS, RP0
2.CLRWDT
3.CLRF
4.BSF
5.MOVLW
6.MOVWF
TMR0
STATUS, RP0
'00101111’b
OPTION
7.CLRWDT
8.MOVLW '00101xxx’b
9.MOVWF OPTION
10.BCF
STATUS, RP0
TABLE 7-1:
Address
Name
01h
TMR0
;Skip if already in
; Bank 0
;Clear WDT
;Clear TMR0 & Prescaler
;Bank 1
;These 3 lines (5, 6, 7)
; are required only if
; desired PS are
; 000 or 001
;Set Postscaler to
; desired WDT rate
;Return to Bank 0
;Clear WDT and
;prescaler
BSF
MOVLW
STATUS, RP0
b'xxxx0xxx'
MOVWF
BCF
OPTION_REG
STATUS, RP0
;Select TMR0, new
;prescale value and
;clock source
REGISTERS ASSOCIATED WITH TIMER0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer0 module register
Value on:
POR
Value on
All Other
Resets
xxxx xxxx uuuu uuuu
0Bh/8Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
81h
OPTION
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 1111 1111
85h
TRISA
—
—
—
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
---1 1111 ---1 1111
Legend: — = Unimplemented locations, read as ‘0’, x = unknown, u = unchanged.
Note:
Shaded bits are not used by TMR0 module.
1998-2013 Microchip Technology Inc.
DS40182D-page 39
PIC16CE62X
NOTES:
DS40182D-page 40
1998-2013 Microchip Technology Inc.
PIC16CE62X
8.0
COMPARATOR MODULE
The comparator module contains two analog
comparators. The inputs to the comparators are
multiplexed with the RA0 through RA3 pins. The
on-chip voltage reference (Section 9.0) can also be an
input to the comparators.
REGISTER 8-1:
R-0
C2OUT
bit7
The CMCON register, shown in Register 8-1, controls
the comparator input and output multiplexers. A block
diagram of the comparator is shown in Figure 8-1.
CMCON REGISTER (ADDRESS 1Fh)
R-0
C1OUT
U-0
—
U-0
—
bit 7:
C2OUT: Comparator 2 output
1 = C2 VIN+ > C2 VIN–
0 = C2 VIN+ < C2 VIN–
bit 6:
C1OUT: Comparator 1 output
1 = C1 VIN+ > C1 VIN–
0 = C1 VIN+ < C1 VIN–
R/W-0
CIS
R/W-0
CM2
R/W-0
CM1
R/W-0
CM0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 5-4: Unimplemented: Read as '0'
bit 3:
CIS: Comparator Input Switch
When CM: = 001:
1 = C1 VIN– connects to RA3
0 = C1 VIN– connects to RA0
When CM = 010:
1 = C1 VIN– connects to RA3
C2 VIN– connects to RA2
0 = C1 VIN– connects to RA0
C2 VIN– connects to RA1
bit 2-0: CM: Comparator mode
Figure 8-1.
1998-2013 Microchip Technology Inc.
DS40182D-page 41
PIC16CE62X
8.1
Comparator Configuration
There are eight modes of operation for the
comparators. The CMCON register is used to select
the mode. Figure 8-1 shows the eight possible modes.
The TRISA register controls the data direction of the
comparator pins for each mode. If the comparator
FIGURE 8-1:
RA0/AN0
RA3/AN3
RA1/AN1
RA2/AN2
mode is changed, the comparator output level may not
be valid for the specified mode change delay shown
in Table 13-1.
Note:
Comparator interrupts should be disabled
during a comparator mode change, otherwise a false interrupt may occur.
COMPARATOR I/O OPERATING MODES
A
VIN-
A
VIN+
A
VIN-
A
VIN+
+
Off
(Read as '0')
C1
+
Off
(Read as '0')
C2
RA0/AN0
RA3/AN3
RA1/AN1
RA2/AN2
D
VIN-
D
VIN+
D
VIN-
D
VIN+
+
C1
Off
(Read as '0')
C2
Off
(Read as '0')
+
CM = 000
Comparators Reset
RA0/AN0
RA3/AN3
RA1/AN1
RA2/AN2
A
A
VINVIN+
A
VIN-
A
VIN+
CM = 111
Comparators Off
+
C1
C1OUT
+
C2
C2OUT
RA0/AN0 A
CIS=0 VIN-
RA3/AN3 A
CIS=1 VIN+
RA1/AN1 A
CIS=0 VIN-
RA2/AN2 A
CIS=1 VIN+
+
RA0/AN0
RA3/AN3
RA1/AN1
RA2/AN2
A
VIN-
+
D
VIN+
A
VIN-
A
VIN+
+
C1
C1OUT
+
RA0/AN0
RA3/AN3
C2
C2OUT
CM = 011
C2
C2OUT
From VREF Module
Four Inputs Multiplexed to
Two Comparators
-
C1OUT
-
CM = 100
Two Independent Comparators
C1
RA1/AN1
A
VIN-
D
VIN+
A
VIN-
A
VIN+
RA2/AN2
RA4 Open Drain
CM = 010
+
C1
C1OUT
C2
C2OUT
+
CM = 110
Two Common Reference Comparators
Two Common Reference Comparators with Outputs
RA0/AN0
RA3/AN3
RA1/AN1
RA2/AN2
D
VIN-
D
VIN+
A
VIN-
A
VIN+
+
C1
Off
(Read as '0')
RA0/AN0
RA3/AN3
+
C2
C2OUT
RA1/AN1
RA2/AN2
A
CIS=0
VINCIS=1
VIN+
-
A
VIN-
-
A
VIN+
A
+
+
CM = 101
One Independent Comparator
C1
C1OUT
C2
C2OUT
CM = 001
Three Inputs Multiplexed to
Two Comparators
A = Analog Input, Port Reads Zeros Always
D = Digital Input
CIS = CMCON, Comparator Input Switch
DS40182D-page 42
1998-2013 Microchip Technology Inc.
PIC16CE62X
The code example in Example 8-1 depicts the steps
required to configure the comparator module. RA3 and
RA4 are configured as digital output. RA0 and RA1 are
configured as the V- inputs and RA2 as the V+ input to
both comparators.
EXAMPLE 8-1:
INITIALIZING
COMPARATOR MODULE
BCF
CALL
MOVF
BCF
BSF
BSF
BCF
BSF
BSF
0X20
;Init flag register
;Init PORTA
;Move comparator contents to W
;Mask comparator bits
;Store bits in flag register
;Init comparator mode
;CM = 011
;Select Bank1
;Initialize data direction
;Set RA as inputs
;RA as outputs
;TRISA always read ‘0’
STATUS,RP0 ;Select Bank 0
DELAY 10
;10s delay
CMCON,F
;Read CMCON to end change condition
PIR1,CMIF
;Clear pending interrupts
STATUS,RP0 ;Select Bank 1
PIE1,CMIE
;Enable comparator interrupts
STATUS,RP0 ;Select Bank 0
INTCON,PEIE ;Enable peripheral interrupts
INTCON,GIE ;Global interrupt enable
8.2
Comparator Operation
8.3
An external or internal reference signal may be used
depending on the comparator operating mode. The
analog signal that is present at VIN– is compared to the
signal at VIN+, and the digital output of the comparator
is adjusted accordingly (Figure 8-2).
FIGURE 8-2:
FLAG_REG EQU
CLRF
FLAG_REG
CLRF
PORTA
MOVF
CMCON,W
ANDLW
0xC0
IORWF
FLAG_REG,F
MOVLW
0x03
MOVWF
CMCON
BSF
STATUS,RP0
MOVLW
0x07
MOVWF
TRISA
A single comparator is shown in Figure 8-2 along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN–, the output of the
comparator is a digital low level. When the analog input
at VIN+ is greater than the analog input VIN–, the output
of the comparator is a digital high level. The shaded
areas of the output of the comparator in Figure 8-2
represent the uncertainty due to input offsets and
response time.
1998-2013 Microchip Technology Inc.
Comparator Reference
VIN+
VIN–
SINGLE COMPARATOR
+
–
Output
VVININ–
–
VVININ+
+
Output
Output
8.3.1
EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the
comparator module can be configured to have the comparators operate from the same or different reference
sources. However, threshold detector applications may
require the same reference. The reference signal must
be between VSS and VDD and can be applied to either
pin of the comparator(s).
8.3.2
INTERNAL REFERENCE SIGNAL
The comparator module also allows the selection of an
internally generated voltage reference for the
comparators. Section 13, Instruction Sets, contains a
detailed description of the Voltage Reference Module
that provides this signal. The internal reference signal
is used when the comparators are in mode
CM=010 (Figure 8-1). In this mode, the internal
voltage reference is applied to the VIN+ pin of both
comparators.
DS40182D-page 43
PIC16CE62X
8.4
Comparator Response Time
8.5
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output has a valid level. If the internal reference is changed, the maximum delay of the internal
voltage reference must be considered when using the
comparator outputs, otherwise the maximum delay of
the comparators should be used (Table 13-1 ).
Comparator Outputs
The comparator outputs are read through the CMCON
register. These bits are read only. The comparator
outputs may also be directly output to the RA3 and RA4
I/O pins. When the CM = 110, multiplexors in the
output path of the RA3 and RA4 pins will switch and the
output of each pin will be the unsynchronized output of
the comparator. The uncertainty of each of the
comparators is related to the input offset voltage and
the response time given in the specifications.
Figure 8-3 shows the comparator output block diagram.
The TRISA bits will still function as an output
enable/disable for the RA3 and RA4 pins while in this
mode.
Note 1: When reading the PORT register, all pins
configured as analog inputs will read as
a ‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
2: Analog levels on any pin that is defined
as a digital input may cause the input
buffer to consume more current than is
specified.
FIGURE 8-3:
COMPARATOR OUTPUT BLOCK DIAGRAM
Port Pins
MULTIPLEX
+
-
To RA3 or
RA4 Pin
Data
Bus
Q
D
RD CMCON
Set
CMIF
Bit
EN
D
Q
From
Other
Comparator
EN
CL
RD CMCON
NRESET
DS40182D-page 44
1998-2013 Microchip Technology Inc.
PIC16CE62X
8.6
Comparator Interrupts
wake-up the device from SLEEP mode when enabled.
While the comparator is powered-up, higher sleep
currents than shown in the power down current
specification will occur. Each comparator that is
operational will consume additional current as shown in
the comparator specifications. To minimize power
consumption while in SLEEP mode, turn off the
comparators, CM = 111, before entering sleep. If
the device wakes-up from sleep, the contents of the
CMCON register are not affected.
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON, to
determine the actual change that has occurred. The
CMIF bit, PIR1, is the comparator interrupt flag.
The CMIF bit must be reset by clearing ‘0’. Since it is
also possible to write a '1' to this register, a simulated
interrupt may be initiated.
8.8
The CMIE bit (PIE1) and the PEIE bit
(INTCON) must be set to enable the interrupt. In
addition, the GIE bit must also be set. If any of these
bits are clear, the interrupt is not enabled, though the
CMIF bit will still be set if an interrupt condition occurs.
Note:
A device reset forces the CMCON register to its reset
state. This forces the comparator module to be in the
comparator reset mode, CM = 000. This ensures
that all potential inputs are analog inputs. Device current is minimized when analog inputs are present at
reset time. The comparators will be powered-down
during the reset interval.
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR1)
interrupt flag may not get set.
8.9
The user, in the interrupt service routine, can clear the
interrupt in the following manner:
a)
b)
Comparator Operation During SLEEP
When a comparator is active and the device is placed
in SLEEP mode, the comparator remains active and
the interrupt is functional if enabled. This interrupt will
FIGURE 8-4:
Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 8-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up may occur. A
maximum
source
impedance
of
10 k
is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
Any read or write of CMCON. This will end the
mismatch condition.
Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition, and
allow flag bit CMIF to be cleared.
8.7
Effects of a RESET
ANALOG INPUT MODEL
VDD
VT = 0.6V
RS < 10K
RIC
AIN
VA
CPIN
5 pF
VT = 0.6V
ILEAKAGE
±500 nA
VSS
Legend
CPIN
VT
ILEAKAGE
RIC
RS
VA
1998-2013 Microchip Technology Inc.
= Input capacitance
= Threshold voltage
= Leakage current at the pin due to various junctions
= Interconnect resistance
= Source impedance
= Analog voltage
DS40182D-page 45
PIC16CE62X
TABLE 8-1:
Address
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR
Value on
All Other
Resets
1Fh
CMCON
C2OUT
C1OUT
—
—
CIS
CM2
CM1
CM0
00-- 0000 00-- 0000
9Fh
VRCON
VREN
VROE
VRR
—
VR3
VR2
VR1
VR0
000- 0000 000- 0000
0Bh
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
PIR1
—
CMIF
—
—
—
—
—
—
-0-- ---- -0-- ----
8Ch
PIE1
—
CMIE
—
—
—
—
—
—
-0-- ---- -0-- ----
85h
TRISA
—
—
—
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
---1 1111 ---1 1111
Legend: - = Unimplemented, read as "0", x = Unknown, u = unchanged
DS40182D-page 46
1998-2013 Microchip Technology Inc.
PIC16CE62X
9.0
VOLTAGE REFERENCE
MODULE
9.1
The Voltage Reference can output 16 distinct voltage
levels for each range.
The Voltage Reference is a 16-tap resistor ladder
network that provides a selectable voltage reference.
The resistor ladder is segmented to provide two ranges
of VREF values and has a power-down function to
conserve power when the reference is not being used.
The VRCON register controls the operation of the
reference as shown in Register 9-1. The block diagram
is given in Figure 9-1.
REGISTER 9-1:
R/W-0
VREN
bit7
Configuring the Voltage Reference
The equations used to calculate the output of the
Voltage Reference are as follows:
if VRR = 1: VREF = (VR/24) x VDD
if VRR = 0: VREF = (VDD x 1/4) + (VR/32) x VDD
The setting time of the Voltage Reference must be
considered when changing the VREF output
(Table 13-1). Example 9-1 shows an example of how to
configure the Voltage Reference for an output voltage
of 1.25V with VDD = 5.0V.
VRCON REGISTER (ADDRESS 9Fh)
R/W-0
VROE
R/W-0
VRR
U-0
—
R/W-0
VR3
R/W-0
VR2
bit 7:
VREN: VREF Enable
1 = VREF circuit powered on
0 = VREF circuit powered down, no IDD drain
bit 6:
VROE: VREF Output Enable
1 = VREF is output on RA2 pin
0 = VREF is disconnected from RA2 pin
bit 5:
VRR: VREF Range selection
1 = Low Range
0 = High Range
bit 4:
Unimplemented: Read as '0'
R/W-0
VR1
R/W-0
VR0
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit 3-0: VR: VREF value selection 0 VR [3:0] 15
when VRR = 1: VREF = (VR/ 24) * VDD
when VRR = 0: VREF = 1/4 * VDD + (VR/ 32) * VDD
FIGURE 9-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages
VREN
8R
R
R
R
R
8R
VRR
VR3
VREF
(From VRCON)
16-1 Analog Mux
VR0
Note:
R is defined in Table 13-2.
1998-2013 Microchip Technology Inc.
DS40182D-page 47
PIC16CE62X
EXAMPLE 9-1:
MOVLW
VOLTAGE REFERENCE
CONFIGURATION
0x02
; 4 Inputs Muxed
MOVWF
CMCON
; to 2 comps.
BSF
STATUS,RP0
; go to Bank 1
MOVLW
0x07
; RA3-RA0 are
MOVWF
TRISA
; outputs
MOVLW
0xA6
; enable VREF
MOVWF
VRCON
; low range
BCF
STATUS,RP0
; go to Bank 0
CALL
DELAY10
; 10s delay
9.4
A device reset disables the Voltage Reference by clearing bit VREN (VRCON). This reset also disconnects
the reference from the RA2 pin by clearing bit VROE
(VRCON) and selects the high voltage range by
clearing bit VRR (VRCON). The VREF value select
bits, VRCON, are also cleared.
9.5
Voltage Reference Accuracy/Error
The full range of VSS to VDD cannot be realized due to
the construction of the module. The transistors on the
top and bottom of the resistor ladder network
(Figure 9-1) keep VREF from approaching VSS or VDD.
The Voltage Reference is VDD derived and therefore,
the VREF output changes with fluctuations in VDD. The
absolute accuracy of the Voltage Reference can be
found in Table 13-2.
9.3
Connection Considerations
The
Voltage
Reference
Module
operates
independently of the comparator module. The output of
the reference generator may be connected to the RA2
pin if the TRISA bit is set and the VROE bit,
VRCON, is set. Enabling the Voltage Reference
output onto the RA2 pin with an input signal present will
increase current consumption. Connecting RA2 as a
digital output with VREF enabled will also increase
current consumption.
; set VR=6
9.2
Effects of a Reset
The RA2 pin can be used as a simple D/A output with
limited drive capability. Due to the limited drive
capability, a buffer must be used in conjunction with the
Voltage Reference output for external connections to
VREF. Figure 9-2 shows an example buffering
technique.
Operation During Sleep
When the device wakes up from sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the VRCON register are not affected. To minimize
current consumption in SLEEP mode, the Voltage
Reference should be disabled.
FIGURE 9-2:
VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
R(1)
VREF
Module
RA2
•
+
–
•
VREF Output
Voltage
Reference
Output
Impedance
Note 1:
R is dependent upon the Voltage Reference Configuration VRCON and VRCON.
TABLE 9-1:
REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value On
POR / BOD
Value On
All Other
Resets
VRCON
VREN
VROE
VRR
—
VR3
VR2
VR1
VR0
000- 0000
000- 0000
1Fh
CMCON
C2OUT
C1OUT
—
—
CIS
CM2
CM1
CM0
00-- 0000
00-- 0000
85h
TRISA
—
—
—
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
---1 1111
---1 1111
Address
Name
9Fh
Legend: - = Unimplemented, read as "0"
DS40182D-page 48
1998-2013 Microchip Technology Inc.
PIC16CE62X
10.0
SPECIAL FEATURES OF THE
CPU
Special circuits to deal with the needs of real time applications are what sets a microcontroller apart from other
processors. The PIC16CE62X family has a host of
such features intended to maximize system reliability,
minimize cost through elimination of external components, provide power saving operating modes and offer
code protection.
These are:
1.
2.
3.
4.
5.
6.
7.
8.
OSC selection
Reset
Power-on Reset (POR)
Power-up Timer (PWRT)
Oscillator Start-Up Timer (OST)
Brown-out Reset (BOD)
Interrupts
Watchdog Timer (WDT)
SLEEP
Code protection
ID Locations
In-circuit serial programming
1998-2013 Microchip Technology Inc.
The PIC16CE62X has a Watchdog Timer which is
controlled by configuration bits. It runs off its own RC
oscillator for added reliability. There are two timers that
offer necessary delays on power-up. One is the
Oscillator Start-up Timer (OST), intended to keep the
chip in reset until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only, and is
designed to keep the part in reset while the power
supply stabilizes. There is also circuitry to reset the
device if a brown-out occurs, which provides at least a
72 ms reset. With these three functions on-chip, most
applications need no external reset circuitry.
The SLEEP mode is designed to offer a very low
current power-down mode. The user can wake-up from
SLEEP through external reset, Watchdog Timer
wake-up or through an interrupt. Several oscillator
options are also made available to allow the part to fit
the application. The RC oscillator option saves system
cost, while the LP crystal option saves power. A set of
configuration bits are used to select various options.
DS40182D-page 49
PIC16CE62X
10.1
Configuration Bits
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in
program memory location 2007h.
The user will note that address 2007h is beyond
the user program memory space. In fact, it belongs
to the special test/configuration memory space
(2000h – 3FFFh), which can be accessed only during
programming.
REGISTER 10-1: CONFIGURATION WORD
CP1
CP0(2)
CP1
CP0(2)
CP1
CP0(2)
—
BODEN(1) CP1
bit13
CP0(2) PWRTE(1) WDTE F0SC1
F0SC0
bit0
CONFIG
Address
REGISTER: 2007h
bit 13-8, CP1:CP0 Pairs: Code protection bit pairs(2)
5-4: Code protection for 2K program memory
11 = Program memory code protection off
10 = 0400h-07FFh code protected
01 = 0200h-07FFh code protected
00 = 0000h-07FFh code protected
Code protection for 1K program memory
11 = Program memory code protection off
10 =Program memory code protection on
01 = 0200h-03FFh code protected
00 = 0000h-03FFh code protected
Code protection for 0.5K program memory
11 = Program memory code protection off
10 = Program memory code protection off
01 = Program memory code protection off
00 = 0000h-01FFh code protected
bit 7:
Unimplemented: Read as '1'
bit 6:
BODEN: Brown-out Reset Enable bit (1)
1 = BOD enabled
0 = BOD disabled
bit 3:
PWRTE: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2:
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0:
FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.
2: All of the CP pairs have to be given the same value to enable the code protection scheme listed.
DS40182D-page 50
1998-2013 Microchip Technology Inc.
PIC16CE62X
10.2
Oscillator Configurations
10.2.1
OSCILLATOR TYPES
LP
XT
HS
RC
10.2.2
Low Power Crystal
Crystal/Resonator
High Speed Crystal/Resonator
Resistor/Capacitor
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
Mode
FIGURE 10-1: CRYSTAL OPERATION
(OR CERAMIC RESONATOR)
(HS, XT OR LP OSC
CONFIGURATION)
OSC1
C1
To Internal Logic
SLEEP
RF
OSC2
RS
C2 see Note
Note:
A series resistor may be required for AT
strip cut crystals.
OSC1
OSC2
455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF
15 - 68 pF
15 - 68 pF
68 - 100 pF
15 - 68 pF
15 - 68 pF
HS
8.0 MHz
16.0 MHz
10 - 68 pF
10 - 22 pF
10 - 68 pF
10 - 22 pF
These values are for design guidance only. See notes at
bottom of page.
TABLE 10-2:
Osc Type
LP
XT
HS
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR,
PIC16CE62X
Crystal
Freq
Cap. Range
C1
Cap. Range
C2
33 pF
32 kHz
33 pF
200 kHz
15 pF
15 pF
200 kHz
47-68 pF
47-68 pF
1 MHz
15 pF
15 pF
15 pF
4 MHz
15 pF
4 MHz
15 pF
15 pF
8 MHz
15-33 pF
15-33 pF
20 MHz
15-33 pF
15-33 pF
These values are for design guidance only. See notes at
bottom of page.
1.
Recommended values of C1 and C2 are identical to
the ranges tested table.
2.
Higher capacitance increases the stability of oscillator,
but also increases the start-up time.
3.
Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal
manufacturer for appropriate values of external components.
4.
Rs may be required in HS mode, as well as XT mode,
to avoid overdriving crystals with low drive level specification.
PIC16CE62X
See Table 10-1 and Table 10-2 for recommended values
of C1 and C2.
Freq
XT
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1 and OSC2 pins to establish
oscillation (Figure 10-1). The PIC16CE62X oscillator
design requires the use of a parallel cut crystal. Use of
a series cut crystal may give a frequency out of the
crystal manufacturers specifications. When in XT, LP or
HS modes, the device can have an external clock
source to drive the OSC1 pin (Figure 10-2).
XTAL
CERAMIC RESONATORS,
PIC16CE62X
Ranges Tested:
The PIC16CE62X can be operated in four different
oscillator options. The user can program two
configuration bits (FOSC1 and FOSC0) to select one of
these four modes:
•
•
•
•
TABLE 10-1:
FIGURE 10-2: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
Clock From
ext. system
OSC1
PIC16CE62X
Open
OSC2
1998-2013 Microchip Technology Inc.
DS40182D-page 51
PIC16CE62X
10.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
Either a prepackaged oscillator can be used or a simple
oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and
better stability. A well-designed crystal oscillator will
provide good performance with TTL gates. Two types of
crystal oscillator circuits can be used; one with series
resonance or one with parallel resonance.
Figure 10-3 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the
fundamental frequency of the crystal. The 74AS04
inverter performs the 180 phase shift that a parallel
oscillator requires. The 4.7 k resistor provides the
negative feedback for stability. The 10 k
potentiometers bias the 74AS04 in the linear region.
This could be used for external oscillator designs.
FIGURE 10-3: EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
To Other
Devices
10k
74AS04
4.7k
PIC16CE62X
CLKIN
74AS04
RC OSCILLATOR
For timing insensitive applications the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (Rext) and capacitor (Cext) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency,
especially for low Cext values. The user also needs to
take into account variation due to tolerance of external
R and C components used. Figure 10-5 shows how the
R/C combination is connected to the PIC16CE62X. For
Rext values below 2.2 k, the oscillator operation may
become unstable, or stop completely. For very high
Rext values (i.e., 1 M), the oscillator becomes
sensitive to noise, humidity and leakage. Thus, we
recommend to keep Rext between 3 k and 100 k.
Although the oscillator will operate with no external
capacitor (Cext = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or
package lead frame capacitance.
See Section 14.0 for RC frequency variation from part
to part due to normal process variation. The variation is
larger for larger R (since leakage current variation will
affect RC frequency more for large R) and for smaller C
(since variation of input capacitance will affect RC frequency more).
10k
XTAL
10k
20 pF
10.2.4
20 pF
Figure 10-4 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a 180
phase shift in a series resonant oscillator circuit. The
330 k resistors provide the negative feedback to bias
the inverters in their linear region.
See Section 14.0 for variation of oscillator frequency
due to VDD for given Rext/Cext values, as well as
frequency variation due to operating temperature for
given R, C, and VDD values.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin and can be used for test purposes or to synchronize other logic (Figure 3-2 for
waveform).
FIGURE 10-5: RC OSCILLATOR MODE
FIGURE 10-4: EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
VDD
PIC16CE62X
Rext
330
To other
Devices
330
74AS04
74AS04
74AS04
OSC1
Internal Clock
PIC16CE62X
CLKIN
0.1 F
Cext
VDD
FOSC/4 OSC2/CLKOUT
XTAL
DS40182D-page 52
1998-2013 Microchip Technology Inc.
PIC16CE62X
10.3
Reset
The PIC16CE62X differentiates between various kinds
of reset:
a)
b)
c)
d)
e)
f)
Power-on reset (POR)
MCLR reset during normal operation
MCLR reset during SLEEP
WDT reset (normal operation)
WDT wake-up (SLEEP)
Brown-out Reset (BOD)
state” on Power-on reset, MCLR reset, WDT reset and
MCLR reset during SLEEP. They are not affected by a
WDT wake-up, since this is viewed as the resumption
of normal operation. TO and PD bits are set or cleared
differently in different reset situations as indicated in
Table 10-4. These bits are used in software to determine the nature of the reset. See Table 10-6 for a full
description of reset states of all registers.
A simplified block diagram of the on-chip reset circuit is
shown in Figure 10-6.
Some registers are not affected in any reset condition.
Their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
The MCLR reset path has a noise filter to detect and
ignore small pulses. See Table 13-5 for pulse width
specification.
FIGURE 10-6: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR/
VPP Pin
WDT
Module
SLEEP
WDT
Time-out
Reset
VDD rise
detect
Power-on Reset
VDD
Brown-out
Reset
S
BODEN
OST/PWRT
OST
Chip_Reset
10-bit Ripple-counter
OSC1/
CLKIN
Pin
On-chip(1)
RC OSC
R
Q
PWRT
10-bit Ripple-counter
Enable PWRT
See Table 10-3 for time-out situations.
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
1998-2013 Microchip Technology Inc.
DS40182D-page 53
PIC16CE62X
10.4
10.4.1
Power-on Reset (POR), Power-up
Timer (PWRT), Oscillator Start-up
Timer (OST) and Brown-out Reset
(BOD)
The Power-Up Time delay will vary from chip-to-chip
and due to VDD, temperature and process variation.
See DC parameters for details.
POWER-ON RESET (POR)
The Oscillator Start-Up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
10.4.3
The on-chip POR circuit holds the chip in reset until
VDD has reached a high enough level for proper operation. To take advantage of the POR, just tie the MCLR
pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on
Reset. A maximum rise time for VDD is required. See
electrical specifications for details.
The OST time-out is invoked only for XT, LP and HS
modes and only on power-on reset or wake-up from
SLEEP.
10.4.4
The POR circuit does not produce an internal reset
when VDD declines.
BROWN-OUT RESET (BOD)
The PIC16CE62X members have on-chip Brown-out
Reset circuitry. A configuration bit, BOREN, can disable
(if clear/programmed) or enable (if set) the Brown-out
Reset circuitry. If VDD falls below 4.0V (refer to BVDD
parameter D005) for greater than parameter (TBOR) in
Table 13-5, the brown-out situation will reset the chip. A
reset won’t occur if VDD falls below 4.0V for less than
parameter (TBOR).
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, etc.) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating conditions are
met.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting”.
10.4.2
OSCILLATOR START-UP TIMER (OST)
On any reset (Power-on, Brown-out, Watch-dog, etc.)
the chip will remain in reset until VDD rises above BVDD.
The Power-up Timer will then be invoked and will keep
the chip in reset an additional 72 ms.
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms (nominal)
time-out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates on an internal RC
oscillator. The chip is kept in reset as long as PWRT is
active. The PWRT delay allows the VDD to rise to an
acceptable level. A configuration bit, PWRTE, can
disable (if set) or enable (if cleared or programmed) the
Power-up Timer. The Power-up Timer should always be
enabled when Brown-out Reset is enabled.
If VDD drops below BVDD while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be re-initialized. Once VDD
rises above BVDD, the Power-Up Timer will execute a
72 ms reset. The Power-up Timer should always be
enabled when Brown-out Reset is enabled. Figure 10-7
shows typical Brown-out situations.
FIGURE 10-7: BROWN-OUT SITUATIONS
VDD
Internal
Reset
BVDD
72 ms
VDD
Internal
Reset
BVDD
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