PIC18F27/47/57Q84
28/40/44/48-Pin, Low-Power, High-Performance
Microcontroller with XLP Technology
Introduction
The PIC18-Q84 microcontroller family is available in 28/40/44/48-pin devices for many automotive and industrial
applications. The many communication peripherals found on the product family, such as Controller Area Network
(CAN), Serial Peripheral Interface (SPI), Inter-Integrated Circuit (I2C), two Universal Asynchronous Receiver
Transmitters (UARTs), can handle a wide range of wired and wireless (using external modules) communication
protocols for intelligent applications. Combined with the Core Independent Peripherals (CIPs) integration capabilities,
this capacity enables functions for motor control, power supply, sensor, signal and user interface applications.
Additionally, this family includes a 12-bit Analog-to-Digital Converter (ADC) with Computation and Context Switching
extensions for automated signal analysis to reduce the complexity of the application.
PIC18-Q84 Family Types
JTAG Boundary Scan
Temperature Indicator
Peripheral Module Disable
Vectored Interrupts
32-Bit CRC with Scanner
Windowed Watchdog Timer
Direct Memory Access (DMA)
UART/
UART with Protocol Support
SPI/I2C
CAN FD
High-Low Voltage Detect
8-Bit DAC
Comparator/
Zero-Cross Detect
12-Bit ADC w/Computation and Context Switching (channels)
Configurable Logic Cell
16-Bit Universal Timer
Numerically Controlled
Oscillator
Signal Measurement Timer
16-Bit Dual PWM/
CCP
Complimentary Waveform
Generator
8-Bit Timer with HLT/
16-Bit Timers
I/O Pins/
Peripheral Pin Select
Memory Access Partition/
Device Information Area
Data EEPROM
(bytes)
Data SRAM
(bytes)
Device
Program Memory Flash
(bytes)
Table 1. Devices Included in This Data Sheet
PIC18F27Q84
128k
12800
1024
Y/Y
25/Y
3/3
4/3
3
1
2
3
8
24
1
2/1
1
Y
2/1
3/2
8
Y
Y
Y
Y
Y
Y
PIC18F47Q84
128k
12800
1024
Y/Y
36/Y
3/3
4/3
3
1
2
3
8
35
1
2/1
1
Y
2/1
3/2
8
Y
Y
Y
Y
Y
Y
PIC18F57Q84
128k
12800
1024
Y/Y
44/Y
3/3
4/3
3
1
2
3
8
43
1
2/1
1
Y
2/1
3/2
8
Y
Y
Y
Y
Y
Y
Features
•
•
•
C Compiler Optimized RISC Architecture
Operating Speed:
– DC – 64 MHz clock input
– 62.5 ns minimum instruction cycle
Eight Direct Memory Access (DMA) Controllers:
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 1
PIC18F27/47/57Q84
•
•
•
•
•
•
•
– Data transfers to SFR/GPR spaces from either Program Flash Memory, Data EEPROM or SFR/GPR
spaces
– User programmable source and destination sizes
– Hardware and software triggered data transfers
Vectored Interrupt Capability:
– Selectable high/low priority
– Fixed interrupt latency of three instruction cycles
– Programmable vector table base address
– Backwards compatible with previous interrupt capabilities
128-Level Deep Hardware Stack
Low-Current Power-on Reset (POR)
Configurable Power-up Timer (PWRT)
Brown-out Reset (BOR)
Low-Power BOR (LPBOR) Option
Windowed Watchdog Timer (WWDT):
– Watchdog Reset on too long or too short interval between watchdog clear events
– Variable prescaler selection
– Variable window size selection
Memory
•
•
•
•
•
•
•
•
Up to 128 KB of Program Flash Memory
Up to 13 KB of Data SRAM Memory
1024 Bytes Data EEPROM
Memory Access Partition: The Program Flash Memory can be partitioned into:
– Application Block
– Boot Block
– Storage Area Flash (SAF) Block
Programmable Code Protection and Write Protection
Device Information Area (DIA) Stores:
– Temperature indicator factory calibrated data
– Fixed Voltage Reference measurement data
– Microchip unique identifier
Device Characteristics Information (DCI) Area Stores:
– Program/erase row sizes
– Pin count details
– EEPROM size
Direct, Indirect and Relative Addressing modes
Operating Characteristics
•
•
Operating Voltage Range:
– 1.8V to 5.5V
Temperature Range:
– Industrial: -40°C to 85°C
– Extended: -40°C to 125°C
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 2
PIC18F27/47/57Q84
Power-Saving Functionality
•
•
•
•
•
Doze: CPU and Peripherals Running at Different Cycle Rates (typically CPU is lower)
Idle: CPU Halted While Peripherals Operate
Sleep: Lowest Power Consumption
Peripheral Module Disable (PMD):
– Ability to selectively disable hardware module to minimize active power consumption of unused peripherals
Low-Power Mode Features:
– Sleep: < 1µA typical @ 3V
– Operating Current:
• 48µA @ 32 kHz, 3V, typical
Digital Peripherals
•
•
•
•
•
•
•
•
•
•
•
•
Four 16-Bit Pulse-Width Modulators (PWM):
– Dual outputs for each PWM module
– Integrated 16-bit timer/counter
– Double-buffered user registers for duty cycles
– Right/Left/Center/Variable aligned modes of operation
– Multiple clock and Reset signal selections
Three 16-Bit Timers (TMR0/1/3)
Three 8-Bit Timers (TMR2/4/6) with Hardware Limit Timer (HLT)
Two Universal Timers (TMRU16A/16B):
– New Timer modules with features of TMR0/TMR1/TMR2 (Gate, Hardware Limit)
– Two 16-bit timers can be chained together to create a combined 32-bit timer
Eight Configurable Logic Cell (CLC):
– Integrated combinational and sequential logic
Three Complimentary Waveform Generators (CWG):
– Rising and falling edge dead-band control
– Full-bridge, half-bridge, 1-channel drive
– Multiple signal sources
– Programmable dead band
– Fault-shutdown input
Three Capture/Compare/PWM (CCP) Modules:
– 16-bit resolution for Capture/Compare modes
– 10-bit resolution for PWM mode
Three Numerically Controlled Oscillators (NCO):
– Generates true linear frequency control and increased frequency resolution
– Input clock up to 64 MHz
Signal Measurement Timer (SMT):
– 24-bit timer/counter with prescaler
– Several modes of operation like Time-of-Flight, Period and Duty Cycle measurement, etc.
Data Signal Modulator (DSM):
– Multiplex two carrier clocks, with glitch prevention feature
– Multiple sources for each carrier
Programmable CRC with Memory Scan:
– Reliable data/program memory monitoring for Fail-Safe operation (e.g., Class B)
– Calculate 16-bit CRC over any portion of Program Flash Memory
CAN Flexible Data-Rate (FD) Module:
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 3
PIC18F27/47/57Q84
•
•
•
•
•
– Functional in CAN FD or CAN 2.0B modes
– One dedicated transmit FIFO
– Three programmable transmit/receive FIFOs
– One transmit event queue
– 12 acceptance masks/filters
Five UART Modules:
– LIN host and client, DMX mode, DALI gear and device protocols
– Asynchronous UART, RS-232, RS-485 compatible
– Automatic and user timed BREAK period generation
– Automatic checksums
– Programmable 1, 1.5, and two Stop bits
– Wake-up on BREAK reception
– DMA compatible
Two SPI Modules:
– Configurable length bytes
– Arbitrary length data packets
– Transmit-without-receive and receive-without-transmit options
– Transfer byte counter
– Separate transmit and receive buffers with 2-byte FIFO and DMA capabilities
One I2C module, SMBus, PMBus™ Compatible:
– 7-bit and 10-bit Addressing modes with Address Masking modes
– Dedicated address, transmit and receive buffers and DMA capabilities
– Bus collision detection with arbitration
– Bus time-out detection and handling
– I2C, SMBus 2.0 and SMBus 3.0, and 1.8V input level selections
– Multi-Host mode, including self-addressing
Device I/O Port Features:
– 25 I/O pins (PIC18F26/27Q84)
– 36 I/O pins (PIC18F46/47Q84)
– 44 I/O pins (PIC18F56/57Q84)
– Individually programmable I/O direction, open-drain, slew rate and weak pull-up control
– Interrupt-on-change on most pins
– Three programmable external interrupt pins
Peripheral Pin Select (PPS):
– Enables pin mapping of digital I/O
Analog Peripherals
•
Analog-to-Digital Converter with Computation and Context Switching:
– Up to 43 external channels
– Automated math functions on input signals:
• Averaging, filter calculations, oversampling and threshold comparison
– Four Separate Contexts (settings and results) saved and accessible separately
– Contexts can be accessed through firmware or DMA
– Operates in Sleep
– Five internal analog channels
– Hardware Capacitive Voltage Divider (CVD) Support:
• Adjustable sample and hold capacitor array
• Guard ring digital output drive
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 4
PIC18F27/47/57Q84
•
•
•
•
•
Automates touch sampling and reduces software size and CPU usage when touch or proximity
sensing is required
8-Bit Digital-to-Analog Converter (DAC):
– Buffered output available on two I/O pins
– Internal connections to ADC and Comparators
Two Comparators (CMP):
– Four external inputs
– Configurable output polarity
– External output via Peripheral Pin Select
Zero-Cross Detect (ZCD):
– Detect when AC signal on pin crosses ground
Voltage Reference:
– Fixed Voltage Reference with 1.024V, 2.048V and 4.096V output levels
– Internal connections to ADC, Comparator and DAC
Clocking Structure
•
•
•
•
•
•
High-Precision Internal Oscillator Block (HFINTOSC):
– Selectable frequencies up to 64 MHz
– ±1% at calibration
– Active Clock Tuning of HFINTOSC for better accuracy
32 kHz Low-Power Internal Oscillator (LFINTOSC)
External 32 kHz Crystal Oscillator (SOSC)
External High-frequency Oscillator Block:
– Three crystal/resonator modes
– Digital Clock Input mode
– 4x PLL with external sources
Fail-Safe Clock Monitor:
– Allows for operational recovery if external clock stops
Oscillator Start-up Timer (OST):
– Ensures stability of crystal oscillator sources
Programming/Debug Features
•
•
•
In-Circuit Serial Programming™ (ICSP™) via Two Pins
In-Circuit Debug (ICD) with Three Breakpoints via Two Pins
Debug Integrated On-Chip
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 5
PIC18F27/47/57Q84
Table of Contents
Introduction.....................................................................................................................................................1
PIC18-Q84 Family Types............................................................................................................................... 1
Features......................................................................................................................................................... 1
1.
Packages................................................................................................................................................ 9
2.
Pin Diagrams.........................................................................................................................................10
3.
Pin Allocation Tables............................................................................................................................. 14
4.
Guidelines for Getting Started with PIC18-Q84 Microcontrollers.......................................................... 19
5.
Register and Bit Naming Conventions.................................................................................................. 24
6.
Register Legend....................................................................................................................................26
7.
PIC18 CPU............................................................................................................................................27
8.
Device Configuration.............................................................................................................................45
9.
Memory Organization............................................................................................................................68
10. NVM - Nonvolatile Memory Module...................................................................................................... 99
11. VIC - Vectored Interrupt Controller Module......................................................................................... 125
12. OSC - Oscillator Module (With Fail-Safe Clock Monitor).................................................................... 206
13. CRC - Cyclic Redundancy Check Module with Memory Scanner.......................................................233
14. Resets................................................................................................................................................. 255
15. WWDT - Windowed Watchdog Timer..................................................................................................268
16. DMA - Direct Memory Access............................................................................................................. 279
17. Power-Saving Modes.......................................................................................................................... 317
18. PMD - Peripheral Module Disable.......................................................................................................326
19. I/O Ports.............................................................................................................................................. 337
20. IOC - Interrupt-on-Change.................................................................................................................. 353
21. PPS - Peripheral Pin Select Module................................................................................................... 359
22. CLC - Configurable Logic Cell.............................................................................................................373
23. CLKREF - Reference Clock Output Module........................................................................................394
24. TMR0 - Timer0 Module....................................................................................................................... 399
25. TMR1 - Timer1 Module with Gate Control...........................................................................................407
26. TMR2 - Timer2 Module....................................................................................................................... 424
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 6
PIC18F27/47/57Q84
27. SMT - Signal Measurement Timer...................................................................................................... 448
28. UTMR - Universal Timer Module.........................................................................................................474
29. CCP - Capture/Compare/PWM Module.............................................................................................. 513
30. Capture, Compare, and PWM Timers Selection................................................................................. 526
31. PWM - Pulse-Width Modulator with Compare.....................................................................................529
32. CWG - Complementary Waveform Generator Module........................................................................556
33. NCO - Numerically Controlled Oscillator Module................................................................................ 584
34. DSM - Data Signal Modulator Module.................................................................................................594
35. UART - Universal Asynchronous Receiver Transmitter with Protocol Support................................... 605
36. SPI - Serial Peripheral Interface Module.............................................................................................651
37. I2C - Inter-Integrated Circuit Module................................................................................................... 684
38. CAN FD - Controller Area Network, Flexible Data-Rate..................................................................... 770
39. JTAG Boundary Scan..........................................................................................................................876
40. HLVD - High/Low-Voltage Detect........................................................................................................ 883
41. FVR - Fixed Voltage Reference.......................................................................................................... 891
42. Temperature Indicator Module............................................................................................................ 895
43. ADC - Analog-to-Digital Converter with Computation and Context Module........................................ 900
44. DAC - Digital-to-Analog Converter Module......................................................................................... 954
45. CMP - Comparator Module................................................................................................................. 959
46. ZCD - Zero-Cross Detection Module...................................................................................................970
47. Instruction Set Summary.....................................................................................................................977
48. ICSP™ - In-Circuit Serial Programming™......................................................................................... 1062
49. Register Summary............................................................................................................................ 1065
50. Electrical Specifications.................................................................................................................... 1085
51. DC and AC Characteristics Graphs and Tables.................................................................................1114
52. Packaging Information....................................................................................................................... 1115
53. Appendix A: Revision History............................................................................................................ 1141
The Microchip Website............................................................................................................................. 1142
Product Change Notification Service........................................................................................................1142
Customer Support.................................................................................................................................... 1142
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 7
PIC18F27/47/57Q84
Product Identification System................................................................................................................... 1143
Microchip Devices Code Protection Feature............................................................................................ 1143
Legal Notice..............................................................................................................................................1144
Trademarks...............................................................................................................................................1144
Quality Management System................................................................................................................... 1145
Worldwide Sales and Service................................................................................................................... 1146
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 8
PIC18F27/47/57Q84
Packages
1.
Packages
Table 1-1. Packages
Device
PIC18F27Q84
28-pin 28-pin 28-pin
SPDIP SOIC SSOP
●
●
PIC18F47Q84
●
28-pin
VQFN
4x4x1
40-pin
PDIP
40-pin
VQFN
5x5x0.9
44-pin
TQFP
●
●
●
48-pin
VQFN
6x6x0.9
●
●
●
PIC18F57Q84
© 2021 Microchip Technology Inc.
48-pin
TQFP
7x7x1
Preliminary Datasheet
DS40002213D-page 9
PIC18F27/47/57Q84
Pin Diagrams
Pin Diagrams
Figure 2-1.
28-Pin SPDIP
28-Pin SSOP
28-Pin SOIC
MCLR/VPP/RE3
RA0
RA1
RA2
RA3
RA4
RA5
VSS
RA7
RA6
RC0
RC1
RC2
RC3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7/ICSPDAT
RB6/ICSPCLK
RB5
RB4
RB3
RB2
RB1
RB0
VDD
VSS
RC7
RC6
RC5
RC4
RA1
RA0
RE3/MCLR/VPP
RB7/ICSPDAT
RB6/ICSPCLK
RB5
RB4
Figure 2-2.
28-Pin VQFN
28 27 26 25 24 23 22
RA2
RA3
RA4
RA5
VSS
RA7
RA6
1
21 RB3
2
20 RB2
3
19 RB1
4
18 RB0
5
17 VDD
6
16 VSS
7
15 RC7
8
9 10 11 12 13 14
RC0
RC1
RC2
RC3
RC4
RC5
RC6
2.
Note: It is recommended that the exposed bottom pad be connected to VSS; however, it must not be the only VSS
connection to the device.
Figure 2-3.
40-Pin PDIP
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 10
PIC18F27/47/57Q84
Pin Diagrams
MCLR/VPP/RE3
RA0
RA1
RA2
RA3
RA4
RA5
RE0
RE1
RE2
VDD
VSS
RA7
RA6
RC0
RC1
RC2
RC3
RD0
RD1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7/ICSPDAT
RB6/ICSPCLK
RB5
RB4
RB3
RB2
RB1
RB0
VDD
VSS
RD7
RD6
RD5
RD4
RC7
RC6
RC5
RC4
RD3
RD2
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
Figure 2-4.
40-Pin VQFN
40 39 38 37 36 35 34 33 32 31
RC7
RD4
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
1
30 RC0
2
29 RA6
3
28
4
27
5
26
6
25
7
24
8
23
9
22
10
21
RA7
VSS
VDD
RE2
RE1
RE0
RA5
RA4
RB3
RB4
RB5
ICSPCLK/RB6
ICSPDAT/RB7
VPP/MCLR/RE3
RA0
RA1
RA2
RA3
11 12 13 14 15 16 17 18 19 20
Note: It is recommended that the exposed bottom pad be connected to VSS; however, it must not be the only VSS
connection to the device.
Figure 2-5.
44-Pin TQFP
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 11
PIC18F27/47/57Q84
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RC1
NC
Pin Diagrams
44 43 42 41 40 39 38 37 36 35 34
RC7
RD4
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
RB3
1
33
2
32
3
31
4
30
5
29
6
28
7
27
8
26
9
25
10
24
11
NC
RC0
RA6
RA7
VSS
VDD
RE2
RE1
RE0
RA5
RA4
23
NC
NC
RB4
RB5
ICSPCLK/RB6
ICSPDAT/RB7
VPP/MCLR/RE3
RA0
RA1
RA2
RA3
12 13 14 15 16 17 18 19 20 21 22
RF1
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RF3
RF2
Figure 2-6.
48-Pin VQFN
1
48 47 46 45 44 43 42 41 40 39 38 37
36 RF0
2
35 RC1
3
34
4
33
5
32
6
31
7
30
RB0
RB1
RB2
RB3
RF4
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
RC0
RA6
RA7
VSS
VDD
RE2
RE1
RE0
RA5
RA4
RA3
RF5
RF6
RF7
RB4
RB5
ICSPCLK/RB6
ICSPDAT/RB7
VPP/MCLR/RE3
RA0
RA1
RA2
RC7
RD4
RD5
RD6
RD7
VSS
VDD
Note: It is recommended that the exposed bottom pad be connected to VSS; however, it must not be the only VSS
connection to the device.
Figure 2-7.
48-Pin TQFP
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 12
PIC18F27/47/57Q84
1
48 47 46 45 44 43 42 41 40 39 38 37
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
12
26
© 2021 Microchip Technology Inc.
RF0
RC1
RC0
RA6
RA7
VSS
VDD
RE2
RE1
RE0
RA5
RA4
RA3
25
13 14 15 16 17 18 19 20 21 22 23 24
RF5
RF6
RF7
RB4
RB5
ICSPCLK/RB6
ICSPDAT/RB7
VPP/MCLR/RE3
RA0
RA1
RA2
RC7
RD4
RD5
RD6
RD7
VSS
VDD
RB0
RB1
RB2
RB3
RF4
RF1
RC6
RC5
RC4
RD3
RD2
RD1
RD0
RC3
RC2
RF3
RF2
Pin Diagrams
Preliminary Datasheet
DS40002213D-page 13
3.
28Pin
I/O(2)
SPDIP,
28Pin
SOIC,
VQFN
rotatethispage90
A/D
Reference
ZCD
Timers/SMT
16-Bit PWM/
CCP
CWG
—
—
—
—
—
—
—
—
—
—
—
C1IN1+
—
—
—
—
T0CKI(1)
Comparator
SPI
I2C
UART
DSM
IOC
Interrupt
CAN FD
CRC on Boot
JTAG
Basic
—
—
—
—
IOCA0
—
—
—
TMS
—
CLCIN5(1)
—
—
—
—
IOCA1
—
—
—
—
—
—
—
—
—
—
—
IOCA2
—
—
BOOTA2
—
—
—
—
—
—
—
—
MDCARL(1) IOCA3
—
—
—
—
—
—
—
—
SS2(1)
—
(1) IOCA4
CTS5(1) MDCARH
—
—
BOOTA4
—
—
—
SS1(1)
—
—
—
—
TCK
CLC
SSOP
2
27
ANA0
—
RA1
3
28
ANA1
—
RA2
4
1
ANA2
VREF- (DAC)
VREF- (ADC)
5
2
ANA3
RA4
6
3
ANA4
RA5
7
4
ANA5
C2IN0-
VREF+ (DAC)
VREF+ (ADC)
—
—
C2IN1-
CLCIN4(1)
CLCIN1(1)
C1IN1-
DAC1OUT1
RA3
CLCIN0(1)
C1IN0-
RA0
C1IN0+
C2IN0+
—
—
—
—
—
RX5(1)
MDSRC(1)
IOCA5
—
Preliminary Datasheet
CLKOUT
RA6
10
7
ANA6
—
—
—
—
—
—
—
—
—
CTS3(1)
—
IOCA6
—
—
—
—
RA7
9
6
ANA7
—
—
—
—
—
—
—
—
—
RX3(1)
—
IOCA7
—
—
—
—
RB0
21
18
ANB0
—
C2IN1+
ZCDIN
—
—
CWG1(1)
—
—
—
—
—
IOCB0
INT0(1)
—
—
—
—
—
—
—
CWG2(1)
—
—
—(4)
—
—
IOCB1
INT1(1)
—
—
—
—
—
—
—
CWG3(1)
—
SDI2(1)
—(4)
—
—
IOCB2
INT2(1)
—
—
—
—
—
—
—
—
—
SCK2(1)
—
—
—
IOCB3
—
CANRX(1)
—
TDO
—
—
—
—
CTS4(1)
—
IOCB4
—
—
—
—
—
—
—
—
RX4(1)
—
IOCB5
—
—
—
TDI
—
—
—
CTS2(1)
—
IOCB6
—
—
—
—
ICSPCLK
C1IN3RB1
22
19
ANB1
—
RB2
23
20
ANB2
—
C2IN3—
C1IN2-
21
ANB3
—
RB4
25
22
ADACT(1)
—
—
—
T5G(1)
—
—
RB5
26
23
ANB5
—
—
—
T1G(1)
CCP3(1)
—
C2IN2-
ANB4
CLCIN2(1)
OSC1
CLKIN
DS40002213D-page 14
RB6
27
24
ANB6
—
—
—
—
—
—
RB7
28
25
ANB7
DAC1OUT2
—
—
T6IN(1)
PWM3ERS(1)
—
CLCIN7(1)
—
—
RX2(1)
—
IOCB7
—
—
—
—
ICSPDAT
—
—
—
—
—
—
—
IOCC0
—
—
—
—
SOSCO
CLCIN6(1)
CLCIN3(1)
T1CKI(1)
T3CKI(1)
RC0
11
8
ANC0
—
—
—
T3G(1)
SMT1WIN(1)
PIC18F27/47/57Q84
24
OSC2
Pin Allocation Tables
RB3
Pin Allocation Tables
© 2021 Microchip Technology Inc.
Table 3-1. 28-Pin Allocation Table
© 2021 Microchip Technology Inc.
...........continued
28Pin
I/O(2)
SPDIP,
28Pin
SOIC,
VQFN
rotatethispage90
A/D
Reference
Comparator
ZCD
Timers/SMT
16-Bit PWM/
CCP
CWG
CLC
SPI
I2C
UART
DSM
IOC
Interrupt
CAN FD
CRC on Boot
JTAG
Basic
CCP2(1)
—
—
—
—
—
—
IOCC1
—
—
—
—
SOSCIN
SOSCI
—
—
—
—
—
—
—
SSOP
RC1
12
9
ANC1
—
—
—
SMT1SIG(1)
RC2
13
10
ANC2
—
—
—
T5CKI(1)
PWM1ERS(1)
PWMIN0(1)
CCP1(1)
—
—
IOCC2
—
—
RC3
14
11
ANC3
—
—
—
T2IN(1)
—
—
SCK1(1) SCL1(3,4)
—
—
IOCC3
—
—
—
—
—
RC4
15
12
ANC4
—
—
—
—
—
—
—
SDI1(1)
SDA(3,4)
—
—
IOCC4
—
—
BOOTC4
—
—
RC5
16
13
ANC5
—
—
—
T4IN(1)
PWM2ERS(1)
—
—
—
—
—
—
IOCC5
—
—
BOOTC5
—
—
RC6
17
14
ANC6
—
—
—
—
PWMIN1(1)
—
—
—
—
CTS1(1)
—
IOCC6
—
—
—
—
—
RC7
18
15
ANC7
—
—
—
—
—
—
—
—
—
RX1(1)
—
IOCC7
—
—
—
—
—
RE3
1
26
—
—
—
—
—
—
—
—
—
—
—
—
IOCE3
—
—
—
—
Vpp/MCLR
Preliminary Datasheet
VSS
19
16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VSS
VDD(5)
20
17
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD(5)
VSS
8
5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
VSS
DSM1
—
—
CANTX
—
—
—
DTR1
RTS1
CWG1A
PWM11
PWM12
PWM21
OUT(2)
ADGRDA
—
—
ADGRDB
PWM22
C1OUT
—
C2OUT
—
TMR0
PWM31
PWM32
CCP1
CCP2
DTR2
CWG1C
CLC1OUT
CWG1D
CLC2OUT
SS1
CWG2A
CLC3OUT
SCK1
RTS2
TX2
CWG2B
CLC4OUT
SDO1
SDA1
CWG2C
CLC5OUT
SS2
SCL1
CWG2D
CLC6OUT
SCK2
CWG3A
CLC7OUT
SDO2
CWG3B
CLC8OUT
CWG3C
CWG3D
DTR3
RTS3
TX3
DTR4
RTS4
TX4
DTR5
TX5
Notes:
DS40002213D-page 15
1.
This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the peripheral input selection table for details on which PORT pins may be used for this signal.
2.
All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in the peripheral output selection table.
3.
4.
This is a bidirectional signal. For normal module operation, the firmware needs to map this signal to the same pin in both the PPS input and PPS output registers.
These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard TTL/ST as selected by the INLVL register, instead of
the I2C specific or SMBus input buffer thresholds.
5.
A 0.1 uF bypass capacitor to VSS is required on the VDD pin.
Pin Allocation Tables
RTS5
PIC18F27/47/57Q84
CCP3
TX1
CWG1B
© 2021 Microchip Technology Inc.
Table 3-2. 40/44/48-Pin Allocation Table
40Pin
40Pin
44Pin
PDIP
VQFN
TQFP
RA0
2
17
19
RA1
3
18
20
I/O(2)
rotatethispage90
48Pin
A/D
Reference
21
ANA0
—
22
ANA1
—
TQFP /
ZCD
Timers/SM
T
16-Bit
PWM/
CCP
CWG
—
—
—
—
—
—
—
—
—
—
—
C1IN1+
—
—
—
—
T0CKI(1)
Comparator
SPI
I2C
UART
DSM
IOC
Interrupt
CAN
FD
CRC
on
Boot
JTAG
Basic
—
—
—
—
IOCA0
—
—
—
TMS
—
CLCIN5(1)
—
—
—
—
IOCA1
—
—
—
—
—
—
—
—
—
—
—
IOCA2
—
—
BOOTA2
—
—
—
—
—
—
—
—
MDCARL(1) IOCA3
—
—
—
—
—
—
—
—
SS2(1)
—
(1) IOCA4
CTS5(1) MDCARH
—
—
BOOTA4
—
—
—
SS1(1)
MDSRC(1) IOCA5
—
—
—
TCK
CLC
VQFN
CLCIN0(1)
C1IN0C2IN0-
CLCIN1(1)
C1IN1C2IN1-
CLCIN4(1)
DAC1OUT1
RA2
4
19
21
23
ANA2
VREF(DAC)
VREF(ADC)
Preliminary Datasheet
RA3
5
20
22
24
ANA3
RA4
6
21
23
25
ANA4
26
ANA5
RA5
7
22
24
VREF+
(DAC)
VREF+
(ADC)
—
—
C1IN0+
C2IN0+
—
—
—
—
—
—
RX5(1)
—
CLKOUT
RA6
14
29
31
33
ANA6
—
—
—
—
—
—
—
—
—
CTS3(1)
—
IOCA6
—
—
—
—
RA7
13
28
30
32
ANA7
—
—
—
—
—
—
—
—
—
RX3(1)
—
IOCA7
—
—
—
—
RB0
33
8
8
8
ANB0
—
C2IN1+
ZCDIN
—
—
CWG1(1)
—
—
—
—
—
IOCB0
INT0(1)
—
—
—
—
—
—
—
CWG2(1)
—
—
—(4)
—
—
IOCB1
INT1(1)
—
—
—
—
—
—
—
CWG3(1)
—
SDI2(1)
—(4)
—
—
IOCB2
INT2(1)
—
—
—
—
—
—
—
—
—
SCK2(1)
—
—
—
IOCB3
—
—
—
TDO
—
—
—
—
CTS4(1)
—
IOCB4
—
—
—
—
—
—
—
—
RX4(1)
—
IOCB5
—
—
—
TDI
—
—
CTS2(1)
—
IOCB6
—
—
—
—
ICSPCLK
34
9
9
9
ANB1
—
RB2
35
10
10
10
ANB2
—
RB3
36
11
11
11
ANB3
—
RB4
37
12
14
16
ADACT(1)
—
—
—
T5G(1)
—
—
RB5
38
13
15
17
ANB5
—
—
—
T1G(1)
CCP3(1)
—
C2IN3—
C1IN2-
DS40002213D-page 16
C2IN2-
ANB4
CLCIN2(1)
RB6
39
14
16
18
ANB6
—
—
—
—
—
—
CLCIN6(1)
Pin Allocation Tables
RB1
OSC1
CLKIN
PIC18F27/47/57Q84
C1IN3-
OSC2
© 2021 Microchip Technology Inc.
...........continued
I/O(2)
40Pin
40Pin
44Pin
PDIP
VQFN
TQFP
40
15
17
rotatethispage90
RB7
48Pin
TQFP /
A/D
Reference
Comparator
ZCD
Timers/SM
T
16-Bit
PWM/
CCP
CWG
ANB7
DAC1OUT2
—
—
T6IN(1)
PWM3ERS(1)
—
—
CCP2(1)
SPI
I2C
UART
DSM
IOC
Interrupt
CAN
FD
CRC
on
Boot
JTAG
Basic
CLCIN7(1)
—
—
RX2(1)
—
IOCB7
—
—
—
—
ICSPDAT
—
—
—
—
—
—
IOCC0
—
—
—
—
SOSCO
—
—
—
—
—
—
IOCC1
—
—
—
—
SOSCIN
SOSCI
CCP1(1)
—
—
—
—
—
—
IOCC2
—
—
—
—
—
—
CLC
VQFN
19
CLCIN3(1)
T1CKI(1)
T3CKI(1)
RC0
15
30
32
34
ANC0
—
—
—
T3G(1)
SMT1WIN(1)
Preliminary Datasheet
16
31
35
35
ANC1
—
—
—
SMT1SIG(1)
RC2
17
32
36
40
ANC2
—
—
—
T5CKI(1)
RC3
18
33
37
41
ANC3
—
—
—
T2IN(1)
PWM1ERS(1)
—
—
SCK1(1) SCL1(3,4)
—
—
IOCC3
—
—
—
—
RC4
23
38
42
46
ANC4
—
—
—
—
—
—
—
SDI1(1) SDA(3,4)
—
—
IOCC4
—
—
BOOTC4
—
—
RC5
24
39
43
47
ANC5
—
—
—
T4IN(1)
PWM2ERS(1)
—
—
—
—
—
—
IOCC5
—
—
BOOTC5
—
—
RC6
25
40
44
48
ANC6
—
—
—
—
PWMIN1(1)
—
—
—
—
CTS1(1)
—
IOCC6
—
—
—
—
—
RC7
26
1
1
1
ANC7
—
—
—
—
—
—
—
—
—
RX1(1)
—
IOCC7
—
—
—
—
—
RD0
19
34
38
42
AND0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RD1
20
35
39
43
AND1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RD2
21
36
40
44
AND2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RD3
22
37
41
45
AND3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RD4
27
2
2
2
AND4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RD5
28
3
3
3
AND5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RD6
29
4
4
4
AND6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RD7
30
5
5
5
AND7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RE0
8
23
25
27
ANE0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RE1
9
24
26
28
ANE1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RE2
10
25
27
29
ANE2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Vpp/
MCLR
PWMIN0(1)
1
16
18
20
—
—
—
—
—
—
—
—
—
—
—
RF0
—
—
—
36
ANF0
—
—
—
—
RF1
—
—
—
37
ANF1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IOCE3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RF2
—
—
—
38
ANF2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RF3
—
—
—
39
ANF3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RF4
—
—
—
12
ANF4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RF5
—
—
—
13
ANF5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PIC18F27/47/57Q84
RE3
Pin Allocation Tables
DS40002213D-page 17
RC1
© 2021 Microchip Technology Inc.
...........continued
48Pin
40Pin
40Pin
44Pin
PDIP
VQFN
TQFP
RF6
—
—
—
14
ANF6
—
—
—
—
—
—
—
—
—
—
—
—
RF7
—
—
—
15
ANF7
—
—
—
—
—
—
—
—
—
—
—
—
VSS
12, 31
6, 27
6, 29
6,31
—
—
—
—
—
—
—
—
—
—
—
—
—
VDD(5) 11, 32
7, 26
7, 28
7, 30
—
—
—
—
—
—
—
—
—
—
—
—
DSM1
I/O(2)
rotatethispage90
TQFP /
A/D
Reference
Comparator
ZCD
Timers/SM
T
16-Bit
PWM/
CCP
CWG
CLC
SPI
I2C
UART
DSM
CRC
on
Boot
JTAG
—
—
—
—
—
—
—
—
—
—
—
—
VSS
—
—
—
—
—
VDD(5)
—
—
—
—
—
—
Interrupt
Basic
VQFN
DTR1
RTS1
CWG1A
PWM11
PWM12
PWM21
Preliminary Datasheet
CAN
FD
IOC
OUT(2)
ADGRDA
ADGRDB
PWM22
C1OUT
—
C2OUT
—
TMR0
PWM31
PWM32
CCP1
CCP2
CCP3
TX1
CWG1B
DTR2
CWG1C CLC1OUT
CWG1D CLC2OUT
SS1
CWG2A CLC3OUT
SCK1
RTS2
TX2
CWG2B CLC4OUT
SDO1
SDA1
CWG2C CLC5OUT
SS2
SCL1
CWG2D CLC6OUT
SCK2
CWG3A CLC7OUT
SDO2
CWG3B CLC8OUT
CWG3C
CWG3D
DTR3
RTS3
TX3
DTR4
RTS4
TX4
DTR5
RTS5
TX5
Notes:
2.
All output signals shown in this row are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options as described in the peripheral output selection table.
3.
4.
This is a bidirectional signal. For normal module operation, the firmware needs to map this signal to the same pin in both the PPS input and PPS output registers.
These pins are configured for I2C logic levels; The SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard TTL/ST as
selected by the INLVL register, instead of the I2C specific or SMBus input buffer thresholds.
5.
A 0.1 uF bypass capacitor to VSS is required on all VDD pins.
PIC18F27/47/57Q84
This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the peripheral input selection table for details on which PORT pins may
be used for this signal.
Pin Allocation Tables
DS40002213D-page 18
1.
PIC18F27/47/57Q84
Guidelines for Getting Started with PIC18-Q84 Micr...
4.
Guidelines for Getting Started with PIC18-Q84 Microcontrollers
4.1
Basic Connection Requirements
Getting started with the PIC18-Q84 family of 8-bit microcontrollers requires attention to a minimal set of device pin
connections before proceeding with development.
The following pins must always be connected:
•
•
All VDD and VSS pins (see Power Supply Pins)
MCLR pin (see Master Clear (MCLR) Pin)
These pins must also be connected if they are being used in the end application:
•
•
ICSPCLK/ICSPDAT pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see InCircuit Serial Programming (ICSP) Pins)
OSCI and OSCO pins when an external oscillator source is used (see External Oscillator Pins)
Additionally, the following pins may be required:
•
VREF+/VREF- pins are used when external voltage reference for analog modules is implemented
The minimum mandatory connections are shown in the figure below.
Figure 4-1. Recommended Minimum Connections
Rev. 10-000249C
4/1/2019
VDD
VDD
R1
R2
VSS
C2
MCLR
C1
PIC MCU
VSS
Key:
C1: 0.1 F, 20V ceramic (recommended)
R1: 10 kΩ (recommended)
R2: 100Ω to 470Ω (recommended)
C2: 0.1 F, 20V ceramic (required)
4.2
Power Supply Pins
4.2.1
Decoupling Capacitors
The use of decoupling capacitors on every pair of power supply pins (VDD and VSS) is required.
Consider the following criteria when using decoupling capacitors:
•
•
Value and type of capacitor: A 0.1 μF (100 nF), 10-20V capacitor is recommended. The capacitor needs to be
a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are
recommended.
Placement on the printed circuit board: The decoupling capacitors need to be placed as close to the pins as
possible. It is recommended to place the capacitors on the same side of the board as the device. If space is
constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater than 0.25 inch (6 mm).
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 19
PIC18F27/47/57Q84
Guidelines for Getting Started with PIC18-Q84 Micr...
•
•
4.2.2
Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz),
add a second ceramic type capacitor in parallel to the above described decoupling capacitor. The value of the
second capacitor can be in the range of 0.01 μF to 0.001 μF. Place this second capacitor next to each primary
decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as
close to the power and ground pins as possible (e.g., 0.1 μF in parallel with 0.001 μF).
Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to
the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first
in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a
minimum, thereby reducing PCB trace inductance.
Tank Capacitors
On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for
integrated circuits, including microcontrollers, to supply a local power source. The value of the tank capacitor will be
determined based on the trace resistance that connects the power supply source to the device, and the maximum
current drawn by the device in the application. In other words, select the tank capacitor that meets the acceptable
voltage sag at the device. Typical values range from 4.7 μF to 47 μF.
4.3
Master Clear (MCLR) Pin
The MCLR pin provides two specific device functions: Device Reset, and Device Programming and Debugging. If
programming and debugging are not required in the end application, a direct connection to VDD may be all that
is required. The addition of other components, to help increase the application’s resistance to spurious Resets
from voltage sags, may be beneficial. A typical configuration is shown in Figure 4-1. Other circuit designs may be
implemented, depending on the application’s requirements.
During programming and debugging, the resistance and capacitance that can be added to the pin must be
considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH
and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R1 and C1 will need
to be adjusted based on the application and PCB requirements. For example, it is recommended that the capacitor,
C1, be isolated from the MCLR pin during programming and debugging operations by using a jumper (Figure 4-2).
The jumper is replaced for normal run-time operations.
Any components associated with the MCLR pin need to be placed within 0.25 inch (6 mm) of the pin.
Figure 4-2. Example of MCLR Pin Connections
VDD
Rev. 30-000058A
4/5/2017
R1
R2
JP
MCLR
PIC MCU
C1
Notes:
1. R1 ≤ 10 kΩ is recommended. A suggested starting value is 10 kΩ. Ensure that the MCLR pin VIH and VIL
specifications are met.
2. R2 ≤ 470Ω will limit any current flowing into MCLR from the extended capacitor, C1, in the event of MCLR pin
breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
4.4
In-Circuit Serial Programming™ (ICSP™) Pins
The ICSPCLK and ICSPDAT pins are used for ICSP and debugging purposes. It is recommended to keep the trace
length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of
ohms, not to exceed 100Ω.
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Guidelines for Getting Started with PIC18-Q84 Micr...
Pull-up resistors, series diodes and capacitors on the ICSPCLK and ICSPDAT pins are not recommended as they
can interfere with the programmer/debugger communications to the device. If such discrete components are an
application requirement, they need to be removed from the circuit during programming and debugging. Alternatively,
refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming
specification for information on capacitive loading limits, and pin input voltage high (VIH) and input low (VIL)
requirements.
For device emulation, ensure that the “Communication Channel Select” (i.e., ICSPCLK/ICSPDAT pins), programmed
into the device, matches the physical connections for the ICSP to the Microchip debugger/emulator tool.
4.5
External Oscillator Pins
Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a lowfrequency secondary oscillator.
The oscillator circuit needs to be placed on the same side of the board as the device. Place the oscillator circuit close
to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins.
The load capacitors have to be placed next to the oscillator itself, on the same side of the board.
Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The grounded copper
pour needs to be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground
pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed.
Layout suggestions are shown in the following figure. In-line packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With fine-pitch packages, it is not always possible to completely
surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored ground layer.
In all cases, the guard trace(s) must be returned to ground.
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Guidelines for Getting Started with PIC18-Q84 Micr...
Figure 4-3. Suggested Placement of the Oscillator Circuit
In planning the application’s routing and I/O assignments, ensure that adjacent PORT pins, and other signals in close
proximity to the oscillator, are benign (i.e., free of high frequencies, short rise and fall times, and other similar noise).
For additional information and design guidance on oscillator circuits, refer to these Microchip Application Notes,
available at the corporate website (www.microchip.com):
•
•
•
•
®
AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC™ and PICmicro Devices”
®
AN849, “Basic PICmicro Oscillator Design”
®
AN943, “Practical PICmicro Oscillator Analysis and Design”
AN949, “Making Your Oscillator Work”
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4.6
Unused I/Os
Unused I/O pins need to be configured as outputs and driven to a logic low state. Alternatively, connect a 1 kΩ to 10
kΩ resistor to VSS on unused pins to drive the output to logic low.
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Register and Bit Naming Conventions
5.
5.1
Register and Bit Naming Conventions
Register Names
When there are multiple instances of the same peripheral in a device, the Peripheral Control registers will be depicted
as the concatenation of a peripheral identifier, peripheral instance, and control identifier. The control registers section
will show just one instance of all the register names with an ‘x’ in the place of the peripheral instance number. This
naming convention may also be applied to peripherals when there is only one instance of that peripheral in the device
to maintain compatibility with other devices in the family that contain more than one.
5.2
Bit Names
There are two variants for bit names:
•
•
5.2.1
Short name: Bit function abbreviation
Long name: Peripheral abbreviation + short name
Short Bit Names
Short bit names are an abbreviation for the bit function. For example, some peripherals are enabled with the EN bit.
The bit names shown in the registers are the short name variant.
Short bit names are useful when accessing bits in C programs. The general format for accessing bits by the short
name is RegisterNamebits.ShortName. For example, the enable bit, ON, in the ADCON0 register can be set in C
programs with the instruction ADCON0bits.ON = 1.
Short names are generally not useful in assembly programs because the same name may be used by different
peripherals in different bit positions. When this occurs, during the include file generation, all instances of that short
bit name are appended with an underscore plus the name of the register in which the bit resides to avoid naming
contentions.
5.2.2
Long Bit Names
Long bit names are constructed by adding a peripheral abbreviation prefix to the short name. The prefix is unique
to the peripheral, thereby making every long bit name unique. The long bit name for the ADC enable bit is the ADC
prefix, AD, appended with the enable bit short name, ON, resulting in the unique bit name ADON.
Long bit names are useful in both C and assembly programs. For example, in C the ADCON0 enable bit can be set
with the ADON = 1 instruction. In assembly, this bit can be set with the BSF ADCON0,ADON instruction.
5.2.3
Bit Fields
Bit fields are two or more adjacent bits in the same register. Bit fields adhere only to the short bit naming convention.
For example, the three Least Significant bit of the ADCON2 register contain the ADC Operating Mode Selection bit.
The short name for this field is MD and the long name is ADMD. Bit field access is only possible in C programs. The
following example demonstrates a C program instruction for setting the ADC to operate in Accumulate mode:
ADCON2bits.MD = 0b001;
Individual bits in a bit field can also be accessed with long and short bit names. Each bit is the field name appended
with the number of the bit position within the field. For example, the Most Significant mode bit has the short bit name
MD2 and the long bit name is ADMD2. The following two examples demonstrate assembly program sequences for
setting the ADC to operate in Accumulate mode:
MOVLW
ANDWF
~(1 Main Priority
In this case, interrupt routines and peripheral operation (DMAx, Scanner) will stall the Main loop. Interrupt will
preempt peripheral operation, which results in lowest interrupt latency.
7.2.4
Peripheral 1 Priority > ISR Priority > Main Priority > Peripheral 2 Priority
In this case, the Peripheral 1 will stall the execution of the CPU. However, Peripheral 2 can access the memory in
cycles unused by Peripheral 1, ISR and the Main Routine.
7.3
8x8 Hardware Multiplier
This device includes an 8x8 hardware multiplier as part of the ALU within the CPU. The multiplier performs an
unsigned operation and yields a 16-bit result that is stored in the product register, PROD. The multiplier’s operation
does not affect any flags in the STATUS register.
Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the
advantages of higher computational throughput and reduced code size for multiplication algorithms and allows the
device to be used in many applications previously reserved for digital signal processors. A comparison of various
hardware and software multiply operations, along with the savings in memory and execution time, is shown in Table
7-2.
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Table 7-2. Performance Comparison for Various Multiply Operations
Routine
8x8 unsigned
8x8 signed
16x16 unsigned
16x16 signed
7.3.1
Program
Time
Cycles
Memory
(Max) @ 64 MHz @ 40 MHz @ 10 MHz @ 4 MHz
(Words)
Multiply Method
Without hardware multiply
13
69
4.3 μs
6.9 μs
27.6 μs
69 μs
Hardware multiply
1
1
62.5 ns
100 ns
400 ns
1 μs
Without hardware multiply
33
91
5.7 μs
9.1 μs
36.4 μs
91 μs
Hardware multiply
6
6
375 ns
600 ns
2.4 μs
6 μs
Without hardware multiply
21
242
15.1 μs
24.2 μs
96.8 μs
242 μs
Hardware multiply
28
28
1.8 μs
2.8 μs
11.2 μs
28 μs
Without hardware multiply
52
254
15.9 μs
25.4 μs
102.6 μs
254 μs
Hardware multiply
35
40
2.5 μs
4.0 μs
16.0 μs
40 μs
Operation
Example 7-3 shows the instruction sequence for an 8x8 unsigned multiplication. Only one instruction is required
when one of the arguments is already loaded in the WREG register. Example 7-4 shows the sequence to do an 8x8
signed multiplication. To account for the sign bits of the arguments, each argument’s Most Significant bit (MSb) is
tested and the appropriate subtractions are done.
Example 7-3. 8x8 Unsigned Multiply Routine
MOVF
ARG1, W
;
MULWF
ARG2
; ARG1 * ARG2 -> PRODH:PRODL
Example 7-4. 8x8 Signed Multiply Routine
MOVF
MULWF
BTFSC
SUBWF
MOVF
BTFSC
SUBWF
7.3.2
ARG1, W
ARG2
ARG2, SB
PRODH, F
ARG2, W
ARG1, SB
PRODH, F
; ARG1 * ARG2 -> PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH - ARG1
; Test Sign Bit
; PRODH = PRODH - ARG2
16x16 Unsigned Multiplication Algorithm
Example 7-6 shows the sequence to do a 16x16 unsigned multiplication. Example 7-5 shows the algorithm that is
used. The 32-bit result is stored in four registers.
Example 7-5. 16x16 Unsigned Multiply Algorithm
RES3: RES0 = ARG1H: ARG1L • ARG2H: ARG2L = ARG1H • ARG2H • 216 + ARG1H • ARG2L • 28
+ ARG1L • ARG2H • 28 + ARG1L • ARG2L
Example 7-6. 16x16 Unsigned Multiply Routine
MOVF
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;
;
;
7.3.3
MULWF
MOVFF
MOVFF
ARG2L
PRODH, RES1
PRODL, RES0
; ARG1L * ARG2L → PRODH:PRODL
;
;
MOVF
MULWF
MOVFF
MOVFF
ARG1H, W
ARG2H
PRODH, RES3
PRODL, RES2
;
; ARG1H * ARG2H → PRODH:PRODL
;
;
MOVF
MULWF
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
ARG1L, W
ARG2H
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
; ARG1L * ARG2H → PRODH:PRODL
;
; Add cross products
;
;
;
;
MOVF
MULWF
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
ARG1H, W
ARG2L
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
;
; ARG1H * ARG2L → PRODH:PRODL
;
; Add cross products
;
;
;
;
16x16 Signed Multiplication Algorithm
Example 7-8 shows the sequence to do a 16x16 signed multiply. Example 7-7 shows the algorithm used. The 32-bit
result is stored in four registers. To account for the sign bits of the arguments, the MSb for each argument pair is
tested and the appropriate subtractions are done.
Example 7-7. 16x16 Signed Multiply Algorithm
RES3: RES0 = ARG1H: ARG1L • ARG2H: ARG2L = ARG1H • ARG2H • 216 + ARG1H • ARG2L • 28
+ ARG1L • ARG2H • 28 + ARG1L • ARG2L + − 1 • ARG2H < 7 > • ARG1H: ARG1L • 216 +
− 1 • ARG1H < 7 > • ARG2H: ARG2L • 216
Example 7-8. 16x16 Signed Multiply Routine
;
;
;
MOVF
MULW
MOVF
MOVFF
ARG1L, W
ARG2L
PRODH, RES1
PRODL, RES0
; ARG1L * ARG2L → PRODH:PRODL
;
;
MOVF
MULWF
MOVFF
MOVFF
ARG1H, W
ARG2H
PRODH, RES3
PRODL, RES2
; ARG1H * ARG2H → PRODH:PRODL
;
;
MOVF
MULWF
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
ARG1L, W
ARG2H
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
; ARG1L * ARG2H → PRODH:PRODL
;
; Add cross products
;
;
;
;
MOVF
ARG1H, W
;
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;
;
MULWF
MOVF
ADDWF
MOVF
ADDWFC
CLRF
ADDWFC
ARG2L
PRODL, W
RES1, F
PRODH, W
RES2, F
WREG
RES3, F
; ARG1H * ARG2L → PRODH:PRODL
;
; Add cross products
;
;
;
;
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
ARG2H, 7
SIGN_ARG1
ARG1L, W
RES2
ARG1H, W
RES3
; ARG2H:ARG2L neg?
; no, check ARG1
;
;
;
ARG1H, 7
CONT_CODE
ARG2L, W
RES2
ARG2H, W
RES3
; ARG1H:ARG1L neg?
; no, done
;
;
;
SIGN_ARG1:
BTFSS
BRA
MOVF
SUBWF
MOVF
SUBWFB
;
CONT_CODE:
:
7.4
PIC18 Instruction Cycle
7.4.1
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four cycles of the oscillator clock. The instruction fetch and execute are pipelined
in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction
cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the
Program Counter (PC) to change (e.g., GOTO), then two cycles are required to complete the instruction (Figure 7-3).
A fetch cycle begins with the Program Counter (PC) incrementing followed by the execution cycle. In the execution
cycle, the fetched instruction is latched into the Instruction Register (IR). This instruction is then decoded and
executed during the next few oscillator clock cycles. Data memory is read (operand read) and written (destination
write) during the execution cycle as well.
Figure 7-3. Instruction Pipeline Flow
Rev. 10-000 337A
2/28/201 9
TCY0
TCY1
Fetch 1
Execute 1
1. MOVLW
55h
2. MOVWF
PORTB
3. BRA
Sub_1
4. BSF
PORTA, BITS (Forced NOP)
Fetch 2
TCY2
TCY3
TCY4
TCY5
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush (NOP)
Fetch Sub_1
5. Instruction @ address Sub_1
Execute Sub_1
Note: There are some instructions that take multiple cycles to execute. Refer to the “Instruction Set Summary”
section for details.
7.4.2
Instructions in Program Memory
The program memory is addressed in bytes. Instructions are stored as either two bytes, four bytes, or six bytes in
program memory. The Least Significant Byte of an instruction word is always stored in a program memory location
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with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of
two and the LSb will always read ‘0’. See the “Program Counter” section in the “Memory Organization” chapter
for more details. The instructions in the Program Memory figure below shows how instruction words are stored in the
program memory.
The CALL and GOTO instructions have the absolute program memory address embedded into the instruction. Since
instructions are always stored on word boundaries, the data contained in the instruction is a word address. The
word address is written to the corresponding bits of the Program Counter register, which accesses the desired byte
address in program memory. Instruction #2 in the example shows how the instruction GOTO 0006h is encoded in the
program memory. Program branch instructions, which encode a relative address offset, operate in the same manner.
The offset value stored in a branch instruction represents the number of single-word instructions that the PC will be
offset by.
Figure 7-4. Instructions in Program Memory
LSB = 1
LSB = 0
Word Address
Program Memory
Byte Locations
7.4.3
Instruction 1:
Instruction 2:
MOVLW
GOTO
055h
0006h
Instruction 3:
MOVFF
123h, 456h
Instruction 4:
MOVFFL
123h, 456h
0Fh
EFh
F0h
C1h
F4h
00h
F4h
F4h
55h
03h
00h
23h
56h
60h
8Ch
56h
000000h
000002h
000004h
000006h
000008h
00000Ah
00000Ch
00000Eh
000010h
000012h
000014h
000016h
000018h
00001Ah
Multi-Word Instructions
The standard PIC18 instruction set has six two-word instructions: CALL, MOVFF, GOTO, LFSR, MOVSF and MOVSS
and two three-word instructions: MOVFFL and MOVSFL. In all cases, the second and the third word of the instruction
always has 1111 as its four Most Significant bits; the other 12 bits are literal data, usually a data memory address.
The use of 1111 in the four MSbs of an instruction specifies a special form of NOP. If the instruction is executed
in proper sequence, immediately after the first word, the data in the second word is accessed and used by the
instruction sequence. If the first word is skipped for some reason and the second word is executed by itself, a NOP is
executed instead. This is necessary for cases when the two-word instruction is preceded by a conditional instruction
that changes the PC.
Table 7-3 and Table 7-4 show more details of how two-word instructions work. Table 7-5 and Table 7-6 show more
details of how three-word instructions work.
Important: See the “PIC18 Instruction Execution and the Extended Instruction Set” section for
information on two-word instructions in the extended instruction set.
Table 7-3. Two-Word Instructions (Case 1)
Object Code
Source Code
Comment
0110 0110 0000 0000
TSTFSZ REG1
; is RAM location 0?
1100 0001 0101 0011
MOVFF REG1,REG2
; No, skip this word
1111 0100 0101 0110
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...........continued
Object Code
Source Code
Comment
0010 0100 0000 0000
ADDWF REG3
; continue code
Table 7-4. Two-Word Instructions (Case 2)
Object Code
Source Code
Comment
0110 0110 0000 0000
TSTFSZ REG1
; is RAM location 0?
1100 0001 0101 0011
MOVFF REG1,REG2
; Yes, execute this word
1111 0100 0101 0110
0010 0100 0000 0000
; 2nd word of instruction
ADDWF REG3
; continue code
Table 7-5. Three-Word Instructions (Case 1)
Object Code
Source Code
Comment
0110 0110 0000 0000
TSTFSZ REG1
; is RAM location 0?
0000 0000 0110 0000
MOVFFL REG1,REG2
; Yes, skip this word
1111 0100 1000 1100
; Execute this word as NOP
1111 0100 0101 0110
; Execute this word as NOP
0010 0100 0000 0000
ADDWF REG3
; continue code
Table 7-6. Three-Word Instructions (Case 2)
Object Code
Source Code
Comment
0110 0110 0000 0000
TSTFSZ REG1
; is RAM location 0?
0000 0000 0110 0000
MOVFFL REG1,REG2
; No, execute this word
1111 0100 1000 1100
; 2nd word of instruction
1111 0100 0101 0110
; 3rd word of instruction
0010 0100 0000 0000
7.5
ADDWF REG3
; continue code
STATUS Register
The STATUS register contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for
any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits,
the results of the instruction are not written; instead, the STATUS register is updated according to the instruction
performed. Therefore, the result of an instruction with the STATUS register as its destination may be different than
intended. As an example, CLRF STATUS will set the Z bit and leave the remaining Status bits unchanged (‘000u
u1uu’).
It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register,
because these instructions do not affect the Z, C, DC, OV or N bits in the STATUS register. For other instructions that
do not affect Status bits, see the instruction set summaries.
Important: The C and DC bits operate as the Borrow and Digit Borrow bits, respectively, in subtraction.
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7.6
Call Shadow Register
When CALL instruction is used, the WREG, BSR and STATUS are automatically saved in hardware and can be
accessed using the WREG_CSHAD, BSR_CSHAD and STATUS_CSHAD registers.
Important:
The contents of these registers need to be handled correctly to avoid erroneous code execution.
7.7
Register Definitions: System Arbiter
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7.7.1
ISRPR
Name:
Address:
ISRPR
0x0BF
Interrupt Service Routine Priority Register
Bit
7
6
5
4
3
Access
Reset
2
R/W
1
1
PR[2:0]
R/W
1
0
R/W
1
Bits 2:0 – PR[2:0] Interrupt Service Routine Priority Selection
Value
Description
111
110
101
100
011
010
001
000
System Arbiter Priority Level: 7 (Lowest Priority)
System Arbiter Priority Level: 6
System Arbiter Priority Level: 5
System Arbiter Priority Level: 4
System Arbiter Priority Level: 3
System Arbiter Priority Level: 2
System Arbiter Priority Level: 1
System Arbiter Priority Level: 0 (Highest Priority)
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7.7.2
MAINPR
Name:
Address:
MAINPR
0x0BE
Main Routine Priority Register
Bit
7
6
5
4
3
Access
Reset
2
R/W
1
1
PR[2:0]
R/W
1
0
R/W
1
Bits 2:0 – PR[2:0] Main Routine Priority Selection
Value
Description
111
110
101
100
011
010
001
000
System Arbiter Priority Level: 7 (Lowest Priority)
System Arbiter Priority Level: 6
System Arbiter Priority Level: 5
System Arbiter Priority Level: 4
System Arbiter Priority Level: 3
System Arbiter Priority Level: 2
System Arbiter Priority Level: 1
System Arbiter Priority Level: 0 (Highest Priority)
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7.7.3
DMAxPR
Name:
Address:
DMAxPR
0x0B6,0x0B7,0x0B8,0x0B9,0x0BA,0x0BB,0x0BC,0x0BD
DMAx Priority Register
Bit
7
6
5
4
3
Access
Reset
2
R/W
1
1
PR[2:0]
R/W
1
0
R/W
1
Bits 2:0 – PR[2:0] DMAx Priority Selection
Value
Description
111
110
101
100
011
010
001
000
System Arbiter Priority Level: 7 (Lowest Priority)
System Arbiter Priority Level: 6
System Arbiter Priority Level: 5
System Arbiter Priority Level: 4
System Arbiter Priority Level: 3
System Arbiter Priority Level: 2
System Arbiter Priority Level: 1
System Arbiter Priority Level: 0 (Highest Priority)
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7.7.4
SCANPR
Name:
Address:
SCANPR
0x0B5
Scanner Priority Register
Bit
7
6
5
4
3
Access
Reset
2
R/W
1
1
PR[2:0]
R/W
1
0
R/W
1
Bits 2:0 – PR[2:0] Scanner Priority Selection
Value
Description
111
110
101
100
011
010
001
000
System Arbiter Priority Level: 7 (Lowest Priority)
System Arbiter Priority Level: 6
System Arbiter Priority Level: 5
System Arbiter Priority Level: 4
System Arbiter Priority Level: 3
System Arbiter Priority Level: 2
System Arbiter Priority Level: 1
System Arbiter Priority Level: 0 (Highest Priority)
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7.7.5
PRLOCK
Name:
Address:
PRLOCK
0x0B4
Priority Lock Register
Bit
7
6
5
4
3
Access
Reset
2
1
0
PRLOCKED
R/W
0
Bit 0 – PRLOCKED PR Register Lock
Value
Description
1
Priority registers are locked and cannot be written; Peripherals do not have access to the memory
0
Priority registers can be modified by write operations; Peripherals do not have access to the memory
Important:
1. The PRLOCKED bit can only be set or cleared after the unlock sequence.
2. If the Configuration Bit PR1WAY = 1, the PRLOCKED bit cannot be cleared after it has been set. A
device Reset will clear the bit and allow one more set.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 40
PIC18F27/47/57Q84
PIC18 CPU
7.7.6
PROD
Name:
Address:
PROD
0x4F3
Timer Register
Product Register Pair
Bit
Access
Reset
Bit
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
12
11
PROD[15:8]
R/W
R/W
0
0
4
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
x
R/W
x
R/W
x
R/W
x
PROD[7:0]
Access
Reset
R/W
x
R/W
x
R/W
x
R/W
x
Bits 15:0 – PROD[15:0] PROD Most Significant
Notes: The individual bytes in this multi-byte register can be accessed with the following register names:
• PRODH: Accesses the high byte PROD[15:8]
• PRODL: Accesses the low byte PROD[7:0]
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 41
PIC18F27/47/57Q84
PIC18 CPU
7.7.7
STATUS
Name:
Address:
STATUS
0x4D8
STATUS Register
Bit
Access
Reset
7
6
TO
R
1
5
PD
R
1
4
N
R/W
0
3
OV
R/W
0
2
Z
R/W
0
1
DC
R/W
0
0
C
R/W
0
Bit 6 – TO Time-Out
Reset States: POR/BOR = 1
All Other Resets = q
Value
Description
1
Set at power-up or by execution of CLRWDT or SLEEP instruction
0
A WDT Time-out occurred
Bit 5 – PD Power-Down
Reset States: POR/BOR = 1
All Other Resets = q
Value
Description
1
Set at power-up or by execution of CLRWDT instruction
0
Cleared by execution of the SLEEP instruction
Bit 4 – N Negative
Used for signed arithmetic (two’s complement); indicates if the result is negative,
(ALU MSb = 1).
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
The result is negative
0
The result is positive
Bit 3 – OV Overflow
Used for signed arithmetic (two’s complement); indicates an overflow of the 7-bit magnitude, which causes the sign
bit (bit 7) to change state.
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
Overflow occurred for current signed arithmetic operation
0
No overflow occurred
Bit 2 – Z Zero
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
The result of an arithmetic or logic operation is zero
0
The result of an arithmetic or logic operation is not zero
Bit 1 – DC Digit Carry / Borrow
ADDWF, ADDLW, SUBLW, SUBWF instructions(1)
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
A carry-out from the 4th low-order bit of the result occurred
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 42
PIC18F27/47/57Q84
PIC18 CPU
Value
0
Description
No carry-out from the 4th low-order bit of the result
Bit 0 – C Carry / Borrow
ADDWF, ADDLW, SUBLW, SUBWF instructions(1,2)
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
A carry-out from the Most Significant bit of the result occurred
0
No carry-out from the Most Significant bit of the result occurred
Notes:
1. For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second
operand.
2. For Rotate (RRCF, RLCF) instructions, this bit is loaded with either the high or low-order bit of the Source
register.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 43
PIC18F27/47/57Q84
PIC18 CPU
7.8
Address
Register Summary - System Arbiter Control
Name
0x00
...
0xB3
0xB4
0xB5
0xB6
0xB7
0xB8
0xB9
0xBA
0xBB
0xBC
0xBD
0xBE
0xBF
0xC0
...
0x0372
0x0373
0x0374
0x0375
0x0376
0x0377
0x0378
0x0379
0x037A
STATUS_CSHAD
WREG_CSHAD
BSR_CSHAD
Reserved
STATUS_SHAD
WREG_SHAD
BSR_SHAD
Reserved
0x037B
PCLAT_SHAD
0x037D
0x037F
0x0381
0x0383
0x0385
...
0x04D7
0x04D8
0x04D9
...
0x04F2
0x04F3
Bit Pos.
7
6
5
4
3
2
1
0
Reserved
PRLOCK
SCANPR
DMA1PR
DMA2PR
DMA3PR
DMA4PR
DMA5PR
DMA6PR
DMA7PR
DMA8PR
MAINPR
ISRPR
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
PRLOCKED
PR[2:0]
PR[2:0]
PR[2:0]
PR[2:0]
PR[2:0]
PR[2:0]
PR[2:0]
PR[2:0]
PR[2:0]
PR[2:0]
PR[2:0]
Reserved
FSR0_SHAD
FSR1_SHAD
FSR2_SHAD
PROD_SHAD
7:0
7:0
7:0
TO
7:0
7:0
7:0
TO
PD
N
OV
Z
DC
C
Z
DC
C
DC
C
WREG[7:0]
BSR[5:0]
PD
N
OV
WREG[7:0]
BSR[5:0]
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
PCLATH[7:0]
PCLATU[4:0]
FSRL[7:0]
FSRH[5:0]
FSRL[7:0]
FSRH[5:0]
FSRL[7:0]
FSRH[5:0]
PROD[7:0]
PROD[15:8]
Reserved
STATUS
7:0
TO
PD
N
OV
Z
Reserved
PROD
7:0
15:8
© 2021 Microchip Technology Inc.
PROD[7:0]
PROD[15:8]
Preliminary Datasheet
DS40002213D-page 44
PIC18F27/47/57Q84
Device Configuration
8.
8.1
Device Configuration
Configuration Settings
The Configuration settings allow the user to setup the device with several choices of oscillators, Resets and memory
protection options. These are implemented at 30 0000h - 30 0022h.
Important: The DEBUG Configuration bit is managed automatically by device development tools
including debuggers and programmers. For normal device operation, this bit needs to be maintained as a
‘1’.
8.2
Code Protection
Code protection allows the device to be protected from unauthorized access. Internal access to the program memory
is unaffected by any code protection setting. A single code-protect bit controls the access for both program memory
and data EEPROM memory.
The entire program memory and Data EEPROM space is protected from external reads and writes by the CP bit.
When CP = 0, external reads and writes are inhibited and a read will return all ‘0’s. The CPU can continue to read
the memory, regardless of the protection bit settings. Self-writing the program memory is dependent upon the write
protection setting.
8.3
User ID
32 words in the memory space (20 0000h - 20 003Fh) are designated as ID locations where the user can store
checksum or other code identification numbers. These locations are readable and writable during normal execution.
See the “User ID, Device ID and Configuration Settings Access, DIA and DCI” section for more information on
accessing these memory locations. For more information on checksum calculation, see the “PIC18FXXQ84 Family
Programming Specification” (DS40002137).
8.4
Device ID and Revision ID
The 16-bit device ID word is located at 0x3FFFFE and the 16-bit revision ID is located at 0x3FFFFC. These locations
are read-only and cannot be erased or modified.
Development tools, such as device programmers and debuggers, may be used to read the Device ID, Revision
ID and Configuration bits. Refer to the “NVM - Nonvolatile Memory Module” section for more information on
accessing these locations.
8.5
Register Definitions: Configuration Words
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 45
PIC18F27/47/57Q84
Device Configuration
8.5.1
CONFIG1
Name:
Address:
CONFIG1
30 0000h
Configuration Byte 1
Bit
Access
Reset
7
6
R/W
1
5
RSTOSC[2:0]
R/W
1
4
3
R/W
1
2
R/W
1
1
FEXTOSC[2:0]
R/W
1
0
R/W
1
Bits 6:4 – RSTOSC[2:0] Power-up Default Value for COSC
This value is the Reset default value for COSC and selects the oscillator first used by user software. Refer to the
COSC operation.
Value
Description
111
EXTOSC operating per FEXTOSC bits
110
HFINTOSC with HFFRQ = 4 MHz and CDIV = 4:1. Resets COSC/NOSC to b'110'.
101
LFINTOSC
100
SOSC
011
Reserved
010
EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits
001
Reserved
000
HFINTOSC with HFFRQ = 64 MHz and CDIV = 1:1. Resets COSC/NOSC to b'110'.
Bits 2:0 – FEXTOSC[2:0] External Oscillator Mode Selection
Value
Description
111
ECH (external clock) above 8 MHz
110
ECM (external clock) for 500 kHz to 8 MHz
101
ECL (external clock) below 500 kHz
100
Oscillator not enabled
011
Reserved (do not use)
010
HS (crystal oscillator) above 4 MHz
001
XT (crystal oscillator) above 500 kHz, below 4 MHz
000
LP (crystal oscillator) optimized for 32.768 kHz
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 46
PIC18F27/47/57Q84
Device Configuration
8.5.2
CONFIG2
Name:
Address:
CONFIG2
30 0001h
Configuration Byte 2
Bit
Access
Reset
7
FCMENS
R/W
1
6
FCMENP
R/W
1
5
FCMEN
R/W
1
4
JTAGEN
R/W
1
3
CSWEN
R/W
1
2
1
PR1WAY
R/W
1
0
CLKOUTEN
R/W
1
Bit 7 – FCMENS Fail-Safe Clock Monitor Enable for Secondary Crystal Oscillator Enable
Value
Description
1
Fail-Safe Clock Monitor enabled for Secondary Crystal, Fail-Safe timer will set the FSCMS bit and
trigger OSFIF interrupt on secondary crystal failure
0
Fail-Safe Clock Monitor disabled for Secondary Crystal
Bit 6 – FCMENP Fail-Safe Clock Monitor Enable for Primary Crystal Oscillator
Value
Description
1
Fail-Safe Clock Monitor enabled for Primary Crystal Oscillator, Fail-Safe timer will set FSCMP bit and
trigger OSFIF interrupt on primary crystal failure
0
Fail-Safe Clock Monitor disabled for Primary Crystal Oscillator
Bit 5 – FCMEN Fail-Safe Clock Monitor Enable for FOSC
Value
Description
1
Fail-Safe Clock Monitor enabled, Fail-Safe timer will initiate a clock switch and trigger OSFIF interrupt
on FOSC failure
0
Fail-Safe Clock Monitor disabled
Bit 4 – JTAGEN JTAG Boundary Scan Enable
Value
Description
1
Enable JTAG Boundary Scan mode and pins
0
Disable JTAG Boundary Scan mode, JTAG pins revert to user functions
Bit 3 – CSWEN Clock Switch Enable
Value
Description
1
Writing to NOSC and NDIV is allowed
0
The NOSC and NDIV bits cannot be changed by user software
Bit 1 – PR1WAY PRLOCKED One-Way Set Enable
Value
Description
1
The PRLOCKED bit can be cleared and set only once; Priority registers remain locked after one
clear/set cycle
0
The PRLOCKED bit can be set and cleared repeatedly (subject to the unlock sequence)
Bit 0 – CLKOUTEN Clock Out Enable
If FEXTOSC = HS, XT, LP, then this bit is ignored.
Otherwise:
Value
Description
1
CLKOUT function is disabled; I/O function on OSC2
0
CLKOUT function is enabled; FOSC/4 clock appears at OSC2
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 47
PIC18F27/47/57Q84
Device Configuration
8.5.3
CONFIG3
Name:
Address:
CONFIG3
30 0002h
Configuration Byte 3
Bit
Access
Reset
7
6
BOREN[1:0]
R/W
R/W
0
0
5
LPBOREN
R/W
1
4
IVT1WAY
R/W
1
3
MVECEN
R/W
1
2
1
PWRTS[1:0]
R/W
R/W
1
1
0
MCLRE
R/W
1
Bits 7:6 – BOREN[1:0] Brown-out Reset Enable
When enabled, Brown-out Reset Voltage (VBOR) is set by the BORV bit.
Value
Description
11
Brown-out Reset enabled, SBOREN bit is ignored
10
Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored
01
Brown-out Reset enabled according to SBOREN
00
Brown-out Reset disabled
Bit 5 – LPBOREN Low-Power BOR Enable
Value
Description
1
Low-Power Brown-out Reset is disabled
0
Low-Power Brown-out Reset is enabled
Bit 4 – IVT1WAY IVTLOCK One-Way Set Enable
Value
Description
1
IVTLOCK bit can be cleared and set only once; IVT registers remain locked after one clear/set cycle
0
IVTLOCK bit can be set and cleared repeatedly (subject to the unlock sequence)
Bit 3 – MVECEN Multivector Enable
Value
Description
1
Multivector is enabled; vector table used for interrupts
0
Legacy interrupt behavior
Bits 2:1 – PWRTS[1:0] Power-up Timer Selection
Value
Description
11
PWRT is disabled
10
PWRT is set at 64 ms
01
PWRT is set at 16 ms
00
PWRT is set at 1 ms
Bit 0 – MCLRE Master Clear (MCLR) Enable
Value
Condition
Description
x
If LVP = 1
RA3 pin function is MCLR
1
If LVP = 0
MCLR pin is MCLR
0
If LVP = 0
MCLR pin function is a port-defined function
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 48
PIC18F27/47/57Q84
Device Configuration
8.5.4
CONFIG4
Name:
Address:
CONFIG4
30 0003h
Configuration Byte 4
Bit
Access
Reset
7
XINST
R/W
1
6
5
LVP
R/W
1
4
STVREN
R/W
1
3
PPS1WAY
R/W
1
2
ZCD
R/W
1
1
0
BORV[1:0]
R/W
1
R/W
1
Bit 7 – XINST Extended Instruction Set Enable
Value
Description
1
Extended Instruction Set and Indexed Addressing mode disabled (Legacy mode)
0
Extended Instruction Set and Indexed Addressing mode enabled
Bit 5 – LVP Low-Voltage Programming Enable
The LVP bit cannot be written (to zero) while operating from the LVP programming interface. The purpose of this rule
is to prevent the user from dropping out of LVP mode while programming from LVP mode, or accidentally eliminating
LVP mode from the Configuration state.
Value
Description
1
Low-Voltage Programming enabled. MCLR/VPP pin function is MCLR. MCLRE Configuration bit is
ignored.
0
HV on MCLR/VPP must be used for programming
Bit 4 – STVREN Stack Overflow/Underflow Reset Enable
Value
Description
1
Stack Overflow or Underflow will cause a Reset
0
Stack Overflow or Underflow will not cause a Reset
Bit 3 – PPS1WAY PPSLOCKED One-Way Set Enable
Value
Description
1
The PPSLOCKED bit can only be set once after an unlocking sequence is executed; once PPSLOCK
is set, all future changes to PPS registers are prevented
0
The PPSLOCKED bit can be set and cleared as needed (unlocking sequence is required)
Bit 2 – ZCD ZCD Disable
Value
Description
1
ZCD disabled, ZCD can be enabled by setting the ZCDSEN bit of ZCDCON
0
ZCD always enabled, PMDx[ZCDMD] bit is ignored
Bits 1:0 – BORV[1:0] Brown-out Reset Voltage Selection(1)
Value
Description
11
Brown-out Reset Voltage (VBOR) set to 1.90V
10
Brown-out Reset Voltage (VBOR) set to 2.45V
01
Brown-out Reset Voltage (VBOR) set to 2.7V
00
Brown-out Reset Voltage (VBOR) set to 2.85V
Note:
1. The higher voltage setting is recommended for operation at or above 16 MHz.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 49
PIC18F27/47/57Q84
Device Configuration
8.5.5
CONFIG5
Name:
Address:
CONFIG5
30 0004h
Configuration Byte 5
Bit
7
6
5
4
3
R/W
0
R/W
1
R/W
1
WDTE[1:0]
Access
Reset
R/W
0
2
WDTCPS[4:0]
R/W
1
1
0
R/W
1
R/W
1
Bits 6:5 – WDTE[1:0] WDT Operating Mode
Value
Description
11
WDT enabled regardless of Sleep; the SEN bit in WDTCON0 is ignored
10
WDT enabled while Sleep = 0, suspended when Sleep = 1; the SEN bit in WDTCON0 is ignored
01
WDT enabled/disabled by the SEN bit in WDTCON0
00
WDT disabled, the SEN bit in WDTCON0 is ignored
Bits 4:0 – WDTCPS[4:0] WDT Period Select
WDTCON0[WDTPS] at POR
Typical Time Out
Value
Divider Ratio
(FIN = 31 kHz)
WDTCPS
11111
11110 to 10011
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
01011
11110 to 10011
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
© 2021 Microchip Technology Inc.
1:65536
1:32
1:8388608
1:4194304
1:2097152
1:1048576
1:524288
1:262144
1:131072
1:65536
1:32768
1:16384
1:8192
1:4096
1:2048
1:1024
1:512
1:256
1:128
1:64
1:32
216
25
223
222
221
220
219
218
217
216
215
214
213
212
211
210
29
28
27
26
25
2s
1 ms
256s
128s
64s
32s
16s
8s
4s
2s
1s
512 ms
256 ms
128 ms
64 ms
32 ms
16 ms
8 ms
4 ms
2 ms
1 ms
Preliminary Datasheet
Software Control of WDTPS?
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
DS40002213D-page 50
PIC18F27/47/57Q84
Device Configuration
8.5.6
CONFIG6
Name:
Address:
CONFIG6
30 0005h
Configuration Byte 6
Bit
7
6
5
Access
Reset
R/W
1
4
WDTCCS[2:0]
R/W
1
3
2
R/W
1
R/W
1
1
WDTCWS[2:0]
R/W
1
0
R/W
1
Bits 5:3 – WDTCCS[2:0] WDT Input Clock Selector
Value
Condition
Description
x
WDTE = 00
These bits have no effect
111
WDTE ≠ 00
Software control
110 to
WDTE ≠ 00
Reserved
011
010
WDTE ≠ 00
WDT reference clock is the SOSC
001
WDTE ≠ 00
WDT reference clock is the 31.25 kHz MFINTOSC
000
WDTE ≠ 00
WDT reference clock is the 31.0 kHz LFINTOSC
Bits 2:0 – WDTCWS[2:0] WDT Window Select
WDTCON1[WINDOW] at POR
WDTCWS
111
110
101
100
011
010
001
000
Value
Window Delay
Percent of Time
Window Opening
Percent of Time
111
110
101
100
011
010
001
000
n/a
n/a
25
37.5
50
62.5
75
87.5
100
100
75
62.5
50
37.5
25
12.5
© 2021 Microchip Technology Inc.
Software Control of
WINDOW
Keyed Access
Required?
Yes
No
No
Yes
Preliminary Datasheet
DS40002213D-page 51
PIC18F27/47/57Q84
Device Configuration
8.5.7
CONFIG7
Name:
Address:
CONFIG7
30 0006h
Configuration Byte 7
Bit
7
6
Access
Reset
5
DEBUG
R/W
1
4
SAFEN
R/W
1
3
BBEN
R/W
1
2
R/W
1
1
BBSIZE[2:0]
R/W
1
0
R/W
1
Bit 5 – DEBUG Debugger Enable
Value
Description
1
Background debugger disabled
0
Background debugger enabled
Bit 4 – SAFEN Storage Area Flash (SAF) Enable(1)
Value
Description
1
SAF is disabled
0
SAF is enabled
Bit 3 – BBEN Boot Block Enable(1)
Value
Description
1
Boot Block is disabled
0
Boot Block is enabled
Bits 2:0 – BBSIZE[2:0] Boot Block Size Selection(2)
Table 8-1. Boot Block Size
BBEN
BBSIZE
End Address of
Boot Block
1
0
0
0
0
0
0
0
0
xxx
111
110
101
100
011
010
001
000
–
00 03FFh
00 07FFh
00 0FFFh
00 1FFFh
00 3FFFh
00 7FFFh
00 FFFFh
01 FFFFh
Boot Block Size (words)
PIC18Fx6Q83/Q84
PIC18Fx7Q83/Q84
–
512
1024
2048
4096
8192
16384
–
32768
–
Notes:
1. Once protection is enabled through ICSP™ or a self-write, it can only be reset through a Bulk Erase.
2. BBSIZE[2:0] bits can only be changed when BBEN = 1. Once BBEN = 0, BBSIZE[2:0] can only be changed
through a Bulk Erase.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 52
PIC18F27/47/57Q84
Device Configuration
8.5.8
CONFIG8
Name:
Address:
CONFIG8
30 0007h
Configuration Byte 8
Bit
Access
Reset
7
WRTAPP
R/W
1
6
5
4
3
WRTSAF
R/W
1
2
WRTD
R/W
1
1
WRTC
R/W
1
0
WRTB
R/W
1
Bit 7 – WRTAPP Application Block Write Protection(1)
Value
Description
1
Application Block is NOT write-protected
0
Application Block is write-protected
Bit 3 – WRTSAF Storage Area Flash (SAF) Write Protection(1,2)
Value
Description
1
SAF is NOT write-protected
0
SAF is write-protected
Bit 2 – WRTD Data EEPROM Write Protection(1)
Value
Description
1
Data EEPROM is NOT write-protected
0
Data EEPROM is write-protected
Bit 1 – WRTC Configuration Register Write Protection(1)
Value
Description
1
Configuration registers are NOT write-protected
0
Configuration registers are write-protected
Bit 0 – WRTB Boot Block Write Protection(1,3)
Value
Description
1
Boot Block is NOT write-protected
0
Boot Block is write-protected
Notes:
1. Once protection is enabled through ICSP™ or a self-write, it can only be reset through a Bulk Erase.
2. Applicable only if SAFEN = 0.
3.
Applicable only if BBEN = 0.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 53
PIC18F27/47/57Q84
Device Configuration
8.5.9
CONFIG9
Name:
Address:
CONFIG9
30 0008h
Configuration Byte 9
Bit
7
6
Access
Reset
5
ODCON
R/W
1
4
BPEN
R/W
1
3
2
1
0
BOOTPINSEL[1:0]
R/W
R/W
1
1
Bit 5 – ODCON CRC-on-Boot Pin Open-Drain Configuration
Value
Description
1
CRC-on-boot output drives both high-going and low-going signals (source and sink current)
0
CRC-on-boot output drives only low-going signals (sink current only)
Bit 4 – BPEN CRC-on-Boot Output Pin Enable
Value
Description
1
CRC-on-boot output pin disabled
0
CRC-on-boot output pin determined by BOOTPINSEL[1:0]
Bits 1:0 – BOOTPINSEL[1:0] CRC-on-Boot Pin Select
Value
Description
11
CRC-on-boot output pin is RC5
10
CRC-on-boot output pin is RC4
01
CRC-on-boot output pin is RA2
00
CRC-on-boot output pin is RA4
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 54
PIC18F27/47/57Q84
Device Configuration
8.5.10
CONFIG10
Name:
Address:
CONFIG10
30 0009h
Configuration Byte 10
Bit
7
6
5
4
3
2
Access
Reset
1
0
CP
R/W
1
Bit 0 – CP User Program Flash Memory and Data EEPROM Code Protection(1)
Value
Description
1
User Program Flash Memory and Data EEPROM code protection are disabled
0
User Program Flash Memory and Data EEPROM code protection are enabled
Note:
1. Once this bit is enabled, it can only be reset through a Bulk Erase.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 55
PIC18F27/47/57Q84
Device Configuration
8.5.11
CONFIG11
Name:
Address:
CONFIG11
30 000Ah
Configuration Byte 11
Bit
Access
Reset
7
BOOTPOR
R/W
1
6
COE
R/W
1
5
CFGSCEN
R/W
1
4
DATSCEN
R/W
1
3
SAFSCEN
R/W
1
2
APPSCEN
R/W
1
1
BOOTCOE
R/W
1
0
BOOTSCEN
R/W
1
Bit 7 – BOOTPOR CRC-on-Boot Enable
Value
Description
1
CRC-on-boot disabled, device will immediately execute user code upon device Reset
0
CRC-on-boot enabled, device will perform CRC check of configured memory before executing user
code upon device Reset
Bit 6 – COE Continue on Error for Non-Boot Block Areas Enable
Value
Description
1
Device will halt if a mismatch is found between expected and calculated CRC values for the non-boot
block areas of memory
0
Device will continue execution even if a mismatch is found between expected and calculated CRC
values for the non-boot block areas of memory
Bit 5 – CFGSCEN Non-Boot Block Area CRC Configuration Fuse Scan Enable
Value
Description
1
Non-boot block area CRC scan/calculation will not include Configuration Fuse values in its calculation
0
Non-boot block area CRC scan/calculation will include all Configuration Fuse values except
CONFIG14H-CONFIG16L in its calculation
Bit 4 – DATSCEN Non-Boot Block Area CRC Data EEPROM Scan Enable
Value
Description
1
Non-boot block area CRC scan/calculation will not include Data EEPROM values in its calculation
0
Non-boot block area CRC scan/calculation will include Data EEPROM values in its calculation
Bit 3 – SAFSCEN Non-Boot Block Area CRC SAF Area Scan Enable
Value
Description
1
Non-boot block area CRC scan/calculation will not include SAF area of Flash memory in its calculation
if SAF area is enabled
0
Non-boot block area CRC scan/calculation will include SAF area of Flash memory in its calculation if
SAF area is enabled
Bit 2 – APPSCEN Non-Boot Block Area CRC Application Code Area Scan Enable
Value
Description
1
Non-boot block area CRC scan/calculation will not include main application code area of Flash memory
in its calculations
0
Non-boot block area CRC scan/calculation will include main application code area of Flash memory in
its calculations
Bit 1 – BOOTCOE Continue on Error for Boot Block Areas Enable
Value
Description
1
Device will halt if a mismatch is found between expected and calculated CRC values for the boot block
areas of memory
0
Device will continue execution even if a mismatch is found between expected and calculated CRC
values for the boot block areas of memory
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 56
PIC18F27/47/57Q84
Device Configuration
Bit 0 – BOOTSCEN Boot Block Area CRC Scan Enable
Value
Description
1
CRC Scan/calculation on boot block area will not be run
0
CRC Scan/calculation on boot block area will be run
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 57
PIC18F27/47/57Q84
Device Configuration
8.5.12
CRC Boot Polynomial
Name:
Address:
CRC Boot Polynomial
30 000Bh
The Polynomial for the CRC of the boot block segment of memory
Note: The CRC-on-boot module uses a 32-bit polynomial, as such the polynomial configuration spans from
CONFIG12 to CONFIG15, with the MSB of CONFIG12 being the XOR of polynomial term X31 and the LSB of
CONFIG15 being the XOR of polynomial term X0.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
1
R/W
1
R/W
1
23
22
21
R/W
1
R/W
1
R/W
1
15
14
13
R/W
1
R/W
1
R/W
1
7
6
5
R/W
1
R/W
1
R/W
1
28
27
BCRCPOL[31:24]
R/W
R/W
1
1
20
19
BCRCPOL[23:16]
R/W
R/W
1
1
12
11
BCRCPOL[15:8]
R/W
R/W
1
1
4
3
BCRCPOL[7:0]
R/W
R/W
1
1
26
25
24
R/W
1
R/W
1
R/W
1
18
17
16
R/W
1
R/W
1
R/W
1
10
9
8
R/W
1
R/W
1
R/W
1
2
1
0
R/W
1
R/W
1
R/W
1
Bits 31:0 – BCRCPOL[31:0] XOR of Polynomial Term Xn Enable bits
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 58
PIC18F27/47/57Q84
Device Configuration
8.5.13
CRC Boot Seed
Name:
Address:
CRC Boot Seed
30 000Fh
The Seed for the CRC of the boot block segment of memory
Note: The CRC-on-boot module uses a 32-bit polynomial, as such the boot block seed spans from CONFIG16 to
CONFIG19, with the MSB of CONFIG16 being the MSB of the seed and the LSB of CONFIG19 being the LSB of the
seed.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
1
R/W
1
R/W
1
23
22
21
R/W
1
R/W
1
R/W
1
15
14
13
R/W
1
R/W
1
R/W
1
7
6
5
R/W
1
R/W
1
R/W
1
28
27
BCRCSEED[31:24]
R/W
R/W
1
1
20
19
BCRCSEED[23:16]
R/W
R/W
1
1
12
11
BCRCSEED[15:8]
R/W
R/W
1
1
4
3
BCRCSEED[7:0]
R/W
R/W
1
1
26
25
24
R/W
1
R/W
1
R/W
1
18
17
16
R/W
1
R/W
1
R/W
1
10
9
8
R/W
1
R/W
1
R/W
1
2
1
0
R/W
1
R/W
1
R/W
1
Bits 31:0 – BCRCSEED[31:0] Boot Block CRC Seed Field
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 59
PIC18F27/47/57Q84
Device Configuration
8.5.14
CRC Boot Expected Value
Name:
Address:
CRC Boot Expected Value
30 0013h
The Expected Value for the CRC of the boot block segment of memory
Note: The CRC-on-boot module uses a 32-bit polynomial, as such the expected value spans from CONFIG20 to
CONFIG23, with the MSB of CONFIG20 being the MSB of the expected value, and the LSB of CONFIG23 being the
LSB of the expected value.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
1
R/W
1
R/W
1
23
22
21
R/W
1
R/W
1
R/W
1
15
14
13
R/W
1
R/W
1
R/W
1
7
6
5
R/W
1
R/W
1
R/W
1
28
27
BCRCERES[31:24]
R/W
R/W
1
1
20
19
BCRCERES[23:16]
R/W
R/W
1
1
12
11
BCRCERES[15:8]
R/W
R/W
1
1
4
3
BCRCERES[7:0]
R/W
R/W
1
1
26
25
24
R/W
1
R/W
1
R/W
1
18
17
16
R/W
1
R/W
1
R/W
1
10
9
8
R/W
1
R/W
1
R/W
1
2
1
0
R/W
1
R/W
1
R/W
1
Bits 31:0 – BCRCERES[31:0] Boot Block Area CRC Expected Result
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 60
PIC18F27/47/57Q84
Device Configuration
8.5.15
CRC Polynomial
Name:
Address:
CRC Polynomial
30 0017h
The Polynomial for the CRC of the non-boot block segments of memory
Note: The CRC-on-boot module uses a 32-bit polynomial, as such the polynomial configuration spans from
CONFIG24 to CONFIG27, with the MSB of CONFIG24 being the XOR of polynomial term X31 and the LSB of
CONFIG27 being the XOR of polynomial term X0.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
1
R/W
1
R/W
1
23
22
21
R/W
1
R/W
1
R/W
1
15
14
13
R/W
1
R/W
1
R/W
1
7
6
5
R/W
1
R/W
1
R/W
1
28
27
CRCPOL[31:24]
R/W
R/W
1
1
20
19
CRCPOL[23:16]
R/W
R/W
1
1
12
11
CRCPOL[15:8]
R/W
R/W
1
1
4
3
CRCPOL[7:0]
R/W
R/W
1
1
26
25
24
R/W
1
R/W
1
R/W
1
18
17
16
R/W
1
R/W
1
R/W
1
10
9
8
R/W
1
R/W
1
R/W
1
2
1
0
R/W
1
R/W
1
R/W
1
Bits 31:0 – CRCPOL[31:0] XOR of Polynomial Term Xn Enable bits
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 61
PIC18F27/47/57Q84
Device Configuration
8.5.16
CRC Seed
Name:
Address:
CRC Seed
30 001Bh
The Seed for the CRC of the non-boot block segments of memory
Note: The CRC-on-boot module uses a 32-bit polynomial, as such the seed spans from CONFIG28 to CONFIG31,
with the MSB of CONFIG28 being the MSB of the seed and the LSB of CONFIG31 being the LSB of the seed.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
1
R/W
1
R/W
1
23
22
21
R/W
1
R/W
1
R/W
1
15
14
13
R/W
1
R/W
1
R/W
1
7
6
5
R/W
1
R/W
1
R/W
1
28
27
CRCSEED[31:24]
R/W
R/W
1
1
20
19
CRCSEED[23:16]
R/W
R/W
1
1
12
11
CRCSEED[15:8]
R/W
R/W
1
1
4
3
CRCSEED[7:0]
R/W
R/W
1
1
26
25
24
R/W
1
R/W
1
R/W
1
18
17
16
R/W
1
R/W
1
R/W
1
10
9
8
R/W
1
R/W
1
R/W
1
2
1
0
R/W
1
R/W
1
R/W
1
Bits 31:0 – CRCSEED[31:0] Non-Boot Block Area CRC Seed Field
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 62
PIC18F27/47/57Q84
Device Configuration
8.5.17
CRC Expected Value
Name:
Address:
CRC Expected Value
30 001Fh
The Expected Value for the CRC of the non-boot block segments of memory
Note: The CRC-on-boot module uses a 32-bit polynomial, as such the expected value spans from CONFIG32 to
CONFIG35, with the MSB of CONFIG32 being the MSB of the expected value, and the LSB of CONFIG35 being the
LSB of the expected value.
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
1
R/W
1
R/W
1
23
22
21
R/W
1
R/W
1
R/W
1
15
14
13
R/W
1
R/W
1
R/W
1
7
6
5
R/W
1
R/W
1
R/W
1
28
27
CRCERES[31:24]
R/W
R/W
1
1
20
19
CRCERES[23:16]
R/W
R/W
1
1
12
11
CRCERES[15:8]
R/W
R/W
1
1
4
3
CRCERES[7:0]
R/W
R/W
1
1
26
25
24
R/W
1
R/W
1
R/W
1
18
17
16
R/W
1
R/W
1
R/W
1
10
9
8
R/W
1
R/W
1
R/W
1
2
1
0
R/W
1
R/W
1
R/W
1
Bits 31:0 – CRCERES[31:0] Non-Boot Block Area CRC Expected Result
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 63
PIC18F27/47/57Q84
Device Configuration
8.6
Address
00
...
2FFFFF
300000
300001
300002
300003
300004
300005
300006
300007
300008
300009
30000A30
000A
Register Summary - Configuration Settings
Name
7
6
5
4
3
JTAGEN
IVT1WAY
STVREN
CSWEN
MVECEN
PPS1WAY
2
1
0
Reserved
CONFIG1
CONFIG2
CONFIG3
CONFIG4
CONFIG5
CONFIG6
CONFIG7
CONFIG8
CONFIG9
CONFIG10
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
CONFIG11
7:0
30000B30
000B
CRC Boot
Polynomial
30000F30
000F
CRC Boot Seed
30001330 CRC Boot Expected
0013
Value
30001730
0017
CRC Polynomial
30001B30
001B
CRC Seed
30001F30
001F
CRC Expected
Value
8.7
Bit Pos.
RSTOSC[2:0]
FCMENS
FCMENP
FCMEN
BOREN[1:0]
LPBOREN
XINST
LVP
WDTE[1:0]
DEBUG
WDTCCS[2:0]
SAFEN
ODCON
BPEN
CFGSCEN
DATSCEN
WRTAPP
BOOTPOR
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
COE
BBEN
WRTSAF
SAFSCEN
FEXTOSC[2:0]
PR1WAY
CLKOUTEN
PWRTS[1:0]
MCLRE
ZCD
BORV[1:0]
WDTCPS[4:0]
WDTCWS[2:0]
BBSIZE[2:0]
WRTD
WRTC
WRTB
BOOTPINSEL[1:0]
CP
APPSCEN
BOOTCOE
BOOTSCEN
BCRCPOL[7:0]
BCRCPOL[15:8]
BCRCPOL[23:16]
BCRCPOL[31:24]
BCRCSEED[7:0]
BCRCSEED[15:8]
BCRCSEED[23:16]
BCRCSEED[31:24]
BCRCERES[7:0]
BCRCERES[15:8]
BCRCERES[23:16]
BCRCERES[31:24]
CRCPOL[7:0]
CRCPOL[15:8]
CRCPOL[23:16]
CRCPOL[31:24]
CRCSEED[7:0]
CRCSEED[15:8]
CRCSEED[23:16]
CRCSEED[31:24]
CRCERES[7:0]
CRCERES[15:8]
CRCERES[23:16]
CRCERES[31:24]
Register Definitions: Device ID and Revision ID
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 64
PIC18F27/47/57Q84
Device Configuration
8.7.1
Device ID
Name:
Address:
DEVICEID
0x3FFFFE
Device ID Register
Bit
15
14
13
12
11
10
9
8
R
q
R
q
R
q
R
q
3
2
1
0
R
q
R
q
R
q
R
q
DEV[15:8]
Access
Reset
R
q
R
q
R
q
R
q
Bit
7
6
5
4
DEV[7:0]
Access
Reset
R
q
R
q
R
q
R
q
Bits 15:0 – DEV[15:0] Device ID
Device
Device ID
PIC18F27Q84
PIC18F47Q84
PIC18F57Q84
9903h
9904h
9905h
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 65
PIC18F27/47/57Q84
Device Configuration
8.7.2
Revision ID
Name:
Address:
REVISIONID
0x3FFFFC
Revision ID Register
Bit
15
14
13
12
11
R
1
R
0
RO
q
5
4
3
RO
q
RO
q
1010[3:0]
Access
Reset
R
1
Bit
7
Access
Reset
R
0
6
MJRREV[1:0]
RO
RO
q
q
10
9
MJRREV[5:2]
RO
RO
q
q
2
MNRREV[5:0]
RO
RO
q
q
8
RO
q
1
0
RO
q
RO
q
Bits 15:12 – 1010[3:0] Read as 'b1010
These bits are fixed with value 'b1010 for all devices in this family.
Bits 11:6 – MJRREV[5:0] Major Revision ID
These bits are used to identify a major revision (A0, B0, C0, etc.).
Revision A = 'b00 0000
Revision B = 'b00 0001
Bits 5:0 – MNRREV[5:0] Minor Revision ID
These bits are used to identify a minor revision.
Revision A0 = 'b00 0000
Revision B0 = 'b00 0000
Revision B1 = 'b00 0001
Tip: For example, the REVISIONID register value for revision B1 will be 0xA041.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 66
PIC18F27/47/57Q84
Device Configuration
8.8
Register Summary - DEVID/REVID
Address
Name
0x00
...
0x3FFFFB
Reserved
0x3FFFFC
REVISIONID
0x3FFFFE
DEVICEID
Bit Pos.
7
7:0
15:8
7:0
15:8
© 2021 Microchip Technology Inc.
6
5
4
3
MJRREV[1:0]
2
1
0
MNRREV[5:0]
1010[3:0]
MJRREV[5:2]
DEV[7:0]
DEV[15:8]
Preliminary Datasheet
DS40002213D-page 67
PIC18F27/47/57Q84
Memory Organization
9.
Memory Organization
There are three types of memory in PIC18 microcontroller devices:
•
•
•
Program Memory
Data RAM
Data EEPROM
In Harvard architecture devices, the data and program memories use separate buses that allow for concurrent
access of the two memory spaces. The data EEPROM, for practical purposes, can be regarded as a peripheral
device, since it is addressed and accessed through a set of control registers.
Additional detailed information on the operation of the Program Flash Memory and data EEPROM memory is
provided in the “NVM - Nonvolatile Memory Module” section.
9.1
Program Memory Organization
PIC18 microcontrollers implement a 21-bit Program Counter, which is capable of addressing a 2 Mbyte program
memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2
Mbyte address will return all ‘0’s (a NOP instruction).
Refer to the following tables for device memory maps and code protection Configuration bits associated with the
various sections of PFM.
The Reset vector address is at 000000h. The PIC18-Q84 devices feature a vectored interrupt controller with a
dedicated interrupt vector table stored in the program memory. Refer to the “VIC - Vectored Interrupt Controller
Module” chapter for more details.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 68
PIC18F27/47/57Q84
Memory Organization
Figure 9-1. Program and Data Memory Map
Rev. 40-000101G
4/20/2017
Address
Device
PIC18Fx6Q84
PIC18Fx7Q84
00 0000h
to
00 3FFFh
00 4000h
to
00 7FFFh
Program Flash
Memory
(32 KW)(1)
Program Flash
Memory
(64 KW)(1)
00 8000h
to
00 FFFFh
01 0000h
to
01 FFFFh
02 0000h
to
1F FFFFh
20 0000h
to
20 001Fh
20 0020h
to
2B FFFFh
2C 0000h
to
2C 00FFh
2C 0100h
to
2F FFFFh
30 0000h
to
30 0022h
30 0023h
to
37 FFFFh
38 0000h
to
38 03FFh
38 0400h
to
3B FFFFh
3C 0000h
to
3C 000Ah
3C 000Bh
to
3F FFFBh
3F FFFCh
to
3F FFFDh
3F FFFEh
to
3F FFFFh
Note 1:
Not
Present(2)
Not
Present(2)
User IDs (32 Words)(3)
Reserved
Device Information Area (DIA)(3)(5)
Reserved
Configuration Words
(3)
Reserved
Data EEPROM (1024 Bytes)
Reserved
Device Configuration Information(3)(4)(5)
Reserved
Revision ID (1 Word)(3)(4)(5)
Device ID (1 Word)(3)(4)(5)
Storage Area Flash is implemented as the last 128 Words of User Flash, if enabled.
2:
The addresses do not roll over. The region is read as ‘0’.
3:
Not code-protected.
4:
Hard-coded in silicon.
5:
This region cannot be written by the user and it’s not affected by a Bulk Erase.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 69
PIC18F27/47/57Q84
Memory Organization
9.1.1
Memory Access Partition
In the PIC18-Q84 devices, the program memory can be further partitioned into the following sub-blocks:
• Application block
• Boot block
• Storage Area Flash (SAF) block
Refer to the Program Flash Memory Partition table for more details.
9.1.1.1
Application Block
Application block is where the user’s firmware resides by default. Default settings of the Configuration bits (BBEN
= 1 and SAFEN = 1) assign all memory in the program Flash memory area to the application block. The WRTAPP
Configuration bit is used to write-protect the application block.
9.1.1.2
Boot Block
Boot block is an area in program memory that is ideal for storing bootloader code. Code placed in this area can be
executed by the CPU. The boot block can be write-protected, independent of the main application block. The Boot
Block is enabled by the BBEN Configuration bit and size is based on the value of the BBSIZE Configuration bits. The
WRTB Configuration bit is used to write-protect the Boot Block.
9.1.1.3
Storage Area Flash
Storage Area Flash (SAF) is the area in program memory that can be used as data storage. SAF is enabled by the
SAFEN Configuration bit. If enabled, the code placed in this area cannot be executed by the CPU. The SAF block
is placed at the end of memory and spans 128 Words. The WRTSAF Configuration bit is used to write-protect the
Storage Area Flash.
Important: If write-protected locations are written to, memory is not changed and the WRERR bit is set.
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Table 9-1. Program Flash Memory Partition
Partition(3)
Region
Address
BBEN = 1
SAFEN = 1
BBEN = 1
SAFEN = 0
00 0000h
....
Last Boot Block
Memory Address
Last Boot Block
Memory
Address(1) + 1
BBEN = 0
SAFEN = 1
BBEN = 0
SAFEN = 0
Boot Block
Boot Block
Application Block
....
Program Flash
Memory
Application Block
Last Program
Application Block
Memory
(2)
Address - 100h
Last Program
Memory
Address(2) FEh(4)
....
Application Block
Storage Area
Flash Block
Storage Area
Flash Block
Last Program
Memory
Address(2)
Notes:
1. Last Boot Block address is based on BBSIZE bits. Refer to the “Device Configuration” chapter for more
details.
2. For Last Program Memory address refer the table above.
3. Refer to the “Device Configuration” chapter for BBEN and SAFEN bit definitions.
4. Storage Area Flash is implemented as the last 128 Words of user Flash memory.
9.1.2
Program Counter
The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide
and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and
writable. The high byte, or PCH register, contains the PC[15:8] bits; it is not directly readable or writable. Updates to
the PCH register are performed through the PCLATH register. The upper byte is called PCU. This register contains
the PC[20:16] bits; it is also not directly readable or writable. Updates to the PCU register are performed through the
PCLATU register.
The contents of PCLATH and PCLATU are transferred to the Program Counter by any operation that writes PCL.
Similarly, the upper two bytes of the Program Counter are transferred to PCLATH and PCLATU by an operation that
reads PCL. This is useful for computed offsets to the PC (see Computed GOTO).
The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word
instructions, the Least Significant bit of PCL is fixed to a value of ‘0’. The PC increments by two to address sequential
instructions in the program memory.
The CALL, RCALL, GOTO and program branch instructions write to the Program Counter directly. For these
instructions, the contents of PCLATH and PCLATU are not transferred to the Program Counter.
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Memory Organization
9.1.3
Return Address Stack
The return address stack allows any combination of up to 127 program calls and interrupts to occur. The PC is
pushed onto the stack when a CALL or RCALL instruction is executed or an interrupt is Acknowledged. The PC value
is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of
the RETURN or CALL instructions.
The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through
the Top-of-Stack (TOS) Special File registers. Data can also be pushed to, or popped from the stack, using these
registers.
A CALL type instruction causes a push onto the stack; the Stack Pointer is first incremented and the location pointed
to by the Stack Pointer is written with the contents of the PC (already pointing to the instruction following the CALL).
A RETURN type instruction causes a pop from the stack; the contents of the location pointed to by the STKPTR are
transferred to the PC and then the Stack Pointer is decremented.
The Stack Pointer is initialized to 0x00 after all Resets.
9.1.3.1
Top-of-Stack Access
Only the top of the return address stack (TOS) is readable and writable. A set of three registers, TOSU:TOSH:TOSL,
hold the contents of the stack location pointed to by the STKPTR register (see Figure 9-2). This allows users to
implement a software stack if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value
by reading the TOSU:TOSH:TOSL registers. These values can be placed on a user defined software stack. At return
time, the software can return these values to TOSU:TOSH:TOSL and do a return.
The user must disable the Global Interrupt Enable (GIE) bits while accessing the stack to prevent inadvertent stack
corruption.
Figure 9-2. Return Address Stack and Associated Registers
Return Address Stack
1111111
1111110
1111101
STKPTR
0000010
Top-of-Stack Registers
TOSU
00h
TOSH
1Ah
TOSL
34h
0000011
Top-of-Stack
001A34h
0000010
000D58h
0000001
0000000
9.1.3.2
Return Stack Pointer
The STKPTR register contains the Stack Pointer value. The STKOVF (Stack Overflow) Status bit and the STKUNF
(Stack Underflow) Status bit can be accessed using the PCON0 register. The value of the Stack Pointer can be
zero through 127. On Reset, the Stack Pointer value will be zero. The user may read and write the Stack Pointer
value. After the PC is pushed onto the stack 128 times (without popping any values off the stack), the STKOVF bit is
set. The STKOVF bit is cleared by software or by a POR. The action that takes place when the stack becomes full
depends on the state of the STVREN (Stack Overflow Reset Enable) Configuration bit.
If STVREN is set (default), a Reset will be generated and a Stack Overflow will be indicated by the STKOVF bit.
This includes CALL and CALLW instructions, as well as stacking the return address during an interrupt response. The
STKOVF bit will remain set and the Stack Pointer will be set to zero.
If STVREN is cleared, the STKOVF bit will be set on the 128th push and the Stack Pointer will remain at 127 but no
Reset will occur. Any additional pushes will overwrite the 127st push but the STKPTR will remain unchanged.
Setting STKOVF = 1 in software will change the bit, but will not generate a Reset.
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Memory Organization
The STKUNF bit is set when a stack pop returns a value of zero. The STKUNF bit is cleared by software or by POR.
The action that takes place when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset
Enable) Configuration bit.
If STVREN is set (default) and the stack has been popped enough times to unload the stack, the next pop will return
a value of zero to the PC, it will set the STKUNF bit and a Reset will be generated. This condition can be generated
by the RETURN, RETLW and RETFIE instructions.
If STVREN is cleared, the STKUNF bit will be set, but no Reset will occur.
Important: Returning a value of zero to the PC on an underflow has the effect of vectoring the program
to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. This
is not the same as a Reset, as the contents of the SFRs are not affected.
9.1.3.3
PUSH and POP Instructions
Since the Top-of-Stack is readable and writable, the ability to push values onto the stack and pull values off the
stack without disturbing normal program execution is a desirable feature. The PIC18 instruction set includes two
instructions, PUSH and POP, that permit the TOS to be manipulated under software control. TOSU, TOSH and TOSL
can be modified to place data or a return address on the stack.
The PUSH instruction places the current PC value onto the stack. This increments the Stack Pointer and loads the
current PC value onto the stack.
The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto
the stack then becomes the TOS value.
9.1.3.4
Fast Register Stack
There are three levels of fast stack registers available - one for CALL type instructions and two for interrupts. A fast
register stack is provided for the STATUS, WREG and BSR registers, to provide a “fast return” option for interrupts.
It is loaded with the current value of the corresponding register when the processor vectors for an interrupt. All
interrupt sources will push values into the stack registers. The values in the registers are then loaded back into their
associated registers if the RETFIE, FAST instruction is used to return from the interrupt. Refer to “Call Shadow
Register” section for interrupt call shadow registers.
The following example shows a source code example that uses the Fast Register Stack during a subroutine call and
return.
Example 9-1. Fast Register Stack Code Example
CALL SUB1, FAST ;STATUS, WREG, BSR SAVED IN FAST REGISTER STACK
•
•
SUB1:
•
•
RETURN, FAST
;RESTORE VALUES SAVED IN FAST REGISTER STACK
9.1.4
Look-up Tables in Program Memory
There may be programming situations that require the creation of data structures, or look-up tables, in program
memory. For PIC18 devices, look-up tables can be implemented in two ways:
9.1.4.1
•
Computed GOTO
•
Table Reads
Computed GOTO
A computed GOTO is accomplished by adding an offset to the Program Counter. An example is shown in the following
code example.
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Memory Organization
A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW nn instructions. The W register
is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is
the ADDWF PCL instruction. The next instruction executed will be one of the RETLW nn instructions that returns the
value ‘nn’ to the calling function.
The offset value (in WREG) specifies the number of bytes that the Program Counter will advance and must be
multiples of two (LSb = 0).
In this method, only one data byte may be stored in each instruction location and room on the return address stack is
required.
Example 9-2. Computed GOTO Using an Offset Value
RLNCF
CALL
ORG
TABLE:
ADDWF
RETLW
RETLW
RETLW
.
.
.
9.1.4.2
OFFSET, W
TABLE
; W must be an even number, Max OFFSET = 127
nn00h
; 00 in LSByte ensures no addition overflow
PCL
A
B
C
;
;
;
;
Add OFFSET to program counter
Value @ OFFSET=0
Value @ OFFSET=1
Value @ OFFSET=2
Program Flash Memory Access
A more compact method of storing data in program memory allows two bytes of data to be stored in each instruction
location.
Look-up table data may be stored two bytes per program word by using table reads and writes. The Table Pointer
(TBLPTR) register specifies the byte address and the Table Latch (TABLAT) register contains the data that is read
from or written to program memory. Data is transferred to or from program memory one byte at a time.
Table read and table write operations are discussed further in the “Table Read Operations” and “Table Write
Operations” sections in the “NVM - Nonvolatile Memory Module” chapter.
9.2
Device Information Area
The Device Information Area (DIA) is a dedicated region in the program memory space. The DIA contains the
calibration data for the internal temperature indicator module, the Microchip Unique Identifier words, and the Fixed
Voltage Reference voltage readings measured in mV.
The complete DIA table is shown below, followed by a description of each region and its functionality. The data is
mapped from 2C0000h to 2C003Fh. These locations are read-only and cannot be erased or modified. The data is
programmed into the device during manufacturing.
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Memory Organization
Table 9-2. Device Information Area
Address Range
Name of Region
Standard Device Information
MUI0
MUI1
MUI2
MUI3
2C0000h-2C0011h
MUI4
Microchip Unique Identifier (9 Words)
MUI5
MUI6
MUI7
MUI8
2C0012h-2C0013h
MUI9
Reserved (1 Word)
EUI0
EUI1
EUI2
2C0014h-2C0023h
EUI3
EUI4
Optional External Unique Identifier (8 Words)
EUI5
EUI6
EUI7
× 256
Gain = 0.1C
count (low range setting)
2C0024h-2C0025h
TSLR1(1)
2C0026h-2C0027h
TSLR2(1)
Temperature indicator ADC reading at 90°C (low
range setting)
2C0028h-2C0029h
TSLR3(1)
Offset (low range setting)
2C002Ah-2C002Bh
TSHR1(2)
2C002Ch-2C002Dh
TSHR2(2)
× 256
Gain = 0.1C
count (high range setting)
2C002Eh-2C002Fh
TSHR3(2)
Offset (high range setting)
2C0030h-2C0031h
FVRA1X
ADC FVR1 Output voltage for 1x setting (in mV)
2C0032h-2C0033h
FVRA2X
ADC FVR1 Output Voltage for 2x setting (in mV)
2C0034h-2C0035h
FVRA4X
ADC FVR1 Output Voltage for 4x setting (in mV)
2C0036h-2C0037h
FVRC1X
Comparator FVR2 output voltage for 1x setting (in
mV)
2C0038h-2C0039h
FVRC2X
Comparator FVR2 output voltage for 2x setting (in
mV)
2C003Ah-2C003Bh
FVRC4X
Comparator FVR2 output voltage for 4x setting (in
mV)
© 2021 Microchip Technology Inc.
Temperature indicator ADC reading at 90°C (high
range setting)
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Memory Organization
...........continued
Address Range
Name of Region
2C003Ch-2C003Fh
Standard Device Information
Unassigned (2 Words)
Notes:
1. TSLR: Address 2C0024h-2C0029h store the measurements for the low range setting of the temperature
sensor at VDD = 3V, VREF+ = 2.048V from FVR1.
2. TSHR: Address 2C002Ah-2C002Fh store the measurements for the high range setting of the temperature
sensor at VDD = 3V, VREF+ = 2.048V from FVR1.
9.2.1
Microchip Unique Identifier (MUI)
This family of devices is individually encoded during final manufacturing with a Microchip Unique Identifier (MUI). The
MUI cannot be user-erased. This feature allows for manufacturing traceability of Microchip Technology devices in
applications where this is required. It may also be used by the application manufacturer for a number of functions that
require unverified unique identification, such as:
• Tracking the device
• Unique serial number
The MUI is stored in read-only locations, located between 2C0000h to 2C0013h in the DIA space. The DIA table lists
the addresses of the identifier words.
Important: For applications that require verified unique identification, contact the Microchip Technology
sales office to create a Serialized Quick Turn Programming option.
9.2.2
External Unique Identifier (EUI)
The EUI data is stored at locations 2C0014h-2C0023h in the program memory region. This region is an
optional space for placing application specific information. The data is coded per customer requirements during
manufacturing. The EUI cannot be erased by a Bulk Erase command.
Important: Data is stored in this address range on receiving a request from the customer. The customer
may contact the local sales representative or Field Applications Engineer, and provide them the unique
identifier information that is required to be stored in this region.
9.2.3
Standard Parameters for the Temperature Sensor
The purpose of the temperature indicator module is to provide a temperature-dependent voltage that can be
measured by an analog module. The DIA table contains standard parameters for the temperature sensor for low
and high range. The values are measured during test and are unique to each device. The calibration data can be
used to plot the approximate sensor output voltage, VTSENSE vs. Temperature curve. The “Temperature Indicator
Module” chapter explains the operation of the Temperature Indicator module and defines terms such as the low
range and high range settings of the sensor.
9.2.4
Fixed Voltage Reference Data
The DIA stores measured FVR voltages for this device in mV for the different buffer settings of 1x, 2x or 4x at
program memory locations. For more information on the FVR, refer to the “FVR - Fixed Voltage Reference”
chapter.
9.3
Device Configuration Information
The Device Configuration Information (DCI) is a dedicated region in the program memory mapped from 3C0000h
to 3C0009h. The data stored in these location is read-only and cannot be erased. Refer to the table below for
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Preliminary Datasheet
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Memory Organization
the complete DCI table address and description. The DCI holds information about the device, which is useful for
programming and Bootloader applications.
The erase size is the minimum erasable unit in the PFM, expressed as rows. The total device Flash memory capacity
is (Erase size * Number of user-erasable pages).
Table 9-3. Device Configuration Information for PIC18-Q84 Devices
Address
Name
Description
3C0000h-3C0001h
ERSIZ
3C0002h-3C0003h
Value
Units
PIC18F26/46/56Q84
PIC18F27/47/57Q84
Erase page size
128
128
Words
WLSIZ
Number of write
latches per row
0
0
Words
3C0004h-3C0005h
URSIZ
Number of usererasable pages
256
512
Pages
3C0006h-3C0007h
EESIZ
Data EEPROM
memory size
1024
1024
Bytes
3C0008h-3C0009h
PCNT
Pin count
28/40(1)/48
28/40(1)/48
Pins
Note:
1. Pin count of 40 is also used for 44-pin part.
9.4
Data Memory Organization
Important: The operation of some aspects of data memory are changed when the PIC18 extended
instruction set is enabled. See PIC18 Instruction Execution and the Extended Instruction Set for more
information.
The data memory in PIC18 devices is implemented as static RAM. The memory space is divided into as many as
64 banks that contain 256 bytes each. The figure below shows the data memory organization for all devices in the
device family.
The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The SFRs
are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and
scratchpad operations in the user’s application. Any read of an unimplemented location will read as ‘0’.
The value in the Bank Select Register (BSR) determines which bank is being accessed. The instruction set and
architecture allow operations across all banks. The entire data memory may be accessed by Direct, Indirect or
Indexed Addressing modes. Addressing modes are discussed later in this subsection.
To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, PIC18 devices
implement an Access Bank. This is a virtual 256-byte memory space that provides fast access to SFRs and the top
half of GPR Bank 5 without using the Bank Select Register. The Access Bank section provides a detailed description
of the Access RAM.
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Preliminary Datasheet
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PIC18F27/47/57Q84
Memory Organization
Figure 9-3. Data Memory Map
PIC18F
Bank
BSR
addr[13:8]
addr[7:0]
0
'b00 0000
0x00-0x5F
41
'b10 1001 0x00-0xFF
1
'b00 0001
0x00-0xFF
42
'b10 1010 0x00-0xFF
2
'b00 0010
0x00-0xFF
43
'b10 1011 0x00-0xFF
3
'b00 0011
0x00-0xFF
44
'b10 1100 0x00-0xFF
'b00 0100
0x00-0x5F
Virtual Access Bank
45
'b10 1101 0x00-0xFF
'b00 0100
0x60-0xFF
Access RAM
0x00-0x5F
46
'b10 1110 0x00-0xFF
'b00 0101
0x00-0x5F
Fast SFR
0x60-0xFF
47
'b10 1111 0x00-0xFF
'b00 0101
0x60-0xFF
48
'b11 0000 0x00-0xFF
6
'b00 0110
0x00-0xFF
GPR
49
'b11 0001 0x00-0xFF
7
'b00 0111
0x00-0xFF
SFR
50
'b11 0010 0x00-0xFF
8
'b00 1000
0x00-0xFF
Buffer RAM
51
'b11 0011 0x00-0xFF
9
'b00 1001
0x00-0xFF
CAN RAM
52
'b11 0100 0x00-0xFF
10
'b00 1010
0x00-0xFF
Unimplemented
53
'b11 0101 0x00-0xFF
11
'b00 1011
0x00-0xFF
54
'b11 0110 0x00-0xFF
12
'b00 1100
0x00-0xFF
55
'b11 0111 0x00-0xFF
13
'b00 1101
0x00-0xFF
56
'b11 1000 0x00-0xFF
14
'b00 1110
0x00-0xFF
57
'b11 1001 0x00-0xFF
15
0x00-0xFF
58
'b11 1010 0x00-0xFF
16
'b00 1111
'b01 0000
0x00-0xFF
59
'b11 1011 0x00-0xFF
17
'b01 0001
0x00-0xFF
60
'b11 1100 0x00-0xFF
18
'b01 0010
0x00-0xFF
61
'b11 1101 0x00-0xFF
19
'b01 0011
0x00-0xFF
62
'b11 1110 0x00-0xFF
20
'b01 0100
0x00-0xFF
63
'b11 1111 0x00-0xFF
21
'b01 0101
0x00-0xFF
22
'b01 0110
0x00-0xFF
23
'b01 0111
0x00-0xFF
24
'b01 1000
0x00-0xFF
25
'b01 1001
0x00-0xFF
26
'b01 1010
0x00-0xFF
27
'b01 1011
0x00-0xFF
28
'b01 1100
0x00-0xFF
29
'b01 1101
0x00-0xFF
30
'b01 1110
0x00-0xFF
31
'b01 1111
0x00-0xFF
32
'b10 0000
0x00-0xFF
33
'b10 0001
0x00-0xFF
34
'b10 0010
0x00-0xFF
35
'b10 0011
0x00-0xFF
36
'b10 0100
0x00-0xFF
37
'b10 0101
0x00-0xFF
38
'b10 0110
0x00-0xFF
39
'b10 0111
0x00-0xFF
40
'b10 1000
0x00-0xFF
4
5
x6Q84
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Bank
x7Q84
Preliminary Datasheet
BSR
addr[13:8]
addr[7:0]
PIC18F
x6Q84
x7Q84
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Memory Organization
9.4.1
Bank Select Register
To rapidly access the RAM space in PIC18 devices, the memory is split using the banking scheme. This divides
the memory space into contiguous banks of 256 bytes each. Depending on the instruction, each location can be
addressed directly by its full address, or an 8-bit low-order address and a bank pointer.
Most instructions in the PIC18 instruction set make use of the bank pointer known as the Bank Select Register
(BSR). This SFR holds the Most Significant bits of a location’s address; the instruction itself includes the eight Least
Significant bits. The BSR can be loaded directly by using the MOVLB instruction.
The value of the BSR indicates the bank in data memory being accessed; the eight bits in the instruction show the
location in the bank and can be thought of as an offset from the bank’s lower boundary. The relationship between the
BSR’s value and the bank division in data memory is shown in Figure 9-4.
When writing the firmware in assembly, the user must always be careful to ensure that the proper bank is selected
before performing a data read or write. When using the C compiler to write the firmware, the BSR is tracked and
maintained by the compiler.
While any bank can be selected, only those banks that are actually implemented can be read or written to. Writes to
unimplemented banks are ignored, while reads from unimplemented banks will return ‘0’. Refer Figure 9-3 for a list of
implemented banks.
Figure 9-4. Use of the Bank Select Register (Direct Addressing)
7
0
0
0
0
0
Rev. 30-000108B
02/28/2019
Data Memory
BSR(1)
0
0
1
0000h
0
0100h
Bank Select
0200h
Bank 0
Bank 1
Bank 2
0300h
00h
FFh
00h
From Opcode
7
1
1
1
1
1
1
0
1
1
FFh
00h
FFh
Bank 3
through
Bank 61
3E00h
Bank 62
3F00h
3FFFh
Note 1:
9.4.2
Bank 63
00h
FFh
00h
FFh
The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR value) to
the registers of the Access Bank.
Access Bank
While the use of the BSR with an embedded 8-bit address allows users to address the entire range of data memory, it
also means that the user must always ensure that the correct bank is selected. Otherwise, data may be read from or
written to the wrong location. Verifying and/or changing the BSR for each read or write to data memory can become
very inefficient.
To streamline access for the most commonly used data memory locations, the data memory is configured with a
virtual Access Bank, which allows users to access a mapped block of memory without specifying a BSR. The Access
Bank consists of the first 96 bytes of memory in Bank 5 (0500h-055Fh) and the last 160 bytes of memory in Bank 4
(0460h-04FFh). The upper half is known as the “Access RAM” and is composed of GPRs. The lower half is where
the device’s SFRs are mapped. These two areas are mapped contiguously as the virtual Access Bank and can be
addressed in a linear fashion by an 8-bit address (see Data Memory Map).
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Preliminary Datasheet
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Memory Organization
The Access Bank is used by core PIC18 instructions that include the Access RAM bit (the ‘a’ parameter in the
instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the
data memory address. When ‘a’ is ‘0’, however, the instruction ignores the BSR and uses the Access Bank address
map.
Using this “forced” addressing allows the instruction to operate on a data address in a single cycle, without updating
the BSR first. Access RAM also allows for faster and more code efficient context saving and switching of variables.
The mapping of the Access Bank is slightly different when the extended instruction set is enabled (XINST
Configuration bit = 1). This is discussed in more detail in the Mapping the Access Bank in Indexed Liberal Offset
Mode section.
9.5
Data Addressing Modes
Important: The execution of some instructions in the core PIC18 instruction set are changed when the
PIC18 extended instruction set is enabled. See Data Memory and the Extended Instruction Set for more
information.
Information in the data memory space can be addressed in several ways. For most instructions, the Addressing
mode is fixed. Other instructions may use up to three modes, depending on which operands are used and whether or
not the extended instruction set is enabled.
The Addressing modes are:
•
•
•
•
Inherent
Literal
Direct
Indirect
An additional Addressing mode, Indexed Literal Offset, is available when the extended instruction set is enabled
(XINST Configuration bit = 1). Its operation is discussed in greater detail in Indexed Addressing with Literal Offset.
9.5.1
Inherent and Literal Addressing
Many PIC18 control instructions do not need any argument at all; they either perform an operation that globally
affects the device or they operate implicitly on one register. This Addressing mode is known as Inherent Addressing.
Examples include SLEEP, RESET and DAW.
Other instructions work in a similar way but require an additional explicit argument in the opcode. This is known
as Literal Addressing mode because they require some literal value as an argument. Examples include ADDLW and
MOVLW, which respectively, add or move a literal value to the W register. Other examples include CALL and GOTO,
which include a program memory address.
9.5.2
Direct Addressing
Direct Addressing specifies all or part of the source and/or destination address of the operation within the opcode
itself. The options are specified by the arguments accompanying the instruction.
In the core PIC18 instruction set, bit-oriented and byte-oriented instructions use some version of Direct Addressing
by default. All of these instructions include some 8-bit literal address as their Least Significant Byte. This address
specifies either a register address in one of the banks of data RAM (see Data Memory Organization) or a location in
the Access Bank (see Access Bank) as the data source for the instruction.
The Access RAM bit ‘a’ determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR (see Bank
Select Register) are used with the address to determine the complete 12-bit address of the register. When ‘a’ is ‘0’,
the address is interpreted as being a register in the Access Bank.
The destination of the operation’s results is determined by the destination bit ‘d’. When ‘d’ is ‘1’, the results are stored
back in the source register, overwriting its original contents. When ‘d’ is ‘0’, the results are stored in the W register.
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Instructions without the ‘d’ argument have a destination that is implicit in the instruction; their destination is either the
target register being operated on or the W register.
9.5.3
Indirect Addressing
Indirect Addressing allows the user to access a location in data memory without giving a fixed address in the
instruction. This is done by using File Select Registers (FSRs) as pointers to the locations which are to be read
or written. Since the FSRs are themselves located in RAM as Special File Registers, they can also be directly
manipulated under program control. This makes FSRs very useful in implementing data structures, such as tables
and arrays in data memory.
The registers for Indirect Addressing are also implemented with Indirect File Operands (INDFs) that permit automatic
manipulation of the pointer value with auto-incrementing, auto-decrementing or offsetting with another value. This
allows for efficient code, using loops, such as the following example of clearing an entire RAM bank.
Example 9-3. How to Clear RAM (Bank 1) Using Indirect Addressing
LFSR
NEXT:
CLRF
BTFSS
BRA
FSR0,100h
; Set FSR0 to beginning of Bank1
POSTINC0
; Clear location in Bank1 then increment FSR0
FSR0H,1
NEXT
; Has high FSR0 byte incremented to next bank?
; NO, clear next byte in Bank1
CONTINUE:
9.5.3.1
; YES, continue
FSR Registers and the INDF Operand
At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represent a pair of 8-bit
registers, FSRnH and FSRnL. Each FSR pair holds the full address of the RAM location. The FSR value can address
the entire range of the data memory in a linear fashion. The FSR register pairs, then, serve as pointers to data
memory locations.
Indirect Addressing is accomplished with a set of Indirect File Operands, INDF0 through INDF2. These can be
thought of as “virtual” registers; they are mapped in the SFR space but are not physically implemented. Reading
or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1,
for example, reads the data at the address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as
operands actually use the contents of their corresponding FSR as a pointer to the instruction’s target. The INDF
operand is just a convenient way of using the pointer.
Because Indirect Addressing uses a full address, the FSR value can target any location in any bank regardless of
the BSR value. However, the Access RAM bit must be cleared to zero to ensure that the INDF register in Access
space is the object of the operation instead of a register in one of the other banks. The assembler default value for
the Access RAM bit is zero when targeting any of the indirect operands.
9.5.3.2
FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW
In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these
are “virtual” registers that cannot be directly read or written. Accessing these registers actually accesses the location
to which the associated FSR register pair points, and also performs a specific action on the FSR value. They are:
•
•
•
•
POSTDEC: accesses the location to which the FSR points, then automatically decrements the FSR by 1
afterwards
POSTINC: accesses the location to which the FSR points, then automatically increments the FSR by 1
afterwards
PREINC: automatically increments the FSR by one, then uses the location to which the FSR points in the
operation
PLUSW: adds the signed value of the W register (range of -127 to 128) to that of the FSR and uses the location
to which the result points in the operation.
In this context, accessing an INDF register uses the value in the associated FSR register without changing it.
Similarly, accessing a PLUSW register gives the FSR value an offset by that in the W register; however, neither W
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nor the FSR is actually changed in the operation. Accessing the other virtual registers changes the value of the FSR
register.
Figure 9-5. Indirect Addressing
Data Memory
0000h
ADDWF, INDF1, 0
Using an instruction with one of the
indirect addressing registers as the
operand....
0100h
0200h
...uses the 14-bit address stored in
the FSR pair associated with that
register....
FSR1H:FSR1L
7
0
x x 11 1 1 1 0
7
Bank 1
Bank 2
0300h
00h
FFh
00h
FFh
00h
FFh
0
Bank 3
through
Bank 61
1 1 0 0 1 1 0 0
...to determine the data memory
location to be used in that operation.
In this case, the FSR1 pair contains
3ECCh. This means the contents of
location 3ECCh will be added to that
of the W register and stored back in
3ECCh.
Bank 0
Rev. 30-000109A
4/18/2017
3E00h
Bank 62
3F00h
3FFFh
Bank 63
00h
FFh
00h
FFh
Operations on the FSRs with POSTDEC, POSTINC and PREINC affect the entire register pair; that is, rollovers of
the FSRnL register from FFh to 00h carry over to the FSRnH register. On the other hand, results of these operations
do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.).
The PLUSW register can be used to implement a form of Indexed Addressing in the data memory space. By
manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In
some
applications, this can be used to implement some powerful program control structure, such as software stacks,
inside of data memory.
9.5.3.3
Operations by FSRs on FSRs
Indirect Addressing operations that target other FSRs or virtual registers represent special cases. For example, using
an FSR to point to one of the virtual registers will not result in successful operations. As a specific case, assume that
FSR0H:FSR0L contains the address of INDF1. Attempts to read the value of the INDF1 using INDF0 as an operand
will return 00h. Attempts to write to INDF1 using INDF0 as the operand will result in a NOP.
On the other hand, using the virtual registers to write to an FSR pair may not occur as planned. In these cases, the
value will be written to the FSR pair but without any incrementing or decrementing. Thus, writing to either the INDF2
or POSTDEC2 register will write the same value to the FSR2H:FSR2L.
Since the FSRs are physical registers mapped in the SFR space, they can be manipulated through all direct
operations. Users need to proceed cautiously when working on these registers, particularly if their code uses Indirect
Addressing.
Similarly, operations by Indirect Addressing are generally permitted on all other SFRs. Users need to exercise the
appropriate caution that they do not inadvertently change settings that might affect the operation of the device.
9.6
Data Memory and the Extended Instruction Set
Enabling the PIC18 extended instruction set (XINST Configuration bit = 1) significantly changes certain aspects of
data memory and its addressing. Specifically, the use of the Access Bank for many of the core PIC18 instructions is
different; this is due to the introduction of a new Addressing mode for the data memory space.
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What does not change is just as important. The size of the data memory space is unchanged, as well as its linear
addressing. The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect
Addressing mode; inherent and literal instructions do not change at all. Indirect addressing with FSR0 and FSR1 also
remain unchanged.
9.6.1
Indexed Addressing with Literal Offset
Enabling the PIC18 extended instruction set changes the behavior of Indirect Addressing using the FSR2 register
pair within Access RAM. Under the proper conditions, instructions that use the Access Bank – that is, most
bit-oriented and byte-oriented instructions – can invoke a form of Indexed Addressing using an offset specified in
the instruction. This special Addressing mode is known as Indexed Addressing with Literal Offset, or Indexed Literal
Offset mode.
When using the extended instruction set, this Addressing mode requires the following:
•
The use of the Access Bank is forced (‘a’ = 0) and
•
The file address argument is less than or equal to 5Fh.
Under these conditions, the file address of the instruction is not interpreted as the lower byte of an address (used
with the BSR in Direct Addressing), or as an 8-bit address in the Access Bank. Instead, the value is interpreted as an
offset value to an Address Pointer, specified by FSR2. The offset and the contents of FSR2 are added to obtain the
target address of the operation.
9.6.2
Instructions Affected by Indexed Literal Offset Mode
Any of the core PIC18 instructions that can use Direct Addressing are potentially affected by the Indexed Literal
Offset Addressing mode. This includes all byte-oriented and bit-oriented instructions, or almost one-half of the
standard PIC18 instruction set. Instructions that only use Inherent or Literal Addressing modes are unaffected.
Additionally, byte-oriented and bit-oriented instructions are not affected if they do not use the Access Bank (Access
RAM bit is ‘1’), or include a file address of 60h or above. Instructions meeting these criteria will continue to execute
as before. A comparison of the different possible Addressing modes when the extended instruction set is enabled is
shown in the following figure.
Those who desire to use byte-oriented or bit-oriented instructions in the Indexed Literal Offset mode need to note the
changes to assembler syntax for this mode. This is described in more detail in the “Extended Instruction Syntax”
section.
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Figure 9-6. Comparing Addressing Options for Bit-Oriented and Byte-Oriented Instructions (Extended
Instruction Set Enabled)
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
When ‘a’ = 0 and f ≥ 60h
The instruction executes in
Direct Forced mode. ‘f’ is interpreted as a location in the
Access RAM between 060h
and 0FFh. This is the same as
locations 460h to 4FFh
(Bank4) of data memory.
Locations below 60h are not
available in this Addressing
mode.
0000h
Bank 0 - 3
0400h
0460h
04FFh
Bank 4
00h
Access
SFRs
60h
FFh
Bank 5-63
Access RAM
3FFFh
Data Memory
When ‘a’ = 0 and f ≤ 5 Fh
The instruction executes in
Indexed Literal Offset mode. ‘f’
is interpreted as an offset to the
address value in FSR2. The
two are added together to
obtain the address of the target
register for the instruction. The
address can be anywhere in
the data memory space.
0000h
Bank 0 - 3
0400h
Bank 4
0460h
04FFh
0500h
0560h
Access
SFRs
Access
GPR
Bank 5-63
FSR2H
3FFFh
9.6.3
FSR2L
Data Memory
ADDWF [k], d
where ‘k’ is the same as ‘f’.
The instruction executes in
Direct mode (also known as
Direct Long mode). ‘f’ is interpreted as a location in one of
the 63 banks of the data
memory space. The bank is
designated by the Bank
Select Register (BSR). The
address can be in any
implemented bank in the data
memory space.
ffff ffff
+
Note that in this mode, the
correct syntax is now:
When ‘a’ = 1 (all values of f)
0010 01da
0000h
Bank 0 - 3
0400h
Bank 4
0460h
04FFh
Access
SFRs
BSR
0000 1010
Bank 5-63
Bank 10
0010 01da
ffff ffff
3FFFh
Data Memory
Mapping the Access Bank in Indexed Literal Offset Mode
The use of Indexed Literal Offset Addressing mode effectively changes how the first 96 locations of Access RAM
(00h to 5Fh) are mapped. Rather than containing just the contents of the top section of Bank 5, this mode maps the
contents from a user defined “window” that can be located anywhere in the data memory space. The value of FSR2
establishes the lower boundary of the addresses mapped into the window, while the upper boundary is defined by
FSR2 plus 95 (5Fh). Addresses in the Access RAM above 5Fh are mapped as previously described (see Access
Bank). An example of Access Bank remapping in this Addressing mode is shown in the following figure.
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Figure 9-7. Remapping the Access Bank with Indexed Literal Offset Addressing
EXAMPLE:
ADDWF, f, d, a
FSR2H:FSR2L = 0x0A20
0000h
Bank 0 - 3
0400h
Bank 4
0460h
Locations in the region
from the FSR2 pointer
(A20h) to the pointer plus
05Fh (A7Fh) are mapped
to the Access RAM
(000h-05Fh).
Special File Registers at
460h through 4FFh are
mapped to 60h through
FFh, as usual.
Bank 4 addresses below
5Fh can still be addressed
by using the BSR.
Access
SFRs
0500h
00h
Bank 10 Window
Bank 5-9
60h
SFRs
0A20h
Bank 10
Window
0A7Fh
Bank 10
FFh
Access RAM
Bank 11 - 63
3FFFh
Data Memory
Remapping of the Access Bank applies only to operations using the Indexed Literal Offset mode. Operations that use
the BSR (Access RAM bit is ‘1’) will continue to use Direct Addressing as before.
9.6.4
PIC18 Instruction Execution and the Extended Instruction Set
Enabling the extended instruction set adds additional commands to the existing PIC18 instruction set. These
instructions are executed as described in the “Extended Instruction Set” section.
9.7
Register Definitions: Memory Organization
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9.7.1
PCL
Name:
Address:
PCL
0x4F9
Low byte of the Program Counter Register
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
PCL[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – PCL[7:0] Provides direct read and write access to the Program Counter
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9.7.2
PCLAT
Name:
Address:
PCLAT
0x4FA
Program Counter Latches
Holding register for bits [21:9] of the Program Counter (PC). Reads of the PCL register transfer the upper PC bits to
the PCLAT register. Writes to PCL register transfer the PCLAT value to the PC.
Bit
15
14
13
Access
Reset
Bit
Access
Reset
7
6
5
R/W
0
R/W
0
R/W
0
12
11
R/W
0
R/W
0
4
3
PCLATH[7:0]
R/W
R/W
0
0
10
PCLATU[4:0]
R/W
0
9
8
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 12:8 – PCLATU[4:0] Upper PC Latch Register
Holding register for Program Counter [21:17]
Bits 7:0 – PCLATH[7:0] High PC Latch Register
Holding register for Program Counter [16:8]
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9.7.3
TOS
Name:
Address:
TOS
0x4FD
Top-of-Stack Register
Contents of the stack pointed to by the STKPTR register. This is the value that will be loaded into the Program
Counter upon a RETURN or RETFIE instruction.
Bit
23
22
21
Access
Reset
Bit
15
14
13
20
19
R/W
0
12
17
16
R/W
0
18
TOS[20:16]
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TOS[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
TOS[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 20:0 – TOS[20:0] Top-of-Stack
Notes: The individual bytes in this multi-byte register can be accessed with the following register names:
• TOSU: Accesses the upper byte TOS[20:16]
• TOSH: Accesses the high byte TOS[15:8]
• TOSL: Accesses the low byte TOS[7:0]
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9.7.4
STKPTR
Name:
Address:
STKPTR
0x4FC
Stack Pointer Register
Bit
Access
Reset
7
6
5
4
R/W
0
R/W
0
R/W
0
3
STKPTR[6:0]
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 6:0 – STKPTR[6:0] Stack Pointer Location
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9.7.5
WREG
Name:
Address:
WREG
0x4E8
Working Data Register
Bit
7
6
5
4
3
2
1
0
R/W
x
R/W
x
R/W
x
R/W
x
WREG[7:0]
Access
Reset
R/W
x
R/W
x
R/W
x
R/W
x
Bits 7:0 – WREG[7:0]
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9.7.6
INDF
Name:
Address:
INDFx
0x4EF,0x4E7,0x4DF
Indirect Data Register
This is a virtual register. The GPR/SFR register addressed by the FSRx register is the target for all operations
involving the INDFx register.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
INDF[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – INDF[7:0] Indirect data pointed to by the FSRx register
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9.7.7
POSTDEC
Name:
Address:
POSTDECx
0x4ED,0x4E5,0x4DD
Indirect Data Register with post decrement
This is a virtual register. The GPR/SFR register addressed by the FSRx register is the target for all operations
involving the POSTDECx register. FSRx is decrememted after the read or write operation.
Bit
Access
Reset
7
6
5
R/W
0
R/W
0
R/W
0
4
3
POSTDEC[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – POSTDEC[7:0]
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9.7.8
POSTINC
Name:
Address:
POSTINCx
0x4EE,0x4E6,0x4DE
Indirect Data Register with post increment
This is a virtual register. The GPR/SFR register addressed by the FSRx register is the target for all operations
involving the POSTINCx register. FSRx is incremented after the read or write operation.
Bit
Access
Reset
7
6
5
R/W
0
R/W
0
R/W
0
4
3
POSTINC[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – POSTINC[7:0]
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9.7.9
PREINC
Name:
Address:
PREINCx
0x4EC,0x4E4,0x4DC
Indirect Data Register with pre-increment
This is a virtual register. The GPR/SFR register addressed by the FSRx register plus 1 is the target for all operations
involving the PREINCx register. FSRx is incremented before the read or write operation.
Bit
Access
Reset
7
6
5
R/W
0
R/W
0
R/W
0
4
3
PREINC[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – PREINC[7:0]
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9.7.10
PLUSW
Name:
Address:
PLUSWx
0x4EB,0x4E3,0x4DB
Indirect Data Register with WREG offset
This is a virtual register. The GPR/SFR register addressed by the sum of the FSRx register plus the signed value of
the W register is the target for all operations involving the PLUSWx register.
Bit
Access
Reset
7
6
5
R/W
0
R/W
0
R/W
0
4
3
PLUSW[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – PLUSW[7:0]
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9.7.11
FSR
Name:
Address:
FSRx
0x4E9,0x4E1,0x4D9
Indirect Address Register
The FSR value is the address of the data to which the INDF register points.
Bit
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
FSRH[5:0]
Access
Reset
Bit
7
6
R/W
0
R/W
0
5
4
FSRL[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 13:8 – FSRH[5:0] Most Significant address of INDF data
Bits 7:0 – FSRL[7:0] Least Significant address of INDF data
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9.7.12
BSR
Name:
Address:
BSR
0x4E0
Bank Select Register
The BSR indicates the data memory bank of the GPR address.
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
BSR[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 5:0 – BSR[5:0] Most Significant bits of the data memory address
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9.8
Register Summary - Memory Organization
Address
Name
0x00
...
0x04D8
Reserved
0x04D9
FSR2
0x04DB
0x04DC
0x04DD
0x04DE
0x04DF
0x04E0
PLUSW2
PREINC2
POSTDEC2
POSTINC2
INDF2
BSR
0x04E1
FSR1
0x04E3
0x04E4
0x04E5
0x04E6
0x04E7
0x04E8
PLUSW1
PREINC1
POSTDEC1
POSTINC1
INDF1
WREG
0x04E9
FSR0
0x04EB
0x04EC
0x04ED
0x04EE
0x04EF
0x04F0
...
0x04F8
0x04F9
PLUSW0
PREINC0
POSTDEC0
POSTINC0
INDF0
0x04FA
PCLAT
0x04FC
STKPTR
0x04FD
TOS
Bit Pos.
7
7:0
15:8
7:0
7:0
7:0
7:0
7:0
7:0
7:0
15:8
7:0
7:0
7:0
7:0
7:0
7:0
7:0
15:8
7:0
7:0
7:0
7:0
7:0
6
5
4
3
2
1
0
FSRL[7:0]
FSRH[5:0]
PLUSW[7:0]
PREINC[7:0]
POSTDEC[7:0]
POSTINC[7:0]
INDF[7:0]
BSR[5:0]
FSRL[7:0]
FSRH[5:0]
PLUSW[7:0]
PREINC[7:0]
POSTDEC[7:0]
POSTINC[7:0]
INDF[7:0]
WREG[7:0]
FSRL[7:0]
FSRH[5:0]
PLUSW[7:0]
PREINC[7:0]
POSTDEC[7:0]
POSTINC[7:0]
INDF[7:0]
Reserved
PCL
7:0
7:0
15:8
7:0
7:0
15:8
23:16
© 2021 Microchip Technology Inc.
PCL[7:0]
PCLATH[7:0]
PCLATU[4:0]
STKPTR[6:0]
TOS[7:0]
TOS[15:8]
TOS[20:16]
Preliminary Datasheet
DS40002213D-page 98
PIC18F27/47/57Q84
NVM - Nonvolatile Memory Module
10.
NVM - Nonvolatile Memory Module
The Nonvolatile Memory (NVM) module provides run-time read and write access to the Program Flash Memory
(PFM), Data Flash Memory (DFM) and Configuration bits. PFM includes the program memory and user ID space.
DFM is also referred to as EEPROM which is accessed one byte at a time and the erase before write is automatic.
The Table Pointer provides read-only access to the PFM, DFM and Configuration bits. The NVM controls provide
both read and write access to PFM, DFM and Configuration bits.
Reads and writes to and from the DFM are limited to single byte operations, whereas those for PFM are 16-bit word
or 128-word page operations. The page buffer memory occupies one full bank of RAM space located in the RAM
bank following the last occupied GPR bank. Refer to the “Memory Organization” chapter for more details about the
buffer RAM.
The registers used for control, address and data are as follows:
• NVMCON0 - Operation start and active status
• NVMCON1 - Operation type and error status
• NVMLOCK - Write-only register to guard against accidental writes
• NVMADR - Read/write target address (multibyte register)
• NVMDAT - Read/write target data (multibyte register)
• TBLPTR - Table Pointer PFM target address for reads and buffer RAM address for writes (multibyte register)
• TABLAT - Table Pointer read/write target data (single byte register)
The write and erase times are controlled by an on-chip timer. The write and erase voltages are generated by an
on-chip charge pump rated to function over the operating voltage range of the device.
PFM and DFM can be protected in two ways: code protection and write protection. Code protection (Configuration bit
CP) disables read and write access through an external device programmer. Write protection prevents user software
writes to NVM areas tagged for protection by the WRTn Configuration bits. Code protection does not affect the
self-write and erase functionality, whereas write protection does. Attempts to write a protected location will set the
WRERR bit. Code protection and write protection can only be reset on a Bulk Erase performed by an external
programmer.
The Bulk Erase command is used to completely erase different memory regions. The area to be erased is selected
using a bit field combination. The Bulk Erase command can only be issued through an external programmer. There is
no run time access for this command.
If the device is code-protected and a Bulk Erase command for the configuration memory is issued; all other memory
regions are also erased. Refer to the ”Programming Specifications” for more details.
10.1
Operations
NVM write operations are controlled by selecting the desired action with the NVMCMD bits and then starting the
operation by executing the unlock sequence. NVM read operations are started by setting the GO bit after setting the
read operation. Available NVM operations are shown in the following table.
Table 10-1. NVM Operations
NVMCMD
Unlock
Operation
DFM
PFM
Source/Destination
WRERR
INT
000
No
Read
byte
word
NVM to NVMDAT
No
No
001
No
Read and Post Increment
byte
word
NVM to NVMDAT
No
No
010
No
Read Page
—
page
NVM to Buffer RAM
No
No
011
Yes
Write
byte
word
NVMDAT to NVM
Yes
Yes
100
Yes
Write and Post Increment
byte
word
NVMDAT to NVM
Yes
Yes
101
Yes
Write Page
—
page
Buffer RAM to NVM
Yes
Yes
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 99
PIC18F27/47/57Q84
NVM - Nonvolatile Memory Module
...........continued
NVMCMD
Unlock
Operation
DFM
PFM
Source/Destination
WRERR
INT
110
Yes
Erase Page
—
page
n/a
Yes
Yes
111
No
Reserved (No Operation)
—
—
—
No
No
Important: When the GO bit is set, writes operations are blocked on all NVM registers. The GO bit is
cleared by hardware when the operation is complete. The GO bit cannot be cleared by software.
10.2
Unlock Sequence
As an additional layer of protection against memory corruption, a specific code execution unlock sequence is required
to initiate a write or erase operation. All interrupts need to be disabled before starting the unlock sequence to ensure
proper execution.
Example 10-1. Unlock Sequence in C
NVMLOCK = 0x55;
NVMLOCK = 0xAA;
NVMCON0bits.GO = 1;
10.3
Program Flash Memory (PFM)
The Program Flash Memory is readable, writable and erasable over the entire VDD range.
A 128-word PFM page is the only size that can be erased by user software. A Bulk Erase operation cannot be issued
from user code. A read from program memory is executed either one byte, one word or a 128-word page at a time. A
write to program memory can be executed as either 1 or 128 words at a time.
Writing or erasing program memory will cease instruction fetches until the operation is complete. The program
memory cannot be accessed during the write or erase, so code cannot execute. An internal programming timer
controls the write time of program memory writes and erases.
A value written to program memory does not need to be a valid instruction. Executing a program memory location
that forms an invalid instruction results in a NOP.
It is important to understand the PFM memory structure for erase and programming operations. Program memory
word size is 16 bits wide.
After a page has been erased, all or a portion of this page can be programmed. Data can be written directly into PFM
one 16-bit word at a time using the NVMADR, NVMDAT and NVMCON1 controls or as a full page from the buffer
RAM. The buffer RAM is directly accessible as any other SFR/GPR register and also may be loaded via sequential
writes using the TABLAT and TBLPTR registers.
Important: To modify only a portion of a previously programmed page, the contents of the entire page
must be read and saved in the buffer RAM prior to the page erase. The Read Page operation is the
easiest way to do this. The page needs to be erased so that the new data can be written into the buffer
RAM to reprogram the page of PFM. However, any unprogrammed locations can be written using the
single word Write operation without first erasing the page.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 100
PIC18F27/47/57Q84
NVM - Nonvolatile Memory Module
10.3.1
Page Erase
The erase size is always 128 words. Only through the use of an external programmer can larger areas of program
memory be Bulk Erased. Word erase in the program memory is not supported.
When initiating an erase sequence from user code, a page of 128 words of program memory is erased. The
NVMADR[21:8] bits point to the page being erased. The NVMADR[7:0] bits are ignored. The NVMCON0 and
NVMCON1 registers command the erase operation. The NVMCMD bits are set to select the erase operation. The GO
bit is set to initiate the erase operation as the last step in the unlock sequence.
The NVM unlock sequence described in the Unlock Sequence section must be used; this guards against accidental
writes. Instruction execution is halted during the erase cycle. The erase cycle is terminated by the internal
programming timer.
The sequence of events for erasing a page of PFM is:
1.
2.
Set the NVMADR registers to an address within the intended page.
Set the NVMCMD control bits to ‘b110 (Page Erase).
3.
4.
5.
6.
7.
8.
Disable all interrupts.
Perform the unlock sequence as described in the Unlock Sequence section.
Set the GO bit to start the PFM page erase.
Monitor the GO bit or NVMIF interrupt flag to determine when the erase has completed.
Interrupts can be enabled after the GO bit is clear.
Set the NVMCMD control bits to ‘b000.
If the PFM address is write-protected, the GO bit will be cleared, the erase operation will not take place, and the
WRERR bit will be set.
While erasing the PFM page, the CPU operation is suspended and then resumes when the operation is complete.
Upon erase completion, the GO bit is cleared in hardware, the NVMIF is set, and an interrupt will occur (if the NVMIE
bit is set and interrupts are enabled).
The buffer RAM data are not affected by erase operations and the NVMCMD bits will remain unchanged throughout
the erase opeation.
Figure 10-1. PFM Page Erase Flowchart
Start Erase Operation
Load NVMADR register with
address in the page to be erased
Set NVM Command to erase
(NVMCMD = ‘b110)
Disable Interrupts
(GIE = 0)
Execute unlock sequence
including setting the GO bit
CPU stalls while erase executes
Enable Interrupts
(GIE = 1)
Clear NVM Command
(NVMCMD = ‘b000)
End Erase Operation
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 101
PIC18F27/47/57Q84
NVM - Nonvolatile Memory Module
Example 10-2. Erasing a Page of Program Flash Memory in C
// Code sequence to erase one page of PFM
// PFM target address is specified by PAGE_ADDR
// Save interrupt enable bit value
uint8_t GIEBitValue = INTCON0bits.GIE;
// Load NVMADR with the base address of the memory page
NVMADR = PAGE_ADDR;
NVMCON1bits.CMD = 0x06;
// Set the page erase command
INTCON0bits.GIE = 0;
// Disable interrupts
//––––––––– Required Unlock Sequence –––––––––
NVMLOCK = 0x55;
NVMLOCK = 0xAA;
NVMCON0bits.GO = 1;
// Start page erase
//–––––––––––––––––––––––––––––––––––––––––––––
while (NVMCON0bits.GO);
// Wait for the erase operation to
complete
// Verify erase operation success and call the recovery function if
needed
if (NVMCON1bits.WRERR){
ERASE_FAULT_RECOVERY();
}
INTCON0bits.GIE = GIEBitValue;
value
NVMCON1bits.CMD = 0x00;
// Restore interrupt enable bit
// Disable writes to memory
Important:
• If a write or erase operation is terminated by an unexpected Reset, the WRERR bit will be set and the
user can check to decide whether a rewrite of the location(s) is needed.
• If a write or erase operation is attempted on a write-protected area, the WRERR bit will be set.
• If a write or erase operation is attempted on an invalid address location, the WRERR bit is set. (Refer
to the Program and Data Memory Map in the “Memory Organization” chapter for more information
on valid address locations.)
10.3.2
Page Read
PFM can be read one word or 128-word page at a time. A page is read by setting the NVMADR registers to an
address within the target page and setting the NVMCMD bits to ‘b010. The page content is then transferred from
PFM to the buffer RAM by starting the read operation by setting the GO bit.
The sequence of events for reading a 128-word page of PFM is:
1.
2.
Set the NVMADR registers to an address within the intended page.
Set the NVMCMD control bits to ‘b010 (Page Read).
3.
4.
Set the GO bit to start the PFM page read.
Monitor the GO bit or NVMIF interrupt flag to determine when the read has completed.
Example 10-3. Reading a Page of Program Flash Memory in C
// Code sequence to read one page of PFM to Buffer Ram
// PFM target address is specified by PAGE_ADDR
// Load NVMADR with the base address of the memory page
NVMADR = PAGE_ADDR;
NVMCON1bits.CMD = 0x02;
© 2021 Microchip Technology Inc.
// Set the page read command
Preliminary Datasheet
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PIC18F27/47/57Q84
NVM - Nonvolatile Memory Module
NVMCON0bits.GO = 1;
while (NVMCON0bits.GO);
complete
10.3.3
// Start page read
// Wait for the read operation to
Word Read
A single 16-bit word is read by setting the NVMADR registers to the target address and setting the NVMCMD bits to
‘b000. The word is then transferred from PFM to the NVMDAT registers by starting the read operation by setting the
GO bit.
The sequence of events for reading a word of PFM is:
1.
2.
Set the NVMADR registers to the target address.
Set the NVMCMD control bits to ‘b000 (Word Read).
3.
4.
Set the GO bit to start the PFM word read.
Monitor the GO bit or NVMIF interrupt flag to determine when the read has completed.
Example 10-4. Reading a Word from Program Flash Memory in C
// Code sequence to read one word from PFM
// PFM target address is specified by WORD_ADDR
// Variable to store the word value from desired location in PFM
uint16_t WordValue;
// Load NVMADR with the desired word address
NVMADR = WORD_ADDR;
NVMCON1bits.CMD = 0x00;
// Set the word read command
NVMCON0bits.GO = 1;
// Start word read
while (NVMCON0bits.GO);
// Wait for the read operation to
complete
WordValue = NVMDAT;
// Store the read value to a variable
10.3.4
Page Write
A page is written by first loading the buffer registers in the buffer RAM. All buffer registers are then written to PFM by
setting the NVMADR to an address within the intended address range of the target PFM page, setting the NVMCMD
bits to ‘b101, and then executing the unlock sequence and setting the GO bit.
If the PFM address in the NVMADR is write-protected, or if NVMADR points to an invalid location, the GO bit is
cleared without any effect and the WRERR bit is set.
CPU operation is suspended during a page write cycle and resumes when the operation is complete. The page
write operation completes in one extended instruction cycle. When complete, the GO bit is cleared by hardware and
NVMIF is set. An interrupt will occur if NVMIE is also set. The buffer registers and NVMCMD bits are not changed
throughout the write operation.
The internal programming timer controls the write time. The write/erase voltages are generated by an on-chip charge
pump and rated to operate over the voltage range of the device.
Important: Individual bytes of program memory may be modified, provided that the modification does
not attempt to change any NVM bit from a ‘0’ to a ‘1’. When modifying individual bytes with a page write
operation, it is necessary to load all buffer registers with either 0xFF or the existing contents of memory
before executing a page write operation. The fastest way to do this is by performing a page read operation.
In this device a PFM page is 128 words (256 bytes). This is the same size as one bank of general purpose RAM
(GPR). This area of GPR space is dedicated as a buffer area for NVM page operations. The buffer areas for each
device in the family are shown in the following table:
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
NVM - Nonvolatile Memory Module
Table 10-2. NVM Buffer Banks
Device
GPR Bank Number
PIC18Fx7Q84
37
PIC18Fx6Q84
21
There are several ways to address the data in the GPR buffer space:
• Using the TBLRD and TBLWT instructions
•
•
Using the indirect FSR registers
Direct read and writes to specific GPR locations
Neglecting the bank select bits, the 8 address bits of the GPR buffer space correspond to the 8 LSbs of each PFM
page. In other words, there is a one-to-one correspondence between the NVMADRL register and the FSRxL register,
where the x in FSRx is 0, 1 or 2.
The sequence of events for programming a page of PFM is:
1.
2.
Set the NVMADR registers to an address within the intended page.
Set the NVMCMD to ‘b110 (Erase Page).
3.
4.
5.
6.
7.
Disable all interrupts.
Perform the unlock sequence as described in the Unlock Sequence section.
Set the GO bit to start the PFM page erase.
Monitor the GO bit or NVMIF interrupt flag to determine when the erase has completed.
Set NVMCMD to ‘b101 (Page Write).
8.
9.
10.
11.
12.
Perform the unlock sequence.
Set the GO bit to start the PFM page write.
Monitor the GO bit or NVMIF interrupt flag to determine when the write has completed.
Interrupts can be enabled after the GO bit is clear.
Set the NVMCMD control bits to ‘b000.
Example 10-5. Writing a Page of Program Flash Memory in C
// Code sequence to write a page of PFM
// Input[] is the user data that needs to be written to PFM
// PFM target address is specified by PAGE_ADDR
#define PAGESIZE 128
// PFM page size
// Save Interrupt Enable bit Value
uint8_t GIEBitValue = INTCON0bits.GIE;
// The BufferRAMStartAddr will be changed based on the device, refer
// to the "Memory Organization" chapter for more details
uint16_t bufferRAM __at(BufferRAMStartAddr);
// Defining a pointer to the first location of the Buffer RAM
uint16_t *bufferRamPtr = (uint16_t*) & bufferRAM;
//Copy application buffer contents to the Buffer RAM
for (uint8_t i = 0; i < PAGESIZE; i++) {
*bufferRamPtr++ = Input[i];
}
// Load NVMADR with the base address of the memory page
NVMADR = PAGE_ADDR;
NVMCON1bits.CMD = 0x06;
// Set the page erase command
INTCON0bits.GIE = 0;
// Disable interrupts
//––––––––– Required Unlock Sequence –––––––––
NVMLOCK = 0x55;
NVMLOCK = 0xAA;
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
NVM - Nonvolatile Memory Module
NVMCON0bits.GO = 1;
// Start page erase
//–––––––––––––––––––––––––––––––––––––––––––––
while (NVMCON0bits.GO);
// Wait for the erase operation to
complete
// Verify erase operation success and call the recovery function if
needed
if (NVMCON1bits.WRERR){
ERASE_FAULT_RECOVERY();
}
// NVMADR is already pointing to target page
NVMCON1bits.CMD = 0x05;
// Set the page write command
//––––––––– Required Unlock Sequence –––––––––
NVMLOCK = 0x55;
NVMLOCK = 0xAA;
NVMCON0bits.GO = 1;
// Start page write
//–––––––––––––––––––––––––––––––––––––––––––––
while (NVMCON0bits.GO);
// Wait for the write operation to
complete
// Verify write operation success and call the recovery function if
needed
if (NVMCON1bits.WRERR){
WRITE_FAULT_RECOVERY();
}
INTCON0bits.GIE = GIEBitValue;
value
NVMCON1bits.CMD = 0x00;
10.3.5
// Restore interrupt enable bit
// Disable writes to memory
Word Write
PFM can be written one word at a time to a pre-erased memory location. Refer to the “Word Modify” section for
more information on writing to a prewritten memory location.
A single word is written by setting the NVMADR to the target address and loading NVMDAT with the desired word.
The word is then transferred to PFM by setting the NVMCMD bits to ‘b011 then executing the unlock sequence and
setting the GO bit.
The sequence of events for programming single word to a pre-erased location of PFM is:
1.
2.
3.
Set the NVMADR registers to the target address.
Load the NVMDAT with desired word.
Set the NVMCMD control bits to ‘b011 (Word Write).
4.
5.
6.
7.
8.
9.
Disable all interrupts.
Perform the unlock sequence as described in the Unlock Sequence section.
Set the GO bit to start the PFM word write.
Monitor the GO bit or NVMIF interrupt flag to determine when the write has completed.
Interrupts can be enabled after the GO bit is clear.
Set the NVMCMD control bits to ‘b000.
Example 10-6. Writing a Word of Program Flash Memory in C
// Code sequence to program one word to a pre-erased location in PFM
// PFM target address is specified by WORD_ADDR
// Target data is specified by WordValue
// Save interrupt enable bit value
uint8_t GIEBitValue = INTCON0bits.GIE;
// Load NVMADR with the target address of the word
NVMADR = WORD_ADDR;
NVMDAT = WordValue;
// Load NVMDAT with the desired
value
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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NVM - Nonvolatile Memory Module
NVMCON1bits.CMD = 0x03;
// Set the word write command
INTCON0bits.GIE = 0;
// Disable interrupts
//––––––––– Required Unlock Sequence –––––––––
NVMLOCK = 0x55;
NVMLOCK = 0xAA;
NVMCON0bits.GO = 1;
// Start word write
//–––––––––––––––––––––––––––––––––––––––––––––––
while (NVMCON0bits.GO);
// Wait for the write operation to
complete
// Verify word write operation success and call the recovery function
if needed
if (NVMCON1bits.WRERR){
WRITE_FAULT_RECOVERY();
}
INTCON0bits.GIE = GIEBitValue;
value
NVMCON1bits.CMD = 0x00;
10.3.6
// Restore interrupt enable bit
// Disable writes to memory
Word Modify
Changing a word in PFM requires erasing the word before it is rewritten. However, the PFM cannot be erased by less
than a page at a time. Changing a single word requires reading the page, erasing the page, and then rewriting the
page with the modified word. The NVM command set includes page operations to simplify this task.
The steps necessary to change one or more words in PFM space are as follows:
1. Set the NVMADR registers to the target address.
2. Set the NVMCMD to ‘b010 (Page Read).
3.
4.
5.
6.
Set the GO bit to start the PFM read into the GPR buffer.
Monitor the GO bit or NVMIF interrupt flag to determine when the read has completed.
Make the desired changes to the GPR buffer data.
Set NVMCMD to ‘b110 (Page Erase).
7.
8.
9.
10.
11.
Disable all interrupts.
Perform the unlock sequence as described in the Unlock Sequence section.
Set the GO bit to start the PFM page erase.
Monitor the GO bit or NVMIF interrupt flag to determine when the erase has completed.
Set NVMCMD to ‘b101 (Page Write).
12.
13.
14.
15.
16.
Perform the unlock sequence.
Set the GO bit to start the PFM page write.
Monitor the GO bit or NVMIF interrupt flag to determine when the write has completed.
Interrupts can be enabled after the GO bit is clear.
Set the NVMCMD control bits to ‘b000.
Example 10-7. Modifying a Word in Program Flash Memory in C
// Code sequence to modify one word in a programmed page of PFM
// The variable with desired value is specified by ModifiedWord
// PFM target address is specified by WORD_ADDR
// PFM page size is specified by PAGESIZE
// The Buffer RAM start address is specified by BufferRAMStartAddr.
This value
// will be changed based on the device, refer to the "Memory
Organization"
//chapter for more details.
// Save Interrupt Enable bit Value
uint8_t GIEBitValue = INTCON0bits.GIE;
uint16_t bufferRAM __at(BufferRAMStartAddr);
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
NVM - Nonvolatile Memory Module
// Defining a pointer to the first location of the Buffer RAM
uint16_t *bufferRamPtr = (uint16_t*) & bufferRAM;
// Load NVMADR with the base address of the memory page
NVMADR = WORD_ADDR;
NVMCON1bits.CMD = 0x02;
// Set the page read command
INTCON0bits.GIE = 0;
// Disable interrupts
NVMCON0bits.GO = 1;
// Start page read
while (NVMCON0bits.GO);
// Wait for the read operation to
complete
// NVMADR is already pointing to target page
NVMCON1bits.CMD = 0x06;
// Set the page erase command
//––––––––– Required Unlock Sequence –––––––––
NVMLOCK = 0x55;
NVMLOCK = 0xAA;
NVMCON0bits.GO = 1;
// Start page erase
//–––––––––––––––––––––––––––––––––––––––––––––
while (NVMCON0bits.GO);
// Wait for the erase operation to
complete
// Verify erase operation success and call the recovery function if
needed
if (NVMCON1bits.WRERR){
ERASE_FAULT_RECOVERY();
}
//Modify Buffer RAM for the given word to be written to PFM
uint8_t offset = (uint8_t) ((WORD_ADDR & ((PAGESIZE * 2) - 1)) / 2);
bufferRamPtr += offset;
*bufferRamPtr = ModifiedWord;
// NVMADR is already pointing to target page
NVMCON1bits.CMD = 0x05;
// Set the page write command
//––––––––– Required Unlock Sequence –––––––––
NVMLOCK = 0x55;
NVMLOCK = 0xAA;
NVMCON0bits.GO = 1;
// Start page write
//–––––––––––––––––––––––––––––––––––––––––––––
while (NVMCON0bits.GO);
// Wait for the write operation to
complete
// Verify write operation success and call the recovery function if
needed
if (NVMCON1bits.WRERR){
WRITE_FAULT_RECOVERY();
}
INTCON0bits.GIE = GIEBitValue;
NVMCON1bits.CMD = 0x00;
10.3.7
// Restore interrupt enable bit value
// Disable writes to memory
Write Verify
Depending on the application, good programming practice can dictate that the value written to the memory shall
be verified against the original value. This can be used in applications where excessive writes can stress bits near
the specification limit. Since program memory is stored as a full page, the stored program memory contents are
compared with the intended data stored in the buffer RAM after the last write is complete.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
NVM - Nonvolatile Memory Module
Figure 10-2. Program Flash Memory Write Verify Flowchart
Rev. 10-000051=
1/30/2019
Start
Verify Operation
This routine assumes that the last
page of data written was from the
buffer RAM. This image will be
used to verify the data currently
stored in PFM
Set NVMCMD to Read and Post
Increment
Set GO bit
NVMDAT =
RAM image ?
Yes
No
No
Fail
Verify Operation
Last word ?
Yes
End
Verify Operation
10.3.8
Unexpected Termination of Write Operation
If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory location
just programmed needs to be verified and reprogrammed, if needed. If the write operation is interrupted by a MCLR
Reset or a WDT Time-out Reset during normal operation, the WRERR bit will be set, which the user can check to
decide whether a rewrite of the location(s) is needed.
10.3.9
User ID, Device ID, Configuration Settings Access, DIA and DCI
The NVMADR value determines which NVM address space is accessed. The User IDs and Configuration areas allow
read and write access, whereas Device and Revision IDs are limited to read-only.
Reading and writing User ID space is identical to reading and writing PFM space as described in the preceding
paragraphs.
Writing to the Configuration bits is performed in the same manner as writing to the Data Flash Memory (DFM).
Configuration settings are modified one byte at a time with the NVM Read and Write operations. When a Write
operation is performed on a Configuration byte, an erase byte is performed automatically before the new byte is
written. Any code protection settings that are not enabled will remain not enabled after the Write operation, unless the
© 2021 Microchip Technology Inc.
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new values enable them. However, any code protection settings that are enabled cannot be disabled by a self-write
of the configuration space. The user can modify the configuration space by the following steps:
1. Read the target Configuration byte by setting the NVMADR with the target address.
2. Retrieve the Configuration byte with the Read operation (NVMCMD = ‘b000).
3.
4.
Modify the Configuration byte in NVMDAT register.
Write the NVMDAT register to the Configuration byte using the Write operation (NVMCMD = ‘b011) and
unlock sequence.
10.3.10 Table Pointer Operations
To read and write program memory, there are two operations that allow the processor to move bytes between the
program memory space and the data RAM:
•
Table Read (TBLRD*)
•
Table Write (TBLWT*)
The SFR registers associated with these operations include:
• TABLAT register
• TBLPTR registers
The program memory space is 16 bits wide, while the data RAM space is eight bits wide. The TBLPTR registers
determine the address of one byte of the NVM memory. Table reads move one byte of data from NVM space to the
TABLAT register, and table writes move the TABLAT data to the buffer RAM ready for a subsequent write to NVM
space with the NVM controls.
10.3.10.1 Table Pointer Register
The Table Pointer (TBLPTR) register addresses a byte within the program memory. The TBLPTR comprises
three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer (bits 0 through 21). The
bits 0 through 20 allow the device to address up to 2 Mbytes of program memory space. Bit 21 allows access to the
Device ID, the User ID, Configuration bits as well as the DIA and DCI.
The Table Pointer register, TBLPTR, is used by the TBLRD and TBLWT instructions. These instructions can increment
and decrement the TBLPTR, depending on specific appended characters shown in the following table. The increment
and decrement operations on the TBLPTR affect only bits 0 through 20.
Table 10-3. Table Pointer Operations with TBLRD and TBLWT Instructions
Example
Operation on Table Pointer
TBLRD*
TBLWT*
TBLPTR is not modified
TBLRD*+
TBLWT*+
TBLPTR is incremented after the read/write
TBLRD*TBLWT*-
TBLPTR is decremented after the read/write
TBLRD+*
TBLWT+*
TBLPTR is incremented before the read/write
10.3.10.2 Table Latch Register
The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register receives one
byte of NVM data resulting from a TBLRD* instruction and is the source of the 8-bit data sent to the holding register
space as a result of a TBLWT* instruction.
10.3.10.3 Table Read Operations
The table read operation retrieves one byte of data directly from program memory pointed to by the TBLPTR
registers and places it into the TABLAT register. The following figure shows the operation of a table read.
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Figure 10-3. Table Read Operation
Instruction: TBLRD*
Table Pointer(1)
Program Memory
TBLPTRU TBLPTRH TBLPTRL
Table Latch (8-bit)
TABLAT
Program Memory
(TBLPTR)
Note 1: The Table Pointer register points to a byte in program memory.
10.3.10.4 Table Write Operations
The table write operation stores one byte of data from the TABLAT register into a buffer RAM register. The following
figure shows the operation of a table write from the TABLAT register to the buffer RAM space. The procedure to write
the contents of the buffer RAM into program memory is detailed in the "Writing to Program Flash Memory" section.
Figure 10-4. Table Write Operation
Instruction: TBLWT*
GPR Space
Table Pointer(1)
Program Memory
Table Latch (8-bit)
TBLPTRU TBLPTRH TBLPTRL
TABLAT
Buffer RAM
Program Memory
(TBLPTR[MSbs])
Note 1: During table writes the Table Pointer does not point directly to program memory. TBLPTRL
actually points to an address within the buffer registers. TBLPTRU:TBLPTRH points to program memory
where the entire buffer space will eventually be written with the NVM commands.
Table operations work with byte entities. Tables containing data, rather than program instructions, are not required
to be word-aligned. Therefore, a table can start and end at any byte address. If a table write is being used to write
executable code into program memory, program instructions will need to be word-aligned.
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10.3.10.5 Table Pointer Boundaries
The TBLPTR register is used in reads of the Program Flash Memory. Writes using the TBLPTR register go into to a
buffer RAM from which the data can eventually be transferred to Program Flash Memory using the NVMADR register
and NVM commands.
When a TBLRD instruction is executed, all 22 bits of the TBLPTR determine which byte is read from program memory
directly into the TABLAT register.
When a TBLWT instruction is executed, the byte in the TABLAT register is written, though not to Flash memory but to
a buffer register in preparation for a program memory write. All the buffer registers together form a write block of size
128 words/256 bytes. The LSbs of the TBLPTR register determine to which specific address within the buffer register
block the write affects. The size of the write block determines the number of LSbs that are affected. The MSbs of the
TBLPTR register have no effect during TBLWT operations.
When a program memory page write is executed, the entire buffer register block is written to the Flash memory at the
address determined by the MSbs of the NVMADR register. The LSbs are ignored during Flash memory writes.
The following figure illustrates the relevant boundaries of the TBLPTR register based on NVM operations.
Figure 10-5. Table Pointer Boundaries Based on Operation
21
TBLPTRU
16
15
TBLPTRH
8
NVMADRH
NVMADRU
Page Erase/Write
NVMADR[21:8]
7
TBLPTRL
0
TBLPTRL
Table Write
TBLPTR[7:0]
Table Read - TBLPTR[21:0]
Note:
1. Refer to the “Memory Organization” chapter for more details about the the size of the buffer registers block.
10.3.10.6 Reading the Program Flash Memory
The TBLRD instruction retrieves data from program memory at the location to which the TBLPTR register points and
places it into the TABLAT SFR register. Table reads from program memory are performed one byte at a time. The
instruction set includes incrementing the TBLPTR register automatically for the next table read operation.
The CPU operation is suspended during the read, and resumes operation immediately after. From the user point of
view, the value in the TABLAT register is valid in the next instruction cycle.
The internal program memory is typically organized by words. The Least Significant bit of the address selects
between the high and low bytes of the word. The following figure illustrates the interface between the internal
program memory and the TABLAT register.
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Figure 10-6. Reads from Program Flash Memory
Program Flash Memory
(Even Byte Address)
(Odd Byte Address)
TBLPTR = xxxxx1
Instruction
Register (IR)
FETCH
TBLRD
TBLPTR = xxxxx0
TABLAT
Read Register
Figure 10-7. Program Flash Memory Read Flowchart
Start Read Operation
Select Byte Address
(TBLPTR Register)
Initiate Read Operation
(TBLRD)
Data read now
in TABLAT register
End Read Operation
Example 10-8. Reading a Program Flash Memory Word
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
READ_WORD:
TBLRD*+
MOVF
MOVWF
TBLRD*+
MOVFW
MOVF
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
TABLAT, W
WORD_EVEN
TABLAT, W
WORD_ODD
© 2021 Microchip Technology Inc.
; Load TBLPTR with the base
; address of the word
; read into TABLAT and increment
; get data
; read into TABLAT and increment
; get data
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10.4
Data Flash Memory (DFM)
The Data Flash Memory is a nonvolatile memory array, also referred to as EEPROM. The DFM is mapped above
program memory space. The DFM can be accessed using the Table Pointer or NVM Special Function Registers
(SFRs). The DFM is readable and writable during normal operation over the entire VDD range.
The DFM can only be read and written one byte at a time. When interfacing to the data memory block, the NVMDATL
register holds the 8-bit data for read/write and the NVMADR register holds the address of the DFM location being
accessed.
The DFM is rated for high erase/write cycle endurance. A byte write automatically erases the location and writes the
new data (erase-before-write). The write time is controlled by an internal programming timer; it will vary with voltage
and temperature as well as from device-to-device. Refer to the data EEPROM memory parameters in the “Electrical
specifications” chapter for the limits.
10.4.1
Reading the DFM
To read a DFM location, the user must write the address to the NVMADR register, set the NVMCMD bits for a
single read operation (NVMCMD = ‘b000), and then set the GO control bit. The data is available on the very next
instruction cycle. Therefore, the NVMDATL register can be read by the next instruction. NVMDATL will hold this value
until another read operation, or until it is written to by the user (during a write operation).
Note: Only byte reads are supported for DFM. Reading DFM with the Read Page operation is not supported.
The sequence of events for reading a byte of DFM is:
1.
2.
Set the NVMADR registers to an address within the intended page.
Set the NVMCMD control bits to ‘b000 (Byte Read).
3.
4.
Set the GO bit to start the DFM byte read.
Monitor the GO bit or NVMIF interrupt flag to determine when the read has completed.
This process is also shown in the following flowchart.
Figure 10-8. DFM Read Flowchart
Start Read Operation
Set DFM Byte Address
(NVMADR=Address)
Set NVM Read Command
(NVMCMD=’b000)
Initiate Read
(GO=1)
Data read now in NVMDATL
End Read Operation
Example 10-9. Reading a Byte from Data Flash Memory in C
// Code sequence to read one byte from DFM
// DFM target address is specified by DFM_ADDR
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// Variable to store the byte value from desired location in DFM
uint8_t ByteValue;
// Load NVMADR with the desired byte address
NVMADR = DFM_ADDR;
NVMCON1bits.CMD = 0x00;
// Set the byte read command
NVMCON0bits.GO = 1;
// Start byte read
while (NVMCON0bits.GO);
// Wait for the read operation to
complete
ByteValue = NVMDATL;
// Store the read value to a
variable
10.4.2
Writing to DFM
To write a DFM location, the address must first be written to the NVMADR register, the data written to the NVMDATL
register, and the Write operation command set in the NVMCMD bits. The sequence shown in Unlock Sequence must
be followed to initiate the write cycle. Multibyte Page writes are not supported for the DFM.
The write will not begin if the NVM unlock sequence is not exactly followed for each byte. It is strongly recommended
to disable interrupts during this code segment.
When not actively writing to the DFM, the NVMCMD bits need to be kept clear at all times as an extra precaution
against accidental writes. The NVMCMD bits are not cleared by hardware.
After a write sequence has been initiated, NVMCON0, NVMCON1, NVMADR and NVMDAT cannot be modified.
Each DFM write operation includes an implicit erase cycle for that byte. CPU execution continues in parallel and at
the completion of the write cycle, the GO bit is cleared in hardware and the NVM Interrupt Flag (NVMIF) bit is set.
The user can either enable the interrupt or poll the bit. NVMIF must be cleared by software.
The sequence of events for programming one byte of DFM is:
1.
2.
3.
Set NVMADR registers with the target byte address.
Load NVMDATL register with desired byte.
Set the NVMCMD control bits to ‘b011 (Byte Write).
4.
5.
6.
7.
8.
9.
Disable all interrupts.
Perform the unlock sequence as described in the Unlock Sequence section.
Set the GO bit to start the DFM byte write.
Monitor the GO bit or NVMIF interrupt flag to determine when the write has been completed.
Interrupts can be enabled after the GO bit is clear.
Set the NVMCMD control bits to ‘b000.
Example 10-10. Writing a Byte to Data Flash Memory in C
// Code sequence to write one byte to a DFM
// DFM target address is specified by DFM_ADDR
// Target data is specified by ByteValue
// Save interrupt enable bit value
uint8_t GIEBitValue = INTCON0bits.GIE;
// Load NVMADR with the target address of the byte
NVMADR = DFM_ADDR;
NVMDATL = ByteValue;
// Load NVMDAT with the desired
value
NVMCON1bits.CMD = 0x03;
// Set the byte write command
INTCON0bits.GIE = 0;
// Disable interrupts
//––––––––– Required Unlock Sequence –––––––––
NVMLOCK = 0x55;
NVMLOCK = 0xAA;
NVMCON0bits.GO = 1;
// Start byte write
//–––––––––––––––––––––––––––––––––––––––––––––––
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while (NVMCON0bits.GO);
// Wait for the write operation to
complete
// Verify byte write operation success and call the recovery function
if needed
if (NVMCON1bits.WRERR){
WRITE_FAULT_RECOVERY();
}
INTCON0bits.GIE = GIEBitValue;
value
NVMCON1bits.CMD = 0;
10.4.3
// Restore interrupt enable bit
// Disable writes to memory
Erasing the DFM
The DFM does not support the Page Erase operation. However, the DFM can be erased by writing 0xFF to all
locations in the memory that need to be erased. The simple code example bellow shows how to erase ‘n’ number of
bytes in DFM. Refer to the “Memory Organization” chapter for more details about the DFM size and valid address
locations.
Example 10-11. Erasing n Bytes of Data Flash Memory in C
// Code sequence to erase n bytes of DFM
// DFM target start address is specified by PAGE_ADDR
// Number of bytes to be eares is specified by n
// Save interrupt enable bit value
uint8_t GIEBitValue = INTCON0bits.GIE;
// Load NVMADR with the target address of the byte
NVMADR = DFM_ADDR;
NVMDATL = 0xFF;
// Load NVMDATL with 0xFF
NVMCON1bits.CMD = 0x04;
// Set the write and post increment
command
INTCON0bits.GIE = 0;
// Disable interrupts
for (uint8_t i = 0; i < n; i++}(
NVMLOCK = 0x55;
NVMLOCK = 0xAA;
NVMCON0bits.GO = 1;
}
// Verify byte erase operation success and call the recovery function
if needed
if (NVMCON1bits.WRERR){
ERASE_FAULT_RECOVERY();
}
INTCON0bits.GIE = GIEBitValue;
value
NVMCON1bits.CMD = 0;
10.4.4
// Restore interrupt enable bit
// Disable writes to memory
DFM Write Verify
Depending on the application, good programming practice can dictate that the value written to the memory shall be
verified against the original value. This can be used in applications where excessive writes can stress bits near the
specification limit to ensure that the intended values are written correctly to the specified memory locations.
10.4.5
Operation During Code-Protect and Write-Protect
The DFM can be code-protected using the CP Configuration bit. In-Circuit Serial Programming read and write
operations are disabled when code protection is enabled. However, internal reads operate normally. Internal writes
operate normally provided that write protection is not enabled.
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If the DFM is write-protected or if NVMADR points at an invalid address location, attempts to set the GO bit will fail
and the WRERR bit will be set.
10.4.6
Protection Against Spurious Writes
A write sequence is valid only when both the following conditions are met. This prevents spurious writes that might
lead to data corruption.
1.
2.
10.5
All NVM read, write and erase operations are enabled with the NVMCMD control bits. It is suggested to have
the NVMCMD bits cleared at all times except during memory writes. This prevents memory operations if any of
the control bits are set accidentally.
The NVM unlock sequence must be performed each time before all operations except the memory read
operation.
Register Definitions: NVM
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10.5.1
NVMCON0
Name:
Address:
NVMCON0
0x040
Nonvolatile Memory Control Register 0
Bit
7
6
5
4
3
2
1
0
GO
R/S/HC
0
Access
Reset
Bit 0 – GO Start Operation Control
Start the operation specified by the NVMCMD bits
Value
Description
1
Start operation (must be set after UNLOCK sequence for all operations except READ)
0
Operation is complete
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10.5.2
NVMCON1
Name:
Address:
NVMCON1
0x041
Nonvolatile Memory Control Register 1
Bit
Access
Reset
7
WRERR
R/C/HS
0
6
5
4
3
2
R/W
0
1
NVMCMD[2:0]
R/W
0
0
R/W
0
Bit 7 – WRERR NVM Write Error
Reset States: POR = 0
All other Resets = u
Value
Description
1
A write operation was interrupted by a Reset,
or a write or erase operation was attempted on a write-protected area,
or a write or erase operation was attempted on an unimplemented area,
or a write or erase operation was attempted while locked,
or a page operation was directed to a DFM area
0
All write/erase operations have completed successfully
Bits 2:0 – NVMCMD[2:0] NVM Command
Table 10-4. NVM Operations
NVMCMD
Unlock
000
001
010
011
100
101
110
111
No
No
No
Yes
Yes
Yes
Yes
No
Operation
DFM
PFM
Source/Destination
WRERR
INT
Read
Read and Post Increment
Read Page
Write
Write and Post Increment
Write Page
Erase Page
Reserved (No Operation)
byte
byte
—
byte
byte
—
—
—
word
word
page
word
word
page
page
—
NVM to NVMDAT
NVM to NVMDAT
NVM to Buffer RAM
NVMDAT to NVM
NVMDAT to NVM
Buffer RAM to NVM
n/a
—
No
No
No
Yes
Yes
Yes
Yes
No
No
No
No
Yes
Yes
Yes
Yes
No
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10.5.3
NVMLOCK
Name:
Address:
NVMLOCK
0x042
Nonvolatile Memory Write Restriction Control Register
NVM write and erase operations require writing 0x55 then 0xAA to this register immediately before the operation
execution.
Bit
Access
Reset
7
6
5
WO
0
WO
0
WO
0
4
3
NVMLOCK[7:0]
WO
WO
0
0
2
1
0
WO
0
WO
0
WO
0
Bits 7:0 – NVMLOCK[7:0]
Reading this register always returns ‘0’.
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10.5.4
NVMADR
Name:
Address:
NVMADR
0x043
Nonvolatile Memory Address Register
Bit
23
22
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
21
20
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
19
18
NVMADR[21:16]
R/W
R/W
0
0
12
11
NVMADR[15:8]
R/W
R/W
0
0
4
3
NVMADR[7:0]
R/W
R/W
0
0
17
16
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 21:0 – NVMADR[21:0] NVM Address
Notes: The individual bytes in this multibyte register can be accessed with the following register names:
• NVMADRU: Accesses the upper byte NVMADR[21:16]
• NVMADRH: Accesses the high byte NVMADR[15:8]
• NVMADRL: Accesses the low byte NVMADR[7:0]
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10.5.5
NVMDAT
Name:
Address:
NVMDAT
0x046
Nonvolatile Memory Data Register
Bit
Access
Reset
Bit
Access
Reset
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
12
11
NVMDAT[15:8]
R/W
R/W
0
0
4
3
NVMDAT[7:0]
R/W
R/W
0
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – NVMDAT[15:0] NVM Data
Notes: The individual bytes in this multibyte register can be accessed with the following register names:
• NVMDATH: Accesses the high byte NVMDAT[15:8]
• NVMDATL: Accesses the low byte NVMDAT[7:0]
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10.5.6
TBLPTR
Name:
Address:
TBLPTR
0x4F6
Table Pointer Register
Bit
23
22
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
21
TBLPTR21
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
20
19
R/W
0
R/W
0
18
TBLPTR[20:16]
R/W
0
17
16
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
12
11
TBLPTR[15:8]
R/W
R/W
0
0
4
3
TBLPTR[7:0]
R/W
R/W
0
0
Bit 21 – TBLPTR21 NVM Most Significant Address bit
Value
Description
1
Access Configuration, User ID, Device ID, and Revision ID spaces
0
Access Program Flash Memory space
Bits 20:0 – TBLPTR[20:0] NVM Address bits
Notes: The individual bytes in this multibyte register can be accessed with the following register names:
• TBLPTRU: Accesses the upper byte TBLPTR[21:16]
• TBLPTRH: Accesses the high byte TBLPTR[15:8]
• TBLPTRL: Accesses the low byte TBLPTR[7:0]
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10.5.7
TABLAT
Name:
Address:
TABLAT
0x4F5
Table Latch Register
Bit
Access
Reset
7
6
5
R/W
0
R/W
0
R/W
0
4
3
TABLAT[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – TABLAT[7:0] The value of the NVM memory byte returned from the address contained in TBLPTR after a
TBLRD command, or the data written to the latch by a TBLWT command.
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10.6
Address
Register Summary - NVM
Name
0x00
...
0x3F
0x40
0x41
0x42
NVMCON0
NVMCON1
NVMLOCK
0x43
NVMADR
0x46
NVMDAT
0x48
...
0x04F4
0x04F5
0x04F6
Bit Pos.
7
6
5
4
3
2
1
0
Reserved
7:0
7:0
7:0
7:0
15:8
23:16
7:0
15:8
GO
WRERR
NVMCMD[2:0]
NVMLOCK[7:0]
NVMADR[7:0]
NVMADR[15:8]
NVMADR[21:16]
NVMDAT[7:0]
NVMDAT[15:8]
Reserved
TABLAT
TBLPTR
7:0
7:0
15:8
23:16
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TABLAT[7:0]
TBLPTR[7:0]
TBLPTR[15:8]
TBLPTR21
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VIC - Vectored Interrupt Controller Module
11.
VIC - Vectored Interrupt Controller Module
11.1
Overview
The Vectored Interrupt Controller (VIC) module reduces the numerous peripheral interrupt request signals to a single
interrupt request signal to the CPU. This module includes the following major features:
•
•
•
•
•
•
Interrupt Vector Table (IVT) with a unique vector for each interrupt source
Fixed and ensured interrupt latency
Programmable base address for IVT with lock
Two user-selectable priority levels - High priority and low priority
Two levels of context saving
Interrupt state Status bits to indicate the current execution status of the CPU
The VIC module assembles all of the interrupt request signals and resolves the interrupts based on both a fixed
natural order priority (i.e., determined by the IVT), and a user-assigned priority (i.e., determined by the IPRx
registers), thereby eliminating scanning of interrupt sources.
11.2
Interrupt Control and Status Registers
The devices in this family implement the following registers for the interrupt controller:
•
•
•
•
•
•
INTCON0, INTCON1 Control Registers
PIRx - Peripheral Interrupt Status Registers
PIEx - Peripheral Interrupt Enable Registers
IPRx - Peripheral Interrupt Priority Registers
IVTBASE Address Registers
IVTLOCK Register
Global interrupt control functions and external interrupts are controlled from the INTCON0 register. The INTCON1
register contains the status flags for the interrupt controller.
The PIRx registers contain all of the interrupt request flags. Each source of interrupt has a Status bit, which is set
by the respective peripherals or an external signal, and is either cleared via software or automatically cleared by
hardware upon clearing of the interrupt condition, depending on the peripheral and bit.
The PIEx registers contain all of the interrupt enable bits. These control bits are used to individually enable interrupts
from the peripherals or external signals.
The IPRx registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source
can be assigned to either a high or low priority.
The IVTBASE register is user programmable and is used to determine the start address of the IVT and the IVTLOCK
register is used to prevent any unintended writes to the IVTBASE register.
There are two other Configuration bits that control the way the interrupt controller can be configured: the MVECEN bit
and the IVT1WAY bit.
The MVECEN bit determines whether the IVT is used to determine the interrupt priorities. The IVT1WAY bit
determines the number of times that the IVTLOCKED bit can be cleared and set after a device Reset. See Interrupt
Vector Table Address Calculation for details.
11.3
Interrupt Vector Table
The interrupt controller supports an IVT that contains the vector address location for each interrupt request source.
The IVT resides in program memory, starting at the address location determined by IVTBASE The IVT contains one
vector for each source of interrupt. Each interrupt vector location contains the starting address of the associated
Interrupt Service Routine (ISR).
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PIC18F27/47/57Q84
VIC - Vectored Interrupt Controller Module
The MVECEN Configuration bit controls the availability of the vector table.
11.3.1
Interrupt Vector Table Base Address (IVTBASE)
The start address of the vector table is user-programmable through the IVTBASE. The user must ensure the start
address is such that it can encompass the entire vector table inside the program memory.
Each vector address is a 16-bit word (or two address locations on PIC18 devices). For ‘n’ interrupt sources, there
are ‘2n’ address locations necessary to hold the table, starting from IVTBASE as the first location. Thus, the starting
address needs to be chosen such that the address range from IVTBASE to “IVTBASE+2n-1” can be encompassed
within the program Flash memory.
For example, if the highest vector number was 81, IVTBASE needs to be chosen such that “IVTBASE+0xA1” is less
than the last memory location in program Flash memory.
A programmable vector table base address is useful in situations to switch between different sets of vector tables,
depending on the application. It can also be used when the application program needs to update the existing vector
table (vector address values).
Important: It is required that the user assign an even address to IVTBASE for correct operation.
11.3.2
Interrupt Vector Table Contents
MVECEN = 0
When MVECEN = 0, the address location pointed to by IVTBASE has a GOTO instruction for a high-priority interrupt.
Similarly, the corresponding low-priority vector also has a GOTO instruction, which is executed in case of a low-priority
interrupt.
MVECEN = 1
When MVECEN = 1, the value in the vector table of each interrupt points to the address location of the first
instruction of the Interrupt Service Routine, hence: ISR Location = Interrupt Vector Table entry HADR (and a data cycle is not
occurring) or when CRCGO = 0.
4.
5.
CRCEN and CRCGO bits must be set before setting the SGO bit.
See Table 13-2.
Table 13-2. Scanner Operating Modes
TRIGEN
BURSTMD
Scanner Operation
0
0
Memory access is requested when the CRC module is ready to accept data; the
request is granted if no other higher priority source request is pending.
1
0
Memory access is requested when the CRC module is ready to accept data and
trigger selection is true; the request is granted if no other higher priority source
request is pending.
x
1
Memory access is always requested; the request is granted if no other higher
priority source request is pending.
Note: Refer to the “System Arbitration” and the “Memory Access Scheme” sections for more details about
Priority selection and Memory Access Scheme.
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PIC18F27/47/57Q84
CRC - Cyclic Redundancy Check Module with Memory S...
13.13.9 SCANLADR
Name:
SCANLADR
Scan Low Address Registers
Bit
23
22
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
21
20
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
19
18
SCANLADRU[5:0]
R/W
R/W
0
0
12
11
SCANLADRH[7:0]
R/W
R/W
0
0
4
3
SCANLADRL[7:0]
R/W
R/W
0
0
17
16
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 21:16 – SCANLADRU[5:0] Scan Start/Current Address upper byte
Upper bits of the current address to be fetched from, value increments on each fetch of memory.
Bits 15:8 – SCANLADRH[7:0] Scan Start/Current Address high byte
High byte of the current address to be fetched from, value increments on each fetch of memory.
Bits 7:0 – SCANLADRL[7:0] Scan Start/Current Address low byte
Low byte of the current address to be fetched from, value increments on each fetch of memory.
Notes:
1. Registers SCANLADRU/H/L form a 22-bit value, but are not guarded for atomic or asynchronous access;
registers may only be read or written while SGO = 0.
2.
While SGO = 1, writing to this register is ignored.
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CRC - Cyclic Redundancy Check Module with Memory S...
13.13.10 SCANHADR
Name:
SCANHADR
Scan High Address Registers
Bit
23
22
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
21
20
R/W
1
R/W
1
15
14
13
R/W
1
R/W
1
R/W
1
7
6
5
R/W
1
R/W
1
R/W
1
19
18
SCANHADRU[5:0]
R/W
R/W
1
1
12
11
SCANHADRH[7:0]
R/W
R/W
1
1
4
3
SCANHADRL[7:0]
R/W
R/W
1
1
17
16
R/W
1
R/W
1
10
9
8
R/W
1
R/W
1
R/W
1
2
1
0
R/W
1
R/W
1
R/W
1
Bits 21:16 – SCANHADRU[5:0] Scan End Address
Upper bits of the address at the end of the designated scan
Bits 15:8 – SCANHADRH[7:0] Scan End Address
High byte of the address at the end of the designated scan
Bits 7:0 – SCANHADRL[7:0] Scan End Address
Low byte of the address at the end of the designated scan
Notes:
1. Registers SCANHADRU/H/L form a 22-bit value but are not guarded for atomic or asynchronous access;
registers may only be read or written while SGO = 0.
2.
While SGO = 1, writing to this register is ignored.
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CRC - Cyclic Redundancy Check Module with Memory S...
13.13.11 SCANTRIG
Name:
Address:
SCANTRIG
0x361
SCAN Trigger Selection Register
Bit
7
6
Access
Reset
5
4
3
R/W
0
R/W
0
2
TSEL[4:0]
R/W
0
1
0
R/W
0
R/W
0
Bits 4:0 – TSEL[4:0] Scanner Data Trigger Input Selection
Table 13-3. Scanner Data Trigger Input Sources
TSEL Value
11111-10110
10110
10101
10100
10011
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
Trigger Input Sources
—
CLC8_OUT
CLC7_OUT
CLC6_OUT
CLC5_OUT
CLC4_OUT
CLC3_OUT
CLC2_OUT
CLC1_OUT
SMT1_OUT
Reserved
Reserved
Reserved
TU16B_OUT
TU16A_OUT
TMR6_Postscaler_OUT
TMR5_OUT
TMR4_Postscaler_OUT
TMR3_OUT
TMR2_Postscaler_OUT
TMR1_OUT
TMR0_OUT
CLCKREF_OUT
LFINTOSC(1)
Note:
1. The number of implemented bits varies by device.
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13.13.12 BOOTREG
Name:
Address:
BOOTREG
0x038
CRC on Boot Status Register
Bit
Access
Reset
7
BPOUT
R/W
0
6
BOOTDONE
R/W
0
5
4
3
2
1
B1
R/W
0
0
B0
R/W
0
Bit 7 – BPOUT CRC-on-Boot Output Pin Value
Value
Description
1
Drive CRC-on-Boot Output Pin to 1/Tri-state pin (depending on setting of nODCON configuration bit
0
Drive CRC-on-Boot Output Pin to 0
Bit 6 – BOOTDONE CRC-on-Boot on Previous Reset Status/ CRC-on-Bot on Next Reset Configuration
Value
Description
1
CRC-on-Boot has run on previous reset, run user code on next non-POR reset
0
Run CRC-on-Boot on next non-POR reset
Bit 1 – B1 CRC-on-Boot Output 1
Value
Description
1
No CRC mismatch in non-Boot Sector (Application sector, SAF sector, data EEPROM, CONFIG)
0
CRC mismatch in non-Boot Sector
Bit 0 – B0 CRC-on-Boot Output 0
Value
Description
1
No CRC mismatch in Boot Sector
0
CRC mismatch in Boot Sector
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CRC - Cyclic Redundancy Check Module with Memory S...
13.14
Address
0x00
...
0x37
0x38
0x39
...
0x034E
Register Summary - CRC
Name
Bit Pos.
7
6
7:0
BPOUT
BOOTDONE
5
4
3
2
1
0
B1
B0
SHIFTM
FULL
BURSTMD
BUSY
Reserved
BOOTREG
Reserved
0x034F
CRCDATA
0x0353
CRCOUT
0x0353
CRCSHIFT
0x0353
CRCXOR
0x0357
0x0358
0x0359
0x035A
...
0x035F
0x0360
0x0361
CRCCON0
CRCCON1
CRCCON2
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
7:0
7:0
EN
GO
BUSY
EN
TRIGEN
SGO
CRCDATAL[7:0]
CRCDATAH[7:0]
CRCDATAU[7:0]
CRCDATAT[7:0]
CRCOUTL[7:0]
CRCOUTH[7:0]
CRCOUTU[7:0]
CRCOUTT[7:0]
CRCSHIFTL[7:0]
CRCSHIFTH[7:0]
CRCSHIFTU[7:0]
CRCSHIFTT[7:0]
CRCXORL[7:0]
CRCXORH[7:0]
CRCXORU[7:0]
CRCXORT[7:0]
ACCM
SETUP[1:0]
PLEN[4:0]
DLEN[4:0]
Reserved
SCANCON0
SCANTRIG
7:0
7:0
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TSEL[4:0]
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Resets
14.
Resets
There are multiple ways to reset the device:
•
•
•
•
•
•
Power-on Reset (POR)
Brown-out Reset (BOR)
Low-Power Brown-out Reset (LPBOR)
MCLR Reset
WDT Reset
RESET instruction
•
•
•
•
•
•
Stack Overflow
Stack Underflow
Programming mode exit
Memory Execution Violation Reset
Main LDO Voltage Regulator Reset
Configuration Memory Reset
A simplified block diagram of the On-Chip Reset Circuit is shown in the block diagram below.
Figure 14-1. Simplified Block Diagram of On-Chip Reset Circuit
Re v. 10 -00 00 06 G
3/7/20 19
ICSP Programming Mode Exit
RESET Instruction
Memory Violation
Main LDO Voltage Regulator
Configuration Memory
Stack Underflow
Stack Overflow
VPP /MCLR
MCLRE
WWDT Time-out/
Window violation
Device
Reset
Power-on
Reset
VDD
Brown-out
Reset
Power-up
Timer
LFINTOSC
LPBOR
Reset
2
PWRTS
Note:
1. See BOR Operating Modes table for BOR active conditions.
14.1
Power-on Reset (POR)
The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow
rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR
or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The
POR bit will be set to ‘0’ if a Power-on Reset has occurred.
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Resets
14.2
Brown-out Reset (BOR)
The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level. Between the POR and
BOR, complete voltage range coverage for execution protection can be implemented. The BOR bit will be set to ‘0’ if
a Brown-out Reset has occurred.
The Brown-out Reset module has four operating modes controlled by the BOREN Configuration bits. The four
operating modes are:
•
•
•
•
BOR is always on
BOR is off when in Sleep
BOR is controlled by software
BOR is always off
Refer to the BOR Operating Modes table for more information.
A VDD noise rejection filter prevents the BOR from triggering on small events. If VDD falls below VBOR for a duration
greater than parameter TBORDC, the device will reset. Refer to the “Electrical Specifications” chapter for more
details.
14.2.1
BOR is Always ON
When the BOREN Configuration bits are programmed to 'b11, the BOR is always on. The device start-up will be
delayed until the BOR is ready and VDD is higher than the BOR threshold.
BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep.
14.2.2
BOR is OFF in Sleep
When the BOREN Configuration bits are programmed to 'b10, the BOR is on, except in Sleep. The device start-up
will be delayed until the BOR is ready and VDD is higher than the BOR threshold.
BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready.
14.2.3
BOR Controlled by Software
When the BOREN Configuration bits are programmed to 'b01, the BOR is controlled by the SBOREN bit. The device
start-up is not delayed by the BOR ready condition or the VDD level.
BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the BORRDY
bit.
BOR protection selected by SBOREN bit is unchanged by Sleep.
14.2.4
BOR is always OFF
When the BOREN Configuration bits are programmed to 'b00, the BOR is off at all times. The device start-up is not
delayed by the BOR ready condition or the VDD level.
Table 14-1. BOR Operating Modes
BOREN SBOREN Device Mode BOR Mode
11(1)
10
X
Instruction Execution upon:
Release of POR
Wake-up from Sleep
X
Active
Wait for release of BOR (BORRDY
= 1)
Begins immediately
Awake
Active
Wait for release of BOR (BORRDY
= 1)
N/A
Sleep
Hibernate
N/A
Wait for release of BOR
(BORRDY = 1)
X
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Resets
...........continued
Instruction Execution upon:
BOREN SBOREN Device Mode BOR Mode
01
00
1
X
Active
0
X
Hibernate
X
X
Disabled
Release of POR
Wake-up from Sleep
Wait for release of BOR (BORRDY
= 1)
Begins immediately
Begins immediately
Note:
1. In this specific case, “Release of POR” and “Wake-up from Sleep”, there is no BOR ready delay in start-up.
The BOR ready flag (BORRDY = 1) will be set before the CPU is ready to execute instructions because the
BOR circuit is forced on by the BOREN bits.
Figure 14-2. Brown-Out Situations
Rev. 30-000092A
4/12/2017
VDD
VBOR
Internal
Reset
TPWRT(1)
VDD
VBOR
Internal
Reset
< TPWRT
TPWRT(1)
VDD
VBOR
Internal
Reset
TPWRT(1)
Note:
1. TPWRT delay only if the Configuration bits enable the Power-up Timer.
14.2.5
BOR and Bulk Erase
BOR is forced ON during PFM Bulk Erase operations to make sure that the system code protection cannot be
compromised by reducing VDD.
During Bulk Erase, the BOR is enabled at the lowest BOR threshold level, even if it is configured to some other value.
If VDD falls, the erase cycle will be aborted, but the device will not be reset.
14.3
Low-Power Brown-out Reset (LPBOR)
The Low-Power Brown-out Reset (LPBOR) provides an additional BOR circuit for low-power operation. Refer to the
figure below to see how the BOR interacts with other modules.
The LPBOR is used to monitor the external VDD pin. When too low of a voltage is detected, the device is held in
Reset.
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Resets
Figure 14-3. LPBOR, BOR, POR Relationship
Rev. 30-000091B
6/21/2017
Any Reset
BOR
BOR Event
REARM POR
Event
To PCON
indicator bit
POR
LPBOR
POR Event
LPBOR Event
Reset
logic
14.3.1
Enabling LPBOR
The LPBOR is controlled by the LPBOREN Configuration bit. When the device is erased, the LPBOR module defaults
to disabled.
14.3.2
LPBOR Module Output
The output of the LPBOR module indicates whether or not a Reset is to be asserted. This signal is OR’d with the
Reset signal of the BOR module to provide the generic BOR signal, which goes to the PCON0 register and to the
power control block.
14.4
MCLR Reset
MCLR is an optional external input that can reset the device. The MCLR function is controlled by the MCLRE and
LVP Configuration bits (see table below). The RMCLR bit will be set to ‘0’ if a MCLR has occurred.
Table 14-2. MCLR Configuration
14.4.1
MCLRE
LVP
MCLR
x
1
Enabled
1
0
Enabled
0
0
Disabled
MCLR Enabled
When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR pin is connected to VDD
through an internal weak pull-up.
The device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses.
Important: An internal Reset event (RESET instruction, BOR, WWDT, POR, STKOVF, STKUNF) does not
drive the MCLR pin low.
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Resets
14.4.2
MCLR Disabled
When MCLR is disabled, the MCLR pin becomes input-only and pin functions such as internal weak pull-ups are
under software control.
14.5
Windowed Watchdog Timer (WWDT) Reset
The Windowed Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the
time-out period or window set. The TO and PD bits in the STATUS register and the RWDT bit are changed to indicate
a WDT Reset. The WDTWV bit indicates if the WDT Reset has occurred due to a time-out or a window violation.
14.6
RESET Instruction
A RESET instruction will cause a device Reset. The RI bit will be set to ‘0’. See Table 14-3 for default conditions after
a RESET instruction has occurred.
14.7
Stack Overflow/Underflow Reset
The device can be reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits indicate the Reset
condition. These Resets are enabled by setting the STVREN Configuration bit.
14.8
Programming Mode Exit
Upon exit of Programming mode, the device will operate as if a POR had just occurred.
14.9
Power-up Timer (PWRT)
The Power-up Timer provides a selected time-out duration on POR or Brown-out Reset.
The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for VDD to rise to an
acceptable level. The Power-up Timer is selected by setting the PWRTS Configuration bits accordingly.
The Power-up Timer starts after the release of the POR and BOR/LPBOR if enabled, as shown in Figure 14-4.
14.10
Start-up Sequence
Upon the release of a POR or BOR, the following must occur before the device will begin executing:
1.
2.
3.
Power-up Timer runs to completion (if enabled).
Oscillator Start-up Timer runs to completion (if required for selected oscillator source).
MCLR must be released (if enabled).
The total time-out will vary based on the oscillator configuration and Power-up Timer configuration.
The Power-up Timer and Oscillator Start-up Timer run independently of MCLR Reset. If MCLR is kept low long
enough, the Power-up Timer and Oscillator Start-up Timer will expire. Upon bringing MCLR high, the device will begin
execution after 10 FOSC cycles (see figure below). This is useful for testing purposes or to synchronize more than one
device operating in parallel.
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Resets
Figure 14-4. Reset Start-Up Sequence
Rev. 30-000093A
4/12/2017
VDD
Internal POR
TPWRT
Power-up Timer
MCLR
TMCLR
Internal RESET
Oscillator Modes
External Crystal
TOST
Oscillator Start-up Timer
Oscillator
FOSC
Internal Oscillator
Oscillator
FOSC
External Clock (EC)
CLKIN
FOSC
14.10.1 Memory Execution Violation
A memory execution violation Reset occurs if executing an instruction being fetched from outside the valid execution
area. The invalid execution areas are:
1. Addresses outside implemented program memory
2. Storage Area Flash (SAF) inside program memory, if it is enabled
When a memory execution violation is generated, the device is reset and the MEMV bit is cleared to signal the cause
of the Reset. The MEMV bit must be set in the user code after a memory execution violation Reset has occurred to
detect further violation Resets.
14.11
Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and PCON0 registers are updated to indicate the cause of the Reset.
The following table shows the Reset conditions of these registers.
Table 14-3. Reset Condition for Special Registers
Program
Counter
STATUS
Register(1,2)
PCON0 Register
PCON1 Register
Power-on Reset
0
-110 0000
0011 110x
---- -111
Brown-out Reset
0
-110 0000
0011 11u0
---- -u1u
Condition
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Resets
...........continued
Program
Counter
STATUS
Register(1,2)
PCON0 Register
PCON1 Register
MCLR Reset during
normal operation
0
-uuu uuuu
uuuu 0uuu
---- -uuu
MCLR Reset during
Sleep
0
-10u uuuu
uuuu 0uuu
---- -uuu
WDT Time-out Reset
0
-0uu uuuu
uuu0 uuuu
---- -uuu
WDT Wake-up from
Sleep
PC + 2
-00u uuuu
uuuu uuuu
---- -uuu
0
-uuu uuuu
uu0u uuuu
---- -uuu
Interrupt Wake-up
from Sleep
PC + 2(3)
-10u uuuu
uuuu uuuu
---- -uuu
RESET Instruction
Executed
0
-uuu uuuu
uuuu u0uu
---- -uuu
Stack Overflow Reset
(STVREN = 1)
0
-uuu uuuu
1uuu uuuu
---- -uuu
Stack Underflow
Reset (STVREN = 1)
0
-uuu uuuu
u1uu uuuu
---- -uuu
Data Protection
(Fuse Fault)
0
-uuu uuuu
uuuu uuuu
---- -uu0
VREG or ULP Ready
Fault
0
-110 0000
0011 110u
---- -0u1
Memory Violation
Reset
0
-uuu uuuu
uuuu uuuu
---- -u0u
Condition
WWDT Window
Violation Reset
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Notes:
1. If a Status bit is not implemented, that bit will be read as ‘0’.
2.
3.
14.12
Status bits Z, C, DC are reset by POR/BOR.
When the wake-up is due to an interrupt and Global Interrupt Enable (GIE) bit is set, the return address is
pushed on the stack and PC is loaded with the corresponding interrupt vector (depending on source, high or
low priority) after execution of PC + 2.
Power Control (PCON0/PCON1) Registers
The Power Control (PCON0/PCON1) registers contains flag bits to differentiate between the following reset events:
•
•
•
•
•
•
•
•
•
Brown-out Reset (BOR)
Power-on Reset (POR)
Reset Instruction Reset (RI)
MCLR Reset (RMCLR)
Watchdog Timer Reset (RWDT)
Watchdog Window Violation (WDTWV)
Stack Underflow Reset (STKUNF)
Stack Overflow Reset (STKOVF)
Configuration Memory Reset (RCM)
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Resets
•
•
Memory Violation Reset (MEMV)
Main LDO Voltage Regulator Reset (RVREG)
Hardware will change the corresponding register bit or bits as a result of the Reset event. Bits for other Reset events
remain unchanged. See Table 14-3 for more details.
Software will reset the bit to the Inactive state after restart. (Hardware will not reset the bit.)
Software may also set any PCON0 bit to the Active state, so that user code may be tested, but no Reset action will
be generated.
14.13
Register Definitions: Power Control
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Resets
14.13.1 BORCON
Name:
Address:
BORCON
0x049
Brown-out Reset Control Register
Bit
Access
Reset
7
SBOREN
R/W
1
6
5
4
3
2
1
0
BORRDY
R
q
Bit 7 – SBOREN Software Brown-out Reset Enable
Reset States: POR/BOR = 1
All Other Resets = u
Value
Condition
Description
—
If BOREN ≠ 01
SBOREN is read/write, but has no effect on the BOR
1
If BOREN = 01
BOR Enabled
0
If BOREN = 01
BOR Disabled
Bit 0 – BORRDY Brown-out Reset Circuit Ready Status
Reset States: POR/BOR = q
All Other Resets = u
Value
Description
1
The Brown-out Reset Circuit is active and armed
0
The Brown-out Reset Circuit is disabled or is warming up
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Resets
14.13.2 PCON0
Name:
Address:
PCON0
0x4F0
Power Control Register 0
Bit
Access
Reset
7
STKOVF
R/W/HS
0
6
STKUNF
R/W/HS
0
5
WDTWV
R/W/HC
1
4
RWDT
R/W/HC
1
3
RMCLR
R/W/HC
1
2
RI
R/W/HC
1
1
POR
R/W/HC
0
0
BOR
R/W/HC
q
Bit 7 – STKOVF Stack Overflow Flag
Reset States: POR/BOR = 0
All Other Resets = q
Value
Description
1
A Stack Overflow occurred (more CALLs than fit on the stack)
0
A Stack Overflow has not occurred or set to ‘0’ by firmware
Bit 6 – STKUNF Stack Underflow Flag
Reset States: POR/BOR = 0
All Other Resets = q
Value
Description
1
A Stack Underflow occurred (more RETURNs than CALLs)
0
A Stack Underflow has not occurred or set to ‘0’ by firmware
Bit 5 – WDTWV Watchdog Window Violation Flag
Reset States: POR/BOR = 1
All Other Resets = q
Value
Description
1
A WDT window violation has not occurred or set to ‘1’ by firmware
0
A CLRWDT instruction was issued when the WDT Reset window was closed (set to ‘0’ in hardware
when a WDT window violation Reset occurs)
Bit 4 – RWDT WDT Reset Flag
Reset States: POR/BOR = 1
All Other Resets = q
Value
Description
1
A WDT overflow/time-out Reset has not occurred or set to ‘1’ by firmware
0
A WDT overflow/time-out Reset has occurred (set to ‘0’ in hardware when a WDT Reset occurs)
Bit 3 – RMCLR MCLR Reset Flag
Reset States: POR/BOR = 1
All Other Resets = q
Value
Description
1
A MCLR Reset has not occurred or set to ‘1’ by firmware
0
A MCLR Reset has occurred (set to ‘0’ in hardware when a MCLR Reset occurs)
Bit 2 – RI RESET Instruction Flag
Reset States: POR/BOR = 1
All Other Resets = q
Value
Description
1
A RESET instruction has not been executed or set to ‘1’ by firmware
0
A RESET instruction has been executed (set to ‘0’ in hardware upon executing a RESET instruction)
Bit 1 – POR Power-on Reset Status
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Resets
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
No Power-on Reset occurred or set to ‘1’ by firmware
0
A Power-on Reset occurred (set to ‘0’ in hardware when a Power-on Reset occurs)
Bit 0 – BOR Brown-out Reset Status
Reset States: POR/BOR = q
All Other Resets = u
Value
Description
1
No Brown-out Reset occurred or set to ‘1’ by firmware
0
A Brown-out Reset occurred (set to ‘0’ in hardware when a Brown-out Reset occurs)
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Resets
14.13.3 PCON1
Name:
Address:
PCON1
0x4F1
Power Control Register 1
Bit
7
6
5
4
3
Access
Reset
2
RVREG
R/W/HC
1
1
MEMV
R/W/HC
0
0
RCM
R/W/HC
q
Bit 2 – RVREG Main LDO Voltage Regulator Reset Flag
Reset States: POR/BOR = 1
All Other Resets = q
Value
Description
1
No LDO or ULP “ready” Reset has occurred or set to ‘1’ by firmware
0
LDO or ULP “ready” Reset has occurred (VDDCORE reached its minimum spec)
Bit 1 – MEMV Memory Violation Reset Flag
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
No memory violation Reset occurred or set to ‘1’ by firmware
0
A memory violation Reset occurred (set to ‘0’ in hardware when a Memory Violation occurs)
Bit 0 – RCM Configuration Memory Reset Flag
Reset States: POR/BOR = q
All Other Resets = u
Value
Description
1
A Reset occurred due to corruption of the configuration and/or calibration data latches
0
The configuration and calibration latches have not been corrupted
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Resets
14.14
Address
0x00
...
0x48
0x49
0x4A
...
0x04EF
0x04F0
0x04F1
Register Summary - BOR Control and Power Control
Name
Bit Pos.
7
7:0
SBOREN
7:0
7:0
STKOVF
6
5
4
3
2
1
0
Reserved
BORCON
BORRDY
Reserved
PCON0
PCON1
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STKUNF
WDTWV
RWDT
RMCLR
Preliminary Datasheet
RI
RVREG
POR
MEMV
BOR
RCM
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WWDT - Windowed Watchdog Timer
15.
WWDT - Windowed Watchdog Timer
A Watchdog Timer (WDT) is a system timer that generates a Reset if the firmware does not issue a CLRWDT
instruction within the time-out period. A Watchdog Timer is typically used to recover the system from unexpected
events. The Windowed Watchdog Timer (WWDT) differs from non-windowed operation in that CLRWDT instructions
are only accepted when they are performed within a specific window during the time-out period.
The WWDT has the following features:
• Selectable clock source
• Multiple operating modes
– WWDT is always on
– WWDT is off when in Sleep
– WWDT is controlled by software
– WWDT is always off
• Configurable time-out period from 1 ms to 256s (nominal)
• Configurable window size from 12.5% to 100% of the time-out period
• Multiple Reset conditions
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WWDT - Windowed Watchdog Timer
Figure 15-1. Windowed Watchdog Timer Block Diagram
WWDT
Armed
WDT
Window
Violation
Window Closed
CLRWDT
Window
Sizes
Comparator
WINDOW
RESET
..
.
See
WDTCON1
Register
..
.
R
18-bit Prescale
Counter
E
CS
PS
R
5-bit
WDT Counter
Overflow
Latch
WDT Time-out
WDTE = b01
SEN
WDTE = b11
WDTE = b10
Sleep
15.1
Independent Clock Source
The WWDT can derive its time base from either the 31 KHz LFINTOSC or 31.25 kHz MFINTOSC internal oscillators,
depending on the value of WDT Operating Mode (WDTE) Configuration bits. If WDTE = 'b1x, then the clock
source will be enabled depending on the WDTCCS Configuration bits. If WDTE = 'b01, the SEN bit will be set by
software to enable WWDT, and the clock source is enabled by the CS bits. Time intervals in this chapter are based
on a minimum nominal interval of 1 ms. See the device Electrical Specifications for LFINTOSC and MFINTOSC
tolerances.
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WWDT - Windowed Watchdog Timer
15.2
WWDT Operating Modes
The Windowed Watchdog Timer module has four operating modes that are controlled by the WDTE Configuration bit.
The table below summarizes the different WWDT operating modes.
Table 15-1. WWDT Operating Modes
WDTE
SEN
Device Mode
WWDT Mode
11
X
X
Active
10
X
Awake
Active
Sleep
Disabled
1
X
Active
0
X
Disabled
X
X
Disabled
01
00
15.2.1
WWDT Is Always On
When the WDTE Configuration bits are set to 'b11, the WWDT is always on. WWDT protection is active during
Sleep.
15.2.2
WWDT is Off in Sleep
When the WDTE Configuration bits are set to 'b10, the WWDT is on, except in Sleep mode. WWDT protection is not
active during Sleep.
15.2.3
WWDT Controlled by Software
hen the WDTE Configuration bits are set to 'b01, the WWDT is controlled by the SEN bit. WWDT protection is
unchanged by Sleep. See Table 15-1 for more details.
15.3
Time-out Period
When the WDTCPS Configuration bits are set to the default value of 'b11111, the PS bits set the time-out
period from 1 ms to 256 seconds (nominal). If any value other than the default value is assigned to the WDTCPS
Configuration bits, then the timer period will be based on the WDTCPS Configuration bits. After a Reset, the default
time-out period is 2s.
15.4
Watchdog Window
The Windowed Watchdog Timer has an optional Windowed mode that is controlled by either the WDTCWS
Configuration bits or the WINDOW bits. In the Windowed mode (WINDOW < 'b1111), the CLRWDT instruction
must occur within the allowed window of the WDT period. Any CLRWDT instruction that occurs outside of this window
will trigger a window violation and will cause a WWDT Reset, similar to a WWDT time-out. See Figure 15-2 for an
example.
When the WDTCWS Configuration bits are 'b111 then the window size is controlled by the WINDOW bits, otherwise
the window size is controlled by the WDTCWS bits. The five Most Significant bits of the WDTTMR register are used
to determine whether the window is open, as defined by the window size. In the event of a window violation, a Reset
will be generated and the WDTWV bit of the PCON0 register will be cleared. This bit is set by a POR and can be set
by software.
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WWDT - Windowed Watchdog Timer
Figure 15-2. Window Period and Delay
CLRWDT Instruction
(or other WDT Reset)
Window Period
Window Closed
Window Open
Window Delay
(window violation can occur)
15.5
Time-out Event
Clearing the Watchdog Timer
The Watchdog Timer is cleared when any of the following conditions occur:
• Any Reset
• A valid CLRWDT instruction is executed
•
•
•
•
•
15.5.1
The device enters Sleep
The devices exits Sleep by Interrupt
The WWDT is disabled
The Oscillator Start-up Timer (OST) is running
Any write to the WDTCON0 or WDTCON1 registers
CLRWDT Considerations (Windowed Mode)
When in Windowed mode, the WWDT must be armed before a CLRWDT instruction will clear the timer. This is
performed by reading the WDTCON0 register. Executing a CLRWDT instruction without performing such an arming
action will trigger a window violation regardless of whether the window is open or not. See Table 15-2 for more
information.
15.6
Operation During Sleep
When the device enters Sleep, the Watchdog Timer is cleared. If the WWDT is enabled during Sleep, the Watchdog
Timer resumes counting. When the device exits Sleep, the Watchdog Timer is cleared again. The Watchdog Timer
remains clear until the Oscillator Start-up Timer (OST) completes, if enabled. When a WWDT time-out occurs while
the device is in Sleep, no Reset is generated. Instead, the device wakes up and resumes operation. The TO and PD
bits in the STATUS register are changed to indicate the event. The RWDT bit in the PCON0 register indicates that a
Watchdog Reset has occurred.
Table 15-2. WWDT Clearing Conditions
Conditions
WWDT
WDTE = 'b00
WDTE = 'b01 and SEN = 0
WDTE = 'b10 and enter Sleep
Cleared
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = SOSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP
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WWDT - Windowed Watchdog Timer
...........continued
Conditions
WWDT
Change INTOSC divider (IRCF bits)
15.7
Unaffected
Register Definitions: Windowed Watchdog Timer Control
Long bit name prefixes for the Reference Clock peripherals are shown in the following table. Refer to the "Long Bit
Names" section in the “Register and Bit Naming Conventions” chapter for more information.
Peripheral
Bit Name Prefix
WDT
WDT
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WWDT - Windowed Watchdog Timer
15.7.1
WDTCON0
Name:
Address:
WDTCON0
0x078
Watchdog Timer Control Register 0
Bit
7
6
Access
Reset
5
4
R/W
q
R/W
q
3
PS[4:0]
R/W
q
2
1
R/W
q
R/W
q
0
SEN
R/W
0
Bits 5:1 – PS[4:0] Watchdog Timer Prescaler Select(2)
Value
Description
11111 to Reserved. Results in minimum interval (1 ms)
10011
10010
1:8388608 (223) (Interval 256s nominal)
10001
1:4194304 (222) (Interval 128s nominal)
10000
1:2097152 (221) (Interval 64s nominal)
01111
1:1048576 (220) (Interval 32s nominal)
01110
1:524288 (219) (Interval 16s nominal)
01101
1:262144 (218) (Interval 8s nominal)
01100
1:131072 (217) (Interval 4s nominal)
01011
1:65536 (Interval 2s nominal) (Reset value)
01010
1:32768 (Interval 1s nominal)
01001
1:16384 (Interval 512 ms nominal)
01000
1:8192 (Interval 256 ms nominal)
00111
1:4096 (Interval 128 ms nominal)
00110
1:2048 (Interval 64 ms nominal)
00101
1:1024 (Interval 32 ms nominal)
00100
1:512 (Interval 16 ms nominal)
00011
1:256 (Interval 8 ms nominal)
00010
1:128 (Interval 4 ms nominal)
00001
1:64 (Interval 2 ms nominal)
00000
1:32 (Interval 1 ms nominal)
Bit 0 – SEN Software Enable/Disable for Watchdog Timer
Value
Condition
Description
x
1
0
x
If WDTE = 1x
If WDTE = 01
If WDTE = 01
If WDTE = 00
This bit is ignored
WDT is turned on
WDT is turned off
This bit is ignored
Notes:
1. When the WDTCPS Configuration bits = 'b11111, the Reset value (q) of WDTPS is 'b01011. Otherwise, the
Reset value of WDTPS is equal to the WDTCPS in Configuration bits.
2. When the WDTCPS in Configuration bits ≠ 'b11111, these bits are read-only.
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WWDT - Windowed Watchdog Timer
15.7.2
WDTCON1
Name:
Address:
WDTCON1
0x079
Watchdog Timer Control Register 1
Bit
7
Access
Reset
6
5
CS[2:0]
R/W
q
R/W
q
4
3
2
R/W
q
R/W
q
1
WINDOW[2:0]
R/W
q
0
R/W
q
Bits 6:4 – CS[2:0] Watchdog Timer Clock Select(1,3)
CS
Clock Source
111-100
011
010
001
000
Reserved
EXTOSC
SOSC
MFINTOSC (31.25 kHz)
LFINTOSC (31 kHz)
Bits 2:0 – WINDOW[2:0] Watchdog Timer Window Select(2,4)
WINDOW
Window Delay Percent of Time
Window Opening Percent of Time
111
110
101
100
011
010
001
000
N/A
12.5
25
37.5
50
62.5
75
87.5
100
87.5
75
62.5
50
37.5
25
12.5
Notes:
1. When the WDTCCS in Configuration bits = '0b111, the Reset value of WDTCS is 'b000.
2.
3.
The Reset value (q) of WINDOW is determined by the value of WDTCWS in the Configuration bits.
When the WDTCCS in Configuration bits ≠ 'b111, these bits are read-only.
4.
When the WDTCWS in Configuration bits ≠ 'b111, these bits are read-only.
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WWDT - Windowed Watchdog Timer
15.7.3
WDTPSH
Name:
Address:
WDTPSH
0x07B
WWDT Prescaler Select Register (Read-Only)
Bit
7
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
PSCNTH[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 7:0 – PSCNTH[7:0] Prescaler Select High Byte(1)
Note:
1. The 18-bit WDT prescaler value, PSCNT[17:0] includes the WDTPSL, WDTPSH and the lower bits of the
WDTTMR registers. PSCNT[17:0] is intended for debug operations and will be read during normal operation.
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WWDT - Windowed Watchdog Timer
15.7.4
WDTPSL
Name:
Address:
WDTPSL
0x07A
WWDT Prescaler Select Register (Read-Only)
Bit
7
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
PSCNTL[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 7:0 – PSCNTL[7:0] Prescaler Select Low Byte(1)
Note:
1. The 18-bit WDT prescaler value, PSCNT[17:0] includes the WDTPSL, WDTPSH and the lower bits of the
WDTTMR registers. PSCNT[17:0] is intended for debug operations and will be read during normal operation.
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WWDT - Windowed Watchdog Timer
15.7.5
WDTTMR
Name:
Address:
WDTTMR
0x07C
WDT Timer Register (Read-Only)
Bit
Access
Reset
7
6
R
0
R
0
5
TMR[4:0]
R
0
4
3
R
0
2
STATE
R
0
R
0
1
0
PSCNT[17:16]
R
0
R
0
Bits 7:3 – TMR[4:0] Watchdog Window Value
WINDOW
111
110
101
100
011
010
001
000
WDT Window State
Open Percent
Closed
Open
N/A
00000-00011
00000-00111
00000-01011
00000-01111
00000-10011
00000-10111
00000-11011
00000-11111
00100-11111
01000-11111
01100-11111
10000-11111
10100-11111
11000-11111
11100-11111
100
87.5
75
62.5
50
37.5
25
12.5
Bit 2 – STATE WDT Armed Status
Value
Description
1
WDT is armed
0
WDT is not armed
Bits 1:0 – PSCNT[17:16] Prescaler Select Upper Byte(1)
Note:
1. The 18-bit WDT prescaler value, PSCNT[17:0] includes the WDTPSL, WDTPSH and the lower bits of the
WDTTMR registers. PSCNT[17:0] is intended for debug operations and will not be read during normal
operation.
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WWDT - Windowed Watchdog Timer
15.8
Address
0x00
...
0x77
0x78
0x79
0x7A
0x7B
0x7C
Register Summary: WDT Control
Name
Bit Pos.
7
6
5
4
3
2
1
0
Reserved
WDTCON0
WDTCON1
WDTPSL
WDTPSH
WDTTMR
7:0
7:0
7:0
7:0
7:0
© 2021 Microchip Technology Inc.
PS[4:0]
SEN
CS[2:0]
WINDOW[2:0]
PSCNTL[7:0]
PSCNTH[7:0]
TMR[4:0]
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STATE
PSCNT[17:16]
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DMA - Direct Memory Access
16.
DMA - Direct Memory Access
The Direct Memory Access (DMA) module is designed to service data transfers between different memory regions
directly, without intervention from the CPU. By eliminating the need for CPU-intensive management of handling
interrupts intended for data transfers, the CPU now can spend more time on other tasks.
The DMA modules can be independently programmed to transfer data between different memory locations, move
different data sizes, and use a wide range of hardware triggers to initiate transfers. The DMA modules can even be
programmed to work together, in order to carry out more complex data transfers without CPU overhead.
Key features of the DMA module include:
• Support access to the following memory regions:
– GPR and SFR space (R/W)
– Program Flash memory (R only)
– Data EEPROM memory (R only)
• Programmable priority between the DMA and CPU operations. Refer to the “System Arbitration” section in the
“PIC18 CPU” chapter for details.
• Programmable Source and Destination Address modes:
– Fixed address
– Post-increment address
– Post-decrement address
• Programmable source and destination sizes
• Source and Destination Pointer register, dynamically updated and reloadable
• Source and Destination Count register, dynamically updated and reloadable
• Programmable auto-stop based on source or destination counter
• Software triggered transfers
• Multiple user-selectable sources for hardware triggered transfers
• Multiple user-selectable sources for aborting DMA transfers
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DMA - Direct Memory Access
16.1
DMA Registers
The operation of the DMA module is controlled by the following registers:
•
•
•
•
•
•
•
•
•
•
•
•
•
DMA Instance Selection (DMASELECT) register
Control (DMAnCON0, DMAnCON1) registers
Data Buffer (DMAnBUF) register
Source Start Address (DMAnSSA) register
Source Pointer (DMAnSPTR) register
Source Message Size (DMAnSSZ) register
Source Count (DMAnSCNT) register
Destination Start Address (DMAnDSA) register
Destination Pointer (DMAnDPTR) register
Destination Message Size (DMAnDSZ) register
Destination Count (DMAnDCNT) register
Start Interrupt Request Source (DMAnSIRQ) register
Abort Interrupt Request Source (DMAnAIRQ) register
The registers are detailed in Register Definitions: DMA.
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DMA - Direct Memory Access
16.2
DMA Organization
The DMA module is designed to move data by using the existing instruction bus and data bus without the need for
any dual-porting of memory or peripheral systems (Figure 16-1). The DMA accesses the required bus when granted
by the system arbiter.
Figure 16-1. DMA Functional Block Diagram
Rev. 10-000271A
11/8/2018
DMA1
Control Registers
Source Start Address
Source Size
Destination Start Address
..
..
.
Program Flash
Memory
System Arbiter
Destination Size
Data EEPROM
GPR/SFR
RAM Space
DMAn
Control Registers
Source Start Address
Source Size
Priority
Destination Start Address
Destination Size
Depending on the priority of the DMA with respect to CPU execution (Refer to section “Memory Access Scheme” in
the “PIC18 CPU” chapter for more information), the DMA Controller can move data through two methods:
•
•
16.3
Stalling the CPU execution until it has completed its transfers (DMA has higher priority over the CPU in this
mode of operation).
Utilizing unused CPU cycles for DMA transfers (CPU has higher priority over the DMA in this mode of
operation). Unused CPU cycles are referred to as bubbles, which are instruction cycles available for use by the
DMA to perform read and write operations. In this way, the effective bandwidth for handling data is increased; at
the same time, DMA operations can proceed without causing a processor stall.
DMA Interface
The DMA module transfers data from the source to the destination one byte at a time, this smallest data movement is
called a DMA data transaction. A DMA message refers to one or more DMA data transactions.
Each DMA data transaction consists of two separate actions:
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DMA - Direct Memory Access
•
•
Reading the source address memory and storing the value in the DMA Buffer register
Writing the contents of the DMA Buffer register to the destination address memory
Important: DMA data movement is a two-cycle operation.
The XIP bit is a Status bit to indicate whether or not the data in the DMAnBUF register has been written to the
destination address. If the bit is set, then data is waiting to be written to the destination. If clear, it means that either
data has been written to the destination or that no source read has occurred.
The DMA has read access to PFM, Data EEPROM, and SFR/GPR space, and write access to SFR/GPR space.
Based on these memory access capabilities, the DMA can support the following memory transactions:
Table 16-1. DMA MEMORY ACCESS
Read Source
Write Destination
Program Flash Memory
GPR
Program Flash Memory
SFR
Data EE
GPR
Data EE
SFR
GPR
GPR
GPR
SFR
SFR
GPR
SFR
SFR
Important: Even though the DMA module has access to all memory and peripherals that are also
available to the CPU, it is recommended that the DMA does not access any register that is part of the
system arbitration. The DMA, as a system arbitration client must not be read or written by itself or by
another DMA instantiation.
The following sections discuss the various control interfaces required for DMA data transfers.
16.3.1
Special Function Registers with DMA Access only
The DMA can transfer data to any GPR or SFR location. For better user accessibility, some of the more commonly
used SFR spaces have their mirror registers placed in a separate data memory location. These mirror registers can
be only accessed by the DMA module through the DMA Source and Destination Address registers. The figure below
shows the register map for these registers.
These registers are useful to multiple peripherals together like the Timers, PWMs and also other DMA modules using
one of the DMA modules.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 282
PIC18F27/47/57Q84
DMA - Direct Memory Access
Figure 16-2. Special Function Register Map (DMA Access Only)
40FFh
40FEh
40FDh
40FCh
40FBh
40FAh
40F9h
40F8h
40F7h
40F6h
40F5h
40F4h
40F3h
40F2h
40F1h
40F0h
40EFh
40EEh
40EDh
40ECh
40CBh
40EAh
40E9h
40E8h
40E7h
40E6h
40E5h
40E4h
40E3h
40E2h
40E1h
40E0h
41FFh
41FEh
41FDh
41FCh
41FBh
41FAh
41F9h
41F8h
41F7h
41F6h
41F5h
41F4h
41F3h
41F2h
41F1h
41F0h
41EFh
41EEh
41EDh
41ECh
41CBh
41EAh
41E9h
41E8h
41E7h
41E6h
41E5h
41E4h
41E3h
41E2h
41E1h
41E0h
16.3.2
ADRESH_M1
ADRESL_M1
ADPCH_M1
ADCAP_M1
ADACQH_M1
ADACQL_M1
ADPREVH_M1
ADPREVL_M1
ADRPT_M1
ADCNT_M1
ADACCU_M1
ADACCH_M1
ADACCL_M1
ADFLTRH_M1
ADFLTRL_M1
ADSTPTH_M1
ADSTPTL_M1
ADERRH_M1
ADERRL_M1
ADUTHH_M1
ADUTHL_M1
ADLTHH_M1
ADLTHL_M1
40DFh
40DEh
40DDh
40DCh
40DBh
40DAh
40D9h
40D8h
40D7h
40D6h
40D5h
40D4h
40D3h
40D2h
40D1h
40D0h
40CFh
40CEh
40CDh
40CCh
40CBh
40CAh
40C9h
40C8h
40C7h
40C6h
40C5h
40C4h
40C3h
40C2h
40C1h
40C0h
CX4_ADPREH_M1
CX4_ADPREL_M1
CX4_ADRESH_M1
CX4_ADRESL_M1
CX4_ADPCH_M1
CX4_ADCLK_M1
CX4_ADACT_M1
CX4_ADREF_M1
CX4_ADCON3_M1
CX4_ADCON2_M1
CX4_ADCON1_M1
CX4_ADCON0_M1
CX4_ADCAP_M1
CX4_ADACQH_M1
CX4_ADACQL_M1
CX4_ADPREVH_M1
CX4_ADPREVL_M1
CX4_ADRPT_M1
CX4_ADCNT_M1
CX4_ADACCU_M1
CX4_ADACCH_M1
CX4_ADACCL_M1
CX4_ADFLTRH_M1
CX4_ADFLTRL_M1
CX4_ADSTPTH_M1
CX4_ADSTPTL_M1
CX4_ADERRH_M1
CX4_ADERRL_M1
CX4_ADUTHH_M1
CX4_ADUTHL_M1
CX4_ADLTHH_M1
CX4_ADLTHL_M1
40BFh
40BEh
40BDh
40BCh
40BBh
40BAh
40B9h
40B8h
40B7h
40B6h
40B5h
40B4h
40B3h
40B2h
40B1h
40B0h
40AFh
40AEh
40ADh
40ACh
40ABh
40AAh
40A9h
40A8h
40A7h
40A6h
40A5h
40A4h
40A3h
40A2h
40A1h
40A0h
CX3_ADPREH_M1
CX3_ADPREL_M1
CX3_ADRESH_M1
CX3_ADRESL_M1
CX3_ADPCH_M1
CX3_ADCLK_M1
CX3_ADACT_M1
CX3_ADREF_M1
CX3_ADCON3_M1
CX3_ADCON2_M1
CX3_ADCON1_M1
CX3_ADCON0_M1
CX3_ADCAP_M1
CX3_ADACQH_M1
CX3_ADACQL_M1
CX3_ADPREVH_M1
CX3_ADPREVL_M1
CX3_ADRPT_M1
CX3_ADCNT_M1
CX3_ADACCU_M1
CX3_ADACCH_M1
CX3_ADACCL_M1
CX3_ADFLTRH_M1
CX3_ADFLTRL_M1
CX3_ADSTPTH_M1
CX3_ADSTPTL_M1
CX3_ADERRH_M1
CX3_ADERRL_M1
CX3_ADUTHH_M1
CX3_ADUTHL_M1
CX3_ADLTHH_M1
CX3_ADLTHL_M1
409Fh
409Eh
409Dh
409Ch
409Bh
409Ah
4099h
4098h
4097h
4096h
4095h
4094h
4093h
4092h
4091h
4090h
408Fh
408Eh
408Dh
408Ch
408Bh
408Ah
4089h
4088h
4087h
4086h
4085h
4084h
4083h
4082h
4081h
4080h
CX2_ADPREH_M1
CX2_ADPREL_M1
CX2_ADRESH_M1
CX2_ADRESL_M1
CX2_ADPCH_M1
CX2_ADCLK_M1
CX2_ADACT_M1
CX2_ADREF_M1
CX2_ADCON3_M1
CX2_ADCON2_M1
CX2_ADCON1_M1
CX2_ADCON0_M1
CX2_ADCAP_M1
CX2_ADACQH_M1
CX2_ADACQL_M1
CX2_ADPREVH_M1
CX2_ADPREVL_M1
CX2_ADRPT_M1
CX2_ADCNT_M1
CX2_ADACCU_M1
CX2_ADACCH_M1
CX2_ADACCL_M1
CX2_ADFLTRH_M1
CX2_ADFLTRL_M1
CX2_ADSTPTH_M1
CX2_ADSTPTL_M1
CX2_ADERRH_M1
CX2_ADERRL_M1
CX2_ADUTHH_M1
CX2_ADUTHL_M1
CX2_ADLTHH_M1
CX2_ADLTHL_M1
407Fh
407Eh
407Dh
407Ch
407Bh
407Ah
4079h
4078h
4077h
4076h
4075h
4074h
4073h
4072h
4071h
4070h
406Fh
406Eh
406Dh
406Ch
406Bh
406Ah
4069h
4068h
4067h
4066h
4065h
4064h
4063h
4062h
4061h
4060h
CX1_ADPREH_M1
CX1_ADPREL_M1
CX1_ADRESH_M1
CX1_ADRESL_M1
CX1_ADPCH_M1
CX1_ADCLK_M1
CX1_ADACT_M1
CX1_ADREF_M1
CX1_ADCON3_M1
CX1_ADCON2_M1
CX1_ADCON1_M1
CX1_ADCON0_M1
CX1_ADCAP_M1
CX1_ADACQH_M1
CX1_ADACQL_M1
CX1_ADPREVH_M1
CX1_ADPREVL_M1
CX1_ADRPT_M1
CX1_ADCNT_M1
CX1_ADACCU_M1
CX1_ADACCH_M1
CX1_ADACCL_M1
CX1_ADFLTRH_M1
CX1_ADFLTRL_M1
CX1_ADSTPTH_M1
CX1_ADSTPTL_M1
CX1_ADERRH_M1
CX1_ADERRL_M1
CX1_ADUTHH_M1
CX1_ADUTHL_M1
CX1_ADLTHH_M1
CX1_ADLTHL_M1
405Fh
405Eh
405Dh
405Ch
405Bh
405Ah
4059h
4058h
4057h
4056h
4055h
4054h
4053h
4052h
4051h
4050h
404Fh
404Eh
404Dh
404Ch
404Bh
404Ah
4049h
4048h
4047h
4046h
4045h
4044h
4043h
4042h
4041h
4040h
T6PR_M1
CCPR3H_M2
CCPR3L_M2
T4PR_M1
CCPR2H_M2
CCPR2L_M2
T2PR_M1
CCPR1H_M2
CCPR1L_M2
TMR5H_M1
TMR5L_M1
TMR3H_M1
TMR3L_M1
TMR1H_M1
TMR1L_M1
IOCEF_M1
IOCCF_M1
IOCBF_M1
IOCAF_M1
41DFh
41DEh
41DDh
41DCh
41DBh
41DAh
41D9h
41D8h
41D7h
41D6h
41D5h
41D4h
41D3h
41D2h
41D1h
41D0h
41CFh
41CEh
41CDh
41CCh
41CBh
41CAh
41C9h
41C8h
41C7h
41C6h
41C5h
41C4h
41C3h
41C2h
41C1h
41C0h
-
41BFh
41BEh
41BDh
41BCh
41BBh
41BAh
41B9h
41B8h
41B7h
41B6h
41B5h
41B4h
41B3h
41B2h
41B1h
41B0h
41AFh
41AEh
41ADh
41ACh
41ABh
41AAh
41A9h
41A8h
41A7h
41A6h
41A5h
41A4h
41A3h
41A2h
41A1h
41A0h
DMAnSIRQ_DMA8
DMAnAIRQ_DMA8
DMAnCON1_DMA8
DMAnCON0_DMA8
DMAnSSAU_DMA8
DMAnSSAH_DMA8
DMAnSSAL_DMA8
DMAnSSZH_DMA8
DMAnSSZL_DMA8
DMAnSPTRU_DMA8
DMAnSPTRH_DMA8
DMAnSPTRL_DMA8
DMAnSCNTH_DMA8
DMAnSCNTL_DMA8
DMAnDSAH_DMA8
DMAnDSAL_DMA8
DMAnDSZH_DMA8
DMAnDSZL_DMA8
DMAnDPTRH_DMA8
DMAnDPTRL_DMA8
DMAnDCNTH_DMA8
DMAnDCNTL_DMA8
DMAnBUF_DMA8
DMAnSIRQ_DMA7
419Fh
419Eh
419Dh
419Ch
419Bh
419Ah
4199h
4198h
4197h
4196h
4195h
4194h
4193h
4192h
4191h
4190h
418Fh
418Eh
418Dh
418Ch
418Bh
418Ah
4189h
4188h
4187h
4186h
4185h
4184h
4183h
4182h
4181h
4180h
DMAnAIRQ_DMA7
DMAnCON1_DMA7
DMAnCON0_DMA7
DMAnSSAU_DMA7
DMAnSSAH_DMA7
DMAnSSAL_DMA7
DMAnSSZH_DMA7
DMAnSSZL_DMA7
DMAnSPTRU_DMA7
DMAnSPTRH_DMA7
DMAnSPTRL_DMA7
DMAnSCNTH_DMA7
DMAnSCNTL_DMA7
DMAnDSAH_DMA7
DMAnDSAL_DMA7
DMAnDSZH_DMA7
DMAnDSZL_DMA7
DMAnDPTRH_DMA7
DMAnDPTRL_DMA7
DMAnDCNTH_DMA7
DMAnDCNTL_DMA7
DMAnBUF_DMA7
DMAnSIRQ_DMA6
DMAnAIRQ_DMA6
DMAnCON1_DMA6
DMAnCON0_DMA6
DMAnSSAU_DMA6
DMAnSSAH_DMA6
DMAnSSAL_DMA6
DMAnSSZH_DMA6
DMAnSSZL_DMA6
DMAnSPTRU_DMA6
417Fh
417Eh
417Dh
417Ch
417Bh
417Ah
4179h
4178h
4177h
4176h
4175h
4174h
4173h
4172h
4171h
4170h
416Fh
416Eh
416Dh
416Ch
416Bh
416Ah
4169h
4168h
4167h
4166h
4165h
4164h
4163h
4162h
4161h
4160h
DMAnSPTRH_DMA6
DMAnSPTRL_DMA6
DMAnSCNTH_DMA6
DMAnSCNTL_DMA6
DMAnDSAH_DMA6
DMAnDSAL_DMA6
DMAnDSZH_DMA6
DMAnDSZL_DMA6
DMAnDPTRH_DMA6
DMAnDPTRL_DMA6
DMAnDCNTH_DMA6
DMAnDCNTL_DMA6
DMAnBUF_DMA6
DMAnSIRQ_DMA5
DMAnAIRQ_DMA5
DMAnCON1_DMA5
DMAnCON0_DMA5
DMAnSSAU_DMA5
DMAnSSAH_DMA5
DMAnSSAL_DMA5
DMAnSSZH_DMA5
DMAnSSZL_DMA5
DMAnSPTRU_DMA5
DMAnSPTRH_DMA5
DMAnSPTRL_DMA5
DMAnSCNTH_DMA5
DMAnSCNTL_DMA5
DMAnDSAH_DMA5
DMAnDSAL_DMA5
DMAnDSZH_DMA5
DMAnDSZL_DMA5
DMAnDPTRH_DMA5
415Fh
415Eh
415Dh
415Ch
415Bh
415Ah
4159h
4158h
4157h
4156h
4155h
4154h
4153h
4152h
4151h
4150h
414Fh
414Eh
414Dh
414Ch
414Bh
414Ah
4149h
4148h
4147h
4146h
4145h
4144h
4143h
4142h
4141h
4140h
DMAnDPTRL_DMA5
DMAnDCNTH_DMA5
DMAnDCNTL_DMA5
DMAnBUF_DMA5
DMAnSIRQ_DMA4
DMAnAIRQ_DMA4
DMAnCON1_DMA4
DMAnCON0_DMA4
DMAnSSAU_DMA4
DMAnSSAH_DMA4
DMAnSSAL_DMA4
DMAnSSZH_DMA4
DMAnSSZL_DMA4
DMAnSPTRU_DMA4
DMAnSPTRH_DMA4
DMAnSPTRL_DMA4
DMAnSCNTH_DMA4
DMAnSCNTL_DMA4
DMAnDSAH_DMA4
DMAnDSAL_DMA4
DMAnDSZH_DMA4
DMAnDSZL_DMA4
DMAnDPTRH_DMA4
DMAnDPTRL_DMA4
DMAnDCNTH_DMA4
DMAnDCNTL_DMA4
DMAnBUF_DMA4
DMAnSIRQ_DMA3
DMAnAIRQ_DMA3
DMAnCON1_DMA3
DMAnCON0_DMA3
DMAnSSAU_DMA3
403Fh
403Eh
403Dh
403Ch
403Bh
403Ah
4039h
4038h
4037h
4036h
4035h
4034h
4033h
4032h
4031h
4030h
402Fh
402Eh
402Dh
402Ch
402Bh
402Ah
4029h
4028h
4027h
4026h
4025h
4024h
4023h
4022h
4021h
4020h
413Fh
413Eh
413Dh
413Ch
413Bh
413Ah
4139h
4138h
4137h
4136h
4135h
4134h
4133h
4132h
4131h
4130h
412Fh
412Eh
412Dh
412Ch
412Bh
412Ah
4129h
4128h
4127h
4126h
4125h
4124h
4123h
4122h
4121h
4120h
PWM4PRH_M1
PWM4PRL_M1
PWM4S1P2H_M2
PWM4S1P2L_M2
PWM4S1P1H_M3
PWM4S1P1L_M3
PWM3PRH_M1
PWM3PRL_M1
PWM3S1P2H_M2
PWM3S1P2L_M2
PWM3S1P1H_M3
PWM3S1P1L_M3
PWM2PRH_M1
PWM2PRL_M1
PWM2S1P2H_M2
PWM2S1P2L_M2
PWM2S1P1H_M3
PWM2S1P1L_M3
PWM1PRH_M1
PWM1PRL_M1
PWM1S1P2H_M2
PWM1S1P2L_M2
PWM1S1P1H_M3
PWM1S1P1L_M3
DMAnSSAH_DMA3
DMAnSSAL_DMA3
DMAnSSZH_DMA3
DMAnSSZL_DMA3
DMAnSPTRU_DMA3
DMAnSPTRH_DMA3
DMAnSPTRL_DMA3
DMAnSCNTH_DMA3
DMAnSCNTL_DMA3
DMAnDSAH_DMA3
DMAnDSAL_DMA3
DMAnDSZH_DMA3
DMAnDSZL_DMA3
DMAnDPTRH_DMA3
DMAnDPTRL_DMA3
DMAnDCNTH_DMA3
DMAnDCNTL_DMA3
DMAnBUF_DMA3
DMAnSIRQ_DMA2
DMAnAIRQ_DMA2
DMAnCON1_DMA2
DMAnCON0_DMA2
DMAnSSAU_DMA2
DMAnSSAH_DMA2
DMAnSSAL_DMA2
DMAnSSZH_DMA2
DMAnSSZL_DMA2
DMAnSPTRU_DMA2
DMAnSPTRH_DMA2
DMAnSPTRL_DMA2
DMAnSCNTH_DMA2
DMAnSCNTL_DMA2
401Fh
401Eh
401Dh
401Ch
401Bh
401Ah
4019h
4018h
4017h
4016h
4015h
4014h
4013h
4012h
4011h
4010h
400Fh
400Eh
400Dh
400Ch
400Bh
400Ah
4009h
4008h
4007h
4006h
4005h
4004h
4003h
4002h
4001h
4000h
411Fh
411Eh
411Dh
411Ch
411Bh
411Ah
4119h
4118h
4117h
4116h
4115h
4114h
4113h
4112h
4111h
4110h
410Fh
410Eh
410Dh
410Ch
410Bh
410Ah
4109h
4108h
4107h
4106h
4105h
4104h
4103h
4102h
4101h
4100h
PWM4S1P2H_M1
PWM4S1P2L_M1
PWM4S1P1H_M2
PWM4S1P1L_M2
PWM3S1P2H_M1
PWM3S1P2L_M1
PWM3S1P1H_M2
PWM3S1P1L_M2
PWM2S1P2H_M1
PWM2S1P2L_M1
PWM2S1P1H_M2
PWM2S1P1L_M2
PWM1S1P2H_M1
PWM1S1P2L_M1
PWM1S1P1H_M2
PWM1S1P1L_M2
PWM4S1P1H_M1
PWM4S1P1L_M1
PWM3S1P1H_M1
PWM3S1P1L_M1
PWM2S1P1H_M1
PWM2S1P1L_M1
PWM1S1P1H_M1
PWM1S1P1L_M1
CCPR3H_M1
CCPR3L_M1
CCPR2H_M1
CCPR2L_M1
CCPR1H_M1
CCPR1L_M1
DMAnDSAH_DMA2
DMAnDSAL_DMA2
DMAnDSZH_DMA2
DMAnDSZL_DMA2
DMAnDPTRH_DMA2
DMAnDPTRL_DMA2
DMAnDCNTH_DMA2
DMAnDCNTL_DMA2
DMAnBUF_DMA2
DMAnSIRQ_DMA1
DMAnAIRQ_DMA1
DMAnCON1_DMA1
DMAnCON0_DMA1
DMAnSSAU_DMA1
DMAnSSAH_DMA1
DMAnSSAL_DMA1
DMAnSSZH_DMA1
DMAnSSZL_DMA1
DMAnSPTRU_DMA1
DMAnSPTRH_DMA1
DMAnSPTRL_DMA1
DMAnSCNTH_DMA1
DMAnSCNTL_DMA1
DMAnDSAH_DMA1
DMAnDSAL_DMA1
DMAnDSZH_DMA1
DMAnDSZL_DMA1
DMAnDPTRH_DMA1
DMAnDPTRL_DMA1
DMAnDCNTH_DMA1
DMAnDCNTL_DMA1
DMAnBUF_DMA1
DMA Addressing
The start addresses for the source read and destination write operations are set using the DMAnSSA and DMAnDSA
registers, respectively.
When the DMA message transfers are in progress, the DMAnSPTR and DMAnDPTR registers contain the current
Address Pointers for each source read and destination write operation. These registers are modified after each
transaction based on the Address mode selection bits.
The SMODE and DMODE bits determine the address modes of operation by controlling how the DMAnSPTR and
DMAnDPTR registers are updated after every DMA data transaction (Figure 16-3).
Each address can be separately configured to:
• Remain unchanged
• Increment by 1
• Decrement by 1
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 283
PIC18F27/47/57Q84
DMA - Direct Memory Access
Figure 16-3. DMA Pointers Block Diagram
DMAnSSA
DMAnDSA
DMAnSPTR
DMAnDPTR
+1
0
-1
+1
0
-1
SMODE
DMODE
The DMA can initiate data transfers from the PFM, Data EEPROM or SFR/GPR space. The SMR bits are used to
select the type of memory being pointed to by the Source Address Pointer. The SMR bits are required because the
PFM and SFR/GPR spaces have overlapping addresses that do not allow the specified address to uniquely define
the memory location to be accessed.
Important:
1. For proper memory read access to occur, the combination of address and space selection must be
valid.
2. The destination does not have space selection bits because it can only write to the SFR/GPR
space.
16.3.3
DMA Message Size/Counters
A transaction is the transfer of one byte. A message consists of one or more transactions. A complete DMA process
consists of one or more messages. The size registers determine how many transactions are in a message. The
DMAnSSZ registers determine the source size and DMAnDSZ registers determine the destination size.
When a DMA transfer is initiated, the size registers are copied to corresponding counter registers that control the
duration of the message. The DMAnSCNT registers count the source transactions and the DMAnDCNT registers
count the destination transactions. Both are simultaneously decremented by one after each transaction.
A message is started by setting the DGO bit and terminates when the smaller of the two counters reaches zero.
When either counter reaches zero, the DGO bit is cleared and the counter and pointer registers are immediately
reloaded with the corresponding size and address data. If the other counter did not reach zero, then the next
message will continue with the count and address corresponding to that register. Refer to Figure 16-4.
When the Source and Destination Size registers are not equal, then the ratio of the largest to the smallest size
determines how many messages are in the DMA process. For example, when the destination size is six and the
source size is two, then each message will consist of two transactions and the complete DMA process will consist of
three messages. When the larger size is not an even integer of the smaller size, then the last message in the process
will terminate early when the larger count reaches zero. In that case, the larger counter will reset and the smaller
counter will have a remainder skewing any subsequent messages by that amount.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 284
PIC18F27/47/57Q84
DMA - Direct Memory Access
Table 16-2 has a few examples of configuring DMA Message sizes.
Important: Reading the DMAnSCNT or DMAnDCNT registers will never return zero. When either register
is decremented from ‘1’, it is immediately reloaded from the corresponding size register.
Table 16-2. Example Message Size
Operation
Example
SCNT
DCNT
Comments
Read from single
SFR location to RAM
UART Receive Buffer
1
N
N equals the number
of bytes desired in
the destination buffer.
N≥1.
Write to single SFR
location from RAM
UART Transmit
Buffer
N
1
N equals the number
of bytes desired in
the source buffer.
N≥1.
Read from multiple
SFR location
ADC Result registers
2
2*N
N equals the number
of ADC results to
be stored in memory.
N≥1
PWM Duty Cycle
registers
2*N
2
N equals the number
of PWM duty cycle
values to be loaded
from a memory table.
N≥1
Write to Multiple SFR
registers
Figure 16-4. DMA Counters Block Diagram
DMAnSSZ
DMAnDSZ
DMAnSCNT
DMAnDCNT
1
16.3.4
1
DMA Message Transfers
Once the Enable bit is set to start DMA message transfers, the Source/Destination Pointer and Counter registers are
initialized to the conditions shown in the table below.
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Table 16-3. DMA Initial Conditions
Register
Value Loaded
DMAnSPTR
DMAnSSA
DMAnSCNT
DMAnSSZ
DMAnDPTR
DMAnDSA
DMAnDCNT
DMAnDSZ
During the DMA operation after each transaction, Table 16-4 and Table 16-5 indicate how the Source/Destination
Pointer and Counter registers are modified.
The following sections discuss how to initiate and terminate DMA transfers.
Table 16-4. DMA Source Pointer/Counter During Operation
Register
Modified Source Counter/Pointer Value
DMAnSCNT = DMAnSCNT -1
DMAnSCNT != 1
SMODE = 00: DMAnSPTR = DMAnSPTR
SMODE = 01: DMAnSPTR = DMAnSPTR + 1
SMODE = 10: DMAnSPTR = DMAnSPTR - 1
DMAnSCNT = DMAnSSZ
DMAnSCNT == 1
DMAnSPTR = DMAnSSA
Table 16-5. DMA Destination Pointer/Counter During Operation
Register
Modified Destination Counter/Pointer Value
DMAnDCNT = DMAnDCNT -1
DMAnDCNT != 1
DMODE = 00: DMAnDPTR = DMAnDPTR
DMODE = 01: DMAnDPTR = DMAnDPTR + 1
DMODE = 10: DMAnDPTR = DMAnDPTR - 1
DMAnDCNT = DMAnDSZ
DMAnDCNT == 1
DMAnDPTR = DMAnDSA
16.3.4.1 Starting DMA Message Transfers
The DMA can initiate data transactions by either of the following two conditions:
• User software control
• Hardware trigger, SIRQ
16.3.4.1.1 User Software Control
Software starts or stops DMA transaction by setting/clearing the DGO bit. The DGO bit is also used to indicate
whether a DMA hardware trigger has been received and a message is in progress.
Important:
1. Software start can only occur when the EN bit is set.
2. If the CPU writes to the DGO bit while it is already set, there is no effect on the system, the DMA will
continue to operate normally.
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DMA - Direct Memory Access
16.3.4.1.2 Hardware Trigger, SIRQ
A hardware trigger is an interrupt request from another module sent to the DMA with the purpose of starting a DMA
message. The DMA start trigger source is user-selectable using the DMAnSIRQ register.
The SIRQEN bit is used to enable sampling of external interrupt triggers by which a DMA transfer can be started.
When set, the DMA will sample the selected interrupt source and when cleared, the DMA will ignore the interrupt
source. Clearing the SIRQEN bit does not stop a DMA transaction currently in progress, it only stops more hardware
request signals from being received.
16.3.4.2 Stopping DMA Message Transfers
The DMA controller can stop data transactions by any of the following conditions:
•
•
•
•
•
Clearing the DGO bit
Hardware abort trigger, AIRQ
Source count reload
Destination count reload
Clearing the EN bit
16.3.4.2.1 User Software Control
If the user clears the DGO bit, the message will be stopped and the DMA will remain in the current configuration.
For example, if the user clears the DGO bit after source data has been read, but before it is written to the destination,
then the data in the DMAnBUF register will not reach its destination.
This is also referred to as a soft-stop as the operation can resume, if desired, by setting the DGO bit again.
16.3.4.2.2 Hardware Trigger, AIRQ
The AIRQEN bit is used to enable sampling of external interrupt triggers by which a DMA transaction can be aborted.
Once an abort interrupt request has been received, the DMA will perform a soft-stop by clearing the DGO bit, as well
as clearing the SIRQEN bit so overruns do not occur. The AIRQEN bit is also cleared to prevent additional abort
signals from triggering false aborts.
If desired, the DGO bit can be set again and the DMA will resume operation from where it left off after the soft stop
had occurred, as none of the DMA state information is changed in the event of an abort.
16.3.4.2.3 Source Count Reload
A DMA message is considered to be complete when the Source Count register is decremented from 1 and then
reloaded (i.e., once the last byte from either the source read or destination write has occurred). When the SSTP bit is
set and the Source Count register is reloaded, then further message transfer is stopped.
16.3.4.2.4 Destination Count Reload
A DMA message is considered to be complete when the Destination Count register is decremented from 1 and then
reloaded (i.e., once the last byte from either the source read or destination write has occurred). When the DSTP bit is
set and the Destination Count register is reloaded then further message transfer is stopped.
Important: Reading the DMAnSCNT or DMAnDCNT registers will never return zero. When either register
is decremented from ‘1’, it is immediately reloaded from the corresponding size register.
16.3.4.2.5 Clearing the EN bit
If the user clears the EN bit, the message will be stopped and the DMA will return to its default configuration. This is
also referred to as a hard stop, as the DMA cannot resume operation from where it was stopped.
Important: After the DMA message transfer is stopped, it requires an extra instruction cycle before the
Stop condition takes effect. Thus, after the Stop condition has occurred, a source read or a destination
write can occur depending on the source or destination bus availability.
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DMA - Direct Memory Access
16.4
Disable DMA Message Transfer Upon Completion
Once the DMA message is complete, it may be desirable to disable the trigger source to prevent overrun or under run
of data. This can be done by any of the following methods:
• Clearing the SIRQEN bit
• Setting the SSTP bit
• Setting the DSTP bit
16.4.1
Clearing the SIRQEN bit
Clearing the SIRQEN bit stops the sampling of external start interrupt triggers, hence preventing further DMA
message transfers.
An example would be a communications peripheral with a level-triggered interrupt. The peripheral will continue to
request data (because its buffer is empty) even though there is no more data to be moved. Disabling the SIRQEN bit
prevents the DMA from processing these requests.
16.4.2
Source/Destination Stop
The SSTP and DSTP bits determine whether or not to disable the hardware triggers (SIRQEN = 0), once a DMA
message has completed.
When the SSTP bit is set and the DMAnSCNT = 0, then the SIRQEN bit will be cleared. Similarly, when the DSTP bit
is set and the DMAnDCNT = 0, the SIRQEN bit will be cleared.
Important: The SSTP and DSTP bits are independent functions and do not depend on each other. It is
possible for a message to be stopped by either counter at message end or both counters at message end.
16.5
Types of Hardware Triggers
The DMA has two different trigger inputs, the source trigger and the abort trigger. Each of these trigger sources is
user configurable using the DMAnSIRQ and DMAnAIRQ registers.
Based on the source selected for each trigger, there are two types of requests that can be sent to the DMA:
• Edge triggers
• Level triggers
16.5.1
Edge Trigger Requests
An edge request occurs only once when a given module interrupt requirements are true. Examples of edge triggers
are the ADC conversion complete and the interrupt-on-change interrupts.
16.5.2
Level Trigger Requests
A level request is asserted as long as the condition that causes the interrupt is true. Examples of level triggers are the
UART receive and transmit interrupts.
16.6
Types of Data Transfers
Based on the memory access capabilities of the DMA (see Table 16-1), the following sections discuss the different
types of data movement between the source and destination memory regions.
•
•
N:1
This type of transfer is common when sending predefined data packets (such as strings) through a single
interface point (such as communications modules transmit registers).
N:N
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•
•
16.7
This type of transfer is useful for moving information out of the program Flash or Data EEPROM to SRAM for
manipulation by the CPU or other peripherals.
1:1
This type of transfer is common when bridging two different modules data streams together (communications
bridge).
1:N
This type of transfer is useful for moving information from a single data source into a memory buffer
(communications receive registers).
DMA Interrupts
Each DMA has its own set of four interrupt flags, used to indicate a range of conditions during data transfers. The
interrupt flag bits can be accessed using the corresponding PIR registers (refer to the “VIC - Vectored Interrupt
Controller” chapter).
16.7.1
DMA Source Count Interrupt
The Source Count Interrupt Flag (DMAxSCNTIF) is set every time the DMAnSCNT register reaches zero and is
reloaded to its starting value.
16.7.2
DMA Destination Count Interrupt
The Destination Count Interrupt Flag (DMAxDCNTIF) is set every time the DMAnDCNT register reaches zero and is
reloaded to its starting value.
The DMA source and destination count interrupts signal the CPU when the DMA messages are completed.
16.7.3
Abort Interrupt
The Abort Interrupt Flag (DMAxAIF) is used to signal that the DMA has halted activity due to an abort signal from one
of the abort sources. This is used to indicate that the transaction has been halted by a hardware event.
16.7.4
Overrun Interrupt
When the DMA receives a trigger to start a new message before the current message is completed, then the Overrun
Interrupt Flag (DMAxORIF) bit is set.
This condition indicates that the DMA is being requested before its current transaction is finished. This implies that
the active DMA may not be able to keep up with the demands from the peripheral module being serviced, which may
result in data loss.
The DMAxORIF flag being set does not cause the current DMA transfer to terminate.
The overrun interrupt is only available for trigger sources that are edge-based and not available for sources that
are level-based. Therefore, a level-based interrupt source does not trigger a DMA overrun error due to the potential
latency issues in the system.
An example of an interrupt that can use the overrun interrupt is a timer overflow (or period match) interrupt. This
event only happens every time the timer rolls over and is not dependent on any other system conditions.
An example of an interrupt that does not allow the overrun interrupt is the UART TX buffer. The UART will continue to
assert the interrupt until the DMA is able to process the message. Due to latency issues, the DMA may not be able
to service an empty buffer immediately, but the UART continues to assert its transmit interrupt until it is serviced. If
overrun was allowed in this case, the overrun would occur almost immediately as the module samples the interrupt
sources every instruction cycle.
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DMA - Direct Memory Access
16.8
DMA Setup and Operation
The following steps illustrate how to configure the DMA for data transfer:
1.
2.
Select the desired DMA using the DMASELECT register.
Program the appropriate source and destination addresses for the transaction into the DMAnSSA and
DMAnDSA registers.
3. Select the source memory region that is being addressed by the DMAnSSA register, using the SMR bits.
4. Program the SMODE and DMODE bits to select the addressing mode.
5. Program the source size (DMAnSSZ) and destination size (DMAnDSZ) registers with the number of bytes to
be transferred. It is recommended for proper operation that the size registers be a multiple of each other.
6. If the user desires to disable data transfers once the message has completed, then the SSTP and DSTP bits
need to be set. (See Source/Destination Stop).
7. If using hardware triggers for data transfer, set up the hardware trigger interrupt sources for the starting and
aborting DMA transfers (DMAnSIRQ and DMAnAIRQ), and set the corresponding Interrupt Request Enable
bits (SIRQEN and AIRQEN).
8. Select the priority level for the DMA (see “System Arbitration” section in the “PIC18 CPU” chapter) and lock
the priorities (see the “Priority Lock” section in the “PIC18 CPU” chapter).
9. Enable the DMA by setting the EN bit.
10. If using software control for data transfer, set the DGO bit, else this bit will be set by the hardware trigger.
Once the DMA is set up, Figure 16-5 describes the sequence of operation when the DMA uses hardware triggers and
utilizes the unused CPU cycles (bubble) for DMA transfers.
The following sections describe with visual reference the sequence of events for different configurations of the DMA
module.
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Figure 16-5. DMA Operation with Hardware Trigger
Configure DMA
Module
EN = 1
DMA Source/
Destination Pointers/
Counters are loaded
N
SIRQEN = 1 &
Trigger?
Y
DGO = 1
Y
N
Bubble?
Y
DMAnBUF = &DMAnSPTR
XIP = 1
Source Read
N
Bubble?
Y
&DMAnDPTR = DMABUF
XIP = 0
Destination Write
Y
DMAnSCNT = 0
Reload
DMAnSCNT &
DMAnSPTR
DMAxSCNTIF
=1
DGO = 0
N
Update
DMAnSSA,
DMAnSCNT
SIRQEN = 0
Y
SSTP = 1
N
DMAnDCNT = 0
Y
Reload
DMAnDCNT &
DMAnDPTR
DMAnDCNTIF
=1
DGO = 0
N
Update
DMAnDSA,
DMAnDCNT
AIRQEN = 0
Y
DSTP = 1
N
N
DGO = 0
Y
End Process
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DMA - Direct Memory Access
16.8.1
Source Stop
When the Source Stop bit is set (SSTP = 1) and the DMAnSCNT register reloads, the DMA clears the SIRQEN bit to
stop receiving new start interrupt request signals and sets the DMAnSCNTIF flag. Refer to the figure below for more
details.
Figure 16-6. GPR-GPR Transactions with Hardware Triggers, SSTP = 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Instruction
Clock
EN
SIRQEN
Source Hardware
Trigger
DGO
DMAnSPTR
0x100
0x101
0x102
0x103
0x100
DMAnDPTR
0x200
0x201
0x200
0x201
0x200
DMAnSCNT
4
3
2
1
4
DMAnDCNT
2
1
2
1
2
DMA STATE
SR(1) DW(2) SR(1) DW(2)
IDLE
IDLE
SR(1) DW(2) SR(1) DW(2)
IDLE
DMAxSCNTIF
DMAxDCNTIF
DMAnSSA
0x100
DMAnDSA
0x200
DMAnSSZ
0x4
DMAnDSZ
0x2
Notes:
1. SR - Source Read
2. DW - Destination Write
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DMA - Direct Memory Access
16.8.2
Destination Stop
When the Destination Stop bit is set (DSTP = 1) and the DMAnDCNT register reloads, the DMA clears the SIRQEN
bit to stop receiving new start interrupt request signals and sets the DMAxDCNTIF flag.
Figure 16-7. GPR-GPR Transactions with Hardware Triggers, DSTP = 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Instruction
Clock
EN
SIRQEN
Source Hardware
Trigger
DGO
DMAnSPTR
0x100
0x101
0x100
0x101
0x100
DMAnDPTR
0x200
0x201
0x202
0x203
0x200
DMAnSCNT
2
1
2
1
2
DMAnDCNT
4
3
2
1
4
DMA STATE
SR(1) DW(2) SR(1) DW(2)
IDLE
IDLE
SR(1) DW(2) SR(1) DW(2)
IDLE
DMAxSCNTIF
DMAxDCNTIF
DMAnSSA
0x100
DMAnDSA
0x200
DMAnSSZ
0x2
DMAnDSZ
0x4
Notes:
1. SR - Source Read
2. DW - Destination Write
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DMA - Direct Memory Access
16.8.3
Continuous Transfer
When the Source or the Destination Stop bit is cleared (SSTP, DSTP = 0), the transactions continue unless stopped
by the user. The DMAxSCNTIF and DMAxDCNTIF flags are set whenever the respective counter registers are
reloaded.
Figure 16-8. GPR-GPR Transactions with Hardware Triggers, SSTP, DSTP = 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
31
30
32
Instruction
Clock
EN
SIRQEN
Source
Hardware
Trigger
DGO
DMAnSPTR
0x100
0x101
0x100
0x101
0x100
0x101
0x100
0x101
0x100
DMAnDPTR
0x200
0x201
0x202
0x203
0x200
0x201
0x202
0x203
0x202
DMAnSCNT
2
1
2
1
2
1
2
1
2
DMAnDCNT
4
3
2
1
4
3
2
1
2
DMA
STATE
IDLE
SR(1)DW(2) SR(1) DW(2)
IDLE
SR(1) DW(2) SR(1) DW(2)
IDLE
SR(1) DW(2) SR(1) DW(2)
IDLE
SR(1) DW(2) SR(1) DW(2)
IDLE
DMAxSCNTIF
DMAxDCNTIF
DMAnSSA
0x100
DMAnDSA
0x200
DMAnSSZ
0x2
DMAnDSZ
0x4
Notes:
1. SR - Source Read
2. DW - Destination Write
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DMA - Direct Memory Access
16.8.4
Transfer from SFR to GPR
The following visual reference describes the sequence of events when copying ADC results to a GPR location. The
ADC Interrupt flag can be chosen as the source hardware trigger, the source address can be set to point to the ADC
Result registers (e.g., at 0x3EEF), the destination address can be set to point to any GPR location of our choice (e.g.,
at 0x100).
Figure 16-9. SFR Space to GPR Space Transfer
1
2
3
4
5
6
7
8
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+x
Instruction
Clock
EN
SIRQEN
Source Hardware
Trigger
DGO
DMAnSPTR
0x3EEF
0x3EF0
0x3EEF
0x3EF0
0x3EEF
DMAnDPTR
0x100
0x101
0x102
0x103
0x103
DMAnSCNT
2
1
2
1
2
DMAnDCNT
10
9
8
7
6
DMA STATE
SR(1) DW(2) SR(1) DW(2)
IDLE
IDLE
SR(1) DW(2) SR(1) DW(2)
IDLE
DMAxSCNTIF
DMAxDCNTIF
DMAnSSA
0x3EEF
DMAnDSA
0x100
DMAnSSZ
0x2
DMAnDSZ
0xA
SMODE
0x1
DMODE
0x1
Notes:
1. SR - Source Read
2. DW - Destination Write
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DMA - Direct Memory Access
16.8.5
Overrun Condition
The Overrun Interrupt flag is set if the DMA receives a trigger to start a new message before the current message is
completed.
Figure 16-10. Overrun Interrupt
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Instruction
Clock
EN
SIRQEN
Source Hardware
Trigger
DGO
DMAnSPTR
0x100
0x101
0x100
0x101
0x100
DMAnDPTR
0x200
0x201
0x202
0x203
0x200
DMAnSCNT
2
1
2
1
2
DMAnDCNT
4
3
2
1
4
DMA STATE
SR(1) DW(2) SR(1) DW(2)
IDLE
IDLE
SR(1) DW(2) SR(1) DW(2)
IDLE
DMAxSCNTIF
DMAxDCNTIF
DMAxORIF
DMAnCON1bits.SMA = 01
DMAnSSA
0x100
DMAnDSA
0x200
DMAnSSZ
0x2
DMAnDSZ
0x20
Notes:
1. SR - Source Read
2. DW - Destination Write
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DMA - Direct Memory Access
16.8.6
Abort Trigger, Message Complete
The AIRQEN needs to be set in order for the DMA to sample abort interrupt sources. When an abort interrupt is
received, the SIRQEN bit is cleared and the AIRQEN bit is cleared to avoid receiving further abort triggers.
Figure 16-11. Abort at the End of Message
1
2
3
4
5
6
7
8
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
Instruction
Clock
EN
SIRQEN
AIRQEN
Source Hardware
Trigger
Abort Hardware
Trigger
DGO
DMAnSPTR
0x3EEF
0x3EF0
0x3EEF
0x3EF0
0x3EEF
DMAnDPTR
0x100
0x101
0x109
0x10A
0x100
DMAnSCNT
2
1
2
1
2
DMAnDCNT
10
9
2
1
10
DMA STATE
SR(1) DW(2) SR(1) DW(2)
IDLE
IDLE
SR(1) DW(2) SR(1) DW(2)
IDLE
DMAxSCNTIF
DMAxDCNTIF
DMAxAIF
DMAnSSA
0x3EEF
DMAnDSA
0x100
DMAnSSZ
0x2
DMAnDSZ
0xA
Notes:
1. SR - Source Read
2. DW - Destination Write
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DMA - Direct Memory Access
16.8.7
Abort Trigger, Message in Progress
When an abort interrupt request is received in a DMA transaction, the DMA will perform a soft-stop by clearing the
DGO bit (i.e., if the DMA was reading the source register, it will complete the read operation and then clear the DGO
bit).
The SIRQEN bit is cleared to prevent any overrun and the AIRQEN bit is cleared to prevent any false aborts. When
the DGO bit is set again, the DMA will resume operation from where it left off after the soft-stop.
Figure 16-12. Abort During Message Transfer
1
2
3
4
5
6
7
8
9
10
11
10
12
Instruction
Clock
EN
SIRQEN
AIRQEN
Source Hardware
Trigger
Abort Hardware
Trigger
DGO
DMAnSPTR
0x3EEF
0x3EF0
0x3EEF
DMAnDPTR
0x100
0x101
0x102
DMAnSCNT
2
1
2
DMAnDCNT
10
9
8
IDLE
DMA STATE
SR(1)
IDLE
DW(2)
SR(1)
DW(2)
IDLE
DMAnCONbits.XIP
DMAxAIF
DMAnSSA
0x3EEF
DMAnDSA
0x100
DMAnSSZ
0x2
DMAnDSZ
0xA
Notes:
1. SR - Source Read
2. DW - Destination Write
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DMA - Direct Memory Access
16.9
Reset
The DMA registers are set to the default state on any Reset. The registers are also reset to the default state when the
enable bit is cleared (EN = 0). User firmware needs to setup all the registers to resume DMA operation.
16.10
Power-Saving Mode Operation
The DMA utilizes system clocks and it is treated as a peripheral when it comes to power-saving operations. Like
other peripherals, the DMA also uses Peripheral Module Disable bits to further tailor its operation in low-power states.
16.10.1 Sleep Mode
When the device enters Sleep mode, the system clock to the module is shut down, therefore no DMA operation is
supported in Sleep. Once the system clock is disabled, the requisite read and write clocks are also disabled, without
which the DMA cannot perform any of its tasks.
Any transfers that may be in progress are resumed on exiting from Sleep mode. Register contents are not affected
by the device entering or leaving Sleep mode. It is recommended that DMA transactions be allowed to finish before
entering Sleep mode.
16.10.2 Idle Mode
In Idle mode, all of the system clocks (including the read and write clocks) are still operating, but the CPU is not using
them to save power.
Therefore, every instruction cycle is available to the system arbiter and if the bubble is granted to the DMA, it may be
utilized to move data.
16.10.3 Doze Mode
Similar to the Idle mode, the CPU does not utilize all of the available instruction cycles slots that are available to it in
order to save power. It only executes instructions based on its Doze mode settings.
Therefore, every instruction not used by the CPU is available for system arbitration and may be utilized by the DMA,
if granted by the arbiter.
16.10.4 Peripheral Module Disable
The Peripheral Module Disable (PMD) registers provide a method to disable DMA by gating all clock sources
supplied to it. The respective DMAxMD bit needs to be set in order to disable the DMA.
16.11
Example Setup Code
This code example illustrates using DMA1 to transfer 10 bytes of data from 0x1000 in Flash memory to the UART
transmit buffer.
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Preliminary Datasheet
DS40002213D-page 299
PIC18F27/47/57Q84
DMA - Direct Memory Access
void initializeDMA(){
//Select DMA1 by setting DMASELECT register to 0x00
DMASELECT = 0x00;
//DMAnCON1 - DPTR remains, Source Memory Region PFM, SPTR increments,
SSTP
DMAnCON1 = 0x0B;
//Source registers
//Source size
DMAnSSZH = 0x00;
DMAnSSZL = 0x0A;
//Source start address, 0x1000
DMAnSSAU = 0x00;
DMAnSSAH = 0x10;
DMAnSSAL = 0x00;
//Destination registers
//Destination size
DMAnDSZH = 0x00;
DMAnDSZL = 0x01;
//Destination start address,
DMAnDSA = &U1TXB;
//Start trigger source U1TX. Refer the datasheet for the correct code
DMAnSIRQ = 0xnn;
//Change arbiter priority if needed and perform lock operation
DMA1PR = 0x01;
// Change the priority only if needed
PRLOCK = 0x55;
// This sequence
PRLOCK = 0xAA;
// is mandatory
PRLOCKbits.PRLOCKED = 1; // for DMA operation
//Enable the DMA & the trigger to start DMA transfer
DMAnCON0 = 0xC0;
}
16.12
Register Overlay
All DMA instances in this device share the same set of registers. Only one DMA instance is accessible at a time. The
value in the DMASELECT register is one less than the selected DMA instance. For example, a DMASELECT value of
‘0’ selects DMA1.
16.13
Register Definitions: DMA
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
DMA - Direct Memory Access
16.13.1 DMASELECT
Name:
Address:
DMASELECT
0x0E8
DMA Instance Selection Register
Selects which DMA instance is accessed by the DMA registers
Bit
7
6
5
4
3
Access
Reset
2
R/W
0
1
SLCT[2:0]
R/W
0
0
R/W
0
Bits 2:0 – SLCT[2:0] DMA Instance Selection
Value
Description
n
Shared DMA registers of instance n+1 are selected for read and write operations
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DMA - Direct Memory Access
16.13.2 DMAnCON0
Name:
Address:
DMAnCON0
0x0FC
DMA Control Register 0
Bit
Access
Reset
7
EN
R/W
0
6
SIRQEN
R/W/HC
0
5
DGO
R/W/HS/HC
0
4
3
2
AIRQEN
R/W/HC
0
1
0
XIP
R/HS/HC
0
Bit 7 – EN DMA Module Enable
Value
Description
1
Enables module
0
Disables module
Bit 6 – SIRQEN Start of Transfer Interrupt Request Enable
Value
Description
1
Hardware triggers are allowed to start DMA transfers
0
Hardware triggers are not allowed to start the DMA transfers
Bit 5 – DGO DMA Transaction
Value
Description
1
DMA transaction is in progress
0
DMA transaction is not in progress
Bit 2 – AIRQEN Abort of Transfer Interrupt Request Enable
Value
Description
1
Hardware triggers are allowed to abort DMA transfers
0
Hardware triggers are not allowed to abort the DMA transfers
Bit 0 – XIP Transfer in Progress Status
Value
Description
1
The DMA buffer register currently holds contents from a read operation and has not transferred data to
the destination
0
The DMA buffer register is empty or has successfully transferred data to the destination address
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Preliminary Datasheet
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DMA - Direct Memory Access
16.13.3 DMAnCON1
Name:
Address:
DMAnCON1
0x0FD
DMA Control Register 1
Bit
Access
Reset
7
6
DMODE[1:0]
R/W
R/W
0
0
5
DSTP
R/W
0
4
3
SMR[1:0]
R/W
0
R/W
0
2
1
SMODE[1:0]
R/W
R/W
0
0
0
SSTP
R/W
0
Bits 7:6 – DMODE[1:0] Destination Address Mode Selection
Value
Description
11
Reserved, do not use
10
Destination Pointer (DMADPTR) is decremented after each transfer
01
Destination Pointer (DMADPTR) is incremented after each transfer
00
Destination Pointer (DMADPTR) remains unchanged after each transfer
Bit 5 – DSTP Destination Counter Reload Stop
Value
Description
1
SIRQEN bit is cleared when destination counter reloads
0
SIRQEN bit is not cleared when destination counter reloads
Bits 4:3 – SMR[1:0] Source Memory Region Selection
Value
Description
1x
Data EEPROM is selected as the DMA source memory
01
Program Flash Memory is selected as the DMA source memory
00
SFR/GPR data space is selected as the DMA source memory
Bits 2:1 – SMODE[1:0] Source Address Mode Selection
Value
Description
11
Reserved, do not use
10
Source Pointer (DMASPTR) is decremented after each transfer
01
Source Pointer (DMASPTR) is incremented after each transfer
00
Source Pointer (DMASPTR) remains unchanged after each transfer
Bit 0 – SSTP Source Counter Reload Stop
Value
Description
1
SIRQEN bit is cleared when source counter reloads
0
SIRQEN bit is not cleared when source counter reloads
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DMA - Direct Memory Access
16.13.4 DMAnBUF
Name:
Address:
DMAnBUF
0x0E9
DMA Data Buffer Register
Bit
7
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
BUF[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 7:0 – BUF[7:0] DMA Data Buffer
Description
These bits reflect the content of the internal data buffer the DMA peripheral uses to hold the data being moved from
the source to destination.
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DMA - Direct Memory Access
16.13.5 DMAnSSA
Name:
Address:
DMAnSSA
0x0F9
DMA Source Start Address Register
Bit
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
SSA[21:16]
Access
Reset
Bit
15
14
R/W
0
R/W
0
13
12
SSA[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
SSA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 21:0 – SSA[21:0] Source Start Address
Notes: The individual bytes in this multi-byte register can be accessed with the following register names.
1. DMAnSSAU: Accesses the upper most byte [23:16].
2. DMAnSSAH: Accesses the high byte [15:8].
3. DMAnSSAL: Access the low byte [7:0].
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Preliminary Datasheet
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DMA - Direct Memory Access
16.13.6 DMAnSSZ
Name:
Address:
DMAnSSZ
0x0F7
DMA Source Size Register
Bit
15
14
13
12
11
10
9
8
SSZ[11:8]
Access
Reset
Bit
7
6
5
4
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
SSZ[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 11:0 – SSZ[11:0] Source Message Size
Notes: The individual bytes in this multi-byte register can be accessed with the following register names.
1. DMAnSSZH: Accesses the high byte [15:8].
2. DMAnSSZL: Access the low byte [7:0].
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DMA - Direct Memory Access
16.13.7 DMAnSCNT
Name:
Address:
DMAnSCNT
0x0F2
DMA Source Count Register
Bit
15
14
13
12
11
10
9
8
SCNT[11:8]
Access
Reset
Bit
7
6
5
4
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
SCNT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 11:0 – SCNT[11:0] Current Source Byte Count
Notes: The individual bytes in this multi-byte register can be accessed with the following register names.
1. DMAnSCNTH: Accesses the high byte [15:8].
2. DMAnSCNTL: Access the low byte [7:0].
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DMA - Direct Memory Access
16.13.8 DMAnSPTR
Name:
Address:
DMAnSPTR
0x0F4
DMA Source Pointer Register
Bit
23
22
21
20
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
SPTR[21:16]
Access
Reset
Bit
15
14
R
0
R
0
13
12
SPTR[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
SPTR[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 21:0 – SPTR[21:0] Current Source Address Pointer
Notes: The individual bytes in this multi-byte register can be accessed with the following register names.
1. DMAnSPTRU: Accesses the upper most byte [23:16].
2. DMAnSPTRH: Accesses the high byte [15:8].
3. DMAnSPTRL: Access the low byte [7:0].
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Preliminary Datasheet
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DMA - Direct Memory Access
16.13.9 DMAnDSA
Name:
Address:
DMAnDSA
0x0F0
DMA Destination Start Address Register
Bit
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
DSA[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
DSA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – DSA[15:0] Destination Start Address
Notes: The individual bytes in this multi-byte register can be accessed with the following register names.
1. DMAnDSAH: Accesses the high byte [15:8].
2. DMAnDSAL: Access the low byte [7:0].
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
DMA - Direct Memory Access
16.13.10 DMAnDSZ
Name:
Address:
DMAnDSZ
0x0EE
DMA Destination Size Register
Bit
15
14
13
12
11
10
9
8
DSZ[11:8]
Access
Reset
Bit
7
6
5
4
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
DSZ[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 11:0 – DSZ[11:0] Destination Message Size
Notes: The individual bytes in this multi-byte register can be accessed with the following register names.
1. DMAnDSZH: Accesses the high byte [15:8].
2. DMAnDSZL: Access the low byte [7:0].
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
DMA - Direct Memory Access
16.13.11 DMAnDCNT
Name:
Address:
DMAnDCNT
0x0EA
DMA Destination Count Register
Bit
15
14
13
12
11
10
9
8
DCNT[11:8]
Access
Reset
Bit
7
6
5
4
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
DCNT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 11:0 – DCNT[11:0] Current Destination Byte Count
Notes: The individual bytes in this multi-byte register can be accessed with the following register names.
1. DMAnDCNTH: Accesses the high byte [15:8].
2. DMAnDCNTL: Access the low byte Destination Message Size bits [7:0].
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
DMA - Direct Memory Access
16.13.12 DMAnDPTR
Name:
Address:
DMAnDPTR
0x0EC
DMA Destination Pointer Register
Bit
15
14
13
12
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
DPTR[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
DPTR[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 15:0 – DPTR[15:0] Current Destination Address Pointer
Notes: The individual bytes in this multi-byte register can be accessed with the following register names.
1. DMAnDPTRH: Accesses the high byte [15:8].
2. DMAnDPTRL: Access the low byte [7:0].
© 2021 Microchip Technology Inc.
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DMA - Direct Memory Access
16.13.13 DMAnSIRQ
Name:
Address:
DMAnSIRQ
0x0FF
DMA Start Interrupt Request Source Selection Register
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
SIRQ[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – SIRQ[7:0] DMA Start Interrupt Request Source Selection
Table 16-6. DMAxSIRQ and DMAxAIRQ Interrupt Sources
Vector Number
Interrupt Source
Vector Number
(cont.)
Interrupt Source
(cont.)
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
HLVD (High/Low-Voltage Detect)
OSF (Oscillator Fail)
CSW (Clock Switching)
TU16A
CLC1 (Configurable Logic Cell)
CAN (CAN Error)
IOC (Interrupt On Change)
INT0
ZCD (Zero-Cross Detection)
AD (ADC Conversion Complete)
ACT (Active Clock Tuning)
CM1 (Comparator)
SMT1 (Signal Measurement Timer)
SMT1PRA
SMT1PWA
ADCH0
ADCH1
ADCH2
ADCH3
DMA1SCNT (Direct Memory Access)
DMA1DCNT
DMA1OR
DMA1A
SPI1RX (Serial Peripheral Interface)
SPI1TX
SPI1
TMR2
TMR1
TMR1G
CCP1 (Capture/Compare/PWM)
TMR0
U1RX
0x4C
0x4D
0x4E
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
CLC4
PWM4RINT
PWM4GINT
INT2
CLC5
CWG2 (Complementary Waveform Generator)
NCO2
DMA3SCNT
DMA3DCNT
DMA3OR
DMA3A
CCP3
CLC6
CWG3
TMR4
DMA4SCNT
DMA4DCNT
DMA4OR
DMA4A
U4RX
U4TX
U4E
U4
DMA5SCNT
DMA5DCNT
DMA5OR
DMA5A
U5RX
U5TX
U5E
U5
DMA6SCNT
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DMA - Direct Memory Access
...........continued
Vector Number
Interrupt Source
Vector Number
(cont.)
Interrupt Source
(cont.)
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
U1TX
U1E
U1
CANRX
CANTX
PWM1RINT
PWM1GINT
SPI2RX
SPI2TX
SPI2
TU16B
TMR3
TMR3G
PWM2RINT
PWM2GINT
INT1
CLC2
CWG1 (Complementary Waveform Generator)
NCO1 (Numerically Controlled Oscillator)
DMA2SCNT
DMA2DCNT
DMA2OR
DMA2A
I2C1RX
I2C1TX
I2C1
I2C1E
CLC3
PWM3RINT
PWM3GINT
U2RX
U2TX
U2E
U2
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
0x7B
0x7C
0x7D
0x7E
0x7F
0x80
0x81
0x82
0x83
0x84
0x85
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x8F
DMA6DCNT
DMA6OR
DMA6A
CLC7
CM2
NCO3
DMA7SCNT
DMA7DCNT
DMA7OR
DMA7ABRT
NVM
CLC8
CRC (Cyclic Redundancy Check)
TMR6
DMA8SCNT
DMA8DCNT
DMA8OR
DMA8ABRT
TU16APR
TU16ACAPT
TU16AZERO
TU16BPR
TU16BCAPT
TU16BZERO
-
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
TMR5
TMR5G
CCP2
SCAN
U3RX
U3TX
U3E
U3
0x90
0x91
0x92
0x93
0x94
0x95
0x96
0x97
PWM1.S1P1 (PWM1 Parameter 1 of Slice 1)
PWM1.S1P2 (PWM1 Parameter 2 of Slice 1)
PWM2S1P1
PWM2S1P2
PWM3S1P1
PWM3S1P2
PWM4S1P1
PWM4S1P2
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
DMA - Direct Memory Access
16.13.14 DMAnAIRQ
Name:
Address:
DMAnAIRQ
0x0FE
DMA Abort Interrupt Request Source Selection Register
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
AIRQ[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – AIRQ[7:0] DMA Abort Interrupt Request Source Selection
Refer to DMA Interrupt Sources Table.
© 2021 Microchip Technology Inc.
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PIC18F27/47/57Q84
DMA - Direct Memory Access
16.14
Address
Register Summary - DMA
Name
0x00
...
0xE7
0xE8
0xE9
DMASELECT
DMAnBUF
0xEA
DMAnDCNT
DMAnDPTR
0xEE
DMAnDSZ
0xF0
DMAnDSA
0xF2
DMAnSCNT
0xF7
7
6
5
4
3
2
1
0
Reserved
0xEC
0xF4
Bit Pos.
DMAnSPTR
DMAnSSZ
0xF9
DMAnSSA
0xFC
0xFD
0xFE
0xFF
DMAnCON0
DMAnCON1
DMAnAIRQ
DMAnSIRQ
7:0
7:0
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
23:16
7:0
15:8
7:0
15:8
23:16
7:0
7:0
7:0
7:0
SLCT[2:0]
BUF[7:0]
DCNT[7:0]
DCNT[11:8]
DPTR[7:0]
DPTR[15:8]
DSZ[7:0]
DSZ[11:8]
DSA[7:0]
DSA[15:8]
SCNT[7:0]
SCNT[11:8]
SPTR[7:0]
SPTR[15:8]
SPTR[21:16]
SSZ[7:0]
SSZ[11:8]
SSA[7:0]
SSA[15:8]
EN
SIRQEN
DMODE[1:0]
© 2021 Microchip Technology Inc.
DGO
DSTP
SMR[1:0]
AIRQ[7:0]
SIRQ[7:0]
Preliminary Datasheet
SSA[21:16]
AIRQEN
SMODE[1:0]
XIP
SSTP
DS40002213D-page 316
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Power-Saving Modes
17.
Power-Saving Modes
The purpose of the Power-Saving modes is to reduce power consumption. There are three Power-Saving modes:
•
•
•
17.1
Doze mode
Sleep mode
Idle mode
Doze Mode
Doze mode allows for power saving by reducing CPU operation and Program Flash Memory (PFM) access, without
affecting peripheral operation. Doze mode differs from Sleep mode because the band gap and system oscillators
continue to operate, while only the CPU and PFM are affected. The reduced execution saves power by eliminating
unnecessary operations within the CPU and memory.
When the Doze Enable bit is set (DOZEN = 'b1) the CPU executes only one instruction cycle out of every N
cycles as defined by the DOZE bits. For example, if DOZE = 001, the instruction cycle ratio is 1:4. The CPU and
memory execute for one instruction cycle and then lay Idle for three instruction cycles. During the unused cycles, the
peripherals continue to operate at the system clock speed.
17.1.1
Doze Operation
The Doze operation is illustrated in Figure 17-1. As with normal operation, the instruction is fetched for the next
instruction cycle while the previous instruction is executed. The Q-clocks to the peripherals continue throughout the
periods in which no instructions are fetched or executed. The following configuration settings apply for this example:
•
Doze enabled (DOZEN = 1)
•
•
CPU instruction cycle to peripheral instruction cycle ratio of 1:4
Recover-on-Interrupt enabled (ROI = 1)
Figure 17-1. Doze Mode Operation Example
System
Clock
1
1
2
Instruction
Period
1
2
3
2
3
4
3
4
1
2
2
3
4
1
1
2
3
4
1
2
3
4
1
2
2
3
4
1
1
3
4
1
2
3
4
1
2
3
4
1
2
3
4
2
3
4
4
4
1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4
1 2 3 4
1 2 3 4
PFM Op s
Fetch
Fetch
Push
0004h
Fetch
Fetch
CPU Op s
Exec
Exec
Exec(1,2)
NOP
Exec
Exec
CPU Clock
3
Exec
Interrupt
(ROI = 1)
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Power-Saving Modes
Notes:
1. Multicycle instructions are executed to completion before fetching 0x0004.
2.
17.1.2
If the prefetched instruction clears GIE, the ISR will not occur, but DOZEN is still cleared and the CPU will
resume execution at full speed.
Interrupts During Doze
System behavior for interrupts that may occur during Doze mode are be configured using the ROI bit and the DOE
bit. Refer to the example below for details about system behavior in all cases for a transition from Main to ISR back to
Main.
Example 17-1. Doze Software Example
// Mainline operation
bool somethingToDo = FALSE;
void main() {
initializeSystem();
// DOZE = 64:1 (for example)
// ROI = 1;
GIE = 1; // enable interrupts
while (1) {
// If ADC completed, process data
if (somethingToDo) {
doSomething();
DOZEN = 1; // resume low-power
}
}
}
// Data interrupt handler
void interrupt() {
// DOZEN = 0 because ROI = 1
if (ADIF) {
somethingToDo = TRUE;
DOE = 0; // make main() go fast
ADIF = 0;
}
// else check other interrupts...
if (TMR0IF) {
timerTick++;
DOE = 1; // make main() go slow
TMR0IF = 0;
}
}
Note:
1. User software can change DOE bit in the ISR.
17.2
Sleep Mode
Sleep mode provides the greatest power savings because both the CPU and selected peripherals cease to operate.
However, some peripheral clocks continue to operate during sleep. The peripherals that use those clocks also
continue to operate. Sleep mode is entered by executing the SLEEP instruction, while the IDLEN bit is clear. Upon
entering Sleep mode, the following conditions exist:
1.
2.
3.
4.
The WDT will be cleared but keeps running if enabled for operation during Sleep
The PD bit of the STATUS register is cleared
The TO bit of the STATUS register is set
The CPU clock is disabled
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Power-Saving Modes
5.
6.
7.
LFINTOSC, SOSC, HFINTOSC, and ADCRC (FRC) are unaffected. Peripherals using them may continue
operation during Sleep.
I/O ports maintain the status they had before Sleep was executed (driving high, low, or high-impedance)
Resets other than WDT are not affected by Sleep mode
Important: Refer to individual chapters for more details on peripheral operation during Sleep.
To minimize current consumption, the following conditions will be considered:
•
•
•
•
•
I/O pins must not be floating
External circuitry sinking current from I/O pins
Internal circuitry sourcing current to I/O pins
Current draw from pins with internal weak pull-ups
Peripherals using clock source unaffected by Sleep
I/O pins that are high-impedance inputs need to be pulled to VDD or VSS externally to avoid switching currents caused
by floating inputs. Examples of internal circuitry that might be consuming current include modules such as the DAC
and FVR peripherals.
17.2.1
Wake-up from Sleep
The device can wake up from Sleep through one of the following events:
1.
2.
3.
4.
5.
6.
External Reset input on MCLR pin, if enabled
BOR Reset, if enabled
Low-Power Brown-out Reset (LPBOR), if enabled
POR Reset
Windowed Watchdog Timer, if enabled
All interrupt sources except clock switch interrupt can wake up the part.
Important: The first five events will cause a device Reset. The last event in the list is considered a
continuation of program execution. Fore more information about determining whether a device Reset or
wake-up event occurred, refer to the “Resets” chapter.
When the SLEEP instruction is being executed, the next instruction (PC + 2) is prefetched. For the device to wake up
through an interrupt event, the corresponding Interrupt Enable bit must be enabled in the PIEx register. Wake-up will
occur regardless of the state of the Global Interrupt Enable (GIE) bit. If the GIE bit is disabled, the device will continue
execution at the instruction after the SLEEP instruction. If the GIE bit is enabled, the device executes the instruction
after the SLEEP instruction and then call the Interrupt Service Routine (ISR).
Important: It is recommended to add a NOP as the immediate instruction after the SLEEP instruction.
The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up. Upon a wake-fromSleep event, the core will wait for a combination of three conditions before beginning execution. The conditions are:
•
•
•
PFM Ready
System Clock Ready
BOR Ready (unless BOR is disabled)
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Power-Saving Modes
17.2.2
Wake-up Using Interrupts
When global interrupts are disabled (GIE cleared) and any interrupt source, with the exception of the clock switch
interrupt, has both its interrupt enable bit and interrupt flag bit set, one of the following will occur:
•
If the interrupt occurs before the execution of a SLEEP instruction
– SLEEP instruction will execute as a NOP
•
– WDT and WDT prescaler will not be cleared
– TO bit of the STATUS register will not be set
– PD bit of the STATUS register will not be cleared
If the interrupt occurs during or after the execution of a SLEEP instruction
– SLEEP instruction will be completely executed
–
–
–
–
Device will immediately wake up from Sleep
WDT and WDT prescaler will be cleared
TO bit of the STATUS register will be set
PD bit of the STATUS register will be cleared
In the event where flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to
have become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP.
Figure 17-2. Wake-up From Sleep Through Interrupt
CLKIN(1)
TOS T(3)
CLKOUT (2)
Inte rrupt Flag
Interrupt Latency(4)
Glo bal Interru pt
Ena ble
Processor in
Sleep
Instruction Flo w
PC
Instruction
Fetche d
Instruction
Fetche d
PC
PC + 1
Inst(PC) = Slee p
Inst(PC + 1)
PC + 2
Inst(PC + 2)
Inst(PC - 1)
Sleep
Inst(PC + 1)
PC + 2
PC + 2
Forced NOP
0004h
0005h
Inst(0x0004)
Inst(0x0005)
Forced NOP
Inst(0x0004)
Notes:
1. External clock - High, Medium, Low mode assumed.
2. CLKOUT is shown here for timing reference.
3. TOST = 1024 TOSC. This delay does not apply to EC and INTOSC Oscillator modes.
4. GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0x0004. If GIE = 0, execution will
continue in-line.
17.2.3
Low-Power Sleep Mode
This device family contains an internal Low Dropout (LDO) voltage regulator, which allows the device I/O pins to
operate at voltages up to VDD while the internal device logic operates at a lower voltage. The LDO and its associated
reference circuitry must remain active in Sleep but can operate in different power modes. This allows the user to
optimize the operating current in Sleep mode, depending on the application requirements.
17.2.3.1 Sleep Current vs. Wake-up Time
The Low-Power Sleep mode can be selected by setting the VREGPM bits as following:
• VREGPM = 'b00; the voltage regulator is in High-Power mode. In this mode, the voltage regulator and
reference circuitry remain in the normal configuration while in Sleep. Hence, there is no delay needed for these
circuits to stabilize after wake-up. (fastest wake-up from Sleep)
• VREGPM = 'b01; the voltage regulator is in Low-Power mode. In this mode, when waking up from Sleep, an
extra delay time is required for the voltage regulator and reference circuitry to return to the normal configuration
and stabilize. (faster wake-up from Sleep)
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Power-Saving Modes
•
•
VREGPM = 'b10; the voltage regulator is in Ultra-Low-Power mode. In this mode, the voltage regulator and
reference circuitry are in the lowest current consumption mode and all the auxiliary circuits remain shut down.
Wake up from Sleep in this mode need the longest delay time for the voltage regulator and reference circuitry to
stabilize. (lowest current consumption)
VREGPM = 'b11; this mode is the similar to the Ultra-Low-Power mode (VREGPM = 'b10), and is
recommended ONLY for extended temperature ranges at or above 70℃.
17.2.3.2 Peripheral Usage in Sleep
Some peripherals that can operate in High-Power Sleep mode (VREGPM = 'b00) will not operate as intented in the
Low-Power Sleep modes (VREGPM = 'b01 and 'b11). The Low-Power Sleep modes are intended for use with the
following peripherals:
•
•
•
Brown-out Reset (BOR)
Windowed Watchdog Timer (WWDT)
External interrupt pin/Interrupt-On-Change pins
It is the responsibility of the end user to determine what is acceptable for their application when setting the VREGPM
settings in order to ensure correct operation in Sleep.
17.3
Idle Mode
When the IDLEN bit is clear, the SLEEP instruction will put the device into full Sleep mode. When IDLEN is set,
the SLEEP instruction will put the device into Idle mode. In Idle mode, the CPU and memory operations are halted,
but the peripheral clocks continue to run. This mode is similar to Doze mode, except that in Idle both the CPU and
program memory are shut off.
Important:
1. Peripherals using FOSC will continue to operate while in Idle (but not in Sleep). Peripherals using
HFINTOSC:LFINTOSC will continue running in both Idle and Sleep.
2. When the Clock Out Enable (CLKOUTEN) Configuration bit is cleared, the CLKOUT pin will
continue operating while in Idle.
17.3.1
Idle and Interrupts
Idle mode ends when an interrupt occurs (even if global interrupts are disabled), but IDLEN is not changed. The
device can re-enter Idle by executing the SLEEP instruction. If Recover-on-Interrupt is enabled (ROI = 1), the interrupt
that brings the device out of Idle also restores full-speed CPU execution when Doze is also enabled.
17.3.2
Idle and WWDT
When in Idle, the WWDT Reset is blocked and will instead wake the device. The WWDT wake-up is not an interrupt,
therefore ROI does not apply.
Important: The WWDT can bring the device out of Idle, in the same way it brings the device out of Sleep.
The DOZEN bit is not affected.
17.4
Peripheral Operation in Power-Saving Modes
All selected clock sources and the peripherals running from them are active in both Idle and Doze modes. Only in
Sleep mode, both the FOSC and FOSC/4 clocks are unavailable. However, all other clock sources enabled specifically
or through peripheral clock selection before the part enters Sleep, remain operating in Sleep.
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Power-Saving Modes
17.5
Register Definitions: Power-Savings Control
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Power-Saving Modes
17.5.1
CPUDOZE
Name:
Address:
CPUDOZE
0x4F2
Doze and Idle Register
Bit
Access
Reset
7
IDLEN
R/W
0
6
DOZEN
R/W/HC/HS
0
5
ROI
R/W
0
4
DOE
R/W/HC/HS
0
3
2
R/W
0
1
DOZE[2:0]
R/W
0
0
R/W
0
Bit 7 – IDLEN Idle Enable
Value
Description
1
A SLEEP instruction places device into Idle mode
0
A SLEEP instruction places the device into Sleep mode
Bit 6 – DOZEN Doze Enable(1)
Value
Description
1
Places devices into Doze setting
0
Places devices into Normal mode
Bit 5 – ROI Recover-on-Interrupt(1)
Value
Description
1
Entering the Interrupt Service Routine (ISR) makes DOZEN = 0
0
Entering the Interrupt Service Routine (ISR) does not change DOZEN
Bit 4 – DOE Doze-on-Exit(1)
Value
Description
1
Exiting the ISR makes DOZEN = 1
0
Exiting the ISR does not change DOZEN
Bits 2:0 – DOZE[2:0] Ratio of CPU Instruction Cycles to Peripheral Instruction Cycles
Value
Description
111
1:256
110
1:128
101
1:64
100
1:32
011
1:16
010
1:8
001
1:4
000
1:2
Note:
1. When ROI = 1 or DOE = 1.
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Power-Saving Modes
17.5.2
VREGCON
Name:
Address:
VREGCON
0x048
Voltage Regulator Control Register
Bit
7
6
5
4
3
PMSYS[1:0]
Access
Reset
R
q
R
q
2
1
0
VREGPM[1:0]
R/W
R/W
1
0
Bits 5:4 – PMSYS[1:0] System Power Mode Status
Value
Description
11
Regulator in Ultra-Low-Power (ULP) mode for extended temperature range is active
10
Regulator in Ultra-Low-Power (ULP) mode is active
01
Regulator in Low-Power mode (LP) mode is active
00
Regulator in High-Power mode (HP) mode is active
Bits 1:0 – VREGPM[1:0] Voltage Regulator Power Mode Selection
Value
Description
11
Regulator in Ultra-Low-Power (ULP) mode. Use ONLY for extended temperature range
10
Regulator in Ultra-Low-Power (ULP) mode (lowest current consumption)
01
Regulator in Low-Power mode (LP) (faster wake-up from Sleep)
00
Regulator in High-Power mode (HP) (fastest wake-up from Sleep)
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Power-Saving Modes
17.6
Address
0x00
...
0x47
0x48
0x49
...
0x04F1
0x04F2
Register Summary - Power-Savings Control
Name
Bit Pos.
7
6
5
4
3
2
1
0
Reserved
VREGCON
7:0
PMSYS[1:0]
VREGPM[1:0]
Reserved
CPUDOZE
7:0
IDLEN
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DOZEN
ROI
DOE
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PMD - Peripheral Module Disable
18.
PMD - Peripheral Module Disable
18.1
Overview
This module provides the ability to selectively enable or disable a peripheral. Disabling a peripheral places it in
its lowest possible power state. The user can selectively disable unused modules to reduce the overall power
consumption.
Important: All modules are ON by default following any system Reset.
18.2
Disabling a Module
A peripheral can be disabled by setting the corresponding peripheral disable bit in the PMDx register. Disabling a
module has the following effects:
18.3
•
•
The module is held in Reset and does not function.
All the SFRs pertaining to that peripheral become “unimplemented”
– Writing is disabled
– Reading returns 0x00
•
Module outputs are disabled
Enabling a Module
Clearing the corresponding module disable bit in the PMDx register, re-enables the module and the SFRs will reflect
the Power-on Reset values.
Important: There will be no reads/writes to the module SFRs for at least two instruction cycles after it has
been re-enabled.
18.4
Register Definitions: Peripheral Module Disable
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PMD - Peripheral Module Disable
18.4.1
PMD0
Name:
Address:
PMD0
0x060
PMD Control Register 0
Bit
Access
Reset
7
SYSCMD
R/W
0
6
FVRMD
R/W
0
5
HLVDMD
R/W
0
4
CRCMD
R/W
0
3
SCANMD
R/W
0
2
1
CLKRMD
R/W
0
0
IOCMD
R/W
0
Bit 7 – SYSCMD Disable Peripheral System Clock Network(1)
Value
Description
1
System clock network disabled (FOSC)
0
System clock network enabled
Bit 6 – FVRMD Disable Fixed Voltage Reference
Disable Fixed Voltage Reference
Value
Description
1
FVR module disabled
0
FVR module enabled
Bit 5 – HLVDMD Disable High/Low-Voltage Detect
Value
Description
1
HLVD module disabled
0
HLVD module enabled
Bit 4 – CRCMD Disable CRC Module
Value
Description
1
CRC module disabled
0
CRC module enabled
Bit 3 – SCANMD Disable NVM Memory Scanner
Value
Description
1
NVM memory scanner module disabled
0
NVM memory scanner module enabled
Bit 1 – CLKRMD Disable Clock Reference
Value
Description
1
Clock reference module disabled
0
Clock reference module enabled
Bit 0 – IOCMD Disable Interrupt-on-Change
Value
Description
1
Interrupt-on-change module is disabled
0
Interrupt-on-change module is enabled
Note:
1. Clearing the SYSCMD bit disables the system clock (FOSC) to peripherals, however peripherals clocked by
FOSC/4 are not affected.
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PMD - Peripheral Module Disable
18.4.2
PMD1
Name:
Address:
PMD1
0x061
PMD Control Register 1
Bit
Access
Reset
7
SMT1MD
R/W
0
6
TMR6MD
R/W
0
5
TMR5MD
R/W
0
4
TMR4MD
R/W
0
3
TMR3MD
R/W
0
2
TMR2MD
R/W
0
1
TMR1MD
R/W
0
0
TMR0MD
R/W
0
Bit 7 – SMT1MD Disable SMT1 Module
Value
Description
1
SMT1 module disabled
0
SMT1 module enabled
Bits 0, 1, 2, 3, 4, 5, 6 – TMRnMD Disable Timer TMRn
Value
Description
1
TMRn module disabled
0
TMRn module enabled
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PMD - Peripheral Module Disable
18.4.3
PMD2
Name:
Address:
PMD2
0x062
PMD Control Register 2
Bit
Access
Reset
7
CANMD
R/W
0
6
5
4
3
2
1
TU16BMD
R/W
0
0
TU16AMD
R/W
0
Bit 7 – CANMD Disable CAN Module
Value
Description
1
CAN module disabled
0
CAN module enabled
Bit 1 – TU16BMD Disable Universal Timer UT16B
Value
Description
1
UT16B module disabled
0
UT16B module enabled
Bit 0 – TU16AMD Disable Universal Timer UT16A
Value
Description
1
UT16A module disabled
0
UT16A module enabled
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PMD - Peripheral Module Disable
18.4.4
PMD3
Name:
Address:
PMD3
0x063
PMD Control Register 3
Bit
Access
Reset
7
ACTMD
R/W
0
6
DAC1MD
R/W
0
5
ADCMD
R/W
0
4
3
2
C2MD
R/W
0
1
C1MD
R/W
0
0
ZCDMD
R/W
0
Bit 7 – ACTMD Disable Active Clock Tuning
Value
Description
1
Active Clock Tuning disabled
0
Active Clock Tuning enabled
Bit 6 – DAC1MD Disable Digital to Analog Converter
Value
Description
1
DAC module disabled
0
DAC module enabled
Bit 5 – ADCMD Disable Analog to Digital Converter
Value
Description
1
ADC module disabled
0
ADC module enabled
Bit 2 – C2MD Disable Comparator 2
Value
Description
1
CM2 module disabled
0
CM2 module enabled
Bit 1 – C1MD Disable Comparator 1
Value
Description
1
CM1 module disabled
0
CM1 module enabled
Bit 0 – ZCDMD Disable Zero Cross Detect(1)
Value
Description
1
ZCD module disabled
0
ZCD module enabled
Note:
1. Subject to the value of ZCD Configuration bit.
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PMD - Peripheral Module Disable
18.4.5
PMD4
Name:
Address:
PMD4
0x064
PMD Control Register 4
Bit
Access
Reset
7
6
CWG3MD
R/W
0
5
CWG2MD
R/W
0
4
CWG1MD
R/W
0
3
DSM1MD
R/W
0
2
NCO3MD
R/W
0
1
NCO2MD
R/W
0
0
NCO1MD
R/W
0
Bit 6 – CWG3MD Disable Complimentary Waveform Generator 3
Value
Description
1
CWG3 module disabled
0
CWG3 module enabled
Bit 5 – CWG2MD Disable Complimentary Waveform Generator 2
Value
Description
1
CWG2 module disabled
0
CWG2 module enabled
Bit 4 – CWG1MD Disable Complimentary Waveform Generator 1
Value
Description
1
CWG1 module disabled
0
CWG1 module enabled
Bit 3 – DSM1MD Disable Digital Signal Modulator
Value
Description
1
DSM module disabled
0
DSM module enabled
Bit 2 – NCO3MD Disable Numerically Controlled Oscillator 3
Value
Description
1
NCO3 module disabled
0
NCO3 module enabled
Bit 1 – NCO2MD Disable Numerically Controlled Oscillator 2
Value
Description
1
NCO2 module disabled
0
NCO2 module enabled
Bit 0 – NCO1MD Disable Numerically Controlled Oscillator 1
Value
Description
1
NCO1 module disabled
0
NCO1 module enabled
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PMD - Peripheral Module Disable
18.4.6
PMD5
Name:
Address:
PMD5
0x065
PMD Control Register 5
Bit
Access
Reset
7
PWM4MD
R/W
0
6
PWM3MD
R/W
0
5
PWM2MD
R/W
0
4
PWM1MD
R/W
0
3
2
CCP3MD
R/W
0
1
CCP2MD
R/W
0
0
CCP1MD
R/W
0
Bit 7 – PWM4MD Disable Pulse Width Modulator 4
Value
Description
1
PWM4 module disabled
0
PWM4 module enabled
Bit 6 – PWM3MD Disable Pulse Width Modulator 3
Value
Description
1
PWM3 module disabled
0
PWM3 module enabled
Bit 5 – PWM2MD Disable Pulse Width Modulator 2
Value
Description
1
PWM2 module disabled
0
PWM2 module enabled
Bit 4 – PWM1MD Disable Pulse Width Modulator 1
Value
Description
1
PWM1 module disabled
0
PWM1 module enabled
Bit 2 – CCP3MD Disable Capture Compare 3
Value
Description
1
CCP3 module disabled
0
CCP3 module enabled
Bit 1 – CCP2MD Disable Capture Compare 2
Value
Description
1
CCP2 module disabled
0
CCP2 module enabled
Bit 0 – CCP1MD Disable Capture Compare 1
Value
Description
1
CCP1 module disabled
0
CCP1 module enabled
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PMD - Peripheral Module Disable
18.4.7
PMD6
Name:
Address:
PMD6
0x066
PMD Control Register 6
Bit
Access
Reset
7
U5MD
R/W
0
6
U4MD
R/W
0
5
U3MD
R/W
0
4
U2MD
R/W
0
3
U1MD
R/W
0
2
SPI2MD
R/W
0
1
SPI1MD
R/W
0
0
I2C1MD
R/W
0
Bits 3, 4, 5, 6, 7 – UnMD Disable UART Un
Value
Description
1
UARTn module disabled
0
UARTn module enabled
Bit 2 – SPI2MD Disable Serial Peripheral Interface 2
Value
Description
1
SPI2 module disabled
0
SPI2 module enabled
Bit 1 – SPI1MD Disable Serial Peripheral Interface 1
Value
Description
1
SPI1 module disabled
0
SPI1 module enabled
Bit 0 – I2C1MD Disable I2C
Value
Description
1
I2C1 module disabled
0
I2C1 module enabled
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PMD - Peripheral Module Disable
18.4.8
PMD7
Name:
Address:
PMD7
0x067
PMD Control Register 7
Bit
Access
Reset
7
CLC8MD
R/W
0
6
CLC7MD
R/W
0
5
CLC6MD
R/W
0
4
CLC5MD
R/W
0
3
CLC4MD
R/W
0
2
CLC3MD
R/W
0
1
CLC2MD
R/W
0
0
CLC1MD
R/W
0
Bits 0, 1, 2, 3, 4, 5, 6, 7 – CLCnMD Disable CLCn
Value
Description
1
CLCn module disabled
0
CLCn module enabled
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PMD - Peripheral Module Disable
18.4.9
PMD8
Name:
Address:
PMD8
0x068
PMD Control Register 8
Bit
Access
Reset
7
DMA8MD
R/W
0
6
DMA7MD
R/W
0
5
DMA6MD
R/W
0
4
DMA5MD
R/W
0
3
DMA4MD
R/W
0
2
DMA3MD
R/W
0
1
DMA2MD
R/W
0
0
DMA1MD
R/W
0
Bits 0, 1, 2, 3, 4, 5, 6, 7 – DMAnMD Disable DMAn
Value
Description
1
DMAn module disabled
0
DMAn module enabled
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PMD - Peripheral Module Disable
18.5
Address
0x00
...
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
Register Summary - PMD
Name
Bit Pos.
7
6
5
4
3
2
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
SYSCMD
SMT1MD
CANMD
ACTMD
FVRMD
TMR6MD
HLVDMD
TMR5MD
CRCMD
TMR4MD
SCANMD
TMR3MD
TMR2MD
DAC1MD
CWG3MD
PWM3MD
U4MD
CLC7MD
DMA7MD
ADCMD
CWG2MD
PWM2MD
U3MD
CLC6MD
DMA6MD
CWG1MD
PWM1MD
U2MD
CLC5MD
DMA5MD
DSM1MD
1
0
CLKRMD
TMR1MD
TU16BMD
C1MD
NCO2MD
CCP2MD
SPI1MD
CLC2MD
DMA2MD
IOCMD
TMR0MD
TU16AMD
ZCDMD
NCO1MD
CCP1MD
I2C1MD
CLC1MD
DMA1MD
Reserved
PMD0
PMD1
PMD2
PMD3
PMD4
PMD5
PMD6
PMD7
PMD8
PWM4MD
U5MD
CLC8MD
DMA8MD
© 2021 Microchip Technology Inc.
U1MD
CLC4MD
DMA4MD
Preliminary Datasheet
C2MD
NCO3MD
CCP3MD
SPI2MD
CLC3MD
DMA3MD
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I/O Ports
19.
I/O Ports
19.1
Overview
Table 19-1. Port Availability per Device
Device
PORTA
PORTB
PORTC
PORTD
PORTE
28-pin devices
●
●
●
40/44-pin devices
●
●
●
●
●(2)
48-pin devices
●
●
●
●
●(2)
PORTF
●(1)
●
Notes:
1. Pin RE3 only.
2. Pins RE0, RE1, RE2 and RE3 only.
Each port has eight registers to control the operation. These registers are:
•
•
•
•
•
•
•
•
PORTx registers (reads the levels on the pins of the device)
LATx registers (output latch)
TRISx registers (data direction)
ANSELx registers (analog select)
WPUx registers (weak pull-up)
INLVLx (input level control)
SLRCONx registers (slew rate control)
ODCONx registers (open-drain control)
In this chapter the generic names such as PORTx, LATx, TRISx, etc. can be associated with PORTA, PORTB,
PORTC, etc., depending on availability per device.
A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in the following figure:
Figure 19-1. Generic I/O Port Operation
Re v. 10 -00 00 52 A
2/11 /20 19
Read LATx
TRISx
D
Q
Write LATx
Write PORTx
VDD
CK
Data Register
Data bus
I/O pin
Read PORTx
To digital peripherals
ANSELx
To analog peripherals
VSS
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I/O Ports
19.2
PORTx - Data Register
PORTx is a bidirectional port, and its corresponding data direction register is TRISx.
Reading the PORTx register reads the status of the pins, whereas writing to it will write to the PORT latch. All write
operations are read-modify-write operations. Therefore, a write to a port implies that the PORT pins are read, and this
value is modified, then written to the PORT data latch (LATx). The PORT data latch LATx holds the output port data
and contains the latest value of a LATx or PORTx write. The example below shows how to initialize PORTA.
Example 19-1. Initializing PORTA in assembly
; This code example illustrates initializing the PORTA register.
; The other ports are initialized in the same manner.
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
PORTA
PORTA
LATA
LATA
ANSELA
ANSELA
TRISA
B'00111000'
TRISA
;
;Clear PORTA
;
;Clear Data Latch
;
;Enable digital drivers
;
;Set RA[5:3] as inputs
;and set others as outputs
Example 19-2. Initializing PORTA in C
// This code example illustrates initializing the PORTA register.
// The other ports are initialized in the same manner.
PORTA
LATA
ANSELA
TRISA
outputs
=
=
=
=
0x00;
0x00;
0x00;
0x38;
//
//
//
//
Clear PORTA
Clear Data Latch
Enable digital drivers
Set RA[5:3] as inputs and set others as
Important: Most PORT pins share functions with device peripherals, both analog and digital. In general,
when a peripheral is enabled on a PORT pin, that pin cannot be used as a general purpose output;
however, the pin can still be read.
19.3
LATx - Output Latch
The Data Latch (LATx registers) is useful for read-modify-write operations on the value that the I/O pins are driving.
A write operation to the LATx register has the same effect as a write to the corresponding PORTx register. A read
of the LATx register reads of the values held in the I/O PORT latches, while a read of the PORTx register reads the
actual I/O pin value.
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I/O Ports
Important: As a general rule, output operations to a port must use the LAT register to avoid read-modifywrite issues. For example, a bit set or clear operation reads the port, modifies the bit, and writes the result
back to the port. When two bit operations are executed in succession, output loading on the changed bit
may delay the change at the output in which case the bit will be misread in the second bit operation and
written to an unexpected level. The LAT registers are isolated from the port loading and therefore changes
are not delayed.
19.4
TRISx - Direction Control
The TRISx register controls the PORTx pin output drivers, even when the pins are being used as analog inputs. The
user must ensure the bits in the TRISx register are set when using the pins as analog inputs. I/O pins configured as
analog inputs always read ‘0’.
Setting a TRISx bit (TRISx = 1) will make the corresponding PORTx pin an input (i.e., disable the output driver).
Clearing a TRISx bit (TRISx = 0) will make the corresponding PORTx pin an output (i.e., it enables output driver and
puts the contents of the output latch on the selected pin).
19.5
ANSELx - Analog Control
Ports that support analog inputs have an associated ANSELx register. The ANSELx register is used to configure the
input mode of an I/O pin to analog. Setting an ANSELx bit high will disable the digital input buffer associated with
that bit and cause the corresponding input value to always read ‘0’, whether the value is read in PORTx register or
selected by PPS as a peripheral input.
Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing
excessive current in the logic input circuitry.
The state of the ANSELx bits has no effect on digital or analog output functions. A pin with TRIS clear and ANSEL
set will still operate as a digital output, but the input mode will be analog. This can cause unexpected behavior when
executing read-modify-write instructions on the PORTx register.
Important: The ANSELx bits default to the Analog mode after Reset. To use any pins as digital general
purpose or peripheral inputs, the corresponding ANSEL bits must be changed to ‘0’ by user.
19.6
WPUx - Weak Pull-Up Control
The WPUx register controls the individual weak pull-ups for each PORT pin. When a WPUx bit is set (WPUx = 1), the
weak pull-up will be enabled for the corresponding pin. When a WPUx bit is cleared (WPUx = 0), the weak pull-up will
be disabled for the corresponding pin.
19.7
INLVLx - Input Threshold Control
The INLVLx register controls the input voltage threshold for each of the available PORTx input pins. A selection
between the Schmitt Trigger CMOS or the TTL compatible thresholds is available. If that feature is enabled, the input
threshold is important in determining the value of a read of the PORTx register and also all other peripherals which
are connected to the input. Refer to the I/O Ports table in the “Electrical Specifications” chapter for more details on
threshold levels.
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I/O Ports
Important: Changing the input threshold selection must be performed while all peripheral modules are
disabled. Changing the threshold level during the time a module is active may inadvertently generate a
transition associated with an input pin, regardless of the actual voltage level on that pin.
19.8
SLRCONx - Slew Rate Control
The SLRCONx register controls the slew rate option for each PORT pin. Slew rate for each PORT pin can be
controlled independently. When a SLRCONx bit is set (SLRCONx = 1), the corresponding PORT pin drive is slew
rate limited. When a SLRCONx bit is cleared (SLRCONx = 0), The corresponding PORT pin drive slews at the
maximum rate possible.
19.9
ODCONx - Open-Drain Control
The ODCONx register controls the open-drain feature of the port. Open-drain operation is independently selected for
each pin. When a ODCONx bit is set (ODCONx = 1), the corresponding port output becomes an open-drain driver
capable of sinking current only. When a ODCONx bit is cleared (ODCONx = 0), the corresponding port output pin is
the standard push-pull drive capable of sourcing and sinking current.
Important: It is necessary to set open-drain control when using the pin for I2C.
19.10
Edge Selectable Interrupt-on-Change
An interrupt can be generated by detecting a signal at the PORT pin that has either a rising edge or a falling edge.
Individual pins can be independently configured to generate an interrupt. Refer to the “IOC - Interrupt-on-Change”
chapter for more details.
19.11
I2C Pad Control
For this family of devices, the I2C specific pads are available on RB1, RB2, RC3 and RC4 pins. The I2C
characteristics of each of these pins is controlled by the RxyI2C registers. These characteristics include enabling I2C
specific slew rate (over standard GPIO slew rate), selecting internal pull-ups for I2C pins, and selecting appropriate
input threshold as per SMBus specifications.
Important: Any peripheral using the I2C pins reads the I2C input levels when enabled via RxyI2C.
19.12
I/O Priorities
Each pin defaults to the data latch after Reset. Other functions are selected with the peripheral pin select logic. Refer
to the “PPS - Peripheral Pin Select Module” chapter for more details.
Analog input functions, such as ADC and comparator inputs, are not shown in the peripheral pin select lists. These
inputs are active when the I/O pin is set for Analog mode using the ANSELx register. Digital output functions may
continue to control the pin when it is in Analog mode.
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I/O Ports
Analog outputs, when enabled, take priority over digital outputs and force the digital output driver into a highimpedance state.
The pin function priorities are as follows:
1.
2.
3.
4.
19.13
Port functions determined by the Configuration bits
Analog outputs (input buffers must be disabled)
Analog inputs
Port inputs and outputs from PPS
MCLR/VPP/RE3 Pin
The MCLR/VPP pin is an input-only pin. Its operation is controlled by the MCLRE Configuration bit. When selected
as a PORT pin (MCLRE = 0), it functions as a digital input-only pin; as such, it does not have TRISx and LATx bits
associated with its operation. Otherwise, it functions as the device’s Master Clear input. In either configuration, the
MCLR/VPP pin also functions as the programming voltage input pin during high voltage programming.
The MCLR/VPP pin is a read-only bit and will read ‘1’ when MCLRE = 1 (i.e., Master Clear enabled).
Important: On a Power-on Reset, the MCLR/VPP pin is enabled as a digital input-only if Master Clear
functionality is disabled.
The MCLR/VPP pin has an individually controlled internal weak pull-up. When set, the corresponding WPU bit
enables the pull-up. When the MCLR/VPP pin is configured as MCLR (MCLRE = 1 and, LVP = 0), or configured for
Low-Voltage Programming (MCLRE = x and LVP = 1), the pull-up is always enabled and the WPU bit has no effect.
19.14
Register Definitions: Port Control
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I/O Ports
19.14.1 PORTx
Name:
PORTx
PORTx Register
Bit
Access
Reset
7
Rx7
R/W
x
6
Rx6
R/W
x
5
Rx5
R/W
x
4
Rx4
R/W
x
3
Rx3
R/W
x
2
Rx2
R/W
x
1
Rx1
R/W
x
0
Rx0
R/W
x
Bits 0, 1, 2, 3, 4, 5, 6, 7 – Rxn Port I/O Value
Reset States: POR/BOR = xxxxxxxx
All Other Resets = uuuuuuuu
Value
Description
1
PORT pin is ≥ VIH
0
PORT pin is ≤ VIL
Important:
• Writes to PORTx are actually written to the corresponding LATx register.
Reads from PORTx register return actual I/O pin values.
• The PORT bit associated with the MCLR pin is Read-Only and will read ‘1’ when MCLR function is
enabled (LVP = 1 or (LVP = 0 and MCLRE = 1)).
•
Refer to the “Pin Allocation Table” for details about MCLR pin and pin availability per port.
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19.14.2 LATx
Name:
LATx
Output Latch Register
Bit
Access
Reset
7
LATx7
R/W
x
6
LATx6
R/W
x
5
LATx5
R/W
x
4
LATx4
R/W
x
3
LATx3
R/W
x
2
LATx2
R/W
x
1
LATx1
R/W
x
0
LATx0
R/W
x
Bits 0, 1, 2, 3, 4, 5, 6, 7 – LATxn Output Latch Value
Reset States: POR/BOR = xxxxxxxx
All Other Resets = uuuuuuuu
Important:
• Writes to LATx are equivalent with writes to the corresponding PORTx register. Reads from LATx
register return register values, not I/O pin values.
• Refer to the “Pin Allocation Table” for details about pin availability per port.
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I/O Ports
19.14.3 TRISx
Name:
TRISx
Tri-State Control Register
Bit
Access
Reset
7
TRISx7
R/W
1
6
TRISx6
R/W
1
5
TRISx5
R/W
1
4
TRISx4
R/W
1
3
TRISx3
R/W
1
2
TRISx2
R/W
1
1
TRISx1
R/W
1
0
TRISx0
R/W
1
Bits 0, 1, 2, 3, 4, 5, 6, 7 – TRISxn Port I/O Tri-state Control
Value
Description
1
PORTx output driver is disabled. PORTx pin configured as an input (tri-stated)
0
PORTx output driver is enabled. PORTx pin configured as an output
Important:
• The TRIS bit associated with the MCLR pin is Read-Only and the value is 1.
•
Refer to the “Pin Allocation Table” for details about MCLR pin and pin availability per port.
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I/O Ports
19.14.4 ANSELx
Name:
ANSELx
Analog Select Register
Bit
Access
Reset
7
ANSELx7
R/W
1
6
ANSELx6
R/W
1
5
ANSELx5
R/W
1
4
ANSELx4
R/W
1
3
ANSELx3
R/W
1
2
ANSELx2
R/W
1
1
ANSELx1
R/W
1
0
ANSELx0
R/W
1
Bits 0, 1, 2, 3, 4, 5, 6, 7 – ANSELxn Analog Select on RX Pin
Value
Description
1
Analog input. Pin is assigned as analog input. Digital input buffer disabled.
0
Digital I/O. Pin is assigned to port or digital special function.
Important:
• When setting a pin as an analog input, the corresponding TRIS bit must be set to Input mode to allow
external control of the voltage on the pin.
• Refer to the “Pin Allocation Table” for details about pin availability per port.
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19.14.5 WPUx
Name:
WPUx
Weak pull-up Register
Bit
Access
Reset
7
WPUx7
R/W
0
6
WPUx6
R/W
0
5
WPUx5
R/W
0
4
WPUx4
R/W
0
3
WPUx3
R/W
0
2
WPUx2
R/W
0
1
WPUx1
R/W
0
0
WPUx0
R/W
0
Bits 0, 1, 2, 3, 4, 5, 6, 7 – WPUxn Weak Pull-up PORTx Control
Value
Description
1
Weak pull-up enabled
0
Weak pull-up disabled
Important:
• The weak pull-up device is automatically disabled if the pin is configured as an output but this register
remains unchanged.
• If MCLRE = 1, the weak pull-up on MCLR pin is always enabled and the corresponding WPU bit is
not affected.
• Refer to the “Pin Allocation Table” for details about pin availability per port.
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I/O Ports
19.14.6 INLVLx
Name:
INLVLx
Input Level Control Register
Bit
Access
Reset
7
INLVLx7
R/W
1
6
INLVLx6
R/W
1
5
INLVLx5
R/W
1
4
INLVLx4
R/W
1
3
INLVLx3
R/W
1
2
INLVLx2
R/W
1
1
INLVLx1
R/W
1
0
INLVLx0
R/W
1
Bits 0, 1, 2, 3, 4, 5, 6, 7 – INLVLxn Input Level Select on RX Pin
Value
Description
1
ST input used for port reads and interrupt-on-change
0
TTL input used for port reads and interrupt-on-change
Important: Refer to the “Pin Allocation Table” for details about pin availability per port.
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19.14.7 SLRCONx
Name:
SLRCONx
Slew Rate Control Register
Bit
Access
Reset
7
SLRx7
R/W
1
6
SLRx6
R/W
1
5
SLRx5
R/W
1
4
SLRx4
R/W
1
3
SLRx3
R/W
1
2
SLRx2
R/W
1
1
SLRx1
R/W
1
0
SLRx0
R/W
1
Bits 0, 1, 2, 3, 4, 5, 6, 7 – SLRxn Slew Rate Control on RX Pin
Value
Description
1
PORT pin slew rate is limited
0
PORT pin slews at maximum rate
Important: Refer to the “Pin Allocation Table” for details about pin availability per port.
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19.14.8 ODCONx
Name:
ODCONx
Open-Drain Control Register
Bit
Access
Reset
7
ODCx7
R/W
0
6
ODCx6
R/W
0
5
ODCx5
R/W
0
4
ODCx4
R/W
0
3
ODCx3
R/W
0
2
ODCx2
R/W
0
1
ODCx1
R/W
0
0
ODCx0
R/W
0
Bits 0, 1, 2, 3, 4, 5, 6, 7 – ODCxn Open-Drain Configuration on Rx Pin
Value
Description
1
PORT pin operates as open-drain drive (sink current only)
0
PORT pin operates as standard push-pull drive (source and sink current)
Important: Refer to the “Pin Allocation Table” for details about pin availability per port.
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I/O Ports
19.14.9 RxyI2C
Name:
RxyI2C
I2C Pad Rxy Control Register
Bit
7
6
5
SLEW[1:0]
Access
Reset
R/W
0
4
3
2
1
0
PU[1:0]
R/W
0
R/W
0
TH[1:0]
R/W
0
R/W
0
R/W
0
Bits 7:6 – SLEW[1:0] I2C Specific Slew Rate Limiting Control
Value
Description
11
I2C fast-mode-plus (1 MHz) slew rate enabled. The SLRxy bit is ignored.
10
Reserved
01
I2C fast-mode (400 kHz) slew rate enabled. The SLRxy bit is ignored.
00
Standard GPIO Slew Rate; enabled/disabled via SLRxy bit
Bits 5:4 – PU[1:0] I2C Pull-up Selection
Value
Description
11
Reserved
10
10x current of standard weak pull-up
01
2x current of standard weak pull-up
00
Standard GPIO weak pull-up, enabled via WPUxy bit
Bits 1:0 – TH[1:0] I2C Input Threshold Selection
Value
Description
11
SMBus 3.0 (1.35V) input threshold
10
SMBus 2.0 (2.1 V) input threshold
01
I2C-specific input thresholds
00
Standard GPIO Input pull-up, enabled via INLVLxy registers
Important: Refer to the “Pin Allocation Table” for details about I2C compatible pins.
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I/O Ports
19.15
Address
0x00
...
0x0285
0x0286
0x0287
0x0288
0x0289
0x028A
...
0x03FF
0x0400
0x0401
0x0402
0x0403
0x0404
0x0405
...
0x0407
0x0408
0x0409
0x040A
0x040B
0x040C
0x040D
...
0x040F
0x0410
0x0411
0x0412
0x0413
0x0414
0x0415
...
0x0417
0x0418
0x0419
0x041A
0x041B
0x041C
0x041D
...
0x041F
0x0420
0x0421
0x0422
0x0423
0x0424
0x0425
...
0x0427
0x0428
0x0429
0x042A
0x042B
0x042C
Register Summary - IO Ports
Name
Bit Pos.
7
6
5
4
3
2
1
0
Reserved
RC4I2C
RC3I2C
RB2I2C
RB1I2C
7:0
7:0
7:0
7:0
SLEW[1:0]
SLEW[1:0]
SLEW[1:0]
SLEW[1:0]
PU[1:0]
PU[1:0]
PU[1:0]
PU[1:0]
TH[1:0]
TH[1:0]
TH[1:0]
TH[1:0]
Reserved
ANSELA
WPUA
ODCONA
SLRCONA
INLVLA
7:0
7:0
7:0
7:0
7:0
ANSELA7
WPUA7
ODCA7
SLRA7
INLVLA7
ANSELA6
WPUA6
ODCA6
SLRA6
INLVLA6
ANSELA5
WPUA5
ODCA5
SLRA5
INLVLA5
ANSELA4
WPUA4
ODCA4
SLRA4
INLVLA4
ANSELA3
WPUA3
ODCA3
SLRA3
INLVLA3
ANSELA2
WPUA2
ODCA2
SLRA2
INLVLA2
ANSELA1
WPUA1
ODCA1
SLRA1
INLVLA1
ANSELA0
WPUA0
ODCA0
SLRA0
INLVLA0
7:0
7:0
7:0
7:0
7:0
ANSELB7
WPUB7
ODCB7
SLRB7
INLVLB7
ANSELB6
WPUB6
ODCB6
SLRB6
INLVLB6
ANSELB5
WPUB5
ODCB5
SLRB5
INLVLB5
ANSELB4
WPUB4
ODCB4
SLRB4
INLVLB4
ANSELB3
WPUB3
ODCB3
SLRB3
INLVLB3
ANSELB2
WPUB2
ODCB2
SLRB2
INLVLB2
ANSELB1
WPUB1
ODCB1
SLRB1
INLVLB1
ANSELB0
WPUB0
ODCB0
SLRB0
INLVLB0
7:0
7:0
7:0
7:0
7:0
ANSELC7
WPUC7
ODCC7
SLRC7
INLVLC7
ANSELC6
WPUC6
ODCC6
SLRC6
INLVLC6
ANSELC5
WPUC5
ODCC5
SLRC5
INLVLC5
ANSELC4
WPUC4
ODCC4
SLRC4
INLVLC4
ANSELC3
WPUC3
ODCC3
SLRC3
INLVLC3
ANSELC2
WPUC2
ODCC2
SLRC2
INLVLC2
ANSELC1
WPUC1
ODCC1
SLRC1
INLVLC1
ANSELC0
WPUC0
ODCC0
SLRC0
INLVLC0
7:0
7:0
7:0
7:0
7:0
ANSELD7
WPUD7
ODCD7
SLRD7
INLVLD7
ANSELD6
WPUD6
ODCD6
SLRD6
INLVLD6
ANSELD5
WPUD5
ODCD5
SLRD5
INLVLD5
ANSELD4
WPUD4
ODCD4
SLRD4
INLVLD4
ANSELD3
WPUD3
ODCD3
SLRD3
INLVLD3
ANSELD2
WPUD2
ODCD2
SLRD2
INLVLD2
ANSELD1
WPUD1
ODCD1
SLRD1
INLVLD1
ANSELD0
WPUD0
ODCD0
SLRD0
INLVLD0
INLVLE3
ANSELE2
WPUE2
ODCE2
SLRE2
INLVLE2
ANSELE1
WPUE1
ODCE1
SLRE1
INLVLE1
ANSELE0
WPUE0
ODCE0
SLRE0
INLVLE0
ANSELF3
WPUF3
ODCF3
SLRF3
INLVLF3
ANSELF2
WPUF2
ODCF2
SLRF2
INLVLF2
ANSELF1
WPUF1
ODCF1
SLRF1
INLVLF1
ANSELF0
WPUF0
ODCF0
SLRF0
INLVLF0
Reserved
ANSELB
WPUB
ODCONB
SLRCONB
INLVLB
Reserved
ANSELC
WPUC
ODCONC
SLRCONC
INLVLC
Reserved
ANSELD
WPUD
ODCOND
SLRCOND
INLVLD
Reserved
ANSELE
WPUE
ODCONE
SLRCONE
INLVLE
7:0
7:0
7:0
7:0
7:0
WPUE3
Reserved
ANSELF
WPUF
ODCONF
SLRCONF
INLVLF
7:0
7:0
7:0
7:0
7:0
ANSELF7
WPUF7
ODCF7
SLRF7
INLVLF7
© 2021 Microchip Technology Inc.
ANSELF6
WPUF6
ODCF6
SLRF6
INLVLF6
ANSELF5
WPUF5
ODCF5
SLRF5
INLVLF5
ANSELF4
WPUF4
ODCF4
SLRF4
INLVLF4
Preliminary Datasheet
DS40002213D-page 351
PIC18F27/47/57Q84
I/O Ports
...........continued
Address
0x042D
...
0x04BD
0x04BE
0x04BF
0x04C0
0x04C1
0x04C2
0x04C3
0x04C4
...
0x04C5
0x04C6
0x04C7
0x04C8
0x04C9
0x04CA
0x04CB
0x04CC
...
0x04CD
0x04CE
0x04CF
0x04D0
0x04D1
0x04D2
0x04D3
Name
Bit Pos.
7
6
5
4
3
2
1
0
7:0
7:0
7:0
7:0
7:0
7:0
LATA7
LATB7
LATC7
LATD7
LATA6
LATB6
LATC6
LATD6
LATA5
LATB5
LATC5
LATD5
LATA4
LATB4
LATC4
LATD4
LATA3
LATB3
LATC3
LATD3
LATF7
LATF6
LATF5
LATF4
LATF3
LATA2
LATB2
LATC2
LATD2
LATE2
LATF2
LATA1
LATB1
LATC1
LATD1
LATE1
LATF1
LATA0
LATB0
LATC0
LATD0
LATE0
LATF0
7:0
7:0
7:0
7:0
7:0
7:0
TRISA7
TRISB7
TRISC7
TRISD7
TRISA6
TRISB6
TRISC6
TRISD6
TRISA5
TRISB5
TRISC5
TRISD5
TRISA4
TRISB4
TRISC4
TRISD4
TRISF7
TRISF6
TRISF5
TRISF4
TRISA3
TRISB3
TRISC3
TRISD3
Reserved
TRISF3
TRISA2
TRISB2
TRISC2
TRISD2
TRISE2
TRISF2
TRISA1
TRISB1
TRISC1
TRISD1
TRISE1
TRISF1
TRISA0
TRISB0
TRISC0
TRISD0
TRISE0
TRISF0
7:0
7:0
7:0
7:0
7:0
7:0
RA7
RB7
RC7
RD7
RA6
RB6
RC6
RD6
RA5
RB5
RC5
RD5
RA4
RB4
RC4
RD4
RF7
RF6
RF5
RF4
RA3
RB3
RC3
RD3
RE3
RF3
RA2
RB2
RC2
RD2
RE2
RF2
RA1
RB1
RC1
RD1
RE1
RF1
RA0
RB0
RC0
RD0
RE0
RF0
Reserved
LATA
LATB
LATC
LATD
LATE
LATF
Reserved
TRISA
TRISB
TRISC
TRISD
TRISE
TRISF
Reserved
PORTA
PORTB
PORTC
PORTD
PORTE
PORTF
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 352
PIC18F27/47/57Q84
IOC - Interrupt-on-Change
20.
IOC - Interrupt-on-Change
20.1
Overview
The pins denoted in the table below can be configured to operate as Interrupt-on-Change (IOC) pins for this device.
An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual
PORT pin, or combination of PORT pins, can be configured to generate an interrupt.
Table 20-1. IOC Pin Availability per Device
Device
PORTA
PORTB
PORTC
PORTD
PORTE
28-pin devices
●
●
●
●(1)
40/44-pin devices
●
●
●
●(2)
48-pin devices
●
●
●
●(2)
PORTF
Notes:
1. Pin RE3 only.
2. Pins RE0, RE1, RE2 and RE3 only.
Important: If MCLRE = 1 or LVP = 1, the MCLR pin port functionality is disabled and IOC on that pin is
not available.
The Interrupt-on-Change module has the following features:
• Interrupt-on-Change enable (Host Switch)
• Individual pin configuration
• Rising and falling edge detection
• Individual pin interrupt flags
The following figure is a block diagram of the IOC module.
Figure 20-1. Interrupt-on-Change Block Diagram (PORTA Example)
Positive
Edge
Detect
IOCAPx
RAx
IOC
Flag
Set/Reset
Logic
Write to IOCAFx flag
IOCIE
Negative
Edge
Detect
IOCANx
© 2021 Microchip Technology Inc.
IOC interrupt
to CPU core
From all other
IOCnFx flags
Preliminary Datasheet
DS40002213D-page 353
PIC18F27/47/57Q84
IOC - Interrupt-on-Change
20.2
Enabling the Module
In order for individual PORT pins to generate an interrupt, the IOC Interrupt Enable (IOCIE) bit of the Peripheral
Interrupt Enable (PIEx) register must be set. If the IOC Interrupt Enable bit is disabled, the edge detection on the pin
will still occur, but an interrupt will not be generated.
20.3
Individual Pin Configuration
A rising edge detector and a falling edge detector are present for each PORT pin. To enable a pin to detect a rising
edge, the associated bit of the IOCxP register must be set. To enable a pin to detect a falling edge, the associated bit
of the IOCxN register must be set. A PORT pin can be configured to detect rising and falling edges simultaneously by
setting both associated bits of the IOCxP and IOCxN registers, respectively.
20.4
Interrupt Flags
The bits located in the IOCxF registers are status flags that correspond to the interrupt-on-change pins of each port.
If an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and
an interrupt will be generated if the IOCIE bit is set. The IOCIF bit located in the corresponding Peripheral Interrupt
Request (PIRx) register, is all the IOCxF bits ORd together. The IOCIF bit is read-only. All of the IOCxF Status bits
must be cleared to clear the IOCIF bit.
20.5
Clearing Interrupt Flags
The individual status flags, (IOCxF register bits), will be cleared by resetting them to zero. If another edge is detected
during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the
value actually being written.
To ensure that no detected edge is lost while clearing flags, only AND operations masking out known changed bits
must be performed. The following sequence is an example of clearing an IOC interrupt flag using this method.
Example 20-1. Clearing Interrupt Flags
(PORTA Example)
MOVLW
XORWF
ANDWF
20.6
0xff
IOCAF, W
IOCAF, F
Operation in Sleep
An interrupt-on-change event will wake the device from Sleep mode, if the IOCIE bit is set. If an edge is detected
while in Sleep mode, the IOCxF register will be updated prior to the first instruction executed out of Sleep.
20.7
Register Definitions: Interrupt-on-Change Control
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 354
PIC18F27/47/57Q84
IOC - Interrupt-on-Change
20.7.1
IOCxF
Name:
IOCxF
Interrupt-on-Change Flag Register
Bit
Access
Reset
7
IOCxF7
R/W/HS
0
6
IOCxF6
R/W/HS
0
5
IOCxF5
R/W/HS
0
4
IOCxF4
R/W/HS
0
3
IOCxF3
R/W/HS
0
2
IOCxF2
R/W/HS
0
1
IOCxF1
R/W/HS
0
0
IOCxF0
R/W/HS
0
Bits 0, 1, 2, 3, 4, 5, 6, 7 – IOCxFn Interrupt-on-Change Flag
Value
Condition
Description
1
IOCxP[n] = 1
A positive edge was detected on the Rx[n] pin
1
IOCxN[n] = 1
A negative edge was detected on the Rx[n] pin
0
IOCxP[n] = x and IOCxN[n] = x No change was detected, or the user cleared the detected change
Important:
• If MCLRE = 1 or LVP = 1, the MCLR pin port functionality is disabled and IOC on that pin is not
available.
• Refer to the “Pin Allocation Table” for details about pins with configurable IOC per port.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 355
PIC18F27/47/57Q84
IOC - Interrupt-on-Change
20.7.2
IOCxN
Name:
IOCxN
Interrupt-on-Change Negative Edge Register Example
Bit
Access
Reset
7
IOCxN7
R/W
0
6
IOCxN6
R/W
0
5
IOCxN5
R/W
0
4
IOCxN4
R/W
0
3
IOCxN3
R/W
0
2
IOCxN2
R/W
0
1
IOCxN1
R/W
0
0
IOCxN0
R/W
0
Bits 0, 1, 2, 3, 4, 5, 6, 7 – IOCxNn Interrupt-on-Change Negative Edge Enable
Value
Description
1
Interrupt-on-Change enabled on the IOCx pin for a negative-going edge. Associated Status bit and
interrupt flag will be set upon detecting an edge.
0
Falling edge Interrupt-on-Change disabled for the associated pin
Important:
• If MCLRE = 1 or LVP = 1, the MCLR pin port functionality is disabled and IOC on that pin is not
available.
• Refer to the “Pin Allocation Table” for details about pins with configurable IOC per port.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 356
PIC18F27/47/57Q84
IOC - Interrupt-on-Change
20.7.3
IOCxP
Name:
IOCxP
Interrupt-on-Change Positive Edge Register
Bit
Access
Reset
7
IOCxP7
R/W
0
6
IOCxP6
R/W
0
5
IOCxP5
R/W
0
4
IOCxP4
R/W
0
3
IOCxP3
R/W
0
2
IOCxP2
R/W
0
1
IOCxP1
R/W
0
0
IOCxP0
R/W
0
Bits 0, 1, 2, 3, 4, 5, 6, 7 – IOCxPn Interrupt-on-Change Positive Edge Enable
Value
Description
1
Interrupt-on-Change enabled on the IOCx pin for a positive-going edge. Associated Status bit and
interrupt flag will be set upon detecting an edge.
0
Rising edge Interrupt-on-Change disabled for the associated pin.
Important:
• If MCLRE = 1 or LVP = 1, the MCLR pin port functionality is disabled and IOC on that pin is not
available.
• Refer to the “Pin Allocation Table” for details about pins with configurable IOC per port.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 357
PIC18F27/47/57Q84
IOC - Interrupt-on-Change
20.8
Address
0x00
...
0x0404
0x0405
0x0406
0x0407
0x0408
...
0x040C
0x040D
0x040E
0x040F
0x0410
...
0x0414
0x0415
0x0416
0x0417
0x0418
...
0x0424
0x0425
0x0426
0x0427
Register Summary: Interrupt-on-Change Control
Name
Bit Pos.
7
6
5
4
3
2
1
0
7:0
7:0
7:0
IOCAP7
IOCAN7
IOCAF7
IOCAP6
IOCAN6
IOCAF6
IOCAP5
IOCAN5
IOCAF5
IOCAP4
IOCAN4
IOCAF4
IOCAP3
IOCAN3
IOCAF3
IOCAP2
IOCAN2
IOCAF2
IOCAP1
IOCAN1
IOCAF1
IOCAP0
IOCAN0
IOCAF0
7:0
7:0
7:0
IOCBP7
IOCBN7
IOCBF7
IOCBP6
IOCBN6
IOCBF6
IOCBP5
IOCBN5
IOCBF5
IOCBP4
IOCBN4
IOCBF4
IOCBP3
IOCBN3
IOCBF3
IOCBP2
IOCBN2
IOCBF2
IOCBP1
IOCBN1
IOCBF1
IOCBP0
IOCBN0
IOCBF0
7:0
7:0
7:0
IOCCP7
IOCCN7
IOCCF7
IOCCP6
IOCCN6
IOCCF6
IOCCP5
IOCCN5
IOCCF5
IOCCP4
IOCCN4
IOCCF4
IOCCP3
IOCCN3
IOCCF3
IOCCP2
IOCCN2
IOCCF2
IOCCP1
IOCCN1
IOCCF1
IOCCP0
IOCCN0
IOCCF0
Reserved
IOCAP
IOCAN
IOCAF
Reserved
IOCBP
IOCBN
IOCBF
Reserved
IOCCP
IOCCN
IOCCF
Reserved
IOCEP
IOCEN
IOCEF
7:0
7:0
7:0
© 2021 Microchip Technology Inc.
IOCEP3
IOCEN3
IOCEF3
Preliminary Datasheet
DS40002213D-page 358
PIC18F27/47/57Q84
PPS - Peripheral Pin Select Module
21.
PPS - Peripheral Pin Select Module
21.1
Filename:
Overview
PPS Block Diagram.vsdx
Title:
The Peripheral
Pin Select (PPS)
module connects peripheral inputs and outputs to the device I/O pins. Only digital
Last Edit:
3/26/2019
signals areFirst
included
Used: in the selections.
Notes:
Important: All analog inputs and outputs remain fixed to their assigned pins and cannot be changed
through PPS.
Input and output selections are independent as shown in the figure below.
Figure 21-1. PPS Block Diagram
abcPPS
RA0PPS
RA0
Peripheral abc
RA0
Rxy
Peripheral xyz
Rxy
RxyPPS
xyzPPS
Input selections
21.2
Output selections
PPS Inputs
Each digital peripheral has a dedicated PPS Peripheral Input Selection (xxxPPS) register with which the input pin to
the peripheral is selected. Devices that have 20 leads or less (8/14/16/20) allow PPS routing to any I/O pin, while
devices with 28 leads or more allow PPS routing to I/Os contained within two ports (see the PPS Input Selection
Table below).
Important: The notation “xxx” in the generic register name is a placeholder for the peripheral identifier.
For example, xxx = T0CKI for the T0CKIPPS register.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 359
PIC18F27/47/57Q84
PPS - Peripheral Pin Select Module
Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level
regardless of peripheral PPS selection. If a pin also has analog functions associated, the ANSEL bit for that pin must
be cleared to enable the digital input buffer.
Table 21-1. PPS Input Selection Table
Peripheral
Interrupt 0
Interrupt 1
Interrupt 2
Timer0 Clock
Timer1 Clock
Timer1 Gate
Timer3 Clock
Timer3 Gate
Timer5 Clock
Timer5 Gate
Timer2 Input
Timer4 Input
Timer6 Input
Universal Timer Input 0
Universal Timer Input 1
CCP1
CCP2
CCP3
SMT1 Window
SMT1 Signal
PWM Input 0
PWM Input 1
PWM1 External Reset
Source
PWM2 External Reset
Source
PWM3 External Reset
Source
PWM4 External Reset
Source
CWG1
CWG2
CWG3
DSM1 Carrier Low
DSM1 Carrier High
DSM1 Source
CLCx Input 1
CLCx Input 2
CLCx Input 3
CLCx Input 4
CLCx Input 5
CLCx Input 6
INT0PPS
INT1PPS
INT2PPS
T0CKIPPS
T1CKIPPS
T1GPPS
T3CKIPPS
T3GPPS
T5CKIPPS
T5GPPS
T2INPPS
T4INPPS
T6INPPS
TUIN0PPS
TUIN1PPS
CCP1PPS
CCP2PPS
CCP3PPS
SMT1WINPPS
SMT1SIGPPS
PWMIN0PPS
PWMIN1PPS
PWM1ERSPPS
Default Pin
Selection at
POR
RB0
RB1
RB2
RA4
RC0
RB5
RC0
RC0
RC2
RB4
RC3
RC5
RB7
RC0
RB5
RC2
RC1
RB5
RC0
RC1
RC2
RC6
RC3
PWM2ERSPPS
PPS Input Register
Register Reset
Value at POR
28-Pin Devices 40-Pin Devices 48-Pin Devices
000
001
010
100
000
101
000
000
010
100
011
101
111
000
101
010
001
101
000
001
010
110
011
A
A
A
A
A
—
—
A
A
—
A
—
—
A
—
—
—
—
—
—
—
A
A
B
B
B
B
—
B
B
—
—
B
—
B
B
—
B
B
B
B
B
B
B
—
—
—
—
—
—
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
A
A
A
A
A
—
—
A
A
—
A
—
—
—
—
—
—
—
—
—
—
A
A
RC5
'b010 101
A
—
C
A — C — — —— C — E —
PWM3ERSPPS
RB7
'b001 111
—
B
C
— B — D —— B — D — —
PWM4ERSPPS
RC3
'b010 011
A
—
C
A — C — — —— C — E —
CWG1PPS
CWG2PPS
CWG3PPS
MD1CARLPPS
MD1CARHPPS
MD1SRCPPS
CLCIN0PPS
CLCIN1PPS
CLCIN2PPS
CLCIN3PPS
CLCIN4PPS
CLCIN5PPS
RB0
RB1
RB2
RA3
RA4
RA5
RA0
RA1
RB6
RB7
RA0
RA1
'b001
'b001
'b001
'b000
'b000
'b000
'b000
'b000
'b001
'b001
'b000
'b000
—
—
—
A
A
A
A
A
—
—
A
A
B
B
B
—
—
—
—
—
B
B
—
—
C
C
C
C
C
C
C
C
C
C
C
C
—
—
—
A
A
A
A
A
—
—
A
A
© 2021 Microchip Technology Inc.
'b001
'b001
'b001
'b000
'b010
'b001
'b010
'b010
'b010
'b001
'b010
'b010
'b001
'b010
'b001
'b010
'b010
'b001
'b010
'b010
'b010
'b010
'b010
Available Input Port
000
001
010
011
100
101
000
001
110
111
000
001
Preliminary Datasheet
B
B
B
B
—
B
B
—
—
B
—
B
B
—
B
B
B
B
B
B
B
—
—
B
B
B
—
—
—
—
—
B
B
—
—
—
—
—
—
C
C
C
C
C
—
C
C
—
C
C
C
C
—
C
C
C
—
C
—
—
—
—
—
—
C
C
—
—
C
C
—
—
—
—
—
—
—
—
—
D
—
—
D
—
—
—
—
D
—
—
—
—
—
D
D
D
D
D
D
—
—
D
D
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
E
—
—
—
—
—
—
—
E
—
—
—
—
—
—
—
—
—
—
—
—
—
A B ——— —
— B — D — —
— B ——— F
A ———— F
—— C — E —
— B C —— —
—— C — E —
A — C —— —
—— C — E —
— B — D — —
A — C —— —
— B C —— —
— B — D — —
—— C — E —
— B — — — F—
—— C —— F
—— C —— F
— B — D — —
—— C —— F
—— C —— F
—— C —— F
A ——— E —
A — C —
—
— B — D —
— B — D —
— B — D —
A —— D —
A —— D —
A —— D —
A — C ——
A — C ——
— B — D —
— B — D —
A — C ——
A — C ——
DS40002213D-page 360
—
—
—
—
—
—
—
—
—
—
—
—
PIC18F27/47/57Q84
PPS - Peripheral Pin Select Module
...........continued
Peripheral
CLCx Input 7
CLCx Input 8
ADC Conversion
Trigger
SPI1 Clock
SPI1 Data
SPI1 Client Select
SPI2 Clock
SPI2 Data
SPI2 Client Select
I2C1 Clock
I2C1 Data
UART1 Receive
UART1 Clear to Send
UART2 Receive
UART2 Clear to Send
UART3 Receive
UART3 Clear to Send
UART4 Receive
UART4 Clear to Send
UART5 Receive
UART5 Clear to Send
CAN Receive
CLCIN6PPS
CLCIN7PPS
ADACTPPS
Default Pin
Selection at
POR
RB6
RB7
RB4
SPI1SCKPPS
SPI1SDIPPS
SPI1SSPPS
SPI2SCKPPS
SPI2SDIPPS
SPI2SSPPS
I2C1SCLPPS(1)
I2C1SDAPPS(1)
U1RXPPS
U1CTSPPS
U2RXPPS
U2CTSPPS
U3RXPPS
U3CTSPPS
U4RXPPS
U4CTSPPS
U5RXPPS
U5CTSPPS
CANRXPPS
RC3
RC4
RA5
RB3
RB2
RA4
RC3
RC4
RC7
RC6
RB7
RB6
RA7
RA6
RB5
RB4
RA5
RA4
RB3
PPS Input Register
Register Reset
Value at POR
Available Input Port
28-Pin Devices 40-Pin Devices 48-Pin Devices
'b001 110
'b001 111
'b001 100
—
—
—
B
B
B
C
C
C
— B — D —— B — D — —
— B — D —— B — D — —
— B — D —— B — D — —
'b010
'b010
'b000
'b001
'b001
'b000
'b010
'b010
'b010
'b010
'b001
'b001
'b000
'b000
'b001
'b001
'b000
'b000
'b001
—
—
A
—
—
A
—
—
—
—
—
—
A
A
—
—
A
A
—
B
B
—
B
B
—
B
B
B
B
B
B
B
B
B
B
—
—
B
C
C
C
C
C
C
C
C
C
C
C
C
—
—
C
C
C
C
C
—
—
A
—
—
A
—
—
—
—
—
—
A
A
—
—
A
A
—
011
100
101
011
010
100
011
100
111
110
111
110
111
110
101
100
101
100
011
B
B
—
B
B
—
B
B
B
B
B
B
B
B
B
B
—
—
B
C
C
—
—
—
—
C
C
C
C
—
—
—
—
—
—
C
C
—
—
—
D
D
D
D
—
—
—
—
D
D
—
—
D
D
—
—
D
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— B C ——
— B C ——
A —— D —
— B — D —
— B — D —
A —— D —
— B C ——
— B C ——
—— C ——
—— C ——
— B — D —
— B — D —
A ————
A ————
— B — D —
— B — D —
A ————
A ————
— B — D —
Note:
1. Bidirectional pin. The corresponding output must select the same pin.
21.3
PPS Outputs
Each digital peripheral has a dedicated Pin Rxy Output Source Selection (RxyPPS) register with which the pin output
source is selected. With few exceptions, the port TRIS control associated with that pin retains control over the pin
output driver. Peripherals that control the pin output driver as part of the peripheral operation will override the TRIS
control as needed. The I2C module is an example of such a peripheral.
Important: The notation ‘Rxy’ is a place holder for the pin identifier. The ‘x’ holds the place of the PORT
letter and the ‘y’ holds the place of the bit number. For example, Rxy = RA0 for the RA0PPS register.
The PPS Output Selection Table below shows the output codes for each peripheral, as well as the available Port
selections.
Table 21-2. PPS Output Selection Table
RxyPPS
0x46
0x45
Output Source
CANTX
ADGRDB
© 2021 Microchip Technology Inc.
28-Pin Devices
—
B
C
A
—
C
Available Output Ports
40-Pin Devices
48-Pin Devices
— B — D — — B — D — —
A — C — — A — — — — F
Preliminary Datasheet
DS40002213D-page 361
—
—
—
—
—
—
—
—
F
F
—
—
F
F
—
—
F
F
—
PIC18F27/47/57Q84
PPS - Peripheral Pin Select Module
...........continued
RxyPPS
0x44
0x43
0x42
0x41
0x40
0x3F
0x3E - 0x3C
0x3B
0x3A
0x39
0x38
0x37
0x36
0x35
0x34
0x33
0x32
0x31
0x30
0x2F
0x2E
0x2D
0x2C
0x2B
0x2A
0x29
0x28
0x27
0x26
0x25
0x24
0x23
0x22
0x21
0x20
0x1F
0x1E
0x1D
0x1C
0x1B
0x1A
0x19
0x18
0x17
0x16
Output Source
ADGRDA
DSM1
CLKR
NCO3
NCO2
NCO1
Reserved
TU16B
TU16A
TMR0
I2C1 SDA(1)
I2C1 SCL(1)
SPI2 SS
SPI2 SDO
SPI2 SCK
SPI1 SS
SPI1 SDO
SPI1 SCK
C2OUT
C1OUT
UART5 RTS
UART5 TXDE
UART5 TX
UART4 RTS
UART4 TXDE
UART4 TX
UART3 RTS
UART3 TXDE
UART3 TX
UART2 RTS
UART2 TXDE
UART2 TX
UART1 RTS
UART1 TXDE
UART1 TX
PWM4S1P2_OUT
PWM4S1P1_OUT
PWM3S1P2_OUT
PWM3S1P1_OUT
PWM2S1P2_OUT
PWM2S1P1_OUT
PWM1S1P2_OUT
PWM1S1P1_OUT
CCP3
CCP2
© 2021 Microchip Technology Inc.
28-Pin Devices
A
—
C
A
—
C
—
B
C
—
B
C
—
B
C
A
—
C
—
—
—
—
B
C
—
B
C
—
B
C
—
B
C
—
B
C
A
—
C
—
B
C
—
B
C
A
—
C
—
B
C
—
B
C
A
—
C
A
—
C
—
B
C
—
B
C
—
B
C
A
B
—
A
B
—
A
B
—
A
B
—
A
B
—
A
B
—
—
B
C
—
B
C
—
B
C
—
B
C
—
B
C
—
B
C
A
—
C
A
—
C
—
B
C
—
B
C
—
B
C
—
B
C
—
B
C
—
B
C
—
B
C
—
B
C
Available Output Ports
40-Pin Devices
A — C — — A
A — — D — A
— B C — — —
— B — — E —
— B — D — —
A — — D — A
— — — — — —
— B — D — —
— B C — — —
— B C — — —
— B C — — —
— B C — — —
A — — D — A
— B — D — —
— B — D — —
A — — D — A
— B C — — —
— B C — — —
A — — — E A
A — — D — A
— B C — — —
— B C — — —
— B C — — —
A — — D — A
A — — D — A
A — — D — A
A B — — — A
A B — — — A
A B — — — A
— B — D — —
— B — D — —
— B — D — —
— B C — — —
— B C — — —
— B C — — —
A — — D — A
A — C — — —
— B — D — —
— B — D — —
— B — D — —
— B — D — —
— B C — — —
— B C — — —
— B — D — —
— B C — — —
Preliminary Datasheet
48-Pin Devices
— — — —
— — D —
B — — E
B — — E
B — D —
— — D —
— — — —
B — D —
— C — —
— C — —
B C — —
B C — —
— — D —
B — D —
B — D —
— — D —
B C — —
B C — —
— — — E
— — D —
— C — —
— C — —
— C — —
— — D —
— — D —
— — D —
— — — —
— — — —
— — — —
B — D —
B — D —
B — D —
— C — —
— C — —
— C — —
— — D —
— C — —
B — D —
B — D —
B — D —
B — D —
— C — —
— C — —
B — D —
— C — —
F
—
—
—
—
—
—
—
F
F
—
—
—
—
—
—
—
—
—
—
F
F
F
—
—
—
F
F
F
—
—
—
F
F
F
—
F
—
—
—
—
F
F
—
F
DS40002213D-page 362
PIC18F27/47/57Q84
PPS - Peripheral Pin Select Module
...........continued
RxyPPS
Output Source
0x15
0x14
0x13
0x12
0x11
0x10
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
CCP1
CWG3D
CWG3C
CWG3B
CWG3A
CWG2D
CWG2C
CWG2B
CWG2A
CWG1D
CWG1C
CWG1B
CWG1A
CLC8OUT
CLC7OUT
CLC6OUT
CLC5OUT
CLC4OUT
CLC3OUT
CLC2OUT
CLC1OUT
LATxy
28-Pin Devices
—
B
C
A
—
C
A
—
C
A
—
C
—
B
C
—
B
C
—
B
C
—
B
C
—
B
C
—
B
C
—
B
C
—
B
C
—
B
C
—
B
C
—
B
C
A
—
C
A
—
C
—
B
C
—
B
C
A
—
C
A
—
C
A
B
C
Available Output Ports
40-Pin Devices
— B C — — —
A — — D — A
A — — D — A
A — — — E A
— B C — — —
— B — D — —
— B — D — —
— B — D — —
— B C — — —
— B — D — —
— B — D — —
— B — D — —
— B C — — —
— B — D — —
— B — D — —
A — C — — A
A — C — — A
— B — D — —
— B — D — —
A — C — — A
A — C — — A
A B C D E A
48-Pin Devices
— C — —
— — D —
— — D —
— — — E
B C — —
B — D —
B — D —
B — D —
B C — —
B — D —
B — D —
B — D —
B C — —
B — D —
B — D —
— — — —
— — — —
B — D —
B — D —
— — — —
— — — —
B C D E
F
—
—
—
—
—
—
—
—
—
—
—
—
—
—
F
F
—
—
F
F
F
Note:
1. Bidirectional pin. The corresponding input must select the same pin.
21.4
Bidirectional Pins
PPS selections for peripherals with bidirectional signals on a single pin must be made so that the PPS input and PPS
output select the same pin. The I2C Serial Clock (SCL) and Serial Data (SDA) are examples of such pins.
Important: The I2C default pins, and a limited number of other alternate pins, are I2C and SMBus
compatible. SDA and SCL signals can be routed to any pin; however, pins without I2C compatibility will
operate at standard TTL/ST logic levels as selected by the port’s INLVL register.
21.5
PPS Lock
The PPS module provides an extra layer of protection to prevent inadvertent changes to the PPS selection registers.
The PPSLOCKED bit is used in combination with specific code execution blocks to lock/unlock the PPS selection
registers.
Important: The PPSLOCKED bit is clear by default (PPSLOCKED = 0), which allows the PPS selection
registers to be modified without an unlock sequence.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 363
PIC18F27/47/57Q84
PPS - Peripheral Pin Select Module
PPS selection registers are locked when the PPSLOCKED bit is set (PPSLOCKED = 1). Setting the PPSLOCKED bit
requires a specific lock sequence as shown in the examples below in both C and assembly languages.
PPS selection registers are unlocked when the PPSLOCKED bit is clear (PPSLOCKED = 0). Clearing the
PPSLOCKED bit requires a specific unlock sequence as shown in the examples below in both C and assembly
languages.
Important: All interrupts must be disabled before starting the lock/unlock sequence to ensure proper
execution.
Example 21-1. PPS Lock Sequence (Assembly language)
; suspend interrupts
BCF
INTCON0,GIE
BANKSEL PPSLOCK
; required sequence, next 5 instructions
MOVLW
0x55
MOVWF
PPSLOCK
MOVLW
0xAA
MOVWF
PPSLOCK
; Set PPSLOCKED bit
BSF
PPSLOCK,PPSLOCKED
; restore interrupts
BSF
INTCON0,GIE
Example 21-2. PPS Lock Sequence (C language)
INTCON0bits.GIE = 0;
PPSLOCK = 0x55;
PPSLOCK = 0xAA;
PPSLOCKbits.PPSLOCKED = 1;
INTCON0bits.GIE = 1;
//Suspend interrupts
//Required sequence
//Required sequence
//Set PPSLOCKED bit
//Restore interrupts
Example 21-3. PPS Unlock Sequence (Assembly language)
; suspend interrupts
BCF
INTCON0,GIE
BANKSEL PPSLOCK
; required sequence, next 5 instructions
MOVLW
0x55
MOVWF
PPSLOCK
MOVLW
0xAA
MOVWF
PPSLOCK
; Clear PPSLOCKED bit
BCF
PPSLOCK,PPSLOCKED
; restore interrupts
BSF
INTCON0,GIE
Example 21-4. PPS Unlock Sequence (C language)
INTCON0bits.GIE = 0;
PPSLOCK = 0x55;
© 2021 Microchip Technology Inc.
//Suspend interrupts
//Required sequence
Preliminary Datasheet
DS40002213D-page 364
PIC18F27/47/57Q84
PPS - Peripheral Pin Select Module
PPSLOCK = 0xAA;
PPSLOCKbits.PPSLOCKED = 0;
INTCON0bits.GIE = 1;
21.5.1
//Required sequence
//Clear PPSLOCKED bit
//Restore interrupts
PPS One-Way Lock
The PPS1WAY Configuration bit can also be used to prevent inadvertent modification to the PPS selection registers.
When the PPS1WAY bit is set (PPS1WAY = 1), the PPSLOCKED bit can only be set one time after a device Reset.
Once the PPSLOCKED bit has been set, it cannot be cleared again unless a device Reset is executed.
When the PPS1WAY bit is clear (PPS1WAY = 0), the PPSLOCKED bit can be set or cleared as needed; however, the
PPS lock/unlock sequences must be executed.
21.6
Operation During Sleep
PPS input and output selections are unaffected by Sleep.
21.7
Effects of a Reset
A device Power-on Reset (POR) or Brown-out Reset (BOR) returns all PPS input selection registers to their default
values, and clears all PPS output selection registers. All other Resets leave the selections unchanged. Default input
selections are shown in the PPS input register details table. The PPSLOCKED bit is cleared in all Reset conditions.
21.8
Register Definitions: Peripheral Pin Select (PPS)
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 365
PIC18F27/47/57Q84
PPS - Peripheral Pin Select Module
21.8.1
xxxPPS
Name:
xxxPPS
Peripheral Input Selection Register
Bit
7
6
Access
Reset
5
R/W
m
4
PORT[2:0]
R/W
m
3
2
R/W
m
R/W
m
1
PIN[2:0]
R/W
m
0
R/W
m
Bits 5:3 – PORT[2:0] Peripheral Input PORT Selection(1)
See the PPS Input Selection Table for the list of available Ports and default pin locations.
Reset States: POR = mmm
All other Resets = uuu
Value
Description
101
PORTF
100
PORTE
011
PORTD
010
PORTC
001
PORTB
000
PORTA
Bits 2:0 – PIN[2:0] Peripheral Input PORT Pin Selection(2)
Reset States: POR = mmm
All other Resets = uuu
Value
Description
111
Peripheral input is from PORTx Pin 7 (Rx7)
110
Peripheral input is from PORTx Pin 6 (Rx6)
101
Peripheral input is from PORTx Pin 5 (Rx5)
100
Peripheral input is from PORTx Pin 4 (Rx4)
011
Peripheral input is from PORTx Pin 3 (Rx3)
010
Peripheral input is from PORTx Pin 2 (Rx2)
001
Peripheral input is from PORTx Pin 1 (Rx1)
000
Peripheral input is from PORTx Pin 0 (Rx0)
Notes:
1. The Reset value ‘m’ is determined by device default locations for that input.
2. Refer to the Pin Allocation Table for details about available pins per port.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 366
PIC18F27/47/57Q84
PPS - Peripheral Pin Select Module
21.8.2
RxyPPS
Name:
RxyPPS
Pin Rxy Output Source Selection Register
Bit
7
6
Access
Reset
5
4
R/W
0
R/W
0
3
2
RxyPPS[5:0]
R/W
R/W
0
0
1
0
R/W
0
R/W
0
Bits 5:0 – RxyPPS[5:0] Pin Rxy Output Source Selection
See the PPS Output Selection Table for the list of RxyPPS Output Source codes
Reset States: POR = 0000000
All other Resets = uuuuuuu
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 367
PIC18F27/47/57Q84
PPS - Peripheral Pin Select Module
21.8.3
PPSLOCK
Name:
PPSLOCK
PPS Lock Register
Bit
7
6
5
4
3
Access
Reset
2
1
0
PPSLOCKED
R/W
0
Bit 0 – PPSLOCKED PPS Locked
Reset States: POR = 0
All other Resets = 0
Value
Description
1
PPS is locked. PPS selections cannot be changed. Writes to any PPS register are ignored.
0
PPS is not locked. PPS selections can be changed, but may require the PPS lock/unlock sequence.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 368
PIC18F27/47/57Q84
PPS - Peripheral Pin Select Module
21.9
Address
0x00
...
0x01FF
0x0200
0x0201
0x0202
0x0203
0x0204
0x0205
0x0206
0x0207
0x0208
0x0209
0x020A
0x020B
0x020C
0x020D
0x020E
0x020F
0x0210
0x0211
0x0212
0x0213
0x0214
0x0215
0x0216
0x0217
0x0218
0x0219
0x021A
0x021B
0x021C
0x021D
0x021E
0x021F
0x0220
0x0221
0x0222
0x0223
0x0224
...
0x0228
0x0229
0x022A
0x022B
0x022C
0x022D
0x022E
0x022F
0x0230
0x0231
...
0x023C
0x023D
0x023E
0x023F
Register Summary: Peripheral Pin Select Module
Name
Bit Pos.
7
6
5
4
3
2
1
0
Reserved
PPSLOCK
RA0PPS
RA1PPS
RA2PPS
RA3PPS
RA4PPS
RA5PPS
RA6PPS
RA7PPS
RB0PPS
RB1PPS
RB2PPS
RB3PPS
RB4PPS
RB5PPS
RB6PPS
RB7PPS
RC0PPS
RC1PPS
RC2PPS
RC3PPS
RC4PPS
RC5PPS
RC6PPS
RC7PPS
RD0PPS
RD1PPS
RD2PPS
RD3PPS
RD4PPS
RD5PPS
RD6PPS
RD7PPS
RE0PPS
RE1PPS
RE2PPS
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
RA0PPS[6:0]
RA1PPS[6:0]
RA2PPS[6:0]
RA3PPS[6:0]
RA4PPS[6:0]
RA5PPS[6:0]
RA6PPS[6:0]
RA7PPS[6:0]
RB0PPS[6:0]
RB1PPS[6:0]
RB2PPS[6:0]
RB3PPS[6:0]
RB4PPS[6:0]
RB5PPS[6:0]
RB6PPS[6:0]
RB7PPS[6:0]
RC0PPS[6:0]
RC1PPS[6:0]
RC2PPS[6:0]
RC3PPS[6:0]
RC4PPS[6:0]
RC5PPS[6:0]
RC6PPS[6:0]
RC7PPS[6:0]
RD0PPS[6:0]
RD1PPS[6:0]
RD2PPS[6:0]
RD3PPS[6:0]
RD4PPS[6:0]
RD5PPS[6:0]
RD6PPS[6:0]
RD7PPS[6:0]
RE0PPS[6:0]
RE1PPS[6:0]
RE2PPS[6:0]
PPSLOCKED
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
RF0PPS[6:0]
RF1PPS[6:0]
RF2PPS[6:0]
RF3PPS[6:0]
RF4PPS[6:0]
RF5PPS[6:0]
RF6PPS[6:0]
RF7PPS[6:0]
Reserved
RF0PPS
RF1PPS
RF2PPS
RF3PPS
RF4PPS
RF5PPS
RF6PPS
RF7PPS
Reserved
CANRXPPS
INT0PPS
INT1PPS
7:0
7:0
7:0
© 2021 Microchip Technology Inc.
PORT[2:0]
PORT
PORT[1:0]
Preliminary Datasheet
PIN[2:0]
PIN[2:0]
PIN[2:0]
DS40002213D-page 369
PIC18F27/47/57Q84
PPS - Peripheral Pin Select Module
...........continued
Address
Name
Bit Pos.
7
6
5
4
3
2
1
0x0240
0x0241
INT2PPS
T0CKIPPS
7:0
7:0
PORT[2:0]
PORT[2:0]
PIN[2:0]
PIN[2:0]
0x0242
0x0243
0x0244
0x0245
0x0246
0x0247
0x0248
0x0249
0x024A
0x024B
...
0x024C
0x024D
0x024E
0x024F
0x0250
0x0251
0x0252
0x0253
0x0254
0x0255
0x0256
0x0257
0x0258
0x0259
0x025A
0x025B
0x025C
0x025D
0x025E
0x025F
0x0260
0x0261
0x0262
0x0263
0x0264
0x0265
0x0266
0x0267
0x0268
0x0269
0x026A
0x026B
0x026C
0x026D
0x026E
0x026F
0x0270
0x0271
0x0272
0x0273
0x0274
0x0275
0x0276
0x0277
0x0278
0x0279
T1CKIPPS
T1GPPS
T3CKIPPS
T3GPPS
T5CKIPPS
T5GPPS
T2INPPS
T4INPPS
T6INPPS
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
PORT[2:0]
PORT[1:0]
PORT[2:0]
PORT[1:0]
PORT[2:0]
PORT[1:0]
PORT[1:0]
PORT[1:0]
PORT[1:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
7:0
7:0
7:0
7:0
7:0
PORT[2:0]
PORT[2:0]
PORT[2:0]
PORT[2:0]
PORT[1:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
PORT[1:0]
PORT[2:0]
PORT[1:0]
PORT[2:0]
PORT[2:0]
PORT[2:0]
PORT[2:0]
PORT[2:0]
PORT[1:0]
PORT[1:0]
PORT[1:0]
PORT[1:0]
PORT[1:0]
PORT[1:0]
PORT[1:0]
PORT[1:0]
PORT[1:0]
PORT[1:0]
PORT[1:0]
PORT[1:0]
PORT[1:0]
PORT[1:0]
PORT[1:0]
PORT[1:0]
PORT[1:0]
PORT[1:0]
PORT[1:0]
PORT[1:0]
PORT[1:0]
PORT[1:0]
PORT[1:0]
PORT[2:0]
PORT[2:0]
PORT[1:0]
PORT[1:0]
PORT[2:0]
PORT[2:0]
PORT[1:0]
PORT[1:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
PIN[2:0]
0
Reserved
TUIN0PPS
TUIN1PPS
CCP1PPS
CCP2PPS
CCP3PPS
Reserved
PWM1ERSPPS
PWM2ERSPPS
PWM3ERSPPS
PWM4ERSPPS
PWMIN0PPS
PWMIN1PPS
SMT1WINPPS
SMT1SIGPPS
CWG1PPS
CWG2PPS
CWG3PPS
MD1CARLPPS
MD1CARHPPS
MD1SRCPPS
CLCIN0PPS
CLCIN1PPS
CLCIN2PPS
CLCIN3PPS
CLCIN4PPS
CLCIN5PPS
CLCIN6PPS
CLCIN7PPS
ADACTPPS
SPI1SCKPPS
SPI1SDIPPS
SPI1SSPPS
SPI2SCKPPS
SPI2SDIPPS
SPI2SSPPS
I2C1SDAPPS
I2C1SCLPPS
U1RXPPS
U1CTSPPS
U2RXPPS
U2CTSPPS
U3RXPPS
U3CTSPPS
U4RXPPS
U4CTSPPS
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 370
PIC18F27/47/57Q84
PPS - Peripheral Pin Select Module
...........continued
Address
Name
Bit Pos.
0x027A
0x027B
U5RXPPS
U5CTSPPS
7:0
7:0
7
© 2021 Microchip Technology Inc.
6
5
4
PORT[2:0]
PORT[2:0]
Preliminary Datasheet
3
2
1
0
PIN[2:0]
PIN[2:0]
DS40002213D-page 371
PIC18F27/47/57Q84
PPS - Peripheral Pin Select Module
21.9.1
CANRXPPS
Name:
Address:
CANRXPPS
0x23D
CAN FD Receive PPS Register
Bit
7
6
Access
Reset
5
R/W
0
4
PORT[2:0]
R/W
0
3
2
R/W
0
R/W
0
1
PIN[2:0]
R/W
0
0
R/W
0
Bits 5:3 – PORT[2:0] CANRX Input PORT Selection bits
Bits 2:0 – PIN[2:0] ADACT Input PORT Pin Selection bits
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
CLC - Configurable Logic Cell
CLC - Configurable Logic Cell
The Configurable Logic Cell (CLC) module provides programmable logic that operates outside the speed limitations
of software execution. The logic cell takes up to 256 input signals and, through the use of configurable gates, reduces
those inputs to four logic lines that drive one of eight selectable single-output logic functions.
Input sources are a combination of the following:
• I/O pins
• Internal clocks
• Peripherals
• Register bits
The output can be directed internally to peripherals and to an output pin.
The following figure is a simplified diagram showing signal flow through the CLC. Possible configurations include:
• Combinatorial Logic
– AND
– NAND
– AND-OR
– AND-OR-INVERT
– OR-XOR
– OR-XNOR
• Latches
– SR
– Clocked D with Set and Reset
– Transparent D with Set and Reset
Figure 22-1. CLC Simplified Block Diagram
D
OUT
CLCxOUT
Q
Q1
LCx_in[0]
LCx_in[1]
LCx_in[2]
.
.
.
LCx_in[n-2]
LCx_in[n-1]
LCx_in[n]
CLCx_out
Input Data Selection Gates(1)
22.
EN
lcx g1
lcx g2
lcx g3
to Peripherals
RxyPPS
Logic
lcxq
Function
PPS
CLCx
(2)
lcx g4
POL
MODE
TRIS
Interrupt
det
INTP
INTN
set bit
CLCxIF
Interrupt
det
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 373
PIC18F27/47/57Q84
CLC - Configurable Logic Cell
Notes:
1. See Figure 22-2 for input data selection and gating.
2. See Figure 22-3 for programmable logic functions.
22.1
CLC Setup
Programming the CLC module is performed by configuring the four stages in the logic signal flow. The four stages
are:
• Data selection
• Data gating
• Logic function selection
• Output polarity
Each stage is set up at run time by writing to the corresponding CLC Special Function Registers. This has the added
advantage of permitting logic reconfiguration on-the-fly during program execution.
22.1.1
Data Selection
Data inputs are selected with CLCnSEL0 through CLCnSEL3 registers.
Important: Data selections are undefined at power-up.
Depending on the number of bits implemented in the CLCnSELy registers, there can be as many as 256 sources
available as inputs to the configurable logic. Four multiplexers are used to independently select these inputs to pass
on to the next stage as indicated on the left side of the following diagram.
Data inputs in the figure are identified by a generic numbered input name.
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Preliminary Datasheet
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PIC18F27/47/57Q84
CLC - Configurable Logic Cell
Figure 22-2. Input Data Selection and Gating
Data Selection
LCx_in[0]
Data GATE 1
G1D1T
d1T
G1D1N
d1N
G1D2T
LCx_in[n]
G1D2N
D1S
lcxg1
G1D3T
LCx_in[0]
d2T
d2N
LCx_in[n]
G1POL
G1D3N
G1D4T
G1D4N
D2S
LCx_in[0]
Data GATE 2
d3T
lcxg2
d3N
(Same as Data GATE 1)
LCx_in[n]
D3S
Data GATE 3
LCx_in[0]
lcxg3
(Same as Data GATE 1)
d4T
d4N
Data GATE 4
LCx_in[n]
lcxg4
D4S
(Same as Data GATE 1)
Note: are
All undefined
controls are
undefined at power up
Note: All controls
at power-up
The CLC Input Selection table correlates the generic input name to the actual signal for each CLC module. The table
column labeled ‘DyS Value’ indicates the MUX selection code for the selected data input. DyS is an abbreviation for
the MUX select input codes, D1S through D4S, where ‘y’ is the gate number.
22.1.2
Data Gating
Outputs from the input multiplexers are directed to the desired logic function input through the data gating stage.
Each data gate can direct any combination of the four selected inputs.
The gate stage is more than just signal direction. The gate can be configured to direct each input signal as inverted or
noninverted data. Directed signals are ANDed together in each gate. The output of each gate can be inverted before
going on to the logic function stage.
The gating is in essence a 1-to-4 input AND/NAND/OR/ NOR gate. When every input is inverted and the output is
inverted, the gate is an AND of all enabled data inputs. When the inputs and output are not inverted, the gate is an
OR or all enabled inputs.
Table 22-1 summarizes the basic logic that can be obtained in gate 1 by using the gate logic select bits. The table
shows the logic of four input variables, but each gate can be configured to use less than four. If no inputs are
selected, the output will be ‘0’ or ‘1’, depending on the gate output polarity bit.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 375
PIC18F27/47/57Q84
CLC - Configurable Logic Cell
Table 22-1. Data Gating Logic
CLCnGLSy
0x55
0x55
0xAA
0xAA
0x00
0x00
GyPOL
1
0
1
0
0
1
Gate Logic
AND
NAND
NOR
OR
Logic 0
Logic 1
It is possible (but not recommended) to select both the true and negated values of an input. When this is done, the
gate output is ‘0’, regardless of the other inputs, but may emit logic glitches (transient-induced pulses). If the output of
the channel must be ‘0’ or ‘1’, the recommended method is to set all gate bits to ‘0’ and use the gate polarity bit to set
the desired level.
Data gating is configured with the logic gate select registers as follows:
• Gate 1: CLCnGLS0
• Gate 2: CLCnGLS1
• Gate 3: CLCnGLS2
• Gate 4: CLCnGLS3
Note: Register number suffixes are different than the gate numbers because other variations of this module have
multiple gate selections in the same register.
Data gating is indicated in the right side of Figure 22-2. Only one gate is shown in detail. The remaining three gates
are configured identically with the exception that the data enables correspond to the enables for that gate.
22.1.3
Logic Function
There are eight available logic functions including:
•
•
•
•
•
•
•
•
AND-OR
OR-XOR
AND
SR Latch
D Flip-Flop with Set and Reset
D Flip-Flop with Reset
J-K Flip-Flop with Reset
Transparent Latch with Set and Reset
Logic functions are shown in the following diagram. Each logic function has four inputs and one output. The four
inputs are the four data gate outputs of the previous stage. The output is fed to the inversion stage and from there to
other peripherals, an output pin, and back to the CLC itself.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 376
PIC18F27/47/57Q84
CLC - Configurable Logic Cell
Figure 22-3. Programmable Logic Functions
Rev. 10-000122B
9/13/2016
AND-OR
OR-XOR
lcxg1
lcxg1
lcxg2
lcxg2
lcxq
lcxq
lcxg3
lcxg3
lcxg4
lcxg4
MODE = 000
MODE = 001
4-input AND
S-R Latch
lcxg1
lcxg1
S
lcxg2
lcxg2
lcxg3
lcxg4
Q
lcxq
R
lcxg4
MODE = 010
MODE = 011
1-Input D Flip-Flop with S and R
2-Input D Flip-Flop with R
lcxg4
D
lcxg1
S
Q
lcxq
lcxg4
D
lcxg2
lcxg1
R
lcxg3
lcxg2
lcxq
lcxq
lcxg3
lcxg2
Q
R
lcxg3
MODE = 100
MODE = 101
J-K Flip-Flop with R
1-Input Transparent Latch with S and R
J
Q
lcxq
lcxg4
lcxg2
D
lcxg3
LE
S
Q
lcxq
lcxg1
lcxg4
K
R
lcxg3
MODE = 110
22.1.4
R
lcxg1
MODE = 111
Output Polarity
The last stage in the Configurable Logic Cell is the output polarity. Setting the POL bit inverts the output signal from
the logic stage. Changing the polarity while the interrupts are enabled will cause an interrupt for the resulting output
transition.
22.2
CLC Interrupts
An interrupt will be generated upon a change in the output value of the CLCx when the appropriate interrupt enables
are set. A rising edge detector and a falling edge detector are present in each CLC for this purpose.
The CLCxIF bit of the associated PIR register will be set when either edge detector is triggered and its associated
enable bit is set. The INTP bit enables rising edge interrupts and the INTN bit enables falling edge interrupts.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 377
PIC18F27/47/57Q84
CLC - Configurable Logic Cell
To fully enable the interrupt, set the following bits:
• CLCxIE bit of the respective PIE register
• INTP bit (for a rising edge detection)
• INTN bit (for a falling edge detection)
If priority interrupts are not used:
1. Clear the IPEN bit of the INTCON register.
2. Set the GIE bit of the INTCON register.
3. Set the GIEL bit of the INTCON register.
If the CLC is a high priority interrupt:
1. Set the IPEN bit of the INTCON register.
2. Set the CLCxIP bit of the respective IPR register.
3. Set the GIEH bit of the INTCON register.
If the CLC is a low priority interrupt:
1. Set the IPEN bit of the INTCON register.
2. Clear the CLCxIP bit of the respective IPR register.
3. Set the GIEL bit of the INTCON register.
The CLCxIF bit of the respective PIR register must be cleared in software as part of the interrupt service. If another
edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence.
22.3
Effects of a Reset
The CLCnCON register is cleared to ‘0’ as the result of a Reset. All other selection and gating values remain
unchanged.
22.4
Output Mirror Copies
Mirror copies of all CLCxOUT bits are contained in the CLCDATA register. Reading this register reads the outputs
of all CLCs simultaneously. This prevents any reading skew introduced by testing or reading the OUT bits in the
individual CLCnCON registers.
22.5
Operation During Sleep
The CLC module operates independently from the system clock and will continue to run during Sleep, provided that
the input sources selected remain Active.
The HFINTOSC remains Active during Sleep when the CLC module is enabled and the HFINTOSC is selected as an
input source, regardless of the system clock source selected.
In other words, if the HFINTOSC is simultaneously selected as both the system clock and as a CLC input source
then, when the CLC is enabled, the CPU will go Idle during Sleep, but the CLC will continue to operate and the
HFINTOSC will remain Active. This will have a direct effect on the Sleep mode current.
22.6
CLC Setup Steps
These steps need to be followed when setting up the CLC:
1.
2.
3.
4.
Disable CLC by clearing the EN bit.
Select desired inputs using the CLCnSEL0 through the CLCnSEL3 registers.
Clear any ANSEL bits associated with CLC input pins.
Set all TRIS bits associated with inputs. However, a CLC input will also operate if the pin is configured as an
output, in which case the TRIS bits must be cleared.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 378
PIC18F27/47/57Q84
CLC - Configurable Logic Cell
5.
6.
7.
8.
Enable the chosen inputs through the four gates using the CLCnGLS0 through CLCnGLS3 registers.
Select the gate output polarities with the GyPOL bits.
Select the desired logic function with the MODE bits.
Select the desired polarity of the logic output with the POL bit. (This step may be combined with the previous
gate output polarity step).
9. If driving a device pin, configure the associated pin PPS control register and also clear the TRIS bit
corresponding to that output.
10. Configure the interrupts (optional). See CLC Interrupts.
11. Enable the CLC by setting the EN bit.
22.7
Register Overlay
All CLCs in this device share the same set of registers. Only one CLC instance is accessible at a time. The value
in the CLCSELECT register is one less than the selected CLC instance. For example, a CLCSELECT value of ‘0’
selects CLC1.
22.8
Register Definitions: Configurable Logic Cell
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Preliminary Datasheet
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PIC18F27/47/57Q84
CLC - Configurable Logic Cell
22.8.1
CLCSELECT
Name:
Address:
CLCSELECT
0x0D5
CLC Instance Selection Register
Selects which CLC instance is accessed by the CLC registers
Bit
7
6
5
4
3
Access
Reset
2
R/W
0
1
SLCT[2:0]
R/W
0
0
R/W
0
Bits 2:0 – SLCT[2:0] CLC instance selection
Value
Description
n
Shared CLC registers of instance n+1 are selected for read and write operations.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
CLC - Configurable Logic Cell
22.8.2
CLCnCON
Name:
Address:
CLCnCON
0x0D6
Configurable Logic Cell Control Register
Bit
Access
Reset
7
EN
R/W
0
6
5
OUT
R
0
4
INTP
R/W
0
3
INTN
R/W
0
2
R/W
0
1
MODE[2:0]
R/W
0
0
R/W
0
Bit 7 – EN CLC Enable
Value
Description
1
Configurable logic cell is enabled and mixing signals
0
Configurable logic cell is disabled and has logic zero output
Bit 5 – OUT Logic cell output data, after LCPOL. Sampled from CLCxOUT
Bit 4 – INTP Configurable Logic Cell Positive Edge Going Interrupt Enable
Value
Description
1
CLCxIF will be set when a rising edge occurs on CLCxOUT
0
Rising edges on CLCxOUT have no effect on CLCxIF
Bit 3 – INTN Configurable Logic Cell Negative Edge Going Interrupt Enable
Value
Description
1
CLCxIF will be set when a falling edge occurs on CLCxOUT
0
Falling edges on CLCxOUT have no effect on CLCxIF
Bits 2:0 – MODE[2:0] Configurable Logic Cell Functional Mode Selection
Value
Description
111
Cell is 1-input transparent latch with Set and Reset
110
Cell is J-K flip-flop with Reset
101
Cell is 2-input D flip-flop with Reset
100
Cell is 1-input D flip-flop with Set and Reset
011
Cell is SR latch
010
Cell is 4-input AND
001
Cell is OR-XOR
000
Cell is AND-OR
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
CLC - Configurable Logic Cell
22.8.3
CLCnPOL
Name:
Address:
CLCnPOL
0x0D7
Signal Polarity Control Register
Bit
Access
Reset
7
POL
R/W
0
6
5
4
3
G4POL
R/W
x
2
G3POL
R/W
x
1
G2POL
R/W
x
0
G1POL
R/W
x
Bit 7 – POL CLCxOUT Output Polarity Control
Value
Description
1
The output of the logic cell is inverted
0
The output of the logic cell is not inverted
Bits 0, 1, 2, 3 – GyPOL Gate Output Polarity Control
Reset States: POR/BOR = xxxx
All Other Resets = uuuu
Value
Description
1
The gate output is inverted when applied to the logic cell
0
The output of the gate is not inverted
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
CLC - Configurable Logic Cell
22.8.4
CLCnSEL0
Name:
Address:
CLCnSEL0
0x0D8
Generic CLCn Data 1 Select Register
Bit
7
6
5
4
3
2
1
0
R/W
x
R/W
x
R/W
x
R/W
x
D1S[7:0]
Access
Reset
R/W
x
R/W
x
R/W
x
R/W
x
Bits 7:0 – D1S[7:0] CLCn Data1 Input Selection
Table 22-2. CLC Input Selection
DyS
Input Source
DyS (cont.)
Input Source (cont.)
DyS (cont.)
Input Source (cont.)
[0] 0000 0000
CLCIN0PPS
[32] 0010 0000
CCP2
[64] 0100 0000
SPI1_SDO
[1] 0000 0001
CLCIN1PPS
[33] 0010 0001
CCP3
[65] 0100 0001
SPI1_SCK
[2] 0000 0010
CLCIN2PPS
[34] 0010 0010
PWM1S1P1_OUT
[66] 0100 0010
SPI1_SS
[3] 0000 0011
CLCIN3PPS
[35] 0010 0011
PWM1S1P2_OUT
[67] 0100 0011
SPI2_SDO
[4] 0000 0100
CLCIN4PPS
[36] 0010 0100
PWM2S1P1_OUT
[68] 0100 0100
SPI2_SCK
[5] 0000 0101
CLCIN5PPS
[37] 0010 0101
PWM2S1P2_OUT
[69] 0100 0101
SPI2_SS
[6] 0000 0110
CLCIN6PPS
[38] 0010 0110
PWM3S1P1_OUT
[70] 0100 0110
I2C_SCL
[7] 0000 0111
CLCIN7PPS
[39] 0010 0111
PWM3S1P2_OUT
[71] 0100 0111
I2C_SDA
[8] 0000 1000
FOSC
[40] 0010 1000
PWM4S1P1_OUT
[72] 0100 1000
CWG1A
[9] 0000 1001
HFINTOSC(1)
[41] 0010 1001
PWM4S1P2_OUT
[73] 0100 1001
CWG1B
[10] 0000 1010
LFINTOSC(1)
[42] 0010 1010
NCO1
[74] 0100 1010
CWG2A
[11] 0000 1011
MFINTOSC(1)
[43] 0010 1011
NCO2
[75] 0100 1011
CWG2B
[12] 0000 1100
MFINTOSC (32 kHz)(1)
[44] 0010 1100
NCO3
[76] 0100 1100
CWG3A
[13] 0000 1101
SFINTOSC (1 MHz)(1)
[45] 0010 1101
CMP1_OUT
[77] 0100 1101
CWG3B
[14] 0000 1110
SOSC(1)
[46] 0010 1110
CMP2_OUT
...
—
[15] 0000 1111
EXTOSC(1)
[47] 0010 1111
ZCD
...
—
[16] 0001 0000
ADCRC(1)
[48] 0011 0000
IOC
...
—
[17] 0001 0001
CLKR
[49] 0011 0001
DSM1
...
—
[18] 0001 0010
TMR0
[50] 0011 0010
HLVD_OUT
...
—
[19] 0001 0011
TMR1
[51] 0011 0011
CLC1
...
—
[20] 0001 0100
TMR2
[52] 0011 0100
CLC2
...
—
[21] 0001 0101
TMR3
[53] 0011 0101
CLC3
...
—
[22] 0001 0110
TMR4
[54] 0011 0110
CLC4
...
—
[23] 0001 0111
TMR5
[55] 0011 0111
CLC5
...
—
[24] 0001 1000
TMR6
[56] 0011 1000
CLC6
...
—
[25] 0001 1001
TU16A
[57] 0011 1001
CLC7
...
—
[26] 0001 1010
TU16B
[58] 0011 1010
CLC8
...
—
[27] 0001 1011
—
[59] 0011 1011
U1TX
...
—
[28] 0001 1100
—
[60] 0011 1100
U2TX
...
—
[29] 0001 1101
—
[61] 0011 1101
U3TX
...
—
[30] 0001 1110
SMT1
[62] 0011 1110
U4TX
...
—
[31] 0001 1111
CCP1
[63] 0011 1111
U5TX
[127] 0111 1111
—
Note:
1.
Requests clock.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 383
PIC18F27/47/57Q84
CLC - Configurable Logic Cell
Reset States: POR/BOR = xxxxxxxx
All Other Resets = uuuuuuuu
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 384
PIC18F27/47/57Q84
CLC - Configurable Logic Cell
22.8.5
CLCnSEL1
Name:
Address:
CLCnSEL1
0x0D9
Generic CLCn Data 1 Select Register
Bit
7
6
5
4
3
2
1
0
R/W
x
R/W
x
R/W
x
R/W
x
D2S[7:0]
Access
Reset
R/W
x
R/W
x
R/W
x
R/W
x
Bits 7:0 – D2S[7:0] CLCn Data2 Input Selection
Reset States: POR/BOR = xxxxxxxx
All Other Resets = uuuuuuuu
Value
Description
n
Refer to the CLC Input Selection table for input selections.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 385
PIC18F27/47/57Q84
CLC - Configurable Logic Cell
22.8.6
CLCnSEL2
Name:
Address:
CLCnSEL2
0x0DA
Generic CLCn Data 1 Select Register
Bit
7
6
5
4
3
2
1
0
R/W
x
R/W
x
R/W
x
R/W
x
D3S[7:0]
Access
Reset
R/W
x
R/W
x
R/W
x
R/W
x
Bits 7:0 – D3S[7:0] CLCn Data3 Input Selection
Reset States: POR/BOR = xxxxxxxx
All Other Resets = uuuuuuuu
Value
Description
n
Refer to the CLC Input Selection table for input selections.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 386
PIC18F27/47/57Q84
CLC - Configurable Logic Cell
22.8.7
CLCnSEL3
Name:
Address:
CLCnSEL3
0x0DB
Generic CLCn Data 4 Select Register
Bit
7
6
5
4
3
2
1
0
R/W
x
R/W
x
R/W
x
R/W
x
D4S[7:0]
Access
Reset
R/W
x
R/W
x
R/W
x
R/W
x
Bits 7:0 – D4S[7:0] CLCn Data4 Input Selection
Reset States: POR/BOR = xxxxxxxx
All Other Resets = uuuuuuuu
Value
Description
n
Refer to the CLC Input Selection table for input selections.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 387
PIC18F27/47/57Q84
CLC - Configurable Logic Cell
22.8.8
CLCnGLS0
Name:
Address:
CLCnGLS0
0x0DC
CLCn Gate1 Logic Select Register
Bit
Access
Reset
7
G1D4T
R/W
x
6
G1D4N
R/W
x
5
G1D3T
R/W
x
4
G1D3N
R/W
x
3
G1D2T
R/W
x
2
G1D2N
R/W
x
1
G1D1T
R/W
x
0
G1D1N
R/W
x
Bits 1, 3, 5, 7 – G1DyT dyT: Gate1 Data ‘y’ True (noninverted)
Reset States: POR/BOR = xxxx
All Other Resets = uuuu
Value
Description
1
dyT is gated into g1
0
dyT is not gated into g1
Bits 0, 2, 4, 6 – G1DyN dyN: Gate1 Data ‘y’ Negated (inverted)
Reset States: POR/BOR = xxxx
All Other Resets = uuuu
Value
Description
1
dyN is gated into g1
0
dyN is not gated into g1
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 388
PIC18F27/47/57Q84
CLC - Configurable Logic Cell
22.8.9
CLCnGLS1
Name:
Address:
CLCnGLS1
0x0DD
CLCn Gate2 Logic Select Register
Bit
Access
Reset
7
G2D4T
R/W
x
6
G2D4N
R/W
x
5
G2D3T
R/W
x
4
G2D3N
R/W
x
3
G2D2T
R/W
x
2
G2D2N
R/W
x
1
G2D1T
R/W
x
0
G2D1N
R/W
x
Bits 1, 3, 5, 7 – G2DyT dyT: Gate2 Data ‘y’ True (noninverted)
Reset States: POR/BOR = xxxx
All Other Resets = uuuu
Value
Description
1
dyT is gated into g2
0
dyT is not gated into g2
Bits 0, 2, 4, 6 – G2DyN dyN: Gate2 Data ‘y’ Negated (inverted)
Reset States: POR/BOR = xxxx
All Other Resets = uuuu
Value
Description
1
dyN is gated into g2
0
dyN is not gated into g2
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 389
PIC18F27/47/57Q84
CLC - Configurable Logic Cell
22.8.10 CLCnGLS2
Name:
Address:
CLCnGLS2
0x0DE
CLCn Gate3 Logic Select Register
Bit
Access
Reset
7
G3D4T
R/W
x
6
G3D4N
R/W
x
5
G3D3T
R/W
x
4
G3D3N
R/W
x
3
G3D2T
R/W
x
2
G3D2N
R/W
x
1
G3D1T
R/W
x
0
G3D1N
R/W
x
Bits 1, 3, 5, 7 – G3DyT dyT: Gate3 Data ‘y’ True (noninverted)
Reset States: POR/BOR = xxxx
All Other Resets = uuuu
Value
Description
1
dyT is gated into g3
0
dyT is not gated into g3
Bits 0, 2, 4, 6 – G3DyN dyN: Gate3 Data ‘y’ Negated (inverted)
Reset States: POR/BOR = xxxx
All Other Resets = uuuu
Value
Description
1
dyN is gated into g3
0
dyN is not gated into g3
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 390
PIC18F27/47/57Q84
CLC - Configurable Logic Cell
22.8.11 CLCnGLS3
Name:
Address:
CLCnGLS3
0x0DF
CLCn Gate4 Logic Select Register
Bit
Access
Reset
7
G4D4T
R/W
x
6
G4D4N
R/W
x
5
G4D3T
R/W
x
4
G4D3N
R/W
x
3
G4D2T
R/W
x
2
G4D2N
R/W
x
1
G4D1T
R/W
x
0
G4D1N
R/W
x
Bits 1, 3, 5, 7 – G4DyT dyT: Gate4 Data ‘y’ True (noninverted)
Reset States: POR/BOR = xxxx
All Other Resets = uuuu
Value
Description
1
dyT is gated into g4
0
dyT is not gated into g4
Bits 0, 2, 4, 6 – G4DyN dyN: Gate4 Data ‘y’ Negated (inverted)
Reset States: POR/BOR = xxxx
All Other Resets = uuuu
Value
Description
1
dyN is gated into g4
0
dyN is not gated into g4
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 391
PIC18F27/47/57Q84
CLC - Configurable Logic Cell
22.8.12 CLCDATA
Name:
Address:
CLCDATA
0x0D4
CLC Data Output Register
Mirror copy of CLC outputs
Bit
Access
Reset
7
CLC8OUT
R/W
0
6
CLC7OUT
R/W
0
5
CLC6OUT
R/W
0
4
CLC5OUT
R/W
0
3
CLC4OUT
R/W
0
2
CLC3OUT
R/W
0
1
CLC2OUT
R/W
0
0
CLC1OUT
R/W
0
Bits 0, 1, 2, 3, 4, 5, 6, 7 – CLCxOUT Mirror copy of CLCx_out
Value
Description
1
CLCx_out is 1
0
CLCx_out is 0
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 392
PIC18F27/47/57Q84
CLC - Configurable Logic Cell
22.9
Address
0x00
...
0xD3
0xD4
0xD5
0xD6
0xD7
0xD8
0xD9
0xDA
0xDB
0xDC
0xDD
0xDE
0xDF
Register Summary - CLC Control
Name
Bit Pos.
7
6
5
4
3
2
1
0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
CLC8OUT
CLC7OUT
CLC6OUT
CLC5OUT
CLC4OUT
CLC3OUT
CLC1OUT
OUT
INTP
G3POL
CLC2OUT
SLCT[2:0]
MODE[2:0]
G2POL
G1D2N
G2D2N
G3D2N
G4D2N
G1D1T
G2D1T
G3D1T
G4D1T
G1D1N
G2D1N
G3D1N
G4D1N
Reserved
CLCDATA
CLCSELECT
CLCnCON
CLCnPOL
CLCnSEL0
CLCnSEL1
CLCnSEL2
CLCnSEL3
CLCnGLS0
CLCnGLS1
CLCnGLS2
CLCnGLS3
EN
POL
G1D4T
G2D4T
G3D4T
G4D4T
© 2021 Microchip Technology Inc.
G1D4N
G2D4N
G3D4N
G4D4N
G1D3T
G2D3T
G3D3T
G4D3T
INTN
G4POL
D1S[7:0]
D2S[7:0]
D3S[7:0]
D4S[7:0]
G1D3N
G1D2T
G2D3N
G2D2T
G3D3N
G3D2T
G4D3N
G4D2T
Preliminary Datasheet
G1POL
DS40002213D-page 393
PIC18F27/47/57Q84
CLKREF - Reference Clock Output Module
23.
CLKREF - Reference Clock Output Module
The reference clock output module provides the ability to send a clock signal to the clock reference output pin
(CLKR). The reference clock output can be routed internally as an input signal for other peripherals, such as the
timers and CLCs.
The reference clock output module has the following features:
•
•
•
Selectable clock source using the CLKRCLK register
Programmable clock divider
Selectable duty cycle
The figure below shows the simplified block diagram of the clock reference module.
Figure 23-1. Clock Reference Block Diagram
Rev. 10-000261B
1/23/2019
DIV
EN
Counter Reset
Reference Clock Divider
128
See
CLKRCLK
Register
64
32
16
8
4
2
110
DC
RxyPPS
101
100
011
CLKR
Duty Cycle
PPS
010
001
To Peripherals
000
EN
CLK
111
Figure 23-2. Clock Reference Timing
Rev. 10-000264B
1/23/2019
P1
P2
CLKRCLK
EN
CLKR Output
DIV = 001
DC = 10
Duty Cycle
(50%)
CLKR Output
CLKRCLK/2
DIV = 001
DC = 01
Duty Cycle
(25%)
23.1
Clock Source
The clock source of the reference clock peripheral is selected with the CLK bits.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 394
PIC18F27/47/57Q84
CLKREF - Reference Clock Output Module
23.1.1
Clock Synchronization
The CLKR output signal is ensured to be glitch-free when the EN bit is set to start the module and enable the CLKR
output. When the reference clock output is disabled, the output signal will be disabled immediately.
23.2
Programmable Clock Divider
The module takes the clock input and divides it based on the value of the DIV bits.
The following configurations are available:
•
•
•
•
•
•
•
•
23.3
Base clock frequency value
Base clock frequency divided by 2
Base clock frequency divided by 4
Base clock frequency divided by 8
Base clock frequency divided by 16
Base clock frequency divided by 32
Base clock frequency divided by 64
Base clock frequency divided by 128
Selectable Duty Cycle
The DC bits are used to modify the duty cycle of the output clock. A duty cycle of 0%, 25%, 50%, or 75% can be
selected for all clock rates when the DIV value is not 0b000. When DIV = 0b000, the duty cycle defaults to 50% for
all values of DC except 0b00, in which case the duty cycle is 0% (constant low output).
Important: The DC value at Reset is 10. This makes the default duty cycle 50% and not 0%.
Important: Clock dividers and clock duty cycles can be changed while the module is enabled but doing
so may cause glitches to occur on the output. To avoid possible glitches, clock dividers and clock duty
cycles will be changed only when the EN bit is clear.
23.4
Operation in Sleep Mode
The reference clock module continues to operate and provide a signal output in Sleep for all clock source selections
except FOSC (CLK = 0).
23.5
Register Definitions: Reference Clock
Long bit name prefixes for the Reference Clock peripherals are shown in the following table. Refer to the “Long Bit
Names” section in the “Register and Bit Naming Conventions” chapter for more information.
Table 23-1.
Peripheral
Bit Name Prefix
CLKR
CLKR
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 395
PIC18F27/47/57Q84
CLKREF - Reference Clock Output Module
23.5.1
CLKRCON
Name:
Address:
CLKRCON
0x039
Reference Clock Control Register
Bit
Access
Reset
7
EN
R/W
0
6
5
4
3
2
R/W
0
R/W
0
DC[1:0]
R/W
1
1
DIV[2:0]
R/W
0
0
R/W
0
Bit 7 – EN Reference Clock Module Enable
Value
Description
1
Reference clock module enabled
0
Reference clock module is disabled
Bits 4:3 – DC[1:0] Reference Clock Duty Cycle(1)
Value
Description
11
Clock outputs duty cycle of 75%
10
Clock outputs duty cycle of 50%
01
Clock outputs duty cycle of 25%
00
Clock outputs duty cycle of 0%
Bits 2:0 – DIV[2:0] Reference Clock Divider
Value
Description
111
Base clock value divided by 128
110
Base clock value divided by 64
101
Base clock value divided by 32
100
Base clock value divided by 16
011
Base clock value divided by 8
010
Base clock value divided by 4
001
Base clock value divided by 2
000
Base clock value
Note:
1. Bits are valid for DIV ≥ 001. For DIV = 000, duty cycle is fixed at 50%.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 396
PIC18F27/47/57Q84
CLKREF - Reference Clock Output Module
23.5.2
CLKRCLK
Name:
Address:
CLKRCLK
0x03A
Clock Reference Clock Selection Register
Bit
7
6
Access
Reset
5
4
3
R/W
0
R/W
0
2
CLK[4:0]
R/W
0
1
0
R/W
0
R/W
0
Bits 4:0 – CLK[4:0] CLKR Clock Selection
Table 23-2. Clock Reference Module Clock Sources
CLK
Clock Source
11111-10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
Reserved
CLC8_OUT
CLC7_OUT
CLC6_OUT
CLC5_OUT
CLC4_OUT
CLC3_OUT
CLC2_OUT
CLC1_OUT
NCO3_OUT
NCO2_OUT
NCO1_OUT
EXTOSC
SOSC
MFINTOSC (32 kHz)
MFINTOSC (500 kHz)
LFINTOSC
HFINTOSC
FOSC
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 397
PIC18F27/47/57Q84
CLKREF - Reference Clock Output Module
23.6
Address
0x00
...
0x38
0x39
0x3A
Register Summary: Reference CLK
Name
Bit Pos.
7
7:0
7:0
EN
6
5
4
3
2
1
0
Reserved
CLKRCON
CLKRCLK
© 2021 Microchip Technology Inc.
DC[1:0]
DIV[2:0]
CLK[4:0]
Preliminary Datasheet
DS40002213D-page 398
PIC18F27/47/57Q84
TMR0 - Timer0 Module
24.
TMR0 - Timer0 Module
The Timer0 module has the following features:
•
•
•
•
•
•
•
•
•
8-bit timer with programmable period
16-bit timer
Selectable clock sources
Synchronous and asynchronous operation
Programmable prescaler (Independent of Watchdog Timer)
Programmable postscaler
Interrupt on match or overflow
Output on I/O pin (via PPS) or to other peripherals
Operation during Sleep
Figure 24-1. Timer0 Block Diagram
Rev. Tim er0 Blo
2/12/201 9
See T0CON1
Register
T0CKPS
Peripherals
TMR0
bod y
T0OUTPS
T0IF
1
Prescaler
SYNC
0
IN
OUT
TMR0
FOSC/4
T016BIT
T0ASYNC
PPS
T0_out
Postscaler
Q
D
T0CKIPPS
PPS
RxyPPS
CK Q
T0CS
16-bit TMR0 Body Diagram (T016BIT = 1)
8-bit TMR0 Body Diagram (T016BIT = 0)
IN
TMR0L
R
Clear
IN
TMR0L
Timer 0 High
Byte
OUT
8
Read TMR0L
COMPARATOR
OUT
Write TMR0L
T0_match
8
8
TMR0H
Timer 0 High
Byte
Latch
Enable
8
TMR0H
8
Internal Data Bus
24.1
Timer0 Operation
Timer0 can operate as either an 8-bit or 16-bit timer. The mode is selected with the MD16 bit.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 399
PIC18F27/47/57Q84
TMR0 - Timer0 Module
24.1.1
8-Bit Mode
In this mode, Timer0 increments on the rising edge of the selected clock source. A prescaler on the clock input gives
several prescale options (see prescaler control bits, CKPS). In this mode, as shown in Figure 24-1, a buffered version
of TMR0H is maintained.
This is compared with the value of TMR0L on each cycle of the selected clock source. When the two values match,
the following events occur:
• TMR0L is reset
• The contents of TMR0H are copied to the TMR0H buffer for next comparison
24.1.2
16-Bit Mode
In this mode, Timer0 increments on the rising edge of the selected clock source. A prescaler on the clock input gives
several prescale options (see prescaler control bits, CKPS). In this mode, TMR0H:TMR0L form the 16-bit timer value.
As shown in Figure 24-1, reads and writes of the TMR0H register are buffered. The TMR0H register is updated with
the contents of the high byte of Timer0 when the TMR0L register is read. Similarly, writing the TMR0L register causes
a transfer of the TMR0H register value to the Timer0 high byte.
This buffering allows all 16 bits of Timer0 to be read and written at the same time. Timer0 rolls over to 0x0000 on
incrementing past 0xFFFF. This makes the timer free-running. While actively operating in 16-bit mode, the Timer0
value can be read but not written.
24.2
Clock Selection
Timer0 has several options for clock source selections, the option to operate synchronously/asynchronously and an
available programmable prescaler. The CS bits are used to select the clock source for Timer0.
24.2.1
Synchronous Mode
When the ASYNC bit is clear, Timer0 clock is synchronized to the system clock (FOSC/4). When operating in
Synchronous mode, Timer0 clock frequency cannot exceed FOSC/4. During Sleep mode the system clock is not
available and Timer0 cannot operate.
24.2.2
Asynchronous Mode
When the ASYNC bit is set, Timer0 increments with each rising edge of the input source (or output of the prescaler,
if used). Asynchronous mode allows Timer0 to continue operation during Sleep mode provided the selected clock
source operates during Sleep.
24.2.3
Programmable Prescaler
Timer0 has 16 programmable input prescaler options ranging from 1:1 to 1:32768. The prescaler values are selected
using the CKPS bits. The prescaler counter is not directly readable or writable. The prescaler counter is cleared on
the following events:
•
•
•
24.2.4
A write to the TMR0L register
A write to either the T0CON0 or T0CON1 registers
Any device Reset
Programmable Postscaler
Timer0 has 16 programmable output postscaler options ranging from 1:1 to 1:16. The postscaler values are selected
using the OUTPS bits. The postscaler divides the output of Timer0 by the selected ratio. The postscaler counter is not
directly readable or writable. The postscaler counter is cleared on the following events:
•
•
•
A write to the TMR0L register
A write to either the T0CON0 or T0CON1 registers
Any device Reset
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 400
PIC18F27/47/57Q84
TMR0 - Timer0 Module
24.3
24.3.1
Timer0 Output and Interrupt
Timer0 Output
TMR0_out toggles on every match between TMR0L and TMR0H in 8-bit mode, or when TMR0H:TMR0L rolls over
in 16-bit mode. If the output postscaler is used, the output is scaled by the ratio selected. The Timer0 output can
be routed to an I/O pin via the RxyPPS output selection register, or internally to a number of Core Independent
Peripherals. The Timer0 output can be monitored through software via the OUT output bit.
24.3.2
Timer0 Interrupt
The Timer0 Interrupt Flag (TMR0IF) bit is set when the TMR0_out toggles. If the Timer0 interrupt is enabled
(TMR0IE), the CPU will be interrupted when the TMR0IF bit is set. When the postscaler bits (T0OUTPS) are set to
1:1 operation (no division), the T0IF flag bit will be set with every TMR0 match or rollover. In general, the TMR0IF flag
bit will be set every T0OUTPS +1 matches or rollovers.
24.3.3
Timer0 Example
Timer0 Configuration:
• Timer0 mode = 16-bit
• Clock Source = FOSC/4 (250 kHz)
• Synchronous operation
• Prescaler = 1:1
• Postscaler = 1:2 (T0OUTPS = 1)
In this case, the TMR0_out toggles every two rollovers of TMR0H:TMR0L.
i.e., (0xFFFF)*2*(1/250 kHz) = 524.28 ms
24.4
Operation During Sleep
When operating synchronously, Timer0 will halt when the device enters Sleep mode. When operating asynchronously
and the selected clock source is active, Timer0 will continue to increment and wake the device from Sleep mode if the
Timer0 interrupt is enabled.
24.5
Register Definitions: Timer0 Control
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 401
PIC18F27/47/57Q84
TMR0 - Timer0 Module
24.5.1
T0CON0
Name:
Address:
T0CON0
0x31A
Timer0 Control Register 0
Bit
Access
Reset
7
EN
R/W
0
6
5
OUT
R
0
4
MD16
R/W
0
3
R/W
0
2
1
OUTPS[3:0]
R/W
R/W
0
0
0
R/W
0
Bit 7 – EN TMR0 Enable
Value
Description
1
The module is enabled and operating
0
The module is disabled
Bit 5 – OUT TMR0 Output
Bit 4 – MD16 16-Bit Timer Operation Select
Value
Description
1
TMR0 is a 16-bit timer
0
TMR0 is an 8-bit timer
Bits 3:0 – OUTPS[3:0] TMR0 Output Postscaler (Divider) Select
Value
Description
1111
1:16 Postscaler
1110
1:15 Postscaler
1101
1:14 Postscaler
1100
1:13 Postscaler
1011
1:12 Postscaler
1010
1:11 Postscaler
1001
1:10 Postscaler
1000
1:9 Postscaler
0111
1:8 Postscaler
0110
1:7 Postscaler
0101
1:6 Postscaler
0100
1:5 Postscaler
0011
1:4 Postscaler
0010
1:3 Postscaler
0001
1:2 Postscaler
0000
1:1 Postscaler
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Preliminary Datasheet
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PIC18F27/47/57Q84
TMR0 - Timer0 Module
24.5.2
T0CON1
Name:
Address:
T0CON1
0x31B
Timer0 Control Register 1
Bit
Access
Reset
7
R/W
0
6
CS[2:0]
R/W
0
5
R/W
0
4
ASYNC
R/W
0
3
2
1
0
R/W
0
R/W
0
CKPS[3:0]
R/W
0
R/W
0
Bits 7:5 – CS[2:0] Timer0 Clock Source Select
Value
Description
111
110
101
100
011
010
001
000
CLC1_OUT
SOSC
MFINTOSC (500 kHz)
LFINTOSC
HFINTOSC
FOSC/4
Pin selected by T0CKIPPS (Inverted)
Pin selected by T0CKIPPS (Noninverted)
Bit 4 – ASYNC TMR0 Input Asynchronization Enable
Value
Description
1
The input to the TMR0 counter is not synchronized to system clocks
0
The input to the TMR0 counter is synchronized to Fosc/4
Bits 3:0 – CKPS[3:0] Prescaler Rate Select
Value
Description
1111
1:32768
1110
1:16384
1101
1:8192
1100
1:4096
1011
1:2048
1010
1:1024
1001
1:512
1000
1:256
0111
1:128
0110
1:64
0101
1:32
0100
1:16
0011
1:8
0010
1:4
0001
1:2
0000
1:1
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TMR0 - Timer0 Module
24.5.3
TMR0H
Name:
Address:
TMR0H
0x319
Timer0 Period/Count High Register
Bit
Access
Reset
7
6
5
R/W
1
R/W
1
R/W
1
4
3
TMR0H[7:0]
R/W
R/W
1
1
2
1
0
R/W
1
R/W
1
R/W
1
Bits 7:0 – TMR0H[7:0] TMR0 Most Significant Counter
Value
Condition Description
0 to 255 MD16 = 0 8-bit Timer0 Period Value. TMR0L continues counting from 0 when this value is reached.
0 to 255 MD16 = 1 16-bit Timer0 Most Significant Byte
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TMR0 - Timer0 Module
24.5.4
TMR0L
Name:
Address:
TMR0L
0x318
Timer0 Period/Count Low Register
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TMR0L[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – TMR0L[7:0] TMR0 Least Significant Counter
Value
Condition
Description
0 to 255 MD16 = 0
8-bit Timer0 Counter bits
0 to 255 MD16 = 1
16-bit Timer0 Least Significant Byte
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PIC18F27/47/57Q84
TMR0 - Timer0 Module
24.6
Address
0x00
...
0x0317
0x0318
0x0319
0x031A
0x031B
Register Summary: Timer0
Name
Bit Pos.
7
6
5
4
3
2
1
0
Reserved
TMR0L
TMR0H
T0CON0
T0CON1
7:0
7:0
7:0
7:0
EN
© 2021 Microchip Technology Inc.
OUT
CS[2:0]
TMR0L[7:0]
TMR0H[7:0]
MD16
ASYNC
Preliminary Datasheet
OUTPS[3:0]
CKPS[3:0]
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TMR1 - Timer1 Module with Gate Control
25.
TMR1 - Timer1 Module with Gate Control
The Timer1 module is a 16-bit timer/counter with the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
16-bit timer/counter register pair (TMRxH:TMRxL)
Programmable internal or external clock source
2-bit prescaler
Clock source for optional comparator synchronization
Multiple Timer1 gate (count enable) sources
Interrupt-on-overflow
Wake-up on overflow (external clock, Asynchronous mode only)
16-bit read/write operation
Time base for the capture/compare function with the CCP modules
Special event trigger (with CCP)
Selectable gate source polarity
Gate Toggle mode
Gate Single-Pulse mode
Gate value status
Gate event interrupt
Important: References to the module Timer1 apply to all the odd numbered timers on this device.
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TMR1 - Timer1 Module with Gate Control
Figure 25-1. Timer1 Block Diagram
TxGATE
4
TxGPPS
GSPM
PPS
00 00
1
0
NOTE (5)
1
11 11
D
D
Single Pulse
Acq. Control
Q1
Q
GPOL
GGO/DONE
CK
Q
Interrupt
ON
R
set bit
TMRxGIF
det
GTM
GE
set flag bit
TMRxIF
ON
EN
(2)
Tx_overflow
GVAL
Q
0
To Comparators (6)
TMRx
TMRxH
TMRxL
Q
Synchronized Clock Input
0
D
1
TxCLK
SYNC
TxCLK
4
TxCKIPPS
(1)
PPS
0000
Note
Prescaler
1,2,4,8
(4)
Synchronize(3)
det
111 1
2
CKPS
Fosc/2
Internal
Clock
Sleep
Input
Notes:
1. This signal comes from the pin selected by Timer1 PPS register.
2. TMRx register increments on rising edge.
3. Synchronize does not operate while in Sleep.
4. See TxCLK for clock source selections.
5. See TxGATE for gate source selections.
6. Synchronized comparator output must not be used in conjunction with synchronized input clock.
25.1
Timer1 Operation
The Timer1 module is a 16-bit incrementing counter that is accessed through the TMRx register. Writes to TMRx
directly update the counter. When used with an internal clock source, the module is a timer that increments on every
instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and
increments on every selected edge of the external source.
Timer1 is enabled by configuring the ON and GE bits. Table 25-1 displays the possible Timer1 enable selections.
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TMR1 - Timer1 Module with Gate Control
Table 25-1. Timer1 Enable Selections
25.2
ON
GE
Timer1 Operation
1
1
Count Enabled
1
0
Always On
0
1
Off
0
0
Off
Clock Source Selection
The CS bits select the clock source for Timer1. These bits allow the selection of several possible synchronous and
asynchronous clock sources.
25.2.1
Internal Clock Source
When the internal clock source is selected, the TMRx register will increment on multiples of FOSC as determined by
the Timer1 prescaler.
When the FOSC internal clock source is selected, the TMRx register value will increment by four counts every
instruction clock cycle. Due to this condition, a two LSB error in resolution will occur when reading the TMRx value.
To utilize the full resolution of Timer1, an asynchronous input signal must be used to gate the Timer1 clock input.
Important: In Counter mode, a falling edge must be registered by the counter prior to the first
incrementing rising edge after any one or more of the following conditions:
• Timer1 enabled after POR
• Write to TMRxH or TMRxL
• Timer1 is disabled
• Timer1 is disabled (ON = 0) when TxCKI is high then Timer1 is enabled (ON = 1) when TxCKI is low.
Refer to the figure below.
Figure 25-2. Timer1 Incrementing Edge
TxCKI = 1
When TMRx
Enabled
TxCKI = 0
When TMRx
Enabled
Notes:
1. Arrows indicate counter increments.
2. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of
the clock.
25.2.2
External Clock Source
When the external clock source is selected, the TMRx module may work as a timer or a counter. When enabled to
count, Timer1 is incremented on the rising edge of the external clock input of the TxCKIPPS pin. This external clock
source can be synchronized to the system clock or it can run asynchronously.
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TMR1 - Timer1 Module with Gate Control
25.3
Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The CKPS bits control the prescale
counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a
write to TMRx.
25.4
Secondary Oscillator
A secondary low-power 32.768 kHz oscillator circuit is built-in between pins SOSCI (input) and SOSCO (amplifier
output). This internal circuit is to be used in conjunction with an external 32.768 kHz crystal. The secondary oscillator
is not dedicated only to Timer1; it can also be used by other modules.
The oscillator circuit is enabled by setting the SOSCEN bit of the OSCEN register. This can be used as one of the
Timer1 clock sources selected with the CS bits. The oscillator will continue to run during Sleep.
Important: The oscillator requires a start-up and stabilization time before use. Thus, the SOSCEN bit
of the OSCEN register must be set and a suitable delay observed prior to enabling Timer1. A software
check can be performed to confirm if the secondary oscillator is enabled and ready to use. This is done
by polling the secondary oscillator ready Status bit. Refer to “OSC - Oscillator Module (with Fail-Safe
Clock Monitor)” for more details.
25.5
Timer1 Operation in Asynchronous Counter Mode
When the SYNC control bit is set, the external clock input is not synchronized. The timer increments asynchronously
to the internal phase clocks. If the external clock source is selected then the timer will continue to run during
Sleep and can generate an interrupt on overflow, which will wake up the processor. However, special precautions in
software are needed to read/write the timer.
Important: When switching from synchronous to asynchronous operation, it is possible to skip an
increment. When switching from asynchronous to synchronous operation, it is possible to produce an
additional increment.
25.5.1
Reading and Writing TMRx in Asynchronous Counter Mode
Reading TMRxH or TMRxL while the timer is running from an external asynchronous clock will ensure a valid read
(taken care of in hardware). However, the user must keep in mind that reading the 16-bit timer in two 8-bit values
itself, poses certain problems, since there may be a carry out of TMRxL to TMRxH between the reads.
For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may
occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in
the TMRxH:TMRxL register pair.
25.6
Timer1 16-Bit Read/Write Mode
Timer1 can be configured to read and write all 16 bits of data to and from the 8-bit TMRxL and TMRxH registers,
simultaneously. The 16-bit read and write operations are enabled by setting the RD16 bit. To accomplish this function,
the TMRxH register value is mapped to a buffer register called the TMRxH buffer register. While in 16-Bit mode, the
TMRxH register is not directly readable or writable and all read and write operations take place through the use of
this TMRxH buffer register.
When a read from the TMRxL register is requested, the value of the TMRxH register is simultaneously loaded into the
TMRxH buffer register. When a read from the TMRxH register is requested, the value is provided from the TMRxH
buffer register instead. This provides the user with the ability to accurately read all 16 bits of the Timer1 value from
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TMR1 - Timer1 Module with Gate Control
a single instance in time. Refer to the figure below for more details. In contrast, when not in 16-Bit mode, the user
must read each register separately and determine if the values have become invalid due to a rollover that may have
occurred between the read operations.
When a write request of the TMRxL register is requested, the TMRxH buffer register is simultaneously updated with
the contents of the TMRxH register. The value of TMRxH must be preloaded into the TMRxH buffer register prior to
the write request for the TMRxL register. This provides the user with the ability to write all 16 bits to the TMRx register
at the same time. Any requests to write to TMRxH directly does not clear the Timer1 prescaler value. The prescaler
value is only cleared through write requests to the TMRxL register.
Figure 25-3. Timer1 16-Bit Read/Write Mode Block Diagram
From
TMRx
Circuitr y
TMRx
High Byte
TMRxL
Set TMRxIF
on Overflow
8
Read TMRxL
Write TMRxL
8
8
TMRxH
8
8
25.7
Inte rnal Da ta Bus
Timer1 Gate
Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate circuitry. This is
also referred to as Timer1 gate enable. Timer1 gate can also be driven by multiple selectable sources.
25.7.1
Timer1 Gate Enable
The Timer1 Gate Enable mode is enabled by setting the GE bit. The polarity of the Timer1 Gate Enable mode is
configured using the GPOL bit.
When Timer1 Gate Enable mode is enabled, Timer1 will increment on the rising edge of the Timer1 clock source.
When Timer1 Gate signal is inactive, the timer will not increment and hold the current count. Enable mode is
disabled, no incrementing will occur and Timer1 will hold the current count. See figure below for timing details.
Table 25-2. Timer1 Gate Enable Selections
TMRxCLK
GPOL
TxG
Timer1 Operation
↑
1
1
Counts
↑
1
0
Holds Count
↑
0
1
Holds Count
↑
0
0
Counts
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TMR1 - Timer1 Module with Gate Control
Figure 25-4. Timer1 Gate Enable Mode
TMRxGE
TxGPOL
TxG_IN
TxCKI
TxGVAL
Timer1
25.7.2
Timer1 Gate Source Selection
The gate source for Timer1 is selected using the GSS bits. The polarity selection for the gate source is controlled by
the GPOL bit.
Any of the above mentioned signals can be used to trigger the gate. The output of the CMPx can be synchronized
to the Timer1 clock or left asynchronous. For more information refer to the “Comparator Output Synchronization”
section.
25.7.3
Timer1 Gate Toggle Mode
When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 Gate signal,
as opposed to the duration of a single level pulse. The Timer1 gate source is routed through a flip-flop that changes
state on every incrementing edge of the signal. See figure below for timing details.
Timer1 Gate Toggle mode is enabled by setting the GTM bit. When the GTM bit is cleared, the flip-flop is cleared and
held clear. This is necessary in order to control which edge is measured.
Important: Enabling Toggle mode at the same time as changing the gate polarity may result in
indeterminate operation.
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TMR1 - Timer1 Module with Gate Control
Figure 25-5. Timer1 Gate Toggle Mode
TMRxGE
TxGPOL
TxGTM
TxTxG_IN
TxCKI
TxGVAL
Timer1
25.7.4
Timer1 Gate Single Pulse Mode
When Timer1 Gate Single Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer1 Gate
Single Pulse mode is first enabled by setting the GSPM bit. Next, the GGO/DONE must be set. The Timer1 will
be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the GGO/DONE bit will
automatically be cleared. No other gate events will be allowed to increment Timer1 until the GGO/DONE bit is once
again set in software.
Figure 25-6. Timer1 Gate Single Pulse Mode
TMRxGE
TxGPOL
TxGSPM
Cleared by hardware on
falling edge of TxGVAL
Set by software
TxGGO/
DONE
Counting enabled on
rising edge of TxG
TxG_IN
TxCKI
TxGVAL
TIMER1
TMRxGIF
Cleared by software
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Set by hardware on
falling edge of TxGVAL
Preliminary Datasheet
Cleared by
software
DS40002213D-page 413
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TMR1 - Timer1 Module with Gate Control
Clearing the GSPM bit will also clear the GGO/DONE bit. See the figure below for timing details. Enabling the Toggle
mode and the Single Pulse mode simultaneously will permit both sections to work together. This allows the cycle
times on the Timer1 gate source to be measured. See figure below for timing details.
Figure 25-7. Timer1 Gate Single Pulse and Toggle Combined Mode
TMRxGE
TxGPOL
TxGSPM
TxGTM
Cleared by hardware on
falling edge of TxGVAL
Set by software
TxGGO/
DONE
Counting enabled on
rising edge of TxG
TxG_IN
TxCKI
TxGVAL
TIMER1
TMRxGIF
25.7.5
Cleared by software
Set by hardware on
falling edge of TxGVAL
Cleared by
software
Timer1 Gate Value Status
When Timer1 gate value status is utilized, it is possible to read the most current level of the gate control value. The
value is stored in the GVAL bit in the TxGCON register. The GVAL bit is valid even when the Timer1 gate is not
enabled (GE bit is cleared).
25.7.6
Timer1 Gate Event Interrupt
When Timer1 gate event interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate
event. When the falling edge of GVAL occurs, the TMRxGIF flag bit in one of the PIR registers will be set. If the
TMRxGIE bit in the corresponding PIE register is set, then an interrupt will be recognized.
The TMRxGIF flag bit operates even when the Timer1 gate is not enabled (GE bit is cleared). For more information
on selecting high or low priority status for the Timer1 gate event interrupt see the “VIC - Vectored Interrupt
Controller Module” chapter.
25.8
Timer1 Interrupt
The TMRx register increments to FFFFh and rolls over to 0000h. When TMRx rolls over, the Timer1 interrupt flag bit
of the PIRx register is set. To enable the interrupt-on-rollover, the following bits must be set:
•
•
•
ON bit of the TxCON register
TMRxIE bits of the PIEx register
Global interrupts must be enabled
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TMR1 - Timer1 Module with Gate Control
The interrupt is cleared by clearing the TMRxIF bit as a task in the Interrupt Service Routine. For more information on
selecting high or low priority status for the Timer1 overflow interrupt, see the “VIC - Vectored Interrupt Controller
Module” chapter.
Important: The TMRx register and the TMRxIF bit must be cleared before enabling interrupts.
25.9
Timer1 Operation During Sleep
Timer1 can only operate during Sleep when configured as an asynchronous counter. In this mode, many clock
sources can be used to increment the counter. To set up the timer to wake the device:
•
•
•
•
•
ON bit must be set
TMRxIE bit of the PIEx register must be set
Global interrupts must be enabled
SYNC bit must be set
Configure the TxCLK register for using any clock source other than FOSC and FOSC/4
The device will wake up on an overflow and execute the next instruction. If global interrupts are enabled, the device
will call the Interrupt Service Routine. The secondary oscillator will continue to operate in Sleep regardless of the
SYNC bit setting.
25.10
CCP Capture/Compare Time Base
The CCP modules use TMRx as the time base when operating in Capture or Compare mode. In Capture mode, the
value in TMRx is copied into the CCPRx register on a capture event. In Compare mode, an event is triggered when
the value in the CCPRx register matches the value in TMRx. This event can be a Special Event Trigger.
25.11
CCP Special Event Trigger
When any of the CCPs are configured to trigger a special event, the trigger will clear the TMRx register. This special
event does not cause a Timer1 interrupt. The CCP module may still be configured to generate a CCP interrupt. In this
mode of operation, the CCPRx register becomes the period register for Timer1. Timer1 must be synchronized and
FOSC/4 must be selected as the clock source in order to utilize the Special Event Trigger. Asynchronous operation of
Timer1 can cause a Special Event Trigger to be missed. In the event that a write to TMRxH or TMRxL coincides with
a Special Event Trigger from the CCP, the write will take precedence.
25.12
Peripheral Module Disable
When a peripheral is not used or inactive, the module can be disabled by setting the Module Disable bit in the PMD
registers. This will reduce power consumption to an absolute minimum. Setting the PMD bits holds the module in
Reset and disconnects the module’s clock source. The Module Disable bits for Timer1 (TMR1MD) are in the PMDx
register. See the “PMD - Peripheral Module Disable” chapter for more information.
25.13
Register Definitions: Timer1 Control
Long bit name prefixes for the System Arbiter Priority Registers are shown in the table below where “x” refers to
the Priority Register instance number. Refer to the “Long Bit Names” section in the “Register and Bit Naming
Conventions” chapter for more information.
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TMR1 - Timer1 Module with Gate Control
Table 25-3. Timer1 Register Bit Name Prefixes
Peripheral
Bit Name Prefix
Timer1
T1
Timer3
T3
Timer 5
T5
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TMR1 - Timer1 Module with Gate Control
25.13.1 TxCON
Name:
Address:
TxCON
0x31E,0x32A,0x336
Timer Control Register
Bit
7
6
5
4
3
CKPS[1:0]
Access
Reset
R/W
0
R/W
0
2
SYNC
R/W
0
1
RD16
R/W
0
0
ON
R/W
0
Bits 5:4 – CKPS[1:0] Timer Input Clock Prescaler Select
Reset States: POR/BOR = 00
All Other Resets = uu
Value
Description
11
1:8 Prescaler value
10
1:4 Prescaler value
01
1:2 Prescaler value
00
1:1 Prescaler value
Bit 2 – SYNC Timer External Clock Input Synchronization Control
Reset States: POR/BOR = 0
All Other Resets = u
Value
Condition
Description
x
CS = FOSC/4 or FOSC
This bit is ignored. Timer uses the incoming clock as is.
1
All other clock sources
Do not synchronize external clock input
0
All other clock sources
Synchronize external clock input with system clock
Bit 1 – RD16 16-Bit Read/Write Mode Enable
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
Enables register read/write of Timer in one 16-bit operation
0
Enables register read/write of Timer in two 8-bit operations
Bit 0 – ON Timer On
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
Enables Timer
0
Disables Timer
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TMR1 - Timer1 Module with Gate Control
25.13.2 TxGCON
Name:
Address:
TxGCON
0x31F,0x32B,0x337
Timer Gate Control Register
Bit
Access
Reset
7
GE
R/W
0
6
GPOL
R/W
0
5
GTM
R/W
0
4
GSPM
R/W
0
3
GGO/DONE
R/W
0
2
GVAL
R
x
1
0
Bit 7 – GE Timer Gate Enable
Reset States: POR/BOR = 0
All Other Resets = u
Value
Condition
Description
1
ON = 1
Timer counting is controlled by the Timer gate function
0
ON = 1
Timer is always counting
X
ON = 0
This bit is ignored
Bit 6 – GPOL Timer Gate Polarity
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
Timer gate is active-high (Timer counts when gate is high)
0
Timer gate is active-low (Timer counts when gate is low)
Bit 5 – GTM Timer Gate Toggle Mode
Timer Gate Flip-Flop Toggles on every rising edge when Toggle mode is enabled.
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
Timer Gate Toggle mode is enabled
0
Timer Gate Toggle mode is disabled and Toggle flip-flop is cleared
Bit 4 – GSPM Timer Gate Single Pulse Mode
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
Timer Gate Single Pulse mode is enabled and is controlling Timer gate
0
Timer Gate Single Pulse mode is disabled
Bit 3 – GGO/DONE Timer Gate Single Pulse Acquisition Status
This bit is automatically cleared when TxGSPM is cleared.
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
Timer Gate Single Pulse Acquisition is ready, waiting for an edge
0
Timer Gate Single Pulse Acquisition has completed or has not been started
Bit 2 – GVAL Timer Gate Current State
Indicates the current state of the timer gate that can be provided to TMRxH:TMRxL
Unaffected by Timer Gate Enable (GE bit)
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TMR1 - Timer1 Module with Gate Control
25.13.3 TxCLK
Name:
Address:
TxCLK
0x321,0x32D,0x339
Timer Clock Source Selection Register
Bit
7
6
5
Access
Reset
4
3
R/W
0
R/W
0
2
CS[4:0]
R/W
0
1
0
R/W
0
R/W
0
Bits 4:0 – CS[4:0] Timer Clock Source Selection
Table 25-4. Timer Clock Sources
CS
Timer1
11111-10110
10101
10100
10011
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
TMR5_OUT
TMR3_OUT
Reserved
Pin selected by T1CKIPPS
Clock Source
Timer3
Reserved
CLC8_OUT
CLC7_OUT
CLC6_OUT
CLC5_OUT
CLC4_OUT
CLC3_OUT
CLC2_OUT
CLC1_OUT
TMR5_OUT
Reserved
TMR1_OUT
TMR0_OUT
CLKREF_OUT
EXTOSC
SOSC
MFINTOSC (32 kHz)
MFINTOSC (500 kHz)
LFINTOSC
HFINTOSC
FOSC
FOSC/4
Pin selected by T3CKIPPS
Timer5
Reserved
TMR3_OUT
TMR1_OUT
Pin selected by T5CKIPPS
Reset States: POR/BOR = 00000
All Other Resets = uuuuu
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 419
PIC18F27/47/57Q84
TMR1 - Timer1 Module with Gate Control
25.13.4 TxGATE
Name:
Address:
TxGATE
0x320,0x32C,0x338
Timer Gate Source Selection Register
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
GSS[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 5:0 – GSS[5:0] Timer Gate Source Selection
Table 25-5. Timer Gate Sources
GSS
Timer1
111111-100010
100001
100000
011111
011110
011101
011100
011011
011010
011001
011000
010111
010110
010101
010100
010011
010010
010001
010000
001111
001110
001101
001100
001011
001010
001001
001000
000111
000110
000101
000100
000011
000010
TMR5_OUT
TMR3_OUT
Reserved
© 2021 Microchip Technology Inc.
Gate Source
Timer3
Reserved
CLC8_OUT
CLC7_OUT
CLC6_OUT
CLC5_OUT
CLC4_OUT
CLC3_OUT
CLC2_OUT
CLC1_OUT
ZCD_OUT
CMP2_OUT
CMP1_OUT
NCO3_OUT
NCO2_OUT
NCO1_OUT
PWM4S1P2_OUT
PWM4S1P1_OUT
PWM3S1P2_OUT
PWM3S1P1_OUT
PWM2S1P2_OUT
PWM2S1P1_OUT
PWM1S1P2_OUT
PWM1S1P1_OUT
CCP3_OUT
CCP2_OUT
CCP1_OUT
SMT1_OUT
TMR6_Postscaler_OUT
TMR5_OUT
TMR4_Postscaler_OUT
Reserved
TMR2_Postscaler_OUT
TMR1_OUT
Preliminary Datasheet
Timer5
Reserved
TMR3_OUT
TMR1_OUT
DS40002213D-page 420
PIC18F27/47/57Q84
TMR1 - Timer1 Module with Gate Control
...........continued
GSS
Timer1
000001
000000
Pin selected by T1GPPS
© 2021 Microchip Technology Inc.
Gate Source
Timer3
TMR0_OUT
Pin selected by T3GPPS
Preliminary Datasheet
Timer5
Pin selected by T5GPPS
DS40002213D-page 421
PIC18F27/47/57Q84
TMR1 - Timer1 Module with Gate Control
25.13.5 TMRx
Name:
Address:
TMRx
0x31C,0x328,0x334
Timer Register
Bit
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TMRx[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
TMRx[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – TMRx[15:0] Timer Register Value
Reset States: POR/BOR = 0000000000000000
All Other Resets = uuuuuuuuuuuuuuuu
Notes: The individual bytes in this multibyte register can be accessed with the following register names:
• TMRxH: Accesses the high byte TMRx[15:8]
• TMRxL: Accesses the low byte TMRx[7:0]
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 422
PIC18F27/47/57Q84
TMR1 - Timer1 Module with Gate Control
25.14
Register Summary Timer 1
Address
Name
0x00
...
0x031B
Reserved
0x031C
TMR1
0x031E
0x031F
0x0320
0x0321
0x0322
...
0x0327
T1CON
T1GCON
T1GATE
T1CLK
Bit Pos.
7:0
15:8
7:0
7:0
7:0
7:0
7
6
5
4
3
2
1
0
RD16
ON
RD16
ON
RD16
ON
TMR1[7:0]
TMR1[15:8]
GE
GPOL
CKPS[1:0]
GTM
GSPM
SYNC
GGO/DONE
GVAL
GSS[5:0]
CS[4:0]
Reserved
0x0328
TMR3
0x032A
0x032B
0x032C
0x032D
0x032E
...
0x0333
T3CON
T3GCON
T3GATE
T3CLK
7:0
15:8
7:0
7:0
7:0
7:0
TMR3[7:0]
TMR3[15:8]
GE
GPOL
CKPS[1:0]
GTM
GSPM
SYNC
GGO/DONE
GVAL
GSS[5:0]
CS[4:0]
Reserved
0x0334
TMR5
0x0336
0x0337
0x0338
0x0339
T5CON
T5GCON
T5GATE
T5CLK
7:0
15:8
7:0
7:0
7:0
7:0
TMR5[7:0]
TMR5[15:8]
GE
© 2021 Microchip Technology Inc.
GPOL
CKPS[1:0]
GTM
GSPM
SYNC
GGO/DONE
GVAL
GSS[5:0]
CS[4:0]
Preliminary Datasheet
DS40002213D-page 423
PIC18F27/47/57Q84
TMR2 - Timer2 Module
26.
TMR2 - Timer2 Module
The Timer2 module is a 8-bit timer that incorporates the following features:
•
•
•
•
•
•
•
•
•
•
•
8-bit timer and period registers
Readable and writable
Software programmable prescaler (1:1 to 1:128)
Software programmable postscaler (1:1 to 1:16)
Interrupt on T2TMR match with T2PR
One-shot operation
Full asynchronous operation
Includes Hardware Limit Timer (HLT)
Alternate clock sources
External timer Reset signal sources
Configurable timer Reset operation
See Figure 26-1 for a block diagram of Timer2.
Important: References to module Timer2 apply to all the even numbered timers on this device. (Timer2,
Timer4, etc.)
Figure 26-1. Timer2 with Hardware Limit Timer (HLT) Block Diagram
RSEL
TxINPPS
TxIN
PPS
Rev. 10-000168D
4/29/2019
MODE
External
Reset
Sources(2)
TMRx_ers
Edge Detector
Level Detector
Mode Control
(2 clock Sync)
MODE[3]
reset
CCP_pset(1)
MODE[4:3]=’b01
enable
CKPOL
CS
TxINPPS
TxIN
PPS
TMRx_clk
Prescaler
See
TxCLKCON
register(3)
CKPS
Sync
(2 Clocks)
ON
D
MODE[4:1]=’b1011
0
Sync
1
Fosc/4
PSYNC
1
TxTMR
Q
Clear ON
R
Set flag bit
TMRxIF
Comparator
Postscaler
TxPR
OUTPS
TMRx_postscaled
0
CSYNC
Notes:
1. Signal to the CCP peripheral for PWM pulse trigger in PWM mode.
2. See RSEL for external Reset sources.
3. See CS for clock source selections.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 424
PIC18F27/47/57Q84
TMR2 - Timer2 Module
26.1
Timer2 Operation
Timer2 operates in three major modes:
•
•
•
Free-Running Period
One-shot
Monostable
Within each operating mode, there are several options for starting, stopping, and Reset. Table 26-1 lists the options.
In all modes, the T2TMR count register increments on the rising edge of the clock signal from the programmable
prescaler. When T2TMR equals T2PR, a high level output to the postscaler counter is generated. T2TMR is cleared
on the next clock input.
An external signal from hardware can also be configured to gate the timer operation or force a T2TMR count Reset.
In Gate modes the counter stops when the gate is disabled and resumes when the gate is enabled. In Reset modes,
the T2TMR count is reset on either the level or edge from the external source.
The T2TMR and T2PR registers are both directly readable and writable. The T2TMR register is cleared and the
T2PR register initializes to 0xFF on any device Reset. Both the prescaler and postscaler counters are cleared on the
following events:
•
•
•
•
A write to the T2TMR register
A write to the T2CON register
Any device Reset
External Reset source event that resets the timer.
Important: T2TMR is not cleared when T2CON is written.
26.1.1
Free-Running Period Mode
The value of T2TMR is compared to that of the Period register, T2PR, on each clock cycle. When the two values
match, the comparator resets the value of T2TMR to 0x00 on the next cycle and increments the output postscaler
counter. When the postscaler count equals the value in the OUTPS bits of the T2CON register then a one clock
period wide pulse occurs on the TMR2_postscaled output, and the postscaler count is cleared.
26.1.2
One Shot Mode
The One Shot mode is identical to the Free-Running Period mode except that the ON bit is cleared and the timer is
stopped when T2TMR matches T2PR and will not restart until the ON bit is cycled off and on. Postscaler (OUTPS)
values other than zero are ignored in this mode because the timer is stopped at the first period event and the
postscaler is reset when the timer is restarted.
26.1.3
Monostable Mode
Monostable modes are similar to One Shot modes except that the ON bit is not cleared and the timer can be
restarted by an external Reset event.
26.2
Timer2 Output
The Timer2 module’s primary output is TMR2_postscaled, which pulses for a single TMR2_clk period upon each
match of the postscaler counter and the OUTPS bits of the T2CON register. The postscaler is incremented each time
the T2TMR value matches the T2PR value. This signal can also be selected as an input to other Core Independent
Peripherals:
In addition, the Timer2 is also used by the CCP module for pulse generation in PWM mode. See the “PWM
Overview” and “PWM Period” sections in the “CCP - Capture/Compare/PWM Module” chapter for more details
on setting up Timer2 for use with the CCP and PWM modules.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 425
PIC18F27/47/57Q84
TMR2 - Timer2 Module
26.3
External Reset Sources
In addition to the clock source, the Timer2 can also be driven by an external Reset source input. This external Reset
input is selected for each timer with the corresponding TxRST register. The external Reset input can control starting
and stopping of the timer, as well as resetting the timer, depending on the mode used.
26.4
Timer2 Interrupt
Timer2 can also generate a device interrupt. The interrupt is generated when the postscaler counter matches the
selected postscaler value (OUTPS bits of T2CON register). The interrupt is enabled by setting the TMR2IE interrupt
enable bit. Interrupt timing is illustrated in the figure below.
Figure 26-2. Timer2 Prescaler, Postscaler, and Interrupt Timing Diagram
Rev. 10-000 205B
3/6/201 9
CKPS
b010
TxPR
1
b0001
OUTPS
TMRx_clk
TxTMR
0
1
0
1
0
1
0
TMRx_postscaled
TMRxIF
(1)
(2)
(1)
Note 1:
Setting the interrupt flag is synchronized with the instruction clock.
Synchronization may take as many as two instruction cycles
2: Cleared by software.
26.5
PSYNC bit
Setting the PSYNC bit synchronizes the prescaler output to FOSC/4. Setting this bit is required for reading the Timer2
counter register while the selected Timer clock is asynchronous to FOSC/4.
Note: Setting PSYNC requires that the output of the prescaler is slower than FOSC/4. Setting PSYNC when the
output of the prescaler is greater than or equal to FOSC/4 may cause unexpected results.
26.6
CSYNC bit
All bits in the Timer2 SFRs are synchronized to FOSC/4 by default, not the Timer2 input clock. As such, if the Timer2
input clock is not synchronized to FOSC/4, it is possible for the Timer2 input clock to transition at the same time as
the ON bit is set in software, which may cause undesirable behavior and glitches in the counter. Setting the CSYNC
bit remedies this problem by synchronizing the ON bit to the Timer2 input clock instead of FOSC/4. However, as this
synchronization uses an edge of the TMR2 input clock, up to one input clock cycle will be consumed and not counted
by the Timer2 when CSYNC is set. Conversely, clearing the CSYNC bit synchronizes the ON bit to FOSC/4, which
does not consume any clock edges, but has the previously stated risk of glitches.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 426
PIC18F27/47/57Q84
TMR2 - Timer2 Module
26.7
Operating Modes
The mode of the timer is controlled by the MODE bits. Edge Triggered modes require six Timer clock periods
between external triggers. Level Triggered modes require the triggering level to be at least three Timer clock periods
long. External triggers are ignored while in Debug mode.
Table 26-1. Operating Modes Table
Mode
MODE
[4:3] [2:0]
Output
Operation
00
Start
Reset
Stop
Software gate (Figure 26-3)
ON = 1
—
ON = 0
001
Hardware gate, active-high
(Figure 26-4)
ON = 1 and
TMRx_ers = 1
—
ON = 0 or
TMRx_ers = 0
Hardware gate, active-low
ON = 1 and
TMRx_ers = 0
—
ON = 0 or
TMRx_ers = 1
011
100
101
110
Period Pulse
Period
Pulse
with
Hardware
Rising or falling edge Reset
Rising edge Reset (Figure 26-5)
TMRx_ers ↕
TMRx_ers ↑
Falling edge Reset
TMRx_ers ↓
Low-level Reset
ON = 0 or
TMRx_ers = 0
TMRx_ers = 1
ON = 0 or
TMRx_ers = 1
One-shot
Software start (Figure 26-7)
ON = 1
—
Rising edge start (Figure 26-8)
ON = 1 and
TMRx_ers ↑
—
Falling edge start
ON = 1 and
TMRx_ers ↓
—
011
Any edge start
ON = 1 and
TMRx_ers ↕
—
100
Rising edge start and
Rising edge Reset (Figure 26-9)
ON = 1 and
TMRx_ers ↑
TMRx_ers ↑
Falling edge start and
Falling edge Reset
ON = 1 and
TMRx_ers ↓
TMRx_ers ↓
Rising edge start and
Low-level Reset (Figure 26-10)
ON = 1 and
TMRx_ers ↑
TMRx_ers = 0
Falling edge start and
High-level Reset
ON = 1 and
TMRx_ers ↓
TMRx_ers = 1
001
010
EdgeTriggered Start
(Note 1)
101
EdgeTriggered Start
and
110 Hardware Reset
(Note 1)
111
© 2021 Microchip Technology Inc.
Preliminary Datasheet
ON = 0
TMRx_ers = 0
High-level Reset (Figure 26-6)
000
01
ON = 1
Reset
111
One-shot
Timer Control
000
010
FreeRunning Period
Operation
ON = 0
or
Next clock after
TxTMR = TxPR
(Note 2)
DS40002213D-page 427
PIC18F27/47/57Q84
TMR2 - Timer2 Module
...........continued
MODE
Mode
[4:3] [2:0]
Output
Operation
000
001
Monostable
010
011
Reserved
Reserved
EdgeTriggered
10
Start
(Note 1)
100
101
110
Level
Triggered
Start
Reset
Stop
ON = 0
or
Rising edge start
(Figure 26-11)
Reserved
ON = 1 and
TMRx_ers ↑
—
Falling edge start
ON = 1 and
TMRx_ers ↓
—
Any edge start
ON = 1 and
TMRx_ers ↕
—
Reserved
Reserved
ON = 1 and
High-level start and
Low-level Reset (Figure 26-12)
TMRx_ers = 1
and
111
TMRx_ers = 0
Hardware Reset
11
xxx
ON = 1 and
TMRx_ers = 0 TMRx_ers = 1
Low-level start and
High-level Reset
Next clock after
TxTMR = TxPR
Start
One-shot
Reserved
Timer Control
Operation
(Note 3)
ON = 0 or
Held in Reset
(Note 2)
Reserved
Notes:
1. If ON = 0 then an edge is required to restart the timer after ON = 1.
26.8
2.
When T2TMR = T2PR then the next clock clears ON and stops T2TMR at 00h.
3.
When T2TMR = T2PR then the next clock stops T2TMR at 00h but does not clear ON.
Operation Examples
Unless otherwise specified, the following notes apply to the following timing diagrams:
•
•
•
•
26.8.1
Both the prescaler and postscaler are set to 1:1 (both the CKPS and OUTPS bits.)
The diagrams illustrate any clock except FOSC/4 and show clock-sync delays of at least two full cycles for both
ON and TMRx_ers. When using FOSC/4, the clock-sync delay is at least one instruction period for TMRx_ers;
ON applies in the next instruction period.
ON and TMRx_ers are somewhat generalized, and clock-sync delays may produce results that are slightly
different than illustrated.
The PWM Duty Cycle and PWM output are illustrated assuming that the timer is used for the PWM function of
the CCP module as described in the “PWM Overview” section. The signals are not a part of the Timer2 module.
Software Gate Mode
This mode corresponds to legacy Timer2 operation. The timer increments with each clock input when ON = 1 and
does not increment when ON = 0. When the TxTMR count equals the TxPR period count the timer resets on the next
clock and continues counting from 0. Operation with the ON bit software controlled is illustrated in Figure 26-3. With
TxPR = 5, the counter advances until TxTMR = 5, and goes to zero with the next clock.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 428
PIC18F27/47/57Q84
TMR2 - Timer2 Module
Figure 26-3. Software Gate Mode Timing Diagram (MODE = ‘b00000)
Rev. 10-000 195C
3/6/201 9
TMRx_clk
Instruction(1)
BSF
BCF
BSF
ON
TxPR
TxTMR
5
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
0
1
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note
1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 429
PIC18F27/47/57Q84
TMR2 - Timer2 Module
26.8.2
Hardware Gate Mode
The Hardware Gate modes operate the same as the Software Gate mode except the TMRx_ers external signal can
also gate the timer. When used with the CCP, the gating extends the PWM period. If the timer is stopped when the
PWM output is high, then the duty cycle is also extended.
When MODE = ‘b00001 then the timer is stopped when the external signal is high. When MODE = ‘b00010, then
the timer is stopped when the external signal is low.
Figure 26-4 illustrates the Hardware Gating mode for MODE = ‘b00001 in which a high input level starts the counter.
Figure 26-4. Hardware Gate Mode Timing Diagram (MODE = ‘b00001)
Rev. 10-000 196C
3/6/201 9
TMRx_clk
TMRx_ers
TxPR
TxTMR
5
0
1
2
3
4
5
0
1
2
3
4
5
0
1
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 430
PIC18F27/47/57Q84
TMR2 - Timer2 Module
26.8.3
Edge Triggered Hardware Limit Mode
In Hardware Limit mode, the timer can be reset by the TMRx_ers external signal before the timer reaches the period
count. Three types of Resets are possible:
•
Reset on rising or falling edge (MODE= ‘b00011)
•
Reset on rising edge (MODE = ‘b00100)
•
Reset on falling edge (MODE = ‘b00101)
When the timer is used in conjunction with the CCP in PWM mode then an early Reset shortens the period and
restarts the PWM pulse after a two clock delay. Refer to Figure 26-5.
Figure 26-5. Edge Triggered Hardware Limit Mode Timing Diagram
(MODE = ‘b00100)
Rev. 10-000197C
3/6/2019
TMRx_clk
5
TxPR
Instruction(1)
BSF
BCF
BSF
ON
TMRx_ers
0
TxTMR
1
2
0
1
2
3
4
5
0
1
2
3
4
5
0
1
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note
1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by
the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous
to the timer clock input.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 431
PIC18F27/47/57Q84
TMR2 - Timer2 Module
26.8.4
Level Triggered Hardware Limit Mode
In the Level Triggered Hardware Limit Timer modes the counter is reset by high or low levels of the external signal
TMRx_ers, as shown in Figure 26-6. Selecting MODE = ‘b00110 will cause the timer to reset on a low-level external
signal. Selecting MODE = ‘b00111 will cause the timer to reset on a high-level external signal. In the example, the
counter is reset while TMRx_ers = 1. ON is controlled by BSF and BCF instructions. When ON = 0, the external signal
is ignored.
When the CCP uses the timer as the PWM time base, then the PWM output will be set high when the timer starts
counting and then set low only when the timer count matches the CCPRx value. The timer is reset when either the
timer count matches the TxPR value or two clock periods after the external Reset signal goes true and stays true.
The timer starts counting, and the PWM output is set high, on either the clock following the TxPR match or two clocks
after the external Reset signal relinquishes the Reset. The PWM output will remain high until the timer counts up to
match the CCPRx pulse-width value. If the external Reset signal goes true while the PWM output is high, then the
PWM output will remain high until the Reset signal is released allowing the timer to count up to match the CCPRx
value.
Figure 26-6. Level Triggered Hardware Limit Mode Timing Diagram
(MODE = ‘b00111)
Rev. 10-000 198C
3/5/201 9
TMRx_clk
TxPR
5
Instruction(1)
BSF
BCF
BSF
ON
TMRx_ers
TxTMR
0
1
2
0
1
2
3
4
5
0
0
1
2
3
4
5
0
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note
1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 432
PIC18F27/47/57Q84
TMR2 - Timer2 Module
26.8.5
Software Start One Shot Mode
In One Shot mode, the timer resets and the ON bit is cleared when the timer value matches the TxPR period value.
The ON bit must be set by software to start another timer cycle. Setting MODE = ‘b01000 selects One Shot mode
which is illustrated in Figure 26-7. In the example, ON is controlled by BSF and BCF instructions. In the first case, a
BSF instruction sets ON and the counter runs to completion and clears ON. In the second case, a BSF instruction
starts the cycle, the BCF/BSF instructions turn the counter off and on during the cycle, and then it runs to completion.
When One Shot mode is used in conjunction with the CCP PWM operation, the PWM pulse drive starts concurrent
with setting the ON bit. Clearing the ON bit while the PWM drive is active will extend the PWM drive. The PWM drive
will terminate when the timer value matches the CCPRx pulse-width value. The PWM drive will remain off until the
software sets the ON bit to start another cycle. If the software clears the ON bit after the CCPRx match but before the
TxPR match, then the PWM drive will be extended by the length of time the ON bit remains cleared. Another timing
cycle can only be initiated by setting the ON bit after it has been cleared by a TxPR period count match.
Figure 26-7. Software Start One Shot Mode Timing Diagram (MODE = ‘b01000)
Rev. 10-000 199C
3/6/201 9
TMRx_clk
TxPR
Instruction(1)
5
BSF
BSF
BCF
BSF
ON
TxTMR
0
1
2
3
4
5
0
1
2
3
4
5
0
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note
1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU
to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 433
PIC18F27/47/57Q84
TMR2 - Timer2 Module
26.8.6
Edge Triggered One Shot Mode
The Edge Triggered One Shot modes start the timer on an edge from the external signal input, after the ON bit is set,
and clear the ON bit when the timer matches the TxPR period value. The following edges will start the timer:
•
Rising edge (MODE = ‘b01001)
•
Falling edge (MODE = ‘b01010)
•
Rising or Falling edge (MODE = ‘b01011)
If the timer is halted by clearing the ON bit, then another TMRx_ers edge is required after the ON bit is set to resume
counting. Figure 26-8 illustrates operation in the rising edge One Shot mode.
When Edge Triggered One Shot mode is used in conjunction with the CCP, then the edge-trigger will activate the
PWM drive and the PWM drive will deactivate when the timer matches the CCPRx pulse width value and stay
deactivated when the timer halts at the TxPR period count match.
Figure 26-8. Edge Triggered One Shot Mode Timing Diagram (MODE = ‘b01001)
Rev. 10-000 200C
3/6/201 9
TMRx_clk
TxPR
Instruction(1)
5
BSF
BSF
BCF
ON
TMRx_ers
TxTMR
0
1
2
3
4
5
0
1
2
CCP_pset
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note
1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 434
PIC18F27/47/57Q84
TMR2 - Timer2 Module
26.8.7
Edge Triggered Hardware Limit One Shot Mode
In Edge Triggered Hardware Limit One Shot modes, the timer starts on the first external signal edge after the ON bit
is set and resets on all subsequent edges. Only the first edge after the ON bit is set is needed to start the timer. The
counter will resume counting automatically two clocks after all subsequent external Reset edges. Edge triggers are
as follows:
•
Rising edge start and Reset (MODE = ‘b01100)
•
Falling edge start and Reset (MODE = ‘b01101)
The timer resets and clears the ON bit when the timer value matches the TxPR period value. External signal edges
will have no effect until after software sets the ON bit. Figure 26-9 illustrates the rising edge hardware limit one-shot
operation.
When this mode is used in conjunction with the CCP, then the first starting edge trigger, and all subsequent Reset
edges, will activate the PWM drive. The PWM drive will deactivate when the timer matches the CCPRx pulse-width
value and stay deactivated until the timer halts at the TxPR period match unless an external signal edge resets the
timer before the match occurs.
Figure 26-9. Edge Triggered Hardware Limit One Shot Mode Timing Diagram (MODE = ‘b01100)
Rev. 10-000 201C
3/6/201 9
TMRx_clk
TxPR
Instruction(1)
5
BSF
BSF
ON
TMRx_ers
TxTMR
0
1
2
3
4
5
0
1
2
0
1
2
3
4
5
0
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note
1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 435
PIC18F27/47/57Q84
TMR2 - Timer2 Module
26.8.8
Level Reset, Edge Triggered Hardware Limit One Shot Modes
In Level Triggered One Shot mode, the timer count is reset on the external signal level and starts counting on the
rising/falling edge of the transition from Reset level to the active level while the ON bit is set. Reset levels are
selected as follows:
•
Low Reset level (MODE = ‘b01110)
•
High Reset level (MODE = ‘b01111)
When the timer count matches the TxPR period count, the timer is reset and the ON bit is cleared. When the ON bit
is cleared by either a TxPR match or by software control, a new external signal edge is required after the ON bit is set
to start the counter.
When Level-Triggered Reset One Shot mode is used in conjunction with the CCP PWM operation, the PWM drive
goes active with the external signal edge that starts the timer. The PWM drive goes inactive when the timer count
equals the CCPRx pulse width count. The PWM drive does not go active when the timer count clears at the TxPR
period count match.
Figure 26-10. Low Level Reset, Edge Triggered Hardware Limit One Shot Mode Timing Diagram (MODE =
‘b01110)
Rev. 10-000 202C
3/6/201 9
TMRx_clk
TxPR
Instruction(1)
5
BSF
BSF
ON
TMRx_ers
TxTMR
0
1
2
3
4
5
0
1
0
1
2
3
4
5
0
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note
1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 436
PIC18F27/47/57Q84
TMR2 - Timer2 Module
26.8.9
Edge-Triggered Monostable Modes
The Edge-Triggered Monostable modes start the timer on an edge from the external Reset signal input, after the ON
bit is set, and stop incrementing the timer when the timer matches the TxPR period value. The following edges will
start the timer:
•
Rising edge (MODE = ‘b10001)
•
Falling edge (MODE = ‘b10010)
•
Rising or Falling edge (MODE = ‘b10011)
When an Edge-Triggered Monostable mode is used in conjunction with the CCP PWM operation, the PWM drive
goes active with the external Reset signal edge that starts the timer, but will not go active when the timer matches
the TxPR value. While the timer is incrementing, additional edges on the external Reset signal will not affect the CCP
PWM.
Figure 26-11. Rising Edge-Triggered Monostable Mode Timing Diagram (MODE = ‘b10001)
Rev. 10-000203B
3/6/2019
TMRx_clk
5
TxPR
Instruction(1)
BSF
BCF
BSF
BCF
BSF
ON
TMRx_ers
TxTMR
0
1
2
3
4
5
0
1
2
3
4
5
0
1
2
3
4
5
0
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note
1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 437
PIC18F27/47/57Q84
TMR2 - Timer2 Module
26.8.10 Level Triggered Hardware Limit One Shot Modes
The Level Triggered Hardware Limit One Shot modes hold the timer in Reset on an external Reset level and start
counting when both the ON bit is set and the external signal is not at the Reset level. If one of either the external
signal is not in Reset or the ON bit is set, then the other signal being set/made active will start the timer. Reset levels
are selected as follows:
•
Low Reset level (MODE = ‘b10110)
•
High Reset level (MODE = ‘b10111)
When the timer count matches the TxPR period count, the timer is reset and the ON bit is cleared. When the ON bit
is cleared by either a TxPR match or by software control, the timer will stay in Reset until both the ON bit is set and
the external signal is not at the Reset level.
When Level Triggered Hardware Limit One Shot modes are used in conjunction with the CCP PWM operation, the
PWM drive goes active with either the external signal edge or the setting of the ON bit, whichever of the two starts
the timer.
Figure 26-12. Level Triggered Hardware Limit One Shot Mode Timing Diagram (MODE = ‘b10110)
Rev. 10-000 204B
3/6/201 9
TMRx_clk
TxPR
5
Instruction(1)
BSF
BSF
BCF
BSF
ON
TMRx_ers
TxTMR
0
1
2
3
4
5
0
1
2
3
0
1
2
3
4
5
0
TMRx_postscaled
PWM Duty
Cycle
D3
PWM Output
Note
26.9
1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
Timer2 Operation During Sleep
When PSYNC = 1, Timer2 cannot be operated while the processor is in Sleep mode. The contents of the T2TMR and
T2PR registers will remain unchanged while the processor is in Sleep mode.
When PSYNC = 0, Timer2 will operate in Sleep as long as the clock source selected is also still running. If any
internal oscillator is selected as the clock source, it will stay active during Sleep mode.
26.10
Register Definitions: Timer2 Control
Long bit name prefixes for the Timer2 peripherals are shown in the table below. Refer to the “Long Bit Names”
section in the “Register and Bit Naming Conventions” chapter for more information.
Table 26-2. Timer2 Long Bit Name Prefixes
Peripheral
Bit Name Prefix
Timer2
T2
Timer4
T4
Timer6
T6
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 438
PIC18F27/47/57Q84
TMR2 - Timer2 Module
Notice: References to module Timer2 apply to all the even numbered timers on this device. (Timer2,
Timer4, etc.)
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 439
PIC18F27/47/57Q84
TMR2 - Timer2 Module
26.10.1 TxTMR
Name:
Address:
TxTMR
0x322,0x32E,0x33A
Timer Counter Register
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TxTMR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – TxTMR[7:0] Timerx Counter
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 440
PIC18F27/47/57Q84
TMR2 - Timer2 Module
26.10.2 TxPR
Name:
Address:
TxPR
0x323,0x32F,0x33B
Timer Period Register
Bit
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
TxPR[7:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
Bits 7:0 – TxPR[7:0] Timer Period Register
Value
Description
0 - 255 The timer restarts at ‘0’ when TxTMR reaches TxPR value
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 441
PIC18F27/47/57Q84
TMR2 - Timer2 Module
26.10.3 TxCON
Name:
Address:
TxCON
0x324,0x330,0x33C
Timerx Control Register
Bit
Access
Reset
7
ON
R/W/HC
0
6
R/W
0
5
CKPS[2:0]
R/W
0
4
3
R/W
0
R/W
0
2
1
OUTPS[3:0]
R/W
R/W
0
0
0
R/W
0
Bit 7 – ON Timer On(1)
Value
Description
1
Timer is on
0
Timer is off: all counters and state machines are reset
Bits 6:4 – CKPS[2:0] Timer Clock Prescale Select
Value
Description
111
1:128 Prescaler
110
1:64 Prescaler
101
1:32 Prescaler
100
1:16 Prescaler
011
1:8 Prescaler
010
1:4 Prescaler
001
1:2 Prescaler
000
1:1 Prescaler
Bits 3:0 – OUTPS[3:0] Timer Output Postscaler Select
Value
Description
1111
1:16 Postscaler
1110
1:15 Postscaler
1101
1:14 Postscaler
1100
1:13 Postscaler
1011
1:12 Postscaler
1010
1:11 Postscaler
1001
1:10 Postscaler
1000
1:9 Postscaler
0111
1:8 Postscaler
0110
1:7 Postscaler
0101
1:6 Postscaler
0100
1:5 Postscaler
0011
1:4 Postscaler
0010
1:3 Postscaler
0001
1:2 Postscaler
0000
1:1 Postscaler
Note:
1. In certain modes, the ON bit will be auto-cleared by hardware. See Table 26-1.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 442
PIC18F27/47/57Q84
TMR2 - Timer2 Module
26.10.4 TxHLT
Name:
Address:
TxHLT
0x325,0x331,0x33D
Timer Hardware Limit Control Register
Bit
7
PSYNC
R/W
0
Access
Reset
6
CPOL
R/W
0
5
CSYNC
R/W
0
4
3
R/W
0
R/W
0
2
MODE[4:0]
R/W
0
1
0
R/W
0
R/W
0
Bit 7 – PSYNC Timer Prescaler Synchronization Enable(1, 2)
Value
Description
1
Timer Prescaler Output is synchronized to FOSC/4
0
Timer Prescaler Output is not synchronized to FOSC/4
Bit 6 – CPOL Timer Clock Polarity Selection(3)
Value
Description
1
Falling edge of input clock clocks timer/prescaler
0
Rising edge of input clock clocks timer/prescaler
Bit 5 – CSYNC Timer Clock Synchronization Enable(4, 5)
Value
Description
1
ON bit is synchronized to timer clock input
0
ON bit is not synchronized to timer clock input
Bits 4:0 – MODE[4:0] Timer Control Mode Selection(6, 7)
Value
Description
00000 to See Table 26-1
11111
Notes:
1. Setting this bit ensures that reading TxTMR will return a valid data value.
2. When this bit is ‘1’, the Timer cannot operate in Sleep mode.
3.
CKPOL must not be changed while ON = 1.
4.
5.
6.
Setting this bit ensures glitch-free operation when the ON is enabled or disabled.
When this bit is set, then the timer operation will be delayed by two input clocks after the ON bit is set.
Unless otherwise indicated, all modes start upon ON = 1 and stop upon ON = 0 (stops occur without affecting
the value of TxTMR).
When TxTMR = TxPR, the next clock clears TxTMR, regardless of the operating mode.
7.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 443
PIC18F27/47/57Q84
TMR2 - Timer2 Module
26.10.5 TxCLKCON
Name:
Address:
TxCLKCON
0x326,0x332,0x33E
Timer Clock Source Selection Register
Bit
7
6
5
Access
Reset
4
3
R/W
0
R/W
0
2
CS[4:0]
R/W
0
1
0
R/W
0
R/W
0
Bits 4:0 – CS[4:0] Timer Clock Source Selection
Table 26-3. Clock Source Selection
CS
11111-10110
10101
10100
10011
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
Timer2
Pin selected by T2INPPS
© 2021 Microchip Technology Inc.
Clock Source
Timer4
Reserved
CLC8_OUT
CLC7_OUT
CLC6_OUT
CLC5_OUT
CLC4_OUT
CLC3_OUT
CLC2_OUT
CLC1_OUT
ZCD_OUT
NCO3_OUT
NCO2_OUT
NCO1_OUT
CLKREF_OUT
EXTOSC
SOSC
MFINTOSC (32 kHz)
MFINTOSC (500 kHz)
LFINTOSC
HFINTOSC
FOSC
FOSC/4
Pin selected by T4INPPS
Preliminary Datasheet
Timer6
Pin selected by T6INPPS
DS40002213D-page 444
PIC18F27/47/57Q84
TMR2 - Timer2 Module
26.10.6 TxRST
Name:
Address:
TxRST
0x327,0x333,0x33F
Timer External Reset Signal Selection Register
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
RSEL[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 5:0 – RSEL[5:0] External Reset Source Selection
Table 26-4. External Reset Sources
RSEL
111111-100100
100011
100010
100001
100000
011111
011110
011101
011100
011011
011010
011001
011000
010111
010110
010101
010100
010011
010010
010001
010000
001111
001110
001101
001100
001011
001010
001001
001000
000111
000110
000101
000100
© 2021 Microchip Technology Inc.
TMR2
Reset Source
TMR4
Reserved
U5TX_Edge (Positive/Negative)
U5RX_Edge (Positive/Negative)
U4TX_Edge (Positive/Negative)
U4RX_Edge (Positive/Negative)
U3TX_Edge (Positive/Negative)
U3RX_Edge (Positive/Negative)
U2TX_Edge (Positive/Negative)
U2RX_Edge (Positive/Negative)
U1TX_Edge (Positive/Negative)
U1RX_Edge (Positive/Negative)
CLC8_OUT
CLC7_OUT
CLC6_OUT
CLC5_OUT
CLC4_OUT
CLC3_OUT
CLC2_OUT
CLC1_OUT
ZCD_OUT
CMP2_OUT
CMP1_OUT
PWM4S1P2_OUT
PWM4S1P1_OUT
PWM3S1P2_OUT
PWM3S1P1_OUT
PWM2S1P2_OUT
PWM2S1P1_OUT
PWM1S1P2_OUT
PWM1S1P1_OUT
CCP3_OUT
CCP2_OUT
CCP1_OUT
Preliminary Datasheet
TMR6
DS40002213D-page 445
PIC18F27/47/57Q84
TMR2 - Timer2 Module
...........continued
RSEL
000011
000010
000001
000000
TMR2
TMR6_Postscaler_OUT
TMR4_Postscaler_OUT
Reserved
Pin selected by T2INPPS
© 2021 Microchip Technology Inc.
Reset Source
TMR4
TMR6_Postscaler_OUT
Reserved
TMR2_Postscaler_OUT
Pin selected by T4INPPS
Preliminary Datasheet
TMR6
Reserved
TMR4_Postscaler_OUT
TMR2_Postscaler_OUT
Pin selected by T6INPPS
DS40002213D-page 446
PIC18F27/47/57Q84
TMR2 - Timer2 Module
26.11
Address
0x00
...
0x0321
0x0322
0x0323
0x0324
0x0325
0x0326
0x0327
0x0328
...
0x032D
0x032E
0x032F
0x0330
0x0331
0x0332
0x0333
0x0334
...
0x0339
0x033A
0x033B
0x033C
0x033D
0x033E
0x033F
Register Summary - Timer2
Name
Bit Pos.
7
6
5
4
3
2
1
0
Reserved
T2TMR
T2PR
T2CON
T2HLT
T2CLKCON
T2RST
7:0
7:0
7:0
7:0
7:0
7:0
T2TMR[7:0]
T2PR[7:0]
ON
PSYNC
CPOL
CKPS[2:0]
CSYNC
OUTPS[3:0]
MODE[4:0]
CS[4:0]
RSEL[5:0]
Reserved
T4TMR
T4PR
T4CON
T4HLT
T4CLKCON
T4RST
7:0
7:0
7:0
7:0
7:0
7:0
T4TMR[7:0]
T4PR[7:0]
ON
PSYNC
CPOL
CKPS[2:0]
CSYNC
OUTPS[3:0]
MODE[4:0]
CS[4:0]
RSEL[5:0]
Reserved
T6TMR
T6PR
T6CON
T6HLT
T6CLKCON
T6RST
7:0
7:0
7:0
7:0
7:0
7:0
T6TMR[7:0]
T6PR[7:0]
ON
PSYNC
© 2021 Microchip Technology Inc.
CPOL
CKPS[2:0]
CSYNC
Preliminary Datasheet
OUTPS[3:0]
MODE[4:0]
CS[4:0]
RSEL[5:0]
DS40002213D-page 447
PIC18F27/47/57Q84
SMT - Signal Measurement Timer
27.
SMT - Signal Measurement Timer
The Signal Measurement Timer (SMT) is a 24-bit counter with advanced clock and gating logic, which can be
configured for measuring a variety of digital signal parameters such as pulse width, frequency and duty cycle, and the
time difference between edges on two signals.
Features of the SMT include:
• 24-Bit Timer/Counter
• Two 24-Bit Measurement Capture Registers
• One 24-Bit Period Match Register
• Multi-Mode Operation, Including Relative Timing Measurement
• Interrupt-on-Period Match and Acquisition Complete
• Multiple Clock, Signal and Window Sources
Below is the block diagram for the SMT module.
Figure 27-1. Signal Measurement Timer Block Diagram
Rev. 10-000161E
11/13/2018
Period Latch
SMT_window
SMT
Clock
Sync
Circuit
SMT_signal
SMT
Clock
Sync
Circuit
Set SMTxPRAIF
SMTxPR
Control
Logic
Set SMTxIF
Comparator
Reset
Enable
SMT
Clock
Sources
Prescaler
SMTxTMR
Window Latch
24-bit
Buffer
SMTxCPR
24-bit
Buffer
SMTxCPW
Set SMTxPWAIF
CSEL
27.1
SMT Operation
27.1.1
Clock Source Selection
The SMT clock source is selected by configuring the CSEL bits. The clock source is prescaled by using the PS bits.
The prescaled clock source is used to clock both the counter and any synchronization logic used by the module.
The polarity of the clock source is selected by using the CPOL bit.
27.1.2
Signal and Window Source Selection
The SMT signal and window sources are selected by configuring the SSEL bits and the WSEL bits (refer to the figure
below).
The polarity of the signal and window sources is selected by using the SPOL and WPOL bits, respectively.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 448
PIC18F27/47/57Q84
SMT - Signal Measurement Timer
Figure 27-2. SMT Signal and SMT Window Source Selections
Rev. 10-000173D
11/13/2018
See
SMTxSIG
Register
SMT_signal
SMT_window
WSEL
SSEL
27.1.3
See
SMTxWIN
Register
Time Base
The SMTxTMR register is the 24-bit counter/timer used for measurement in each of the modes of the SMT. Setting
the RST bit clears the SMTxTMR register to 0x000000. It can be written to and read by software. It is not guarded for
atomic access, therefore reads and writes to the SMTxTMR register must be made only when GO = 0.
The counter can be prevented from resetting at the end of the timer period by using the STP bit. When STP = 1,
the SMTxTMR will stop and remain equal to the SMTxPR register. When STP = 0, the SMTxTMR register resets to
0x000000 at the end of the period.
27.1.4
Pulse Width and Period Captures
The SMTxCPW and SMTxCPR registers are used to latch in the value of the SMTxTMR register, based on the SMT
mode of operation. These registers can also be updated with the current value of the SMTxTMR value by setting the
CPWUP and CPRUP bits, respectively.
27.1.5
Status Information
The SMT provides input status information for the user without requiring the need to monitor the raw incoming
signals.
Go Status: Timer run status is indicated by the TS bit. The TS bit is delayed in time by synchronizer delays in
non-counter modes.
Signal Status: Signal status is indicated by the AS bit. This bit is used in all modes, except Window Measure, Timeof-Flight, and Capture modes, and is only valid when TS = 1. The signal status is delayed in time by synchronizer
delays in non-counter modes.
Window Status: Window status is indicated by the WS bit. This bit is only used in Windowed Measure, Gated
Counter, and Gated Window Measure modes, and is only valid when TS = 1. Window status is delayed in time by
synchronizer delays in non-counter modes.
27.1.6
Modes of Operation
The modes of operation are summarized in the table below. The sections following the table provide descriptions and
examples of how each mode can be used. Note that all waveforms assume WPOL/SPOL/CPOL = 0.
For all modes, the REPEAT bit controls whether the acquisition happens only once or is repeated. When REPEAT =
0 (Single Acquisition mode), the timer will stop incrementing and the GO bit will be cleared upon the completion of
an acquisition. Otherwise, the timer will continue and allow for continued acquisitions to overwrite the previous ones,
until the timer is stopped by software.
Table 27-1. Modes of Operation
MODE
Mode of Operation
Synchronous Operation
1111-1011
Reserved
-
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 449
PIC18F27/47/57Q84
SMT - Signal Measurement Timer
...........continued
MODE
Mode of Operation
Synchronous Operation
1010
Windowed Counter
No
1001
Gated Counter
No
1000
Counter
No
0111
Capture
Yes
0110
Time of Flight Measurement
Yes
0101
Gated Windowed Measurement
Yes
0100
Windowed Measurement
Yes
0011
High and Low Time Measurement
Yes
0010
Period and Duty Cycle Measurement
Yes
0001
Gated Timer
Yes
0000
Timer
Yes
27.1.6.1 Timer Mode
Timer mode is the basic mode of operation where the SMTxTMR register is used as a 24-bit timer. No data
acquisition takes place in this mode. The timer increments as long as the GO bit has been set by software. No SMT
window or SMT signal events affect the GO bit. Everything is synchronized to the SMT clock source. When the timer
experiences a period match (SMTxTMR = SMTxPR), the SMTxTMR register is reset and the period match interrupt is
set. Refer to the figure below.
Figure 27-3. Timer Mode Timing Diagram
Rev. 10-000174A
11/13/2018
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxPR
SMTxTMR
11
0
1
2
3
4
5
6
7
8
9 10 11 0
1
2
3
4
5
6
7
8
9
SMTxIF
27.1.6.2 Gated Timer Mode
Gated Timer mode uses the SMT_signal input, selected with the SSEL bits, to control whether or not the SMTxTMR
register will increment. Upon a falling edge of the signal, the SMTxCPW register will update to the current value of the
SMTxTMR register. Example waveforms for both repeated and single acquisitions are provided in the figures below.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 450
PIC18F27/47/57Q84
SMT - Signal Measurement Timer
Figure 27-4. Gated Timer Mode, Repeat Acquisition Timing Diagram
Rev. 10-000176A
11/15/2018
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
0xFFFFFF
SMTxPR
0
SMTxTMR
1
2
3
4
5
6
7
5
SMTxCPW
7
SMTxPWAIF
Figure 27-5. Gated Timer Mode, Single Acquisition Timing Diagram
Rev. 10-000175A
11/15/2018
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxPR
SMTxTMR
0xFFFFFF
0
1
2
3
4
5
SMTxCPW
5
SMTxPWAIF
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 451
PIC18F27/47/57Q84
SMT - Signal Measurement Timer
27.1.6.3 Period and Duty Cycle Measurement Mode
In this mode, either the duty cycle or period of the input signal can be acquired relative to the SMT clock. The
SMTxCPW register is updated on a falling edge of the signal, and the SMTxCPR register is updated on a rising edge
of the signal. The rising edge also resets the SMTxTMR register to 0x000001. The GO bit is reset on a rising edge
when the SMT is in Single Acquisition mode. Refer to the figures below.
Figure 27-6. Period and Duty Cycle, Repeat Acquisition Mode Timing Diagram
Rev. 10-000177A
11/15/2018
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR
0
1
2
3
4
5
6
7
8
SMTxCPW
9 10 11 1
2
3
4
5
5
2
SMTxCPR
11
SMTxPWAIF
SMTxPRAIF
Figure 27-7. Period and Duty Cycle, Single Acquisition Mode Timing Diagram
Rev. 10-000178A
11/15/2018
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR
0
1
2
3
4
5
6
SMTxCPW
7
8
9 10 11
1
5
SMTxCPR
11
SMTxPWAIF
SMTxPRAIF
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 452
PIC18F27/47/57Q84
SMT - Signal Measurement Timer
27.1.6.4 High and Low Measurement Mode
This mode measures the high and low pulse time of the SMT_signal, relative to the SMT clock. The SMTxTMR
register starts incrementing on a rising edge of the input signal. On the falling edge, the SMTxTMR register value
is written to the SMTxCPW register. The SMTxTMR register is then reset and continues to increment. On the next
rising edge, the SMTxTMR register value is written to the SMTxCPR register. The SMTxTMR register is then reset
and continues to increment. Refer to the figures below.
Figure 27-8. High and Low Measurement Mode, Repeat Acquisition Timing Diagram
Rev. 10-000180A
11/15/2018
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR
0
1
2
3
4
5
1
2
3
SMTxCPW
4
5
6
1
2
1
2
3
5
2
SMTxCPR
6
SMTxPWAIF
SMTxPRAIF
Figure 27-9. High and Low Measurement Mode, Single Acquisition Timing Diagram
Rev. 10-000179A
11/15/2018
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR
0
1
2
3
4
5
1
SMTxCPW
2
3
4
5
6
5
SMTxCPR
6
SMTxPWAIF
SMTxPRAIF
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 453
PIC18F27/47/57Q84
SMT - Signal Measurement Timer
27.1.6.5 Windowed Measurement Mode
This mode measures the period of the SMT_window input, selected with the WSEL bits, relative to the SMT clock.
On the rising edge of the window input, the SMTxTMR register value is written to the SMTxCPR register. In Repeat
mode, the SMTxTMR register is reset and continues to increment. The capture and reset process repeats on the next
rising edge. Refer to the figures below.
Figure 27-10. Windowed Measurement Mode, Repeat Acquisition Timing Diagram
Rev. 10-000182A
11/15/2018
SMTxWIN
SMTxWIN_sync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR
0
1
2
3
4
5
6
7
8
9 10 11 12 1
2
3
4
5
6
7
8
12
SMTxCPR
1
2
3
4
8
SMTxPRAIF
Figure 27-11. Windowed Measurement Mode, Single Acquisition Timing Diagram
Rev. 10-000181A
11/15/2018
SMTxWIN
SMTxWIN_sync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR
0
1
2
3
4
5
6
7
8
9 10 11 12
SMTxCPR
12
SMTxPRAIF
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 454
PIC18F27/47/57Q84
SMT - Signal Measurement Timer
27.1.6.6 Gated Window Measurement Mode
This mode measures the duty cycle of the SMT_signal input over a known input window. It does so by incrementing
the SMTxTMR register on each rising edge of the SMTx clock signal when the SMT_signal input is high. The
accumulated SMTxTMR register value is written to the SMTxCPR register, and the SMTxTMR register is reset on
every rising edge of the window input after the first. Refer to the figures below.
Figure 27-12. Gated Windowed Measurement Mode, Repeat Acquisition Timing Diagram
Rev. 10-000184A
11/15/2018
SMTxWIN
SMTxWIN_sync
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR
0
1
2
3
4
5
6
0
1
2
3
6
SMTxCPR
0
3
SMTxPRAIF
Figure 27-13. Gated Windowed Measurement Mode, Single Acquisition Timing Diagram
Rev. 10-000183A
11/15/2018
SMTxWIN
SMTxWIN_sync
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR
0
1
2
3
4
5
6
6
SMTxCPR
SMTxPRAIF
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 455
PIC18F27/47/57Q84
SMT - Signal Measurement Timer
27.1.6.7 Time-of-Flight Measurement Mode
This mode measures the time interval between a rising edge on the SMT_window input and a rising edge on the
SMT_signal input. The SMTxTMR register starts incrementing on the rising edge of the window input. The SMTxTMR
register value is written to the SMTxCPR register and the SMTxTMR register is reset on a rising edge of the signal
input. In the event of two rising edges of the window signal without a signal rising edge, the SMTxCPW register will
be written with the current value of the SMTxTMR register, which will then be reset. Refer to the figures below.
Figure 27-14. Time-of-Flight Mode, Repeat Acquisition Timing Diagram
Rev. 10-000186A
11/15/2018
SMTxWIN
SMTxWIN_sync
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR
0
1
2
3
4
5
1
2
3
4
5
6
7
8
9 10 11 12 13 1
2
13
SMTxCPW
SMTxCPR
4
SMTxPWAIF
SMTxPRAIF
Figure 27-15. Time-of-Flight Mode, Single Acquisition Timing Diagram
Rev. 10-000185A
11/15/2018
SMTxWIN
SMTxWIN_sync
SMTx_signal
SMTx_signalsync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR
0
1
2
3
4
5
SMTxCPW
SMTxCPR
4
SMTxPWAIF
SMTxPRAIF
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 456
PIC18F27/47/57Q84
SMT - Signal Measurement Timer
27.1.6.8 Capture Mode
This mode captures the SMTxTMR register value based on a rising or falling edge of the SMT_window input and
triggers an interrupt. This mimics the capture feature of a CCP module. The timer begins incrementing upon the
GO bit being set. The SMTxTMR register value is written to the SMTxCPR register on each rising edge of the
SMT_window input. The SMTxTMR register value is written to the SMTxCPW register on each falling edge of the
SMT_window input. The timer is not reset by any hardware conditions in this mode and must be reset by software, if
desired. Refer to the figures below.
Figure 27-16. Capture Mode, Repeat Acquisition Timing Diagram
Rev. 10-000188A
11/15/2018
SMTxWIN
SMTxWIN_sync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
3
SMTxCPW
SMTxCPR
19
2
18
32
31
SMTxPWAIF
SMTxPRAIF
Figure 27-17. Capture Mode, Single Acquisition Timing Diagram
Rev. 10-000187A
11/15/2018
SMTxWIN
SMTxWIN_sync
SMTx Clock
SMTxEN
SMTxGO
SMTxGO_sync
SMTxTMR
0
1
2
3
3
SMTxCPW
SMTxCPR
2
SMTxPWAIF
SMTxPRAIF
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 457
PIC18F27/47/57Q84
SMT - Signal Measurement Timer
27.1.6.9 Counter Mode
This mode increments the SMTxTMR register on each rising edge of the SMT_signal input. This mode is
asynchronous to the SMT clock and uses the SMT_signal input as a time source. The SMTxCPW register will
be updated with the current SMTxTMR register value on the falling edge of the SMT_window input. Refer to the
figure below.
Figure 27-18. Counter Mode Timing Diagram
Rev. 10-000189A
11/15/2018
SMTxWIN
SMTx_signal
SMTxEN
SMTxGO
SMTxTMR
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
SMTxCPW
12
27
25
27.1.6.10 Gated Counter Mode
This mode counts rising edges on the SMT_signal input, gated by the SMT_window input. It increments the
SMTxTMR register for each rising edge of the SMT_signal input while the SMT_window input is high. The SMTxTMR
register value is written to the SMTxCPW register upon a falling edge of the SMT_window input. Refer to the figures
below.
Figure 27-19. Gated Counter Mode, Repeat Acquisition Timing Diagram
Rev. 10-000190A
11/15/2018
SMTxWIN
SMTx_signal
SMTxEN
SMTxGO
SMTxTMR
0
1
2
3
4
5
6
7
8
SMTxCPW
9 10 11 12
8
13
13
SMTxPWAIF
Figure 27-20. Gated Counter Mode, Single Acquisition Timing Diagram
Rev. 10-000191A
11/15/2018
SMTxWIN
SMTx_signal
SMTxEN
SMTxGO
SMTxTMR
0
1
2
3
4
5
6
7
SMTxCPW
8
8
SMTxPWAIF
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 458
PIC18F27/47/57Q84
SMT - Signal Measurement Timer
27.1.6.11 Windowed Counter Mode
This mode counts rising edges of the SMT_signal between rising edges of the SMT_window input. Beginning with the
rising edge of the SMT_window input, the SMTxTMR register is incremented for every rising edge of the SMT_signal
input. The SMTxTMR register value is written to the SMTxCPW register on the falling edge of the SMT_window input
and the SMTxTMR register continues to increment. The SMTxTMR register value is written to the SMTxCPR register,
then reset on each rising edge of the SMT_window input after the first. Refer to the figures below.
Figure 27-21. Windowed Counter Mode, Repeat Acquisition Timing Diagram
Rev. 10-000192A
11/15/2018
SMTxWIN
SMTx_signal
SMTxEN
SMTxGO
SMTxTMR
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 1
SMTxCPW
2
3
4
9
5
5
16
SMTxCPR
SMTxPWAIF
SMTxPRAIF
Figure 27-22. Windowed Counter Mode, Single Acquisition Timing Diagram
Rev. 10-000193A
11/15/2018
SMTxWIN
SMTx_signal
SMTxEN
SMTxGO
SMTxTMR
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
SMTxCPW
9
16
SMTxCPR
SMTxPWAIF
SMTxPRAIF
27.1.7
Interrupts
The SMT has three interrupts located in one of the PIR registers:
• Pulse-Width Acquisition Interrupt (SMTxPWAIF): Interrupt triggers when the SMTxCPW register is updated
with the SMTxTMR register value.
• Period Acquisition Interrupt (SMTxPRAIF): Interrupt triggers when the SMTxCPR register is updated with the
SMTxTMR register value.
• Counter Period Match Interrupt (SMTxIF): Interrupt triggers when the SMTxTMR register equals the SMTxPR
register.
Each of the above interrupts can be enabled/disabled using the corresponding bits in the PIE register.
27.1.8
Operation During Sleep
The SMT can operate during Sleep mode, provided that the clock and signal sources continue to function. In general,
internal clock sources, such as HFINTOSC, continue to operate in Sleep mode when selected as the clock source,
whereas external oscillators, such as FOSC and FOSC/4 cease to operate in Sleep.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 459
PIC18F27/47/57Q84
SMT - Signal Measurement Timer
27.2
Register Definitions: SMT Control
Long bit name prefixes for the SMT peripherals are shown in the table below. Replace the x in SMTx with the
SMT peripheral instance number. Refer to the “Long Bit Names” section in the “Register and Nit Naming
Conventions” chapter for more information.
Table 27-2. SMT Long Bit Name Prefixes
Peripheral
Bit Name Prefix
SMT1
SMT1
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 460
PIC18F27/47/57Q84
SMT - Signal Measurement Timer
27.2.1
SMTxCON0
Name:
Address:
SMTxCON0
0x030C
SMT Control Register 0
Bit
Access
Reset
7
EN
R/W
0
6
5
STP
R/W
0
4
WPOL
R/W
0
3
SPOL
R/W
0
2
CPOL
R/W
0
1
0
PS[1:0]
R/W
0
R/W
0
Bit 7 – EN SMT Enable
Value
Description
1
SMT is enabled
0
SMT is disabled; internal states are reset, clock requests are disabled
Bit 5 – STP SMT Counter Halt Enable
Value
Condition
Description
1
When SMTxTMR = SMTxPR Counter remains at SMTxPR; period match interrupt occurs when
clocked
0
When SMTxTMR = SMTxPR Counter resets to 0x000000; period match interrupt occurs when
clocked
Bit 4 – WPOL SMT_window Input Polarity Control
Value
Description
1
SMT_window input is active-low/falling edge enabled
0
SMT_window input is active-high/rising edge enabled
Bit 3 – SPOL SMT_signal Input Polarity Control
Value
Description
1
SMT_signal input is active-low/falling edge enabled
0
SMT_signal input is active-high/rising edge enabled
Bit 2 – CPOL SMT Clock Input Polarity Control
Value
Description
1
SMTxTMR increments on the falling edge of the selected clock signal
0
SMTxTMR increments on the rising edge of the selected clock signal
Bits 1:0 – PS[1:0] SMT Prescale Select
Value
Description
11
Prescaler = 1:8
10
Prescaler = 1:4
01
Prescaler = 1:2
00
Prescaler = 1:1
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 461
PIC18F27/47/57Q84
SMT - Signal Measurement Timer
27.2.2
SMTxCON1
Name:
Address:
SMTxCON1
0x030D
SMT Control Register 1
Bit
Access
Reset
7
GO
R/W
0
6
REPEAT
R/W
0
5
4
3
2
1
0
R/W
0
R/W
0
MODE[3:0]
R/W
0
R/W
0
Bit 7 – GO SMT GO Data Acquisition
Value
Description
1
Incrementing, acquiring data is enabled
0
Incrementing, acquiring data is disabled
Bit 6 – REPEAT SMT Repeat Acquisition Enable
Value
Description
1
Repeat Data Acquisition mode is enabled
0
Single Acquisition mode is enabled
Bits 3:0 – MODE[3:0] SMT Operation Mode Select
Value
Description
1111
Reserved
1110
Reserved
1101
Reserved
1100
Reserved
1011
Reserved
1010
Windowed Counter
1001
Gated Counter
1000
Counter
0111
Capture
0110
Time-of-Flight
0101
Gated Windowed Measurement
0100
Windowed Measurement
0011
High and Low Time Measurement
0010
Period and Duty-Cycle Acquisition
0001
Gated Timer
0000
Timer
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 462
PIC18F27/47/57Q84
SMT - Signal Measurement Timer
27.2.3
SMTxSTAT
Name:
Address:
SMTxSTAT
0x030E
SMT Status Register
Bit
Access
Reset
7
CPRUP
R/W/HC
0
6
CPWUP
R/W/HC
0
5
4
RST
R/W
0
3
2
TS
R
0
1
WS
R
0
0
AS
R
0
Bit 7 – CPRUP SMT Manual Period Buffer Update
Value
Description
1
Request write of SMTxTMR value to SMTxCPR registers
0
SMTxCPR registers update is complete
Bit 6 – CPWUP SMT Manual Pulse Width Buffer Update
Value
Description
1
Request write of SMTxTMR value to SMTxCPW registers
0
SMTxCPW registers update is complete
Bit 4 – RST SMT Manual Timer Reset
Value
Description
1
Request Reset to SMTxTMR registers
0
SMTxTMR registers update is complete
Bit 2 – TS SMT GO Value Status
Value
Description
1
SMTxTMR is incrementing
0
SMTxTMR is not incrementing
Bit 1 – WS SMT Window Status
Value
Description
1
SMT window is open
0
SMT window is closed
Bit 0 – AS SMT Signal Value Status
Value
Description
1
SMT acquisition is in progress
0
SMT acquisition is not in progress
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 463
PIC18F27/47/57Q84
SMT - Signal Measurement Timer
27.2.4
SMTxCLK
Name:
Address:
SMTxCLK
0x030F
SMT Clock Selection Register
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
CSEL[3:0]
Access
Reset
R/W
0
R/W
0
Bits 3:0 – CSEL[3:0] SMT Clock Selection
CSEL Value
1111-1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
© 2021 Microchip Technology Inc.
SOURCE
Reserved
CLKR
EXTOSC
SOSC
MFINTOSC (32 kHz)
MFINTOSC (500 kHz)
LFINTOSC
HFINTOSC
FOSC
FOSC/4
Preliminary Datasheet
Active in Sleep
No
No
Yes
Yes
Yes
Yes
Yes
Yes
No
No
DS40002213D-page 464
PIC18F27/47/57Q84
SMT - Signal Measurement Timer
27.2.5
SMTxWIN
Name:
Address:
SMTxWIN
0x0311
SMT Window Input Select Register
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
WSEL[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 5:0 – WSEL[5:0] SMT Window Signal Selection
WSEL Value
111111-101000
100111
100110
100101
100100
100011
100010
100001
100000
011111
011110
011101
011100
011011
011010
011001
011000
010111
010110
010101
010100
010011
010010
010001
010000
001111
001110-001100
001011
001010
001001
001000
000111
000110
000101
000100
© 2021 Microchip Technology Inc.
Window Source
Reserved
CLC8_OUT
CLC7_OUT
CLC6_OUT
CLC5_OUT
CLC4_OUT
CLC3_OUT
CLC2_OUT
CLC1_OUT
ZCD_OUT
CMP2_OUT
CMP1_OUT
NCO3_OUT
NCO2_OUT
NCO1_OUT
PWM4S1P2_OUT
PWM4S1P1_OUT
PWM3S1P2_OUT
PWM3S1P1_OUT
PWM2S1P2_OUT
PWM2S1P1_OUT
PWM1S1P2_OUT
PWM1S1P1_OUT
CCP3_OUT
CCP2_OUT
CCP1_OUT
Reserved
TU16B_OUT
TU16A_OUT
TMR6_Postscaler_OUT
TMR4_Postscaler_OUT
TMR2_Postscaler_OUT
TMR0_OUT
CLKREF
EXTOSC
Preliminary Datasheet
Active in Sleep
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
DS40002213D-page 465
PIC18F27/47/57Q84
SMT - Signal Measurement Timer
...........continued
WSEL Value
000011
000010
000001
000000
© 2021 Microchip Technology Inc.
Window Source
SOSC
MFINTOSC (32 kHz)
LFINTOSC
SMT1WINPPS
Preliminary Datasheet
Active in Sleep
Yes
Yes
Yes
No
DS40002213D-page 466
PIC18F27/47/57Q84
SMT - Signal Measurement Timer
27.2.6
SMTxSIG
Name:
Address:
SMTxSIG
0x0310
SMT Signal Selection Register
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
SSEL[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 5:0 – SSEL[5:0] SMT Signal Selection
SSEL Value
111111-100110
100101
100100
100011
100010
100001
100000
011111
011110
011101
011100
011011
011010
011001
011000
010111
010110
010101
010100
010011
010010
010001
010000
001111
001110
001101
001100-001010
001001
001000
000111
000110
000101
000100
000011
000010
© 2021 Microchip Technology Inc.
Source
Reserved
CLC8_OUT
CLC7_OUT
CLC6_OUT
CLC5_OUT
CLC4_OUT
CLC3_OUT
CLC2_OUT
CLC1_OUT
ZCD_OUT
CMP2_OUT
CMP1_OUT
NCO3_OUT
NCO2_OUT
NCO1_OUT
PWM4S1P2_OUT
PWM4S1P1_OUT
PWM3S1P2_OUT
PWM3S1P1_OUT
PWM2S1P2_OUT
PWM2S1P1_OUT
PWM1S1P2_OUT
PWM1S1P1_OUT
CCP3_OUT
CCP2_OUT
CCP1_OUT
Reserved
TU16B_OUT
TU16A_OUT
TMR6_Postscaler_OUT
TMR5_OUT
TMR4_Postscaler_OUT
TMR3_OUT
TMR2_Postscaler_OUT
TMR1_OUT
Preliminary Datasheet
DS40002213D-page 467
PIC18F27/47/57Q84
SMT - Signal Measurement Timer
...........continued
SSEL Value
000001
000000
© 2021 Microchip Technology Inc.
Source
TMR0_OUT
SMT1SIGPPS
Preliminary Datasheet
DS40002213D-page 468
PIC18F27/47/57Q84
SMT - Signal Measurement Timer
27.2.7
SMTxTMR
Name:
Address:
SMTxTMR
0x0300
SMT Timer Register
Bit
23
22
21
20
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TMR[23:16]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
TMR[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
TMR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 23:0 – TMR[23:0] SMT Timer Value
Notes: The individual bytes in this multi-byte register can be accessed with the following register names:
• SMTxTMRU: Accesses the upper byte TMR[23:16]
• SMTxTMRH: Accesses the high byte TMR[15:8]
• SMTxTMRL: Accesses the low byte TMR[7:0]
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 469
PIC18F27/47/57Q84
SMT - Signal Measurement Timer
27.2.8
SMTxCPR
Name:
Address:
SMTxCPR
0x0303
SMT Captured Period Register
Bit
23
22
21
20
19
18
17
16
R
x
R
x
R
x
R
x
11
10
9
8
R
x
R
x
R
x
R
x
3
2
1
0
R
x
R
x
R
x
R
x
CPR[23:16]
Access
Reset
R
x
R
x
R
x
R
x
Bit
15
14
13
12
CPR[15:8]
Access
Reset
R
x
R
x
R
x
R
x
Bit
7
6
5
4
CPR[7:0]
Access
Reset
R
x
R
x
R
x
R
x
Bits 23:0 – CPR[23:0] SMTxTMR Value at Time of Period Capture Event
Reset States: POR/BOR = xxxxxxxxxxxxxxxxxxxxxxxx
All Other Resets = uuuuuuuuuuuuuuuuuuuuuuuu
Notes: The individual bytes in this multi-byte register can be accessed with the following register names:
• SMTxCPRU: Accesses the upper byte CPR[23:16]
• SMTxCPRH: Accesses the high byte CPR[15:8]
• SMTxCPRL: Accesses the low byte CPR[7:0]
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 470
PIC18F27/47/57Q84
SMT - Signal Measurement Timer
27.2.9
SMTxCPW
Name:
Address:
SMTxCPW
0x0306
SMT Captured Pulse Width Register
Bit
23
22
21
20
19
18
17
16
R
x
R
x
R
x
R
x
11
10
9
8
R
x
R
x
R
x
R
x
3
2
1
0
R
x
R
x
R
x
R
x
CPW[23:16]
Access
Reset
R
x
R
x
R
x
R
x
Bit
15
14
13
12
CPW[15:8]
Access
Reset
R
x
R
x
R
x
R
x
Bit
7
6
5
4
CPW[7:0]
Access
Reset
R
x
R
x
R
x
R
x
Bits 23:0 – CPW[23:0] SMTxTMR Value at Time of Capture Event
Reset States: POR/BOR = xxxxxxxxxxxxxxxxxxxxxxxx
All Other Resets = uuuuuuuuuuuuuuuuuuuuuuuu
Notes: The individual bytes in this multi-byte register can be accessed with the following register names:
• SMTxCPWU: Accesses the upper byte CPW[23:16]
• SMTxCPWH: Accesses the high byte CPW[15:8]
• SMTxCPWL: Accesses the low byte CPW[7:0]
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 471
PIC18F27/47/57Q84
SMT - Signal Measurement Timer
27.2.10 SMTxPR
Name:
Address:
SMTxPR
0x0309
SMT Period Register
Bit
23
22
21
20
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
11
10
9
8
R/W
1
R/W
1
R/W
1
R/W
1
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
PR[23:16]
Access
Reset
Bit
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
PR[15:8]
Access
Reset
Bit
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
PR[7:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
Bits 23:0 – PR[23:0] The SMTxTMR Value at Which the SMTxTMR Resets to Zero
Notes: The individual bytes in this multi-byte register can be accessed with the following register names:
• SMTxPRU: Accesses the upper byte PR[23:16]
• SMTxPRH: Accesses the high byte PR[15:8]
• SMTxPRL: Accesses the low byte PR[7:0]
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 472
PIC18F27/47/57Q84
SMT - Signal Measurement Timer
27.3
Register Summary - SMT Control
Address
Name
0x00
...
0x02FF
Reserved
0x0300
SMT1TMR
0x0303
SMT1CPR
0x0306
SMT1CPW
0x0309
SMT1PR
0x030C
0x030D
0x030E
0x030F
0x0310
0x0311
SMT1CON0
SMT1CON1
SMT1STAT
SMT1CLK
SMT1SIG
SMT1WIN
Bit Pos.
7:0
15:8
23:16
7:0
15:8
23:16
7:0
15:8
23:16
7:0
15:8
23:16
7:0
7:0
7:0
7:0
7:0
7:0
7
EN
GO
CPRUP
© 2021 Microchip Technology Inc.
6
5
STP
REPEAT
CPWUP
4
3
2
1
0
TMR[7:0]
TMR[15:8]
TMR[23:16]
CPR[7:0]
CPR[15:8]
CPR[23:16]
CPW[7:0]
CPW[15:8]
CPW[23:16]
PR[7:0]
PR[15:8]
PR[23:16]
WPOL
SPOL
RST
Preliminary Datasheet
CPOL
PS[1:0]
MODE[3:0]
TS
WS
CSEL[3:0]
SSEL[5:0]
WSEL[5:0]
AS
DS40002213D-page 473
PIC18F27/47/57Q84
UTMR - Universal Timer Module
28.
UTMR - Universal Timer Module
The UTMR Universal Timer module is a 16-bit timer/counter with a combination of signal measurement and hardware
limit timer functions. It is designed to provide all timer/counter related functions in a single peripheral and includes the
following list of features:
•
•
•
•
•
•
Host/Client chaining, which allows two timer/counters to be combined into a single larger timer/counter with a
single set of control registers
Software independent operation, including both signal measurement and hardware limit features
– External Reset (ERS) inputs
– Individual control of Start, Stop and Reset
– Hardware Limit mode
– One Shot mode
Full asynchronous clocking
– Multiple clock selections
– Synchronization circuitry for control bit and ERS inputs
– Integrated fully programmable prescaler
Dual Output modes
– Pulse output
– Level output
– Output polarity control
Double-buffered period register
– Compatible with DMA control
– Interrupt, Stop or Reset On Match
Interrupt on Start, Stop and Reset
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 474
© 2021 Microchip Technology Inc.
Figure 28-1. Universal Timer Block Diagram
Timer Clock
Selections
TUxyCLK
rotatethispage90
timer clock
Prescaler Block
CPOL
Prescaler Register
TUxyPS
External Input
Sources
TUxyERS
prescaled clock
RUN
CLR
reset
Edge Detection
Edge/Level Polarity
Synchronization
ers
reset
start
stop
S
Q
run/stop
Counter Block
Counter Register
TUxyTMR
count_en
R
zero
capture
CAPT
Capture Register
TUxyCR
0
1
RDSEL
Comparator
PR match
0
OPOL
OM
DS40002213D-page 475
off
OSEN
Module
Enable
Disable
ON
Counter
Prescaler
Period Register
TUxyPR
(Double Buffered)
Interrupt Trigger
DMA Trigger
PRIF
CIF
ZIF
Interrupt
Enable
TUxyIF
To PIRx
PRIFDMA
CIFDMA
ZIFDMA
PIC18F27/47/57Q84
TUxy_OUT
1
UTMR - Universal Timer Module
Preliminary Datasheet
START
STOP
RESET
EPOL
CSYNC
PIC18F27/47/57Q84
UTMR - Universal Timer Module
28.1
Module Nomenclature
The following nomenclature is used for this module on this device:
Table 28-1. Module Nomenclature
28.2
Timer Size (x)
Instance (y)
Module (TUxy)
16 bits
A
TU16A
16 bits
B
TU16B
Clock Source Selection
The TUxyCLK register bits select the clock source for the UTMR module. These bits allow the selection of several
possible synchronous and asynchronous clock sources. Because the selected clock source also controls the optional
synchronization of all external signals for the UTMR module, delays between the selection of a function and its action
may vary according to the frequency of the selected clock source relative to the microcontroller’s clock frequency.
See Synchronous vs. Asynchronous Operation for more details.
When an internal clock source is selected (clock derived from system oscillator), the choice of clock source will affect
the increment rate of the TUxyTMR register, relative to the system instruction rate. When an external clock source is
selected (a clock not derived from the system oscillator), the UTMR module will work as either a timer or a counter.
When enabled to count and the CPOL bit is set, the TUxyTMR counter register is incremented on the rising edge of
the selected external source. For increment on the falling edge of the selected external clock source, the CPOL bit
must be cleared. When operating from an external clock source, the CSYNC bit needs to also be set to synchronize
the controls and ERS signals to the clock domain of the selected external clock.
Important: Due to the inherent uncertainty of reading or writing a 16-bit timer with an 8-bit bus and
operating from an asynchronous clock source, it is recommended that read/write of the timer registers use
the CAPT and the CLR commands. Refer to Timer Counter and Capture Registers for more information.
28.3
UTMR Prescaler
The UTMR module has a fully programmable 8-bit prescaler, allowing division of the clock input by 1 to 256. The
prescaler register TUxyPS is programmed with the desired prescaler value minus one. For example, for a 10:1
prescaler value, the TUxyPS register would be loaded with 0x09. The internal prescaler counter is not directly
readable or writable; however, the prescaler counter is cleared upon a Reset of the TUxyTMR counter register. See
Figure 28-4 and Figure 28-5 for examples of how the counter timing works with respect to a prescaler.
28.4
UTMR Operation
The basic UTMR module has a counter/timer, a double-buffered period register, and a hardwired compare function.
Together with an External Reset Selector (ERS), Clock Selection Mux, and programmable Start/Stop/Reset logic, the
module can be configured for a variety of hardware limit and signal measurement functions. See Figure 28-1 for the
UTMR module block diagram.
Available options include:
1. Synchronous or asynchronous operation
2. Software control via the ON bit
3. Asynchronous read and reset of the counter/timer using the CAPT and CLR bits
4. Selection of a variety of hardware ERS inputs
5. A variety of both software and hardware triggers for start, stop and reset events
6. A Limit mode that stops the counter/timer on a period register match
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 476
PIC18F27/47/57Q84
UTMR - Universal Timer Module
7.
A One-Shot/Monostable mode option
Together, the various combination of options implements all the functions for both a signal measurement and
hardware limit timer.
28.4.1
Synchronous vs. Asynchronous Operation
A new feature of the UTMR module is the isolation of the counter/timer and its control logic to a separate timer
clock domain. This can simplify and accelerate the operation of the timer when running on an external clock source.
Unfortunately, it also makes the control bits in the timer control registers asynchronous to the timer clock domain. It
is, therefore, necessary to synchronize the timer control register bits to the timer clock domain by setting the CSYNC
bit in the TUxyHLT register. This will cause the synchronization of both the ERS inputs and control register bits to the
selected counter/timer clock, and allow the module to operate completely asynchronous from the system clock.
The synchronization logic produces a delay between the assertion of a signal and its effect in operation. Any signal
that goes from the processor domain to the timer domain (like assertion/de-assertion of ON or ERS controls) requires
three counter/timer clocks to synchronize. Any signal that goes from the timer domain to the processor domain (like
assertion/de-assertion of ON bit, RUN bit, ERS controls, output and interrupt signals) requires three system clocks to
synchronize. This delay is generally acceptable in synchronous applications because the start, reset and stop events
are delayed equally, and there is no net change to the counter sequence.
Figure 28-2 shows clock synchronization with the ON bit (Start) and ERS Reset (Stop), whereas Figure 28-3 shows
clock synchronization with setting/clearing of the ON bit (Start/Stop). If an external clock source is selected, then the
UTMR will also continue to run during Sleep and can generate interrupts on Start, Stop or Reset, which will wake-up
the processor.
Figure 28-2. Clock Synchronization with ON bit and Stop Condition
Instruction
read
BSF
ON
BTFSS
ON
BTFSC
ON
BTFSC
RUN
BTFSC
ON
‘1’
‘1’
‘1’
‘0’
ON
RUN
(processor
domain)
sync into
timer domain
run/stop
(timer
domain)
sync into
processor domain
(TIMER RUNNING)
(TIMER STOPPED)
STOP
set CIF
Note:
1. Not to scale; clocks are not shown.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 477
PIC18F27/47/57Q84
UTMR - Universal Timer Module
Figure 28-3. Clock Synchronization with ON bit and Off Condition
Instruction
read
BSF
ON
BTFSS
ON
BTFSC
ON
BTFSC
RUN
BTFSC
ON
‘1’
‘1’
‘1’
‘0’
ON
RUN
(processor
domain)
sync into
timer domain
run/stop
(timer
domain)
sync into
processor domain
(TIMER RUNNING)
(TIMER STOPPED)
STOP
set CIF
Note:
1. Not to scale; clocks are not shown.
Clearing the CSYNC bit will disable the synchronization logic. When CSYNC = 0, ERS asynchronously gates the
clock and/or resets the timer, according to Start, Reset and Stop options. It is possible that the timer clock may
transition at the same time that the ON bit is set by the user or an ERS event occurs or a CLR or CAPT command is
passed (a clock collision), which may cause unpredictable results to the counter value. Setting CSYNC = 1 removes
this uncertainty.
Important: Using an external clock synchronizer, like the CLC or the comparator sync logic, can allow
synchronous applications with CSYNC = 0, but clock rate limitations may apply at the device level.
ON bit must be set for all counting operations. With START = ‘b00 (no ERS Start), setting ON will start the timer as
though a Start condition occurred. With START > ‘b00 (ERS edge/level-triggers Start), setting ON prepares the timer
for an ERS Start condition and enables the ERS detection logic.
ON will return to ‘0’ when a hardware Stop condition occurs or when written by software, except as noted in
One-Shot Mode. Figure 28-4 and Figure 28-5 below show timing examples for One-Shot mode with CSYNC = 1 and
CSYNC = 0, respectively.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 478
PIC18F27/47/57Q84
UTMR - Universal Timer Module
Figure 28-4. Synchronization and Prescaler Timing (CSYNC = 1)
ON
RUN
(1)
(2)
TUCLK
Fosc/4
TUxyTMR
0 (3)
TUxyCR
1
2
3
4=PR
0
1
3
1
CAPT
ERS
PR Match
TMR = PR
Timer Out
(Pulse)
Timer Out
(Level)
ZIF
(4)
PRIF
(4)
CIF
Timer Setup:
START = None (ON = 1)
CSYNC = Sync
PR = 4 (Period of 5)
(4)
RESET = At PR Match
OSEN = Enabled
PS = 2 (Prescaler of 3)
(4)
STOP = Rising ERS Edge
Note:
1. The ON bit is set in the software and cleared by hardware upon Stop (one-shot mode).
2. The RUN trace illustrates the actual RUN SFR bit and not the internal Timer Clock domain run/
stop signal.
3. Ensure that TUxyTMR counter is reset to zero by setting CLR command.
4. Cleared by software.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 479
PIC18F27/47/57Q84
UTMR - Universal Timer Module
Figure 28-5. Synchronization and Prescaler Timing (CSYNC = 0)
ON
RUN
(1)
(2)
TUCLK
Fosc/4
TUxyTMR
0 (3)
1
2
TUxyCR
3
4=PR
0
1
2
1
CAPT
ERS
PR Match
TMR = PR
Timer Out
(Pulse)
Timer Out
(Level)
ZIF
(4)
PRIF
(4)
CIF
Timer Setup:
START = None (ON = 1)
CSYNC = Async
PR = 4 (Period of 5)
(4)
RESET = At PR Match
OSEN = Enabled
PS = 2 (Prescaler of 3)
(4)
STOP = Rising ERS Edge
Note:
1. The ON bit is set in the software and cleared by hardware upon Stop (one-shot mode).
2. The RUN trace illustrates the actual RUN SFR bit and not the internal Timer Clock domain run/
stop signal.
3. Ensure that TUxyTMR counter is reset to zero by setting CLR command.
4. Cleared by software.
28.4.2
Timer Counter and Capture Registers
The UTMR module has two registers to access the timer/counter value – TUxyTMR counter register and TUxyCR
capture register. The size of these registers is the same as the size of the timer. Both registers share the same
memory location and are addressed based on the RDSEL bit in the TUxyCON0 register. Setting the RDSEL bit
addresses the TUxyTMR counter register, whereas clearing the RDSEL bit addresses the TUxyCR capture register.
To read the raw counter value using the TUxyTMR counter register, the RDSEL bit must be set. When the timer is
running in either Synchronous or Asynchronous mode, directly reading the TUxyTMR counter register can produce
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 480
PIC18F27/47/57Q84
UTMR - Universal Timer Module
erroneous values. This can occur when the counter/timer is operating from an asynchronous clock source or when
the read happens coincidentally with the rollover of the bottom 8 bits of the TUxyTMR counter register.
Clearing the RDSEL bit directs all counter/timer reads through the TUxyCR capture register. The TUxyCR capture
register is functionally a read-only register and is loaded directly from the counter/timer in response to either of the
following three conditions:
1.
2.
3.
Setting the CAPT command bit.
When a stop event is generated.
In the event of an ERS rising edge (or falling edge based on EPOL bit selection) if the Stop condition is set to
none. See Stop Event for more details on Stop condition.
It is generally recommended that any read of the timer, when it is running, needs to utilize the CAPT command bit
with the RDSEL bit clear. Asserting the CAPT bit will cause synchronous transfer of the timer value to the TUxyCR
capture register. The CAPT bit remains set until the capture is complete. The TUxyCR capture register can then be
read by the processor without any data corruption. See Figure 28-6 for an example of the CAPT bit operation.
Figure 28-6. CAPT Bit Operation
TUxyTMR
0
1
PR
TUxyCR
RUN
0
PR
42
0
141
(2)
PR Match
TMR = PR
Timer Out
(Pulse)
(3)
(3)
CAPT
ZIF
(4)
(4)
PRIF
(4)
(4)
CIF
(4)
(4)
Timer Setup:
START = None (ON = 1)
CSYNC = Sync
RESET = At PR Match
STOP = None
Note:
1. Cross-domain clock synchronization applies as required but is not highlighted.
2. The RUN trace illustrates the internal Timer Clock domain run/stop signal. Clock sync delays
apply before the value appears in the RUN SFR bit.
3. The uncertainty of the output is due to the prescaler setting.
4. Cleared by software.
In the event of an ERS rising capture, the TUxyCR capture register must be read before the event of a second ERS
rising or the data captured will be overwritten by the second rising event.
The TUxyTMR counter register can be written when the RDSEL bit is set, provided that the ON bit is clear.
Attempting to write to the TUxyTMR counter register with the ON bit set can result in corrupted data. If the intention is
to clear the counter, the CLR command bit needs to be used instead of writing zeros. Asserting the CLR bit clears the
TUxyTMR counter register, even if the ON bit is set. The CLR bit remains set until the counter is reset.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 481
PIC18F27/47/57Q84
UTMR - Universal Timer Module
The CAPT and CLR command bits are subject to synchronization delays which is dependent on the settings of
CSYNC and ON bits as shown in Table 28-2 below.
Table 28-2. Behavior of CAPT and CLR Commands with Respect to ON and CSYNC Bits
ON Bit
CSYNC Bit
Behavior of CAPT and CLR Commands
1 (Timer Running)
1
Synchronization delay of three timer clock cycles applies before the desired
action is performed.
1 (Timer Running)
0
No synchronization delay applies. Desired action is performed immediately.
0 (Timer Stopped)
1
Synchronization delay of three timer clock cycles applies. The desired
action is delayed until timer clock resumes.
0 (Timer Stopped)
0
No synchronization delay applies. Desired action is performed immediately.
Important:
1. Reading and writing the TUxyTMR counter register when the timer is running (ON = 1) is not
recommended. TUxyTMR counter register needs to be read or written to only when the timer is
stopped (ON = 0) to prevent data corruption.
2.
3.
4.
5.
28.4.3
The TUxyTMR register, like many othe registers in the module, remains unchanged after a nonPOR/BOR system Reset. It is recommended to always clear this register at the start of program
execution to avoid counting from an unknown value.
Setting the CLR bit does not reset the TUxyCR capture register.
The TUxyTMR register needs to not be written as a means to change the effective period. If the
intention is to change the timer period, the TUxyPR period register needs to be changed instead.
See Timer Period Register for more details on how to change the timer period while the timer is
running.
When software sets a CLR or CAPT command bit, the bit value of ‘1’ is indicated in the SFR
immediately, to indicate that the over-and-back clock synchronization is not complete. However, a
sufficiently high timer clock frequency might complete the cross-domain synchronization within one
instruction cycle and the bit value would always appear to be ‘0’.
6.
Setting CLR or CAPT command bits to ‘0’ has no effect.
7.
The timer starts counting by incrementing the TUxyTMR value to the next valid counter value. For
instance, if the counter is in Reset state (TUxyTMR = 0) then the timer starts counting from 1. If
the TUxyTMR = PR and RESET = at PR Match, then the timer will start counting by resetting the
counter to zero first.
Timer Period Register
The TUxyPR period register establishes the period of the periodic timer operation or the duration of hardware limit
timing. The register size is the same as the timer size and is initialized to the maximum value.
The TUxyPR period register is double-buffered to simplify software timing and provide atomic updates. Writing to the
higher bytes of TUxyPR always stores data into buffer registers, but does not change the effective PR value. If the
timer is not counting (ON = 0), writing to the Least Significant Byte will change the effective PR value immediately
to the full buffered value. If the timer is counting (ON = 1), writing to the LSB of TUxyPR is also buffered and is
considered armed for an update. When a second qualifying event occurs, which is a Reset event, the effective PR
value is changed to the full buffered value.
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UTMR - Universal Timer Module
Important:
1. Writing to MSBs after arming the load can lead to corrupted operation.
2. Reading the TUxyPR period register returns the most-recently written value, not necessarily the
current effective PR value.
28.4.4
External Reset Source (ERS)
An External Reset Source (ERS) is an external input to the timer module that can be used to trigger Start, Reset
and Stop conditions for the timer. It can be selected by configuring the TUxyERS selection register and goes
through edge/level detection and synchronization as shown in Figure 28-7. The polarity of the ERS signal is selected
using the EPOL bit in the TUxyHLT register. Setting the EPOL bit will invert the state of the selected ERS source.
Also included is a ‘Continuous mode’ selection for Start/Stop conditions to provide an ERS-independent software
controlled start/stop option. See Start, Stop and Reset Events for start, stop and Reset events.
Important:
1. Actions involving ERS require the ON bit to be set and a running clock.
2. The EPOL bit needs to not be changed when ON = 1. Changing EPOL will spontaneously cause an
edge event and can cause timer output to flip.
Figure 28-7. ERS Edge/Level Detection, Synchronization and Polarity Control
START STOP
RESET EPOL
ERS
Signal
Clock
Sync
Rising
Edge
Detect
D
Rising
Q
Either
Clock
Sync
Falling
Edge
Detect
Falling
Level-0
Clock
Sync
Timer Clock
Selections
TUxyCLK
28.4.5
CPOL
ERS
Reset
timer clock
Level-1
To Prescaler
Start, Stop and Reset Events
To enable the counter/timer, the ON bit of the TUxyCON0 register must be set. When ON = 0, the module is disabled,
and the module output is cleared.
When the module is disabled, the following things apply:
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UTMR - Universal Timer Module
1.
2.
3.
4.
5.
6.
RUN SFR bit is cleared.
OPOL bit in the TUxyCON0 register will continue to control the output polarity.
ERS input logic is reset and disabled.
Interrupts will not trigger.
Clock requests are not asserted.
All SFRs can be written.
Important:
1. The value of the TUxyTMR counter and TUxyCR capture registers are not affected when the ON bit
is clear, unless they are changed explicitly by the user.
2. Clock synchronization may apply, in which case, actions performed may or may not have immediate
effect.
3. The ON bit, like many other bits in the module, remains unchanged after a non-POR/BOR system
reset. It is recommended to clear the ON bit at the start of program execution to avoid starting the
system with a running timer.
28.4.5.1 Start Event
The start event for the counter/timer start is selected using the START bits in the TUxyHLT register. The available
options include:
1.
2.
3.
4.
No hardware Start: The counter/timer starts when the ON bit is set. This is the software-based start option.
Any Stop events are ignored, but will still cause a capture.
Either edge of the ERS signal (edge-triggered): The counter/timer starts at the event of either the rising or
falling edge of the ERS signal.
Rising edge of the ERS signal (edge-triggered): The counter/timer starts at the event of a rising edge of the
ERS signal. When the EPOL bit is set, the polarity is inverted and the counter/timer starts at the event of a
falling edge of ERS signal. See Figure 28-10 for an example of rising ERS edge Start and either ERS edge
Stop condition.
ERS = 1 (level-triggered): The counter/timer starts at the presence of a logic one of the ERS signal. When the
EPOL bit is set, the polarity is inverted and the counter/timer starts at the presence of a logic zero of the ERS
signal. Any Stop events that occur when ERS = 1 (or 0, based on EPOL) are ignored, but will still cause a
capture. See Figure 28-11 for an example of level-triggered Start.
Important:
1. In the event of a level-triggered Start/Reset, the active level must be asserted for at least one timer
clock period to ensure proper sampling. If the duration of the asserted level is less than one timer
clock, there is a possibility of the level trigger being missed and not sampled by the timer module.
28.4.5.2 Reset Event
The Reset event for the counter/timer Reset is selected using the RESET bits in the TUxyHLT register. The Reset
function dominates the operation of the counter.
The available options include:
1.
2.
No hardware Reset: No hardware Reset of the counter/timer. The counter will continue to the full value and roll
over to zero.
ERS = 0 (level-triggered): The counter/timer resets at the presence of a logic zero of the ERS signal and/or
when the TUxyTMR counter register is equal to the TUxyPR period register. When the EPOL bit is set, the
polarity is inverted and the counter/timer resets at the presence of a logic one of the ERS signal. This prevents
any start event from advancing the counter and RUN bit is held at zero. See Figure 28-9 for an example of a
level-triggered ERS Reset.(2)
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UTMR - Universal Timer Module
3.
4.
At a start event: The counter/timer resets at the first clock of the counter/timer start and/or when the TUxyTMR
counter register is equal to the TUxyPR period register. The number of cycles needed to reach PR match is
extended by one. If the Start condition is ERS = 1 (or ERS = 0, based on EPOL selection), the Reset will only
apply to the leading ERS edge. See Figure 28-11 for an example of Reset at a Start event.(2)
At period match: The counter/timer resets when TUxyTMR counter register is equal to the TUxyPR period
register.
Important:
1. If the counter is already zero, a Reset event will not trigger ZIF interrupt.
2. When prescaler > 0, then any ERS or Start-based Reset event that occurs during a PR match
period will reset the timer counter and prescaler counter immediately, and the pulse output will not
occur. If the Reset event collides with the pulse output (regardless of prescaler setting), then the
pulse output will occur naturally and the counter will reset at the next prescaler counter naturally.
3. In the event of a level-triggered Start/Reset, the active level must be asserted for at least one timer
clock period to ensure proper sampling. If the duration of the asserted level is less than one timer
clock, there is a possibility of the level trigger being missed and not sampled by the timer module.
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UTMR - Universal Timer Module
Figure 28-8. Coincidental Start and Stop
TUxyTMR
0
PR
242
TUxyCR
0
PR
237
242
0
237
ERS
START
STOP
(2,3)
(3)
(3)
RESET
RUN
(4)
Timer Out
(Pulse)
Timer Out
(Level)
(5)
(5)
(6)
ZIF
(7)
(7)
(7)
PRIF
(7)
(7)
CIF
(7)
(7)
Timer Setup:
START = Rising ERS Edge
CSYNC = Sync
RESET = At Start+PR Match
STOP = Rising ERS Edge
Note:
1. Cross-domain clock synchronization applies as required but is not highlighted.
2. A coincident Start/Stop condition that starts the counter does not cause either a capture
or CIF to be set.
3. A synchronous edge-triggered Start/Stop condition is one timer clock cycle wide internally.
4. The RUN trace illustrates the internal Timer Clock domain run/stop signal. Clock sync delays
apply before the value appears in the RUN SFR bit.
5. The uncertainty of the output is due to the prescaler setting.
6. Timer Out (Level) rises along with ERS when START = Rising/Either ERS Edge.
7. Cleared by software.
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UTMR - Universal Timer Module
Figure 28-9. ERS = 0 Level Reset
TUxyTMR
0
1
33
TUxyCR
0
1
PR
0
142
33
0
142
PW < PR
PW > PR
ERS
ON (2)
RUN (3)
RESET
Timer Out
(Pulse)
(4)
Timer Out
(Level)
ZIF
(5)
(5)
PRIF
CIF
Timer Setup:
START = None (ON = 1)
CSYNC = Sync
(5)
(5)
(5)
(5)
RESET = ERS Level-0+PR Match
OSEN = Enabled
STOP = Either ERS Edge
Note:
1. Cross-domain clock synchronization applies as required but is not highlighted.
2. The ON bit is set in the software and cleared by hardware upon Stop (one-shot mode).
3. The RUN trace illustrates the internal Timer Clock domain run/stop signal. Clock sync delays
apply before the value appears in the RUN SFR bit.
4. The uncertainty of the output is due to the prescaler setting.
5. Cleared by software.
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UTMR - Universal Timer Module
Figure 28-10. Rising Edge Start and Either Edge Stop
TUxyTMR
21
22
242
243
PR PR+1
TOP
0
(2)
TUxyCR
242
1850
ERS
RUN
(3)
PR Match
TMR = PR
Timer Out
(Pulse)
Timer Out
(Level)
(4)
(5)
(6)
(5)
CAPT
ZIF
(7)
PRIF
(7)
CIF
Timer Setup:
START = Rising ERS Edge
CSYNC = Sync
(7)
(7)
RESET = None
STOP = Either ERS Edge
Note:
1. Cross-domain clock synchronization applies as required but is not highlighted.
2. TOP represents the maximum counter value.
3. The RUN trace illustrates the internal Timer Clock domain run/stop signal. Clock sync delays
apply before the value appears in the RUN SFR bit.
4. The uncertainty of the output is due to the prescaler setting.
5. Timer Out (Level) rises along with ERS when START = Rising/Either ERS Edge.
6. Timer Out (Level) falls synchronous to the timer clock.
7. Cleared by software.
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Figure 28-11. Reset at Level Start and Stop at PR Match
TUxyTMR
0
1
42
0
PR
TUxyCR
0
0
0
PR
PR
Short Interval
0
PR
Long Interval
ERS
RUN
(2)
PR Match
TMR = PR
Timer Out
(Pulse)
(3)
(3)
Timer Out
(Level)
ZIF
(4)
(4)
(4)
PRIF
(4)
CIF
(4)
Timer Setup:
START = ERS Level-1
CSYNC = Sync
RESET = At Start+PR Match
(4)
STOP = At PR Match
Note:
1. Cross-domain clock synchronization applies as required but is not highlighted.
2. The RUN trace illustrates the internal Timer Clock domain run/stop signal. Clock sync delays
apply before the value appears in the RUN SFR bit.
3. The uncertainty of the output is due to the prescaler setting.
4. Cleared by software.
28.4.5.3 Stop Event
The stop event for the counter/timer stop is selected using the STOP bits in the TUxyHLT register. The available
options include:
1.
2.
3.
4.
No hardware Stop: The counter/timer runs continuously until the ON bit is cleared. Neither the ERS signal
nor a PR register match will stop the counter/timer. This is the software-controlled stop option. The current
counter value is captured in the TUxyCR capture register at every rising edge of ERS signal, in which case the
TUxyCR capture register must be read before the event of a second ERS rising or the captured data will be
overwritten by the second rising event. When the EPOL bit is set, the polarity is inverted and the counter value
is captured at every falling edge of ERS signal instead.
Either edge of the ERS signal (edge-triggered): The counter/timer stops at the event of either the rising or
falling edge of the ERS signal and the counter value is captured in the TUxyCR capture register. See Figure
28-10 for an example of rising ERS edge Start and either ERS edge Stop condition.
Rising edge of the ERS signal (edge-triggered): The counter/timer stops at the event of a rising edge of the
ERS signal and the counter value is captured in the TUxyCR capture register. When the EPOL bit is set, the
polarity is inverted and the counter/timer stops at the falling edge of the ERS signal.
At period match: The counter/timer stops when the TUxyTMR counter register is equal to the TUxyPR period
register and the counter value is captured in the TUxyCR capture register. See Figure 28-11 for an example of
Stop at PR match.
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UTMR - Universal Timer Module
Important:
1. In the event of coincidental start and stop events, and RUN = 0; the start event takes precedence,
timer capture and CIF interrupt are blocked, and OSEN is ignored. See Figure 28-8 for a
coincidental start and stop event at ERS rising edge. If RUN = 1, then the stop event is ignored, but
will still cause a capture.
2. If Reset and Stop are coincident, the captured value is the value prior to the Reset and the counter
will stop at zero.
3. After stopping, the start edge detector needs up to 3 timer clock periods to resume, and any
overlapping stop events may be ignored in that interval.
4. If the counter is not running (no start has occurred), a stop event will have no side effects, like
capturing data.
28.4.6
Hardware Limit Mode
The Limit mode of operation is controlled by the LIMIT bit in the TUxyCON1 register. Setting the LIMIT bit will cause
the counter/timer value to not advance when the TUxyTMR counter register value equals the value in the TUxyPR
period register (even though the timer is still “running”). If the LIMIT bit is cleared, the counter/timer will continue to
count through the PR match and roll over at the maximum value of the TUxyTMR counter register. The LIMIT bit is
not synchronized to the counter/timer clock and does not need to be changed when the ON bit is set.
Important:
1. This bit is relevant when RESET = ‘b00 (No hardware Reset) and counter equals PR.
2.
28.4.7
The effect of Limit mode is to prevent the counter from exceeding PR value. Reset and CLR events
are not prevented from clearing the counter.
One-Shot Mode
The One-Shot mode is enabled by setting the OSEN bit in the TUxyCON1 register. When the OSEN bit is set,
the counter/timer will increment until a Stop condition is detected. At that time, the ON bit will be cleared and the
counter/timer will stop. See Figure 28-12 for an example of One-Shot mode.
Important: In One-Shot mode, a Stop condition clears the ON bit, even if it coincides with another Start
event. If a Stop event occurs prior to Start, that Stop condition does not clear ON bit.
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UTMR - Universal Timer Module
Figure 28-12. One-Shot Mode
0(2)
TUxyTMR
1
2
PR
TUxyCR
ON
RUN
0
1
2
PR
PR
0
1
2
PR
(3)
(4)
PR Match
TMR = PR
Timer Out
(Pulse)
(5)
(5)
ZIF
(6)
(6)
PRIF
(6)
(6)
CIF
(6)
(6)
Timer Setup:
START = None (ON = 1)
CSYNC = Sync
RESET = At PR Match
OSEN = Enabled
STOP = At PR Match
Note:
1. Cross-domain clock synchronization applies as required but is not highlighted.
2. Ensure that TUxyTMR counter is reset to zero by setting CLR command.
3. The ON bit is set in the software and cleared by hardware upon Stop (one-shot mode).
4. The RUN trace illustrates the internal Timer Clock domain run/stop signal. Clock sync delays
apply before the value appears in the RUN SFR bit.
5. The uncertainty of the output is due to the prescaler setting.
6. Cleared by software.
28.4.8
Run Status Flag
In all modes of operation, the RUN status bit in the TUxyCON1 register is set whenever the counter/timer is active
(after a Start event, but before a Stop condition). The RUN bit will remain set through a Reset condition(1). Note that
the RUN status bit is synchronous to the counter/timer clock and updates may be delayed. Refer to Synchronous vs.
Asynchronous Operation for details about clock synchronization.
Important:
1. The RUN bit is held at zero if a Start has occurred (the counter is “running”), but ERS is holding the
counter at the value zero when RESET = ‘b01 (level-triggered).
2.
28.5
The RUN status bit lags the internal run/stop state by two to three instruction cycles. If Start and
Stop occur rapidly in succession, the RUN bit may not be set at all.
UTMR Output Modes
The UTMR module can generate either a pulsed or level output. When the OM bit in the TUxyCON0 register is set,
the output will follow the Run/Stop state of the counter timer (level output), set to indicate that the timer is running,
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UTMR - Universal Timer Module
and cleared to indicate the timer has stopped. The output remains set through all Reset conditions, except when ERS
is holding the timer/counter in a Reset state (RESET = `b11, level ERS Reset).
When the OM bit is cleared, the timer output is pulsed high at every period match (pulse output). The duration of the
pulse is one single primary clock period at the end of the counter match period, regardless of the prescaler. This is
demonstrated in Figure 28-4 and Figure 28-5 where the pulse output occurs only during the last timer clock period
during the PR match.
The polarity of the output (pulsed or level) is controlled by the OPOL bit in the TUxyCON0 register. When OPOL is
set, the output will either pulse low or be held low when timer output is active. When OPOL is cleared, the output will
be either pulse high or be held high when timer output is active. The OPOL bit will control the output polarity of the
module even when the module is disabled (ON = 0).
Important:
1. When START = 'b01 or 'b10 (edge-triggered), the level output is asserted as soon as the qualified
ERS edge is registered without any synchronization delays (even when CSYNC = 1).
2. When LIMIT = 1, the pulse output will assert as indicated and will remain asserted until the counter
changes from PR.
3. The OPOL bit does not affect the polarity of the RUN SFR bit.
28.6
Interrupt and DMA Triggers
The Universal Timer module provides three interrupt sources – Period Register match, Zero and Capture.
1.
2.
3.
A PR match interrupt occurs and the PRIF interrupt flag in the TUxyCON1 register is set when the TUxyTMR
counter register increments and becomes equal to the TUxyPR period register. The PRIF interrupt will not
occur if the user writes the PR value to the TUxyTMR counter register directly.
A zero interrupt occurs and the ZIF interrupt flag in the TUxyCON1 register is set when the TUxyTMR counter
register becomes equal to zero. This occurs when:
– A Reset condition resets the counter to zero, or
– Software sets the CLR command bit, or
– Counter naturally overflows to zero, or
– User writes zero to the TUxyTMR counter register directly.
A capture interrupt occurs and the CIF interrupt flag in the TUxyCON1 register is set whenever a capture event
occurs, and the TUxyCR capture register is updated with the counter value. See Timer Counter and Capture
Registers for a list of capture event conditions. The CIF interrupt trigger requires a running timer.
Each interrupt has a corresponding enable bit in the TUxyCON0 register (PRIE, ZIE, and CIE). Setting any of the
three interrupt enable bits will allow the module to generate a corresponding interrupt. The interrupt flags (PRIF, ZIF
and CIF) will set even if the corresponding interrupt is disabled.
All the three interrupt flags are combined together to form one single, top system level TUxyIF interrupt flag in the
PIRx register as shown in Figure 28-13. The TUxyIF interrupt flag is a read-only bit in the PIRx register, which is
automatically cleared when all the three interrupt flags (PRIF, ZIF and CIF) are cleared.
The Universal Timer module also provides the three interrupt sources to trigger DMA transfers (PRIF, ZIF and CIF
conditions). The TUxyPR period register is also double-buffered to facilitate DMA loading of the register in response
to a CIF interrupt trigger.
Important:
1. The interrupts need not be enabled with their associated enable bits to be used as triggers for DMA
transfer.
2. The interrupts must be enabled for the TUxyIF flag to be set in the PIRx register as shown in Figure
28-13.
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UTMR - Universal Timer Module
Figure 28-13. Interrupt and DMA Trigger
PR Match
Interrupt
Logic
PRIE
PRIF
PRIFDMA
Capture
Interrupt
Logic
CIE
TUxyIF
in PIRx
CIF
CIFDMA
Zero
Interrupt
Logic
ZIE
ZIF
ZIFDMA
28.7
Operation During Sleep
When the processor is asleep, the counter will hold the selected clock source active and continue to operate as
configured. Because the counter/timer module can generate interrupts, the module is also capable of waking up the
processor.
28.8
Chaining Counter Timers
A feature of the Universal Timer module is the ability to chain two counter/timers into a single module. Setting the
CHxyz bit in the TUCHAIN register will combine two instances of Universal Timers into a single bigger Timer module.
When two Universal Timer modules are chained, one of them becomes the primary module (Host), whereas the
other becomes the secondary module (Client). The Host module forms the least significant segment of the combined
counter/timer whereas the Client module forms the most significant segment. Figure 28-14 shows the Host/Client
configuration of the Chained Operational Model.
When operating in this configuration, control of the combined counter/timer is via the TUxyCON0, TUxyCON1,
TUxyPS, TUxyCLK, TUxyERS, and TUxyHLT registers of the Host module. The same registers of the Client module
become defunct. The timer output, interrupts and DMA triggers for the combined timer/counter are generated by the
Host module.
The TUxyTMR counter, TUxyCR capture, and TUxyPR period registers of both the Host and Client modules are
combined respectively, to provide higher-width register control for the combined counter/timer.
The timer chaining in this device is as follows:
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UTMR - Universal Timer Module
Table 28-3. Timer Chaining
TUxy Instance
Host/Client
TU16A (16-bit)
Host (Least Significant
Segment)
TU16B (16-bit)
Client (Most Significant
Segment)
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TUCHAIN Control Bit
Chained Timer Size
CH16AB
32-bit
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Figure 28-14. Chained Operational Model
Least Significant Segment
TUxyCLK
Timer Clock
Clock Enable
TUxyERS
Gate Logic
TUxyCONz
TUxyHLT
TUxyPS
Control and Match
Carry Enable
Counter
Capture
Period
Registers
Timer Output
Interrupt and
DMA Triggers
Timer Chain Out
Host
TUCHAIN
Client
Timer Chain In
Most Significant Segment
TUxyCLK
Timer Clock
N/C
TUxyERS
N/C
Gate Logic
TUxyCONz
TUxyHLT
TUxyPS
N/C
Logic
Disconnected
Clock Enable
Control and Match
Counter
Capture
Period
Registers
N/C
Note:
1. This is a conceptual diagram only.
2. Control registers, state machine, prescaler and input ERS and clock for
client is not used. Rather they are derived from the host segment.
28.9
Register Definitions: Universal Timer
Long bit name prefixes for the UTMR peripherals are shown in the following table. Refer to the “Long Bit Names”
section in the “Register and Bit Naming Conventions” chapter for more information.
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UTMR - Universal Timer Module
Table 28-4. Universal Timer Long bit name prefixes
Peripheral
Bit Name Prefix
TU16A
TU16A
TU16B
TU16B
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28.9.1
TUxyCON0
Name:
TUxyCON0
Timer Control Register 0
Bit
Access
Reset
7
ON
R/W/HC
0
6
CPOL
R/W
0
5
OM
R/W
0
4
OPOL
R/W
0
3
RDSEL
R/W
0
2
PRIE
R/W
0
1
ZIE
R/W
0
0
CIE
R/W
0
Bit 7 – ON Timer Enable(1,2)
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
The module is enabled
0
The module is disabled and in the lowest-power mode
Bit 6 – CPOL Timer Clock Polarity Select(3,4)
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
The counter advances with the clock rising edge
0
The counter advances with the clock falling edge
Bit 5 – OM Timer Output Mode Select
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
Output is in Level mode
0
Output is in Pulse mode
Bit 4 – OPOL Timer Output Polarity Select(5)
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
Output is high when the timer is Idle
0
Output is low when the timer is Idle
Bit 3 – RDSEL Timer Readout Mode Select(6,7,8)
The RDSEL bit selects the addressing of TUxyTMR and TUxyCR registers. See Timer Counter and Capture
Registers for details.
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
TUxyTMR reads/write the value of the raw counter
0
TUxyCR reads the value of the capture register
Bit 2 – PRIE Period Match Interrupt Enable(9,10)
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
PRIF interrupt will occur when the counter increments from PR-1 to PR
0
PRIF interrupt is disabled
Bit 1 – ZIE Zero Interrupt Enable(9)
Reset States: POR/BOR = 0
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Value
1
0
All Other Resets = u
Description
ZIF interrupt will occur when the counter becomes zero from a nonzero value
ZIF interrupt is disabled
Bit 0 – CIE Capture Interrupt Enable(9,11)
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
CIF interrupt will occur when a capture event occurs
0
CIF interrupt is disabled
Notes:
1. The selected clock will be enabled when this bit is set and a Start condition has occurred.
2. When this bit is set and CSYNC = 1, it takes three timer clocks to synchronize. When this bit is cleared and
CSYNC = 1, the selected clock source (especially external clock sources) must supply at least three additional
clocks to resolve internal states. During this time, if the timer is already running, any stop/Reset related ERS
events that get processed will continue to affect the Run state of the timer. If CSYNC = 0, the ON bit clears
immediately and the timer stops immediately.
3. This bit is not clock synchronized, and needs to only be changed while ON = 0.
4.
5.
The purpose of this control is to select the active edge when using externally-clocked counter mode.
This bit controls the output even when ON = 0.
6.
7.
8.
This bit is shadowed when the module is frozen during debugging and restored when the module resumes
operation.
Capture or stop events load the TUxyCR capture register, regardless of this bit’s setting.
The effect of writing to TUxyCR with RDSEL = 0 is not defined.
9.
10.
11.
12.
The interrupt flags will be set even if the corresponding interrupt is disabled.
The PRIF interrupt will not occur if the user writes the PR value to the TUxyTMR counter register directly.
The CIF interrupt trigger requires a running timer.
This register is not available when the module is chained and operated as a client.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 498
PIC18F27/47/57Q84
UTMR - Universal Timer Module
28.9.2
TUxyCON1
Name:
TUxyCON1
Timer Control Register 1
Bit
Access
Reset
7
RUN
R
0
6
OSEN
R/W
0
5
CLR
R/S/HC
0
4
LIMIT
R/W
0
3
CAPT
R/S/HC
0
2
PRIF
R/W/HS
0
1
ZIF
R/W/HS
0
0
CIF
R/W/HS
0
Bit 7 – RUN Timer Run/Stop Status (read-only)(1,2)
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
Timer is running (counting) and not being held in Reset by ERS (per EPOL bit selection)
0
Timer is not counting or is held in Reset by ERS
Bit 6 – OSEN One Shot Mode Enable(3,4)
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
The counter operates in One Shot mode; ON will be cleared by a Stop condition
0
The counter can be repeatedly Started by the ERS signal
Bit 5 – CLR Timer Counter “Clear” Command(5,6)
Writing this bit with ‘0’ has no effect.
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
Once set, the timer counter and the internal prescaler counter are cleared, then this bit is cleared (the
captured value of TUxyCR is unchanged)
0
Clearing action is complete (or not started)
Bit 4 – LIMIT Limit Mode Enable(4)
This bit is relevant when RESET = ‘b00 (continuous mode) and counter equals PR.
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
Counter value remains equal to PR (unchanged); no additional interrupts occur
0
Counter value goes tor PR+1 when clocked
Bit 3 – CAPT Timer “Capture” Command(5,6,7,8,9)
Writing this bit with ‘0’ has no effect.
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
Once set, the counter value is captured in TUxyCR and this bit is cleared
0
TUxyCR update is complete (or not started)
Bit 2 – PRIF Period Match Interrupt Flag(10,11,12)
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
The counter has incremented from PR-1 to PR
0
The counter has not incremented from PR-1 to PR since this bit was last cleared
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 499
PIC18F27/47/57Q84
UTMR - Universal Timer Module
Bit 1 – ZIF Zero Interrupt Flag(10,11)
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
The counter has reset or rolled over to zero
0
The counter has not reset or rolled over since this bit was last cleared
Bit 0 – CIF Capture Interrupt Flag(10,11,13)
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
A capture event has occurred
0
A capture event has not occurred since this bit was last cleared
Notes:
1. Clock synchronization delays apply.
2. This bit is held at zero if a Start has occurred (the counter is “running”), but ERS is holding the counter at the
value zero when RESET = ‘b01 (level-triggered).
3.
4.
5.
6.
The clearing of the ON bit in One Shot mode is subject to clock synchronization delays. Refer to sections
Synchronous vs. Asynchronous Operation and One-Shot Mode for details.
This bit is not clock synchronized, and needs to only be changed while ON = 0.
9.
This bit is subject to clock synchronization delays; see also Timer Counter and Capture Registers.
If the counter is disabled (ON = 0) or if the module is frozen during debugging, then the timer clock has been
disabled; the effect of setting CLR or CAPT command bits depends on the clock synchronization setting. If
CSYNC = 0, the corresponding action is performed immediately. If CSYNC = 1, the corresponding action is
delayed until the clock resumes (even in frozen state while debugging). See also Timer Counter and Capture
Registers.
A capture event can also be triggered by other means. See Timer Counter and Capture Registers for details.
If CAPT command is near-coincident with a Stop event, the captured value may represent the first event that
occurs.
The captured value is read by setting RDSEL = 0 and reading TUxyCR.
10.
11.
12.
13.
14.
This bit may be set by software in order to invoke an interrupt or DMA operation.
The interrupt flags will be set even if the corresponding interrupt is disabled.
The PRIF interrupt will not occur if the user writes the PR value to the TUxyTMR counter register directly.
The CIF interrupt trigger requires a running timer.
This register is not available when the module is chained and operated as a client.
7.
8.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 500
PIC18F27/47/57Q84
UTMR - Universal Timer Module
28.9.3
TUxyHLT
Name:
TUxyHLT
Hardware Limit Timer Control Register
Bit
Access
Reset
7
EPOL
R/W
0
6
CSYNC
R/W
1
5
4
3
START[1:0]
R/W
0
2
1
0
RESET[1:0]
R/W
0
R/W
0
STOP[1:0]
R/W
0
R/W
0
R/W
0
Bit 7 – EPOL ERS Polarity Selection
Reset States: POR/BOR = 0
All Other Resets = u
Value
Description
1
The edges and levels for Start, Reset and Stop are inverted
0
The edges and levels for Start, Reset and Stop are the true input levels
Bit 6 – CSYNC ERS Clock Synchronization Select(1,2)
Reset States: POR/BOR = 1
All Other Resets = u
Value
Description
1
ERS and ON are synchronized with TUxyCLK
0
The counter starts, stops and resets asynchronously
Bits 5:4 – START[1:0] Counter Start Condition Select(3,4)
Reset States: POR/BOR = 00
All Other Resets = uu
Value
Description
11
Timer counter starts when ERS = 1
10
Timer counter starts at rising edge of ERS
01
Timer counter starts at either edge of ERS
00
No start due to ERS, timer runs when ON = 1
Bits 3:2 – RESET[1:0] Counter Reset Condition Select(4,5,6,7,8)
Reset States: POR/BOR = 00
All Other Resets = uu
Value
Description
11
Timer counter resets at PR match i.e., when counter equals PR; Next clock brings counter to zero
10
Timer counter resets at the first clock when starting and/or also at PR match
01
Timer counter resets when ERS = 0 and/or also at PR match
00
No hardware Reset
Bits 1:0 – STOP[1:0] Counter Stop Condition Select(4,8,9,10,11)
The Stop feature has effect only when the counter is actively running. Once stopped, additional Stop events will not
invoke capture or interrupt.
Reset States: POR/BOR = 00
All Other Resets = uu
Value
Description
11
Timer stops counting at PR match i.e., when counter equals PR; current counter value is captured in
TUxyCR
10
Timer stops counting at rising edge of ERS; current counter value is captured in TUxyCR
01
Timer stops counting at either edge of ERS; current counter value is captured in TUxyCR
00
ERS or PR match do not stop the timer; software must clear ON to stop the timer; current counter
value is captured in TUxyCR at every rising edge of ERS
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 501
PIC18F27/47/57Q84
UTMR - Universal Timer Module
Notes:
1. This bit is Reset to ‘1’.
2.
3.
If CSYNC = 0, the ERS and ON edges must occur sufficiently further away from the clock edge to be
registered into the timer domain. If the ERS and/or ON edges occur too close to the clock edge, it may result in
a Race condition and the ERS/ON edges may be missed.
The TUxyCLK clock source is enabled when ON = 1 regardless of the Start event.
4.
If EPOL = 1, then timer Start/Reset/Stop conditions happen at the alternate level/edge, respectively.
5.
7.
When the timer is running, any subsequent Start condition is ignored. If RESET = ‘b10 (Reset at first clock
after starting), the timer resets at every Start condition, even when the actual start event is being ignored.
If START = ‘b11 (level triggered at ERS = 1), RESET = ‘b10 (Reset at first clock after starting) applies only
at the Off-On transition of the timer’s Run state.
If RESET = ‘b10 (level-triggered), the RUN bit is held at ‘0’.
8.
9.
A Reset or Stop event reloads the PR register as described in Timer Period Register.
Actions involving ERS require ON = 1 and a running clock.
6.
10. Software can always set ON = 0 to stop the counter.
11. If OSEN = 1, a Stop event will clear ON.
12. This register is not clock synchronized and needs to only be written when ON = 0.
13. This register is not available when the module is chained and operated as a client.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 502
PIC18F27/47/57Q84
UTMR - Universal Timer Module
28.9.4
TUxyPS
Name:
TUxyPS
Prescaler Value Register
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
PS[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – PS[7:0] Clock Prescaler register
Reset States: POR/BOR = 00000000
All Other Resets = uuuuuuuu
Value
Description
0xFF-0x0 Divider ratio is (PS+1):1
1
0x00
The input clock is not divided (1:1 clocking)
Notes:
1. This register needs to only be written when ON = 0.
2.
3.
This register is not available when the module is chained and operated as a client.
The internal prescaler counter (not the TUxyPS register) is reset by any Stop or Reset event, and upon any
write to the TUxyPS and TUxyTMR registers. This allows the next timer interval to be full-length.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 503
PIC18F27/47/57Q84
UTMR - Universal Timer Module
28.9.5
TUxyTMR (16-bit)
Name:
Address:
TU16yTMR
0x38B,0x397
Timer Counter Register for 16-bit version of UTMR module. This register can only be addressed when RDSEL = 1.
Bit
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TMR[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
TMR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – TMR[15:0] Timer value
Reset States: POR/BOR = 0000000000000000
All Other Resets = uuuuuuuuuuuuuuuu
Condition Description
RDSEL = 1 The raw counter register is read or written; needs to only be accessed while clocking is disabled i.e.,
when ON = 0.
RDSEL = 0 Reserved. Do not use.
Notes:
1. Writing to this register will change the raw counter value directly. The user must handle the operation correctly
to avoid data corruption. There is no safeguard for atomic access. Reading or writing a running counter is not
recommended. This register needs to only be accesses while clocking is disabled.
2. The individual bytes in this multibyte register can be accessed with the following register names:
– TUxyTMRH: Accesses the high byte TUxyTMR[15:8]
– TUxyTMRL: Accesses the low byte TUxyTMR[7:0]
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 504
PIC18F27/47/57Q84
UTMR - Universal Timer Module
28.9.6
TUxyCR (16-bit)
Name:
Address:
TU16yCR
0x38B,0x397
Timer Capture Register for 16-bit version of UTMR module. This register can only be addressed when RDSEL = 0.
Bit
15
14
13
12
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
CR[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
CR[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 15:0 – CR[15:0] Timer capture value
Reset States: POR/BOR = 0000000000000000
All Other Resets = uuuuuuuuuuuuuuuu
Condition
Description
RDSEL = 1
Reserved. Do not use.
RDSEL = 0
The value captured by the most-recent Stop or Capture event is returned (read-only)
Notes:
1. Writing to this register is not recommended and may result in unexplained behavior.
2. The captured value is updated at Stop or when software sets CAPT = 1, regardless of the RDSEL value. Refer
to Timer Counter and Capture Registers for details.
3. The individual bytes in this multibyte register can be accessed with the following register names:
– TUxyCRH: Accesses the high byte TUxyCR[15:8]
– TUxyCRL: Accesses the low byte TUxyCR[7:0]
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 505
PIC18F27/47/57Q84
UTMR - Universal Timer Module
28.9.7
TUxyPR (16-bit)
Name:
Address:
TU16yPR
0x38D,0x399
Timer Period Register for 16-bit version of UTMR module.
Bit
15
14
13
12
11
10
9
8
R/W
1
R/W
1
R/W
1
R/W
1
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
PR[15:8]
Access
Reset
Bit
R/W
1
R/W
1
R/W
1
R/W
1
7
6
5
4
PR[7:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
Bits 15:0 – PR[15:0] Period value
The period of the timer.
Reset States: POR/BOR = 1111111111111111
All Other Resets = uuuuuuuuuuuuuuuu
Notes:
1. This register is double-buffered; effective PR value is loaded as defined by Timer Period Register.
2. Data written to higher bytes is buffered; data written to LSB is also buffered and arms the effective PR value to
be loaded at the next Reset or CLR event.
3. Reading this register returns the data most-recently written, not necessarily the current PR setting.
4. The individual bytes in this multibyte register can be accessed with the following register names:
– TUxyPRH: Accesses the high byte TUxyPR[15:8]
– TUxyPRL: Accesses the low byte TUxyPR[7:0]
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 506
PIC18F27/47/57Q84
UTMR - Universal Timer Module
28.9.8
TUxyCLK
Name:
TUxyCLK
Clock Input Selector
Bit
7
6
5
Access
Reset
4
3
R/W
0
R/W
0
2
CLK[4:0]
R/W
0
1
0
R/W
0
R/W
0
Bits 4:0 – CLK[4:0] Clock Input Selector
Table 28-5. TUxyCLK Clock Input Selections
CLK
11111
11110
11101
11100
11011
11010
11001
11000
10111
10110
10101
10100
10011
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
Clock Input
CLC8_OUT
CLC7_OUT
CLC6_OUT
CLC5_OUT
CLC4_OUT
CLC3_OUT
CLC2_OUT
CLC1_OUT
NCO3_OUT
NCO2_OUT
NCO1_OUT
PWM4S1P2_OUT
PWM4S1P1_OUT
PWM3S1P2_OUT
PWM3S1P1_OUT
PWM2S1P2_OUT
PWM2S1P1_OUT
PWM1S1P2_OUT
PWM1S1P1_OUT
CCP3_OUT
CCP2_OUT
CCP1_OUT
CLKREF_OUT
EXTOSC
SOSC
MFINTOSC (32 kHz)
MFINTOSC (500 kHz)
LFINTOSC
HFINTOSC
FOSC
TUIN1PPS
TUIN0PPS
Reset States: POR/BOR = 00000
All Other Resets = uuuuu
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 507
PIC18F27/47/57Q84
UTMR - Universal Timer Module
Note:
1. This register is not available when the module is chained and operated as a client.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 508
PIC18F27/47/57Q84
UTMR - Universal Timer Module
28.9.9
TUxyERS
Name:
TUxyERS
External Input Selector
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
ERS[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 5:0 – ERS[5:0] External Reset Source Selector
Table 28-6. TUxyERS External Reset Sources
ERS
111111
111110
111101-100111
100110
100101
100100
100011
100010
100001
100000
011111
011110
011101
011100
011011
011010
011001
011000
010111
010110
010101
010100
010011
010010
010001
010000
001111
001110
001101
001100
001011
001010
001001
001000
External Reset Source Connection
TU16A
TU16B
(1)
TU16ATMRL_Read or TU16ACRL_Read
TU16BTMRL_Read or TU16BCRL_Read(1)
(1)
TU16APRL_Write
TU16BPRL_Write(1)
Reserved
SPI2_SCK
SPI1_SCK
I2C1_SCL
U5TX_Edge (Positive/Negative)
U5RX_Edge (Positive/Negative)
U4TX_Edge (Positive/Negative)
U4RX_Edge (Positive/Negative)
U3TX_Edge (Positive/Negative)
U3RX_Edge (Positive/Negative)
U2TX_Edge (Positive/Negative)
U2RX_Edge (Positive/Negative)
U1TX_Edge (Positive/Negative)
U1RX_Edge (Positive/Negative)
CLC8_OUT
CLC7_OUT
CLC6_OUT
CLC5_OUT
CLC4_OUT
CLC3_OUT
CLC2_OUT
CLC1_OUT
ZCD_OUT
CMP2_OUT
CMP1_OUT
NCO3_OUT
NCO2_OUT
NCO1_OUT
PWM4S1P2_OUT
PWM4S1P1_OUT
PWM3S1P2_OUT
PWM3S1P1_OUT
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 509
PIC18F27/47/57Q84
UTMR - Universal Timer Module
...........continued
ERS
External Reset Source Connection
TU16A
000111
000110
000101
000100
000011
000010
000001
000000
TU16B
PWM2S1P2_OUT
PWM2S1P1_OUT
PWM1S1P2_OUT
PWM1S1P1_OUT
TU16B_OUT
Reserved
Reserved
TU16A_OUT
TUIN1PPS
TUIN0PPS
Note:
1. TUxyPRL_Write,TUxyTMRL_Read and TUxyCRL_Read are event triggers occurring when the indicated SFR
is accessed.
Reset States: POR/BOR = 000000
All Other Resets = uuuuuu
Note:
1. This register is not available when the module is chained and operated as a client.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 510
PIC18F27/47/57Q84
UTMR - Universal Timer Module
28.9.10 TUCHAIN
Name:
Address:
TUCHAIN
0x3BB
Timer Chain Control
Bit
7
6
5
4
3
2
Access
Reset
1
0
CH16AB
R/W
x
Bit 0 – CH16AB Timers TU16A and TU16B Chain Enable
Reset States: POR/BOR = x
All Other Resets = u
Value
Description
1
Timers TU16A (Host) and TU16B (Client) operate as a single 32-bit timer
0
TU16ATMR, TU16ACR and TU16APR form the least significant bits of the counter, capture and period
values, respectively.
Timers TU16A and TU16B operate as independent 16-bit timers
Note:
1. When chained, TUxyCON0, TUxyCON1, TUxyHLT, TUxyPS, TUxyCLK and TUxyERS of the client timer are
undefined. Refer to Chaining Counter Timers for details.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 511
PIC18F27/47/57Q84
UTMR - Universal Timer Module
28.10
Address
Register Summary - Universal Timer
Name
0x00
...
0x0386
0x0387
0x0388
0x0389
0x038A
TU16ACON0
TU16ACON1
TU16AHLT
TU16APS
0x038B
TU16ATMR
0x038B
TU16ACR
0x038D
TU16APR
0x038F
0x0390
0x0391
...
0x0392
0x0393
0x0394
0x0395
0x0396
TU16ACLK
TU16AERS
TU16BCON0
TU16BCON1
TU16BHLT
TU16BPS
0x0397
TU16BTMR
0x0397
TU16BCR
0x0399
TU16BPR
0x039B
0x039C
0x039D
...
0x03BA
0x03BB
TU16BCLK
TU16BERS
Bit Pos.
7
6
7:0
7:0
7:0
7:0
7:0
15:8
7:0
15:8
7:0
15:8
7:0
7:0
ON
RUN
EPOL
CPOL
OSEN
CSYNC
7:0
7:0
7:0
7:0
7:0
15:8
7:0
15:8
7:0
15:8
7:0
7:0
ON
RUN
EPOL
5
4
3
2
1
0
ZIE
ZIF
CIE
CIF
Reserved
OM
OPOL
CLR
LIMIT
START[1:0]
RDSEL
PRIE
CAPT
PRIF
RESET[1:0]
STOP[1:0]
PS[7:0]
TMR[7:0]
TMR[15:8]
CR[7:0]
CR[15:8]
PR[7:0]
PR[15:8]
CLK[4:0]
ERS[5:0]
Reserved
CPOL
OSEN
CSYNC
OM
OPOL
CLR
LIMIT
START[1:0]
RDSEL
PRIE
CAPT
PRIF
RESET[1:0]
ZIE
ZIF
CIE
CIF
STOP[1:0]
PS[7:0]
TMR[7:0]
TMR[15:8]
CR[7:0]
CR[15:8]
PR[7:0]
PR[15:8]
CLK[4:0]
ERS[5:0]
Reserved
TUCHAIN
7:0
© 2021 Microchip Technology Inc.
CH16AB
Preliminary Datasheet
DS40002213D-page 512
PIC18F27/47/57Q84
CCP - Capture/Compare/PWM Module
29.
CCP - Capture/Compare/PWM Module
The Capture/Compare/PWM module is a peripheral that allows the user to time and control different events, and to
generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of
an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has
expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle.
Each individual CCP module can select the timer source that controls the module. The default timer selection is
Timer1 when using Capture/Compare mode and Timer2 when using PWM mode in the CCPx module.
Note that the Capture/Compare mode operation is described with respect to Timer1 and the PWM mode operation is
described with respect to Timer2 in the following sections.
The Capture and Compare functions are identical for all CCP modules.
Important: In devices with more than one CCP module, it is very important to pay close attention to
the register names used. Throughout this section, the prefix “CCPx” is used as a generic replacement for
specific numbering. A number placed where the “x” is in the prefix is used to distinguish between separate
modules. For example, CCP1CON and CCP2CON control the same operational aspects of two completely
different CCP modules.
29.1
CCP Module Configuration
Each Capture/Compare/PWM module is associated with a control register (CCPxCON), a capture input selection
register (CCPxCAP) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers:
CCPRxL (low byte) and CCPRxH (high byte).
29.1.1
CCP Modules and Timer Resources
The CCP modules utilize Timers 1 through 6 that vary with the selected mode. Various timers are available to the
CCP modules in Capture, Compare or PWM modes, as shown in the table below.
Table 29-1. CCP Mode - Timer Resources
CCP Mode
Capture
Compare
PWM
Timer Resource
Timer1, Timer3 or Timer5
Timer2, Timer4 or Timer6
The assignment of a particular timer to a module is selected as shown in the “Capture, Compare, and PWM Timers
Selection” chapter. All of the modules may be active at once and may share the same timer resource if they are
configured to operate in the same mode (Capture/Compare or PWM) at the same time.
29.1.2
Open-Drain Output Option
When operating in Output mode (the Compare or PWM modes), the drivers for the CCPx pins can be optionally
configured as open-drain outputs. This feature allows the voltage level on the pin to be pulled to a higher level
through an external pull-up resistor and allows the output to communicate with external circuits without the need for
additional level shifters.
29.2
Capture Mode
Capture mode makes use of the 16-bit odd numbered timer resources (Timer1, Timer3, etc.). When an event occurs
on the capture source, the 16-bit CCPRx register captures and stores the 16-bit value of the TMRx register. An event
is defined as one of the following and is configured by the MODE bits:
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Preliminary Datasheet
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CCP - Capture/Compare/PWM Module
•
•
•
•
•
Every falling edge of CCPx input
Every rising edge of CCPx input
Every 4th rising edge of CCPx input
Every 16th rising edge of CCPx input
Every edge of CCPx input (rising or falling)
When a capture is made, the Interrupt Request Flag bit CCPxIF of the PIRx register is set. The interrupt flag must be
cleared in software. If another capture occurs before the value in the CCPRx register is read, the old captured value
is overwritten by the new captured value. The following figure shows a simplified diagram of the capture operation.
Important: If an event occurs during a 2-byte read, the high and low-byte data will be from different
events. It is recommended while reading the CCPRx register pair to either disable the module or read the
register pair twice for data integrity.
Figure 29-1. Capture Mode Operation Block Diagram
Rev. 10-000158E
3/11/2019
RxyPPS
CCPx
PPS
CTS
TRIS
CCPRx
Capture Trigger Sources
See CCPxCAP register
Prescaler
1,4,16
and
Edge Detect
set CCPxIF
16
16
CCPx
PPS
MODE
TMR1
CCPxPPS
29.2.1
Capture Sources
The capture source is selected with the CTS bits.
In Capture mode, the CCPx pin must be configured as an input by setting the associated TRIS control bit.
Important: If the CCPx pin is configured as an output, a write to the port can cause a capture condition.
29.2.2
Timer1 Mode for Capture
Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture
feature. In Asynchronous Counter mode, the capture operation may not work.
See the “TMR1 - Timer1 Module with Gate Control” chapter for more information on configuring Timer1.
29.2.3
Software Interrupt Mode
When the Capture mode is changed, a false capture interrupt may be generated. The user will keep the CCPxIE
Interrupt Priority bit of the PIEx register clear to avoid false interrupts. Additionally, the user will clear the CCPxIF
Interrupt Flag bit of the PIRx register following any change in Operating mode.
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CCP - Capture/Compare/PWM Module
Important: Clocking Timer1 from the system clock (FOSC) must not be used in Capture mode. In order for
Capture mode to recognize the trigger event on the CCPx pin, Timer1 must be clocked from the instruction
clock (FOSC/4) or from an external clock source.
29.2.4
CCP Prescaler
There are four prescaler settings specified by the MODE bits. Whenever the CCP module is turned off, or the CCP
module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter.
Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt.
To avoid this unexpected operation, turn the module off by clearing the CCPxCON register before changing the
prescaler. The example below demonstrates the code to perform this function.
Example 29-1. Changing Between Capture Prescalers
BANKSEL
CLRF
MOVLW
MOVWF
29.2.5
CCP1CON
CCP1CON
NEW_CAPT_PS
CCP1CON
;only needed when CCP1CON is not in ACCESS space
;Turn CCP module off
;CCP ON and Prescaler select → W
;Load CCP1CON with this value
Capture During Sleep
Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1
module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source.
When Timer1 is clocked by FOSC/4, Timer1 will not increment during Sleep. When the device wakes from Sleep,
Timer1 will continue from its previous state.
Capture mode will operate during Sleep when Timer1 is clocked by an external clock source.
29.3
Compare Mode
The Compare mode function described in this section is available and identical for all CCP modules.
Compare mode makes use of the 16-bit odd numbered Timer resources (Timer1, Timer3, etc.). The 16-bit value of
the CCPRx register is constantly compared against the 16-bit value of the TMRx register. When a match occurs, one
of the following events can occur:
•
•
•
•
•
•
Toggle the CCPx output and clear TMRx
Toggle the CCPx output without clearing TMRx
Set the CCPx output
Clear the CCPx output
Generate a Pulse output
Generate a Pulse output and clear TMRx
The action on the pin is based on the value of the MODE control bits.
All Compare modes can generate an interrupt. When MODE = 'b0001 or 'b1011, the CCP resets the TMRx
register.
The following figure shows a simplified diagram of the compare operation.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
CCP - Capture/Compare/PWM Module
Figure 29-2. Compare Mode Operation Block Diagram
MODE
Auto-conversion Trigger
CCPRx
CCPx
PPS
Q
S
R
Output
Logic
RxyPPS
Comparator
TMR1
TRIS
Set CCPxIF Interrupt Flag
29.3.1
CCPx Pin Configuration
The CCPx pin must be configured as an output in software by clearing the associated TRIS bit and defining the
appropriate output pin through the RxyPPS registers. See the “PPS - Peripheral Pin Select Module” chapter for
more details.
The CCP output can also be used as an input for other peripherals.
Important: Clearing the CCPxCON register will force the CCPx compare output latch to the default low
level. This is not the PORT I/O data latch.
29.3.2
Timer1 Mode for Compare
In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare
operation may not work in Asynchronous Counter mode.
See the “TMR1 - Timer1 Module with Gate Control” chapter for more information on configuring Timer1.
Important: Clocking Timer1 from the system clock (FOSC) must not be used in Compare mode. In order
for Compare mode to recognize the trigger event on the CCPx pin, Timer1 must be clocked from the
instruction clock (FOSC/4) or from an external clock source.
29.3.3
Compare During Sleep
Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep, unless the
timer is running. The device will wake on interrupt (if enabled).
29.4
PWM Overview
Pulse-Width Modulation (PWM) is a scheme that controls power to a load by switching quickly between fully ON and
fully OFF states. The PWM signal resembles a square wave where the high portion of the signal is considered the
ON state and the low portion of the signal is considered the OFF state. The high portion, also known as the pulse
width, can vary in time and is defined in steps. A larger number of steps applied, which lengthens the pulse width,
also supplies more power to the load. Lowering the number of steps applied, which shortens the pulse width, supplies
less power. The PWM period is defined as the duration of one complete cycle or the total amount of ON and OFF
time combined.
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CCP - Capture/Compare/PWM Module
PWM resolution defines the maximum number of steps that can be present in a single PWM period. A higher
resolution allows for more precise control of the pulse-width time and in turn the power that is applied to the load.
The term duty cycle describes the proportion of the ON time to the OFF time and is expressed in percentages, where
0% is fully OFF and 100% is fully ON. A lower duty cycle corresponds to less power applied and a higher duty cycle
corresponds to more power applied. The figure below shows a typical waveform of the PWM signal.
Figure 29-3. CCP PWM Output Signal
Period
Pulse Width
TMR2 = PR2
TMR2 = CCPRx
TMR2 = 0
29.4.1
Standard PWM Operation
The standard PWM function described in this section is available and identical for all CCP modules. It generates a
Pulse-Width Modulation (PWM) signal on the CCPx pin with up to ten bits of resolution. The period, duty cycle, and
resolution are controlled by the following registers:
•
•
•
•
Even numbered TxPR registers (T2PR, T4PR, etc.)
Even numbered TxCON registers (T2CON, T4CON, etc.)
16-bit CCPRx registers
CCPxCON registers
It is required to have FOSC/4 as the clock input to TxTMR for correct PWM operation. The following figure shows a
simplified block diagram of the PWM operation.
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Preliminary Datasheet
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CCP - Capture/Compare/PWM Module
Figure 29-4. Simplified PWM Block Diagram
Rev. 10-000 157C
2/20/201 9
Duty cycle registers
CCPRxH
CCPRxL
CCPx_out
10-bit Latch(2)
(Not accessible by user)
Comparator
R
S
Q
PPS
RxyPPS
TMR2 Module
R
TMR2
To Peripherals
set CCPIF
CCPx
TRIS Control
(1)
ERS logic
Comparator
CCPx_pset
PR2
Notes:
1. 8-bit timer is concatenated with two bits generated by Fosc or two bits of the internal prescaler to
create 10-bit time-base.
2. The alignment of the 10 bits from the CCPR register is determined by the CCPxFMT bit.
Important: The corresponding TRIS bit must be cleared to enable the PWM output on the CCPx pin.
29.4.2
Setup for PWM Operation
The following steps illustrate how to configure the CCP module for standard PWM operation:
1.
2.
3.
4.
5.
6.
Select the desired output pin with the RxyPPS control to select CCPx as the source. Disable the selected pin
output driver by setting the associated TRIS bit. The output will be enabled later at the end of the PWM setup.
Load the selected timer period register TxPR register with the PWM period value.
Configure the CCP module for the PWM mode by loading the CCPxCON register with the appropriate values.
Load the CCPRx register with the PWM duty cycle value and configure the FMT bit to set the proper register
alignment.
Configure and start the selected Timer:
– Clear the TMRxIF Interrupt Flag bit of the PIRx register. See Note below.
– Select the timer clock source to be as FOSC/4. This is required for correct operation of the PWM module.
– Configure the TxCKPS bits of the TxCON register with the desired Timer prescale value.
– Enable the Timer by setting the TxON bit.
Enable the PWM output:
– Wait until the Timer overflows and the TMRxIF bit of the PIRx register is set. See Note below.
– Enable the CCPx pin output driver by clearing the associated TRIS bit.
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CCP - Capture/Compare/PWM Module
Important: In order to send a complete duty cycle and period on the first PWM output, the
above steps must be included in the setup sequence. If it is not critical to start with a complete
PWM signal on the first output, then step 6 may be ignored.
29.4.3
Timer2 Timer Resource
The PWM standard mode makes use of the 8-bit Timer2 timer resources to specify the PWM period.
29.4.4
PWM Period
The PWM period is specified by the T2PR register of Timer2. The PWM period can be calculated using the formula in
the equation below.
Equation 29-1. PWM Period
PWMPeriod =
T2PR + 1 • 4 • TOSC • TMR2PrescaleValue
where TOSC = 1/FOSC
When T2TMR is equal to T2PR, the following three events occur on the next increment event:
•
•
•
T2TMR is cleared
The CCPx pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.)
The PWM duty cycle is transferred from the CCPRx register into a 10-bit buffer.
Important: The Timer postscaler (see “Timer2 Interrupt”) is not used in the determination of the PWM
frequency.
29.4.5
PWM Duty Cycle
The PWM duty cycle is specified by writing a 10-bit value to the CCPRx register. The alignment of the 10-bit value is
determined by the FMT bit (see Figure 29-5). The CCPRx register can be written to at any time. However, the duty
cycle value is not latched into the 10-bit buffer until after a match between T2PR and T2TMR.
The equations below are used to calculate the PWM pulse width and the PWM duty cycle ratio.
Figure 29-5. PWM 10-Bit Alignment
CCP RxH
CCP RxL
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
FMT = 1
FMT = 0
CCP RxH
CCP RxL
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
10-bit Duty Cycle
9 8 7 6 5 4 3 2 1 0
Equation 29-2. Pulse Width
Pulse Widtℎ = CCPRxH: CCPRxL register value • TOSC • TMR2 Prescale Value
Equation 29-3. Duty Cycle
CCPRxH: CCPRxL register value
DutyCycleRatio =
4 T2PR + 1
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Preliminary Datasheet
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CCP - Capture/Compare/PWM Module
The CCPRx register is used to double buffer the PWM duty cycle. This double buffering is essential for glitchless
PWM operation.
The 8-bit timer T2TMR register is concatenated with either the 2-bit internal system clock (FOSC), or two bits of the
prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1.
When the 10-bit time base matches the CCPRx register, then the CCPx pin is cleared (see Figure 29-4).
29.4.6
PWM Resolution
The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will
result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles.
The maximum PWM resolution is ten bits when T2PR is 0xFF. The resolution is a function of the T2PR register value,
as shown below.
Equation 29-4. PWM Resolution
log 4 T2PR + 1
Resolution =
bits
log 2
Important: If the pulse-width value is greater than the period, the assigned PWM pin(s) will remain
unchanged.
Table 29-2. Example PWM Frequencies and Resolutions (FOSC = 20 MHz)
PWM Frequency
Timer Prescale
T2PR Value
Maximum Resolution (bits)
1.22 kHz
4.88 kHz
19.53 kHz
78.12 kHz
156.3 kHz
208.3 kHz
16
4
1
1
1
1
0xFF
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
8
7
6.6
Table 29-3. Example PWM Frequencies and Resolutions (FOSC = 8 MHz)
PWM Frequency
Timer Prescale
T2PR Value
Maximum Resolution (bits)
29.4.7
1.22 kHz
4.90 kHz
19.61 kHz
76.92 kHz
153.85 kHz
200.0 kHz
16
4
1
1
1
1
0x65
0x65
0x65
0x19
0x0C
0x09
8
8
8
6
5
5
Operation in Sleep Mode
In Sleep mode, the T2TMR register will not increment and the state of the module will not change. If the CCPx pin is
driving a value, it will continue to drive that value. When the device wakes up, T2TMR will continue from the previous
state.
29.4.8
Changes in System Clock Frequency
The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will
result in changes to the PWM frequency. See the “OSC - Oscillator Module (with Fail-Safe Clock Monitor)”
chapter for additional details.
29.4.9
Effects of Reset
Any Reset will force all ports to Input mode and the CCP registers to their Reset states.
29.5
Register Definitions: CCP Control
Long bit name prefixes for the CCP peripherals are shown in the following table. Refer to the “Long Bit Names”
section in the “Register and Bit Naming Conventions” chapter for more information.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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CCP - Capture/Compare/PWM Module
Table 29-4. CCP Long bit name prefixes
Peripheral
Bit Name Prefix
CCP1
CCP1
CCP2
CCP2
CCP3
CCP3
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CCP - Capture/Compare/PWM Module
29.5.1
CCPxCON
Name:
Address:
CCPxCON
0x342,0x346,0x34A
CCP Control Register
Bit
7
EN
R/W
0
Access
Reset
6
5
OUT
R
x
4
FMT
R/W
0
3
2
1
0
R/W
0
R/W
0
MODE[3:0]
R/W
0
R/W
0
Bit 7 – EN CCP Module Enable
Value
Description
1
CCP is enabled
0
CCP is disabled
Bit 5 – OUT CCP Output Data (read-only)
Bit 4 – FMT CCPW (pulse-width) Value Alignment
Value
Condition
x
Capture mode
x
Compare mode
1
PWM mode
0
PWM mode
Description
Not used
Not used
Left-aligned format
Right-aligned format
Bits 3:0 – MODE[3:0] CCP Mode Select
Table 29-5. CCPx Mode Select
MODE Value
Operating Mode
11xx
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
PWM
Compare
Capture
Compare
Operation
PWM operation
Pulse output; clear TMR1(2)
Pulse output
Clear output(1)
Set output(1)
Every 16th rising edge of CCPx input
Every 4th rising edge of CCPx input
Every rising edge of CCPx input
Every falling edge of CCPx input
Every edge of CCPx input
Toggle output
Toggle output; clear TMR1(2)
Disabled
Set CCPxIF
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
—
Notes:
1. The set and clear operations of the Compare mode are reset by setting MODE = 'b0000 or EN = 0.
2.
When MODE = 'b0001 or 'b1011, then the timer associated with the CCP module is cleared. TMR1 is the
default selection for the CCP module, so it is used for indication purposes only.
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Preliminary Datasheet
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CCP - Capture/Compare/PWM Module
29.5.2
CCPxCAP
Name:
Address:
CCPxCAP
0x343,0x347,0x34B
Capture Trigger Input Selection Register
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
CTS[3:0]
Access
Reset
R/W
0
R/W
0
Bits 3:0 – CTS[3:0] Capture Trigger Input Selection
Table 29-6. Capture Trigger Sources
CTS Value
1100-1111
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
© 2021 Microchip Technology Inc.
Source
Reserved
CLC8_OUT
CLC7_OUT
CLC6_OUT
CLC5_OUT
CLC4_OUT
CLC3_OUT
CLC2_OUT
CLC1_OUT
IOC Interrupt
CMP2_OUT
CMP1_OUT
Pin selected by CCPxPPS
Preliminary Datasheet
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CCP - Capture/Compare/PWM Module
29.5.3
CCPRx
Name:
Address:
CCPRx
0x340,0x344,0x348
Capture/Compare/Pulse Width Register
Bit
15
14
13
12
11
10
9
8
R/W
x
R/W
x
R/W
x
R/W
x
3
2
1
0
R/W
x
R/W
x
R/W
x
R/W
x
CCPR[15:8]
Access
Reset
Bit
R/W
x
R/W
x
R/W
x
R/W
x
7
6
5
4
CCPR[7:0]
Access
Reset
R/W
x
R/W
x
R/W
x
R/W
x
Bits 15:0 – CCPR[15:0] Capture/Compare/Pulse Width
Reset States: POR/BOR = xxxxxxxxxxxxxxxx
All other Resets = uuuuuuuuuuuuuuuu
Notes: The individual bytes in this multibyte register can be accessed with the following register names:
• When MODE = Capture or Compare
– CCPRxH: Accesses the high byte CCPR[15:8]
– CCPRxL: Accesses the low byte CCPR[7:0]
• When MODE = PWM and FMT = 0
•
– CCPRx[15:10]: Not used
– CCPRxH[1:0]: Accesses the two Most Significant bits CCPR[9:8]
– CCPRxL: Accesses the eight Least Significant bits CCPR[7:0]
When MODE = PWM and FMT = 1
– CCPRxH: Accesses the eight Most Significant bits CCPR[9:2]
– CCPRxL[7:6]: Accesses the two Least Significant bits CCPR[1:0]
– CCPRx[5:0]: Not used
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Preliminary Datasheet
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CCP - Capture/Compare/PWM Module
29.6
Register Summary - CCP Control
Address
Name
0x00
...
0x033F
Reserved
0x0340
CCPR1
0x0342
0x0343
CCP1CON
CCP1CAP
0x0344
CCPR2
0x0346
0x0347
CCP2CON
CCP2CAP
0x0348
CCPR3
0x034A
0x034B
CCP3CON
CCP3CAP
Bit Pos.
7:0
15:8
7:0
7:0
7:0
15:8
7:0
7:0
7:0
15:8
7:0
7:0
7
EN
EN
EN
© 2021 Microchip Technology Inc.
6
5
4
OUT
CCPR[7:0]
CCPR[15:8]
FMT
OUT
CCPR[7:0]
CCPR[15:8]
FMT
OUT
CCPR[7:0]
CCPR[15:8]
FMT
Preliminary Datasheet
3
2
1
0
MODE[3:0]
CTS[3:0]
MODE[3:0]
CTS[3:0]
MODE[3:0]
CTS[3:0]
DS40002213D-page 525
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Capture, Compare, and PWM Timers Selection
30.
Capture, Compare, and PWM Timers Selection
Each of these modules has an independent timer selection which can be accessed using the timer selection register.
The default timer selection is Timer1 for capture or compare functions and Timer2 for PWM functions.
30.1
Register Definitions: Capture, Compare, and PWM Timer Selection
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Preliminary Datasheet
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PIC18F27/47/57Q84
Capture, Compare, and PWM Timers Selection
30.1.1
CCPTMRS0
Name:
Address:
CCPTMRS0
0x34C
CCP Timers Selection Register
Bit
7
6
Access
Reset
5
4
C3TSEL[1:0]
R/W
R/W
0
1
3
2
C2TSEL[1:0]
R/W
R/W
0
1
1
0
C1TSEL[1:0]
R/W
R/W
0
1
Bits 0:1, 2:3, 4:5 – CnTSEL CCPn Timer Selection
CnTSEL Value
Capture/Compare
PWM
11
10
01
00
Timer5
Timer3
Timer1
Timer6
Timer4
Timer2
© 2021 Microchip Technology Inc.
Reserved
Preliminary Datasheet
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PIC18F27/47/57Q84
Capture, Compare, and PWM Timers Selection
30.2
Address
0x00
...
0x034B
0x034C
Register Summary - Capture, Compare, and PWM Timers Selection
Name
Bit Pos.
7
6
5
4
3
2
1
0
Reserved
CCPTMRS0
7:0
© 2021 Microchip Technology Inc.
C3TSEL[1:0]
Preliminary Datasheet
C2TSEL[1:0]
C1TSEL[1:0]
DS40002213D-page 528
PIC18F27/47/57Q84
PWM - Pulse-Width Modulator with Compare
31.
PWM - Pulse-Width Modulator with Compare
This module is a 16-bit Pulse-Width Modulator (PWM) with a compare feature and multiple outputs. The outputs are
grouped in slices where each slice has two outputs. There can be up to four slices in each PWM module. The EN
bit enables the PWM operation for all slices simultaneously. The prescale counter, postscale counter, and all internal
logic is held in Reset while the EN bit is low.
Features of this module include the following:
• Five main operating modes:
– Left-Aligned
– Right-Aligned
– Center-Aligned
– Variable-Aligned
– Compare
• Pulsed
• Toggled
• Push-pull operation (available in Left and Right Aligned modes only)
• Independent 16-bit period timer
• Programmable clock sources
• Programmable trigger sources for synchronous duty cycle and period changes
• Programmable synchronous/asynchronous Reset sources
• Programmable Reset source polarity control
• Programmable PWM output polarity control
• Up to four two-output slices per module
Block diagrams of each PWM mode are shown in their respective sections.
31.1
Output Slices
A PWM module can have up to four output slices. An output slice consists of two PWM outputs, PWMx_SaP1_out
and PWMx_SaP2_out. Both share the same operating mode. However, other slices may operate in a different mode.
PWMx_SaP1_out and PWMx_SaP2_out have independent duty cycles which are set with the respective P1 and P2
parameter registers.
31.1.1
Output Polarity
The polarity for the PWMx_SaP1_out and PWMx_SaP2_out is controlled with the respective POL1 and POL2 bits.
Setting the polarity bit inverts the output Active state to low true. Toggling the polarity bit toggles the output whether or
not the PWM module is enabled.
31.1.2
Operating Modes
Each output slice can operate in one of six modes selected with the MODE bits. The Left and Right-Aligned modes
can also be operated in Push-Pull mode by setting the PPEN bit. The following sections provide more details on each
mode including block diagrams.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 529
PIC18F27/47/57Q84
PWM - Pulse-Width Modulator with Compare
31.1.2.1 Left-Aligned Mode
In Left-Aligned mode, the active part of the duty cycle is at the beginning of the period. The outputs start active and
stay active for the number of prescaled PWM clock periods specified by the P1 and P2 parameter registers then go
inactive for the remainder of the period. Block and timing diagrams follow.
Figure 31-1. Left-Aligned Block Diagram
P1 Buffer
Duty Cycle
Reset
PR Buffer
PWMx_SaP1_out
Q
Set
Clock
Sources
Prescale
PWMx_clk
Period
Event
Timer
Set
PWMxCLK
PWMx_SaP2_out
Q
Reset
Duty Cycle
P2 Buffer
Figure 31-2. Left-Aligned Timing Diagram
PWMx_clk
PWMx_timer
0
1
2
3
4
5
0
1
2
3
4
5
0
1
SaP1_out
SaP2_out
SaP1IF
SaP2IF
Reset by software
PWMxPIF
PWMxIF
Note: MODE=’b000, PR=5, P1=4, P2=2
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 530
PIC18F27/47/57Q84
PWM - Pulse-Width Modulator with Compare
31.1.2.2 Right-Aligned Mode
In Right-Aligned mode, the active part of the duty cycle is at the end of the period. The outputs start in the Inactive
state and then go Active the number of prescaled PWM clock periods specified by the P1 and P2 parameter registers
before the end of the period. Block and timing diagrams follow.
Figure 31-3. Right-Aligned Block Diagram
P1 Buffer
Duty Cycle
Set
PR Buffer
PWMx_SaP1_out
Q
Reset
Clock
Sources
Prescale
PWMx_clk
Period
Event
Timer
Reset
PWMxCLK
PWMx_SaP2_out
Q
Set
Duty Cycle
P2 Buffer
Figure 31-4. Right-Aligned Timing Diagram
PWMx_clk
PWMx_timer
0
1
2
3
4
5
0
1
2
3
4
5
0
1
SaP1_out
SaP2_out
SaP2IF
SaP1IF
Reset by software
Note: MODE=’b001, PR=5, P1=4, P2=2
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 531
PIC18F27/47/57Q84
PWM - Pulse-Width Modulator with Compare
31.1.2.3 Center-Aligned Mode
In Center-Aligned mode, the active duty cycle is centered in the period. The period for this mode is twice that of other
modes, as shown in the following equation.
Equation 31-1. Center-Aligned Period
PR + 1 × 2
Period =
FPWMx_clk
The parameter register specifies the number of PWM clock periods that the output goes Active before the period
center. The output goes inactive the same number of prescaled PWM clock periods after the period center. Block and
timing diagrams follow.
Figure 31-5. Center-Aligned Block Diagram
P1 Buffer
Duty Cycle
Reset
PR Buffer
PWMx_SaP1_out
Q
Set
Clock
Sources
Prescale
PWMx_clk
Period
Event
Timer
Set
PWMxCLK
PWMx_SaP2_out
Q
Reset
Duty Cycle
P2 Buffer
Figure 31-6. Center-Aligned Timing Diagram
PWMx_clk
PWMx_timer
0
1
2
3
4
5
0
1
2
3
4
5
0
1
SaP1_out
SaP2_out
SaP1IF
Reset by software
SaP2IF
Note: MODE=’b010 PR=5, P1=4, P2=2
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 532
PIC18F27/47/57Q84
PWM - Pulse-Width Modulator with Compare
31.1.2.4 Variable-Alignment Mode
In Variable-Alignment mode, the active part of the duty cycle starts when the parameter 1 value (P1) matches
the timer and ends when the parameter 2 value (P2) matches the timer. Both outputs are identical because both
parameter values are used for the same duty cycle. Block and timing diagrams follow.
Figure 31-7. Variable-Alignment Block Diagram
P1 Buffer
=
PR Buffer
Set
PWMx_SaP1_out
Q
Clock
Sources
Prescale
PWMx_clk
Reset
Period
Event
Timer
PWMxCLK
PWMx_SaP2_out
=
P2 Buffer
Figure 31-8. Variable-Alignment Timing Diagram
PWMx_clk
PWMx_timer
0
1
2
3
4
5
0
1
2
3
4
5
0
1
SaP1_out
SaP2_out
SaP1IF
Reset by software
SaP1IF
PWMxPIF
Note: MODE=’b011 PR=5, P1=4, P2=2
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 533
PIC18F27/47/57Q84
PWM - Pulse-Width Modulator with Compare
31.1.2.5 Compare Modes
In the Compare modes, the PWM timer is compared to the P1 and P2 parameter values. When a match occurs,
the output is either pulsed or toggled. In Pulsed Compare mode, the duty cycle is always one prescaled PWM clock
period. In Toggle Compare mode, the duty cycle is always one full PWM period. Refer to the following sections for
more details.
31.1.2.5.1 Pulsed Compare Mode
In Pulsed Compare mode, the duty cycle is one prescaled PWM clock period that starts when the timer matches the
parameter value and ends one prescaled PWM clock period later. The outputs start in the Inactive state and then go
Active during the duty cycle. Block and timing diagrams follow.
Figure 31-9. Pulsed Compare Block Diagram
P1 Buffer
=
Pulse
Clock
Sources
Prescale
PWMx_clk
Period
Event
Timer
PWMx_SaP1_out
Q
PR Buffer
PWMx_SaP2_out
Q
Pulse
PWMxCLK
=
P2 Buffer
Figure 31-10. Pulsed Compare Timing Diagram
PWMx_clk
PWMx_timer
0
1
2
3
4
5
0
1
2
3
4
5
0
1
SaP1_out
SaP2_out
SaP1IF
Reset by software
SaP1IF
PWMxPIF
Note: MODE=’b100 PR=5, P1=4, P2=2
31.1.2.5.2 Toggled Compare
In Toggled Compare mode, the duty cycle is alternating full PWM periods. The output goes Active when the PWM
timer matches the P1 or P2 parameter value and goes Inactive in the next period at the same match point. Block and
timing diagrams follow.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 534
PIC18F27/47/57Q84
PWM - Pulse-Width Modulator with Compare
Figure 31-11. Toggled Compare Block Diagram
P1 Buffer
=
Toggle
Clock
Sources
Prescale
PWMx_clk
Period
Event
Timer
PWMx_SaP1_out
Q
PR Buffer
PWMx_SaP2_out
Q
Toggle
PWMxCLK
=
P2 Buffer
Figure 31-12. Toggled Compare Timing Diagram
PWMx_clk
PWMx_timer
0
1
2
3
4
5
0
1
2
3
4
5
0
1
SaP1_out
SaP2_out
SaP1IF
Reset by software
SaP1IF
PWMxPIF
Note: MODE=’b101 PR=5, P1=4, P2=2
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 535
PIC18F27/47/57Q84
PWM - Pulse-Width Modulator with Compare
31.1.3
Push-Pull Mode
The Push-Pull mode is enabled by setting the PPEN bit. Push-Pull operates only in the Left-Aligned and RightAligned modes. In the Push-Pull mode, the outputs are Active every other PWM period. PWMx_SaP1_out is Active
when the PWMx_SaP2_out is not and the PWMx_SaP2_out is Active when the PWMx_SaP1_out is not. When the
parameter value (P1 or P2) is greater than the period value (PR), then the corresponding output is Active for one full
PWM period. The following figures illustrate timing examples of Left and Right-Aligned Push-Pull modes.
Figure 31-13. Left-Aligned Push-Pull Mode Timing Diagram
PWMx_clk
PWMx_timer
0
1
2
3
4
5
0
1
2
3
4
5
0
1
SaP1_out
SaP2_out
SaP1IF
SaP2IF
Reset by software
Note: MODE=’b000, PR=5, P1=4, P2=2, PPEN=1
Figure 31-14. Right-Aligned Push-Pull Mode Timing Diagram
PWMx_clk
PWMx_timer
0
1
2
3
4
5
0
1
2
3
4
5
0
1
SaP1_out
SaP2_out
SaP1IF
Reset by software
SaP2IF
Note: MODE=’b001, PR=5, P1=6, P2=2, PPEN=1
31.2
Period Timer
All slices in a PWM instance operate with the same period. The value written to the PWMxPR register is one less
than the number of prescaled PWM clock periods (PWM_clk) in the PWM period.
The PWMxPR register is double buffered. When the PWM is operating, writes to the PWMxPR register are
transferred to the period buffer only after the LD bit is set or an external load event occurs. The transfer occurs
at the next period Reset event. If the LD bit is set less than three PWM clock periods before the end of the period,
then the transfer may be one full period later.
Loading the buffers of multiple PWM instances can be coordinated using the PWMLOAD register. See the Buffered
Period and Parameter Registers section for more details.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 536
PIC18F27/47/57Q84
PWM - Pulse-Width Modulator with Compare
31.3
Clock Sources
The time base for the PWM period prescaler is selected with the CLK bits. Changes take effect immediately when
written. Clearing the EN bit before making clock source changes is recommended to avoid unexpected behavior.
31.3.1
Clock Prescaler
The PWM clock frequency can be reduced with the clock prescaler. There are 256 prescale selections from 1:1 to
1:256.
The CPRE bits select the prescale value. Changes to the prescale value take effect immediately. Clearing the EN bit
before making prescaler changes is recommended to avoid unexpected behavior. The prescale counter is reset when
the EN bit is cleared.
31.4
External Period Resets
The period timer can be reset and held at zero by a logic level from one of various sources. The Reset event also
resets the postscaler counter. The resetting source is selected with the ERS bits.
The Reset can be configured with the ERSNOW bit to occur on either the next PWM clock or the next PWM period
Reset event. When the ERSNOW bit is set, then the Reset will occur on the next PWM clock. When the ERSNOW
bit is cleared, then the Reset will be held off until the period normally resets at the end of the period. The difference
between a normal period Reset and an ERS Reset is that once the timer is reset it is held at zero until the ERS signal
goes false. The following timing diagrams illustrate the two types of external Reset.
Figure 31-15. Right-Aligned Mode with ERSNOW = 1
PWMx_clk
PWMx_timer
0
1
2
3
4
5
0
1
2
3
0
0
0
1
5
0
0
0
1
2
3
4
5
PWMx_ers
SaP1_out
SaP2_out
Note: PR=5, P1=4, P2=2
Figure 31-16. Left-Aligned Mode with ERSNOW = 0
PWMx_clk
PWMx_timer
0
1
2
3
4
PWMx_ers
SaP1_out
SaP2_out
Note: PR=5, P1=4, P2=2
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 537
PIC18F27/47/57Q84
PWM - Pulse-Width Modulator with Compare
31.5
Buffered Period and Parameter Registers
The PWMxPR, PWMxSaP1 and PWMxSaP2 registers are double buffered. The PWM module operates on the
buffered copies. The values in all these registers are copied to the buffer registers when the PWM module is enabled.
Changes to the PWMxPR, PWMxSaP1 and PWMxSaP2 registers do not affect the buffer registers while the PWM is
operating until either software sets the LD bit or an external load event occurs. For all operating modes except Center
Aligned, the values are copied to the buffer registers when the PWM timer is reloaded at the end of the period in
which the load request occurred. In the Center Aligned mode the buffer update occurs on every other period Reset
event because one full center aligned period uses two period cycles. Load requests that occur three or less clocks
before the end of the period may not be serviced until the following period.
A list of external load trigger sources is shown in the PWMxLDS register. Software can set the LD bits of multiple
PWM instances simultaneously with the PWMLOAD register.
Important: No changes are allowed after the LD bit is set until after the LD bit is cleared by hardware.
Unexpected behavior may result if the LD bit is cleared by software.
31.6
Synchronizing Multiple PWMs
To synchronize multiple PWMs, the PWMEN register is used to enable selected PWMs simultaneously. The bits in
the PWMEN register are mirror copies of the EN bit of every PWM in the device. Setting or clearing the EN bits in the
PWMEN register enables or disables all the corresponding PWMs simultaneously.
31.7
Interrupts
Each PWM instance has a period interrupt and interrupts associated with the mode and parameter settings.
31.7.1
Period Interrupt
The period interrupt occurs when the PWMx timer value matches the PR value, thereby also resetting the PWMx
timer. Refer to Figure 31-2 for a timing example. The period interrupt is indicated with the PWMxPIF flag bit in one
of the PIR registers and is set whether or not the interrupt is enabled. This flag must be reset by software. The
PWMxPIF interrupt is enabled with the PWMxPIE bit in the corresponding PIE register.
31.7.1.1 Period Interrupt Postscaler
The frequency of the period interrupt events can be reduced with the period interrupt postscaler. A postscaler counter
suppresses period interrupts until the postscale count is reached. Only one PWM period interrupt is generated for
every postscale counts. There are 256 postscale selections from 1:1 to 1:256.
The PIPOS bits select the postscale value. Changes to the postscale value take effect immediately. Clearing the EN
bit before making postscaler changes is recommended to avoid unexpected behavior. The postscale counter is reset
when the EN bit is cleared.
31.7.2
Parameter Interrupts
The P1 and P2 parameters in each slice have interrupts that occur depending on the selected mode. The individual
parameter interrupts are indicated in the PWMxGIR register and enabled by the corresponding bits in the PWMxGIE
register.
A timing example is shown in Figure 31-2. Refer to the timing diagrams of each of the other modes for more details.
All the enabled PWMxGIR interrupts of one PMW instance are OR’d together into the PWMxIF bit in one of the PIR
registers. The PWMxIF bit is read-only. When any of the PWMxGIR bits are set then the PWMxIF bit is true. All
PWMxGIF flags must be reset to clear the PWMxIF bit. The PWMxIF interrupt is enabled with the PWMxIE bit in the
corresponding PIE register.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 538
PIC18F27/47/57Q84
PWM - Pulse-Width Modulator with Compare
31.8
Operation During Sleep
The PWM module operates in Sleep only if the PWM clock is Active. Some internal clock sources are automatically
enabled to operate in Sleep when a peripheral using them is enabled. Those clock sources are identified in the clock
source table shown in the PWMxCLK clock source selection register.
31.9
Register Definitions: PWM Control
Long bit name prefixes for the PWM peripherals are shown in the table below. Refer to the “Long Bit Names”
section in the “Register and Bit Naming Conventions” chapter for more information.
Table 31-1. PWM Bit Name Prefixes
Peripheral
Bit Name Prefix
PWM1
PWM1
PWM2
PWM2
PWM3
PWM3
PWM4
PWM4
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
PWM - Pulse-Width Modulator with Compare
31.9.1
PWMxERS
Name:
Address:
PWMxERS
0x460,0x46F,0x47E,0x48D
PWMx External Reset Source
Bit
7
6
5
Access
Reset
4
3
R/W
0
R/W
0
2
ERS[4:0]
R/W
0
1
0
R/W
0
R/W
0
Bits 4:0 – ERS[4:0] External Reset Source Select
ERS
11111-10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
Reset Source
PWM1
PWM4S1P2_OUT
PWM4S1P1_OUT
PWM3S1P2_OUT
PWM3S1P1_OUT
PWM2S1P2_OUT
PWM2S1P1_OUT
Reserved
Reserved
PWM1ERSPPS
© 2021 Microchip Technology Inc.
PWM2
PWM3
Reserved (ERS Disabled)
CLC8_OUT
CLC7_OUT
CLC6_OUT
CLC5_OUT
CLC4_OUT
CLC3_OUT
CLC2_OUT
CLC1_OUT
PWM4S1P2_OUT
PWM4S1P2_OUT
PWM4S1P1_OUT
PWM4S1P1_OUT
PWM3S1P2_OUT
Reserved
PWM3S1P1_OUT
Reserved
Reserved
PWM2S1P2_OUT
Reserved
PWM2S1P1_OUT
PWM1S1P2_OUT
PWM1S1P2_OUT
PWM1S1P1_OUT
PWM1S1P1_OUT
PWM2ERSPPS
PWM3ERSPPS
ERS Disabled
Preliminary Datasheet
PWM4
Reserved
Reserved
PWM3S1P2_OUT
PWM3S1P1_OUT
PWM2S1P2_OUT
PWM2S1P1_OUT
PWM1S1P2_OUT
PWM1S1P1_OUT
PWM4ERSPPS
DS40002213D-page 540
PIC18F27/47/57Q84
PWM - Pulse-Width Modulator with Compare
31.9.2
PWMxCLK
Name:
Address:
PWMxCLK
0x461,0x470,0x47F,0x48E
PWMx Clock Source
Bit
7
6
5
Access
Reset
4
3
R/W
0
R/W
0
2
CLK[4:0]
R/W
0
1
0
R/W
0
R/W
0
Bits 4:0 – CLK[4:0] PWM Clock Source Select
CLK
11111-10110
10100
10011
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
Source
Operates in Sleep
Reserved
N/A
CLC8_OUT
Yes(1)
CLC7_OUT
Yes(1)
CLC6_OUT
Yes(1)
CLC5_OUT
Yes(1)
CLC4_OUT
Yes(1)
CLC3_OUT
Yes(1)
CLC2_OUT
Yes(1)
CLC1_OUT
Yes(1)
NCO3_OUT
Yes(1)
NCO2_OUT
Yes(1)
NCO1_OUT
Yes(1)
CLKREF
Yes(1)
EXTOSC
Yes
SOSC
Yes
MFINTOSC (32 kHz)
Yes
MFINTOSC (500 kHz)
Yes
LFINTOSC
Yes
HFINTOSC
Yes
FOSC
No
PWMIN1PPS
Yes(1)
PWMIN0PPS
Yes(1)
Note: Operation during Sleep is possible if the clock supplying the source peripheral operates in Sleep.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 541
PIC18F27/47/57Q84
PWM - Pulse-Width Modulator with Compare
31.9.3
PWMxLDS
Name:
Address:
PWMxLDS
0x462,0x471,0x480,0x48F
PWMx Auto-load Trigger Source Select Register
Bit
7
6
Access
Reset
5
4
3
R/W
0
R/W
0
2
LDS[4:0]
R/W
0
1
0
R/W
0
R/W
0
Bits 4:0 – LDS[4:0] Auto-load Trigger Source Select
LDS
11111-10011
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
© 2021 Microchip Technology Inc.
Source
Auto-load Disabled
DMA8_Destination_Count_Done
DMA7_Destination_Count_Done
DMA6_Destination_Count_Done
DMA5_Destination_Count_Done
DMA4_Destination_Count_Done
DMA3_Destination_Count_Done
DMA2_Destination_Count_Done
DMA1_Destination_Count_Done
CLC8_OUT
CLC7_OUT
CLC6_OUT
CLC5_OUT
CLC4_OUT
CLC3_OUT
CLC2_OUT
CLC1_OUT
PWMIN1PPS
PWMIN0PPS
Auto-load Disabled
Preliminary Datasheet
DS40002213D-page 542
PIC18F27/47/57Q84
PWM - Pulse-Width Modulator with Compare
31.9.4
PWMxPR
Name:
Address:
PWMxPR
0x463,0x472,0x481,0x490
PWMx Period Register
Determines the PWMx period
Bit
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
PR[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
PR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – PR[15:0] PWM Period
Number of PWM clocks periods in the PWM period
Notes: The individual bytes in this multibyte register can be accessed with the following register names:
• PWMxPRH: Accesses the high byte PR[15:8]
• PWMxPRL: Accesses the low byte PR[7:0]
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 543
PIC18F27/47/57Q84
PWM - Pulse-Width Modulator with Compare
31.9.5
PWMxCPRE
Name:
Address:
PWMxCPRE
0x465,0x474,0x483,0x492
PWMx Clock Prescaler Register
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CPRE[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – CPRE[7:0] PWM Clock Prescale Value
Value
Description
n
PWM clock is prescaled by n+1
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
PWM - Pulse-Width Modulator with Compare
31.9.6
PWMxPIPOS
Name:
Address:
PWMxPIPOS
0x466,0x475,0x484,0x493
PWMx Period Interrupt Postscaler Register
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
PIPOS[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – PIPOS[7:0] Period Interrupt Postscale Value
Value
Description
n
Period interrupt occurs after n+1 period events
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
PWM - Pulse-Width Modulator with Compare
31.9.7
PWMxGIR
Name:
Address:
PWMxGIR
0x467,0x476,0x485,0x494
PWMx Interrupt Register
Bit
7
6
5
4
3
Access
Reset
2
1
S1P2
R/W/HS
0
0
S1P1
R/W/HS
0
Bit 1 – SaP2 Slice “a” Parameter 2 Interrupt Flag
Value
MODE
Description
1
Variable-aligned or Compare
Compare match between P2 and PWM counter has occurred
1
Center-aligned
PWMx_SaP2_out has changed
1
Right-aligned
Left edge of PWMx_SaP2_out pulse has occurred
1
Left-aligned
Right edge of PWMx_SaP2_out pulse has occurred
0
All
Interrupt event has not occurred
Bit 0 – SaP1 Slice “a” Parameter 1 Interrupt Flag
Value
MODE
Description
1
Variable-aligned or Compare
Compare match between P1 and PWM counter has occurred
1
Center-aligned
PWMx_SaP1_out has changed
1
Right-aligned
Left edge of PWMx_SaP1_out pulse has occurred
1
Left-aligned
Right edge of PWMx_SaP1_out pulse has occurred
0
All
Interrupt event has not occurred
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 546
PIC18F27/47/57Q84
PWM - Pulse-Width Modulator with Compare
31.9.8
PWMxGIE
Name:
Address:
PWMxGIE
0x468,0x477,0x486,0x495
PWMx Interrupt Enable Register
Bit
7
6
5
4
3
Access
Reset
2
1
S1P2
R/W
0
0
S1P1
R/W
0
Bit 1 – SaP2 Slice “a” Parameter 2 Interrupt Enable
Value
Description
1
Slice “a” Parameter 2 match interrupt is enabled
0
Slice “a” Parameter 2 match interrupt is not enabled
Bit 0 – SaP1 Slice “a” Parameter 1 Interrupt Enable
Value
Description
1
Slice “a” Parameter 1 match interrupt is enabled
0
Slice “a” Parameter 1 match interrupt is not enabled
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 547
PIC18F27/47/57Q84
PWM - Pulse-Width Modulator with Compare
31.9.9
PWMxCON
Name:
Address:
PWMxCON
0x469,0x478,0x487,0x496
PWM Control Register
Bit
Access
Reset
7
EN
R/W
0
6
5
4
3
2
LD
R/W/HC
0
1
ERSPOL
R/W
0
0
ERSNOW
R/W
0
Bit 7 – EN PWM Module Enable
Value
Description
1
PWM module is enabled
0
PWM module is disabled. The prescaler, postscaler, and all internal logic is reset. Outputs go to their
default states. Register values remain unchanged.
Bit 2 – LD Reload Registers
Reload the period and duty cycle registers on the next period event
Value
Description
1
Reload PR/P1/P2 registers
0
Reload not enabled or reload complete
Bit 1 – ERSPOL External Reset Polarity Select
Value
Description
1
External Reset input is active-low
0
External Reset input is active-high
Bit 0 – ERSNOW External Reset Mode Select
Determines when an external Reset event takes effect.
Value
Description
1
Stop counter on the next PWM clock. Output goes to the Inactive state.
0
Stop counter at the end of the period. Output goes to the Inactive state.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 548
PIC18F27/47/57Q84
PWM - Pulse-Width Modulator with Compare
31.9.10 PWMxSaCFG
Name:
PWMxSaCFG
PWM Slice “a” Configuration Register(1)
Bit
Access
Reset
7
POL2
R/W
0
6
POL1
R/W
0
5
4
3
PPEN
R/W
0
2
R/W
0
1
MODE[2:0]
R/W
0
0
R/W
0
Bit 7 – POL2 PWM Slice “a” Parameter 2 Output Polarity
Value
Description
1
PWMx_SaP2_out is low true
0
PWMx_SaP2_out is high true
Bit 6 – POL1 PWM Slice “a” Parameter 1 Output Polarity
Value
Description
1
PWMx_SaP1_out is low true
0
PWMx_SaP1_out is high true
Bit 3 – PPEN Push-Pull Mode Enable
Each period the output alternates between PWMx_SaP1_out and PWMx_SaP2_out. Only Left and Right-Aligned
modes are supported. Other modes may exhibit unexpected results.
Value
Description
1
PWMx Slice “a” Push-Pull mode is enabled
0
PWMx Slice “a” Push-Pull mode is not enabled
Bits 2:0 – MODE[2:0] PWM Module Slice “a” Operating Mode Select
Selects operating mode for both PWMx_SaP1_out and PWMx_SaP2_out
Value
Description
11x
Reserved. Outputs go to Reset state.
101
Compare mode: Toggle PWMx_SaP1_out and PWMx_SaP2_out on PWM timer match with
corresponding parameter register
100
Compare mode: Set PWMx_SaP1_out and PWMx_SaP2_out high on PWM timer match with
corresponding parameter register
011
Variable Aligned mode
010
Center Aligned mode
001
Right Aligned mode
000
Left Aligned mode
Note:
1. Changes to this register must be done only when the EN bit is cleared.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 549
PIC18F27/47/57Q84
PWM - Pulse-Width Modulator with Compare
31.9.11 PWMxSaP1
Name:
PWMxSaP1
PWM Slice “a” Parameter 1 Register
Determines the active period of slice “a”, parameter 1 output
Bit
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
P1[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
P1[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – P1[15:0] Parameter 1 Value
Value
MODE
Description
n
Compare
Compare match event occurs when PWMx timer = n (Refer to MODE selections)
n
Variable aligned PWMx_SaP1_out and PWMx_SaP2 both go high when PWMx timer = n
n
Center-aligned PWMx_SaP1_out is high 2*n PWMx clock periods centered around PWMx period
event
n
Right-aligned
PWMx_SaP1_out is high n PWMx clock periods at end of PWMx period
n
Left-aligned
PWMx_SaP1_out is high n PWMx clock periods at beginning of PWMx period
Notes: The individual bytes in this multibyte register can be accessed with the following register names:
• PWMxSaP1H: Accesses the high byte P1[15:8]
• PWMxSaP1L: Accesses the low byte P1[7:0]
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 550
PIC18F27/47/57Q84
PWM - Pulse-Width Modulator with Compare
31.9.12 PWMxSaP2
Name:
PWMxSaP2
PWM Slice “a” Parameter 2 Register
Determines the active period of slice “a”, parameter 2 output
Bit
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
P2[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
P2[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – P2[15:0] Parameter 2 Value
Value
MODE
Description
n
Compare
Compare match event occurs when PWMx timer = n (Refer to MODE selections)
n
Variable-aligned PWMx_SaP1_out and PWMx_SaP2 both go low when PWMx timer = n
n
Center-aligned PWMx_SaP2_out is high 2*n PWMx clock periods centered around PWMx period
event
n
Right-aligned
PWMx_SaP2_out is high n PWMx clock periods at end of PWMx period
n
Left-aligned
PWMx_SaP2_out is high n PWMx clock periods at beginning of PWMx period
Notes: The individual bytes in this multibyte register can be accessed with the following register names:
• PWMxSaP2H: Accesses the high byte P2[15:8]
• PWMxSaP2L: Accesses the low byte P2[7:0]
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 551
PIC18F27/47/57Q84
PWM - Pulse-Width Modulator with Compare
31.9.13 PWMLOAD
Name:
Address:
PWMLOAD
0x49C
Mirror copies of all PWMxLD bits
Bit
7
6
Access
Reset
5
4
3
MPWM4LD
R/W
0
2
MPWM3LD
R/W
0
1
MPWM2LD
R/W
0
0
MPWM1LD
R/W
0
Bits 0, 1, 2, 3 – MPWMxLD Mirror copy of PWMxLD bit
Mirror copies of all PWMxLD bits can be set simultaneously to synchronize the load event across all PWMs
Value
Description
1
PWMx parameter and period values will be transferred to their buffer registers at the next period Reset
event
0
There are no PWMx period and parameter value transfers pending
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 552
PIC18F27/47/57Q84
PWM - Pulse-Width Modulator with Compare
31.9.14 PWMEN
Name:
Address:
PWMEN
0x49D
Mirror copies of all PWMxEN bits
Bit
7
6
Access
Reset
5
4
3
MPWM4EN
R/W
0
2
MPWM3EN
R/W
0
1
MPWM2EN
R/W
0
0
MPWM1EN
R/W
0
Bits 0, 1, 2, 3 – MPWMxEN Mirror copy of PWMxEN bit
Mirror copies of all PWMxEN bits can be set simultaneously to synchronize the enable event across all PWMs
Value
Description
1
PWMx is enabled
0
PWMx is not enabled
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 553
PIC18F27/47/57Q84
PWM - Pulse-Width Modulator with Compare
31.10
Address
Register Summary - PWM
Name
0x00
...
0x045F
0x0460
0x0461
0x0462
PWM1ERS
PWM1CLK
PWM1LDS
0x0463
PWM1PR
0x0465
0x0466
0x0467
0x0468
0x0469
0x046A
PWM1CPRE
PWM1PIPOS
PWM1GIR
PWM1GIE
PWM1CON
PWM1S1CFG
0x046B
PWM1S1P1
0x046D
PWM1S1P2
0x046F
0x0470
0x0471
PWM2ERS
PWM2CLK
PWM2LDS
0x0472
PWM2PR
0x0474
0x0475
0x0476
0x0477
0x0478
0x0479
PWM2CPRE
PWM2PIPOS
PWM2GIR
PWM2GIE
PWM2CON
PWM2S1CFG
0x047A
PWM2S1P1
0x047C
PWM2S1P2
0x047E
0x047F
0x0480
PWM3ERS
PWM3CLK
PWM3LDS
0x0481
PWM3PR
0x0483
0x0484
0x0485
0x0486
0x0487
0x0488
PWM3CPRE
PWM3PIPOS
PWM3GIR
PWM3GIE
PWM3CON
PWM3S1CFG
0x0489
PWM3S1P1
0x048B
PWM3S1P2
0x048D
0x048E
0x048F
PWM4ERS
PWM4CLK
PWM4LDS
0x0490
PWM4PR
0x0492
0x0493
0x0494
PWM4CPRE
PWM4PIPOS
PWM4GIR
Bit Pos.
7
6
5
4
3
2
1
0
S1P2
S1P2
ERSPOL
MODE[2:0]
S1P1
S1P1
ERSNOW
S1P2
S1P2
ERSPOL
MODE[2:0]
S1P1
S1P1
ERSNOW
S1P2
S1P2
ERSPOL
MODE[2:0]
S1P1
S1P1
ERSNOW
S1P2
S1P1
Reserved
7:0
7:0
7:0
7:0
15:8
7:0
7:0
7:0
7:0
7:0
7:0
7:0
15:8
7:0
15:8
7:0
7:0
7:0
7:0
15:8
7:0
7:0
7:0
7:0
7:0
7:0
7:0
15:8
7:0
15:8
7:0
7:0
7:0
7:0
15:8
7:0
7:0
7:0
7:0
7:0
7:0
7:0
15:8
7:0
15:8
7:0
7:0
7:0
7:0
15:8
7:0
7:0
7:0
ERS[4:0]
CLK[4:0]
LDS[4:0]
PR[7:0]
PR[15:8]
CPRE[7:0]
PIPOS[7:0]
EN
POL2
LD
POL1
PPEN
P1[7:0]
P1[15:8]
P2[7:0]
P2[15:8]
ERS[4:0]
CLK[4:0]
LDS[4:0]
PR[7:0]
PR[15:8]
CPRE[7:0]
PIPOS[7:0]
EN
POL2
LD
POL1
PPEN
P1[7:0]
P1[15:8]
P2[7:0]
P2[15:8]
ERS[4:0]
CLK[4:0]
LDS[4:0]
PR[7:0]
PR[15:8]
CPRE[7:0]
PIPOS[7:0]
EN
POL2
© 2021 Microchip Technology Inc.
LD
POL1
PPEN
P1[7:0]
P1[15:8]
P2[7:0]
P2[15:8]
ERS[4:0]
CLK[4:0]
LDS[4:0]
PR[7:0]
PR[15:8]
CPRE[7:0]
PIPOS[7:0]
Preliminary Datasheet
DS40002213D-page 554
PIC18F27/47/57Q84
PWM - Pulse-Width Modulator with Compare
...........continued
Address
Name
Bit Pos.
0x0495
0x0496
0x0497
PWM4GIE
PWM4CON
PWM4S1CFG
0x0498
PWM4S1P1
0x049A
PWM4S1P2
0x049C
0x049D
PWMLOAD
PWMEN
7:0
7:0
7:0
7:0
15:8
7:0
15:8
7:0
7:0
7
EN
POL2
© 2021 Microchip Technology Inc.
6
POL1
5
4
3
PPEN
P1[7:0]
P1[15:8]
P2[7:0]
P2[15:8]
MPWM4LD
MPWM4EN
Preliminary Datasheet
2
1
0
LD
S1P2
ERSPOL
MODE[2:0]
S1P1
ERSNOW
MPWM3LD
MPWM3EN
MPWM2LD
MPWM2EN
MPWM1LD
MPWM1EN
DS40002213D-page 555
PIC18F27/47/57Q84
CWG - Complementary Waveform Generator Mod...
32.
CWG - Complementary Waveform Generator Module
The Complementary Waveform Generator (CWG) produces half-bridge, full-bridge, and steering of PWM waveforms.
It is backwards compatible with previous CCP functions.
The CWG has the following features:
•
•
•
•
•
32.1
Six Operating modes:
– Synchronous Steering mode
– Asynchronous Steering mode
– Full-Bridge mode, Forward
– Full-Bridge mode, Reverse
– Half-Bridge mode
– Push-Pull mode
Output Polarity Control
Output Steering
Independent 6-bit Rising and Falling Event Dead-Band Timers:
– Clocked dead band
– Independent rising and falling dead-band enables
Auto-Shutdown Control With:
– Selectable shutdown sources
– Auto-restart option
– Auto-shutdown pin override control
Fundamental Operation
The CWG generates two output waveforms from the selected input source.
The off-to-on transition of each output can be delayed from the on-to-off transition of the other output, thereby
creating a time delay immediately where neither output is driven. This is referred to as dead time and is covered in
the Dead-Band Control section.
It may be necessary to guard against the possibility of circuit faults or a feedback event arriving too late or not at all.
In this case, the active drive must be terminated before the Fault condition causes damage. This is referred to as
auto-shutdown and is covered in the Auto-Shutdown section.
32.2
Operating Modes
The CWG module can operate in six different modes, as specified by the MODE bits:
•
•
•
•
•
•
Half-Bridge mode
Push-Pull mode
Asynchronous Steering mode
Synchronous Steering mode
Full-Bridge mode, Forward
Full-Bridge mode, Reverse
All modes accept a single pulse input, and provide up to four outputs as described in the following sections.
All modes include auto-shutdown control as described in Auto-Shutdown section.
Important: Except as noted for Full-Bridge mode, mode changes must only be performed while EN = 0.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 556
PIC18F27/47/57Q84
CWG - Complementary Waveform Generator Mod...
32.2.1
Half-Bridge Mode
In Half-Bridge mode, two output signals are generated as true and inverted versions of the input as illustrated in
Figure 32-1. A non-overlap (dead-band) time is inserted between the two outputs to prevent shoot-through current in
various power supply applications. Dead-band control is described in Dead-Band Control section. The output steering
feature cannot be used in this mode. A basic block diagram of this mode is shown in Figure 32-2.
The unused outputs CWGxC and CWGxD drive similar signals as CWGxA and CWGxB, with polarity independently
controlled by the POLC and POLD bits, respectively.
Figure 32-1. CWG Half-Bridge Mode Operation
Rev. 30-000097A
4/14/2017
CWGx_clock
CWGxA
CWGxC
Rising event dead band
Rising event dead band
Falling event dead band
Falling event dead band
CWGxB
CWGxD
CWGx_data
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 557
PIC18F27/47/57Q84
CWG - Complementary Waveform Generator Mod...
Figure 32-2. Simplified CWG Block Diagram (Half-Bridge Mode, MODE = 'b100)
LSAC
1
0
High-Z
clock
data out
CWG Data
11
10
01
00
Rising Dead-Band Block
CWG Clock
Re v. 10 -00 02 09 D
1/29 /20 19
1
CWG Data A
data in
0
POLA
CWGxA
LSBD
1
11
0
10
High-Z
01
Falling Dead-Band Block
clock
data out
CWG Data B
data in
00
1
CWG
Data
CWG Data Input
0
POLB
D
CWGxB
Q
E
LSAC
EN
1
11
0
10
High-Z
01
00
1
0 CWGxC
POLC
Auto-shutdown source
(CWGxAS1 register)
S
Q
LSBD
R
REN
SHUTDO WN = 0
1
11
0
10
High-Z
01
00
1
0 CWG1D
POLD
SHUTDO WN
FREEZE
D
Q
CWG Data
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 558
PIC18F27/47/57Q84
CWG - Complementary Waveform Generator Mod...
32.2.2
Push-Pull Mode
In Push-Pull mode, two output signals are generated, alternating copies of the input as illustrated in Figure 32-3. This
alternation creates the Push-Pull effect required for driving some transformer-based power supply designs. Steering
modes are not used in Push-Pull mode. A basic block diagram for the Push-Pull mode is shown in Figure 32-4.
The Push-Pull sequencer is reset whenever EN = 0 or if an auto-shutdown event occurs. The sequencer is clocked
by the first input pulse, and the first output appears on CWGxA.
The unused outputs CWGxC and CWGxD drive copies of CWGxA and CWGxB, respectively, but with polarity
controlled by the POLC and POLD bits, respectively.
Figure 32-3. CWG Push-Pull Mode Operation
Rev. 30-000098A
4/14/2017
CWGx clock
CWG Data Input
CWGxA
CWGxB
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 559
PIC18F27/47/57Q84
CWG - Complementary Waveform Generator Mod...
Figure 32-4. Simplified CWG Block Diagram (Push-Pull Mode, MODE = 'b101)
LSAC
Re v. 10 -00 02 10 D
1/29 /20 19
1
11
0
10
High-Z
01
00
CWG Data
1
CWG Data A
0 CWGxA
POLA
D
LSBD
Q
Q
1
11
0
10
High-Z
01
00
CWG Data B
1
CWG Data Input
CWG
Data
D
0 CWGxB
POLB
Q
LSAC
E
1
11
0
10
High-Z
01
EN
00
1
0 CWGxC
POLC
Auto-shutdown source
(CWGxAS1 register)
S
Q
LSBD
R
1
11
0
10
High-Z
01
REN
SHUTDO WN = 0
00
1
0 CWGxD
POLD
SHUTDO WN
FREEZE
D
Q
CWG Data
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 560
PIC18F27/47/57Q84
CWG - Complementary Waveform Generator Mod...
32.2.3
Full-Bridge Mode
In Forward and Reverse Full-Bridge modes, three outputs drive static values while the fourth is modulated by the
input data signal. The mode selection may be toggled between forward and reverse by toggling the MODE[0] bit
of the CWGxCON0 while keeping the MODE[2:1] bits static, without disabling the CWG module. When connected,
as shown in Figure 32-5, the outputs are appropriate for a full-bridge motor driver. Each CWG output signal has
independent polarity control, so the circuit can be adapted to high-active and low-active drivers. A simplified block
diagram for the Full-Bridge modes is shown in Figure 32-6.
Figure 32-5. Example of Full-Bridge Application
Re v. 10 -00 02 63 A
2/8/20 19
VDD
FET
Driver
QA
QC
FET
Driver
CWG1A
LOAD
CWG1B
CWG1C
CWG1D
© 2021 Microchip Technology Inc.
FET
Driver
FET
Driver
QB
Preliminary Datasheet
QD
DS40002213D-page 561
PIC18F27/47/57Q84
CWG - Complementary Waveform Generator Mod...
Figure 32-6. Simplified CWG Block Diagram (Forward and Reverse Full-Bridge Modes)
Re v. 10 -00 02 12 D
2/7/20 19
MODE = 'b010: Forward
LSAC
MODE = 'b011: Reverse
Rising Dead-Band Block
CWG Clock
clock
signal out
signal in
1
11
0
10
High-Z
01
00
CWG
Data
1
CWG Data A
0
POLA
MODE[0]
CWG
Data
D
CWGA
Q
Q
LSBD
cwg data
signal in
signal out
clock
CWG Clock
1
11
0
10
High-Z
01
00
Falling Dead-Band Block
CWG Data Input
CWG Data
1
CWG Data B
0 CWGxB
POLB
D
Q
LSAC
E
EN
1
11
0
10
High-Z
01
00
1
CWG Data C
0 CWGxC
POLC
Auto-shutdown source
(CWGxAS1 register)
S
Q
LSBD
R
REN
SHUTDO WN = 0
1
11
0
10
High-Z
01
00
1
CWG Data D
0 CWGxD
POLD
SHUTDO WN
FREEZE
D
Q
CWG Data
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 562
PIC18F27/47/57Q84
CWG - Complementary Waveform Generator Mod...
In Forward Full-Bridge mode (MODE = 'b010), CWGxA is driven to its Active state, CWGxB and CWGxC are driven
to their Inactive state, and CWGxD is modulated by the input signal, as shown in Figure 32-7.
In Reverse Full-Bridge mode (MODE = 'b011), CWGxC is driven to its Active state, CWGxA and CWGxD are driven
to their Inactive states, and CWGxB is modulated by the input signal, as shown in Figure 32-7.
In Full-Bridge mode, the dead-band period is used when there is a switch from forward to reverse or vice versa.
This dead-band control is described in the Dead-Band Control section, with additional details in the Rising Edge and
Reverse Dead Band and Falling Edge and Forward Dead Band sections. Steering modes are not used with either of
the Full-Bridge modes.
Figure 32-7. Example of Full-Bridge Output
Rev. 30-000099A
4/14/2017
Forward
Mode
Period
CWGxA (2)
CWGxB (2)
CWGxC (2)
Pulse Width
CWGxD (2)
(1)
Reverse
Mode
(1)
Period
CWGxA (2)
Pulse Width
CWGxB (2)
CWGxC (2)
CWGxD (2)
(1)
(1)
Notes:
1. A rising CWG data input creates a rising event on the modulated output.
2. Output signals shown as active-high; all POLy bits are clear.
32.2.3.1 Direction Change in Full-Bridge Mode
In Full-Bridge mode, changing the MODE[0] bit controls the forward/reverse direction. Direction changes occur on the
next rising edge of the modulated input.
The sequence, described as follows, is illustrated in Figure 32-8.
1.
2.
The associated active output CWGxA and the inactive output CWGxC are switched to drive in the opposite
direction.
The previously modulated output CWGxD is switched to the Inactive state, and the previously inactive output
CWGxB begins to modulate.
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3.
CWG modulation resumes after the direction-switch dead band has elapsed.
Figure 32-8. Example of PWM Direction Change at Near 100% Duty Cycle
Rev. 30-000100A
4/14/2017
Forward Period
t1
Reverse Period
CWGxA
Pulse Width
CWGxB
CWGxC
CWGxD
Pulse Width
TON
External Switch C
TOFF
External Switch D
Potential ShootThrough Current
T = TOFF - TON
32.2.3.2 Dead-Band Delay in Full-Bridge Mode
Dead-band delay is important when either of the following conditions is true:
•
•
The direction of the CWG output changes when the duty cycle of the data input is at or near 100%.
The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on
time.
The dead-band delay is inserted only when changing directions, and only the modulated output is affected.
The statically-configured outputs (CWGxA and CWGxC) are not afforded dead-band, and switch essentially
simultaneously.
Figure 32-8 shows an example of the CWG outputs changing directions from forward to reverse, at near 100% duty
cycle. In this example, at time t1, the output of CWGxA and CWGxD becomes inactive, while the output of CWGxC
becomes active. Since the turn-off time of the power devices is longer than the turn-on time, a shoot-through current
will flow through the power devices QC and QD for the duration of ‘T’. The same phenomenon will occur to power
devices QA and QB for the CWG direction change from reverse to forward.
When changing the CWG direction at high duty cycle is required for an application, two possible solutions for
eliminating the shoot-through current are:
1.
2.
32.2.4
Reduce the CWG duty cycle for one period before changing directions.
Use switch drivers that can drive the switches off faster than they can drive them on.
Steering Modes
In both Synchronous and Asynchronous Steering modes, the CWG Data can be steered to any combination of four
CWG outputs. A fixed value will be presented on all the outputs not used for the PWM output. Each output has
independent polarity, steering, and shutdown options. Dead-band control is not used in either Steering mode.
For example, when STRA = 0 then the corresponding pin is held at the level defined by OVRA. When STRA = 1,
then the pin is driven by the CWG Data signal.
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The POLy bits control the signal polarity only when STRy = 1.
The CWG auto-shutdown operation also applies in Steering modes as described in Auto-Shutdown. An autoshutdown event will only affect pins that have STRy = 1.
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Figure 32-9. Simplified CWG Block Diagram (Output Steering Modes)
LSAC
MODE = 'b000: Asynchronous
Re v. 10 -00 02 11 D
2/7/20 19
MODE = 'b001: Synchronous
1
11
0
10
High-Z
01
00
CWG Data A
1
1
POLA
0 CWGxA
0
OVRA
STRA
CWG
Data
CWG Data
Input
LSBD
1
11
0
10
High-Z
01
00
D
CWG Data B
Q
E
1
1
POLB
0 CWGxB
0
OVRB
EN
STRB
LSAC
1
11
0
10
High-Z
01
00
CWG Data C
Auto-shutdown source
(CWGxAS1 register)
S
Q
1
1
POLC
0 CWGxC
0
R
OVRC
STRC
REN
LSBD
SHUTDO WN = 0
1
11
0
10
High-Z
01
00
CWG Data D
1
POLD
0
1
0 CWGxD
OVRD
SHUTDO WN
STRD
FREEZE
D
Q
CWG Data
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32.2.4.1 Synchronous Steering Mode
In Synchronous Steering mode (MODE ='b001), the changes to steering selection registers take effect on the next
rising edge of CWG Data (see figure below). In Synchronous Steering mode, the output will always produce a
complete waveform.
Important: Only the STRx bits are synchronized; the OVRx bits are not synchronized.
Figure 32-10. Example of Synchronous Steering (MODE = 'b001)
Rev. 30-000101A
4/14/2017
CWGx clock
CWG Data
CWGxA
CWGxB
32.2.4.2 Asynchronous Steering Mode
In Asynchronous mode (MODE = 'b000), steering takes effect at the end of the instruction cycle that writes to STRx.
In Asynchronous Steering mode, the output signal may be an incomplete waveform (see figure below). This operation
may be useful when the user firmware needs to immediately remove a signal from the output pin.
Figure 32-11. Example of Asynchronous Steering (MODE = 'b000)
Rev. 30-000102A
4/14/2017
CWG Data
End of Instruction Cycle
End of Instruction Cycle
STRA
CWGxA
CWG1A Follows CWG1 data input
32.2.4.3 Start-up Considerations
The application hardware must use the proper external pull-up and/or pull-down resistors on the CWG output pins.
This is required because all I/O pins are forced to high-impedance at Reset.
The Polarity Control bits (POLy) allow the user to choose whether the output signals are active-high or active-low.
32.3
Clock Source
The clock source is used to drive the dead-band timing circuits. The CWG module allows the following clock sources
to be selected:
•
•
FOSC (system clock)
HFINTOSC
When the HFINTOSC is selected, the HFINTOSC will be kept running during Sleep. Therefore, the CWG modes
requiring dead-band can operate in Sleep, provided that the CWG data input is also active during Sleep. The clock
sources are selected using the CS bit. The system clock FOSC is disabled in Sleep and thus dead-band control
cannot be used.
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32.4
Selectable Input Sources
The CWG generates the output waveforms from the input sources which are selected with the ISM bits. Refer to the
CWGxISM register for more details.
32.5
32.5.1
Output Control
CWG Output
Each CWG output can be routed to a Peripheral Pin Select (PPS) output via the RxyPPS register. Refer to the “PPS
- Peripheral Pin Select Module” chapter for more details.
32.5.2
Polarity Control
The polarity of each CWG output can be selected independently. When the output polarity bit is set, the
corresponding output is active-high. Clearing the output polarity bit configures the corresponding output as active-low.
However, polarity does not affect the override levels. Output polarity is selected with the POLy bits. Auto-shutdown
and steering options are unaffected by polarity.
32.6
Dead-Band Control
The dead-band control provides non-overlapping complementary outputs to prevent shoot-through current when the
outputs switch. Dead-band operation is employed for Half-Bridge and Full-Bridge modes. The CWG contains two
6-bit dead-band counters. One is used for the rising edge of the input source control in Half-Bridge mode or for
reverse direction change dead band in Full-Bridge mode. The other is used for the falling edge of the input source
control in Half-Bridge mode or for forward direction change dead band in Full-Bridge mode.
Dead band is timed by counting CWG clock periods from zero up to the value in the rising or falling dead-band
counter registers.
32.6.1
Dead-Band Functionality In Half-Bridge Mode
In Half-Bridge mode, the dead-band counters dictate the delay between the falling edge of the normal output and the
rising edge of the inverted output. This can be seen in Figure 32-1.
32.6.2
Dead-Band Functionality In Full-Bridge Mode
In Full-Bridge mode, the dead-band counters are used when undergoing a direction change. The MODE[0] bit can
be set or cleared while the CWG is running, allowing for changes from Forward to Reverse mode. The CWGxA
and CWGxC signals will change immediately upon the first rising input edge following a direction change, but the
modulated signals (CWGxB or CWGxD, depending on the direction of the change) will experience a delay dictated by
the dead-band counters.
32.7
Rising Edge and Reverse Dead-Band
In Half-Bridge mode, the rising edge dead-band delays the turn-on of the CWGxA output after the rising edge of the
CWG data input. In Full-Bridge mode, the reverse dead-band delay is only inserted when changing directions from
Forward mode to Reverse mode, and only the modulated output, CWGxB, is affected.
The CWGxDBR register determines the duration of the dead-band interval on the rising edge of the input source
signal. This duration is from 0 to 64 periods of the CWG clock. The following figure illustrates different dead-band
delays for rising and falling CWG Data events.
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Figure 32-12. Dead-Band Operation, CWGxDBR = 0x01, CWGxDBF = 0x02
Rev. 30-000103A
4/14/2017
cwg_clock
CWG Data
CWGxA
CWGxB
Dead band is always initiated on the edge of the input source signal. A count of zero indicates that no dead band is
present.
If the input source signal reverses polarity before the dead-band count is completed, then no signal will be seen on
the respective output.
The CWGxDBR register value is double-buffered. When EN = 0, the buffer is loaded when CWGxDBR is written.
When EN = 1, then the buffer will be loaded at the rising edge following the first falling edge of the CWG Data, after
the LD bit is set.
32.8
Falling Edge and Forward Dead Band
In Half-Bridge mode, the falling edge dead band delays the turn-on of the CWGxB output at the falling edge of the
CWG data input. In Full-Bridge mode, the forward dead-band delay is only inserted when changing directions from
Reverse mode to Forward mode, and only the modulated output CWGxD is affected.
The CWGxDBF register determines the duration of the dead-band interval on the falling edge of the input source
signal. This duration is from zero to 64 periods of CWG clock.
Dead-band delay is always initiated on the edge of the input source signal. A count of zero indicates that no dead
band is present.
If the input source signal reverses polarity before the dead-band count is completed, then no signal will be seen on
the respective output.
Figure 32-13. Dead-Band Operation, CWGxDBR = 0x03, CWGxDBF = 0x06, Source Shorter Than Dead Band
Rev. 30-000104A
4/14/2017
cwg_clock
CWG Data
CWGxA
CWGxB
source shorter than dead band
The CWGxDBF register value is double-buffered. When EN = 0, the buffer is loaded when CWGxDBF is written.
When EN = 1, then the buffer will be loaded at the rising edge following the first falling edge of the data input after the
LD is set.
32.9
Dead-Band Jitter
When the rising and falling edges of the input source are asynchronous to the CWG clock, it creates jitter in the
dead-band time delay. The maximum jitter is equal to one CWG clock period. Refer to the equations below for more
details.
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Equation 32-1. Dead-Band Delay Time Calculation
1
TDEAD − BAND_MIN =
• DBx
FCWG_CLOCK
TDEAD − BAND_MAX =
1
• DBx + 1
FCWG_CLOCK
T JITTER = TDEAD − BAND_MAX − TDEAD − BAND_MIN
T JITTER =
1
FCWG_CLOCK
TDEAD − BAND_MAX = TDEAD − BAND_MIN + T JITTER
Dead-Band Delay Example Calculation
DBx = 0x0A = 10
FCWG_CLOCK = 8 MHz
1
T JITTER =
= 125ns
8 MHz
TDEAD − BAND_MIN = 125ns • 10 = 1.25μs
TDEAD − BAND_MAX = 1.25μs + 0.125 μs = 1.37μs
32.10
Auto-Shutdown
Auto-shutdown is a method to immediately override the CWG output levels with specific overrides that allow for safe
shutdown of the circuit. The Shutdown state can be either cleared automatically or held until cleared by software. The
auto-shutdown circuit is illustrated in the following figure.
Figure 32-14. CWG Shutdown Block Diagram
Write 1 to
SHUTDOWN bit
Re v. 10 -00 01 72 F
2/8/20 19
Auto-shutdown source
(CWGxAS1 register)
S
Q
SHUTDOWN
S
D
FREEZE
REN
Write 0 to
SHUTDOWN bit
Q
CWG_shutdown
R
CWG_data
CK
32.10.1 Shutdown
The Shutdown state can be entered by either of the following two methods:
•
•
Software Generated
External Input
32.10.2 Software Generated Shutdown
Setting the SHUTDOWN bit will force the CWG into the Shutdown state.
When the auto-restart is disabled, the Shutdown state will persist as long as the SHUTDOWN bit is set.
When auto-restart is enabled, the SHUTDOWN bit will clear automatically and resume operation on the next rising
edge event. The SHUTDOWN bit indicates when a Shutdown condition exists. The bit may be set or cleared in
software or by hardware.
32.10.3 External Input Source
External shutdown inputs provide the fastest way to safely suspend CWG operation in the event of a Fault condition.
When any of the selected shutdown inputs goes active, the CWG outputs will immediately go to the selected override
levels without software delay. The override levels are selected by the LSBD and LSAC bits. Several input sources
can be selected to cause a Shutdown condition. All input sources are active-low. The shutdown input sources are
individually enabled by the ASyE bits.
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Important: Shutdown inputs are level sensitive, not edge sensitive. The Shutdown state cannot be
cleared, except by disabling auto-shutdown, as long as the shutdown input level persists.
32.10.4 Pin Override Levels
The levels driven to the CWG outputs during an auto-shutdown event are controlled by the LSBD and LSAC bits. The
LSBD bits control CWGxB/D output levels, while the LSAC bits control the CWGxA/C output levels.
32.10.5 Auto-Shutdown Interrupts
When an auto-shutdown event occurs, either by software or hardware setting SHUTDOWN, the CWGxIF flag bit of
the PIRx register is set.
32.11
Auto-Shutdown Restart
After an auto-shutdown event has occurred, there are two ways to resume operation:
•
•
Software controlled
Auto-restart
In either case, the shutdown source must be cleared before the restart can take place. That is, either the Shutdown
condition must be removed, or the corresponding ASyE bit must be cleared.
32.11.1 Software-Controlled Restart
When the REN bit is clear (REN = 0), the CWG module must be restarted after an auto-shutdown event through
software.
Once all auto-shutdown sources are removed, the software must clear the SHUTDOWN bit. Once SHUTDOWN is
cleared, the CWG module will resume operation upon the first rising edge of the CWG data input.
Important: The SHUTDOWN bit cannot be cleared in software if the Auto-shutdown condition is still
present.
Figure 32-15. Shutdown Functionality, Auto-Restart Disabled (REN = 0, LSAC = ‘b01, LSBD = ‘b01)
Rev. 30-000105A
4/14/2017
Shutdown Event Ceases
REN Cleared by Software
CWG Input
Shutdown Source
SHUTDOWN
CWGxA
CWGxC
Tri-State (No Pulse)
CWGxB
CWGxD
Tri-State (No Pulse)
No Shutdown
Shutdown
Output Resumes
32.11.2 Auto-Restart
When the REN bit is set (REN = 1), the CWG module will restart from the Shutdown state automatically.
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Once all auto-shutdown conditions are removed, the hardware will automatically clear the SHUTDOWN bit. Once
SHUTDOWN is cleared, the CWG module will resume operation upon the first rising edge of the CWG data input.
Important: The SHUTDOWN bit cannot be cleared in software if the Auto-shutdown condition is still
present.
Figure 32-16. Shutdown Functionality, Auto-Restart Enabled (REN = 1, LSAC = ‘b01, LSBD = ‘b01)
Rev. 30-000106A
4/14/2017
Shutdown Event Ceases
REN auto-cleared by hardware
CWG Input
Shutdown Source
SHUTDOWN
CWGxA
CWGxC
Tri-State (No Pulse)
CWGxB
CWGxD
Tri-State (No Pulse)
No Shutdown
Shutdown
32.12
Output Resumes
Operation During Sleep
The CWG module operates independently from the system clock and will continue to run during Sleep, provided that
the clock and input sources selected remain active.
The HFINTOSC remains active during Sleep when all the following conditions are met:
•
•
•
CWG module is enabled
Input source is active
HFINTOSC is selected as the clock source, regardless of the system clock source selected.
In other words, if the HFINTOSC is simultaneously selected as the system clock and the CWG clock source, when
the CWG is enabled and the input source is active, then the CPU will go Idle during Sleep, but the HFINTOSC will
remain active and the CWG will continue to operate. This will have a direct effect on the Sleep mode current.
32.13
Configuring the CWG
1.
Ensure that the TRIS control bits corresponding to CWG outputs are set so that all are configured as inputs,
ensuring that the outputs are inactive during setup. External hardware must ensure that pin levels are held to
safe levels.
2. Clear the EN bit, if not already cleared.
3. Configure the MODE bits to set the output operating mode.
4. Configure the POLy bits to set the output polarities.
5. Configure the ISM bits to select the data input source.
6. If a steering mode is selected, configure the STRy bits to select the desired output on the CWG outputs.
7. Configure the LSBD and LSAC bits to select the auto-shutdown output override states (this is necessary even
if not using auto-shutdown because start-up will be from a Shutdown state).
8. If auto-restart is desired, set the REN bit.
9. If auto-shutdown is desired, configure the ASyE bits to select the shutdown source.
10. Set the desired rising and falling dead-band times with the CWGxDBR and CWGxDBF registers.
11. Select the clock source with the CS bit.
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12. Set the EN bit to enable the module.
13. Clear the TRIS bits that correspond to the CWG outputs to set them as outputs.
If auto-restart is to be used, set the REN bit and the SHUTDOWN bit will be cleared automatically. Otherwise, clear
the SHUTDOWN bit in software to start the CWG.
32.14
Register Definitions: CWG Control
Long bit name prefixes for the CWG peripherals are shown in the table below. Refer to the “Long Bit Names”
section in the “Register and Bit Naming Conventions” chapter for more information.
Table 32-1. CWG Long Bit Name Prefixes
Peripheral
Bit Name Prefix
CWG1
CWG1
CWG2
CWG2
CWG3
CWG3
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32.14.1 CWGxCON0
Name:
Address:
CWGxCON0
0x3C0,0x3C9,0x3D2
CWG Control Register 0
Bit
Access
Reset
7
EN
R/W
0
6
LD
R/W/HC
0
5
4
3
2
R/W
0
1
MODE[2:0]
R/W
0
0
R/W
0
Bit 7 – EN CWG Enable
Value
Description
1
Module is enabled
0
Module is disabled
Bit 6 – LD CWG1 Load Buffers(1)
Value
Description
1
Dead-band count buffers to be loaded on CWG data rising edge, following first falling edge after this bit
is set
0
Buffers remain unchanged
Bits 2:0 – MODE[2:0] CWG Mode
Value
Description
111
Reserved
110
Reserved
101
CWG outputs operate in Push-Pull mode
100
CWG outputs operate in Half-Bridge mode
011
CWG outputs operate in Reverse Full-Bridge mode
010
CWG outputs operate in Forward Full-Bridge mode
001
CWG outputs operate in Synchronous Steering mode
000
CWG outputs operate in Asynchronous Steering mode
Note:
1. This bit can only be set after EN = 1; it cannot be set in the same cycle when EN is set.
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32.14.2 CWGxCON1
Name:
Address:
CWGxCON1
0x3C1,0x3CA,0x3D3
CWG Control Register 1
Bit
7
6
Access
Reset
5
IN
R
x
4
3
POLD
R/W
0
2
POLC
R/W
0
1
POLB
R/W
0
0
POLA
R/W
0
Bit 5 – IN CWG Input Value (read-only)
Value
Description
1
CWG data input is a logic 1
0
CWG data input is a logic 0
Bits 0, 1, 2, 3 – POLy CWG Output ‘y’ Polarity
Value
Description
1
Signal output is inverted polarity
0
Signal output is normal polarity
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32.14.3 CWGxCLK
Name:
Address:
CWGxCLK
0x3BC,0x3C5,0x3CE
CWG Clock Input Selection Register
Bit
7
6
5
4
3
Access
Reset
2
1
0
CS
R/W
0
Bit 0 – CS CWG Clock Source Selection Select
Value
Description
1
HFINTOSC (remains operating during Sleep)
0
FOSC
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32.14.4 CWGxISM
Name:
Address:
CWGxISM
0x3BD,0x3C6,0x3CF
CWGx Input Selection Register
Bit
7
6
5
Access
Reset
4
3
R/W
0
R/W
0
2
ISM[4:0]
R/W
0
1
0
R/W
0
R/W
0
Bits 4:0 – ISM[4:0] CWG Data Input Source Select
ISM
11111-11010
11001
11000
10111
10110
10101
10100
10011
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
CWG1
Pin selected by CWG1PPS
© 2021 Microchip Technology Inc.
Input Selection
CWG2
Reserved
CLC8_OUT
CLC7_OUT
CLC6_OUT
CLC5_OUT
CLC4_OUT
CLC3_OUT
CLC2_OUT
CLC1_OUT
DSM1_OUT
CMP2_OUT
CMP1_OUT
NCO3_OUT
NCO2_OUT
NCO1_OUT
PWM4S1P2_OUT
PWM4S1P1_OUT
PWM3S1P2_OUT
PWM3S1P1_OUT
PWM2S1P2_OUT
PWM2S1P1_OUT
PWM1S1P2_OUT
PWM1S1P1_OUT
CCP3_OUT
CCP2_OUT
CCP1_OUT
Pin selected by CWG2PPS
Preliminary Datasheet
CWG3
Pin selected by CWG3PPS
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32.14.5 CWGxSTR
Name:
Address:
CWGxSTR
0x3C4,0x3CD,0x3D6
CWG Steering Control Register(1)
Bit
7
OVRD
R/W
0
Access
Reset
6
OVRC
R/W
0
5
OVRB
R/W
0
4
OVRA
R/W
0
3
STRD
R/W
0
2
STRC
R/W
0
1
STRB
R/W
0
0
STRA
R/W
0
Bits 4, 5, 6, 7 – OVRy Steering Data OVR'y'
Value
Condition
Description
x
STRy = 1
CWGx'y' output has the CWG data input waveform with polarity control from
POLy bit
1
STRy = 0 and POLy = x CWGx'y' output is high
0
STRy = 0 and POLy = x CWGx'y' output is low
Bits 0, 1, 2, 3 – STRy STR'y' Steering Enable(2)
Value
Description
1
CWGx'y' output has the CWG data input waveform with polarity control from POLy bit
0
CWGx'y' output is assigned to value of OVRy bit
Notes:
1. The bits in this register apply only when MODE = 'b00x (CWGxCON0, Steering modes).
2.
This bit is double-buffered when MODE = 'b001.
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32.14.6 CWGxAS0
Name:
Address:
CWGxAS0
0x3C2,0x3CB,0x3D4
CWG Auto-Shutdown Control Register 0
Bit
7
SHUTDOWN
Access R/W/HS/HC
Reset
0
6
REN
R/W
0
5
4
3
LSBD[1:0]
R/W
0
2
1
0
LSAC[1:0]
R/W
1
R/W
0
R/W
1
Bit 7 – SHUTDOWN Auto-Shutdown Event Status(1,2)
Value
Description
1
An Auto-shutdown state is in effect
0
No auto-shutdown event has occurred
Bit 6 – REN Auto-Restart Enable
Value
Description
1
Auto-restart is enabled
0
Auto-restart is disabled
Bits 5:4 – LSBD[1:0] CWGxB and CWGxD Auto-Shutdown State Control
Value
Description
11
A logic ‘1’ is placed on CWGxB/D when an auto-shutdown event occurs.
10
A logic ‘0’ is placed on CWGxB/D when an auto-shutdown event occurs.
01
Pin is tri-stated on CWGxB/D when an auto-shutdown event occurs.
00
The Inactive state of the pin, including polarity, is placed on CWGxB/D after the required dead-band
interval when an auto-shutdown event occurs.
Bits 3:2 – LSAC[1:0] CWGxA and CWGxC Auto-Shutdown State Control
Value
Description
11
A logic ‘1’ is placed on CWGxA/C when an auto-shutdown event occurs.
10
A logic ‘0’ is placed on CWGxA/C when an auto-shutdown event occurs.
01
Pin is tri-stated on CWGxA/C when an auto-shutdown event occurs.
00
The Inactive state of the pin, including polarity, is placed on CWGxA/C after the required dead-band
interval when an auto-shutdown event occurs.
Notes:
1. This bit may be written while EN = 0, to place the outputs into the shutdown configuration.
2.
The outputs will remain in Auto-Shutdown state until the next rising edge of the CWG data input after this bit is
cleared.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 579
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CWG - Complementary Waveform Generator Mod...
32.14.7 CWGxAS1
Name:
Address:
CWGxAS1
0x3C3,0x3CC,0x3D5
CWG Auto-Shutdown Control Register 1
Bit
7
AS7E
R/W
0
Access
Reset
6
AS6E
R/W
0
5
AS5E
R/W
0
4
AS4E
R/W
0
3
AS3E
R/W
0
2
AS2E
R/W
0
1
AS1E
R/W
0
0
AS0E
R/W
0
Bits 0, 1, 2, 3, 4, 5, 6, 7 – ASyE CWG Auto-shutdown Source Enable(1,2)
ASyE
AS7E
AS6E
AS5E
AS4E
AS3E
AS2E
AS1E
AS0E
CWG1
CLC2_OUT
Pin selected by CWG1PPS
Auto-Shutdown Source
CWG2
CLC6_OUT
CLC3_OUT
CMP2_OUT
CMP1_OUT
TMR6_Postscaler_OUT
TMR4_Postscaler_OUT
TMR2_Postscaler_OUT
Pin selected by CWG2PPS
CWG3
CLC4_OUT
Pin selected by CWG3PPS
Notes:
1. This bit may be written while EN = 0, to place the outputs into the shutdown configuration.
2.
The outputs will remain in Auto-Shutdown state until the next rising edge of the CWG data input after this bit is
cleared.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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CWG - Complementary Waveform Generator Mod...
32.14.8 CWGxDBR
Name:
Address:
CWGxDBR
0x3BE,0x3C7,0x3D0
CWG Rising Dead-Band Count Register
Bit
7
6
5
4
3
2
1
0
R/W
x
R/W
x
R/W
x
DBR[5:0]
Access
Reset
R/W
x
R/W
x
R/W
x
Bits 5:0 – DBR[5:0] CWG Rising Edge-Triggered Dead-Band Count
Reset States: POR/BOR = xxxxxx
All Other Resets = uuuuuu
Value
Description
n
Dead band is active no less than n, and no more than n+1, CWG clock periods after the rising edge
0
0 CWG clock periods. Dead-band generation is bypassed
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Preliminary Datasheet
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CWG - Complementary Waveform Generator Mod...
32.14.9 CWGxDBF
Name:
Address:
CWGxDBF
0x3BF,0x3C8,0x3D1
CWG Falling Dead-Band Count Register
Bit
7
6
5
4
3
2
1
0
R/W
x
R/W
x
R/W
x
DBF[5:0]
Access
Reset
R/W
x
R/W
x
R/W
x
Bits 5:0 – DBF[5:0] CWG Falling Edge-Triggered Dead-Band Count
Reset States: POR/BOR = xxxxxx
All Other Resets = uuuuuu
Value
Description
n
Dead band is active no less than n, and no more than n+1, CWG clock periods after the falling edge
0
0 CWG clock periods. Dead-band generation is bypassed
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
CWG - Complementary Waveform Generator Mod...
32.15
Address
0x00
...
0x03BB
0x03BC
0x03BD
0x03BE
0x03BF
0x03C0
0x03C1
0x03C2
0x03C3
0x03C4
0x03C5
0x03C6
0x03C7
0x03C8
0x03C9
0x03CA
0x03CB
0x03CC
0x03CD
0x03CE
0x03CF
0x03D0
0x03D1
0x03D2
0x03D3
0x03D4
0x03D5
0x03D6
Register Summary - CWG
Name
Bit Pos.
7
6
5
4
3
2
1
0
Reserved
CWG1CLK
CWG1ISM
CWG1DBR
CWG1DBF
CWG1CON0
CWG1CON1
CWG1AS0
CWG1AS1
CWG1STR
CWG2CLK
CWG2ISM
CWG2DBR
CWG2DBF
CWG2CON0
CWG2CON1
CWG2AS0
CWG2AS1
CWG2STR
CWG3CLK
CWG3ISM
CWG3DBR
CWG3DBF
CWG3CON0
CWG3CON1
CWG3AS0
CWG3AS1
CWG3STR
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
CS
ISM[4:0]
DBR[5:0]
DBF[5:0]
EN
LD
IN
SHUTDOWN
AS7E
OVRD
REN
AS6E
OVRC
LSBD[1:0]
AS5E
AS4E
OVRB
OVRA
POLD
POLC
LSAC[1:0]
AS3E
AS2E
STRD
STRC
MODE[2:0]
POLB
AS1E
STRB
POLA
AS0E
STRA
CS
ISM[4:0]
DBR[5:0]
DBF[5:0]
EN
LD
IN
SHUTDOWN
AS7E
OVRD
REN
AS6E
OVRC
LSBD[1:0]
AS5E
AS4E
OVRB
OVRA
POLD
POLC
LSAC[1:0]
AS3E
AS2E
STRD
STRC
MODE[2:0]
POLB
AS1E
STRB
POLA
AS0E
STRA
CS
ISM[4:0]
DBR[5:0]
DBF[5:0]
EN
LD
IN
SHUTDOWN
AS7E
OVRD
© 2021 Microchip Technology Inc.
REN
AS6E
OVRC
LSBD[1:0]
AS5E
AS4E
OVRB
OVRA
POLD
POLC
LSAC[1:0]
AS3E
AS2E
STRD
STRC
Preliminary Datasheet
MODE[2:0]
POLB
POLA
AS1E
STRB
AS0E
STRA
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NCO - Numerically Controlled Oscillator Mo...
33.
NCO - Numerically Controlled Oscillator Module
The Numerically Controlled Oscillator (NCO) module is a timer that uses overflow from the addition of an increment
value to divide the input frequency. The advantage of the addition method over a simple counter driven timer is that
the output frequency resolution does not vary with the divider value. The NCO is most useful for applications that
require frequency accuracy and fine resolution at a fixed duty cycle.
Features of the NCO include:
• 20-Bit Increment Function
• Fixed Duty Cycle (FDC) mode
• Pulse Frequency (PF) mode
• Output Pulse Width Control
• Multiple Clock Input Sources
• Output Polarity Control
• Interrupt Capability
The following figure is a simplified block diagram of the NCO module.
Figure 33-1. Numerically Controlled Oscillator Module Simplified Block Diagram
NCOxINC
20
(1)
INCxBUF
20
NCO_overflow
NCOx Cloc k
Sources
20
Adder
20
NCOx_clk
NCOxACC
See
NCOxCLK
Register
20
NCO_interrupt
Set NCOxIF
Fixed Duty
Cycle Mode
Circuitry
CKS
D
Q
D
Q
TRIS control
0
NCOx_out
_
PPS
1
NCOxOUT
Q
RxyPPS
PFM
POL
To Peripherals
S
EN
Q
_
Ripple
Counter
R
Q
Synchronizer
OUT bit in
NCOxCO N
Register
Pulse
Frequency
Mode Circuitry
R
PWS
Note 1: The increment registers are double-buffered to allow for value changes to be made without first disabling
the NCO module. The full increment value is loaded into the buffer registers on the second rising edge of the
NCOx_clk signal that occurs immediately after a write to the NCOxINCL register. The buffers are not useraccessible and are shown here for reference.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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NCO - Numerically Controlled Oscillator Mo...
33.1
NCO Operation
The NCO operates by repeatedly adding a fixed value to an accumulator. Additions occur at the input clock rate.
The accumulator will overflow with a carry periodically, which is the raw NCO output (NCO_overflow). This effectively
reduces the input clock by the ratio of the addition value to the maximum accumulator value. See the following
equation.
Equation 33-1. NCO Overflow Frequency
NCO Clock Frequency × Increment Value
FOVERFLOW =
220
It is apparent from the equation that there is a linear relationship between the increment value and the overflow
frequency. This linear advantage over divide-by-n timers comes at the cost of output jitter. However, the jitter is
always plus or minus one NCO clock period that occurs periodically, depending on the division remainder. For
example, when there is no division remainder then there is no jitter, whereas a division remainder of 0.5 will result in
a jitter frequency one half of the overflow frequency.
33.1.1
NCO Clock Sources
The NCO can be clocked from a variety of sources including the system clock, internal timers, and other peripherals.
The NCO clock source is selected by configuring the CKS bits.
33.1.2
Accumulator
The accumulator is a 20-bit register. Read and write access to the accumulator is available through three registers:
• NCOxACCL
• NCOxACCH
• NCOxACCU
33.1.3
Adder
The NCO adder is a full adder, which operates synchronously from the source clock. The addition of the previous
result and the increment value replaces the accumulator value on the rising edge of each input clock.
33.1.4
Increment Registers
The increment value is stored in three registers making up a 20-bit word. In order of LSB to MSB they are:
• NCOxINCL
• NCOxINCH
• NCOxINCU
The increment registers are readable and writable and are double-buffered to allow value changes to be made
without first disabling the NCO module.
When the NCO module is enabled, the NCOxINCU and NCOxINCH registers will be written first, then the NCOxINCL
register. Writing to the NCOxINCL register initiates the increment buffer registers to be loaded simultaneously on the
second rising edge of the NCO_clk signal.
When the NCO module is disabled, the increment buffers are loaded immediately after a write to the increment
registers.
Important: The increment buffer registers are not user-accessible.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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NCO - Numerically Controlled Oscillator Mo...
33.2
Fixed Duty Cycle Mode
In Fixed Duty Cycle (FDC) mode, every time the accumulator overflows, the output is toggled. This provides a
50% duty cycle at half the FOVERFLOW frequency, provided that the increment value remains constant. For more
information, see the figure below.
The FDC mode is selected by clearing the PFM bit.
Figure 33-2. FDC Output Mode Timing Diagram
Rev. 10-000029A
11/12/2018
NCOx
Clock
Source
NCOx
Increment
Value
NCOx
Accumulator
Value
4000h
00000h 04000h 08000h
4000h
FC000h 00000h 04000h 08000h
4000h
FC000h 00000h 04000h 08000h
NCO_overflow
NCO_interrupt
NCOx Output
FDC Mode
NCOx Output
PF Mode
NCOxPWS =
000
NCOx Output
PF Mode
NCOxPWS =
001
33.3
Pulse Frequency Mode
In Pulse Frequency (PF) mode, the output becomes active on the rising clock edge immediately following the
overflow event, and goes inactive 1 to 128 clock periods later, determined by the PWS bits. This provides a pulsed
output at the FOVERFLOW frequency. For more information, refer to the figure above.
Important: When the selected pulse width is greater than the accumulator overflow time frame, then the
NCO output does not toggle.
The level of the active and inactive states is determined by the POL bit.
PF mode is selected by setting the PFM bit.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
NCO - Numerically Controlled Oscillator Mo...
33.4
Output Polarity Control
The last stage in the NCO module is the output polarity. The POL bit selects the output polarity. The active level of the
Pulse Frequency mode is high true when the POL bit is cleared.
Changing the polarity while the interrupts are enabled will cause an interrupt for the resulting output transition.
The NCO output signal (NCOx_out) is available by internal routing to several other peripherals.
33.5
Interrupts
When the accumulator overflows, the NCO Interrupt Flag bit, NCOxIF, in the associated PIR register is set. To enable
interrupt service on this event, the following bits must be set:
• EN bit
• NCOxIE bit in the associated PIE register
• Peripheral and Global Interrupt Enable bits
The interrupt must be cleared by software by clearing the NCOxIF bit in the Interrupt Service Routine.
33.6
Effects of a Reset
All of the NCO registers are cleared to zero as the result of any Reset.
33.7
Operation in Sleep
The NCO module operates independently from the system clock and will continue to run during Sleep, provided that
the clock source selected remains active.
The HFINTOSC remains active during Sleep when the NCO module is enabled and the HFINTOSC is selected as the
clock source, regardless of the system clock source selected.
In other words, if the HFINTOSC is simultaneously selected as the system clock and the NCO clock source, when
the NCO is enabled, the CPU will go Idle during Sleep, but the NCO will continue to operate and the HFINTOSC will
remain active.
With a clock running, it will have a direct effect on the Sleep mode current.
33.8
Register Definitions: NCO
Long bit name prefixes for the NCO peripherals are shown in the table below. Refer to the “Long Bit Names”
section in the “Register and Bit Naming Conventions” chapter for more information.
Table 33-1. NCO Long Bit Name Prefixes
Peripheral
Bit Name Prefix
NCO1
NCO1
NCO2
NCO2
NCO3
NCO3
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Preliminary Datasheet
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NCO - Numerically Controlled Oscillator Mo...
33.8.1
NCOxCON
Name:
Address:
NCOxCON
0x446,0x44E,0x456
NCO Control Register
Bit
Access
Reset
7
EN
R/W
0
6
5
OUT
R
0
4
POL
R/W
0
3
2
1
0
PFM
R/W
0
Bit 7 – EN NCO Enable
Value
Description
1
NCO module is enabled
0
NCO module is disabled
Bit 5 – OUT NCO Output
Displays the current logic level of the NCO module output.
Bit 4 – POL NCO Polarity
Value
Description
1
NCO output signal is inverted
0
NCO output signal is not inverted
Bit 0 – PFM NCO Pulse Frequency Mode
Value
Description
1
NCO operates in Pulse Frequency mode. Output frequency is FOVERFLOW.
0
NCO operates in Fixed Duty Cycle mode. Output frequency is FOVERFLOW divided by 2.
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Preliminary Datasheet
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NCO - Numerically Controlled Oscillator Mo...
33.8.2
NCOxCLK
Name:
Address:
NCOxCLK
0x447,0x44F,0x457
NCO Input Clock Control Register
Bit
Access
Reset
7
R/W
0
6
PWS[2:0]
R/W
0
5
4
3
R/W
0
R/W
0
R/W
0
2
CKS[4:0]
R/W
0
1
0
R/W
0
R/W
0
Bits 7:5 – PWS[2:0] NCO Output Pulse Width Select(1)
Value
Description
111
NCO output is active for 128 input clock periods
110
NCO output is active for 64 input clock periods
101
NCO output is active for 32 input clock periods
100
NCO output is active for 16 input clock periods
011
NCO output is active for 8 input clock periods
010
NCO output is active for 4 input clock periods
001
NCO output is active for 2 input clock periods
000
NCO output is active for 1 input clock periods
Bits 4:0 – CKS[4:0] NCO Clock Source Select
CKS
Value
11111-11011
11010
11001
11000
10111
10110
10101
10100
10011
10010
10001
10000
01111-01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
© 2021 Microchip Technology Inc.
NCO1
NCO3_OUT
NCO2_OUT
Reserved
Clock Source
NCO2
Reserved
CLC8_OUT
CLC7_out
CLC6_out
CLC5_OUT
CLC4_OUT
CLC3_out
CLC2_OUT
CLC1_OUT
NCO3_OUT
Reserved
NCO1_OUT
Reserved
TU16B_OUT
TU16A_OUT
TMR6_OUT
TMR4_OUT
TMR2_OUT
CLKREF
EXTOSC
SOSC
MFINTOSC
MFINTOSC
LFINTOSC
HFINTOSC
NC03
Reserved
NCO2_OUT
NCO1_OUT
Preliminary Datasheet
Active in Sleep
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
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NCO - Numerically Controlled Oscillator Mo...
...........continued
CKS
Value
00000
NCO1
Clock Source
NCO2
FOSC
NC03
Active in Sleep
No
Note:
1. PWS applies only when operating in Pulse Frequency mode.
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Preliminary Datasheet
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NCO - Numerically Controlled Oscillator Mo...
33.8.3
NCOxACC
Name:
Address:
NCOxACC
0x440,0x448,0x450
NCO Accumulator Register
Bit
23
22
21
20
19
18
17
16
ACC[19:16]
Access
Reset
Bit
15
14
13
12
R/W
0
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
ACC[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
ACC[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 19:0 – ACC[19:0] Accumulated sum of NCO additions
Notes:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– NCOxACCU: Accesses the upper byte ACC[23:16]
– NCOxACCH: Accesses the high byte ACC[15:8]
– NCOxACCL: Accesses the low byte ACC[7:0]
2. The accumulator spans registers NCOxACCU:NCOxACCH:NCOxACCL. The 24 bits are reserved but not all
are used. This register updates in real-time, asynchronously to the CPU; there is no provision to ensure
atomic access to this 24-bit space using an 8-bit bus. Writing to this register while the module is operating will
produce undefined results.
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Preliminary Datasheet
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NCO - Numerically Controlled Oscillator Mo...
33.8.4
NCOxINC
Name:
Address:
NCOxINC
0x443,0x44B,0x453
NCO Increment Register
Bit
23
22
21
20
19
18
17
16
INC[19:16]
Access
Reset
Bit
15
14
13
12
R/W
0
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
1
INC[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
INC[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 19:0 – INC[19:0] Value by which the NCOxACC is increased by each NCO clock
Notes:
1. The individual bytes in this multi-byte register can be accessed with the following register names:
– NCOxINCU: Accesses the upper byte INC[19:16]
– NCOxINCH: Accesses the high byte INC[15:8]
– NCOxINCL: Accesses the low byte INC[7:0]
2. The logical increment spans NCOxINCU:NCOxINCH:NCOxINCL.
3. NCOxINC is double-buffered as INCBUF:
– INCBUF is updated on the next falling edge of NCOxCLK after writing to NCOxINCL
– NCOxINCU and NCOxINCH will be written prior to writing NCOxINCL
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Preliminary Datasheet
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PIC18F27/47/57Q84
NCO - Numerically Controlled Oscillator Mo...
33.9
Register Summary - NCO
Address
Name
0x00
...
0x043F
Reserved
0x0440
NCO1ACC
0x0443
NCO1INC
0x0446
0x0447
NCO1CON
NCO1CLK
0x0448
NCO2ACC
0x044B
NCO2INC
0x044E
0x044F
NCO2CON
NCO2CLK
0x0450
NCO3ACC
0x0453
NCO3INC
0x0456
0x0457
NCO3CON
NCO3CLK
Bit Pos.
7:0
15:8
23:16
7:0
15:8
23:16
7:0
7:0
7:0
15:8
23:16
7:0
15:8
23:16
7:0
7:0
7:0
15:8
23:16
7:0
15:8
23:16
7:0
7:0
7
6
5
4
3
2
1
0
ACC[7:0]
ACC[15:8]
ACC[19:16]
INC[7:0]
INC[15:8]
INC[19:16]
EN
OUT
POL
PFM
PWS[2:0]
CKS[4:0]
ACC[7:0]
ACC[15:8]
ACC[19:16]
INC[7:0]
INC[15:8]
INC[19:16]
EN
OUT
POL
PFM
PWS[2:0]
CKS[4:0]
ACC[7:0]
ACC[15:8]
ACC[19:16]
INC[7:0]
INC[15:8]
INC[19:16]
EN
© 2021 Microchip Technology Inc.
OUT
POL
PWS[2:0]
PFM
CKS[4:0]
Preliminary Datasheet
DS40002213D-page 593
PIC18F27/47/57Q84
DSM - Data Signal Modulator Module
34.
DSM - Data Signal Modulator Module
The Data Signal Modulator (DSM) is a peripheral that allows the user to mix a data stream, also known as a
modulator signal, with a carrier signal to produce a modulated output. Both the carrier and the modulator signals
are supplied to the DSM module either internally, from the output of a peripheral, or externally through an input pin.
The modulated output signal is generated by performing a logical “AND” operation of both the carrier and modulator
signals, and then provided to the DSM_out pin.
The carrier signal is comprised of two distinct and separate signals. A Carrier High (CARH) signal and a Carrier Low
(CARL) signal. During the time in which the modulator (MOD) signal is in a Logic High state, the DSM mixes the
CARH signal with the modulator signal. When the modulator signal is in a Logic Low state, the DSM mixes the CARL
signal with the modulator signal.
Using this method, the DSM can generate the following types of key modulation schemes:
•
•
•
Frequency Shift Keying (FSK)
Phase-Shift Keying (PSK)
ON-OFF Keying (OOK)
Additionally, the following features are provided within the DSM module:
•
•
•
•
•
Carrier Synchronization
Carrier Source Polarity Select
Programmable Modulator Data
Modulated Output Polarity Select
Peripheral Module Disable, which provides the ability to place the DSM module in the lowest power consumption
mode
The figure below shows a simplified block diagram of the data signal modulator peripheral.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 594
PIC18F27/47/57Q84
DSM - Data Signal Modulator Module
Figure 34-1. Simplified Block Diagram of the Data Signal Modulator
CH
Data Signal Modulator
See
MDxCARH
Register
CARH
CHPOL
D
SYNC
Q
1
MS
0
CHSYNC
RxyPPS
See
MDxSRC
Register
MOD
PPS
DSM_out
OPOL
CL
D
SYNC
Q
1
0
See
MDxCARL
Register
CARL
CLSYNC
CLPOL
34.1
DSM Operation
The DSM module is enabled by setting the EN bit. Clearing the EN bit disables the output of the module, but retains
the carrier and source signal selections. The module will resume operation when the EN bit is set again. The output
of the DSM module can be rerouted to several pins using the PPS output source selection register. When the EN bit
is cleared the output pin is held low.
34.1.1
Modulator Signal Sources
The modulator signal can be supplied from several different sources, and is selected by configuring the MS bits.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 595
PIC18F27/47/57Q84
DSM - Data Signal Modulator Module
34.1.2
Carrier Signal Sources
The carrier high signal and carrier low signal can be supplied from several different sources, and is selected by the
CH bits and CL bits, respectively.
34.2
Carrier Synchronization
During the time when the DSM switches between carrier high and carrier low signal sources, the carrier data in
the modulated output signal can become truncated. To prevent this, the carrier signal can be synchronized to the
modulator signal. When synchronization is enabled, the carrier pulse that is being mixed at the time of the transition
is allowed to transition low before the DSM switches over to the next carrier source.
Synchronization is enabled separately for the carrier high and carrier low signal sources. Synchronization for the
carrier high signal is enabled by setting the CHSYNC bit. Synchronization for the carrier low signal is enabled by
setting the CLSYNC bit. The figures below show the timing diagrams of using various synchronization methods.
Figure 34-2. On-Off Keying (OOK) Synchronization
carrier_low
carrier_high
Modula tor
DSM_out
CHSYNC = 1
CLSYNC = 0
DSM_out
CHSYNC = 1
CLSYNC = 1
DSM_out
CHSYNC = 0
CLSYNC = 0
DSM_out
CHSYNC = 0
CLSYNC = 1
Figure 34-3. No Synchronization (CHSYNC = 0, CLSYNC = 0)
carrier_high
carrier_low
Modula tor
DSM_out
Acti ve Carrier
State
carrier_high
© 2021 Microchip Technology Inc.
carrier_low
Preliminary Datasheet
carrier_high
carrier_low
DS40002213D-page 596
PIC18F27/47/57Q84
DSM - Data Signal Modulator Module
Figure 34-4. Carrier High Synchronization (CHSYNC = 1, CLSYNC = 0)
carrier_high
carrier_low
Modula tor
DSM_out
Acti ve Carrier
State
carrier_high
both
carrier_low
carrier_high
both
carrier_low
Figure 34-5. Carrier Low Synchronization (CHSYNC = 0, CLSYNC = 1)
carrier_high
carrier_low
Modula tor
DSM_out
Acti ve Carrier
State
carrier_high
carrier_low
carrier_high
carrier_low
Figure 34-6. Full Synchronization (CHSYNC = 1, CLSYNC = 1)
carrier_high
carrier_low
Modula tor
Falling edg es
used to sync
DSM_out
Acti ve Carrier
State
34.3
carrier_high
carrier_low
carrier_high
CL
Carrier Source Polarity Select
The signal provided from any selected input source for the carrier high and carrier low signals can be inverted.
Inverting the signal for the carrier high and low source is enabled by setting the CHPOL bit and the CLPOL bit,
respectively.
34.4
Programmable Modulator Data
The BIT control bit can used to generate the modulation signal. This gives the user the ability to provide software
driven modulation.
34.5
Modulated Output Polarity
The modulated output signal provided on the DSM_out pin can also be inverted. Inverting the modulated output
signal is enabled by setting the OPOL bit.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 597
PIC18F27/47/57Q84
DSM - Data Signal Modulator Module
34.6
Operation in Sleep Mode
The DSM can operate during Sleep, if the carrier and modulator input sources are also operable during Sleep. Refer
to “Power-Saving Modes” chapter for more details.
34.7
Effects of a Reset
Upon any device Reset, the DSM module is disabled. The user’s firmware is responsible for initializing the module
before enabling the output. All the registers are reset to their default values.
34.8
Peripheral Module Disable
The DSM module can be completely disabled using the PMD module to achieve maximum power saving. When the
DSMMD bit of the PMD registers is set, the DSM module is completely disabled. This puts the module in its lowest
power consumption state. When enabled again all the registers of the DSM module default to POR status.
34.9
Register Definitions: Modulation Control
Long bit name prefixes for the modulation control peripherals are shown in the table below. Refer to the “Long Bit
Names” section in the “Register and Bit Naming Conventions” chapter for more information.
Table 34-1. Modulation Control Long Bit Name Prefixes
Peripheral
Bit Name Prefix
DSM1
MD1
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 598
PIC18F27/47/57Q84
DSM - Data Signal Modulator Module
34.9.1
MDxCON0
Name:
Address:
MDxCON0
0x6A
Modulation Control Register 0
Bit
Access
Reset
7
EN
R/W
0
6
5
OUT
R/W
0
4
OPOL
R/W
0
3
2
1
0
BIT
R/W
0
Bit 7 – EN Modulator Module Enable
Value
Description
1
DSM is enabled and mixing input signals
0
DSM is disabled and has no output
Bit 5 – OUT Modulator Output(1)
Displays the current DSM_out value
Bit 4 – OPOL Modulator Output Polarity Select
Value
Description
1
DSM output signal is inverted; idle high output
0
DSM output signal is not inverted; idle low output
Bit 0 – BIT Modulation Source Signal(2)
Allows direct software control of the modulation signal
Notes:
1. The modulated output frequency can be greater and asynchronous from the clock that updates this register bit.
The bit value may not be valid for higher speed modulator or carrier signals.
2. MDBIT must be selected as the modulation source in the MDxSRC register for this operation.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 599
PIC18F27/47/57Q84
DSM - Data Signal Modulator Module
34.9.2
MDxCON1
Name:
Address:
MDxCON1
0x6B
Modulation Control Register 1
Bit
7
6
Access
Reset
5
CHPOL
R/W
0
4
CHSYNC
R/W
0
3
2
1
CLPOL
R/W
0
0
CLSYNC
R/W
0
Bit 5 – CHPOL Modulator High Carrier Polarity Select
Value
Description
1
Selected high carrier signal is inverted
0
Selected high carrier signal is not inverted
Bit 4 – CHSYNC Modulator High Carrier Synchronization Enable
Value
Description
1
Modulator waits for a falling edge on the high time carrier signal before allowing a switch to the low
time carrier
0
Modulator output is not synchronized to the high time carrier signal(1)
Bit 1 – CLPOL Modulator Low Carrier Polarity Select
Value
Description
1
Selected low carrier signal is inverted
0
Selected low carrier signal is not inverted
Bit 0 – CLSYNC Modulator Low Carrier Synchronization Enable
Value
Description
1
Modulator waits for a falling edge on the low time carrier signal before allowing a switch to the high
time carrier
0
Modulator output is not synchronized to the low time carrier signal(1)
Note:
1. Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 600
PIC18F27/47/57Q84
DSM - Data Signal Modulator Module
34.9.3
MDxCARH
Name:
Address:
MDxCARH
0x6E
Modulation High Carrier Control Register
Bit
7
6
Access
Reset
5
4
3
R/W
0
R/W
0
2
CH[4:0]
R/W
0
1
0
R/W
0
R/W
0
Bits 4:0 – CH[4:0] Modulator Carrier High Selection
CH
Connection
11111-10111
10110
10101
10100
10011
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
Reserved
CLC8_OUT
CLC7_OUT
CLC6_OUT
CLC5_OUT
CLC4_OUT
CLC3_OUT
CLC2_OUT
CLC1_OUT
NCO3_OUT
NCO2_OUT
NCO1_OUT
PWM4S1P1_OUT
PWM3S1P1_OUT
PWM2S1P1_OUT
PWM1S1P1_OUT
CCP3_OUT
CCP2_OUT
CCP1_OUT
CLKREF_OUT
EXTOSC
HFINTOSC
FOSC (System Clock)
Pin selected by MDCARHPPS
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 601
PIC18F27/47/57Q84
DSM - Data Signal Modulator Module
34.9.4
MDxCARL
Name:
Address:
MDxCARL
0x6D
Modulation Low Carrier Control Register
Bit
7
6
Access
Reset
5
4
3
R/W
0
R/W
0
2
CL[4:0]
R/W
0
1
0
R/W
0
R/W
0
Bits 4:0 – CL[4:0] Modulator Carrier Low Input Selection
CL
Connection
11111-10111
10110
10101
10100
10011
10010
10001
10000
01111
01110
01101
01100
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
Reserved
CLC8_OUT
CLC7_OUT
CLC6_OUT
CLC5_OUT
CLC4_OUT
CLC3_OUT
CLC2_OUT
CLC1_OUT
NCO3_OUT
NCO2_OUT
NCO1_OUT
PWM4S1P2_OUT
PWM3S1P2_OUT
PWM2S1P2_OUT
PWM1S1P2_OUT
CCP3_OUT
CCP2_OUT
CCP1_OUT
CLKREF_OUT
EXTOSC
HFINTOSC
FOSC (System Clock)
Pin selected by MDCARLPPS
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 602
PIC18F27/47/57Q84
DSM - Data Signal Modulator Module
34.9.5
MDxSRC
Name:
Address:
MDxSRC
0x6C
Modulation Source Control Register
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
MS[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 5:0 – MS[5:0] Modulator Source Selection
MS
Connection
111111-100000
100000
011111
011110
011101
011100
011011
011010
011001
011000
010111
010110
010101
010100
010011
010010
010001
010000
001111
001110
001101
001100
001011
001010
001001
001000
000111
000110
000101
000100
000011
000010
000001
000000
Reserved
SPI2_SDO
SPI1_SDO
UART5_TX
UART4_TX
UART3_TX
UART2_TX
UART1_TX
CLC8_OUT
CLC7_OUT
CLC6_OUT
CLC5_OUT
CLC4_OUT
CLC3_OUT
CLC2_OUT
CLC1_OUT
CMP2_OUT
CMP1_OUT
NCO3_OUT
NCO2_OUT
NCO1_OUT
PWM4S1P2_OUT
PWM4S1P1_OUT
PWM3S1P2_OUT
PWM3S1P1_OUT
PWM2S1P2_OUT
PWM2S1P1_OUT
PWM1S1P2_OUT
PWM1S1P1_OUT
CCP3_OUT
CCP2_OUT
CCP1_OUT
MDBIT
Pin selected by MDSRCPPS
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 603
PIC18F27/47/57Q84
DSM - Data Signal Modulator Module
34.10
Address
0x00
...
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
Register Summary - DSM
Name
Bit Pos.
7
7:0
7:0
7:0
7:0
7:0
EN
6
5
4
OUT
CHPOL
OPOL
CHSYNC
3
2
1
0
CLPOL
BIT
CLSYNC
Reserved
MD1CON0
MD1CON1
MD1SRC
MD1CARL
MD1CARH
© 2021 Microchip Technology Inc.
MS[5:0]
CL[4:0]
CH[4:0]
Preliminary Datasheet
DS40002213D-page 604
PIC18F27/47/57Q84
UART - Universal Asynchronous Receiver Tra...
35.
UART - Universal Asynchronous Receiver Transmitter with Protocol
Support
The Universal Asynchronous Receiver Transmitter (UART) module is a serial I/O communications peripheral. It
contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data
transfer, independent of device program execution. The UART, also known as a Serial Communications Interface
(SCI), can be configured as a full-duplex asynchronous system or one of several automated protocols. The FullDuplex mode is useful for communications with peripheral systems, such as wireless modems and USB to serial
interface modules.
Supported protocols include:
•
•
•
LIN Host and Client
DMX Controller and Receiver
DALI Control Gear and Control Device
The UART module includes the following capabilities:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Half and Full-duplex asynchronous transmit and receive
Two-byte input buffer
One-byte output buffer
Programmable 7-bit or 8-bit byte width
9th bit address detection
9th bit even or odd parity
Input buffer overrun error detection
Receive framing error detection
Hardware and software flow control
Automatic checksum calculation and verification
Programmable 1, 1.5, and 2 Stop bits
Programmable data polarity
Manchester encoder/decoder
Operation in Sleep
Automatic detection and calibration of the baud rate
Wake-up on Break reception
Automatic and user timed Break period generation
RX and TX inactivity time-outs (with Timer2)
The operation of the UART module is controlled through nineteen 8-bit registers:
•
•
•
•
•
•
•
•
•
Three control registers (UxCON0-UxCON2)
Error enable and status (UxERRIE, UxERRIR, UxUIR)
UART buffer status and control (UxFIFO)
Three 9-bit protocol parameters (UxP1-UxP3)
16-bit Baud Rate Generator (UxBRG)
Transmit buffer write (UxTXB)
Receive buffer read (UxRXB)
Receive checksum (UxRXCHK)
Transmit checksum (UxTXCHK)
The UART transmit output (TX_out) is available to the TX pin and internally to various peripherals.
Block diagrams of the UART transmitter and receiver are shown in the following figures.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 605
PIC18F27/47/57Q84
UART - Universal Asynchronous Receiver Tra...
Figure 35-1. UART Transmitter Block Diagram
Data bus
Rev. 10-000113D
11/2/2018
8
UxTXIE
Interrupt
FIFO
(if equipped)
UxTXB register
UxTXIF
8
UxTXCHK
+
TXEN
MSb
LSb
(8)
0
RxyPPS
TX pin
Mode
Control
Transmit Shift Register (TSR)
PPS
TX_out
Baud Rate Generator
FOSC
TXMTIF
Address or
Parity mode
÷n
n
+1
Multiplier
x4
x16
BRGS
1
0
UxBRGH UxBRGL
Figure 35-2. UART Receiver Block Diagram
Rev. 10-000114C
11/2/2018
RXFOIF
RXIDL
RXEN
RXPPS
RSR Register
MSb
RX pin
PPS
Baud Rate Generator
Pin Buffer
and Control
FOSC
Mode Data
Recovery
Stop (8)
0
Start
UxRXCHK
+
Address or
Parity Mode
Multiplier
x4
x16
BRGS
1
0
UxBRGH UxBRGL
1
÷n
n
+1
7
LSb
FERIF
PERIF
UxRXB Register
FIFO
8
Data Bus
UxRXIF
UxRXIE
35.1
Interrupt
UART I/O Pin Configuration
The RX input pin is selected with the UxRPPS register. The TX output pin is selected with each pin’s RxyPPS
register. When the TRIS control for the pin corresponding to the TX output is cleared, the UART will control the logic
level on the TX pin. Changing the TXPOL bit in UxCON2 will immediately change the TX pin logic level, regardless of
the value of EN or TXEN.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 606
PIC18F27/47/57Q84
UART - Universal Asynchronous Receiver Tra...
35.2
UART Asynchronous Modes
The UART has five asynchronous modes:
•
•
•
•
•
7-bit
8-bit
8-bit with even parity in the 9th bit
8-bit with odd parity in the 9th bit
8-bit with address indicator in the 9th bit
The UART transmits and receives data using the standard Non-Return-to-Zero (NRZ) format. NRZ is implemented
with two levels: a VOH Mark state, which represents a ‘1’ data bit, and a VOL Space state, which represents a ‘0’
data bit. NRZ implies that consecutively transmitted data bits of the same value stay at the output level of that bit
without returning to a neutral level between each bit transmission. An NRZ transmission port idles in the Mark state.
Each character transmission consists of one Start bit followed by seven or eight data bits, one optional parity or
address bit, and is always terminated by one or more Stop bits. The Start bit is always a space and the Stop bits are
always marks. The most common data format is eight bits with no parity. Each transmitted bit persists for a period of
1/ (Baud Rate). An on-chip dedicated 16-bit Baud Rate Generator is used to derive standard baud rate frequencies
from the system oscillator. See UART Baud Rate Generator for more information.
In all asynchronous modes, the UART transmits and receives the LSb first. The UART’s transmitter and receiver are
functionally independent, but share the same data format and baud rate. Parity is supported by the hardware with
even and odd parity modes.
35.2.1
UART Asynchronous Transmitter
The UART transmitter block diagram is shown in Figure 35-1. The heart of the transmitter is the serial Transmit Shift
Register (TSR), which is not directly accessible by software. The TSR obtains its data from the transmit buffer, which
is the UxTXB register.
35.2.1.1 Enabling the Transmitter
The UART transmitter is enabled for asynchronous operations by configuring the following control bits:
•
TXEN = 1
•
MODE = 0000 through 0011
•
•
•
•
UxBRG = desired baud rate
BRGS = desired baud rate multiplier
RxyPPS = code for desired output pin
ON = 1
All other UART control bits are assumed to be in their default state.
Setting the TXEN bit enables the transmitter circuitry of the UART. The MODE bits select the desired mode. Setting
the ON bit enables the UART. When TXEN is set and the transmitter is not Idle, the TX pin is automatically configured
as an output. When the transmitter is Idle, the TX pin drive is relinquished to the port TRIS control. If the TX pin is
shared with an analog peripheral, the analog I/O function will be disabled by clearing the corresponding ANSEL bit.
Important: The UxTXIF Transmitter Interrupt flag is set when the TXEN Enable bit is set and the UxTXB
register can accept data.
35.2.1.2 Transmitting Data
A transmission is initiated by writing a character to the UxTXB register. If this is the first character, or the previous
character has been completely transmitted from the TSR, the data in the UxTXB is immediately transferred to the
TSR register. If the TSR still contains all or part of a previous character, the new character data is held in the UxTXB
until the previous character transmission is complete. The pending character in the UxTXB is then transferred to the
TSR at the beginning of the previous character Stop bit transmission. The transmission of the Start bit, data bits and
Stop bit sequence commences immediately following the completion of all of the previous character’s Stop bits.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
UART - Universal Asynchronous Receiver Tra...
35.2.1.3 Transmit Data Polarity
The polarity of the transmit data is controlled with the TXPOL bit. The default state of this bit is ‘0’ which selects high
true transmit idle and data bits. Setting the TXPOL bit to ‘1’ will invert the transmit data, resulting in low true idle and
data bits. The TXPOL bit controls transmit data polarity in all modes.
35.2.1.4 Transmit Interrupt Flag
The UxTXIF Interrupt Flag bit in the PIR register is set whenever the UART transmitter is enabled and no character is
being held for transmission in the UxTXB register. In other words, the UxTXIF bit is clear only when the TSR is busy
with a character and a new character has been queued for transmission in the UxTXB register.
The UxTXIF interrupt is enabled by setting the UxTXIE Interrupt Enable bit in the PIE register. However, the UxTXIF
Flag bit will be set whenever the UxTXB register is empty, regardless of the state of the UxTXIE Enable bit. The
UxTXIF bit is read-only and cannot be set or cleared by software.
To use interrupts when transmitting data, set the UxTXIE bit only when there is more data to send. Clear the UxTXIE
Interrupt Enable bit upon writing the UxTXB register with the last character of the transmission.
35.2.1.5 TSR Status
The TXMTIF bit indicates the status of the TSR. This is a read-only bit. The TXMTIF bit is set when the TSR is empty
and idle. The TXMTIF bit is cleared when a character is transferred to the TSR from the UxTXB. The TXMTIF bit
remains clear until all bits, including the Stop bits, have been shifted out of the TSR and a byte is not waiting in the
UxTXB register.
The TXMTIF will generate a summary UxEIF interrupt when the TXMTIE bit is set.
Important: The TSR is not mapped in data memory, so it is not available to the user.
35.2.1.6 Transmitter 7-bit Mode
The 7-Bit mode is selected when the MODE bits are set to ‘0001’. In 7-bit mode, only the seven Least Significant
bits of the data written to UxTXB are transmitted. The Most Significant bit is ignored.
35.2.1.7 Transmitter Parity Modes
When odd or even parity mode is selected, all data is sent as nine bits. The first eight bits are data and the 9th bit
is parity. Even and odd parity is selected when the MODE bits are set to ‘0011’ and ‘0010’, respectively. Parity is
automatically determined by the module and inserted in the serial data stream.
35.2.1.8 Asynchronous Transmission Setup
Use the following steps as a guide for configuring the UART for asynchronous transmissions.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Initialize the UxBRG register pair and the BRGS bit to achieve the desired baud rate.
Set the MODE bits to the desired Asynchronous mode.
Set the TXPOL bit if inverted TX output is desired.
Enable the asynchronous serial port by setting the ON bit.
Enable the transmitter by setting the TXEN Control bit. This will cause the UxTXIF Interrupt flag to be set.
If the device has PPS, configure the desired I/O pin RxyPPS register with the code for the TX output.
If interrupts are desired, set the UxTXIE Interrupt Enable bit in the respective PIE register. An interrupt will
occur immediately provided that global interrupts are also enabled.
Write one byte of data into the UxTXB register. This will start the transmission.
Subsequent bytes may be written when the UxTXIF bit is ‘1’.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
UART - Universal Asynchronous Receiver Tra...
Figure 35-3. UART Asynchronous Transmission
Rev. 10-000115B
9/1/2017
Word 1
Write to UxTXB
BRG Output
(Shift Clock)
TX pin
UxTXIF
(Transmit Buffer
Reg Empty
Flag) bit
TXMTIF (Transmit
Shift Reg Empty
Flag) bit
Start bit
bit 0
bit 1
bit 7/8
Stop bit
Word 1
1 TCY
Figure 35-4. UART Asynchronous Transmission (back-to-back)
Word 1
Rev. 10-000116B
9/1/2017
Word 2
Write to UxTXB
BRG Output
(Shift Clock)
TX pin
UxTXIF
(Transmit Buffer
Reg Empty Flag) bit
TXMTIF
(Transmit Shift
Reg Empty Flag)
bit
35.2.2
Start bit
bit 0
bit 1
bit 7/8
Stop bit
Start bit
Word 1
bit 0
Word 2
1 TCY
UART Asynchronous Receiver
The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 35-2.
The data is received on the RX pin and drives the data recovery block. The data recovery block is actually a
high-speed shifter operating at 4 or 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates
at the bit rate. When all bits of the character have been shifted in, they are immediately transferred to a two-character
First-In First-Out (FIFO) memory. The FIFO buffering allows reception of two complete characters and the start of a
third character before software must begin servicing the UART receiver. The FIFO registers and RSR are not directly
accessible by software. Access to the received data is made via the UxRXB register.
35.2.2.1 Enabling the Receiver
The UART receiver is enabled for asynchronous operation by configuring the following control bits:
•
RXEN = 1
•
MODE = 0000 through 0011
•
•
•
•
UxBRG = desired baud rate
BRGS = desired baud rate multiplier
RXPPS = code for desired input pin
Input pin ANSEL bit = 0
•
ON = 1
All other UART control bits are assumed to be in their default state.
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Setting the RXEN bit enables the receiver circuitry of the UART. Setting the MODE bits configures the UART for the
desired Asynchronous mode. Setting the ON bit enables the UART. The TRIS bit corresponding to the selected RX
I/O pin must be set to configure the pin as an input.
Important: If the RX function is on an analog pin, the corresponding ANSEL bit must be cleared for the
receiver to function.
35.2.2.2 Receiving Data
Data is recovered from the bit stream by timing to the center of the bits and sampling the input level. In High-Speed
mode, there are four BRG clocks per bit and only one sample is taken per bit. In Normal-Speed mode, there are 16
BRG clocks per bit and three samples are taken per bit.
The receiver data recovery circuit initiates character reception on the falling edge of the Start bit. The Start bit
is always a ‘0’. The Start bit is qualified in the middle of the bit. In Normal-Speed mode only, the Start bit is
also qualified at the leading edge of the bit. The following paragraphs describe the majority-detect sampling of the
Normal-Speed mode without inverted polarity.
The falling edge starts the Baud Rate Generator (BRG) clock. The input is sampled at the first and second BRG
clocks.
If both samples are high, then the falling edge is deemed a glitch and the UART returns to the Start bit detection state
without generating an error.
If either sample is low, the data recovery circuit continues counting BRG clocks and takes samples at clock counts:
7, 8, and 9. When less than two samples are low, the Start bit is deemed invalid and the data recovery circuit aborts
character reception, without generating an error, and resumes looking for the falling edge of the Start bit.
When two or more samples are low, the Start bit is deemed valid and the data recovery continues. After a valid Start
bit is detected, the BRG clock counter continues and resets at count 16. This is the beginning of the first data bit.
The data recovery circuit counts the BRG clocks from the beginning of the bit and takes samples at clocks 7, 8, and
9. The bit value is determined from the majority of the samples. The resulting ‘0’ or ‘1’ is shifted into the RSR. The
BRG clock counter continues and resets at count 16. This sequence repeats until all data bits have been sampled
and shifted into the RSR.
After all data bits have been shifted in, the first Stop bit is sampled. Stop bits are always a ‘1’. If the bit sampling
determines that a ‘0’ is in the Stop bit position, the framing error is set for this character. Otherwise, the framing error
is cleared for this character. See Receive Framing Error for more information on framing errors.
35.2.2.3 Receive Data Polarity
The polarity of the receive data is controlled with the RXPOL bit. The default state of this bit is ‘0’ which selects high
true receive idle and data bits. Setting the RXPOL bit to ‘1’ will invert the receive data, resulting in low true idle and
data bits. The RXPOL bit controls receive data polarity in all modes.
35.2.2.4 Receive Interrupts
Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred to the
UART receive FIFO. The UxRXIF Interrupt flag in the respective PIR register is set at this time, provided it is not
being suppressed.
The UxRXIF is suppressed by any of the following:
•
•
FERIF when FERIE is set
PERIF when PERIE is set
When the UART uses DMA for reception, suppressing the UxRXIF suspends the DMA transfer of data until software
processes the error and reads UxRXB to advance the FIFO beyond the error.
The UxRXIF interrupts are enabled by setting all of the following bits:
•
•
UxRXIE, Interrupt Enable bit in the PIE register
Global Interrupt Enable bits
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The UxRXIF Interrupt Flag bit will be set when it is not suppressed and there is an unread character in the FIFO,
regardless of the state of interrupt enable bits. Reading the UxRXB register will transfer the top character out of the
FIFO and reduce the FIFO contents by one. The UxRXIF Interrupt Flag bit is read-only and therefore cannot be set or
cleared by software.
35.2.2.5 Receive Framing Error
Each character in the receive FIFO buffer has a corresponding Framing Error Flag bit. A framing error indicates that
the Stop bit was not seen at the expected time. For example, a Break condition will be received as a 0x00 byte with
the framing error bit set.
The Framing Error flag is accessed via the FERIF bit. The FERIF bit represents the frame status of the top unread
character of the receive FIFO. Therefore, the FERIF bit must be read before reading UxRXB.
The FERIF bit is read-only and only applies to the top unread character of the receive FIFO. A framing error (FERIF
= 1) does not preclude reception of additional characters. It is neither necessary nor possible to clear the FERIF bit
directly. Reading the next character from the FIFO buffer will advance the FIFO to the next character and the next
corresponding framing error, if any.
The FERIF bit is cleared when the character at the top of the FIFO does not have a framing error or when all bytes in
the receive FIFO have been read. Clearing the ON bit resets the receive FIFO, thereby also clearing the FERIF bit.
A framing error will generate a summary UxEIF interrupt when the FERIE bit is set. The summary error is reset when
the FERIF bit of the top of the FIFO is ‘0’ or when all FIFO characters have been retrieved.
Important: When FERIE is set, UxRXIF interrupts are suppressed by FERIF = 1.
35.2.2.6 Receiver Parity Modes
Even or odd parity is automatically detected when the MODE bits are set to ‘0011’ or ‘0010’, respectively. The
parity modes receive eight data bits and one parity bit for a total of nine bits for each character. The PERIF bit
represents the parity error of the top unread character of the receive FIFO rather than the parity bit itself. The parity
error must be read before the UxRXB register is read because reading the UxRXB register will advance the FIFO
pointer to the next byte with its associated PERIF flag.
A parity error will generate a summary UxEIF interrupt when the PERIE bit is set. The summary error is reset when
the PERIF bit of the top of the FIFO is ‘0’ or when all FIFO characters have been retrieved.
Important: When PERIE is set, the UxRXIF interrupts are suppressed by PERIF = 1.
35.2.2.7 Receive FIFO Overflow
When more characters are received than the receive FIFO can hold, the RXFOIF bit is set. The character causing
the Overflow condition is discarded. The RUNOVF bit determines how the receive circuit responds to characters
while the Overflow condition persists. When RUNOVF is set, the receive shifter stays synchronized to the incoming
data stream by responding to Start, data, and Stop bits. However, all received bytes not already in the FIFO are
discarded. When RUNOVF is cleared, the receive shifter ceases operation and Start, data, and Stop bits are ignored.
The Receive Overflow condition is cleared by reading the UxRXB register and clearing the RXFOIF bit. If the UxRXB
register is not read, thereby opening a space in the FIFO, the next character received will be discarded and cause
another Overflow condition.
A receive overflow error will generate a summary UxEIF interrupt when the RXFOIE bit is set.
35.2.2.8 Asynchronous Reception Setup
Use the following steps as a guide for configuring the UART for asynchronous reception:
1.
Initialize the UxBRG register pair and the BRGS bit to achieve the desired baud rate.
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2.
3.
4.
5.
6.
7.
8.
9.
10.
Configure the RXPPS register for the desired RX pin.
Clear the ANSEL bit for the RX pin (if applicable).
Set the MODE bits to the desired Asynchronous mode.
Set the RXPOL bit if the data stream is inverted.
Enable the serial port by setting the ON bit.
If interrupts are desired, set the UxRXIE bit in the PIEx register and enable global interrupts.
Enable reception by setting the RXEN bit.
Read the UxERRIR register to get the error flags.
The UxRXIF Interrupt Flag bit will be set when a character is transferred from the RSR to the receive buffer. An
interrupt will be generated if the UxRXIE interrupt enable bit is also set.
11. Read the UxRXB register to get the received byte.
12. If an overrun occurred, clear the RXFOIF bit.
Figure 35-5. UART Asynchronous Reception
Rev. 10-000117B
1/24/2019
RX pin
Start
bit
bit 0
Last
bit
Stop
bit
Start
bit
Word 1
Rcv Shift Reg
Rcv Buffer Reg
bit 0
Last
bit
Stop
bit
Start
bit
Word 2
Word 1
UxRXB
bit 0
Last
bit
Stop
bit
Word 3
Word 2
UxRXB
RXIDL
Read UxRXB
UxRXIF
(Interrupt flag)
RXFOIF Flag
Cleared by software
Note: This timing diagram shows three bytes appearing on the RX input. The UxRXB is not read before the third
word is received, causing the RXFOIF (FIFO overrun) bit to be set. STPMD = 0, STP=00.
35.2.3
Asynchronous Address Mode
A special Address Detection mode is available for use when multiple receivers share the same transmission line, as
seen in RS-485 systems.
When Asynchronous Address mode is enabled, all data is transmitted and received as 9-bit characters. The 9th bit
determines whether the character is address or data. When the 9th bit is set, the eight Least Significant bits are
the address. When the 9th bit is clear, the Least Significant bits are data. In either case, the 9th bit is stored in
PERIF when the byte is written to the receive FIFO. When PERIE is also set, the RXIF will be suppressed, thereby
suspending DMA transfers allowing software to process the received address.
An address character will enable all receivers that match the address and disable all other receivers. Once a receiver
is enabled, all non-address characters will be received until an address character that does not match is received.
35.2.3.1 Address Mode Transmit
The UART transmitter is enabled for asynchronous address operation by configuring the following control bits:
•
TXEN = 1
•
MODE = 0100
•
UxBRG = desired baud rate
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•
•
•
BRGS = desired baud rate multiplier
RxyPPS = code for desired output pin
ON = 1
Addresses are sent by writing to the UxP1L register. This transmits the written byte with the 9th bit set, which
indicates that the byte is an address.
Data is sent by writing to the UxTXB register. This transmits the written byte with the 9th bit cleared, which indicates
that the byte is data.
To send data to a particular device on the transmission bus, first transmit the address of the intended device. All
subsequent data will be accepted only by that device until an address of another device is transmitted.
Writes to UxP1L take precedence over writes to UxTXB. When both the UxP1L and UxTXB registers are written while
the TSR is busy, the next byte to be transmitted will be from UxP1L.
To ensure all data intended for one device are sent before the address is changed, wait until the TXMTIF bit is high
before writing UxP1L with the new address.
35.2.3.2 Address Mode Receive
The UART receiver is enabled for asynchronous address operation by configuring the following control bits:
•
RXEN = 1
•
MODE = 0100
•
•
•
•
UxBRG = desired baud rate
BRGS = desired baud rate multiplier
RXPPS = code for desired input pin
Input pin ANSEL bit = 0
•
•
•
UxP2L = receiver address
UxP3L = address mask
ON = 1
In Address mode, no data will be transferred to the input FIFO until a valid address is received. This is the default
state. Any of the following conditions will cause the UART to revert to the default state:
•
ON = 0
•
RXEN = 0
•
Received address does not match
When a character with the 9th bit set is received, the Least Significant eight bits of that character will be qualified by
the values in the UxP2L and UxP3L registers.
The byte is XORed with UxP2L then ANDed with UxP3L. A match occurs when the result is 0h, in which case, the
unaltered received character is stored in the receive FIFO, thereby setting the UxRXIF Interrupt bit. The 9th bit is
stored in the corresponding PERIF bit, identifying this byte as an address.
An address match also enables the receiver for all data such that all subsequent characters without the 9th bit set will
be stored in the receive FIFO.
When the 9th bit is set and a match does not occur, the character is not stored in the receive FIFO and all
subsequent data is ignored.
The UxP3L register mask allows a range of addresses to be accepted. Software can then determine the sub-address
of the range by processing the received address character.
35.3
DMX Mode (Full-featured UARTs only)
DMX is a protocol used in stage and show equipment. This includes lighting, fog machines, motors, etc. The protocol
consists of a Controller that sends out commands, and receiver such as theater lights that receive these commands.
The DMX protocol is usually unidirectional, but can be a bidirectional protocol in either Half or Full-Duplex modes.
An example of a Half-Duplex mode is the RDM (Remote Device Management) protocol that sits on DMX512A.
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The Controller transmits commands and the receiver receives them. There are no error conditions or re-transmit
mechanisms.
DMX, or DMX512A as it is known, consists of a “Universe” of 512 channels. This means that one Controller can
output up to 512 bytes on a single DMX link. Each piece of equipment on the line is programmed to listen to a
consecutive sequence of one or more of these bytes.
For example, a fog machine connected to one of the universes may be programmed to receive one byte, starting at
byte number 10, and a lighting unit may be programmed to receive four bytes starting at byte number 22.
35.3.1
DMX Controller
The DMX Controller mode is configured with the following settings:
•
MODE = 1010
•
TXEN = 1
•
RXEN = 0
•
TXPOL = 0
•
•
•
UxP1 = One less than the number of bytes to transmit (excluding the Start code)
UxBRG = Value to achieve 250K baud rate
STP = 10 for two Stop bits
•
•
RxyPPS = TX pin output code
ON = 1
Each DMX transmission begins with a Break followed by a byte called the “Start Code”. The width of the Break is
fixed at 25 bit times. The Break is followed by a “Mark After Break” (MAB) Idle period. After this Idle period, the 1st
through ‘n’th byte is transmitted, where ‘n-1’ is the value in UxP1. See the following figure.
Figure 35-6. DMX Transmit Sequence
Start
Code Byte 1
Byte 2
Byte 3
Rev. 10-000329A
9/5/2017
Start
Code Byte 1
Byte n
Write to UxTXB
TX pin
Break
Start
MAB(1) Code
Byte 1 Byte 2
Byte n
Software
Delay
Break
MAB(1)
Start
Code
UxTXIF
(Transmit Buffer
Reg Empty Flag) bit
TXMTIF (Transmit
Shift Reg Empty
Flag) bit
TXEN
(optional
synchronization) bit
Note 1: The MAB period is fixed at 3 bit times
Software sends the Start Code and the ‘n’ data bytes by writing the UxTXB register with each byte to be sent in the
desired order. A UxTXIF value of ‘1’ indicates when the UxTXB is ready to accept the next byte.
The internal byte counter is not accessible to software. Software needs to keep track of the number of bytes written to
UxTXB to ensure that no more and no less than ‘n’ bytes are sent because the DMX state machine will automatically
insert a Break and reset its internal counter after ‘n’ bytes are written. One way to ensure synchronization between
hardware and software is to toggle TXEN after the last byte of the universe is completely free of the transmit shift
register, as indicated by the TXMTIF bit.
35.3.2
DMX Receiver
The DMX Receiver mode is configured with the following settings:
•
MODE = 1010
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•
TXEN = 0
•
RXEN = 1
•
RXPOL = 0
•
•
•
•
UxP2 = number of first byte to receive
UxP3 = number of last byte to receive
UxBRG = Value to achieve 250K baud rate
STP = 10 for two Stop bits
•
ON = 1
•
•
UxRXPPS = code for desired input pin
Input pin ANSEL bit = 0
When configured as a DMX Receiver, the UART listens for a Break character that is at least 23 bit periods wide. If
the Break is shorter than 23 bit times, the Break is ignored and the DMX state machine remains in Idle mode. Upon
receiving the Break, the DMX counters will be reset to align with the incoming data stream. Immediately after the
Break, the UART will see the “Mark after Break” (MAB). This space is ignored by the UART. The Start Code follows
the MAB and will always be stored in the receive FIFO.
After the Start Code, the 1st through 512th byte will be received, but not all of them are stored in the receive FIFO.
The UART ignores all received bytes until the ones of interest are received. This is done using the UxP2 and UxP3
registers. The UxP2 register holds the value of the byte number to start the receive process. The byte counter starts
at ‘0’ for the first byte after the Start Code. For example, to receive four bytes starting at the 10th byte after the Start
Code, write 009h (9 decimal) to UxP2H:L and 00Ch (12 decimal) to UxP3H:L. The receive FIFO depth is limited,
therefore the bytes must be retrieved by reading UxRXB as they come in to avoid a receive FIFO Overrun condition.
Typically, two Stop bits are inserted between bytes. If either Stop bit is detected as a ‘0’ then the framing error for that
byte will be set.
Since the DMX sequence always starts with a Break, the software can verify that it is in sync with the sequence by
monitoring the RXBKIF flag to ensure that the next byte received after the RXBKIF is processed as the Start Code
and subsequent bytes are processed as the expected data.
35.4
LIN Modes (Full-featured UARTs only)
LIN is a protocol used primarily in automotive applications. The LIN network consists of two kinds of software
processes: a Host process and a Client process. Each network has only one Host process and one or more Client
processes.
From a physical layer point of view, the UART on one processor may be driven by both a Host and a Client process,
as long as only one Host process exists on the network.
A LIN transaction consists of a Host process followed by a Client process. The Client process may involve more
than one client where one is transmitting and the other(s) are receiving. The transaction begins by the following Host
process transmission sequence:
1.
2.
3.
4.
Break
Delimiter bit
Sync Field
PID byte
The PID determines which Client processes are expected to respond to the host. When the PID byte is complete, the
TX output remains in the Idle state. One or more of the Client processes may respond to the Host process. If no one
responds within the inter-byte period, the host is free to start another transmission. The inter-byte period is timed by
software using a means other than the UART.
The Client process follows the Host process. When the client software recognizes the PID then that Client process
responds by either transmitting the required response or by receiving the transmitted data. Only Client processes
send data. Therefore, Client processes receiving data are receiving that of another Client process.
When a client sends data, the client UART automatically calculates the checksum for the transmitted bytes as they
are sent and appends the inverted checksum byte to the client response.
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When a client receives data, the checksum is accumulated on each byte as it is received using the same algorithm
as the sending process. The last byte, which is the inverted checksum value calculated by the sending process, is
added to the locally calculated checksum by the UART. The check passes when the result is all ‘1’s, otherwise the
check fails and the CERIF bit is set.
Two methods for computing the checksum are available: legacy and enhanced. The legacy checksum includes
only the data bytes. The enhanced checksum includes the PID and the data. The C0EN control bit determines the
checksum method. Setting C0EN to ‘1’ selects the enhanced method. Software must select the appropriate method
before the Start bit of the checksum byte is received.
35.4.1
LIN Host/Client Mode
The LIN Host mode includes capabilities to generate client processes. The host process stops at the PID
transmission. Any data that is transmitted in Host/Client mode is done as a client process. LIN Host/Client mode
is configured by the following settings:
•
MODE = 1100
•
TXEN = 1
•
RXEN = 1
•
•
UxBRG = Value to achieve desired baud rate
TXPOL = 0 (for high Idle state)
•
•
•
•
STP = desired Stop bits selection
C0EN = desired Checksum mode
RxyPPS = TX pin selection code
TX pin TRIS control = 0
•
ON = 1
Important: The TXEN bit must be set before the Host process is received and remain set while in LIN
mode whether or not the Client process is a transmitter.
The Host process is started by writing the PID to the UxP1L register when UxP2 is ‘0’ and the UART is Idle. The
UxTXIF will not be set in this case. Only the six Least Significant bits of UxP1L are used in the PID transmission.
The two Most Significant bits of the transmitted PID are PID parity bits. PID[6] is the exclusive-or of PID bits 0, 1, 2,
and 4. PID[7] is the inverse of the exclusive-or of PID bits 1, 3, 4, and 5.
The UART hardware calculates and inserts these bits in the serial stream.
Writing UxP1L automatically clears the UxTXCHK and UxRXCHK registers and generates the Break, the delimiter bit,
the Sync character (55h), and the PID transmission portion of the transaction. The data portion of the transaction that
follows, if there is one, is a Client process. See LIN client Mode for more details of that process. The host receives its
own PID if RXEN is set. Software performs the Client process corresponding to the PID that was sent and received.
Attempting to write UxP1L before an active Host process is complete will not succeed. Instead, the TXWRE bit will be
set.
35.4.2
LIN Client Mode
The LIN Client mode is configured by the following settings:
•
MODE = 1011
•
TXEN = 1
•
RXEN = 1
•
•
•
•
UxP2 = Number of data bytes to transmit
UxP3 = Number of data bytes to receive
UxBRG = Value to achieve default baud rate
TXPOL = 0 (for high Idle state)
•
STP = desired Stop bits selection
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•
•
•
C0EN = desired checksum mode
RxyPPS = TX pin selection code
TX pin TRIS control = 0
•
ON = 1
The Client process starts upon detecting a Break on the RX pin. The Break clears the UxTXCHK, UxRXCHK, UxP2,
and UxP3 registers. At the end of the Break, the auto-baud circuity is activated and the baud rate is automatically set
using the Sync character following the Break. The character following the Sync character is received as the PID code
and is saved in the receive FIFO. The UART computes the two PID parity bits from the six Least Significant bits of
the PID. If either parity bit does not match the corresponding bit of the received PID code, the PERIF flag is set and
saved at the same FIFO location as the PID code. The UxRXIF bit is set indicating that the PID is available.
Software retrieves the PID by reading the UxRXB register and determines the Client process to execute from that.
The checksum method, number of data bytes, and whether to send or receive data, is defined by software according
to the PID code.
35.4.2.1 LIN Client Receiver
When the Client process is a Receiver, the software performs the following tasks:
•
•
•
The UxP3 register is written with a value equal to the number of data bytes to receive.
The C0EN bit is set or cleared to select the appropriate checksum. This must be completed before the Start bit
of the checksum byte is received.
Each byte of the process response is read from UxRXB when UxRXIF is set.
The UART updates the checksum on each received byte. When the last data byte is received, the computed
checksum total is stored in the UxRXCHK register. The next received byte is saved in the receive FIFO and added
with the value in UxRXCHK. The result of this addition is not accessible. However, if the result is not all ‘1’s, the
CERIF bit is set. The CERIF flag persists until cleared by software. Software needs to read UxRXB to remove the
checksum byte from the FIFO, but the byte can be discarded if not needed for any other purpose.
After the checksum is received, the UART ignores all activity on the RX pin until a Break starts the next transaction.
35.4.2.2 LIN Client Transmitter
When the Client process is a transmitter, software performs the following tasks in the order shown:
•
The UxP2 register is written with a value equal to the number of bytes to transmit. This will enable the UxTXIF
flag which is disabled when UxP2 is ‘0’
•
•
The C0EN bit is set or cleared to select the appropriate checksum
Each byte of the process response is written to UxTXB when UxTXIF is set
The UART accumulates the checksum as each byte is written to UxTXB. After the last byte is written, the UART
stores the calculated checksum in the UxTXCHK register and transmits the inverted result as the last byte in the
response.
The UxTXIF flag is disabled when the number of bytes specified by the value in the UxP2 register have been written.
Any writes to UxTXB that exceed the UxP2 count will be ignored and set the TXWRE flag.
35.5
DALI Mode (Full-featured UARTs only)
DALI is a protocol used for intelligent lighting control for building automation. The protocol consists of Control Devices
and Control Gear. A Control Device is an application controller that sends out commands to the light fixtures. The
light fixture itself is termed as a Control Gear. The communication is done using Manchester encoding, which is
performed by the UART hardware.
Manchester encoding consists of the clock and data in a single bit stream (refer to Figure 35-9). A high-to-low or
a low-to-high transition always occurs in the middle of the bit period and may or may not occur at the bit period
boundaries. When the consecutive bits in the bit stream are of the same value (i.e., consecutive ‘1’s or consecutive
‘0’s) a transition occurs at the bit boundary. However, when the bit value changes, there is no transition at the bit
boundary. According to the standard, a half-bit time is typically 416.7 μs long. A double half-bit time or a single bit is
typically 833.3 μs.
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The protocol is inherently half-duplex. Communication over the bus occurs in the form of forward and backward
frames. Wait times between the frames are defined in the standard to prevent collision between the frames.
A Control Device transmission is termed as the forward frame. In the DALI 2.0 standard, a forward frame can be two
or three bytes in length. The two-byte forward frame is used for communication between Control Device and Control
Gear whereas the three-byte forward frame is used for communication between Control Devices on the bus. The first
byte in the forward frame is the control byte and is followed by either one or two data bytes. The transaction begins
when the Control Device starts a transmission. Unlike other protocols, each byte in the frame is transmitted MSb first.
Typical frame timing is shown below.
Figure 35-7. DALI Frame Timing
Control
Code
Control
Code Byte 1
Byte 1
Rev. 10-000331A
9/5/2017
Write to UxTXB
Start bit
TX pin
Stop bits
CC
CC
CC
byte1
Wait Period
Start bit
byte1
UxTXIF
(Transmit Buffer
Reg Empty Flag) bit
TXMTIF (Transmit
Shift Reg Empty
Flag) bit
During the communication between two Control Devices, three bytes are required to be transmitted. In this case, the
software must write the third byte to UxTXB as soon as UxTXIF goes true and before the output shifter becomes
empty. This ensures that the three bytes of the forward frame are transmitted back-to-back without any interruption.
All Control Gear on the bus receive the forward frame. If the forward frame requires a reply to be sent, one of the
Control Gear may respond with a single byte, called the backward frame. The 2.0 standard requires the Control Gear
to begin transmission of the backward frame between 5.5 ms to 10.5 ms (~14 to 22 half-bit times) after reception of
the forward frame. Once the backward frame is received by the Control Device, it is required to wait a minimum of 2.4
ms (~6 half-bit times). After this wait time, the Control Device is free to transmit another forward frame. Refer to the
figure below.
Figure 35-8. DALI Forward/Backward Frame Timing
Rev. 10-000332A
9/7/2017
forward wait period
Device TX
Forward
Frame
forward wait period
Forward
Frame
Gear TX
backward wait period
Forward
Frame
Backward
Frame
Gear UxTXB write
A Start bit is used to indicate the start of the forward and backward frames. When ABDEN = 0, the receiver bit rate
is determined by the BRG register. When ABDEN = 1, the first bit synchronizes the receiver with the transmitter and
sets the receiver bit rate. The low period of the Start bit is measured and is used as the timing reference for all data
bits in the forward and backward frames. The ABDOVF bit is set if the Start bit low period causes the measurement
counter to overflow. All the bits following the Start bit are data bits. The bit stream terminates when no transition is
detected in the middle of a bit period. Refer to the figure below.
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Figure 35-9. Manchester Timing
Rev. 10-000330A
9/5/2017
Byte 0
Byte 1
Byte 0
Write to UxTXB
Start bit
byte 1
byte 0
Stop bits
idle
Start bit
TX pin
UxTXIF
(Transmit Buffer
Reg Empty Flag) bit
TXMTIF (Transmit
Shift Reg Empty
Flag) bit
b7 = 1
b6 = 0
b5 = 0
b4 = 1
b0 = 1
b7 = 0
b6 = 1
b0 = 0
The forward and backward frames are terminated by two Idle bit periods or Stop bits. Normally, these start in the first
bit period of a byte. If both Stop bits are valid, the byte reception is terminated.
If either of the Stop bits is invalid, the frame is tagged as invalid by saving it as a null byte and setting the framing
error in the receive FIFO.
A framing error also occurs when no transition is detected on the bus in the middle of a bit period when the byte
reception is not complete. In such a scenario, the byte will be saved with the FERIF bit set.
35.5.1
Control Device
The Control Device mode is configured with the following settings:
•
MODE = ‘b1000
•
TXEN = 1
•
RXEN = 1
•
•
•
•
UxP1 = Forward frames are held for transmission with this number of half-bit periods after the completion of a
forward or backward frame.
UxP2 = Forward/backward frame threshold delimiter. Any reception that starts this number of half-bit periods
after the completion of a forward or backward frame is detected as forward frame and sets the PERIF flag of the
corresponding received byte.
UxBRG = Value to achieve 1200 baud rate
TXPOL = appropriate polarity for interface circuit
STP = ‘b10 for two Stop bits
•
•
RxyPPS = TX pin selection code
TX pin TRIS control = 0
•
ON = 1
•
A forward frame is initiated by writing the control byte to the UxTXB register. After sending the control byte, each data
byte must be written to the UxTXB register as soon as UxTXIF goes true. It is necessary to perform every write after
UxTXIF goes true, to ensure that the transmit buffer is ready to accept the byte. Each write must also occur before
the TXMTIF bit goes true, to ensure that the bit stream of the forward frame is generated without interruption.
When TXMTIF goes true, indicating the transmit shift register has completed sending the last byte in the frame, the
TX output is held in Idle state for the number of half-bit periods selected by the STP bits.
After the last Stop bit, the TX output is held in the Idle state for an additional wait time determined by the half-bit
period count in the UxP1 register. For example, a 2450 μs delay (~6 half-bit times) requires a value of 6 in UxP1L.
Any writes to the UxTXB register that occur after TXMTIF goes true, but before the UxP1 wait time expires, are held
and then transmitted immediately following the wait time. If a backward frame is received during the wait time, any
bytes that may have been written to UxTXB will be transmitted after completion of the backward frame reception plus
the UxP1 wait time.
The wait timer is reset by the backward frame and starts over immediately following the reception of the Stop bits of
the backward frame. Data pending in the transmit shift register will be sent when the wait time elapses.
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To replace or delete any pending forward frame data, the TXBE bit needs to be set to flush the shift register and
transmit buffer. A new control byte can then be written to the UxTXB register. The control byte will be held in the
buffer and sent at the beginning of the next forward frame following the UxP1 wait time.
In Control Device mode, PERIF is set when a forward frame is received. This helps the software to determine
whether the received byte is part of a forward frame from a Control Device (either from the Control Device under
consideration or from another Control Device on the bus) or a backward frame from a Control Gear.
35.5.2
Control Gear
The Control Gear mode is configured with the following settings:
•
MODE = ‘b1001
•
TXEN = 1
•
RXEN = 1
•
•
•
•
•
UxP1 = Back Frames are held for transmission this number of half-bit periods after the completion of a Forward
Frame.
UxP2 = Forward/Back Frame threshold delimiter. Idle periods longer than this number of half-bit periods are
detected as Forward Frames.
UxBRG = Value to achieve 1200 baud rate
TXPOL = Appropriate polarity for interface circuit
RXPOL = Same as TXPOL
STP = ‘b10 for two Stop bits
•
•
RxyPPS = TX pin output code
TX pin TRIS control = 0
•
•
RXPPS = RX pin selection code
RX pin TRIS control = 1
•
Input pin ANSEL bit = 0
•
ON = 1
•
The UART starts listening for a forward frame when the Control Gear mode is entered. Only the frames that follow
an Idle period longer than UxP2 half-bit periods are detected as forward frames. Backward frames from other Control
Gear are ignored. Only forward frames will be stored in UxRXB. This is necessary because a backward frame can be
sent only as a response to a forward frame.
The forward frame is received one byte at a time in the receive FIFO and retrieved by reading the UxRXB register.
The end of the forward frame starts a timer to delay the backward frame response by a wait time equal to the number
of half-bit periods stored in UxP1.
The data received in the forward frame is processed by the application software. If the application decides to send a
backward frame in response to the forward frame, the value of the backward frame is written to UxTXB. This value is
held for transmission in the transmit shift register until the wait time expires, being transmitted afterwards.
If the backward frame data is written to UxTXB after the wait time has expired, it is held in the UxTXB register until
the end of the wait time following the next forward frame. The TXMTIF bit is false when the backward frame data
is held in the transmit shift register. Receiving a UxRXIF interrupt before the TXMTIF goes true indicates that the
backward frame write was too late and another forward frame was received before sending the backward frame. The
pending backward frame is flushed by setting the TXBE bit to prevent it from being sent after the next forward frame.
35.6
General Purpose Manchester (Full-featured UARTs only)
General purpose Manchester is a subset of the DALI mode. When the UxP1L register is cleared, there is no minimum
wait time between frames. This allows full and half-duplex operation because writes to the UxTXB register are not
held waiting for a receive operation to complete.
General purpose Manchester operation maintains all other aspects of DALI mode as shown in Figure 35-9 such as:
•
•
Single-pulse Start bit
Most Significant bit first
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•
No stop periods between back-to-back bytes
The general purpose Manchester mode is configured with the following settings:
•
MODE = 'b1000
•
TXEN = 1
•
RXEN = 1
•
UxP1 = 0h
•
•
•
•
•
UxBRG = Desired baud rate
TXPOL and RXPOL = Desired Idle state
STP = Desired number of stop periods
RxyPPS = TX pin selection code
TX pin TRIS control = 0
•
•
RXPPS = RX pin selection code
RX pin TRIS control = 1
•
Input pin ANSEL bit = 0
•
ON = 1
The Manchester bit stream timing is shown in Figure 35-9.
35.7
Polarity
Receive and transmit polarity is user selectable and affects all modes of operation.
The idle level is programmable with the TXPOL and RXPOL polarity control bits. Both control bits default to ‘0’, which
selects a high idle level for transmit and receive. The low level Idle state is selected by setting the control bit to ‘1’.
TXPOL controls the TX idle level. RXPOL controls the RX idle level.
35.8
Stop Bits
The number of Stop bits is user selectable with the STP bits. The STP bits affect all modes of operation.
Stop bits selections are shown in the table below:
Table 35-1. Stop Bits Selections
Transmitter Stop bits
Receiver verification
1
Verify Stop bit
1.5
Verify first Stop bit
2
Verify both Stop bits
2
Verify only first Stop bit
In all modes, except DALI, the transmitter is Idle for the number of Stop bit periods between each consecutively
transmitted word. In DALI, the Stop bits are generated after the last bit in the transmitted data stream.
The input is checked for the idle level in the middle of the first Stop bit, when receive verify on first is selected, as well
as in the middle of the second Stop bit, when verify on both is selected. If any Stop bit verification indicates a non-idle
level, the framing error FERIF bit is set for the received word.
35.8.1
Delayed Receive Interrupt
When operating in Half-Duplex mode, where the microcontroller needs to reverse the transceiver direction after a
reception, it may be more convenient to hold off the UxRXIF interrupt until the end of the Stop bits to avoid line
contention. The user selects when the UxRXIF interrupt occurs with the STPMD bit. When STPMD is ‘1’, the UxRXIF
interrupt occurs at the end of the last Stop bit. When STPMD is ‘0’, the UxRXIF interrupt occurs when the received
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byte is stored in the receive FIFO. When STP = 10, the store operation is performed in the middle of the second Stop
bit, otherwise, it is performed in the middle of the first Stop bit.
The FERIF and PERIF interrupts are not delayed with STPMD. When STPMD is set, the preferred indicator for
reversing transceiver direction is the UxRXIF interrupt because it is delayed whereas the others are not.
35.9
Operation After FIFO Overflow
The Receive Shift Register (RSR) can be configured to stop or continue running during a receive FIFO Overflow
condition. Stopped operation is the Legacy mode.
When the RSR continues to run during an Overflow condition, the first word received after clearing the overflow will
always be valid.
When the RSR is stopped during an Overflow condition, the synchronization with the Start bits is lost. Therefore, the
first word received after the overflow is cleared may start in the middle of a word.
Operation during overflow is selected with the RUNOVF bit. When the RUNOVF bit is set, the receiver maintains
synchronization with the Start bits throughout the Overflow condition.
35.10
Receive and Transmit Buffers
The UART uses small buffer areas to transmit and receive data. These are sometimes referred to as FIFOs.
The receiver has a Receive Shift Register (RSR) and two or more buffer registers. The buffer at the top of the FIFO
(earliest byte to enter the FIFO) is by retrieved by reading the UxRXB register.
The transmitter has one or more Transmit Shift Register (TSR) and one buffer register. Writes to UxTXB go to the
transmit buffer then immediately to the TSR, if it is empty. When the TSR is not empty, writes to UxTXB are held then
transferred to the TSR when it becomes available.
35.10.1 FIFO Status
The UxFIFO register contains several Status bits for determining the state of the receive and transmit buffers.
The RXBE bit indicates that the receive FIFO is empty. This bit is essentially the inverse of UxRXIF. The RXBF bit
indicates that the receive FIFO is full.
The TXBE bit indicates that the transmit buffer is empty (same as UxTXIF) and the TXBF bit indicates that the buffer
is full. A third transmitter Status bit, TXWRE (transmit write error), is set whenever a UxTXB write is performed when
the TXBF bit is set. This indicates that the write was unsuccessful.
35.10.2 FIFO Reset
All modes support resetting the receive and transmit buffers.
The receive buffer is flushed and all unread data discarded when the RXBE bit is written to ‘1’. Instead of using a BSF
instruction to set RXBE, the MOVWF instruction with the TXBE bit cleared will be used to avoid inadvertently clearing a
byte pending in the TSR when UxTXB is empty.
Data written to UxTXB when TXEN is low will be held in the Transmit Shift Register (TSR), then sent when TXEN
is set. The transmit buffer and inactive TSR are flushed by setting the TXBE bit. Setting TXBE while a character is
actively transmitting from the TSR will complete the transmission without being flushed.
Clearing the ON bit will discard all received data and transmit data pending in the TSR and UxTXB.
35.11
Flow Control
This section does not apply to the LIN, DALI, or DMX modes.
Flow control is the means by which a sending UART data stream can be suspended by a receiving UART. Flow
control prevents input buffers from overflowing without software intervention. The UART supports both hardware and
XON/XOFF methods of flow control.
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The flow control method is selected with the FLO bits. Flow control is disabled when both bits are cleared.
35.11.1 Hardware Flow Control
The hardware flow control is selected by setting the FLO bits to ‘10’.
The hardware flow control consists of three lines. The RS-232 signal names for two of these are RTS, and CTS.
Both are low true. The third line is called TXDE for transmit drive enable which may be used to control an RS-485
transceiver. This output is high when the TX output is actively sending a character and low at all other times. The
UART is configured as DTE (computer) equipment which means RTS is an output and CTS is an input.
The RTS and CTS signals work as a pair to control the transmission flow. A DTE-to-DTE configuration connects the
RTS output of the receiving UART to the CTS input of the sending UART. Refer to the following figure.
Figure 35-10. Hardware Flow Control Connections
Rev. 10-000333A
1/11/2019
UART 1
RX
RTS
TX
CTS
UART 2
TX
CTS
RX
RTS
The UART receiving data asserts the RTS output low when the input FIFO is empty. When a character is received,
the RTS output goes high until the UxRXB is read to free up both FIFO locations.
When the CTS input goes high after a byte has started to transmit, the transmission will complete normally. The
receiver accommodates this by accepting the character in the second FIFO location even when the CTS input is high.
35.11.2 RS-485 Transceiver Control
The hardware flow control can be used to control the direction of an RS-485 transceiver as shown in the
following figure. The CTS input will be configured to be always enabled by setting the UxCTSPPS selection to
an unimplemented PORT pin, such as RD0. When the signal and control lines are configured as shown in the figure
below, the UART will not receive its own transmissions. To verify that there are no collisions on the RS-485 lines,
the transceiver RE control can be disconnected from TXDE and tied low, thereby enabling loopback reception of all
transmissions. See Collision Detection for more information.
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Figure 35-11. RS-485 Configuration
Rev. 10-000334A
9/6/2017
UART
SN75176
Vcc
R
RX
RE
TXDE
4k7
A
DE B
D
TX
CTS(1)
4k7
Gnd
Note 1: Configure UxCTSPPS to an
unimplemented input such as RD0.
(e.g. UxCTSPPS = 0x18)
35.11.3 XON/XOFF Flow Control
XON/XOFF flow control is selected by setting the FLO bits to ‘01’.
XON/XOFF is a data-based flow control method. The signals to suspend and resume transmission are special
characters sent by the receiver to the transmitter. The advantage is that additional hardware lines are not needed.
XON/XOFF flow control requires full-duplex operation because the transmitter must be able to receive the signal to
suspend transmitting while the transmission is in progress. Although XON and XOFF are not defined in the ASCII
code, the generally accepted values are 13h for XOFF and 11h for XON. The UART uses those codes.
The transmitter defaults to XON, or transmitter enabled. This state is also indicated by the read-only XON bit.
When an XOFF character is received, the transmitter stops transmitting after completing the character actively being
transmitted. The transmitter remains disabled until an XON character is received.
XON will be forced on when software toggles the TXEN bit.
When the RUNOVF bit is set, the XON and XOFF characters continue to be received and processed without the
need to clear the input FIFO by reading UxRXB. However, if the RUNOVF bit is clear then UxRXB must be read to
avoid a receive overflow which will suspend flow control when the receive buffer overflows.
35.12
Checksum (Full-featured UARTs only)
This section does not apply to the LIN mode, which handles checksums automatically.
The transmit and receive checksum adders are enabled when the C0EN bit is set. When enabled, the adders
accumulate every byte that is transmitted or received. The accumulated sum includes the carry of the addition.
Software is responsible for clearing the checksum registers before a transaction and performing the check at the end
of the transaction.
The following examples illustrate how the checksum registers can be used in the Asynchronous modes.
35.12.1 Transmit Checksum Method
1.
2.
3.
4.
Clear the UxTXCHK register.
Set the C0EN bit.
Send all bytes of the transaction output.
Invert UxTXCHK and send the result as the last byte of the transaction.
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35.12.2 Receive Checksum Method
1.
2.
3.
4.
5.
Clear the UxRXCHK register.
Set the C0EN bit.
Receive all bytes in the transaction including the checksum byte.
Set MSb of UxRXCHK if 7-bit mode is selected.
Add ‘1’ to UxRXCHK.
6.
If the result is ‘0’, the checksum passes, otherwise it fails.
The CERIF Checksum Interrupt flag is not active in any mode other than LIN.
35.13
Collision Detection (Full-featured UARTs only)
External forces that interfere with the transmit line are detected in all modes of operation with collision detection.
Collision detection is always active when RXEN and TXEN are both set. When the receive input is connected to the
transmit output through either the same I/O pin or external circuitry, a character will be received for every character
transmitted. The collision detection circuit provides a warning when the word received does not match the word
transmitted.
The TXCIF flag is used to signal collisions. This signal is only useful when the TX output is looped back to the RX
input and everything that is transmitted is expected to be received. If more than one transmitter is active at the same
time, it can be assumed that the TX word will not match the RX word. The TXCIF detects this mismatch and flags an
interrupt. The TXCIF bit will also be set in DALI mode transmissions when the received bit is missing the expected
mid-bit transition.
Collision detection is always active, regardless of whether or not the RX input is connected to the TX output. It is up
to the user to disable the TXCIE bit when collision interrupts are not required. The software overhead of unloading
the receive buffer of transmitted data is avoided by setting the RUNOVF bit and ignoring the receive interrupt and
letting the receive buffer overflow. When the transmission is complete, prepare for receiving data by flushing the
receive buffer (see FIFO Reset) and clearing the RXFOIF overflow flag.
35.14
RX/TX Activity Time-out
The UART works in conjunction with the HLT timers to monitor activity on the RX and TX lines. Use this feature to
determine when there has been no activity on the receive or transmit lines for a user-specified period of time.
To use this feature, set the HLT to the desired time-out period by a combination of the HLT clock source, timer
prescale value, and timer period registers. Configure the HLT to reset on the UART TX or RX line and start the HLT
at the same time the UART is started. UART activity will keep resetting the HLT to prevent a full HLT period from
elapsing. When there has been no activity on the selected TX or RX line for longer than the HLT period, then an HLT
interrupt will occur signaling the time-out event.
For example, the following register settings will configure HLT2 for a 5 ms time-out of no activity on U1RX:
• T2PR = 0x9C (156 prescale periods)
•
35.15
T2CLKCON = 0x05 (500 kHz internal oscillator)
•
T2HLT = 0x04 (free-running, reset on rising edge)
•
T2RST = 0x15 (Reset on U1RX)
•
T2CON = 0xC0 (Timer2 on with 1:16 prescale)
Clock Accuracy With Asynchronous Operation
The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as
VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to
adjust the baud rate clock, but both require a reference clock source of some kind.
The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output. Adjusting the value of the
OSCTUNE register allows for fine resolution changes to the system clock source. See “HFINTOSC Frequency
Tuning” for more information.
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The other method adjusts the value of the Baud Rate Generator. This can be done automatically with the Auto-Baud
Detect feature (see Auto-Baud Detect). There may not be fine enough resolution when adjusting the Baud Rate
Generator to compensate for a gradual change of the peripheral clock frequency.
35.16
UART Baud Rate Generator
The Baud Rate Generator (BRG) is a 16-bit timer that is dedicated to the support of the UART operation. The UxBRG
register pair determines the period of the free running baud rate timer. The multiplier of the baud rate period is
determined by the BRGS bit.
The high baud rate range (BRGS = 1) is intended to extend the baud rate range up to a faster rate when the desired
baud rate is not possible otherwise and to improve the baud rate resolution at high baud rates. Using the normal
baud rate range (BRGS = 0) is recommended when the desired baud rate is achievable with either range.
Important: BRGS = 1 is not supported in the DALI mode.
Writing a new value to UxBRG causes the BRG timer to be reset (or cleared). This ensures that the BRG does not
wait for a timer overflow before outputting the new baud rate.
If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid
this problem, check the status of the RXIDL bit to make sure that the receive operation is Idle before changing the
system clock. The following table contains formulas for determining the baud rate.
Table 35-2. Baud Rate Formulas
BRGS
BRG/UART Mode
Baud Rate Formula
1
High Rate
Fosc/[4(UxBRG+1)]
0
Normal Rate
Fosc/[16(UxBRG+1)]
The following example provides a sample calculation for determining the baud rate and baud rate error.
Example 35-1. Baud Rate Error Calculation
For a device with Fosc of 16 MHz, desired baud rate of 9600, Asynchronous mode, and BRGS = 0.
DesiredBaudrate =
Solving for UxBRG:
UxBRG =
FOSC
16 × UxBRG + 1
FOSC
−1
16 × DesiredBaudrate
UxBRG = 16000000 − 1
16 × 9600
UxBRG = 103.17 ≃ 103
CalculatedBaudrate =
16000000
16 × 103 + 1
CalculatedBaudrate = 9615
Error = CalculatedBaudrate − DesiredBaudrate
DesiredBaudrate
Error = 9615 − 9600
9600
Error ≃ 0.16 %
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35.16.1 Auto-Baud Detect
The UART module supports automatic detection and calibration of the baud rate in the 8-bit asynchronous and LIN
modes. However, setting ABDEN to start auto-baud detection is neither necessary, nor possible in LIN mode because
that mode supports auto-baud detection automatically at the beginning of every data packet. Enabling auto-baud
detect with the ABDEN bit applies to the asynchronous modes only.
When Auto-Baud Detect (ABD) is active, the clock to the BRG is reversed. Rather than the BRG clocking the
incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a
received 55h (ASCII “U”), which is the Sync character for the LIN bus. The unique feature of this character is that it
has five falling edges, including the Start bit edge, and five rising edges, including the Stop bit edge.
In 8-bit Asynchronous mode, setting the ABDEN bit enables the auto-baud calibration sequence. The first falling edge
of the RX input after ABDEN is set will start the auto-baud calibration sequence. While the ABD sequence takes
place, the UART state machine is held in Idle. On the first falling edge of the receive line, the UxBRG begins counting
up using the BRG counter clock, as shown in the following figure. The fifth falling edge will occur on the RX pin at the
beginning of the bit 7 period. At that time, an accumulated value totaling the proper BRG period is left in the UxBRG
register pair, the ABDEN bit is automatically cleared and the ABDIF interrupt flag is set. ABDIF must be cleared by
software.
Figure 35-12. Automatic Baud Rate Calibration
Rev. 10-000120B
9/6/2017
BRG Value
XXXXh
0000h
001Ch
Edge #2
Edge #1
RX pin
Edge #3
Edge #4
Edge #5
start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
BRG Clock
ABDEN
Set by user in 8-bit mode
Auto cleared
RXIDL
Cleared by
software
ABDIF
(Interrupt Flag) bit
UxBRG
XXXXh
001Ch
RXIDL indicates that the sync input is active. RXIDL will go low on the first falling edge and go high on the fifth rising
edge.
The BRG auto-baud clock is determined by the BRGS bit, as shown in the following table.
Table 35-3. BRG Counter Clock Rates
BRGS
BRG Base Clock
BRG ABD Clock
1
Fosc/4
Fosc/32
0
Fosc/16
Fosc/128
During ABD, the internal BRG register is used as a 16-bit counter. However, the UxBRG registers retain the previous
BRG value until the auto-baud process is successfully completed. While calibrating the baud rate period, the internal
BRG register is clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time
when clocked at full speed and is transferred to the UxBRG registers when complete.
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Important:
1. When both the WUE and ABDEN bits are set, the auto-baud detection will occur on the byte
following the Break character (see Auto Wake-on-Break).
2. It is up to the user to verify the incoming character baud rate is within the range of the selected BRG
clock source. Some combinations of oscillator frequency and UART baud rates are not possible.
35.16.2 Auto-Baud Overflow
During the course of automatic baud detection, the ABDOVF bit will be set if the baud rate counter overflows before
the fifth falling edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the
maximum count that can fit in the 16 bits of the UxBRG register pair. After the ABDOVF bit has been set, the state
machine continues to search until the fifth falling edge is detected on the RX pin. Upon detecting the fifth falling RX
edge, the hardware will set the ABDIF Interrupt flag and clear the ABDEN bit. The UxBRG register values retain their
previous value. The ABDIF flag and ABDOVF flag can be cleared by software directly. To generate an interrupt on an
Auto-baud Overflow condition, all the following bits must be set:
• ABDOVE bit
• UxEIE bit in the PIEx register
• Global Interrupt Enable bits
To terminate the auto-baud process before the ABDIF flag is set, clear the ABDEN bit, then clear the ABDOVF bit.
35.16.3 Auto Wake-on-Break
During Sleep mode, all clocks to the UART are suspended. Because of this, the Baud Rate Generator is inactive and
a proper character reception cannot be performed. The Auto Wake-on-Break feature allows the controller to wake up
due to activity on the RX line.
The Auto Wake-up feature is enabled by setting both the WUE bit and the UxIE bit in the PIEx register. Once set, the
normal receive sequence on RX is disabled, and the UART remains in an Idle state, monitoring for a wake-up event
independent of the CPU mode. A wake-up event consists of a transition out of the Idle state on the RX line. (This
coincides with the start of a Break or a wake-up signal character for the LIN protocol.)
The UART module generates a WUIF interrupt coincident with the wake-up event. The interrupt is generated
synchronously to the Q clocks in normal CPU operating modes (Figure 35-13), and asynchronously, if the device
is in Sleep mode (Figure 35-14). The Interrupt condition is cleared by clearing the WUIF bit.
Figure 35-13. Auto Wake-Up Timing During Normal Operation
Rev. 10-000326B
1/11/2019
q1
q2
q3
q4
q1
q2
q3
q4
q1
q2
q3
q4
q1
q2
q3
q4
q1
q2
q3
q4
q1
q2
q3
q4
q1
q2
q3
q4
q1
q2
q3
q4
FOSC
WUE bit
Bit set by user
Auto cleared
RX line
WUIF
Cleared by software
Note 1: The UART remains in Idle while the WUE bit is set.
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Figure 35-14. Auto Wake-Up Timing During Sleep
Rev. 10-000327B
9/6/2017
q1
q2
q3
q4
q1
q2
q3
q4
q2
q1
q3
q4
q1
q2
q3
q4
q1
q2
q3
q4
q1
q2
q3
q4
FOSC
WUE bit
Bit set by user
Auto cleared
RX line
WUIF
Cleared by software
Sleep command executed
Sleep ends
Note 1: The UART remains in idle while the WUE bit is set.
To generate an interrupt on a wake-up event, all the following bits must be set:
• UxIE bit in the PIEx register
• Global interrupt enables
The WUE bit is automatically cleared by the transition to the Idle state on the RX line at the end of the Break. This
signals to the user that the Break event is over. At this point, the UART module is in Idle mode, waiting to receive the
next character.
35.16.3.1 Auto Wake-Up Special Considerations
Break Character
To avoid character errors or character fragments during a wake-up event, all bits in the character causing the Wake
event must be zero.
When the wake-up is enabled, the function works independent of the low time on the data stream. If the WUE
bit is set and a valid non-zero character is received, the low time from the Start bit to the first rising edge will be
interpreted as the wake-up event. The remaining bits of the character will be received as a fragmented character and
subsequent characters can result in framing or overrun errors.
Therefore, the initial character of the transmission must be all zeros. This must be eleven or more bit times, 13 bit
times recommended for LIN bus, or any number of bit times for standard RS-232 devices.
Oscillator Start-up Time
The oscillator start-up time must be considered, especially in applications using oscillators with longer start-up
intervals (i.e., LP, XT or HS/PLL modes). The Sync Break (or wake-up signal) character must be of sufficient length,
and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper
initialization of the UART.
The WUE Bit
To ensure that no actual data is lost, check the RXIDL bit to verify that a receive operation is not in process before
setting the WUE bit. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the
Sleep mode.
35.17
Transmitting a Break
The UART module has the capability of sending either a fixed length Break period or a software-timed Break period.
The fixed length Break consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. The software-timed Break is
generated by setting and clearing the BRKOVR bit.
To send the fixed length Break, set the SENDB and TXEN bits. The Break sequence is then initiated by a write to
UxTXB. The timed Break will occur first, followed by the character written to UxTXB that initiated the Break. The
initiating character is typically the Sync character of the LIN specification.
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SENDB is disabled in the LIN and DMX modes because those modes generate the Break sequence automatically.
The SENDB bit is automatically reset by hardware after the Break Stop bit is complete.
The TXMTIF bit indicates when the transmit operation is Active or Idle, just as it does during normal transmission.
The following figure illustrates the Break sequence.
Figure 35-15. Send-Break Sequence
Sync
Write
Rev. 10-000118B
9/6/2017
Write to UxTXB
BRG Output
(Shift Clock)
TX pin
Start bit
bit 0
bit 1
Stop bit
Sync
start
Break
UxTXIF
(Transmit Buffer
Reg Empty Flag) bit
TXMTIF (Transmit
Shift Reg Empty
Flag) bit
SENDB
(send break
control bit)
35.18
bit 11
Auto cleared
Receiving a Break
The UART has counters to detect when the RX input remains in the Space state for an extended period of time.
When this happens, the RXBKIF bit is set.
A Break is detected when the RX input remains in the Space state for 11 bit periods for asynchronous and LIN
modes, and 23 bit periods for DMX mode.
The user can select to receive the Break interrupt as soon as the Break is detected or at the end of the Break,
when the RX input returns to the Idle state. When the RXBIMD bit is ‘1’, then RXBKIF is set immediately upon Break
detection. When RXBIMD is ‘0’, then RXBKIF is set when the RX input returns to the Idle state.
35.19
UART Operation During Sleep
The UART ceases to operate during Sleep. The safe way to wake the device from Sleep by a serial operation is to
use the Wake-on-Break feature of the UART. See Auto Wake-on-Break.
35.20
Register Definitions: UART
Long bit name prefixes for the UART peripherals are shown in the following table. Refer to the “Long Bit Names”
section in the “Register and Bit Naming Conventions” chapter for more information.
Table 35-4. UART Long Bit Name Prefixes
Peripheral
Bit Name Prefix
UART1 (full featured)
U1
UART2 (full featured)
U2
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...........continued
Peripheral
Bit Name Prefix
UART3 (limited features)
U3
UART4 (limited features)
U4
UART5 (limited features)
U5
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35.20.1 UxCON0
Name:
Address:
UxCON0
0x2AB,0x2BE,0x2D1,0x2E4,0x2F7
UART Control Register 0
Bit
7
BRGS
R/W
0
Access
Reset
6
ABDEN
R/W
0
5
TXEN
R/W
0
4
RXEN
R/W
0
3
2
1
0
R/W
0
R/W
0
MODE[3:0]
R/W
0
R/W
0
Bit 7 – BRGS Baud Rate Generator Speed Select
Value
Description
1
Baud Rate Generator is high speed with 4 baud clocks per bit
0
Baud Rate Generator is normal speed with 16 baud clocks per bit
Bit 6 – ABDEN Auto-baud Detect Enable(3)
Value
Description
1
Auto-baud is enabled. Receiver is waiting for Sync character (0x55)
0
Auto-baud is not enabled or auto-baud is complete
Bit 5 – TXEN Transmit Enable Control(2)
Value
Description
1
Transmit is enabled. TX output pin drive is forced on when transmission is active, and controlled by
PORT TRIS control when transmission is Idle.
0
Transmit is disabled. TX output pin drive is controlled by PORT TRIS control
Bit 4 – RXEN Receive Enable Control(2)
Value
Description
1
Receiver is enabled
0
Receiver is disabled
Bits 3:0 – MODE[3:0] UART Mode Select(1)
Value
Description
1111-110 Reserved
1
1100
LIN Host/Client mode(4)
1011
LIN Client-Only mode(4)
1010
DMX mode(4)
1001
DALI Control Gear mode(4)
1000
DALI Control Device mode(4)
0111-010 Reserved
1
0100
Asynchronous 9-bit UART Address mode. 9th bit: 1 = address, 0 = data
0011
Asynchronous 8-bit UART mode with 9th bit even parity
0010
Asynchronous 8-bit UART mode with 9th bit odd parity
0001
Asynchronous 7-bit UART mode
0000
Asynchronous 8-bit UART mode
Notes:
1. Changing the UART MODE while ON = 1 may cause unexpected results.
2.
3.
Clearing TXEN or RXEN will not clear the corresponding buffers. Use TXBE or RXBE to clear the buffers.
ABDEN is read-only when MODE > 'b0111.
4.
Full-featured UARTs only.
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35.20.2 UxCON1
Name:
Address:
UxCON1
0x2AC,0x2BF,0x2D2,0x2E5,0x2F8
UART Control Register 1
Bit
Access
Reset
7
ON
R/W
0
6
5
4
WUE
R/W/HC
0
3
RXBIMD
R/W
0
2
1
BRKOVR
R/W
0
0
SENDB
R/W/HC
0
Bit 7 – ON Serial Port Enable
Value
Description
1
Serial port enabled
0
Serial port disabled (held in Reset)
Bit 4 – WUE Wake-up Enable
Value
Description
1
Receiver is waiting for falling RX input edge which will set the UxIF bit. Cleared by hardware on
wake-up event. Also requires UxIE bit of PIEx to enable wake
0
Receiver operates normally
Bit 3 – RXBIMD Receive Break Interrupt Mode Select
Value
Description
1
Set RXBKIF immediately when RX in has been low for the minimum Break time
0
Set RXBKIF on rising RX input after RX in has been low for the minimum Break time
Bit 1 – BRKOVR Send Break Software Override
Value
Description
1
TX output is forced to non-Idle state
0
TX output is driven by transmit shift register
Bit 0 – SENDB Send Break Control(1)
Value
Description
1
Output Break upon UxTXB write. Written byte follows Break. Bit is cleared by hardware.
0
Break transmission completed or disabled
Note:
1. This bit is read-only in LIN, DMX, and DALI modes.
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35.20.3 UxCON2
Name:
UxCON2
UART Control Register 2
Bit
Access
Reset
7
RUNOVF
R/W
0
6
RXPOL
R/W/HC
0
5
4
STP[1:0]
R/W
0
R/W
0
3
C0EN
R/W
0
2
TXPOL
R/W
0
1
0
FLO[1:0]
R/W
0
R/W
0
Bit 7 – RUNOVF Run During Overflow Control
Value
Description
1
RX input shifter continues to synchronize with Start bits after Overflow condition
0
RX input shifter stops all activity on receiver Overflow condition
Bit 6 – RXPOL Receive Polarity Control
Value
Description
1
Invert RX polarity, Idle state is low
0
RX polarity is not inverted, Idle state is high
Bits 5:4 – STP[1:0] Stop Bit Mode Control(1)
Value
Description
11
Transmit 2 Stop bits, receiver verifies first Stop bit
10
Transmit 2 Stop bits, receiver verifies first and second Stop bits
01
Transmit 1.5 Stop bits, receiver verifies first Stop bit
00
Transmit 1 Stop bit, receiver verifies first Stop bit
Bit 3 – C0EN Checksum Mode Select(2)
Value
Condition
Description
1
MODE = LIN
Enhanced LIN checksum includes PID in sum
0
MODE = LIN
Legacy LIN checksum does not include PID in sum
1
MODE = not LIN
Checksum is the sum of all TX and RX characters
0
MODE = not LIN
Checksum is disabled
Bit 2 – TXPOL Transmit Control Polarity(1)
Value
Description
1
Output data is inverted, TX output is low in Idle state
0
Output data is not inverted, TX output is high in Idle state
Bits 1:0 – FLO[1:0] Handshake Flow Control
Value
Description
11
Reserved
10
RTS/CTS and TXDE Hardware flow control
01
XON/XOFF Software flow control
00
Flow control is off
Notes:
1. All modes transmit selected number of Stop bits.
2. Full-featured UARTs only.
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35.20.4 UxERRIR
Name:
UxERRIR
UART Error Interrupt Flag Register
Bit
Access
Reset
7
TXMTIF
R/S/C
1
6
PERIF
R/W/HC
0
5
ABDOVF
R/W/S
0
4
CERIF
R/W/S
0
3
FERIF
R/S/C
0
2
RXBKIF
R/W/S
0
1
RXFOIF
R/W/S
0
0
TXCIF
R/W/S
0
Bit 7 – TXMTIF Transmit Shift Register Empty Interrupt Flag
Value
Description
1
Transmit shift register is empty (Set at end of Stop bits)
0
Transmit shift register is actively shifting data
Bit 6 – PERIF Parity Error Interrupt Flag
Value
Condition
1
MODE = LIN or Parity
0
MODE = LIN or Parity
1
MODE = DALI Device
0
MODE = DALI Device
1
MODE = Address
0
MODE = Address
x
MODE = All others
Description
Unread byte at top of input FIFO has parity error
Unread byte at top of input FIFO does not have parity error
Unread byte at top of input FIFO received as Forward Frame
Unread byte at top of input FIFO received as Back Frame
Unread byte at top of input FIFO received as address
Unread byte at top of input FIFO received as data
Not used
Bit 5 – ABDOVF Auto-baud Detect Overflow Interrupt Flag
Value
Condition
Description
1
MODE = DALI
Start bit measurement overflowed counter
0
MODE = DALI
No overflow during Start bit measurement
1
MODE = All others
Baud Rate Generator overflowed during the auto-detection sequence
0
MODE = All others
Baud Rate Generator has not overflowed
Bit 4 – CERIF Checksum Error Interrupt Flag
Value
Condition
1
MODE = LIN
0
MODE = LIN
x
MODE = not LIN
Description
Checksum error
No checksum error
Not used
Bit 3 – FERIF Framing Error Interrupt Flag
Value
Description
1
Unread byte at top of input FIFO has framing error
0
Unread byte at top of input FIFO does not have framing error
Bit 2 – RXBKIF Break Reception Interrupt Flag
Value
Description
1
Break detected
0
No break detected
Bit 1 – RXFOIF Receive FIFO Overflow Interrupt Flag
Value
Description
1
Receive FIFO has overflowed
0
Receive FIFO has not overflowed
Bit 0 – TXCIF Transmit Collision Interrupt Flag(1)
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Value
1
0
Description
Transmitted word is not equal to the word received during transmission
Transmitted word equals the word received during transmission
Note:
1. Full-featured UARTs only.
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35.20.5 UxERRIE
Name:
UxERRIE
UART Error Interrupt Enable Register
Bit
Access
Reset
7
TXMTIE
R/W
0
6
PERIE
R/W
0
5
ABDOVE
R/W
0
4
CERIE
R/W
0
3
FERIE
R/W
0
2
RXBKIE
R/W
0
1
RXFOIE
R/W
0
0
TXCIE
R/W
0
Bit 7 – TXMTIE Transmit Shift Register Empty Interrupt Enable
Value
Description
1
Interrupt enabled
0
Interrupt not enabled
Bit 6 – PERIE Parity Error Interrupt Enable
Value
Description
1
Interrupt enabled
0
Interrupt not enabled
Bit 5 – ABDOVE Auto-baud Detect Overflow Interrupt Enable
Value
Description
1
Interrupt enabled
0
Interrupt not enabled
Bit 4 – CERIE Checksum Error Interrupt Enable
Value
Description
1
Interrupt enabled
0
Interrupt not enabled
Bit 3 – FERIE Framing Error Interrupt Enable
Value
Description
1
Interrupt enabled
0
Interrupt not enabled
Bit 2 – RXBKIE Break Reception Interrupt Enable
Value
Description
1
Interrupt enabled
0
Interrupt not enabled
Bit 1 – RXFOIE Receive FIFO Overflow Interrupt Enable
Value
Description
1
Interrupt enabled
0
Interrupt not enabled
Bit 0 – TXCIE Transmit Collision Interrupt Enable(1)
Value
Description
1
Interrupt enabled
0
Interrupt not enabled
Note:
1. Full-featured UARTs only.
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35.20.6 UxUIR
Name:
Address:
UxUIR
0x2B1,0x2C4,0x2D7,0x2EA,0x2FD
UART General Interrupt Flag Register
Bit
Access
Reset
7
WUIF
R/W/S
0
6
ABDIF
R/W/S
0
5
4
3
2
ABDIE
R/W
0
1
0
Bit 7 – WUIF Wake-up Interrupt
Value
Description
1
Idle to non-Idle transition on RX line detected when WUE is set. Also sets UxIF. (WUIF must be cleared
by software to clear UxIF)
0
WUE not enabled by software or no transition detected
Bit 6 – ABDIF Auto-baud Detect Interrupt
Value
Description
1
Auto-baud detection complete. Status shown in UxIF when ABDIE is set. (Must be cleared by software)
0
Auto-baud not enabled or auto-baud enabled and auto-baud detection not complete
Bit 2 – ABDIE Auto-baud Detect Interrupt Enable
Value
Description
1
ABDIF will set UxIF bit in PIRx register
0
ABDIF will not set UxIF
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35.20.7 UxFIFO
Name:
Address:
UxFIFO
0x2B0,0x2C3,0x2D6,0x2E9,0x2FC
UART FIFO Status Register
Bit
Access
Reset
7
TXWRE
R/W/S
0
6
STPMD
R/W
0
5
TXBE
R/W/S/C
1
4
TXBF
R/S/C
0
3
RXIDL
R/S/C
1
2
XON
S/C
1
1
RXBE
R/W/S/C
1
0
RXBF
R/S/C
0
Bit 7 – TXWRE Transmit Write Error Status (must be cleared by software)
Value
Condition
Description
1
MODE = LIN Host
UxP1L was written when a host process was active
1
MODE = LIN Client
UxTXB was written when UxP2 = 0 or more than UxP2 bytes have been
written to UxTXB since last Break
1
MODE = Address detect UxP1L was written before the previous data in UxP1L was transferred to TX
shifter
1
MODE = All
A new byte was written to UxTXB when the output FIFO was full
0
MODE = All
No error
Bit 6 – STPMD Stop Bit Detection Mode
Value
Condition
Description
1
STP = 11
Assert UxRXIF at end of first Stop bit
1
STP≠ 11
Assert UxRXIF at end of last Stop bit
0
STP = xx
Assert UxRXIF in middle of first Stop bit
Bit 5 – TXBE Transmit Buffer Empty Status
Value
Description
1
Transmit buffer is empty. Setting this bit will clear the transmit buffer and output shift register.
0
Transmit buffer is not empty. Software cannot clear this bit.
Bit 4 – TXBF Transmit Buffer Full Status
Value
Description
1
Transmit buffer is full
0
Transmit buffer is not full
Bit 3 – RXIDL Receive Pin Idle Status
Value
Description
1
Receive pin is in Idle state
0
UART is receiving Start, Stop, Data, Auto-baud, or Break
Bit 2 – XON Software Flow Control Transmit Enable Status
Value
Description
1
Transmitter is enabled
0
Transmitter is disabled
Bit 1 – RXBE Receive Buffer Empty Status
Value
Description
1
Receive buffer is empty. Setting this bit will clear the RX buffer(1)
0
Receive buffer is not empty. Software cannot clear this bit.
Bit 0 – RXBF Receive Buffer Full Status
Value
Description
1
Receive buffer is full
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Value
0
Description
Receive buffer is not full
Note:
1. The BSF instruction will not be used to set RXBE because doing so will clear a byte pending in the transmit
shift register when the UxTXB register is empty. Instead, use the MOVWF instruction with a ‘0’ in the TXBE bit
location.
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35.20.8 UxBRG
Name:
Address:
UxBRG
0x2AE,0x2C1,0x2D4,0x2E7,0x2FA
UART Baud Rate Generator
Bit
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BRG[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
BRG[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – BRG[15:0] Baud Rate Generator Value
The UART Baud Rate equals [Fosc*(1+(BRGS*3)]/[(16*(BRG-1))]
Notes:
1. The individual bytes in this multi-byte register can be accessed with the following register names:
– UxBRGH: Accesses the high byte BRG[15:8]
– UxBRGL: Accesses the low byte BRG[7:0]
2. The UxBRG registers will only be written when ON = 0.
3.
Maximum BRG value when MODE = '100x and BRGS = 1 is 0x7FFE.
4.
Maximum BRG value when MODE = '100x and BRGS = 0 is 0x1FFE.
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35.20.9 UxRXB
Name:
Address:
UxRXB
0x2A1,0x2B4,0x2C7,0x2DA,0x2ED
UART Receive Register
Bit
7
6
5
4
3
2
1
0
R
x
R
x
R
x
R
x
RXB[7:0]
Access
Reset
R
x
R
x
R
x
R
x
Bits 7:0 – RXB[7:0] Top of Receive FIFO
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35.20.10 UxTXB
Name:
Address:
UxTXB
0x2A3,0x2B6,0x2C9,0x2DC,0x2EF
UART Transmit Register
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TXB[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – TXB[7:0] Bottom of Transmit FIFO
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35.20.11 UxP1
Name:
UxP1
UART Parameter 1
Bit
15
14
13
12
7
6
5
4
11
10
9
8
P1[8]
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
P1[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit 8 – P1[8] Parameter 1 Most Significant bit
UART mode operating parameter values
Value
Condition
Description
n
MODE = DMX
Most Significant bit of number of bytes to transmit between Start Code
and automatic Break generation
n
MODE = DALI Control
Most Significant bit of Idle time delay after which a Forward Frame is
Device
sent. Measured in half-bit periods
n
MODE = DALI Control Gear Most Significant bit of delay between the end of a Forward Frame and
the start of the Back Frame Measured in half-bit periods
x
All other modes/Limited
Not used
featured UART
Bits 7:0 – P1[7:0] Parameter 1 Least Significant bits
UART mode operating parameter values
Value
Condition
Description
n
MODE = DMX
Least Significant bits of number of bytes to transmit between Start
Code and automatic Break generation
n
MODE = DALI Control Device Least Significant bits of Idle time delay after which a Forward Frame is
sent. Measured in half-bit periods
n
MODE = DALI Control Gear
Least Significant bits of delay between the end of a Forward Frame
and the start of the Back Frame Measured in half-bit periods
n
MODE = LIN
PID to transmit (Only Least Significant 6 bits used)
n
MODE = Asynchronous
Address to transmit (9th transmit bit automatically set to ‘1’)
Address
x
All other modes
Not used
Notes: The individual bytes in this multi-byte register can be accessed with the following register names:
• UxP1H: Accesses the high byte P1[8]
• UxP1L: Accesses the low byte P1[7:0]
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 644
PIC18F27/47/57Q84
UART - Universal Asynchronous Receiver Tra...
35.20.12 UxP2
Name:
UxP2
UART Parameter 2
Bit
15
14
13
12
7
6
5
4
11
10
9
8
P2[8]
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
P2[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bit 8 – P2[8] Parameter 2 Most Significant bit
UART mode operating parameter values
Value
Condition
n
MODE = DMX
n
MODE = DALI
x
All other modes/Limited featured
UART
R/W
0
Description
Most Significant bit of first address of receive block
Most Significant bit of number of half-bit periods of Idle time in
Forward Frame detection threshold
Not used
Bits 7:0 – P2[7:0] Parameter 2 Least Significant bits
UART mode operating parameter values
Value
Condition
Description
n
MODE = DMX
Least Significant bits of first address of receive block
n
MODE = DALI
Least Significant bits of number of half-bit periods of Idle time in
Forward Frame detection threshold
n
MODE = LIN
Number of data bytes to transmit
n
MODE = Asynchronous Address Receiver address
x
All other modes
Not used
Notes: The individual bytes in this multi-byte register can be accessed with the following register names:
• UxP2H: Accesses the high byte P2[8]
• UxP2L: Accesses the low byte P2[7:0]
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 645
PIC18F27/47/57Q84
UART - Universal Asynchronous Receiver Tra...
35.20.13 UxP3
Name:
UxP3
UART Parameter 3
Bit
15
14
13
12
7
6
5
4
11
10
9
8
P3[8]
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
P3[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit 8 – P3[8] Parameter 3 Most Significant bit
UART mode operating parameter values
Value
Condition
n
MODE = DMX
x
All other modes/Limited featured UART
Description
Most Significant bit of last address of receive block
Not used
Bits 7:0 – P3[7:0] Parameter 3 Least Significant bits
UART mode operating parameter values
Value
Condition
Description
n
MODE = DMX
Least Significant bits of last address of receive block
n
MODE = LIN Client
Number of data bytes to receive
n
MODE = Asynchronous Address Receiver address mask. Received address is XOR’d with UxP2L
then AND’d with UxP3L Match occurs when result is zero
x
All other modes
Not used
Notes: The individual bytes in this multi-byte register can be accessed with the following register names:
• UxP3H: Accesses the high byte P3[8]
• UxP3L: Accesses the low byte P3[7:0]
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 646
PIC18F27/47/57Q84
UART - Universal Asynchronous Receiver Tra...
35.20.14 UxTXCHK
Name:
Address:
UxTXCHK
0x2A4,0x2B7
UART Transmit Checksum Result Register
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TXCHK[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – TXCHK[7:0] Transmit Checksum Value
Value
Condition
n
MODE = LIN and C0EN = 1
n
MODE = LIN and C0EN = 0
n
MODE = All others and C0EN = 1
x
MODE = All others and C0EN = 0
© 2021 Microchip Technology Inc.
Description
Sum of all transmitted bytes including PID
Sum of all transmitted bytes except PID
Sum of all transmitted bytes since last clear
Not used
Preliminary Datasheet
DS40002213D-page 647
PIC18F27/47/57Q84
UART - Universal Asynchronous Receiver Tra...
35.20.15 UxRXCHK
Name:
Address:
UxRXCHK
0x2A2, 0x2B5
UART Receive Checksum Result Register
Bit
Access
Reset
7
6
5
R/W
0
R/W
0
R/W
0
3
RXCHK[7:0]
R/W
R/W
0
0
Bits 7:0 – RXCHK[7:0] Receive Checksum Value
Value
Condition
n
MODE = LIN and C0EN = 1
n
MODE = LIN and C0EN = 0
n
MODE = All others and C0EN = 1
x
MODE = All others and C0EN = 0
© 2021 Microchip Technology Inc.
4
2
1
0
R/W
0
R/W
0
R/W
0
Description
Sum of all received bytes including PID
Sum of all received bytes except PID
Sum of all received bytes since last clear
Not used
Preliminary Datasheet
DS40002213D-page 648
PIC18F27/47/57Q84
UART - Universal Asynchronous Receiver Tra...
35.21
Register Summary - UART
Address
Name
Bit Pos.
7
6
5
4
3
2
1
0
00
0x01
...
0x02A0
0x02A1
0x02A2
0x02A3
0x02A4
U2ERRIE
7:0
TXMTIE
PERIE
ABDOVE
CERIE
FERIE
RXBKIE
RXFOIE
TXCIE
U1RXB
U1RXCHK
U1TXB
U1TXCHK
0x02A5
U1P1
0x02A7
Reserved
U1P2
0x02A9
U1P3
0x02AB
0x02AC
0x02AD
U1CON0
U1CON1
U1CON2
0x02AE
U1BRG
0x02B0
0x02B1
0x02B2
0x02B3
0x02B4
0x02B5
0x02B6
0x02B7
U1FIFO
U1UIR
U1ERRIR
U1ERRIE
U2RXB
U2RXCHK
U2TXB
U2TXCHK
0x02B8
U2P1
0x02BA
U2P2
0x02BC
U2P3
0x02BE
0x02BF
0x02C0
U2CON0
U2CON1
U2CON2
0x02C1
U2BRG
0x02C3
0x02C4
0x02C5
0x02C6
0x02C7
0x02C8
0x02C9
0x02CA
U2FIFO
U2UIR
U2ERRIR
U2ERRIE
U3RXB
Reserved
U3TXB
Reserved
0x02CB
U3P1
0x02CD
U3P2
0x02CF
U3P3
0x02D1
0x02D2
0x02D3
U3CON0
U3CON1
U3CON2
7:0
7:0
7:0
7:0
7:0
15:8
7:0
15:8
7:0
15:8
7:0
7:0
7:0
7:0
15:8
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
15:8
7:0
15:8
7:0
15:8
7:0
7:0
7:0
7:0
15:8
7:0
7:0
7:0
7:0
7:0
RXB[7:0]
RXCHK[7:0]
TXB[7:0]
TXCHK[7:0]
P1[7:0]
P1[8]
P2[7:0]
P2[8]
P3[7:0]
BRGS
ON
RUNOVF
ABDEN
TXWRE
WUIF
TXMTIF
TXMTIE
STPMD
ABDIF
PERIF
PERIE
RXPOL
TXEN
RXEN
WUE
RXBIMD
STP[1:0]
C0EN
BRG[7:0]
BRG[15:8]
TXBE
TXBF
RXIDL
ABDOVF
ABDOVE
CERIF
FERIF
CERIE
FERIE
RXB[7:0]
RXCHK[7:0]
TXB[7:0]
TXCHK[7:0]
P1[7:0]
P3[8]
MODE[3:0]
BRKOVR
SENDB
TXPOL
FLO[1:0]
XON
ABDIE
RXBKIF
RXBKIE
RXBE
RXBF
RXFOIF
RXFOIE
TXCIF
TXCIE
P1[8]
P2[7:0]
P2[8]
P3[7:0]
BRGS
ON
RUNOVF
ABDEN
TXWRE
WUIF
TXMTIF
TXMTIE
STPMD
ABDIF
PERIF
PERIE
RXPOL
TXEN
RXEN
WUE
RXBIMD
STP[1:0]
C0EN
BRG[7:0]
BRG[15:8]
TXBE
TXBF
RXIDL
ABDOVF
ABDOVE
CERIF
FERIF
CERIE
FERIE
RXB[7:0]
7:0
TXB[7:0]
7:0
15:8
7:0
15:8
7:0
15:8
7:0
7:0
7:0
P1[7:0]
P3[8]
MODE[3:0]
BRKOVR
SENDB
TXPOL
FLO[1:0]
XON
ABDIE
RXBKIF
RXBKIE
RXBE
RXBF
RXFOIF
RXFOIE
TXCIF
TXCIE
P2[7:0]
P3[7:0]
BRGS
ON
RUNOVF
© 2021 Microchip Technology Inc.
ABDEN
RXPOL
TXEN
RXEN
WUE
STP[1:0]
RXBIMD
Preliminary Datasheet
MODE[3:0]
BRKOVR
SENDB
TXPOL
FLO[1:0]
DS40002213D-page 649
PIC18F27/47/57Q84
UART - Universal Asynchronous Receiver Tra...
...........continued
Address
Name
Bit Pos.
0x02D4
U3BRG
7:0
15:8
0x02D6
0x02D7
0x02D8
0x02D9
0x02DA
0x02DB
0x02DC
0x02DD
U3FIFO
U3UIR
U3ERRIR
U3ERRIE
U4RXB
Reserved
U4TXB
Reserved
0x02DE
U4P1
0x02E0
U4P2
0x02E2
U4P3
0x02E4
0x02E5
0x02E6
U4CON0
U4CON1
U4CON2
0x02E7
U4BRG
0x02E9
0x02EA
0x02EB
0x02EC
0x02ED
0x02EE
0x02EF
0x02F0
U4FIFO
U4UIR
U4ERRIR
U4ERRIE
U5RXB
Reserved
U5TXB
Reserved
0x02F1
U5P1
0x02F3
U5P2
0x02F5
U5P3
0x02F7
0x02F8
0x02F9
U5CON0
U5CON1
U5CON2
0x02FA
U5BRG
0x02FC
0x02FD
0x02FE
0x02FF
U5FIFO
U5UIR
U5ERRIR
U5ERRIE
7:0
7:0
7:0
7:0
7:0
7
6
5
4
3
2
1
0
RXIDL
XON
ABDIE
RXBKIF
RXBKIE
RXBE
RXBF
BRG[7:0]
BRG[15:8]
TXWRE
WUIF
TXMTIF
TXMTIE
STPMD
ABDIF
PERIF
PERIE
TXBE
ABDOVF
ABDOVE
TXBF
CERIF
FERIF
CERIE
FERIE
RXB[7:0]
7:0
TXB[7:0]
7:0
15:8
7:0
15:8
7:0
15:8
7:0
7:0
7:0
7:0
15:8
7:0
7:0
7:0
7:0
7:0
P1[7:0]
RXFOIF
RXFOIE
P2[7:0]
P3[7:0]
BRGS
ON
RUNOVF
ABDEN
TXWRE
WUIF
TXMTIF
TXMTIE
STPMD
ABDIF
PERIF
PERIE
RXPOL
TXEN
RXEN
WUE
RXBIMD
STP[1:0]
BRG[7:0]
BRG[15:8]
TXBE
TXBF
RXIDL
ABDOVF
ABDOVE
CERIF
FERIF
CERIE
FERIE
RXB[7:0]
7:0
TXB[7:0]
7:0
15:8
7:0
15:8
7:0
15:8
7:0
7:0
7:0
7:0
15:8
7:0
7:0
7:0
7:0
P1[7:0]
MODE[3:0]
BRKOVR
SENDB
TXPOL
FLO[1:0]
XON
ABDIE
RXBKIF
RXBKIE
RXBE
RXBF
RXFOIF
RXFOIE
P2[7:0]
P3[7:0]
BRGS
ON
RUNOVF
ABDEN
TXWRE
WUIF
TXMTIF
TXMTIE
STPMD
ABDIF
PERIF
PERIE
© 2021 Microchip Technology Inc.
RXPOL
TXEN
RXEN
WUE
RXBIMD
STP[1:0]
BRG[7:0]
BRG[15:8]
TXBE
TXBF
RXIDL
ABDOVF
ABDOVE
CERIF
CERIE
FERIF
FERIE
Preliminary Datasheet
MODE[3:0]
BRKOVR
SENDB
TXPOL
FLO[1:0]
XON
ABDIE
RXBKIF
RXBKIE
RXBE
RXBF
RXFOIF
RXFOIE
DS40002213D-page 650
PIC18F27/47/57Q84
SPI - Serial Peripheral Interface Module
36.
SPI - Serial Peripheral Interface Module
The Serial Peripheral Interface (SPI) module is a synchronous serial data communication bus that operates in Full
Duplex mode. Devices communicate in a host/client environment where the host device initiates the communication.
A client device is typically controlled through a chip select known as Client Select. Some examples of client
devices include serial EEPROMs, shift registers, display drivers, A/D converters, and other PIC® devices with SPI
capabilities.
The SPI bus specifies four signal connections:
• Serial Clock (SCK)
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Client Select (SS)
The following figure shows the block diagram of the SPI module.
Figure 36-1. SPI Module Simplified Block Diagram
Data bus
Rev. 10-000076B
11/2/2018
Read
Write
8
8
Receive FIFO
(2 deep)
Transmit FIFO
(2 deep)
8
SDI
SPIxSDIPPS
8
Receive Shift
Register
SDIP
RXR
SS_in
1
SPIxSSPPS
SDO
Transmit
Serializer(1)
TXR
RxyPPS
SDOP
1
SCK_out
0
RxyPPS
SSP
SSET
CKP
SPI Control Module
and Transfer Counter
1
See
SPIxCLK
Register
SCK Generator
1
SS_out
0
1
0
RxyPPS
SSP
SSET
SPIxBAUD
MST
CLKSEL
SCK_in
SPIxSCKPPS
CKP
Note 1:
If the transmit FIFO is empty and TXR=1, the previous value of the
receive shift register will be sent to the transmit serializer.
The SPI transmit output (SDO_out) is available to the remappable PPS SDO pin and internally to the select
peripherals.
The SPI bus typically operates with a single host device and one or more client devices. When multiple client devices
are used, an independent Client Select connection is required from the host device to each client device.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 651
PIC18F27/47/57Q84
SPI - Serial Peripheral Interface Module
The host selects only one client at a time. Most client devices have tri-state outputs so their output signal appears
disconnected from the bus when they are not selected.
Transmissions typically involve Shift registers, eight bits in size, one in the host and one in the client. With either
the host or the client device, data is always shifted out one bit at a time, with the Most Significant bit (MSb) shifted
out first. At the same time, a new bit is shifted into the device. Unlike older Microchip devices, the SPI module on
this device contains one register for incoming data and another register for outgoing data. Both registers also have
multibyte FIFO buffers and allow for DMA bus connections.
The figure below shows a typical connection between two devices configured as host and client devices.
Figure 36-2. SPI Host/Client Connection with FIFOs
Rev. 10-000080C
1/11/2019
SPI Host: MST=1
LSb
MSb
Transmit Shift
Register
Transmit FIFO
(SPIxTXB)
SDOx
SDIx
Receive FIFO
(SPIxRXB)
(Note 1)
Receive FIFO
(SPIxRXB)
Receive Shift
Register
MSb
LSb
Device 1
SPI Client: MST=0
LSb
MSb
Receive Shift
Register
(Note 1)
Transmit FIFO
(SPIxTXB)
SDIx
SCKx
SSxOUT/
GPIO
SDOx
Serial clock
Client Select
(optional)
SCKx
SSxIN
Transmit Shift
Register
MSb
LSb
Device 2
Note 1: In some modes, if the Transmit FIFO is empty, the most recently received byte of data will be
transmitted.
2: This diagram assumes that the LSBF bit is cleared (communications are MSb-first). When LSBF is
set, the communications will be LSb-first.
Data is shifted out of the transmit FIFO on the programmed clock edge and into the receive Shift register on the
opposite edge of the clock.
The host device transmits information on its SDO output pin which is connected to, and received by, the client’s SDI
input pin. The client device transmits information on its SDO output pin, which is connected to, and received by, the
host’s SDI input pin.
The host device sends out the clock signal. Both the host and the client devices need to be configured for the same
clock phase and clock polarity.
During each SPI clock cycle, a full-duplex data transmission occurs. This means that while the host device is sending
out the MSb from its output register (on its SDO pin) and the client device is reading this bit and saving it as the LSb
of its input register. The client device is also sending out the MSb from its Shift register (on its SDO pin) and the host
device is reading this bit and saving it as the LSb of its input register.
After eight bits have been shifted out, the host and client have exchanged register values and stored the incoming
data into the receiver FIFOs.
If there is more data to exchange, the registers are loaded with new data and the process repeats.
Whether the data is meaningful or not (dummy data) depends on the application software. This leads to three
scenarios for data transmission:
• Host sends useful data and client sends dummy data
• Host sends useful data and client sends useful data
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 652
PIC18F27/47/57Q84
SPI - Serial Peripheral Interface Module
•
Host sends dummy data and client sends useful data
In this SPI module, dummy data may be sent without software involvement. Dummy transmit data is automatically
handled by clearing the TXR bit and receive data is ignored by clearing the RXR bit. See Table 36-1 as well as Host
Mode and Client Mode for further TXR/RXR setting details.
This SPI module can send transmissions of any number of bits, and can send information in segments of varying size
(from 1-8 bits in width). As such, transmissions may involve any number of clock cycles, depending on the amount of
data to be transmitted.
When there is no more data to be transmitted, the host stops sending the clock signal and deselects the client. Every
client device connected to the bus that has not been selected through its Client Select line disregards the clock and
transmission signals and does not transmit out any data of its own.
36.1
SPI Controls
The following registers control the SPI operation:
• SPI Interrupt Flag (SPIxINTF) Register
• SPI Interrupt Enable (SPIxINTE) Register
• SPI Byte Count High and Low (SPIxTCNTH/L) Registers
• SPI Bit Count (SPIxTWIDTH) Register
• SPI Baud Rate (SPIxBAUD) Register
• SPI Control (SPIxCON0) Register 0
• SPI Control (SPIxCON1) Register 1
• SPI Control (SPIxCON2) Register 2
• SPI FIFO Status (SPIxSTATUS) Register
• SPI Receiver Buffer (SPIxRXB) Register
• SPI Transmit Buffer (SPIxTXB) Register
• SPI Clock Select (SPIxCLK) Register
SPIxCON0, SPIxCON1, and SPIxCON2 are control registers for the SPI module.
SPIxSTATUS reflects the status of both the SPI module and the receive and transmit FIFOs.
SPIxBAUD and SPIxCLK control the Baud Rate Generator (BRG) of the SPI module when in Host mode. The
SPIxCLK selects the clock source that is used by the BRG. The SPIxBAUD configures the clock divider used on that
clock source. More information on the BRG is available in Host Mode SPI Clock Configuration.
SPIxTxB and SPIxRxB are the Transmit and Receive Buffer registers used to send and receive data on the SPI bus.
The Transmit and Receive Buffer registers offer indirect access to Shift registers that are used for shifting the data
in and out. Both registers access the multibyte FIFOs, allowing for multiple transmissions or receptions to be stored
between software transfers of the data.
The SPIxTCNTH:L register pair either count or control the number of bits or bytes in a data transfer. When BMODE
= 1, the SPIxTCNT value signifies bytes and the SPIxTWIDTH value signifies the number of bits in a byte. When
BMODE = 0, the SPIxTCNT value is concatenated with the SPIxTWIDTH register to signify bits. In Host Receive
Only mode (TXR = 0 and RXR = 1), the data transfer is initiated by writing SPIxTCNT with the desired bit or byte
value to transfer. In Host Transmit mode (TXR = 1), the data transfer is initiated by writing the SPIxTxB register, in
which case the SPIxTCNT is a down counter for the bits or bytes transferred.
The SPIxINTF and SPIxINTE are the flags and enables, respectively, for SPI specific interrupts. They are tied to the
SPIxIF flag and SPIxIE enable bit in the PIR and PIE registers, which is triggered when any interrupt contained in
the SPIxINTF/SPIxINTE registers is triggered. The PIR/PIE registers also contain SPIxTXIF/SPIxTXIE bits, which are
the Interrupt flag and enable for the SPI Transmit Interrupt, as well as the SPIxRXIF/SPIxRXIE bits, which are the
Interrupt flag and Enable bit for the SPI receive interrupt.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 653
PIC18F27/47/57Q84
SPI - Serial Peripheral Interface Module
36.2
SPI Operation
When initializing the SPI, several options need to be specified. This is done by programming the appropriate control
bits of the SPIxCON0, SPIxCON1, and SPIxCON2 registers. These control bits allow the following to be configured:
• Host mode (SCK is the clock output)
• Client mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Input, Output, and Client Select Polarity
• Data Input Sample Phase (middle or end of data output time)
• Clock Edge (output data on first/second edge of SCK)
• Clock Rate (Host mode only)
• Client Select mode (Host or Client mode)
• MSB-First or LSB-First
• Receive/Transmit modes:
– Full-Duplex
– Receive Only (receive without transmit)
– Transmit Only (transmit without receive)
• Transfer Counter mode (only available in Transmit Only mode)
36.2.1
Enabling and Disabling the SPI Module
Setting the EN bit enables the SPI peripheral. However, to reset or reconfigure the SPI mode the EN bit must be
cleared.
Setting the EN bit enables the SPI inputs and outputs: SDI, SDO, SCK_out, SCK_in, SS_out, and SS_in. The pins for
all of these inputs and outputs are selected by the PPS controls, and thus must have their functions mapped properly
to the device pins to function. Refer to the “PPS - Peripheral Pin Select Module” chapter for more details.
SS_out and SCK_out must have the pins to which they are assigned set as outputs (TRIS bits must be ‘0’) in order to
properly output. Clearing the TRIS bit of the SDO pin will cause the SPI module to always control that pin, but is not
necessary for SDO functionality. (see Input and Output Polarity Control)
Configurations selected by the following registers will not be changed while the EN bit is set:
• SPIxBAUD
• SPIxCON1
• SPIxCON0 (with the exception of clearing the EN bit)
Clearing the EN bit aborts any transmissions in progress, disables the setting of interrupt flags by hardware, and
resets the FIFO occupancy. (see Transmit and Receive FIFOs)
36.2.2
BUSY Bit
While a data transfer is in progress, the SPI hardware sets the BUSY bit. This bit can be polled by the user to
determine the current status of the SPI module, and to know when a communication is complete. The following
registers and bits will not be changed by software while the BUSY bit is set:
• SPIxTCNT
• SPIxTWIDTH
• SPIxCON2
• The CLB bit
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Preliminary Datasheet
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PIC18F27/47/57Q84
SPI - Serial Peripheral Interface Module
Important:
1. The BUSY bit is subject to synchronization delay of up to two instruction cycles. The user must
wait for it to set after loading the transmit buffer (SPIxTXB register) before using it to determine the
status of the SPI module.
2. It is also not recommended to read SPIxTCNT while the BUSY bit is set, as the value in the
registers may not be a reliable indicator of the transfer counter. Use the TCZIF bit to accurately
determine that the transfer counter has reached zero.
36.2.3
Transmit and Receive FIFOs
The transmission and reception of data from the SPI module is handled by two FIFOs, one for reception and one for
transmission. These are addressed by the SFRs, SPIxRXB and SPIxTXB, respectively.
The transmit FIFO is written to by software and is read by the SPI module to shift the data onto the SDO pin. The
receive FIFO is written to by the SPI module as it shifts in the data from the SDI pin and is read by software. Setting
the CLB bit resets the occupancy for both FIFOs, emptying both buffers. The FIFOs are also reset by clearing the EN
bit, thus disabling the SPI module.
Important: The transmit and receive FIFO occupancy refer to the number of bytes that are currently
being stored in each FIFO. These values are used in this chapter to illustrate the function of these FIFOs
and are not directly accessible through software.
The SPIxRXB register addresses the receive FIFO and is read-only. Reading from this register will read from the
first FIFO location that was written to by hardware and decrease the receive FIFO occupancy. If the FIFO is empty,
reading from this register will instead return a value of zero and set the RXRE (Receive Buffer Read Error) bit. The
RXRE bit must then be cleared in software in order to properly reflect the status of the read error. When the receive
FIFO is full, the RXBF bit will be set.
The SPIxTXB register addresses the transmit FIFO and is write-only. Writing to the register will write to the first empty
FIFO location and increase the occupancy. If the FIFO is full, writing to this register will not affect the data and will set
the TXWE bit. When the transmit FIFO is empty, the TXBE bit will be set.
More details on enabling and disabling the receive and transmit functions is summarized in Table 36-1 and Client
Mode Transmit Options.
36.2.4
LSb vs. MSb-First Operation
Typically, the SPI communication outputs the Most Significant bit first, but some devices or buses may not conform to
this standard. In this case, the LSBF bit may be used to alter the order in which bits are shifted out during the data
exchange. In both Host and Client mode, the LSBF bit controls whether data is shifted MSb or LSb first. Clearing the
bit (default) configures the data to transfer MSb first, which conforms to traditional SPI operation, while setting the bit
configures the data to transfer LSb first.
36.2.5
Input and Output Polarity Control
SPIxCON1 has three bits that control the polarity of the SPI inputs and outputs:
• The SDIP bit controls the polarity of the SDI input
• The SDOP bit controls the polarity of the SDO output
• The SSP bit controls the polarity of both the client SS input and the host SS output
For all three bits, when the bit is clear, the input or output is active-high, and when the bit is set, the input or output is
active-low. When the EN bit is cleared, SS_out and SCK_out both revert to the Inactive state dictated by their polarity
bits. The SDO output state, when the EN bit is cleared, is determined by several factors as follows:
• When the associated TRIS bit for the SDO pin is cleared, and the SPI goes Idle after a transmission, the SDO
output will remain at the last bit level.
• When the associated TRIS bit for the SDO pin is set, its behavior varies in Client and Host mode:
– In Client mode, the SDO pin tri-states when any of the following are true:
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Preliminary Datasheet
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PIC18F27/47/57Q84
SPI - Serial Peripheral Interface Module
•
•
Client Select is inactive
EN = 0
•
TXR = 0
– In Host mode:
• The SDO pin tri-states when TXR = 0
•
36.2.6
When TXR = 1 and the SPI goes Idle after a transmission, the SDO output will remain at the last bit
level. The SDO pin will revert to the Idle state when EN is cleared.
Transfer Counter
In all Host modes, the transfer counter can be used to determine how many data transfers the SPI will send/receive.
The transfer counter is comprised of the SPIxTCNT registers, and is also partially controlled by the SPIxTWIDTH
register.
The transfer counter has two primary modes, determined by the BMODE bit. Each mode uses the SPIxTCNT and
SPIxTWIDTH registers to determine the number and size of the transfers. In both modes, when the transfer counter
reaches zero, the TCZIF interrupt flag is set.
Important:
In all Client modes and when BMODE = 1 in Host modes, the transfer counter will still decrement as
transfers occur and can be used to count the number of messages sent/received, control SS_out, and
trigger TCZIF. Also, when BMODE = 1, the SPIxTWIDTH register can be used in Host and Client modes
to determine the size of messages sent and received by the SPI, even if the transfer counter is not being
actively used to control the number of messages being sent/received by the SPI module.
36.2.6.1 Total Bit Count Mode (BMODE = 0)
In this mode, SPIxTCNT and SPIxTWIDTH are concatenated to determine the total number of bits to be transferred.
These bits will be loaded from/into the transmit/receive FIFOs in 8-bit increments and the transfer counter will be
decremented by eight until the total number of remaining bits is less than eight. If there are any remaining bits
(SPIxTWIDTH ≠ 0), the transmit FIFO will send out one final message with any extra bits greater than the remainder
ignored.
The SPIxTWIDTH is the remaining bit count but the value does not change as it does for the SPIxTCNT value. The
receiver will load a final byte into the receiver FIFO, and pad the extra bits with zeros. The LSBF bit determines
whether the Most Significant or Least Significant bits of this final byte are ignored or padded. For example, when
LSBF = 0 and the final transfer contains only two bits, then if the last byte sent was 0x5F, the RXB of the receiver will
contain 0x40 which are the two MSbs of the final byte padded with zeros in the LSbs.
In this mode, the SPI host will only transmit messages when the SPIxTCNT value is greater than zero, regardless of
the TXR and RXR settings.
In Host Transmit mode, the transfer starts with the data write to the SPIxTXB register or the count value written to the
SPIxTCNTL register, whichever occurs last.
In Host Receive Only mode, the transfer clocks start when the SPIxTCNTL value is written. Transfer clocks are
suspended when the receive FIFO is full and resume as the FIFO is read.
36.2.6.2 Variable Transfer Size Mode (BMODE = 1)
In this mode, SPIxTWIDTH specifies the width of every individual piece of the data transfer in bits. SPIxTCNT
specifies the number of transfers of this bit length. If SPIxTWIDTH = 0, each piece is a full byte of data. If
SPIxTWIDTH ≠ 0, then only that specified number of bits from the transmit FIFO are shifted out, with the unused bits
ignored.
Received data is padded with zeros in the unused bit areas when transferred into the receive FIFO. The LSBF bit
determines whether the Most Significant or Least Significant bits of the transfers are ignored or padded.
In this mode, the transfer counter being zero only stops messages from being sent or received when in Receive Only
mode.
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Preliminary Datasheet
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PIC18F27/47/57Q84
SPI - Serial Peripheral Interface Module
Important:
With BMODE = 1, it is possible for the transfer counter (SPIxTCNT) to decrement below zero, although
when in ‘Receive Only’ Host mode, transfer clocks will cease when the transfer counter reaches zero.
36.2.6.3 Transfer Counter in Client Mode
In Client mode, the transfer counter will still decrement as data is shifted in and out of the SPI module, but it will not
control data transfers. The BMODE bit along with the transfer counter is used to determine when the device will look
for Client Select faults.
When BMODE = 0, the SSFLT bit will be set if Client Select transitions from its Active to Inactive state during bytes of
data, or if it transitions before the last bit sent during the final byte (if SPIxTWIDTH ≠ 0).
When BMODE = 1, the SSFLT bit will be set if Client Select transitions from its Active to Inactive state before the final
bit of each individual transfer is completed.
Note: SSFLT does not have an associated interrupt, so it will be checked in software. An ideal time to do this is
when the End of Client Select Interrupt (EOSIF) is triggered (see Start of Client Select and End of Client Select
Interrupts).
36.3
Host Mode
In Host mode, the device controls the SCK line, and as such, initiates data transfers and determines when any clients
broadcast data onto the SPI bus.
Host mode can be configured in four different modes, configured by the TXR and RXR bits:
• Full-Duplex mode
• Receive Only mode
• Transmit Only mode
• Transfer Off mode
The modes are illustrated in the following table:
Table 36-1. Host Mode TXR/RXR Settings
RXR = 1
TXR = 1
TXR = 0
Full Duplex mode
BMODE = 1: Transfer when RxFIFO is not full and TxFIFO is
not empty
Receive Only mode
Transfer when RxFIFO is not full and
the Transfer Counter is non-zero
BMODE = 0: Transfer when RXFIFO is not full, TXFIFO is not
empty, and the Transfer Counter is non- zero
Transmitted data is either the top of
the FIFO or the most recently received
data
Transmit Only mode
BMODE = 1: Transfer when TxFIFO is not empty
RXR = 0
BMODE = 0: Transfer when TXFIFO is not empty and the
Transfer Counter is non-zero
No Transfers
Received data is not stored
36.3.1
Full-Duplex Mode
When both TXR and RXR are set, the SPI host is in Full-Duplex mode. In this mode, data transfer triggering is
affected by the BMODE bit.
When BMODE = 1, data transfers will occur whenever both the receive FIFO is not full and there is data present in
the transmit FIFO. In practice, as long as the receive FIFO is not full, data will be transmitted/received as soon as the
SPIxTXB register is written to, matching the functionality of SPI (MSSP) modules on older 8-bit Microchip devices.
The SPIxTCNT will decrement with each transfer. However, when SPIxTCNT is zero the next transfer is not inhibited
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Preliminary Datasheet
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PIC18F27/47/57Q84
SPI - Serial Peripheral Interface Module
and the corresponding SPIxTCNT decrement will cause the count to roll over to the maximum value. The following
figure shows an example of a communication using this mode.
Figure 36-3. SPI Host Operation - Data Exchange RXR = 1, TXR = 1
Rev. 10-000281A
11/9/2018
Software Write to
SPIxTCNT
SPIxTCNT
Note 2
0
5
4
3
2
1
0
Software Write To
TXR
TXR
Software Write to
RXR
RXR
SCK_out
Note 3
SDO_out
`HX
`HX
SRMTIF
TCZIF
Note 2
Software Write
to SPIxTXB
TXFIFO
Occupancy
0
1
2
1
2
1
2
1
0
1
0
SPIxTIF
Software Read
from SPIxRXB
RXFIFO
Occupancy
0
1
0
1
0
1
0
1
0
1
0
SPIxRIF
Note: 1. SS(out) is not shown on this diagram
2. SPIxTCNT write is optional when TXR/RXR = 1/1 and BMODE=1. If BMODE=0, a write to SPIxTCNT is required to start
transmission; TCZIF signals the transition of SPIxTCNT from 1 to 0
3. Transmission gap occurs while waiting for transmitter data.
When BMODE = 0, the transfer counter (SPIxTCNT) must also be written to before transfers will occur. Transfers will
cease when the transfer counter reaches ‘0’. For example, if SPIxTXB is written twice and then SPIxTCNTL is written
with ‘3’ then the transfer will start with the SPIxTCNTL write. The two bytes in the TXFIFO will be sent after which the
transfer will suspend until the third and last byte is written to SPIxTXB.
36.3.2
Transmit Only Mode
When TXR is set and RXR is clear, the SPI host is in Transmit Only mode. In this mode, data transfer triggering is
affected by the BMODE bit.
When BMODE = 1, data transfers will occur whenever the transmit FIFO is not empty. Data will be transmitted as
soon as the SPIxTXB register is written to, matching the functionality of the SPI (MSSP) modules on previous 8-bit
devices. The SPIxTCNT will decrement with each transfer. However, when SPIxTCNT is zero the next transfer is not
inhibited and the corresponding SPIxTCNT decrement will cause the count to roll over to the maximum value. Any
data received in this mode is not stored in the receive FIFO. The following figure shows an example of sending a
command and then sending a byte of data, using this mode.
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Preliminary Datasheet
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PIC18F27/47/57Q84
SPI - Serial Peripheral Interface Module
Figure 36-4. SPI Host Operation - Command+Write Data TXR = 1, RXR = 0
Rev. 10-000282A
11/6/2018
Software Write to
TXTCNTL
Note 2
0
SPIxTXCNT
-1
-2
3
2
1
0
Software Write
to TXR
TXR
Software Write
to RXR
RXR
SCK_out
SDO_out
Shifted data out
SRMTIF
Note 3
BCZIF
Software Write
to SPIxTXB
TxFIFO
Occupancy
Note 4
0
1
2
1
0
1
2
1
2
1
0
SPIxTIF
Note: 1. SS_out is not shown
2. The byte counter is optional when TXR/RXR = 1/0;
3. After the command bytes, wait for SRMTIF before loading SPIxTXB otherwise the command data would decrement SPIxTXCNT.
Alternatively, load SPIxTXCNT= 5 and count the command bytes also; TCZIF signals the end of the transmission.
4. Transmit data interrupt handler (or DMA) must write only the bytes necessary; the byte counter is not available as an indicator.
5. Reading the SPIxRXB is not required because RXR = 0.
When BMODE = 0, the transfer counter (SPIxTCNT) must also be written to before transfers will occur, and transfers
will cease when the transfer counter reaches ‘0’.
For example, if SPIxTXB is written twice and then SPIxTCNTL is written with ‘3’, the transfer will start with the
SPIxTCNTL write. The two bytes in the TXFIFO will be sent after which the transfer will suspend until the third and
last byte is written to SPIxTXB.
36.3.3
Receive Only Mode
When RXR is set and TXR is clear, the SPI host is in Receive Only mode. In this mode, data transfers when the
receive FIFO is not full and the transfer counter is non-zero. In this mode, writing a value to SPIxTCNTL will start
the clocks for transfer. The clocks will suspend while the receive FIFO is full and cease when the SPIxTCNT reaches
zero (see Transfer Counter). If there is any data in the transmit FIFO, the first data written to SPIxTXB will be
transmitted on each data exchange, although the transmit FIFO occupancy will not change, meaning that the same
message will be sent on each transmission. If there is no data in the transmit FIFO, the most recently received data
will be transmitted. The following figure shows an example of sending a command using the Transmit Only mode and
then receiving a byte of data using the Receive Only mode.
Important: When operating in Receive only mode and the size of every SPI transaction is less than 8
bits, it is recommended to operate in BMODE = 1 mode. The size of the packet can be configured using
the SPIxTWIDTH register.
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Preliminary Datasheet
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PIC18F27/47/57Q84
SPI - Serial Peripheral Interface Module
Figure 36-5. SPI Host Operation, Command+Read Data, TXR = 0, RXR = 1
Rev. 10-000283A
11/6/2018
Software Write to
TxCNTL
0
SPIxTXCNT
-1
-2
3
2
1
0
Software Write to
TXR
TXR
Software Write
to RXR
RXR
SCK_out
SDO_out
Shifted data out
Note 2
SRMTIF
TCZIF
Software Write
to SPIxTXB
TXFIFO
Occupancy
0
1
2
1
0
Software Read
from SPIxRXB
RXFIFO
Occupancy
0
1
0
1
0
1
0
SPIxRIF
Note: 1. SS_out is not shown
2. Software must wait for shift-register empty (SRMTIF) before changing TXR, RXR, SPIxTCNT and SPIxTWIDTH controls.
This is not considered an imposition in this case, because the client probably needs time to load output data.
36.3.4
Transfer Off Mode
When both TXR and RXR are cleared, the SPI host is in Transfer Off mode. In this mode, SCK will not toggle and no
data is exchanged. However, writes to SPIxTXB will be transferred to the transmit FIFO which will then be transmitted
when the TXR bit is set.
36.3.5
Host Mode Client Select Control
36.3.5.1 Hardware Client Select Control
The SPI module allows for direct hardware control of a Client Select output. The Client Select output (SS_out) is
controlled both directly, through the SSET bit, and indirectly by the hardware while the transfer counter is non-zero
(see Transfer Counter). The SS_out pin is selected with the PPS controls. The SS_out polarity is controlled by the
SSP bit.
Setting the SSET bit will assert SS_out. Clearing the SSET bit will leave SS_out to be controlled by the transfer
counter. When the transfer counter is loaded, the SPI module will automatically assert SS_out. When the transfer
counter decrements to zero, the SPI module will deassert SS_out either one baud period after the final SCK pulse of
the final transfer (when CKE/SMP = 0/1) or one half baud period otherwise, as shown in the following figure.
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Preliminary Datasheet
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PIC18F27/47/57Q84
SPI - Serial Peripheral Interface Module
Figure 36-6. SPI Host SS Operation - CKE = 0, BMODE = 1, TWIDTH = 0, SSP= 0
Rev. 10-000284A
11/6/2018
SPIEN
baud_clock
Software Write to
SPIxTCNTL
Transfer
Counter
1
0
SS_out
minimum 1 baud clock when FST = 0
approx. 1 baud clock
SCK_out
SDO_bit_number
Note:
7
6
5
4
3
2
1
0
1. SDO bit number illustrates the transmitted bit number, and is not intended to imply SDO_out tristate operation.
2. Assumes SPIxTXB holds data when SPIxTCNTL is written.
36.3.5.2 Software Client Select Control
Client Select can be controlled through software via a general purpose I/O pin. In this case, ensure that the desired
pin is configured as a general purpose output with the PPS and TRIS controls. In this case, SSET will not affect the
Client Select, the Transfer Counter will not automatically control the Client Select output, and all setting and clearing
of the Client Select output line must be directly controlled by software.
36.3.6
Host Mode SPI Clock Configuration
36.3.6.1 SPI Clock Selection
The clock source for SPI Host modes is selected by the SPIxCLK register.
The SPIxBAUD register allows for dividing this clock. The frequency of the SCK output is defined by the following
equation:
Equation 36-1. SCK Output Frequency
FCSEL
FBAUD =
2 × BAUD + 1
where FBAUD is the baud rate frequency output on the SCK pin, FCSEL is the frequency of the input clock selected by
the SPIxCLK register, and BAUD is the value contained in the SPIxBAUD register.
36.3.6.2 Clock and Data Change Alignment
The CKP, CKE, and SMP bits control the relationship between the SCK clock output, SDO output data changes, and
SDI input data sampling. The bit functions are as follows:
• CKP controls SCK output polarity
• CKE controls SDO output change relative to the SCK clock
• SMP controls SDI input sampling relative to the clock edges
The CKE bit, when set, inverts the low Idle state of the SCK output to a high Idle state.
The following figures illustrate the eight possible combinations of the CKP, CKE, and SMP bit selections.
Important: All timing diagrams assume the LSBF bit is cleared.
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Preliminary Datasheet
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PIC18F27/47/57Q84
SPI - Serial Peripheral Interface Module
Figure 36-7. Clocking Detail - Host Mode, CKE = 0, SMP = 0
Rev. 10-000276A
11/6/2018
MST = 1,CKE = 0, SMP = 0
A
SCK
SDO
Previous bit 0
I
A
I
A
I
A
I
A
I
A
I
A
I
A
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
A
A
A
A
A
A
A
A
I
CKP = 0
input sample clock
SCK
SDO
Previous bit 0
I
bit 7
I
bit 6
I
bit 5
I
bit 4
I
bit 3
I
bit 2
I
bit 1
I
CKP = 1
bit 0
input sample clock
TXFIFO
determined
RXFIFO Occupancy increments
TXFIFO Occupancy decrements
SPIxRIF and SPIxTIF interrupts
trigger
Open RXFIFO
latch
Figure 36-8. Clocking Detail - Host Mode, CKE = 1, SMP = 1
Rev. 10-000315A
11/6/2018
MST = 1, CKE = 1, SMP = 1
A
SCK
bit 7
SDO
I
A
I
A
I
A
I
A
I
A
I
A
I
A
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
I
I
I
I
I
I
I
I
next
CKP = 0
tx_buf
write
input sample clock
A
SCK
bit 7
SDO
A
bit 6
A
bit 5
A
bit 4
A
bit 3
A
bit 2
A
bit 1
A
bit 0
I
next
CKP = 1
tx_buf
write
input sample clock
TXFIFO
determined
© 2021 Microchip Technology Inc.
Open RXFIFO
latch
Preliminary Datasheet
RXFIFO Occupancy increments
TXFIFO Occupancy decrements
SPIxRIF and SPIxTIF interrupts
trigger
DS40002213D-page 662
PIC18F27/47/57Q84
SPI - Serial Peripheral Interface Module
Figure 36-9. Clocking Detail - Host Mode, CKE = 0, SMP = 1
Rev. 10-000277A
11/6/2018
MST = 1, CKE = 0, SMP = 1
SCK
A
SDO previous bit 0
bit 7
bit 6
SCK
A
A
SDO previous bit 0
bit 7
I
A
I
A
I
A
bit 5
I
A
bit 4
I
A
bit 3
I
A
bit 2
I
bit 1
A
I
bit 0
CKP = 0
input sample clock
I
I
I
A
bit 6
A
bit 5
I
I
A
bit 4
I
A
bit 3
A
bit 2
I
bit 1
A
I
bit 0
CKP = 1
input sample clock
TXFIFO determined
Open RXFIFO latch
RXFIFO Occupancy increments,
TXFIFO Occupancy decrements,
SPIxRIF and SPIxTIF interrupts
trigger
Figure 36-10. Clocking Detail - Host Mode, CKE = 1, SMP = 0
Rev. 10-000278A
11/6/2018
MST =1, CKE = 1, SMP = 0
SCK
A I
I
SDO
bit 7
A
I
A
I
A
I
A
I
I
A
A
I
A
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
I
I
I
I
I
I
I
CKP = 0
tx_buf
write
input sample clock
SCK
I
SDO
A
bit 7
A
bit 6
A
bit 5
A
bit 4
A
bit 3
A
bit 2
A
bit 1
A
bit 0
CKP = 1
tx_buf
write
input sample clock
TXFIFO to SDO
Open RXFIFO latch
RXFIFO Occupancy increments,
TXFIFO Occupancy decrements,
SPIxRIF and SPIxTIF interrupts
trigger
36.3.6.3 SCK Start-up Delay
When starting an SPI data exchange, the host device asserts the SS output, by either setting the SSET bit or
loading the TCNT value, and then triggers the module to send data by writing SPIxTXB. These data triggers are
synchronized to the clock selected by the SPIxCLK register before the first SCK pulse appears, usually requiring one
or two clock periods of the selected SPI source clock.
The SPI module includes additional synchronization delays on SCK generation specifically designed to ensure
that the Client Select output timing is correct, without requiring precision software timing loops. By default this
synchronization delay is ½ baud period.
When the value of the SPIxBAUD register is a small number (indicating higher SCK frequencies), the code execution
delay between asserting SS and writing SPIxTXB is relatively long compared to the added synchronization delay
before the first SCK edge. With larger values of SPIxBAUD (indicating lower SCK frequencies), the code execution
delay is much smaller relative to the synchronization delay. Therefore, the first SCK edge after SS is asserted will be
closer to the synchronization delay.
Setting the FST bit removes the synchronization delay, allowing systems with low SPIxBAUD values (and thus, long
synchronization delays) to forgo this extra delay in which case the time between the SS assertion and the first SCK
edge depends entirely on the code execution delay.
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Preliminary Datasheet
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PIC18F27/47/57Q84
SPI - Serial Peripheral Interface Module
36.4
Client Mode
36.4.1
Client Mode Transmit Options
The SDO output of the SPI module in Client mode is controlled by the following:
• TXR bit
• TRIS bit associated with the SDO pin
• Client Select input
• Current state of the transmit FIFO
This control is summarized in the following table where TRISxn refers to the bit in the TRIS register corresponding to
the pin that SDO has been assigned with PPS, TXR is the Transmit Data Required Control bit, SS is the state of the
Client Select input, and TXBE is the transmit FIFO Buffer Empty bit.
Table 36-2. Client Mode Transmit
TRISxn(1)
TXR
SS
TXBE
0
0
FALSE
0
Drives state determined by LATxn(2)
0
0
FALSE
1
Drives state determined by LATxn(2)
0
0
TRUE
0
Outputs the oldest byte in the transmit
FIFO Does not remove data from the transmit FIFO
0
0
TRUE
1
Outputs the most recently received byte
0
1
FALSE
0
Drives state determined by LATxn(2)
0
1
FALSE
1
Drives state determined by LATxn(2)
0
1
TRUE
0
Outputs the oldest byte in the transmit FIFO
Removes transmitted byte from the transmit FIFO
Decrements occupancy of transmit FIFO
0
1
TRUE
1
Outputs the most recently received byte
Sets the TXUIF bit
1
0
FALSE
0
Tri-stated
1
0
FALSE
1
Tri-stated
1
0
TRUE
0
Tri-stated
1
0
TRUE
1
Tri-stated
1
1
FALSE
0
Tri-stated
1
1
FALSE
1
Tri-stated
1
1
TRUE
0
Outputs the oldest byte in the transmit FIFO
Removes transmitted byte from the transmit FIFO
Decrements the FIFO occupancy
1
1
TRUE
1
Outputs the most recently received byte
Sets the TXUIF bit
SDO State
Notes:
1. TRISxn is the bit in the TRISx register corresponding to the pin to which SDO has been assigned with PPS.
2. LATxn is the bit in the LATx register corresponding to the pin to which SDO has been assigned with PPS.
36.4.1.1 SDO Drive/Tri-state
The TRIS bit associated with the SDO pin controls whether the SDO pin will tri-state. When this TRIS bit is cleared,
the pin will always be driving to a level, even when the SPI module is inactive. When the SPI module is inactive
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(either due to the host not clocking the SCK line or the SS being false), the SDO pin will be driven to the value of
the LAT bit associated with the SDO pin. When the SPI module is active, its output is determined by both TXR and
whether there is data in the transmit FIFO.
When the TRIS bit associated with the SDO pin is set, the pin will only have an output level driven to it when TXR = 1
and the Client Select input is true. In all other cases, the pin will be tri-stated.
Table 36-3. Client Mode Transmit
TRISxn(1)
TXR
SS
TXBE
0
0
FALSE
0
Output level determined by LATxn(2)
0
0
FALSE
1
Output level determined by LATxn(2)
0
0
TRUE
0
Outputs the oldest byte in the TXFIFO
Does not remove data from the TXFIFO
0
0
TRUE
1
Outputs the most recently received byte
0
1
FALSE
0
Output level determined by LATxn(2)
0
1
FALSE
1
Output level determined by LATxn(2)
0
1
TRUE
0
Outputs the oldest byte in the TXFIFO
Removes transmitted byte from the TXFIFO
Decrements occupancy of TXFIFO
0
1
TRUE
1
Outputs the most recently received byte
Sets the TXUIF bit
1
0
FALSE
0
Tri-stated
1
0
FALSE
1
Tri-stated
1
0
TRUE
0
Tri-stated
1
0
TRUE
1
Tri-stated
1
1
FALSE
0
Tri-stated
1
1
FALSE
1
Tri-stated
1
1
TRUE
0
Outputs the oldest byte in the TXFIFO
Removes transmitted byte from the TXFIFO
Decrements occupancy of TXFIFO
1
1
TRUE
1
Outputs the most recently received byte
Sets the TXUIF bit
SDO State
Notes:
1. TRISxn is the bit in the TRISx register corresponding to the pin that SDO has been assigned with PPS.
2. LATxn is the bit in the LATx register corresponding to the pin that SDO has been assigned with PPS.
36.4.1.2 SDO Output Data
The TXR bit controls the nature of the data that is transmitted in Client mode. When TXR is set, transmitted data is
taken from the transmit FIFO. If the FIFO is empty, the most recently received data will be transmitted and the TXUIF
flag will be set to indicate that a transmit FIFO underflow has occurred.
When TXR is cleared, the data will be taken from the transmit FIFO, and the FIFO occupancy will not decrease. If
the transmit FIFO is empty, the most recently received data will be transmitted, and the TXUIF bit will not be set.
However, if the TRIS bit associated with the SDO pin is set, clearing the TXR bit will cause the SPI module to not
output any data to the SDO pin.
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36.4.2
Client Mode Receive Options
The RXR bit controls the nature of receptions in Client mode. When RXR is set, the SDI input data will be stored
in the receive FIFO if it is not full. If the receive FIFO is full, the RXOIF bit will be set to indicate a receive FIFO
overflow error and the data is discarded. When RXR is cleared, all received data will be ignored and not stored in the
receive FIFO (although it may still be used for transmission if the transmit FIFO is empty). The following figure shows
a typical Client mode communication, showing a case where the host writes two then three bytes, showing interrupts
as well as the behavior of the transfer counter in Client mode (see Transfer Counter in Client Mode for more details
on the transfer counter in Client mode as well as SPI Interrupts for more information on interrupts).
Figure 36-11. SPI Client Mode Operation – Interrupt-Driven, Host Writes 2+3 Bytes
Rev. 10-000285A
11/8/2018
SS_in
SCK_in
SDO_out
SOSIF
Note 1
Output data
Note 2
EOSIF
Transfer Counter
0
Software Write to
SPIxTCNTL
-1
-2
3
2
1
0
Note 3
TCZIF
Software Write
to TXR
TXR
Software Write to
RXR
RXR
Receiver process
SPIxRIF
Software
Read from
SPIxRXB
Note: 1. This delay is exaggerated for illustration, and can be as short as1/2 bit period.
2. If the device is sleeping, SOSIF will wake it up for interrupt service.
3. Setting SPIxTCNTL is optional in this example, otherwise it will count -3, -4, -5, and TCZIF will not occur
36.4.3
Client Mode Client Select
In Client mode, an external Client Select signal can be used to synchronize communication with the host device. The
Client Select line is held in its Inactive state (high by default) until the host device is ready to communicate. When the
Client Select transitions to its Active state, the client knows that a new transmission is starting.
When the Client Select goes false at the end of the transmission, the receive function of the selected SPI client
device returns to the Inactive state. The client is then ready to receive a new transmission when the Client Select
goes true again.
The Client Select signal is received on the SS input pin. This pin is selected with the SPIxSSPPS register (refer to the
“PPS Inputs” section). When the input on this pin is true, transmission and reception are enabled, and the SDO pin
is driven. When the input on this pin is false, the SDO pin is either tri-stated (if the TRIS bit associated with the SDO
pin is set) or driven to the value of the LAT bit associated with the SDO pin (if the TRIS bit associated with the SDO
pin is cleared). The SCK input is ignored when the SS input is false.
If the SS input goes false, while a data transfer is still in progress, it is considered a Client Select fault. The SSFLT
bit indicates whether such an event has occurred. The transfer counter value determines the number of bits in a valid
data transfer (see Transfer Counter for more details).
The Client Select polarity is controlled by the SSP bit. When SSP is set (its default state), the Client Select input is
active-low, and when it is cleared, the Client Select input is active-high.
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The Client Select for the SPI module is controlled by the SSET bit. When SSET is cleared (its default state), the
Client Select will act as described above. When the bit is set, the SPI module will behave as if the SS input is always
in its Active state.
Important:
When SSET is set, the effective SS_in signal is always active. Hence, the SSFLT bit may be disregarded.
36.4.4
Client Mode Clock Configuration
In Client mode, SCK is an input, and must be configured to the same polarity and clock edge as the host device. As
in Host mode, the polarity of the clock input is controlled by the CKP bit and the clock edge used for transmitting data
is controlled by the CKE bit.
36.4.5
Daisy-Chain Configuration
The SPI bus can be connected in a daisy-chain configuration. The first client output is connected to the second
client input, the second client output is connected to the third client input, and so on. The final client output is
connected to the host input. Each client sends out, during a second group of clock pulses, an exact copy of what
was received during the first group of clock pulses. The whole chain acts as one large communication shift register.
The daisy-chain feature only requires a single Client Select line from the host device connected to all client devices
(alternately, the client devices can be configured to ignore the Client Select line by setting the SSET bit). In a
typical daisy-chain configuration, the SCK signal from the host is connected to each of the client device SCK inputs.
However, the SCK input and output are separate signals selected by the PPS control. When the PPS selection is
made to configure the SCK input and SCK output on separate pins then, the SCK output will follow the SCK input,
allowing for SCK signals to be daisy-chained like the SDO/SDI signals.
The following two figures show block diagrams of a typical daisy-chain connection, and a daisy-chain connection with
daisy-chained SPI clocks, respectively.
Figure 36-12. Traditional SPI Daisy-Chain Connection
Rev. 10-000082B
11/8/2018
SCK
SCK
SDOx
SDIx
SDIx
SDOx
SSxOUT/GPIO
SSxIN
SPI Host
SPI Client
#1
SCK
SDIx SPI Client
#2
SDOx
SSxIN
SCK
SDIx SPI Client
#3
SDOx
SSxIN
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SPI - Serial Peripheral Interface Module
Figure 36-13. SPI Daisy-Chain Connection With Chained SCK
Rev. 10-000082C
11/8/2018
SCK(in)
SCK
SPI Host
SDOx
SPI Client
#1
SDIx
SDIx
SSxIN
SSxOUT/GPIO
SCK(out)
SDOx
SCK(in)
SDIx
SSxIN
SPI Client
#2
SCK(out)
SDOx
SCK(in)
SDIx
SSxIN SPI Client
#3
SDOx
36.5
SPI Operation In Sleep Mode
The SPI Host mode will operate in Sleep, provided the clock source selected by SPIxCLK is active in Sleep mode.
FIFOs will operate as they would when the part is awake. When TXR = 1, the transmit FIFO will need to contain data
in order for transfers to take place in Sleep. All interrupts will still set the interrupt flags in Sleep but only enabled
interrupts will wake the device from Sleep.
The SPI Client mode will operate in Sleep, because the clock is provided by an external host device. FIFOs will still
operate and interrupts will set interrupt flags, and enabled interrupts will wake the device from Sleep.
36.6
SPI Interrupts
There are three top level SPI interrupts in the PIRx register:
•
•
•
SPI Transmit (SPIxTXIF)
SPI Receive (SPIxRXIF)
SPI Module status (SPIxIF)
The SPI Module status interrupts are enabled at the module level in the SPIxINTE register. Only enabled status
interrupts will cause the single top level SPIxIF flag to be set.
36.6.1
SPI Receive Interrupt
The SPI receive interrupt is set when the receive FIFO contains data, and is cleared when the receive FIFO is empty.
The interrupt flag, SPIxRXIF, is located in one of the PIR registers. The interrupt enable, SPIxRXIE, is located in the
corresponding PIE register. The SPIxRXIF interrupt flag is read-only.
36.6.2
SPI Transmit Interrupt
The SPI Transmit interrupt is set when the transmit FIFO is not full and can accept a character, and is cleared when
the transmit FIFO is full and cannot accept a character. The interrupt flag, SPIxTXIF, is located in one of the PIR
registers. The interrupt enable, SPIxTXIE, is located in the corresponding PIE register. The SPIxTXIF interrupt flag is
read-only.
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36.6.3
SPI Status Interrupts
The SPIxIF flag is located in one of the PIR registers. This flag is set when any of the individual status flags in
SPIxINTF and their respective SPIxINTE bits are set. In order for any specific interrupt flag to interrupt normal
program flow both the SPIxIE bit, in the PIE register corresponding to the PIR register, and the specific bit in
SPIxINTE associated with that interrupt must be set.
The Status Interrupts include the following:
•
•
•
•
•
•
Shift Register Empty (SRMTIF)
Transfer Counter is Zero (TCZIF)
Start of Client Select (SOSIF)
End of Client Select (EOSIF)
Receiver Overflow (RXOIF)
Transmitter Underflow (TXUIF)
36.6.3.1 Shift Register Empty Interrupt
The Shift Register Empty interrupt flag and enable are the SRMTIF and SRMTIE bits respectively. This interrupt is
only available in Host mode and triggers when a data transfer completes and conditions are not present to start a
new transfer, as dictated by the TXR and RXR bits (see Table 36-1 for conditions for starting a new Host mode data
transfer with different TXR/ RXR settings). This interrupt will be triggered at the end of the last full bit period, after
SCK has been low for one ½-baud period. See the figure below for more details of the timing of this interrupt as well
as other interrupts. This bit will not clear itself when the conditions for starting a new transfer occur, and must be
cleared in software.
Figure 36-14. Transfer And Client Select Interrupt Timing
Rev. 10-000286A
11/8/2018
SS_in
SCK
SDO_bit_number
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SRMTIF
SOSIF
Note 3
TCZIF
EOSIF
Note
Note 3
1: SRMTIF available only in Host mode
2: Clearing of interrupt flags is shown for illustration; actual interrupt flags must be cleared in software
3: SOSIF and EOSIF are set according to SS_in, even in Host mode.
36.6.3.2 Transfer Counter is Zero Interrupt
The Transfer Counter is Zero Interrupt flag and enable are the TCZIF and TCZIE bits, respectively. This interrupt will
trigger when the transfer counter (defined by BMODE, SPIxTCNT and SPIxTWIDTH) decrements from one to zero.
See Figure 36-14 for more details on the timing of this interrupt as well as other interrupts. This bit must be cleared in
software.
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Important:
The TCZIF flag only indicates that the transfer counter has decremented from one to zero, and may not
indicate that the entire data transfer process is complete. Either poll the BUSY bit and wait for it to be
cleared or use the Shift Register Empty Interrupt (SRMTIF) to determine when a data transfer is fully
complete.
36.6.3.3 Start of Client Select and End of Client Select Interrupts
The start of Client Select Interrupt flag and enable are the SOSIF and SOSIE bits, respectively. The end of Client
Select Interrupt flag and enable are the EOSIF and EOSIE bits, respectively. These interrupts trigger at the leading
and trailing edges of the Client Select input.
The interrupts are active in both Host and Client mode, and will trigger on transitions of the Client Select input
regardless of which mode the SPI is in. In Host mode, the PPS controls will be used to assign the Client Select input
to the same pin as the Client Select output, allowing these interrupts to trigger on changes to the Client Select output.
In Client mode, changing the SSET bit can trigger these interrupts, as it changes the effective input value of Client
Select.
Both SOSIF and EOSIF must be cleared in software.
36.6.3.4 Receiver Overflow and Transmitter Underflow Interrupts
The receiver overflow interrupt triggers if data is received when the receive FIFO is already full and RXR = 1. In this
case, the data will be discarded and the RXOIF bit will be set. The Receiver Overflow Interrupt Enable bit is RXOIE.
The Transmitter Underflow Interrupt flag triggers if a data transfer begins when the transmit FIFO is empty and TXR
= 1. In this case, the most recently received data will be transmitted and the TXUIF bit will be set. The Transmitter
Underflow Interrupt Enable bit is TXUIE.
Both these interrupts will only occur in Client mode, as Host mode will not allow the receive FIFO to overflow or the
transmit FIFO to underflow.
36.7
Register Definitions: Serial Peripheral Interface
Long bit name prefixes for the SPI peripherals are shown in the table below where “x” refers to the SPI instance
number. Refer to the “Long Bit Names” section in the “Register and Bit Naming Conventions” chapter for more
information.
Table 36-4. SPI Bit Name Prefixes
Peripheral
Bit Name Prefix
SPI1
SPI1
SPI2
SPI2
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36.7.1
SPIxCON0
Name:
Address:
SPIxCON0
0x084,0x091
SPI Control Register 0
Bit
Access
Reset
7
EN
R/W
0
6
5
4
3
2
LSBF
R/W
0
1
MST
R/W
0
0
BMODE
R/W
0
Bit 7 – EN SPI Enable
Value
Description
1
SPI is enabled
0
SPI is disabled
Bit 2 – LSBF LSb-First Data Exchange Select(1)
Value
Description
1
Data is exchanged LSb first
0
Data is exchanged MSb first (traditional SPI operation)
Bit 1 – MST SPI Host Operating Mode Select(1)
Value
Description
1
SPI module operates as the bus host
0
SPI module operates as a bus client
Bit 0 – BMODE Bit-Length Mode Select(1)
Value
Description
1
SPIxTWIDTH setting applies to every byte: total bits sent is SPIxTWIDTH*SPIxTCNT, end-of-packet
occurs when SPIxTCNT = 0
0
SPIxTWIDTH setting applies only to the last byte exchanged; total bits sent is SPIxTWIDTH +
(SPIxTCNT*8)
Note:
1. Do not change this bit when EN = 1.
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36.7.2
SPIxCON1
Name:
Address:
SPIxCON1
0x085,0x092
SPI Control Register 1
Bit
Access
Reset
7
SMP
R/W
0
6
CKE
R/W
0
5
CKP
R/W
0
4
FST
R/W
0
3
2
SSP
R/W
1
1
SDIP
R/W
0
0
SDOP
R/W
0
Bit 7 – SMP SPI Input Sample Phase Control
Value
Mode
Description
1
Client
Reserved
1
Host
SDI input is sampled at the end of data output time
0
Client or Host
SDI input is sampled in the middle of data output time
Bit 6 – CKE Clock Edge Select
Value
Description
1
Output data changes on transition from Active to Idle clock state
0
Output data changes on transition from Idle to Active clock state
Bit 5 – CKP Clock Polarity Select
Value
Description
1
Idle state for SCK is high level
0
Idle state for SCK is low level
Bit 4 – FST Fast Start Enable
Value
MODE
Description
x
Client
This bit is ignored
1
Host
Delay to first SCK may be less than ½ baud period
0
Host
Delay to first SCK will be at least ½ baud period
Bit 2 – SSP Client Select Input/Output Polarity Control
Value
Description
1
SS is active-low
0
SS is active-high
Bit 1 – SDIP SPI Input Polarity Control
Value
Description
1
SDI input is active-low
0
SDI input is active-high
Bit 0 – SDOP SPI Output Polarity Control
Value
Description
1
SDO output is active-low
0
SDO output is active-high
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36.7.3
SPIxCON2
Name:
Address:
SPIxCON2
0x086,0x093
SPI Control Register 2(3)
Bit
Access
Reset
7
BUSY
R
0
6
SSFLT
R
0
5
4
3
2
SSET
R/W
0
1
TXR
R/W
0
0
RXR
R/W
0
Bit 7 – BUSY SPI Module Busy Status(1)
Value
Description
1
Data exchange is busy
0
Data exchange is not taking place
Bit 6 – SSFLT SS_in Fault Status
Value
Condition Description
x
SSET = 1 This bit is unchanged
1
SSET = 0 SS_in ended the transaction unexpectedly, and the data byte being received was lost
0
SSET = 0 SS_in ended normally
Bit 2 – SSET Client Select Enable
Value
MODE Description
1
Host
SS_out is driven to the Active state continuously
0
Host
SS_out is driven to the Active state while the transmit counter is not zero
1
Client SS_in is ignored and data is clocked on all SCK_in (as though SS = TRUE at all times)
0
Client SS_in enables/disables data input and tri-states SDO if the TRIS bit associated with the SDO
pin is set (see Client Mode Transmit table for details)
Bit 1 – TXR Transmit Data-Required Control(2)
Value
Description
1
TxFIFO data is required for a transfer
0
TxFIFO data is not required for a transfer
Bit 0 – RXR Receive FIFO Space-Required Control(2)
Value
Description
1
Data transfers are suspended when the RxFIFO is full
0
Received data is not stored in the FIFO
Notes:
1. The BUSY bit is subject to synchronization delay of up to two instruction cycles. The user must wait after
loading the transmit buffer (SPIxTXB register) before using it to determine the status of the SPI module.
2. See Host Mode TXR/RXR Settings table as well as section Host Mode and section Client Mode for more
details pertaining to TXR and RXR function.
3. This register will not be written to while a transfer is in progress (BUSY bit is set).
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36.7.4
SPIxCLK
Name:
Address:
SPIxCLK
0x08C,0x099
SPI Clock Selection Register
Bit
7
6
5
Access
Reset
4
3
R/W
0
R/W
0
2
CLKSEL[4:0]
R/W
0
1
0
R/W
0
R/W
0
Bits 4:0 – CLKSEL[4:0] SPI Clock Source Selection
Table 36-5. SPI CLK Source Selections
CLK
Selection
10111-11111
10110
10101
10100
10011
10010
10001
10000
01111
01110
01001-01111
01110
01101
01000
00111
00110
00101
00100
00011
00010
00001
00000
Reserved
CLC8_OUT
CLC7_OUT
CLC6_OUT
CLC5_OUT
CLC4_OUT
CLC3_OUT
CLC2_OUT
CLC1_OUT
SMT1_OUT
Reserved
TU16B_OUT
TU16A_OUT
TMR6_Postscaler_OUT
TMR4_Postscaler_OUT
TMR2_Postscaler_OUT
TMR0_OUT
Clock Reference Output
EXTOSC
MFINTOSC (500 kHz)
HFINTOSC
FOSC (System Clock)
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36.7.5
SPIxBAUD
Name:
Address:
SPIxBAUD
0x089,0x096
SPI Baud Rate Register
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BAUD[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – BAUD[7:0] Baud Clock Prescaler Select
Value
Description
n
SCK high or low time: TSC = SPI Clock Period*(n+1)
SCK toggle frequency: FSCK = FBAUD = SPI Clock Frequency/(2*(n+1))
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36.7.6
SPIxTCNT
Name:
Address:
SPIxTCNT
0x082,0x08F
SPI Transfer Counter Register
Bit
15
14
13
12
11
R/W
0
9
TCNTH[2:0]
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
7
6
5
4
10
8
TCNTL[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 10:8 – TCNTH[2:0] SPI Transfer Counter Most Significant Byte
Value
Condition
Description
n
BMODE = 0
Bits 13-11 of the transfer bit count
n
BMODE = 1
Bits 10-8 of the transfer byte count
Bits 7:0 – TCNTL[7:0] SPI Transfer Counter Least Significant Byte
Value
Condition
Description
n
BMODE = 0
Bits 10-3 of the transfer bit count
n
BMODE = 1
Bits 7-0 of the transfer byte count
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SPI - Serial Peripheral Interface Module
36.7.7
SPIxTWIDTH
Name:
Address:
SPIxTWIDTH
0x088,0x095
SPI Transfer Width Register
Bit
7
6
5
4
3
Access
Reset
2
R/W
0
1
TWIDTH[2:0]
R/W
0
0
R/W
0
Bits 2:0 – TWIDTH[2:0] SPI Transfer Count Byte Width or 3 LSbs of the Transfer Bit Count
Value
Condition
Description
n
BMODE = 0 Bits 2-0 of the transfer bit count
n
BMODE = 1 Number of bits in each transfer byte count. Bits = n (when n > 0) or 8 (when n = 0).
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36.7.8
SPIxSTATUS
Name:
Address:
SPIxSTATUS
0x087,0x094
SPI Status Register
Bit
Access
Reset
7
TXWE
R/C/HS
0
6
5
TXBE
R
1
4
3
RXRE
R/C/HS
0
2
CLB
S
0
1
0
RXBF
R
0
Bit 7 – TXWE Transmit Buffer Write Error
Value
Description
1
SPIxTXB was written while TxFIFO was full
0
No error has occurred
Bit 5 – TXBE Transmit Buffer Empty
Value
Description
1
Transmit buffer TxFIFO is empty
0
Transmit buffer is not empty
Bit 3 – RXRE Receive Buffer Read Error
Value
Description
1
SPIxRXB was read while RxFIFO was empty
0
No error has occurred
Bit 2 – CLB Clear Buffer Control
Value
Description
1
Reset the receive and transmit buffers, making both buffers empty
0
Take no action
Bit 0 – RXBF Receive Buffer Full
Value
Description
1
Receive buffer is full
0
Receive buffer is not full
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 678
PIC18F27/47/57Q84
SPI - Serial Peripheral Interface Module
36.7.9
SPIxRXB
Name:
Address:
SPIxRXB
0x080,0x08D
SPI Receive Buffer
Bit
7
6
5
4
3
2
1
0
R
x
R
x
R
x
R
x
RXB[7:0]
Access
Reset
R
x
R
x
R
x
Bits 7:0 – RXB[7:0] Receive Buffer
Value
Condition
n
Receive buffer is not
empty
0
Receive buffer is empty
© 2021 Microchip Technology Inc.
R
x
Description
Contains the top-most byte of the RXFIFO. Reading this register will remove
the RXFIFO top-most byte and decrease the occupancy of the RXFIFO by
1.
Reading this register will return ‘0’, leave the occupancy unchanged, and set
the RXRE Status bit
Preliminary Datasheet
DS40002213D-page 679
PIC18F27/47/57Q84
SPI - Serial Peripheral Interface Module
36.7.10 SPIxTXB
Name:
Address:
SPIxTXB
0x081,0x08E
SPI Transmit Buffer
Bit
7
6
5
4
3
2
1
0
W
x
W
x
W
x
W
x
TXB[7:0]
Access
Reset
W
x
W
x
W
x
Bits 7:0 – TXB[7:0] Transmit Buffer
Value
Condition
n
Transmit buffer is not
full
x
Transmit buffer is full
© 2021 Microchip Technology Inc.
W
x
Description
Writing to this register adds the data to the top of the TXFIFO and increases
the occupancy of the TXFIFO by 1.
Writing to this register does not affect the data in the TXFIFO or the
occupancy count. The TXWE Status bit will be set.
Preliminary Datasheet
DS40002213D-page 680
PIC18F27/47/57Q84
SPI - Serial Peripheral Interface Module
36.7.11 SPIxINTE
Name:
Address:
SPIxINTE
0x08B,0x098
SPI Interrupt Enable Register
Bit
Access
Reset
7
SRMTIE
R/W
0
6
TCZIE
R/W
0
5
SOSIE
R/W
0
4
EOSIE
R/W
0
3
2
RXOIE
R/W
0
1
TXUIE
R/W
0
0
Bit 7 – SRMTIE Shift Register Empty Interrupt Enable
Value
Description
1
Interrupt is enabled
0
Interrupt is not enabled
Bit 6 – TCZIE Transfer Counter is Zero Interrupt Enable
Value
Description
1
Interrupt is enabled
0
Interrupt is not enabled
Bit 5 – SOSIE Start of Client Select Interrupt Enable
Value
Description
1
Interrupt is enabled
0
Interrupt is not enabled
Bit 4 – EOSIE End of Client Select Interrupt Enable
Value
Description
1
Interrupt is enabled
0
Interrupt is not enabled
Bit 2 – RXOIE Receiver Overflow Interrupt Enable
Value
Description
1
Interrupt is enabled
0
Interrupt is not enabled
Bit 1 – TXUIE Transmitter Underflow Interrupt Enable
Value
Description
1
Interrupt is enabled
0
Interrupt is not enabled
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 681
PIC18F27/47/57Q84
SPI - Serial Peripheral Interface Module
36.7.12 SPIxINTF
Name:
Address:
SPIxINTF
0x08A,0x097
SPI Interrupt Flag Register
Bit
Access
Reset
7
SRMTIF
R/W/HS
0
6
TCZIF
R/W/HS
0
5
SOSIF
R/W/HS
0
4
EOSIF
R/W/HS
0
3
2
RXOIF
R/W/HS
0
1
TXUIF
R/W/HS
0
0
Bit 7 – SRMTIF Shift Register Empty Interrupt Flag
Value
MODE
Description
x
Client
This bit is ignored
1
Host
The data transfer is complete
0
Host
Either no data transfers have occurred or a data transfer is in progress
Bit 6 – TCZIF Transfer Counter is Zero Interrupt Flag
Value
Description
1
The transfer counter has decremented to zero
0
No interrupt pending
Bit 5 – SOSIF Start of Client Select Interrupt Flag
Value
Description
1
SS_in transitioned from false to true
0
No interrupt pending
Bit 4 – EOSIF End of Client Select Interrupt Flag
Value
Description
1
SS_in transitioned from true to false
0
No interrupt pending
Bit 2 – RXOIF Receiver Overflow Interrupt Flag
Value
Description
1
Data transfer completed when RXBF = 1 (edge-triggered) and RXR = 1
0
No interrupt pending
Bit 1 – TXUIF Transmitter Underflow Interrupt Flag
Value
Description
1
Client Data transfer started when TXBE = 1 and TXR = 1
0
No interrupt pending
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 682
PIC18F27/47/57Q84
SPI - Serial Peripheral Interface Module
36.8
Address
0x00
...
0x7F
0x80
0x81
Register Summary - SPI Control
Name
Bit Pos.
7
6
5
4
3
2
RXRE
LSBF
SSP
SSET
CLB
1
0
Reserved
SPI1RXB
SPI1TXB
0x82
SPI1TCNT
0x84
0x85
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
SPI1CON0
SPI1CON1
SPI1CON2
SPI1STATUS
SPI1TWIDTH
SPI1BAUD
SPI1INTF
SPI1INTE
SPI1CLK
SPI2RXB
SPI2TXB
0x8F
SPI2TCNT
0x91
0x92
0x93
0x94
0x95
0x96
0x97
0x98
0x99
SPI2CON0
SPI2CON1
SPI2CON2
SPI2STATUS
SPI2TWIDTH
SPI2BAUD
SPI2INTF
SPI2INTE
SPI2CLK
7:0
7:0
7:0
15:8
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
15:8
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
RXB[7:0]
TXB[7:0]
TCNTL[7:0]
EN
SMP
BUSY
TXWE
CKE
SSFLT
CKP
FST
TXBE
TCNTH[2:0]
MST
SDIP
TXR
BMODE
SDOP
RXR
RXBF
TWIDTH[2:0]
SRMTIF
SRMTIE
TCZIF
TCZIE
SOSIF
SOSIE
BAUD[7:0]
EOSIF
EOSIE
RXOIF
RXOIE
CLKSEL[4:0]
TXUIF
TXUIE
RXB[7:0]
TXB[7:0]
TCNTL[7:0]
EN
SMP
BUSY
TXWE
CKE
SSFLT
CKP
TXBE
FST
RXRE
LSBF
SSP
SSET
CLB
TCNTH[2:0]
MST
SDIP
TXR
BMODE
SDOP
RXR
RXBF
TWIDTH[2:0]
SRMTIF
SRMTIE
© 2021 Microchip Technology Inc.
TCZIF
TCZIE
SOSIF
SOSIE
BAUD[7:0]
EOSIF
EOSIE
Preliminary Datasheet
RXOIF
RXOIE
CLKSEL[4:0]
TXUIF
TXUIE
DS40002213D-page 683
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.
I2C - Inter-Integrated Circuit Module
The Inter-Integrated Circuit (I2C) bus is a multi-host serial data communication bus. Devices communicate in a
host/client environment where the host devices initiate the communication. A client device is controlled through
addressing.
The following figure shows a block diagram of the I2C interface module, and shows both Host and Client modes
together.
Figure 37-1. I2C Block Diagram
I2CxADR0/1/2/3
TH
(See RxyI2C Register)
I2CxSDAPPS
SDA
(in)
CLK
See
I2CxCLK
Register
ABD
(See I2CxCON2
Register)
SDAHT
(See I2CxCON2 Register)
I2CxADB0/1
Address compare
TX Shift
Register
RX Shift
Register
Receive Buffer
I2CxRXB
ABD
(See I2CxCON2
Register)
I2CxADB0/1
SDA
(out)
RxyPPS
Transmit
Buffer
I2CxTXB
I2C Control Unit
See
I2CxBTO
Register
SCL
(in)
RxyPPS
BTO
Client
Module
I2CxSCLPPS
TH
(See RxyI2C Register)
37.1
SCL
(out)
Host
Module
Interrupt
Controller
I2CxPIR
I2C Features
The I2C supports the following modes and features:
•
•
Modes
– Host mode
– Client mode
– Multi-Host mode
Features
– Supports Standard mode (100 kHz), Fast mode (400 kHz) and Fast mode Plus (1 MHz) modes of operation
– Dedicated Address, Receive, and Transmit buffers
– Up to four unique Client addresses
– General Call addressing
– 7-bit and 10-bit addressing with optional masking
– Interrupts for:
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Preliminary Datasheet
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PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
–
–
–
–
–
–
–
37.2
• Start condition
• Restart condition
• Stop condition
• Address match
• Data Write
• Acknowledge Status
• NACK detection
• Data Byte Count
• Bus Collision
• Bus Time-out
Clock Stretching for:
• RX buffer full
• TX buffer empty
• Incoming address match
• Data Write
• Acknowledge Status
Bus Collision Detection with Arbitration
Bus Time-out Detection
• Selectable clock sources
• Clock prescaler
Selectable Serial Data (SDA) Hold Time
Dedicated I2C Pad (I/O) Control
• Standard GPIO or I2C-specific slew rate control
• Selectable I2C pull-up levels
• I2C-specific, SMBus 2.0/3.0, or standard GPIO input threshold level selections
Integrated Direct Memory Access (DMA) support
Remappable pin locations using Peripheral Pin Select (PPS)
I2C Terminology
The I2C communication protocol terminology used throughout this document have been adapted from the Phillips I2C
Specification and can be found in the table below.
I2C Bus Terminology and Definitions
Term
Definition
Host
The device that initiates a transfer, generates the clock signal and terminates a transfer
Client
The device addressed by the host
Multi-Host
A bus containing more than one host device that can initiate communication
Transmitter
The device that shifts data out onto the bus
Receiver
The device that shifts data in from the bus
Arbitration
Procedure that ensures only one host at a time controls the bus
Synchronization
Procedure that synchronizes the clock signal between two or more devices on the bus
Idle
The state in which no activity occurs on the bus and both bus lines are at a high logic level
Active
The state in which one or more devices are communicating on the bus
Matching Address The address byte received by a client that matches the value that is stored in the
I2CxADR0/1/2/3 registers
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PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.3
Addressed Client
Client device that has received a matching address and is actively being clocked by a host
device
Write Request
Host transmits an address with the R/W bit clear indicating that it wishes to transmit data to a
client device
Read Request
Host transmits an address with the R/W bit set indicating that it wishes to receive data from a
client device
Clock Stretching
The action in which a device holds the SCL line low to stall communication
Bus Collision
Occurs when the module samples the SDA line and returns a low state while expecting a high
state
Bus Time-out
Occurs whenever communication stalls for a period longer than acceptable
I2C Module Overview
The I2C module provides a synchronous serial interface between the microcontroller and other I2C-compatible
devices using a bidirectional two-wire bus. Devices operate in a host/client environment that may contain one or more
host devices and one or more client devices. The host device always initiates communication.
The I2C bus consists of two signal connections:
•
•
Serial Clock (SCL)
Serial Data (SDA)
Both the SCL and SDA connections are open-drain lines, each line requiring pull-up resistors to the application’s
supply voltage. Pulling the line to ground is considered a logic ‘0’, while allowing the line to float is considered a logic
‘1’. It is important to note that the voltage levels of the logic low and logic high are not fixed and are dependent on
the bus supply voltage. According to the I2C Specification, a logic low input level is up to 30% of VDD (VIL ≤ 0.3VDD),
while the logic high input level is 70% to 100% of VDD (VIH ≥ 0.7VDD). Both signal connections are considered
bidirectional, although the SCL signal can only be an output in Host mode and an input in Client mode.
All transactions on the bus are initiated and terminated by the host device. Depending on the direction of the data
being transferred, there are four main operations performed by the I2C module:
•
•
•
•
Host Transmit: host is transmitting data to a client
Host Receive: host is receiving data from a client
Client Transmit: client is transmitting data to a host
Client Receive: client is receiving data from a host
The I2C interface allows for a multi-host bus, meaning that there can be several host devices present on the bus. A
host can select a client device by transmitting a unique address on the bus. When the address matches a client’s
address, the client responds with an Acknowledge condition (ACK), and communication between the host and that
client can commence. All other devices connected to the bus must ignore any transactions not intended for them.
The following figure shows a typical I2C bus configuration with one host and two clients.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
Figure 37-2. I2C Host-Client Connections
Receive Buffer
Receive Buffer
Shift Register
SDA
SDA
Shift Register
SCK
Transmit Buffer
I2C Client 1
Transmit Buffer
SCK
Receive Buffer
I2C Host
SDA
SCK
Shift Register
Transmit Buffer
I2C Client 2
37.3.1
Byte Format
As previously mentioned, all I2C communication is performed in 9-bit segments. The transmitting device sends a byte
to a receiver, and once the byte is processed by the receiver, the receiver returns an Acknowledge bit. There are no
limits to the amount of data bytes in a I2C transmission.
After the 8th falling edge of the SCL line, the transmitting device releases control of the SDA line to allow the receiver
to respond with either an Acknowledge (ACK) sequence or a Not Acknowledge (NACK) sequence. At this point, if the
receiving device is a client, it can hold the SCL line low (clock stretch) to allow itself time to process the incoming
byte. Once the byte has been processed, the receiving device releases the SCL line, allowing the host device to
provide the 9th clock pulse, within which the client responds with either an ACK or a NACK sequence. If the receiving
device is a host, it may also hold the SCL line low until it has processed the received byte. Once the byte has been
processed, the host device will generate the 9th clock pulse and transmit the ACK or NACK sequence.
Data is valid to change only while the SCL signal is in a low state, and sampled on the rising edge of SCL. Changes
on the SDA line while the SCL line is high indicate either a Start or Stop condition.
37.3.2
SDA and SCL Pins
The SDA and SCL pins must be configured as open-drain outputs. Open-drain configuration is accomplished by
setting the appropriate bits in the Open-Drain Control (ODCONx) registers, while output direction configuration is
handled by clearing the appropriate bits in the Tri-State Control (TRISx) registers. Input threshold, slew rate, and
internal pull-up settings are configured using the RxyI2C registers. The RxyI2C registers are used exclusively on the
default I2C pin locations, and provide the following selections:
•
Input threshold levels:
– SMBus 3.0 (1.35V) input threshold
– SMBus 2.0 (2.1V) input threshold
– I2C-specific input thresholds
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Preliminary Datasheet
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PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
•
•
– Standard GPIO input thresholds (controlled by the Input Level Control (INLVLx) registers)
Slew rate limiting:
– I2C-specific slew rate limiting
– Standard GPIO slew rate (controlled by the Slew Rate Control (SLRCONx) registers)
2
I C pull-ups:
– Programmable ten or two times the current of the standard internal pull-up
– Standard GPIO pull-up (controlled by the Weak Pull-Up Control (WPUx) registers)
Important: The pin locations for SDA and SCL are remappable through the Peripheral Pin Select (PPS)
registers. If new pin locations for SDA and SCL are desired, user software must configure the INLVLx,
SLRCONx, ODCONx, and TRISx registers for each new pin location. The RxyI2C registers cannot be
used since they are dedicated to the default pin locations. Additionally, the internal pull-ups for non-I2C
pins are not strong enough to drive the pins; therefore, external pull-up resistors must be used.
37.3.2.1
Filename:
Title:
Last Edit:
First
Used:
SDA
Hold
Time
Notes:
SDA Hold Time.vsdx
11/15/2018
SDA hold time refers to the amount of time between the low threshold region of the falling edge of SCL (VIL ≤ 0.3VDD)
and either the low threshold region of the rising edge of SDA (VIL ≤ 0.3VDD) or the high threshold region of the falling
edge of SDA (VIH ≥ 0.7VDD) (see figure below). If the SCL fall time is long or close to the maximum allowable time set
by the I2C Specification, data may be sampled in the undefined logic state between the 70% and 30% region of the
falling SCL edge, leading to data corruption. The I2C module offers selectable SDA hold times, which can be useful to
ensure valid data transfers at various bus data rates and capacitance loads.
Figure 37-3. SDA Hold Time
VIH
0.7VDD
Change of
data allowed
SCL
VIL
0.3VDD
VIH
SDA
SDA Hold
Time
VIL
37.3.3
0.7VDD
0.3VDD
Start Condition
All I2C transmissions begin with a Start condition. The Start condition is used to synchronize the SCL signals
between the host and client devices. The I2C Specification defines a Start condition as a transition of the SDA line
from a logic high level (Idle state) to a logic low level (Active state) while the SCL line is at a logic high (see figure
below). A Start condition is always generated by the host, and is initiated by either writing to the Start (S) bit or by
writing to the I2C Transmit Buffer (I2CxTXB) register, depending on the Address Buffer Disable (ABD) bit setting.
When the I2C module is configured in Host mode, module hardware waits until the bus is free (Idle state). Module
hardware checks the Bus Free Status (BFRE) bit to ensure the bus is Idle before initiating a Start condition. When the
BFRE bit is set, the bus is considered Idle, and indicates that the SCL and SDA lines have been in a Logic High state
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
Filename:
Start Condition.vsdx
for the amount of I2C clock cycles as selected by the Bus Free Time Selection (BFRET) bits. When a Start condition
Title:
is detected on the Last
bus,Edit:
module hardware
clears the BFRE bit, indicating an active bus.
11/15/2018
First
In Multi-Host mode,
it isUsed:
possible for two host devices to issue Start conditions at the same time. If two or more
Notes:
hosts initiate a Start at the same time, a bus collision will occur; however, the I2C Specification states that a bus
collision cannot occur on a Start. In this case, the competing host devices must go through bus arbitration during the
addressing phase.
The figure below shows a Start condition.
Figure 37-4. Start Condition
Start
Condition
SDA
SCL
37.3.4
Acknowledge Sequence
The 9th SCL pulse for any transferred address/data byte is reserved for the Acknowledge (ACK) sequence. During
an Acknowledge sequence, the transmitting device relinquishes control of the SDA line to the receiving device. At this
time, the receiving device must decide whether to pull the SDA line low (ACK) or allow the line to float high (NACK).
Since the Acknowledge sequence is an active-low signal, pulling the SDA line low informs the transmitter that the
receiver has successfully received the transmitted data.
The Acknowledge Data (ACKDT) bit holds the value to be transmitted during an Acknowledge sequence while the
I2CxCNT register is nonzero (I2CxCNT != 0). When a client device receives a matching address, or a receiver
receives valid data, the ACKDT bit is cleared by user software to indicate an ACK. If the client does not receive
a matching address, user software sets the ACKDT bit, indicating a NACK. In Client or Multi-Host modes, if the
Address Interrupt and Hold Enable (ADRIE) or Write Interrupt and Hold Enable (WRIE) bits are set, the clock is
stretched after receiving a matching address or after the 8th falling edge of SCL when a data byte is received. This
allows user software time to determine the ACK/NACK response to send back to the transmitter.
The Acknowledge End of Count (ACKCNT) bit holds the value that will be transmitted once the I2CxCNT register
reaches a zero value (I2CxCNT = 0). When the I2CxCNT register reaches a zero value, the ACKCNT bit can be
cleared (ACKCNT = 0), indicating an ACK, or ACKCNT can be set (ACKCNT = 1), indicating a NACK.
Important: The ACKCNT bit is only used when the I2CxCNT register is zero, otherwise the ACKDT bit is
used for ACK/NACK sequences.
In Host Write or Client Read modes, the Acknowledge Status (ACKSTAT) bit holds the result of the Acknowledge
sequence transmitted by the receiving device. The ACKSTAT bit is cleared when the receiver sends an ACK, and is
set when the receiver does not Acknowledge (NACK).
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Preliminary Datasheet
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PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
The Acknowledge Time Status (ACKT) bit indicates whether or not the bus is in an Acknowledge sequence. The
ACKT bit is set during an ACK/NACK sequence on the 8th falling edge of SCL, and is cleared on the 9th rising edge
of SCL, indicating that the bus is not in an ACK/NACK sequence.
Certain conditions will cause a NACK sequence to be sent automatically. A NACK sequence is generated by module
hardware when any of the following bits are set:
•
•
•
•
Transmit Write Error Status (TXWE)
Transmit Underflow Status (TXU)
Receive Read Error Status (RXRE)
Receive Overflow Status (RXO)
Filename:
Title:
Last Edit:
First Used:
Notes:
Acknowledge Sequence.vsdx
1/8/2019
Important:
Once a NACK is detected on the bus, all subsequent Acknowledge sequences will consist of
a NACK until all error conditions are cleared.
The following figure shows ACK and NACK sequences.
Figure 37-5. ACK/NACK Sequences
Rev. Acknowledg
1/8/2019
8th falling
edge
9th rising
edge
SCL
9th rising
edge
SCL
Acknowledge
(ACK)
SDA
37.3.5
8th falling
edge
SDA
Not Acknowledge
(NACK)
Restart Condition
A Restart condition is essentially the same as a Start condition – the SDA line transitions from an idle level to an
active level while the SCL line is Idle – but may be used in place of a Stop condition whenever the host device has
completed its current transfer but wishes to keep control of the bus. A Restart condition has the same effect as a
Start condition, resetting all client logic and preparing it to receive an address.
A Restart condition is also used when the host wishes to use a combined data transfer format. A combined data
transfer format is used when a host wishes to communicate with a specific register address or memory location.
In a combined format, the host issues a Start condition, followed by the client’s address, followed by a data byte
which represents the desired client register or memory address. Once the client address and data byte have been
acknowledged by the client, the host issues a Restart condition, followed by the client address. If the host wishes to
write data to the client, the LSb of the client address, the Read/not Write (R/W) bit, will be clear. If the host wishes
to read data from the client, the R/W bit will be set. Once the client has acknowledged the second address byte, the
host issues a Restart condition, followed by the upper byte of the client address with the R/W bit set. Client logic will
then acknowledge the upper byte, and begin to transmit data to the host.
Important: In 10-bit Client mode, a Restart is required for the host to read data out of the client,
regardless of which data transfer format is used – host read-only or combined. For example, if the host
wishes to perform a bulk read, it will transmit the client’s 10-bit address with the R/W bit clear.
The figure below shows a Restart condition.
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Preliminary Datasheet
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PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
Figure 37-6. Restart Condition
Restart
Condition
SDA
SCL
37.3.6
Filename:
Stop condition.vsdx
Title:
Stop Condition Last Edit:
11/15/2018
First
Used:
All I2C transmissions
end
with a Stop condition. A Stop condition occurs when the SDA line transitions from a logic
low (active) level to Notes:
a logic high (idle) level while the SCL line is at a logic high level. A Stop condition is always
generated by the host device, and is generated by module hardware when a Not Acknowledge (NACK) is detected
on the bus, a bus time-out event occurs, or when the I2C Byte Count (I2CxCNT) register reaches a zero count. A
Stop condition may also be generated through software by setting the Stop (P) bit.
The figure below shows a Stop condition.
Figure 37-7. Stop Condition
SCL
Stop
Condition
SDA
37.3.7
Bus Time-Out
The SMBus protocol requires a bus watchdog to prevent a stalled device from holding the bus indefinitely. The I2C
Bus Time-Out Clock Source Selection (I2CxBTOC) register provides several clock sources that can be used as the
time-out time base. The I2C Bus Time-Out (I2CxBTO) register is used to determine the actual bus time-out time
period, as well as how the module responds to a time-out.
The bus time-out hardware monitors for the following conditions:
• SCL = 0 (regardless of whether or not the bus is Active)
•
SCL = 1 and SDA = 0 while the bus is Active
If either of these conditions are true, an internal time-out counter increments, and continues to increment as long
as the condition stays true, or until the time-out period has expired. If these conditions change (e.g. SCL = 1), the
internal time-out counter is reset by module hardware.
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I2C - Inter-Integrated Circuit Module
The Bus Time-Out Clock Source Selection (BTOC) bits select the time-out clock source. If an oscillator is selected as
the time-out clock source, such as the LFINTOSC, the time-out clock base period is approximately 1 ms. If a timer is
selected as the time-out clock source, the timer can be configured to produce a variety of time periods.
Remember: The SMBus protocol dictates a 25 ms time-out for client devices and a 35 ms time-out for
host devices.
The Time-Out Time Selection (TOTIME) bits and the Time-Out Prescaler Extension Enable (TOBY32) bit are used to
determine the time-out period. The value written into TOTIME multiplies the base time-out clock period. For example,
if a value of ‘35’ is written into the TOTIME bits, and the LFINTOSC is selected as the time-out clock source, the
time-out period is approximately 35 ms (35 x 1 ms). If the TOBY32 bit is set (TOBY32 = 1), the time-out period
determined by the TOTIME bits is multiplied by 32. If TOBY32 is clear (TOBY32 = 0), the time-out period determined
by the TOTIME bits is used as the time-out period.
The examples below illustrate possible time-out configurations.
Example 37-1. 35 ms BTO Period Configuration
void Init_BTO_35(void)
{
I2C1BTOC = 0x06;
I2C1BTObits.TOREC = 1;
BTOIF
I2C1BTObits.TOBY32 = 0;
I2C1BTObits.TOTIME = 0x23;
// Selections produce a 35 ms BTO period
// LFINTOSC as BTO clock source
// Reset I2C interface, set
// BTO time = TOTIME * TBTOCLK
// TOTIME = TBTOCLK * 35
// = 1 ms * 35 = 35 ms
}
Example 37-2. 64 ms BTO Configuration
void Init_BTO_64(void)
// Selections produce a 64 ms BTO period
{
I2C1BTOC = 0x06;
// LFINTOSC as BTO clock source
I2C1BTObits.TOREC = 1;
// Reset I2C interface, set BTOIF
I2C1BTObits.TOBY32 = 1;
// BTO time = TOTIME * TBTOCLK * 32
// = 2 ms * 32 = 64 ms
I2C1BTObits.TOTIME = 0x02;
// TOTIME = TBTOCLK * 2
// = 1 ms * 2 = 2 ms
}
The Time-Out Recovery Selection (TOREC) bit determines how the module will respond to a bus time-out. When
a bus time-out occurs and TOREC is set (TOREC = 1), the I2C module is reset and module hardware sets the
Bus Time-Out Interrupt Flag (BTOIF). If the Bus Time-Out Interrupt Enable (BTOIE) is also set, an interrupt will be
generated. If a bus time-out occurs and TOREC is clear (TOREC = 0), the BTOIF bit is set, but the module is not
reset.
If the module is configured in Client mode with TOREC set (TOREC = 1), and a bus time-out event occurs
(regardless of the state of the Client Mode Active (SMA) bit), the module is immediately reset, the SMA and Client
Clock Stretching (CSTR) bits are cleared, and the Bus Time-Out Interrupt Flag (BTOIF) bit is set.
If the module is configured in Client mode with TOREC clear (TOREC = 0), and a bus time-out event occurs
(regardless of the state of the Client Mode Active (SMA) bit), the BTOIF bit is set, but user software must reset the
module.
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Preliminary Datasheet
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I2C - Inter-Integrated Circuit Module
Important: It is recommended to set TOREC (TOREC = 1) when operating in Client mode.
If the module is configured in Host mode with TOREC set (TOREC = 1), and the bus time-out event occurs while the
Host is active (Host Mode Active (MMA) = 1), the Host Data Ready (MDR) bit is cleared, the module will immediately
attempt to transmit a Stop condition, and sets the BTOIF bit. Stop condition generation may be delayed if a client
device is stretching the clock, but will resume once the clock is released, or if the client holding the bus also has a
time-out
event occur.
The MMA bit is only cleared after the Stop condition has been generated.
Filename:
Host Mode BTO Event Example .vsdx
Title:
If the
module is configured
in Host mode with TOREC clear (TOREC = 0), and the bus time-out event occurs while
Last Edit:
1/9/2019
theFirst
Host
is active (Host Mode Active (MMA) = 1), the MDR bit is cleared and the BTOIF bit is set, but user software
Used:
Notes:
must
initiate the Stop condition by setting the P bit.
The figure below shows an example of a Bus Time-Out event when the module is operating in Host mode.
Figure 37-8. Host Mode Bus Time-Out Example
Client releases SCL,
Host begins Stop
SDA
SCL
D0
8
Host waits
for ACK/NACK
I2CxTXIF = 1
TXBE = 1
Host attempts to issue Stop ,
but must wait until SCL = 1
Enable Timer2
T2_Postscaled_out
BTOIF = 1
T2TMR_T2PR_Match
TMR2IF = 1
Software
clears BTOIF,
TMR2IF
Hardware clears MMA
MMA
37.3.8
Stop detected
PCIF = 1
Address Buffers
The I2C module has two address buffer registers, I2CxADB0 and I2CxADB1, which can be used as address receive
buffers in Client mode, address transmit buffers in Host mode, or both address transmit and address receive buffers
in 7-bit Multi-Host mode (see table below). The address buffers are enabled/disabled via the Address Buffer Disable
(ABD) bit.
When the ABD bit is clear (ABD = 0), the buffers are enabled, which means:
•
•
•
In 7-bit Host mode, the desired client address with the R/W value is transmitted from the I2CxADB1 register,
bypassing the I2C Transmit Buffer (I2CxTXB). I2CxADB0 is unused.
In 10-bit Host mode, I2CxADB1 holds the upper bits and R/W value of the desired client address, while
I2CxADB0 holds the lower eight bits of the desired client address. Host hardware copies the contents of
I2CxADB1 to the transmit shift register, and waits for an ACK from the client. Once the ACK is received, host
hardware copies the contents of I2CxADB0 to the transmit shift register.
In 7-bit Client mode, a matching received address is loaded into I2CxADB0, bypassing the I2C Receive Buffer
(I2CxRXB). I2CxADB1 is unused.
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I2C - Inter-Integrated Circuit Module
•
•
In 10-bit Client mode, I2CxADB0 is loaded with the lower eight bits of the matching received address, while
I2CxADB1 is loaded with the upper bits and R/W value of the matching received address.
In 7-bit Multi-Host mode, the device can be both a host and a client depending on the sequence of events on the
bus. When being addressed as a client, the matching received address with R/W value is stored into I2CxADB0.
When being used as a host, the desired client address and R/W value are loaded into the I2CxADB1 register.
When the ABD bit is set (ABD = 1), the buffers are disabled, which means:
•
•
In Host mode, the desired client address is transmitted from the I2CxTXB register.
In Client mode, a matching received address is loaded into the I2CxRXB register.
Table 37-1. Address Buffer Direction
37.3.9
Mode
I2CxADB0
I2CxADB1
Client (7-bit)
RX
Unused
Client (10-bit)
RX (address low byte)
RX (address high byte)
Host (7-bit)
Unused
TX
Host (10-bit)
TX (address low byte)
TX (address high byte)
Multi-Host (7-bit)
RX
TX
Transmit Buffer
The I2C module has a dedicated transmit buffer, I2CxTXB, which is independent from the receive buffer.
The transmit buffer is loaded with an address byte (when ABD = 1), or a data byte, that is copied into the transmit
shift register and transmitted onto the bus. When the I2CxTXB register does not contain any transmit data, the
Transmit Buffer Empty Status (TXBE) bit is set (TXBE = 1), allowing user software or the DMA to load a new byte into
the buffer. When the TXBE bit is set and the I2CxCNT register is non-zero (I2CxCNT != 0), the I2C Transmit Interrupt
Flag (I2CxTXIF) bit of the PIR registers is set, and can be used as a DMA trigger. A write to I2CxTXB will clear
both the TXBE and I2CxTXIF bits. Setting the Clear Buffer (CLRBF) bit clears I2CxTXIF, the I2Cx Receive Buffer
(I2CxRXB) and I2CxTXB.
If user software attempts to load I2CxTXB while it is full, the Transmit Write Error Status (TXWE) bit is set, a NACK is
generated, and the new data is ignored. If TXWE is set, user software must clear the bit before attempting to load the
buffer again.
When module hardware attempts to transfer the contents of I2CxTXB to the transmit shift register while I2CxTXB is
empty (TXBE = 1), the Transmit Underflow Status (TXU) bit is set, I2CxTXB is loaded with 0xFF, and a NACK is
generated.
Important: A transmit underflow can only occur when clock stretching is disabled (Clock Stretching
Disable (CSD) bit = 1). Clock stretching prevents transmit underflows because the clock is stretched after
the 8th falling SCL edge, and is only released upon the write of new data into I2CxTXB.
37.3.10 Receive Buffer
The I2C module has a dedicated receive buffer, I2CxRXB, which is independent from the transmit buffer.
Data received through the shift register is transferred to I2CxRXB when the byte is complete. User software or the
DMA can access the byte by reading the I2CxRXB register. When new data is loaded into I2CxRXB, the Receive
Buffer Full Status (RXBF) bit is set, allowing user software or the DMA to read the new data. When the RXBF bit is
set, the I2C Receive Interrupt Flag (I2CxRXIF) bit of the PIR registers is set, and can be used to trigger the DMA. A
read of the I2CxRXB register will clear both RXBF and I2CxRXIF bits. Setting the CLRBF bit clears the I2CxRXIF bit,
I2CxRXB, and I2CxTXB.
If the buffer is read while empty (RXBF = 0), the Receive Read Error Status (RXRE) bit is set, and the module
generates a NACK. User software must clear RXRE to resume normal operation.
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I2C - Inter-Integrated Circuit Module
When the module attempts to transfer the contents of the receive shift register to I2CxRXB while I2CxRXB is full
(RXBF = 1), the Receive Overflow Status (RXO) bit is set, and a NACK is generated. The data currently stored in
I2CxRXB remains unchanged, but the data in the receive shift register is lost.
Important: A receive overflow can only occur when clock stretching is disabled. Clock stretching
prevents receive overflows because the receive shift register cannot receive any more data until user
software or the DMA reads I2CxRXB and the SCL line is released.
37.3.11 Clock Stretching
Clock stretching occurs when a client device holds the SCL line low to pause bus communication. A client device
may stretch the clock to allow more time to process incoming data, prepare a response for the host device, or to
prevent receive overflow or transmit underflow conditions. Clock stretching is enabled by clearing the Clock Stretch
Disable (CSD) bit, and is only available in Client and Multi-Host modes.
When
clock stretching is
enabled
(CSD
= 0),
the Client Clock Stretching (CSTR) bit can be used to determine if the
Filename:
Receive
Buffer
Clock
Stretching.vsdx
clockTitle:
is currently being stretched. While the client is actively stretching the clock, CSTR is set by hardware (CSTR
Edit:
5/8/2019
= 1).Last
Once
the client has
completed its current transaction and clock stretching is no longer required, either module
First Used:
hardware
or user software must clear CSTR to release the clock and resume communication.
Notes:
37.3.11.1 Clock Stretching for Buffer Operations
When enabled (CSD = 0), clock stretching is forced during buffer read/write operations. This allows the client device
time to either load I2CxTXB with transmit data, or read data from I2CxRXB to clear the buffer.
In Client Receive mode, clock stretching prevents receive data overflows. When the first seven bits of a new byte are
received into the receive shift register while I2CxRXB is full (RXBF = 1), client hardware automatically stretches the
clock and sets CSTR. When the client has read the data in I2CxRXB, client hardware automatically clears CSTR to
release the SCL line and continue communication (see figure below).
Figure 37-9. Receive Buffer Clock Stretching
Hardware reads
RXBF = 1
SCL
1 2 3 4 5 6 7
8
Client
releases SCL
Clock
stretched
SDA
D7 D6 D5 D4 D3 D2 D1
D0
Software reads
I2CxRXB
RXBF
CSTR
Hardware sets
CSTR = 1
Hardware
clears RXBF
Hardware
clears CSTR
In Client Transmit mode, clock stretching prevents transmit underflows. When I2CxTXB is empty (TXBE = 1) and the
I2CxCNT register is nonzero (I2CxCNT != 0), client hardware stretches the clock and sets CSTR upon the 8th falling
SCL edge. Once the client has loaded new data into I2CxTXB, client hardware automatically clears CSTR to release
the SCL line and allow further communication (see figure below).
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Preliminary Datasheet
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I2C - Inter-Integrated Circuit Module
Figure 37-10. Transmit Buffer Clock Stretching
Client
releases SCL
Hardware reads
TXBE = 1
SCL
1 2 3 4 5 6 7 8
Host releases SDA to
allow ACK
SDA
9
Clock
Stretched
D7 D6 D5 D4 D3 D2 D1 D0
Software loads
I2CxTXB
TXBE
CSTR
Hardware sets
CSTR = 1
Client copies
ACKDT onto
SDA (ACKDT = 0)
Hardware
clears TXBE
Hardware
clears CSTR
37.3.11.2 Clock Stretching for Other Client Operations
The I2C module provides three Interrupt and Hold Enable features:
• Address Interrupt and Hold Enable
• Data Write Interrupt and Hold Enable
• Acknowledge Status Time Interrupt and Hold Enable
When clock stretching is enabled (CSD = 0), the Interrupt and Hold Enable features provide an interrupt response,
and stretches the clock to allow time for address recognition, data processing, or an ACK/NACK response.
The Address Interrupt and Hold Enable feature will generate an interrupt event and stretch the SCL line when a
matching address is received. This feature is enabled by setting the Address Interrupt and Hold Enable (ADRIE) bit.
When enabled (ADRIE = 1), the CSTR bit and the Address Interrupt Flag (ADRIF) bit are set by module hardware,
and the SCL line is stretched following the 8th falling SCL edge of a received matching address. Once the client has
completed processing the address, software determines whether to send an ACK or a NACK back to the host device.
Client software must clear both the ADRIF and CSTR bits to resume communication.
Important: In 10-bit Client Addressing mode, clock stretching occurs only after the client receives a
matching low address byte, or a matching high address byte with the R/W bit = 1 (Host read) while the
Client Mode Active (SMA) bit is set (SMA = 1). Clock stretching does not occur after the client receives a
matching high address byte with the R/W bit = 0 (Host write).
The Data Write Interrupt and Hold Enable feature provides an interrupt event and stretches the SCL signal after
the client receives a data byte. This feature is enabled by setting the Data Write Interrupt and Hold Enable (WRIE)
bit. When enabled (WRIE = 1), module hardware sets both the CSTR bit and the Data Write Interrupt Flag (WRIF)
bit and stretches the SCL line after the 8th falling edge of SCL. Once the client has read the new data, software
determines whether to send an ACK or a NACK back to the host device. Client software must clear both the CSTR
and WRIF bits to resume communication.
The Acknowledge Status Time Interrupt and Hold Enable feature generates an interrupt event and stretches the SCL
line after the acknowledgement phase of a transaction. This feature is enabled by setting the Acknowledge Status
Time Interrupt and Hold Enable (ACKTIE) bit. When enabled (ACKTIE = 1), module hardware sets the CSTR bit
and the Acknowledge Status Time Interrupt Flag (ACKTIF) bit and stretches the clock after the 9th falling edge of
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I2C - Inter-Integrated Circuit Module
SCL for all address, read, or write operations. Client software must clear both the ACKTIF and CSTR bits to resume
communication.
37.3.12 Data Byte Count
The data byte count refers to the number of data bytes in a complete I2C packet. The data byte count does not
include address bytes. The I2C Byte Count (I2CxCNT) register is used to specify the length, in bytes, of the complete
transaction. The value loaded into I2CxCNT will be decremented by module hardware each time a data byte is
transmitted or received by the module.
Important: The I2CxCNT register will not decrement past a zero value.
When a byte transfer causes the I2CxCNT register to decrement to ‘0’, the Byte Count Interrupt Flag (CNTIF) bit
is set, and if the Byte Count Interrupt Enable (CNTIE) is set, the general purpose I2C Interrupt Flag (I2CxIF) bit of
the Peripheral Interrupt Registers (PIR) is also set. If the I2C Interrupt Enable (I2CxIE) bit of the Peripheral Interrupt
Enable (PIE) registers is set, module hardware will generate an interrupt event.
Important: The I2CxIF bit is read-only and can only be cleared by clearing all the interrupt flag bits of the
I2CxPIR register.
The I2CxCNT register can be read at any time, but it is recommended that a double read is performed to ensure a
valid count value.
The I2CxCNT register can be written to; however, care is required to prevent register corruption. If the I2CxCNT
register is written to during the 8th falling SCL edge of a reception, or during the 9th falling SCL edge of a
transmission, the register value may be corrupted. In Client mode, I2CxCNT can be safely written to any time the
clock is not being stretched (CSTR = 0), or after a Stop condition has been received (Stop Condition Interrupt Flag
(PCIF) = 1). In Host mode, I2CxCNT can be safely written to any time the Host Data Ready (MDR) or Bus Free
(BFRE) bits are set. If the I2C packet is longer than 65,536 bytes, the I2CxCNT register can be updated mid-message
to prevent the count from reaching zero; however, the preventative measures listed above must be followed.
When in either Client Read or Host Write mode and the I2CxCNT value is nonzero (I2CxCNT != 0), the value of the
ACKDT bit is used as the acknowledgement response. When I2CxCNT reaches zero (I2CxCNT = 0), the value of the
Acknowledge End of Count (ACKCNT) bit is used for the acknowledgement response.
In Host read or write operations, when the I2CxCNT register is clear (I2CxCNT = 0) and the Restart Enable (RSEN)
bit is clear, host hardware automatically generates a Stop condition upon the 9th falling edge of SCL. When I2CxCNT
is clear (I2CxCNT = 0) and RSEN is set (RSEN = 1), host hardware will stretch the clock while it waits for the Start
(S) bit to be set (S = 1). When the Start bit has been set, module hardware transmits a Restart condition followed by
the address of the client it wishes to communicate with.
37.3.12.1 Auto-Load I2CxCNT
The I2CxCNT register can be automatically loaded. Auto-loading of the I2CxCNT register is enabled when the
Auto-Load I2C Count Register Enable (ACNT) bit is set (ACNT = 1).
In Host Transmit mode, the first two bytes following either the 7-bit or 10-bit client address are transferred from
I2CxTXB into both I2CxCNT and the transmit shift register.
Important: When using the auto-load feature in any Transmit mode (Client, Host, Multi-Host), the first
of the two bytes following the address is the I2CxCNT register’s high byte, followed by the I2CxCNT
register’s low byte. If the order of these two bytes is switched, the value loaded into the I2CxCNT register
will not be correct.
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Preliminary Datasheet
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I2C - Inter-Integrated Circuit Module
In Host Reception mode, the first two bytes received from the client are loaded into both I2CxCNT and I2CxRXB.
The value of the Acknowledge Data (ACKDT) bit is used as the host’s acknowledgement response to prevent a false
NACK from being generated before the I2CxCNT register is updated with the new count value.
In Client Reception mode, the first two bytes received after a receiving a matching 7-bit or 10-bit address are loaded
into both I2CxCNT and I2CxRXB, and the value of the ACKDT bit is used as the client’s acknowledgement response.
In Client Transmit mode, the first two bytes loaded into I2CxTXB following the reception of a matching 7-bit or 10-bit
address are transferred into both I2CxCNT and the transmit shift register.
Important: It is not necessary to preload the I2CxCNT register when using the auto-load feature. If no
value is loaded by the 9th falling SCL edge following an address transmission or reception, the Byte Count
Interrupt Flag (CNTIF) will be set by module hardware, and must be cleared by software to prevent an
interrupt event before I2CxCNT is updated. Alternatively, I2CxCNT can be preloaded with a nonzero value
to prevent the CNTIF from being set. In this case, the preloaded value will be overwritten once the new
count value has been loaded into I2CxCNT.
37.3.13 DMA Integration
The I2C module can be used with the DMA for data transfers. The DMA can be triggered through software via the
DMA Transaction (DGO) bit, or through the use of the following hardware triggers:
•
•
•
•
I2C Transmit Interrupt Flag (I2CxTXIF)
I2C Receive Interrupt Flag (I2CxRXIF)
I2C Interrupt Flag (I2CxIF)
I2C Error Interrupt Flag (I2CxEIF)
For I2C communication, the I2CxTXIF is commonly used as the hardware trigger source for host or client
transmission, and I2CxRXIF is commonly used as the hardware trigger source for host or client reception.
37.3.13.1 7-Bit Host Transmission
When address buffers are enabled (ABD = 0), I2CxADB1 is loaded with the client address, and I2CxCNT is loaded
with a count value. At this point, I2CxTXB does not contain data, and the Transmit Buffer Empty (TXBE) bit is set
(TXBE = 1). The I2CxTXIF bit is not set since it can only be set when the Host Mode Active (MMA) and TXBE bits are
set. Once software sets the Start (S) bit, the MMA bit is set, and hardware transmits the client address. Upon the 8th
falling SCL edge, since TXBE = 1, the Host Data Request (MDR) and I2CxTXIF bits are set, and hardware stretches
the clock while the DMA loads I2CxTXB with data. Once the DMA loads I2CxTXB, the TXBE, MDR, and I2CxTXIF
bits are cleared by hardware, and the DMA waits for the next occurrence of I2CxTXIF being set.
When address buffers are disabled (ABD = 1), software must load I2CxTXB with the client address to begin
transmission. This is because I2CxTXIF can only be set when MMA = 1, and since a Start has not occurred, MMA =
0. Once the address has been transmitted, I2CxTXIF will be set, triggering the DMA to load I2CxTXB with data.
37.3.13.2 10-Bit Host Transmission
When address buffers are enabled (ABD = 0), I2CxADB1 is loaded with the client high address, I2CxADB0 is loaded
with the client low address, and I2CxCNT is loaded with a count value. Once software sets the Start (S) bit, the MMA
bit is set, and hardware transmits the 10-bit client address. Upon the 8th falling SCL edge of the transmitted address
low byte, since TXBE = 1, the MDR and I2CxTXIF bits are set, and hardware stretches the clock while the DMA loads
I2CxTXB with data. Once the DMA loads I2CxTXB, the TXBE, MDR, and I2CxTXIF bits are cleared by hardware, and
the DMA waits for the next occurrence of I2CxTXIF being set.
When address buffers are disabled (ABD = 1), software must load I2CxTXB with the client high address to begin
transmission. Once the client high address has been transmitted, I2CxTXIF will be set, triggering the DMA to load
I2CxTXB with client low address. Once the DMA loads I2CxTXB with the client low address, the TXBE, MDR, and
I2CxTXIF bits are cleared by hardware, and the DMA waits for the next occurrence of I2CxTXIF being set.
37.3.13.3 7/10-Bit Host Reception
In both 7-bit and 10-bit host receive modes, the state of the ABD bit is ignored. Once the complete 7-bit or 10-bit
address has been received by the client, the client will transmit a data byte. Once the byte has been received by the
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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I2C - Inter-Integrated Circuit Module
host, hardware sets the I2CxRXIF bit, which triggers the DMA to read I2CxRXB. Once the DMA has read I2CxRXB,
I2CxRXIF is cleared by hardware and the DMA waits for the next occurrence of I2CxRXIF being set.
37.3.13.4 7-Bit Client Transmission
In 7-bit Client Transmission mode, the state of ABD is ignored. If the client receives the matching 7-bit address
and TXBE is set, I2CxTXIF is set by hardware, triggering the DMA to load data into I2CxTXB. Once the data is
transmitted from I2CxTXB, I2CxTXIF is set by hardware, triggering the DMA to once again load I2CxTXB with data.
The DMA will continue to load data into I2CxTXB until I2CxCNT reaches a zero value. Once I2CxCNT reaches zero
and the data is transmitted from I2CxTXB, I2CxTXIF will not be set, and the DMA will stop loading data.
37.3.13.5 10-Bit Client Transmission
In 10-bit Client Transmission mode, the state of ABD is ignored. If there is no data in I2CxTXB after the client has
received the address high byte with the R/W bit set, hardware sets I2CxTXIF, triggering the DMA to load I2CxTXB.
The DMA will continue to load data into I2CxTXB until I2CxCNT reaches a zero value. Once I2CxCNT reaches zero
and the data is transmitted from I2CxTXB, I2CxTXIF will not be set, and the DMA will stop loading data.
37.3.13.6 7/10-Bit Client Reception
When address buffers are enabled (ABD = 0), client hardware loads I2CxADB0/1 with the matching address, while
all data is received by I2CxRXB. Once the client loads I2CxRXB with a received data byte, hardware sets I2CxRXIF,
which triggers the DMA to read I2CxRXB. The DMA will continue to read I2CxRXB whenever I2CxRXIF is set.
When address buffers are disabled (ABD = 1), the client loads I2CxRXB with the matching address byte(s) as they
are received. Each received address byte sets I2CxRXIF, which triggers the DMA to read I2CxRXB. The DMA will
continue to read I2CxRXB whenever I2CxRXIF is set.
37.3.14 Interrupts
The I2C module offers several interrupt features designed to assist with communication functions. The interrupt
hardware contains four high-level interrupts and several condition-specific interrupts.
37.3.14.1 High-Level Interrupts
Module hardware provides four high-level interrupts:
• Transmit
• Receive
• General Purpose
• Error
These flag bits are read-only bits, and cannot be cleared by software.
The I2C Transmit Interrupt Flag (I2CxTXIF) bit is set when the I2CxCNT register is nonzero (I2CxCNT != 0), and the
transmit buffer, I2CxTXB, is empty as indicated by the Transmit Buffer Empty Status (TXBE) bit (TXBE = 1). If the
I2C Transmit Interrupt Enable (I2CxTXIE) bit is set, an interrupt event will occur when the I2CxTXIF bit becomes set.
Writing new data to I2CxTXB, or setting the Clear Buffer (CLRBF) bit, will clear the interrupt condition. The I2CxTXIF
bit is also used by the DMA as a trigger source.
Important: I2CxTXIF can only be set when either the Client Mode Active (SMA) or Host Mode Active
(MMA) bits are set, and the I2CxCNT register is nonzero (I2CxCNT != 0). The SMA bit is only set after
an address has been successfully acknowledged by a client device, which prevents false interrupts from
being triggered on address reception. The MMA bit is set once the host completes the transmission of a
Start condition.
The I2C Receive Interrupt Flag (I2CxRXIF) bit is set when the receive shift register has loaded new data into the
receive buffer, I2CxRXB. When new data is loaded into I2CxRXB, the Receive Buffer Full Status (RXBF) bit is set
(RXBF = 1), which also sets I2CxRXIF. If the I2C Receive Interrupt Enable (I2CxRXIE) bit is set, an interrupt event
will occur when the I2CxRXIF bit becomes set. Reading data from I2CxRXB, or setting the CLRBF bit, will clear the
interrupt condition. The I2CxRXIF bit is also used by the DMA as a trigger source.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 699
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
Important: I2CxRXIF can only be set when either the Client Mode Active (SMA) or Host Mode Active
(MMA) bits are set.
The I2C Interrupt Flag (I2CxIF) is the general purpose interrupt. I2CxIF is set whenever any of the interrupt flag bits
contained in the I2C Peripheral Interrupt (I2CxPIR) Register and the associated interrupt enable bits contained in
the I2C Peripheral Interrupt Enable (I2CxPIE) Register are set. If I2CxIF becomes set while the I2C Interrupt Enable
(I2CxIE) bit is set, an interrupt event will occur. I2CxIF is cleared by module hardware when all enabled interrupt flag
bits in I2CxPIR are clear.
The I2C Error Interrupt Flag (I2CxEIF) is set whenever any of the interrupt flag bits contained in the I2C Error
(I2CxERR) Register and their associated interrupt enable bits are set. If I2CxEIF becomes set while the I2C Error
Interrupt Enable (I2CxEIE) bit is set, an interrupt event will occur. I2CxEIF is cleared by hardware when all enabled
error interrupt flag bits in the I2CxERR register are clear.
37.3.14.2 Condition-Specific Interrupts
In addition to the high-level interrupts, module hardware provides several condition-specific interrupts.
The I2C Peripheral Interrupt (I2CxPIR) Register contains the following interrupt flag bits:
•
•
•
•
•
•
•
CNTIF: Byte Count Interrupt Flag
ACKTIF: Acknowledge Status Time Interrupt Flag
WRIF: Data Write Interrupt Flag
ADRIF: Address Interrupt Flag
PCIF: Stop Condition Interrupt Flag
RSCIF: Restart Condition Interrupt Flag
SCIF: Start Condition Interrupt Flag
When any of the flag bits in I2CxPIR become set and the associated interrupt enable bits in I2CxPIE are set, the
generic I2CxIF is also set. If the generic I2CxIE bit is set, an interrupt event is generated whenever one of the
I2CxPIR flag bits becomes set. If the I2CxIE bit is clear, the I2CxPIR flag bit will still be set by hardware; however, no
interrupt event will be triggered.
CNTIF becomes set (CNTIF = 1) when the I2CxCNT register value reaches zero, indicating that all data bytes in the
I2C packet have been transmitted or received. CNTIF is set after the 9th falling SCL edge when I2CxCNT reaches
zero (I2CxCNT = 0).
ACKTIF is set (ACKTIF = 1) by the 9th falling edge of SCL for any byte when the device is addressed as a client
in any Client or Multi-Host mode. If the Acknowledge Interrupt and Hold Enable (ACKTIE) bit is set and ACKTIF
becomes set:
•
If an ACK is detected, clock stretching is also enabled (CSTR = 1).
•
If a NACK is detected, no clock stretching occurs (CSTR = 0).
WRIF is set (WRIF = 1) after the 8th falling edge of SCL when the module receives a data byte in Client or Multi-Host
modes. Once the data byte is received, WRIF is set, as is the Receive Buffer Full Status (RXBF) bit, the I2CxRXIF
bit, and if the Data Write Interrupt and Hold Enable (WRIE) bit is set, the generic I2CxIF bit is also set. WRIF is a
read/write bit and must be cleared in software, while the RXBF, I2CxRXIF, and I2CxIF bits are read-only and are
cleared by reading I2CxRXB or by setting the Clear Buffer bit (CLRBF = 1).
ADRIF is set on the 8th falling edge of SCL after the module has received a matching 7-bit address, after receiving a
matching 10-bit upper address byte, and after receiving a matching 10-bit lower address byte in Client or Multi-Host
modes. Upon receiving a matching 7-bit address or 10-bit upper address, the address is copied to I2CxADB0, the
R/W bit setting is copied to the Read Information (R) bit, the Data (D) bit is cleared, and the ADRIF bit is set. If
the Address Interrupt and Hold Enable (ADRIE) bit is set, I2CxIF is set, and the clock will be stretched while the
module determines whether to ACK or NACK the transmitter. Upon receiving the matching 10-bit lower address, the
address is copied to I2CxADB1, and the ADRIF bit is set. If ADRIE is also set, the clock is stretched while the module
determines the ACK/NACK response to return to the transmitter.
PCIF is set whenever a Stop condition is detected on the bus.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 700
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
RSCIF is set upon the detection of a Restart condition.
SCIF is set upon the detection of a Start condition.
In addition to the I2CxPIR register, the I2C Error (I2CxERR) register contains three interrupt flag bits that are used
to detect bus errors. These read/write bits are set by module hardware, but must be cleared by user software. The
I2CxERR register also includes the interrupt enable bits for these three error conditions, and when set, will cause an
interrupt event whenever the associated interrupt flag bit becomes set.
I2CxERR contains the following interrupt flag bits:
•
•
•
BTOIF: Bus Time-Out Interrupt Flag
BCLIF: Bus Collision Interrupt Flag
NACKIF: NACK Detect Interrupt Flag
BTOIF is set when a bus time-out occurs. The bus time-out period is configured using one of the time-out sources
selected by the I2C Bus Time-Out Clock Source Selection (I2CxBTOC) register.
If the module is configured in Client mode with TOREC set (TOREC = 1), and a bus time-out event occurs
(regardless of the state of the Client Mode Active (SMA) bit), the module is immediately reset, the SMA and Client
Clock Stretching (CSTR) bits are cleared, and the BTOIF bit is set. If the Bus Time-Out Interrupt Enable (BTOIE) bit
is set, the generic I2C Error Interrupt Flag (I2CxEIF) bit is set.
If the module is configured in Client mode with TOREC clear (TOREC = 0), and a bus time-out event occurs
(regardless of the state of the Client Mode Active (SMA) bit), the BTOIF bit is set, but user software must reset the
module. If the Bus Time-Out Interrupt Enable (BTOIE) bit is set, the generic I2C Error Interrupt Flag (I2CxEIF) bit is
set.
If the module is configured in Host mode with TOREC set (TOREC = 1), and the bus time-out event occurs while the
Host is active (Host Mode Active (MMA) = 1), the Host Data Ready (MDR) bit is cleared, the module will immediately
attempt to transmit a Stop condition, and sets the BTOIF bit. Stop condition generation may be delayed if a client
device is stretching the clock, but will resume once the clock is released, or if the client holding the bus also has a
time-out event occur. The MMA bit is only cleared after the Stop condition has been generated. If the Bus Time-Out
Interrupt Enable (BTOIE) bit is set, the generic I2C Error Interrupt Flag (I2CxEIF) bit is set.
If the module is configured in Host mode with TOREC clear (TOREC = 0), and the bus time-out event occurs while
the Host is active (Host Mode Active (MMA) = 1), the MDR bit is cleared and the BTOIF bit is set, but user software
must initiate the Stop condition by setting the P bit. If the Bus Time-Out Interrupt Enable (BTOIE) bit is set, the
generic I2C Error Interrupt Flag (I2CxEIF) bit is set.
BCLIF is set upon the detection of a bus collision. A bus collision occurs any time the SDA line is sampled at a logic
low while the module expects both SCL and SDA lines to be at a high logic level. When a bus collision occurs, BCLIF
is set, and if the Bus Collision Detect Interrupt Enable (BCLIE) bit is set, I2CxEIF is also set, and the module is reset.
NACKIF is set when either the host or client is active (SMA = 1 || MMA = 1) and a NACK response is detected on
the bus. A NACK response occurs during the 9th SCL pulse in which the SDA line is released to a logic high. In Host
mode, a NACK can be issued when the host has finished receiving data from a client, or when the host receives
incorrect data. In Client mode, a NACK is issued when the client does not receive a matching address, or when it
receives incorrect data. A NACK can also be automatically issued when any of the following bits become set, which
will also set NACKIF and I2CxEIF:
•
•
•
•
TXWE: Transmit Write Error Status
RXRE: Receive Read Error Status
TXU: Transmit Underflow Status
RXO: Receive Overflow Status
Important: The I2CxEIF bit is read-only, and is only cleared by hardware after all enabled I2CxERR error
flags have been cleared.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 701
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.3.15 Operation in Sleep
The I2C module can operate while in Sleep mode.
In Client mode, the module can transmit and receive data as long as the system clock source operates in Sleep. If
the generic I2C Interrupt Enable (I2CxIE) bit is set and the client receives or transmits a complete byte, I2CxIF is set
and the device wakes up from Sleep.
In Host mode, both the system clock and the selected I2CxCLK source must be able to operate in Sleep. If the
I2CxIE bit is set and the I2CxIF bit becomes set, the device wakes from Sleep.
37.4
I2C Operation
All I2C communication is performed in 9-bit segments consisting of an 8-bit address/data segment followed by a
1-bit acknowledgement segment. Address and data bytes are transmitted with the Most Significant bit (MSb) first.
Interaction between the I2C module and other devices on the bus is controlled and monitored through several I2C
Control, Status, and Interrupt registers.
To begin any I2C communication, mater hardware checks to ensure that the bus is in an Idle state as indicated by
the Bus Free Status (BFRE) bit. When BFRE = 1, both SDA and SCL lines are floating to a logic high and the bus
is considered ‘Idle’. When the host detects an Idle bus, it transmits a Start condition, followed by the address of the
client it intends to communicate with. The client address can be either 7-bit or 10-bit, depending on the application
design.
In 7-bit Addressing mode, the Least Significant bit (LSb) of the 7-bit client address is reserved for the Read/not Write
(R/W) bit, while in 10-bit Addressing mode, the LSb of the high address byte is reserved as the R/W bit. If the R/W
bit is clear (R/W = 0), the host intends to read information from the client. If R/W is set (R/W = 1), the host intends
to write information to the client. If the addressed client exists on the bus, it must respond with an Acknowledgement
(ACK) sequence.
Once a client has been successfully addressed, the host will continue to receive data from the client, write data to
the client, or a combination of both. Data is always transmitted Most Significant bit (MSb) first. When the host has
completed its transactions, it can either issue a Stop condition, signaling to the client that communication is to be
terminated, or a Restart condition, informing the bus that the current host wishes to hold the bus to communicate with
the same or other client devices.
37.4.1
I2C Client Mode Operation
The I2C module provides four Client Operation modes as selected by the I2C Mode Select (MODE) bits:
•
•
•
•
I2C Client mode with recognition of up to four 7-bit addresses
I2C Client mode with recognition of up to two masked 7-bit addresses
I2C Client mode with recognition of up to two 10-bit addresses
I2C Client mode with recognition of one masked 10-bit address
During operation, the client device waits until module hardware detects a Start condition on the bus. Once the Start
condition is detected, the client waits for the incoming address information to be received by the receive shift register.
The address is then compared to the addresses stored in the I2C Address 0/1/2/3 registers (I2CxADR0, I2CxADR1,
I2CxADR2, I2CxADR3), and if an address match is detected, client hardware transfers the matching address into
either the I2CxADB0/I2CxADB1 registers or the I2CxRXB register, depending on the state of the Address Buffer
Disable (ABD) bit. If there are no address matches, there is no response from the client.
37.4.1.1 Client Addressing Modes
The I2CxADR0, I2CxADR1, I2CxADR2, and I2CxADR3 registers contain the client’s addresses. The first byte (7-bit
mode) or first and second bytes (10-bit mode) following a Start or Restart condition are compared to the values
stored in the I2CxADR registers (see figure below). If an address match occurs, the valid address is transferred to the
I2CxADB0/I2CxADB1 registers or I2CxRXB register, depending on the Addressing mode and the state of the ABD
bit.
Table 37-2. I2C Address Registers
Mode
I2CxADR0
© 2021 Microchip Technology Inc.
I2CxADR1
I2CxADR2
Preliminary Datasheet
I2CxADR3
DS40002213D-page 702
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
7-bit
7-bit address
7-bit address
7-bit address
7-bit address
7-bit w/ masking
7-bit address
7-bit mask for I2CxADR0
7-bit address
7-bit mask for I2CxADR2
10-bit
Address low byte
Address high byte
Address low byte
Address high byte
10-bit w/ masking Address low byte
Address high byte
Address low byte mask
Address high byte mask
Filename:
Masking Example.vsdx
Title:
In 7-bit Address mode, the received address byte is compared to all four I2CxADR registers independently to
Last Edit:
1/8/2019
determine
a match. The R/W bit is ignored during address comparison. If a match occurs, the matching received
First Used:
address
Notes: is transferred from the receive shift register to either the I2CxADB0 register (when ABD = 0) or to the
I2CxRXB register (when ABD = 1), and the value of the R/W bit is loaded into the Read Information (R) bit.
In 7-bit Address with Masking mode, I2CxADR0 holds one client address and I2CxADR1 holds the mask value for
I2CxADR0, while I2CxADR2 holds a second client address and I2CxADR3 holds the mask value for I2CxADR2. A
zero bit in a mask register means that the associated bit in the address register is a ‘don’t care’, which means that the
particular address bit is not used in the address comparison between the received address in the shift register and
the address stored in either I2CxADR0 or I2CxADR2 (see figure below).
Figure 37-11. 7-Bit Address with Masking Example
7-bit address
I2CxRSR (receive shift register)
1
1
0
0
1
I2CxADR1 (Address Mask)
R/W
0
X
Bits ignored
(masked)
X X
Bits compared
I2CxADR0 (Client Address)
0
1
1
1
1
0
1
0
1
1
1
1
0
1
0
X
X
Mask bit = 0: associated
address bit is ignored
In 10-bit Address mode, I2CxADR0 and I2CxADR1, and I2CxADR2 and I2CxADR3, are combined to create two
10-bit addresses. I2CxADR0 and I2CxADR2 hold the lower eight bits of the address, while I2CxADR1 and I2CxADR3
hold the upper two bits of the address, the R/W bit, and the five-digit ‘11110’ code assigned to the five Most
Significant bits of the high address byte.
Important: The ‘11110’ code is specified by the I2C Specification, but is not supported by Microchip. It is
up to the user to ensure the correct bit values are loaded into the address high byte. If a host device has
included the five-digit code in the address it intends to transmit, the client must also include those bits in
client address.
The upper received address byte is compared to the values in I2CxADR1 and I2CxADR3, and if a match occurs, the
address is stored in either I2CxADB1 (when ABD = 0) or in I2CxRXB (when ABD = 1), and the value of the R/W bit
is transferred into the R bit. The lower received address byte is compared to the values in I2CxADR0 and I2CxADR2,
and if a match occurs, the address is stored in either I2CxADB0 (when ABD = 0) or in I2CxRXB (when ABD = 1).
In 10-bit Address with Masking mode, I2CxADR0 and I2CxADR1 are combined to form the 10-bit address, while
I2CxADR2 and I2CxADR3 are combined to form the 10-bit mask. The upper received address byte is compared to
the masked value in I2CxADR1, and if a match occurs, the address is stored in either I2CxADB1 (when ABD = 0) or
in I2CxRXB (when ABD = 1), and the value of the R/W bit is transferred into the R bit. The lower received address
byte is compared to the value in I2CxADR0, and if a match occurs, the address is stored in either I2CxADB0 (when
ABD = 0) or in I2CxRXB (when ABD = 1).
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 703
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.4.1.2 General Call Addressing Support
The I2C Specification reserves the address 0x00 as the General Call address. The General Call address is used
to address all client modules connected to the bus at the same time. When a host issues a General Call, all client
devices may respond with an ACK. The General Call Enable (GCEN) bit determines whether client hardware will
respond to a General Call address. When GCEN is set (GCEN = 1), client hardware will respond to a General Call
with an ACK, and when GCEN is clear (GCEN = 0), the General Call is ignored, and the client responds with a
NACK.
When the module receives a General Call, the ADRIF bit is set and the address is stored in I2CxADB0. If the ADRIE
bit is set, the module will generate an interrupt and stretch the clock after the 8th falling edge of SCL. This allows the
Filename:
General
Addressing.vsdx
client
to determine
the Call
acknowledgement
response to return to the host (see figure below).
Title:
Last Edit:
First Used:
Notes:
1/8/2019
Important: When using the General Call addressing feature, loading the I2CxADR0/1/2/3 registers
with the 0x00 address is not recommended. Additionally, client hardware only supports General Call
addressing in 7-bit Addressing modes.
Figure 37-12. General Call Addressing
Rev. General Ca
1/8/2019
Start (S)
SDA
SCL
General Call Address (0x00)
1
2
3
4
5
ACK
6
7
8
9
D7
D6
D5
D4
D3
D2
D1
D0
ACK
1
2
3
4
5
6
7
8
9
Cleared by software
ADRIF
General Call address
loaded into I2CxADB0
37.4.1.3 Client Operation in 7-Bit Addressing Modes
The upper seven bits of an address byte are used to determine a client’s address, while the LSb of the address byte
is reserved as the Read/not Write (R/W) bit. When R/W is set (R/W = 1), the host device intends to read data from
the client. When R/W is clear (R/W = 0), the host device intends to write data to the client. When an address match
occurs, the R/W bit is copied to the Read Information (R) bit, and the 7-bit address is copied to I2CxADB0.
37.4.1.3.1 Client Transmission (7-Bit Addressing Mode)
The following section describes the sequence of events that occur when the module is transmitting data in 7-bit
Addressing mode:
1.
2.
3.
The host device issues a Start condition. Once the Start condition has been detected, client hardware sets
the Start Condition Interrupt Flag (SCIF) bit. If the Start Condition Interrupt Enable (SCIE) bit is also set, the
generic I2CxIF is also set.
Host hardware transmits the 7-bit client address with the R/W bit set, indicating that it intends to read data
from the client.
The received address is compared to the values in the I2CxADR registers. If the client is configured
in 7-bit Addressing mode (no masking), the received address is independently compared to each of the
I2CxADR0/1/2/3 registers. In 7-bit Addressing with Masking mode, the received address is compared to the
masked value of I2CxADR0 and I2CxADR2.
If an address match occurs:
– The Client Mode Active (SMA) bit is set by module hardware.
– The R/W bit value is copied to the Read Information (R) bit by module hardware.
– The Data (D) bit is cleared by hardware, indicating the last received byte was an address.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 704
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
– The Address Interrupt Flag (ADRIF) bit is set. If the Address Interrupt and Hold Enable (ADRIE) bit
is set, and the Clock Stretching Disable (CSD) bit is clear, hardware sets the Client Clock Stretching
(CSTR) bit and the generic I2CxIF bit. This allows time for the client to read either I2CxADB0 or I2CxRXB
and selectively ACK/NACK based on the received address. When the client has finished processing the
address, software must clear CSTR to resume operation.
– The matching received address is loaded into either the I2CxADB0 register or into the I2CxRXB register
as determined by the Address Buffer Disable (ABD) bit. When ABD is clear (ABD = 0), the matching
address is copied to I2CxADB0. When ABD is set (ABD = 1), the matching address is copied to
I2CxRXB, which also sets the Receive Buffer Full Status (RXBF) bit and the I2C Receive Interrupt Flag
(I2CxRXIF) bit. I2CxRXIF is a read-only bit, and must be cleared by either reading I2CxRXB or by setting
the Clear Buffer (CLRBF) bit (CLRBF = 1).
4.
5.
6.
7.
8.
9.
If no address match occurs, the module remains Idle.
If the Transmit Buffer Empty Status (TXBE) bit is set (TXBE = 1), I2CxCNT has a nonzero value (I2CxCNT !=
0), and the I2C Transmit Interrupt Flag (I2CxTXIF) is set (I2CxTXIF = 1), client hardware sets CSTR, stretches
the clock (when CSD = 0), and waits for software to load I2CxTXB with data. I2CxTXB must be loaded to clear
I2CxTXIF. Once data is loaded into I2CxTXB, hardware automatically clears CSTR to resume communication.
The host device transmits the 9th clock pulse, and client hardware transfers the value of the ACKDT bit onto
the SDA line. If there are pending errors, such as a receive overflow (RXO = 1), client hardware automatically
generates a NACK condition. NACKIF is set, and the module goes Idle.
Upon the 9th falling SCL edge, the data byte in I2CxTXB is transferred to the transmit shift register, and
I2CxCNT is decremented by one. Additionally, the Acknowledge Status Time Interrupt Flag (ACKTIF) bit is set.
If the Acknowledge Status Time Interrupt and Hold Enable (ACKTIE) bit is also set, the generic I2CxIF is set,
and if client hardware generated an ACK, the CSTR bit is also set and the clock is stretched (when CSD = 0).
If a NACK was generated, the CSTR bit remains unchanged. Once complete, software must clear CSTR and
ACKTIF to release the clock and continue operation.
If the client generated an ACK and I2CxCNT is nonzero, host hardware transmits eight clock pulses, and client
hardware begins to shift the data byte out of the shift register starting with the Most Significant bit (MSb).
After the 8th falling edge of SCL, client hardware checks the status of TXBE and I2CxCNT. If TXBE is set and
I2CxCNT has a nonzero count value, hardware sets CSTR and the clock is stretched (when CSD = 0) until
software loads I2CxTXB with new data. Once I2CxTXB has been loaded, hardware clears TXBE, I2CxTXIF,
and CSTR to resume communication.
Once the host hardware clocks in all eight data bits, it transmits the 9th clock pulse along with the ACK/
NACK response back to the client. Client hardware copies the ACK/NACK value to the Acknowledge Status
(ACKSTAT) bit and sets ACKTIF. If ACKTIE is also set, client hardware sets the generic I2CxIF bit and CSTR,
and stretches the clock (when CSD = 0). Software must clear CSTR to resume operation.
10. After the 9th falling edge of SCL, data currently loaded in I2CxTXB is transferred to the transmit shift register,
setting both TXBE and I2CxTXIF. I2CxCNT is decremented by one. If I2CxCNT is zero (I2CxCNT = 0), CNTIF
is set.
11. If I2CxCNT is nonzero and the host issued an ACK on the last byte (ACKSTAT = 0), the host transmits eight
clock pulses, and client hardware begins to shift data out of the shift register.
12. Repeat steps 8 – 11 until the host has received all the requested data (I2CxCNT = 0). Once all data has been
received, the host issues a NACK, followed by either a Stop or Restart condition. Once the NACK has been
received by the client, hardware sets NACKIF and clears SMA. If the NACK Detect Interrupt Enable (NACKIE)
bit is also set, the generic I2C Error Interrupt Flag (I2CxEIF) is set. If the host issued a Stop condition, client
hardware sets the Stop Condition Interrupt Flag (PCIF). If the host issued a Restart condition, client hardware
sets the Restart Condition Interrupt Flag (RSCIF). If the associated interrupt enable bits are also set, the
generic I2CxIF is also set.
Important: I2CxEIF is read-only, and is cleared by hardware when all enable interrupt flag bits in
I2CxERR are cleared.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 705
© 2021 Microchip Technology Inc.
Figure 37-13. 7-Bit Client Mode Transmission (No Clock Stretching)
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Figure 37-14. 7-Bit Client Mode Transmission (ADRIE = 1)
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DS40002213D-page 707
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PIC18F27/47/57Q84
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I2C - Inter-Integrated Circuit Module
Preliminary Datasheet
$'5,)
© 2021 Microchip Technology Inc.
Figure 37-15. 7-Bit Client Mode Transmission (ACKTIE = 1)
rotatethispage90
Start
SDA
R/W
A7 A6 A5 A4 A3 A2 A1 0
7-bit address
SCL
Matching received
address loaded
into I2CxADB0
Hardware sets
ACKT
ACKTIF
Hardware sets
ACKTIF
D7 D6 D5 D4 D3 D2 D1 D0
NACK
1 2 3 4 5 6 7 8 9
Software reads
I2CxRXB, clearing
I2CxRXIF
Software clears
CSTR
Hardware clears
ACKT
Software clears
ACKTIF
I2CxCNT
0x02
0x01
0x00
DS40002213D-page 708
PIC18F27/47/57Q84
Hardware sets
CNTIF
I2C - Inter-Integrated Circuit Module
Preliminary Datasheet
ACKT
1 2 3 4 5 6 7 8 9
I2CxRXIF set,
data byte
transferred to
I2CxRXB
RXBF
Hardware sets
CSTR
D7 D6 D5 D4 D3 D2 D1 D0
Stop
ACKCNT value
copied to SDA
ACK
1 2 3 4 5 6 7 8 9
CSTR
ACKDT value
copied to SDA
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.4.1.3.2 Client Reception (7-Bit Addressing Mode)
The following section describes the sequence of events that occur when the module is receiving data in 7-bit
Addressing mode:
1.
2.
3.
The host issues a Start condition. Once the Start is detected, client hardware sets the Start Condition Interrupt
Flag (SCIF) bit. If the Start Condition Interrupt Enable (SCIE) bit is also set, the generic I2CxIF bit is also set.
The host transmits the 7-bit client address with the R/W bit clear, indicating that it intends to write data to the
client.
The received address is compared to the values in the I2CxADR registers. If the client is configured
in 7-bit Addressing mode (no masking), the received address is independently compared to each of the
I2CxADR0/1/2/3 registers. In 7-bit Addressing with Masking mode, the received address is compared to the
masked value of I2CxADR0 and I2CxADR2.
If an address match occurs:
– The Client Mode Active (SMA) bit is set by module hardware.
– The R/W bit value is copied to the Read Information (R) bit by module hardware.
– The Data (D) bit is cleared (D = 0) by hardware, indicating the last received byte was an address.
– The Address Interrupt Flag (ADRIF) bit is set (ADRIF = 1). If the Address Interrupt and Hold Enable
(ADRIE) bit is set (ADRIE = 1), and the Clock Stretching Disable (CSD) bit is clear (CSD = 0), hardware
sets the Client Clock Stretching (CSTR) bit and the generic I2CxIF bit. This allows time for the client to
read either I2CxADB0 or I2CxRXB and selectively ACK/NACK based on the received address. When the
client has finished processing the address, software must clear CSTR to resume operation.
– The matching received address is loaded into either the I2CxADB0 register or into the I2CxRXB register
as determined by the Address Buffer Disable (ABD) bit. When ABD is clear (ABD = 0), the matching
address is copied to I2CxADB0. When ABD is set (ABD = 1), the matching address is copied to
I2CxRXB, which also sets the Receive Buffer Full Status (RXBF) bit and the I2C Receive Interrupt Flag
(I2CxRXIF) bit. I2CxRXIF is a read-only bit, and must be cleared by either reading I2CxRXB or by setting
the Clear Buffer (CLRBF) bit (CLRBF = 1).
4.
5.
6.
7.
8.
If no address match occurs, the module remains Idle.
The host device transmits the 9th clock pulse, and client hardware transfers the value of the ACKDT bit onto
the SDA line. If there are pending errors, such as a receive overflow (RXO = 1), client hardware automatically
generates a NACK condition. NACKIF is set, and the module goes Idle.
Upon the 9th falling SCL edge, the Acknowledge Status Time Interrupt Flag (ACKTIF) bit is set. If the
Acknowledge Interrupt and Hold Enable (ACKTIE) bit is also set, the generic I2CxIF is set, and if client
hardware generated an ACK, the CSTR bit is also set and the clock is stretched (when CSD = 0). If a NACK
was generated, the CSTR bit remains unchanged. Once complete, software must clear CSTR and ACKTIF to
release the clock and continue operation.
If client hardware generated a NACK, host hardware generates a Stop condition, the Stop Condition Interrupt
Flag (PCIF) bit is set when client hardware detects the Stop condition, and the client goes Idle. If an ACK was
generated, host hardware transmits the first seven bits of the 8-bit data byte.
If data remains in I2CxRXB (RXBF = 1 and I2CxRXIF = 1) when the first seven bits of the new byte are
received by the shift register, CSTR is set, and if CSD is clear, the clock is stretched after the 7th falling edge
of SCL. This allows time for the client to read I2CxRXB, which clears RXBF and I2CxRXIF, and prevents a
receive buffer overflow. Once RXBF and I2CxRXIF are cleared, hardware releases SCL.
Host hardware transmits the 8th bit of the current data byte into the client receive shift register. Client
hardware then transfers the complete byte into I2CxRXB on the 8th falling edge of SCL, and sets the following
bits:
– I2CxRXIF
– I2CxIF
– Data Write Interrupt Flag (WRIF)
– Data (D)
– RXBF
I2CxCNT is decremented by one. If the Data Write Interrupt and Hold Enable (WRIE) is set (WRIE = 1),
hardware sets CSTR (when CSD = 0) and stretches the clock, allowing time for client software to read
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 709
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
9.
I2CxRXB and determine the state of the ACKDT bit that is transmitted back to the host. Once the client
determines the Acknowledgement response, software clears CSTR to allow further communication.
Host hardware transmits the 9th clock pulse. If there are pending errors, such as receive buffer overflow, client
hardware automatically generates a NACK condition, sets NACKIF, and the module goes Idle. If I2CxCNT is
nonzero (I2CxCNT != 0), client hardware transmits the value of ACKDT as the acknowledgement response to
the host. It is up to software to configure ACKDT appropriately. In most cases, the ACKDT bit must be clear
(ACKDT = 0) so that the host receives an ACK response (logic low level on SDA during the 9th clock pulse).
If I2CxCNT is zero (I2CxCNT = 0), client hardware transmits the value of the Acknowledge End of Count
(ACKCNT) bit as the Acknowledgement response, rather than the value of ACKDT. It is up to software to
configure ACKCNT appropriately. In most cases, ACKCNT must be set (ACKCNT = 1), which represents
a NACK condition. When host hardware detects a NACK on the bus, it will generate a Stop condition. If
ACKCNT is clear (ACKCNT = 0), an ACK will be issued, and host hardware will not issue a Stop condition.
10. Upon the 9th falling edge of SCL, the ACKTIF bit is set. If ACKTIE is also set, the generic I2CxIF is set,
and if CSD is clear, client hardware sets CSTR and stretches the clock. This allows time for software to read
I2CxRXB. Once complete, software must clear both CSTR and ACKTIF to release the clock and continue
communication.
11. Repeat steps 6 -10 until the host has transmitted all the data (I2CxCNT = 0), or until the host issues a Stop or
Restart condition.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 710
© 2021 Microchip Technology Inc.
Figure 37-16. 7-Bit Client Mode Reception (No Clock Stretching)
rotatethispage90
Start
SDA
R/W
A7 A6 A5 A4 A3 A2 A1 0
7-bit address
SCL
Stop
Hardware sets
PCIF
D7 D6 D5 D4 D3 D2 D1 D0
NACK
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
I2CxRXIF set,
data byte
transferred to
I2CxRXB
RXBF
Hardware sets
NACKIF
Software reads
I2CxRXB, clearing
I2CxRXIF
Hardware clears
SMA
Hardware copies
R/W value to R bit
D
0x02
Hardware sets D
bit, last byte was
data
0x01
Hardware sets
CNTIF
0x00
DS40002213D-page 711
PIC18F27/47/57Q84
Hardware clears D
bit, last byte was
address
I2C - Inter-Integrated Circuit Module
Preliminary Datasheet
Hardware sets
SMA
R
I2CxCNT
D7 D6 D5 D4 D3 D2 D1 D0
ACKCNT value
copied to SDA
ACK
Matching received
address loaded
into I2CxADB0
SMA
ACKDT value
copied to SDA
Notes:
© 2021 Microchip Technology Inc.
Figure 37-17. 7-Bit Client Mode Reception (ADRIE = 1)
Start
SDA
Rev. I2C Client
1/9/2019
rotatethispage90
R/W
A7 A6 A5 A4 A3 A2 A1 0
7-bit address
SCL
ACKDT value
copied to SDA
D7 D6 D5 D4 D3 D2 D1 D0
ACKCNT value
copied to SDA
D7 D6 D5 D4 D3 D2 D1 D0
ACK
1 2 3 4 5 6 7 8
Stop
NACK
9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
Matching received
address loaded into
I2CxADB0
ADRIF
Software clears
ADRIF and CSTR
CSTR
I2CxRXIF set,
data byte
transferred to
I2CxRXB
RXBF
DS40002213D-page 712
CNTIF
0x02
0x01
Hardware sets
CNTIF
0x00
PIC18F27/47/57Q84
I2CxCNT
Software reads
I2CxRXB, clearing
I2CxRXIF
I2C - Inter-Integrated Circuit Module
Preliminary Datasheet
Hardware sets
ADRIF and CSTR
© 2021 Microchip Technology Inc.
Figure 37-18. 7-Bit Client Mode Reception (ACKTIE = 1)
Start
SDA
R/W
A7 A6 A5 A4 A3 A2 A1 0
7-bit address
SCL
Matching received
address loaded
into I2CxADB0
Hardware sets
ACKT
ACKTIF
Hardware sets
ACKTIF
1 2 3 4 5 6 7 8 9
Stop
ACKCNT value
copied to SDA
D7 D6 D5 D4 D3 D2 D1 D0
NACK
1 2 3 4 5 6 7 8 9
Software reads
I2CxRXB, clearing
I2CxRXIF
Software clears
CSTR
Hardware clears
ACKT
Software clears
ACKTIF
I2CxCNT
0x02
0x01
0x00
DS40002213D-page 713
PIC18F27/47/57Q84
Hardware sets
CNTIF
I2C - Inter-Integrated Circuit Module
Preliminary Datasheet
ACKT
D7 D6 D5 D4 D3 D2 D1 D0
I2CxRXIF set,
data byte
transferred to
I2CxRXB
RXBF
Hardware sets
CSTR
ACKDT value
copied to SDA
ACK
1 2 3 4 5 6 7 8 9
CSTR
rotatethispage90
© 2021 Microchip Technology Inc.
Figure 37-19. 7-Bit Client Mode Reception (WRIE = 1)
rotatethispage90
Start
SDA
R/W
A7 A6 A5 A4 A3 A2 A1 0
7-bit address
SCL
ACKDT value
copied to SDA
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
NACK
ACK
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8
Stop
ACKCNT value
copied to SDA
9 1 2 3 4 5 6 7 8
9
Matching received
address loaded
into I2CxADB0
WRIF
Software clears
CSTR and WRIF
CSTR
I2CxRXIF set,
data byte
transferred to
I2CxRXB
RXBF
DS40002213D-page 714
CNTIF
0x02
0x01
0x00
Hardware sets
CNTIF
PIC18F27/47/57Q84
I2CxCNT
Software reads
I2CxRXB, clearing
I2CxRXIF
I2C - Inter-Integrated Circuit Module
Preliminary Datasheet
Hardware sets
CSTR and WRIF
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.4.1.4 Client Operation in 10-Bit Addressing Modes
andthe
Lower
Address
Bytes.vsdx
InFilename:
10-bit AddressingUpper
modes,
first10-bit
two bytes
following
a Start condition form the 10-bit address (see figure below).
Title:
The
first byte (address high byte) holds the upper two address bits, the R/W bit, and a five digit code (11110) as
Last Edit:
12/6/2018
defined
by the I2C Specification.
The second byte (address low byte) holds the lower eight address bits. In all 10-bit
First Used:
Addressing
modes,
the R/W value contained in the first byte must always be zero (R/W = 0). If the host intends to
Notes:
read data from the client, it must issue a Restart condition, followed by the address high byte with R/W set (R/W = 1).
The first byte is compared to the values in the I2CxADR1 and I2CxADR3 registers in 10-bit Addressing mode, or to
the masked value of I2CxADR1 in 10-bit Addressing with Masking mode. The second byte is compared to the values
in the I2CxADR0 and I2CxADR2 registers in 10-bit Addressing mode, or to the masked value of I2CxADR0 in 10-bit
Addressing with Masking mode. If an address high byte match occurs, the high address byte is copied to I2CxADB1
and the R/W bit value is copied to the Read Information (R) bit, and if an address low byte match occurs, the low
address byte is copied to I2CxADB0.
Figure 37-20. Upper and Lower 10-Bit Address Bytes
Address High Byte
1
1
1
1
5-digit
address
code
0
Address Low Byte
A9 A8 R/W
Upper two
address bits
A7 A6 A5 A4 A3 A2 A1 A0
Lower eight
address bits
37.4.1.4.1 Client Transmission (10-Bit Addressing Mode)
The following section describes the sequence of events that occur when the module is transmitting data in 10-bit
Addressing mode:
1.
2.
3.
The host device issues a Start condition. Once the Start condition has been detected, client hardware sets
the Start Condition Interrupt Flag (SCIF) bit. If the Start Condition Interrupt Enable (SCIE) bit is also set, the
generic I2CxIF is also set.
Host hardware transmits the 10-bit high address byte with the R/W bit clear (R/W = 0).
Client hardware compares the received address to the values in the I2CxADR registers. If the client is
configured in 10-bit Addressing mode (no masking), the received high address byte is compared to the values
in I2CxADR1 and I2CxADR3. In 10-bit Addressing with Masking mode, the received high address byte is
compared to the masked value of I2CxADR1.
If an address match occurs:
– The R/W value is copied to the Read Information (R) bit by module hardware.
– The Data (D) bit is cleared by hardware.
– The Address Interrupt Flag (ADRIF) bit is set (ADRIF = 1).
– The matching address is loaded into either the I2CxADB1 register or into the I2CxRXB register as
determined by the Address Buffer Disable (ABD) bit. When ABD is clear (ABD = 0), the matching address
is copied to I2CxADB1. When ABD is set (ABD = 1), the matching address is copied to I2CxRXB, which
also sets the Receive Buffer Full Status (RXBF) bit and the I2C Receive Interrupt Flag (I2CxRXIF) bit.
Important: Regardless of whether the Address Interrupt and Hold Enable (ADRIE) bit is set, clock
stretching does not occur when the R/W bit is clear in 10-bit Addressing modes.
If no address match occurs, the module remains Idle.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 715
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
4.
5.
The host device transmits the 9th clock pulse, and client hardware transfers the value of the ACKDT bit
onto the SDA line. If there are pending errors, such as a receive buffer overflow (RXO = 1), client hardware
generates a NACK and the module goes Idle.
The host device transmits the low address byte. If the client is configured in 10-bit Addressing mode
(no masking), the received low address byte is compared to the values in I2CxADR0 and I2CxADR2. In
10-bit Addressing with Masking mode, the received low address byte is compared to the masked value of
I2CxADR0.
If a match occurs:
– The Client Mode Active (SMA) bit is set by module hardware.
– ADRIF is set. If ADRIE is set, and the Clock Stretching Disable (CSD) bit is clear, hardware sets the
Client Clock Stretching (CSTR) bit and the generic I2CxIF bit. This allows time for the client to read either
I2CxADB0 or I2CxRXB and selectively ACK/NACK based on the received address. When the client has
finished processing the address, software must clear CSTR to resume operation.
– The matching received address is loaded into either the I2CxADB0 register or into the I2CxRXB register
as determined by the ABD bit. When ABD is clear (ABD = 0), the matching address is copied to
I2CxADB0. When ABD is set (ABD = 1), the matching address is copied to I2CxRXB, which also sets
RXBF and I2CxRXIF. I2CxRXIF is a read-only bit, and must be cleared by either reading I2CxRXB or by
setting the Clear Buffer (CLRBF) bit (CLRBF = 1).
6.
7.
8.
9.
If no match occurs, the module goes Idle.
The host device transmits the 9th clock pulse, and client hardware transfers the value of the ACKDT bit
onto the SDA line. If there are pending errors, such as a receive buffer overflow (RXO = 1), client hardware
generates a NACK and the module goes Idle.
After the 9th falling edge of SCL, the Acknowledge Status Time Interrupt Flag (ACKTIF) bit is set. If the
Acknowledge Time Interrupt and Hold Enable (ACKTIE) bit is also set, the generic I2CxIF is set, and if client
hardware generated an ACK, the CSTR bit is also set and the clock is stretched (when CSD = 0). If a NACK
was generated, the CSTR bit remains unchanged. Once completed, software must clear CSTR and ACKTIF to
release the clock and resume operation.
Host hardware issues a Restart condition (cannot be a Start condition), and once the client detects the
Restart, hardware sets the Restart Condition Interrupt Flag (RSCIF). If the Restart Condition Interrupt Enable
(RSCIE) bit is also set, the generic I2CxIF is also set.
Host hardware transmits the client’s high address byte with R/W set.
If the received high address byte matches:
–
–
–
–
The R/W bit value is copied to the R bit.
The SMA bit is set.
The D bit is cleared, indicating the last byte as an address.
ADRIF is set. If ADRIE is set, and the CSD bit is clear, hardware sets CSTR and the generic I2CxIF bit.
This allows time for the client to read either I2CxADB1 or I2CxRXB and selectively ACK/NACK based on
the received address. When the client has finished processing the address, software must clear CSTR to
resume operation.
– The matching received address is loaded into either the I2CxADB1 register or into the I2CxRXB register
as determined by the ABD bit. When ABD is clear (ABD = 0), the matching address is copied to
I2CxADB1. When ABD is set (ABD = 1), the matching address is copied to I2CxRXB, which also sets
RXBF and I2CxRXIF. I2CxRXIF is a read-only bit, and must be cleared by either reading I2CxRXB or by
setting CLRBF (CLRBF = 1).
If the address does not match, the module goes Idle.
10. If the Transmit Buffer Empty Status (TXBE) bit is set (TXBE = 1), I2CxCNT has a nonzero value (I2CxCNT !=
0), and the I2C Transmit Interrupt Flag (I2CxTXIF) is set (I2CxTXIF = 1), client hardware sets CSTR, stretches
the clock (when CSD = 0), and waits for software to load I2CxTXB with data. I2CxTXB must be loaded to clear
I2CxTXIF. Once data is loaded into I2CxTXB, hardware automatically clears CSTR to resume communication.
11. The host device transmits the 9th clock pulse, and client hardware transfers the value of the ACKDT bit onto
the SDA line. If there are pending errors, such as a receive overflow (RXO = 1), client hardware automatically
generates a NACK condition. NACKIF is set, and the module goes Idle.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 716
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
12. Upon the 9th falling SCL edge, the data byte in I2CxTXB is transferred to the transmit shift register, and
I2CxCNT is decremented by one. Additionally, the ACKTIF bit is set. If the ACKTIE bit is also set, the generic
I2CxIF is set, and if client hardware generated an ACK, the CSTR bit is also set and the clock is stretched
(when CSD = 0). If a NACK was generated, the CSTR bit remains unchanged. Once complete, software must
clear CSTR and ACKTIF to release the clock and continue operation.
13. If the client generated an ACK and I2CxCNT is nonzero, host hardware transmits eight clock pulses, and client
hardware begins to shift the data byte out of the shift register starting with the Most Significant bit (MSb).
14. After the 8th falling edge of SCL, client hardware checks the status of TXBE and I2CxCNT. If TXBE is set and
I2CxCNT has a nonzero count value, hardware sets CSTR and the clock is stretched (when CSD = 0) until
software loads I2CxTXB with new data. Once I2CxTXB has been loaded, hardware clears CSTR to resume
communication.
15. Once the host hardware clocks in all eight data bits, it transmits the 9th clock pulse along with the ACK/
NACK response back to the client. Client hardware copies the ACK/NACK value to the Acknowledge Status
(ACKSTAT) bit and sets ACKTIF. If ACKTIE is also set, client hardware sets the generic I2CxIF bit and CSTR,
and stretches the clock (when CSD = 0). Software must clear CSTR to resume operation.
16. After the 9th falling edge of SCL, data currently loaded in I2CxTXB is transferred to the transmit shift register,
setting both TXBE and I2CxTXIF. I2CxCNT is decremented by one. If I2CxCNT is zero (I2CxCNT = 0), CNTIF
is set.
17. If I2CxCNT is nonzero and the host issued an ACK on the last byte (ACKSTAT = 0), the host transmits eight
clock pulses, and client hardware begins to shift data out of the shift register.
18. Repeat Steps 13-17 until the host has received all the requested data (I2CxCNT = 0). Once all data is
received, host hardware transmits a NACK condition, followed by either a Stop or Restart condition. Once the
NACK has been received by the client, hardware sets NACKIF and clears SMA. If the NACK Detect Interrupt
Enable (NACKIE) bit is also set, the generic I2C Error Interrupt Flag (I2CxEIF) is set. If the host issued a Stop
condition, client hardware sets the Stop Condition Interrupt Flag (PCIF). If the host issued a Restart condition,
client hardware sets the Restart Condition Interrupt Flag (RSCIF) bit. If the associated interrupt enable bits are
also set, the generic I2CxIF is also set.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 717
© 2021 Microchip Technology Inc.
Figure 37-21. 10-Bit Client Mode Transmission
rotatethispage90
R/W
SDA
1 1 1 1 0 A9 A8 0
High address
SCL
ACK (from client)
A7 A6 A5 A4 A3 A2 A1 A0
Low address
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
Hardware sets
SMA
SMA
Hardware copies R/W
value to R bit
D
Hardware clears D
bit for address bytes
1 1 1 1 0 A9 A8 1
High address
Stop
D7 D6 D5 D4 D3 D2 D1 D0
ACK (from client)
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
Hardware clears
SMA
Hardware sets
NACKIF,
CNTIF
Hardware copies
R/W value to R bit
Hardware sets D
bit, last byte was
data
I2CxCNT
0x01
DS40002213D-page 718
Before Start, software
loads data into I2CxTXB
Data byte transferred to shift register,
I2CxTXIF NOT set
PIC18F27/47/57Q84
Host's NACK
copied to
ACKSTAT
ACKSTAT
TXBE
0x00
I2C - Inter-Integrated Circuit Module
Preliminary Datasheet
R
NACK
(from
host )
R/W
Restart
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.4.1.4.2 Client Reception (10-Bit Addressing Mode)
The following section describes the sequence of events that occur when the module is receiving data in 7-bit
Addressing mode:
1.
2.
3.
The host issues a Start condition. Once the Start is detected, client hardware sets the Start Condition Interrupt
Flag (SCIF) bit. If the Start Condition Interrupt Enable (SCIE) bit is also set, the generic I2CxIF bit is also set.
Host hardware transmits the address high byte with the R/W bit clear (R/W = 0).
The received high address byte is compared to the values in the I2CxADR registers. If the client is configured
in 10-bit Addressing mode (no masking), the received high address byte is compared to the values in the
I2CxADR1 and I2CxADR3 registers. If the client is configured in 10-bit Addressing with Masking mode, the
received high address byte is compared to the masked value in the I2CxADR1 register.
If a high address match occurs:
– The R/W bit value is copied to the Read Information (R) bit by module hardware.
– The Data (D) bit is cleared (D = 0) by hardware, indicating the last received byte was an address.
– The Address Interrupt Flag (ADRIF) bit is set (ADRIF = 1). It is important to note that regardless of
whether the Address Interrupt and Hold Enable (ADRIE) bit is set, clock stretching does not occur when
the R/W bit is clear in 10-bit Addressing modes.
– The matching address is loaded into either the I2CxADB1 register or into the I2CxRXB register as
determined by the Address Buffer Disable (ABD) bit. When ABD is clear (ABD = 0), the matching address
is copied to I2CxADB1. When ABD is set (ABD = 1), the matching address is copied to I2CxRXB, which
also sets the Receive Buffer Full Status (RXBF) bit and the I2C Receive Interrupt Flag (I2CxRXIF) bit.
4.
5.
If no address match occurs, the module remains Idle.
The host device transmits the 9th clock pulse, and client hardware transfers the value of the ACKDT bit
onto the SDA line. If there are pending errors, such as a receive buffer overflow (RXO = 1), client hardware
generates a NACK and the module goes Idle.
The host device transmits the low address byte. If the client is configured in 10-bit Addressing mode
(no masking), the received low address byte is compared to the values in I2CxADR0 and I2CxADR2. In
10-bit Addressing with Masking mode, the received low address byte is compared to the masked value of
I2CxADR0.
If a match occurs:
– The Client Mode Active (SMA) bit is set by module hardware.
– ADRIF is set. If ADRIE is set, and the Clock Stretching Disable (CSD) bit is clear, hardware sets the
Client Clock Stretching (CSTR) bit and the generic I2CxIF bit. This allows time for the client to read either
I2CxADB0 or I2CxRXB and selectively ACK/NACK based on the received address. When the client has
finished processing the address, software must clear CSTR to resume operation.
– The matching received address is loaded into either the I2CxADB0 register or into the I2CxRXB register
as determined by the ABD bit. When ABD is clear (ABD = 0), the matching address is copied to
I2CxADB0. When ABD is set (ABD = 1), the matching address is copied to I2CxRXB, which also sets
the RXBF and the I2CxRXIF bits. I2CxRXIF is a read-only bit, and must be cleared by either reading
I2CxRXB or by setting the Clear Buffer (CLRBF) bit (CLRBF = 1).
6.
7.
8.
9.
If no match occurs, the module goes Idle.
The host device transmits the 9th clock pulse, and client hardware transfers the value of the ACKDT bit
onto the SDA line. If there are pending errors, such as a receive buffer overflow (RXO = 1), client hardware
generates a NACK and the module goes Idle.
After the 9th falling edge of SCL, the Acknowledge Status Time Interrupt Flag (ACKTIF) bit is set. If the
Acknowledge Time Interrupt and Hold Enable (ACKTIE) bit is also set, the generic I2CxIF is set, and if client
hardware generated an ACK, the CSTR bit is also set and the clock is stretched (when CSD = 0). If a NACK
was generated, the CSTR bit remains unchanged. Once completed, software must clear CSTR and ACKTIF to
release the clock and resume operation.
If client hardware generated a NACK, host hardware generates a Stop condition, the Stop Condition Interrupt
Flag (PCIF) is set when client hardware detects the Stop condition, and the client goes Idle. If an ACK was
generated, host hardware transmits the first seven bits of the 8-bit data byte.
If data remains in I2CxRXB (RXBF = 1 and I2CxRXIF = 1) when the first seven bits of the new byte are
received by the shift register, CSTR is set, and if CSD is clear, the clock is stretched after the 7th falling edge
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 719
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
of SCL. This allows time for the client to read I2CxRXB, which clears RXBF and I2CxRXIF, and prevents
a receive buffer overflow. Once I2CxRXB has been read, RXBF and I2CxRXIF are cleared, and hardware
releases SCL.
10. Host hardware transmits the 8th bit of the current data byte into the client receive shift register. Client
hardware then transfers the complete byte into I2CxRXB on the 8th falling edge of SCL, and sets the following
bits:
– I2CxRXIF
– I2CxIF
– Data Write Interrupt Flag (WRIF)
– Data (D)
– RXBF
I2CxCNT is decremented by one. If the Data Write Interrupt and Hold Enable (WRIE) bit is set (WRIE =
1), hardware sets CSTR (when CSD = 0) and stretches the clock, allowing time for client software to read
I2CxRXB and determine the state of the ACKDT bit that is transmitted back to the host. Once the client
determines the Acknowledgement response, software clears CSTR to allow further communication.
11. Upon the 9th falling edge of SCL, the ACKTIF bit is set. If ACKTIE is also set, the generic I2CxIF is set,
and if CSD is clear, client hardware sets CSTR and stretches the clock. This allows time for software to read
I2CxRXB. Once complete, software must clear both CSTR and ACKTIF to release the clock and continue
communication.
12. Repeat Steps 8 – 11 until the host has transmitted all the data (I2CxCNT = 0), or until the host issues a Stop or
Restart condition.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 720
© 2021 Microchip Technology Inc.
Figure 37-22. 10-Bit Client Mode Reception
rotatethispage90
Start
SDA
R/W
1 1 1 1 0 A9 A8 0
ACKDT value
copied to SDA
A7 A6 A5 A4 A3 A2 A1 A0
High address
SCL
RXBF
R
D
Hardware sets
PCIF
D7 D6 D5 D4 D3 D2 D1 D0
ACK
NACK
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
Matching received
High address loaded
into I2CxADB1
Matching received
Low address loaded
into I2CxADB0
Hardware sets
NACKIF
I2CxRXIF set,
data byte
transferred to
I2CxRXB
Hardware sets
SMA
Hardware clears
SMA
Hardware copies
R/W value to R bit
Hardware clears D
bit, last byte was
address
0x01
Hardware sets D
bit, last byte was
data
Hardware sets
CNTIF
0x00
DS40002213D-page 721
PIC18F27/47/57Q84
I2CxCNT
Stop
I2C - Inter-Integrated Circuit Module
Preliminary Datasheet
SMA
ACKCNT value
copied to SDA
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.4.2
I2C Host Mode Operation
The I2C module provides two Host Operation modes as selected by the I2C Mode Select (MODE) bits:
•
•
I2C Host mode with 7-bit addressing
I2C Host mode with 10-bit addressing
To begin any I2C communication, host hardware checks to ensure that the bus is in an Idle state, which means both
the SCL and SDA lines are floating in a high logic state as indicated by the Bus Free Status (BFRE) bit.
Once Host hardware has determined that the bus is free (BFRE = 1), it examines the state of the Address Buffer
Disable (ABD) bit. The ABD bit determines whether the I2CxADB registers are used.
When ABD is clear (ABD = 0), address buffers I2CxADB0 and I2CxADB1 are active. In 7-bit Addressing mode,
software loads I2CxADB1 with the 7-bit client address and R/W bit setting, and also loads I2CxTXB with the first byte
of data . In 10-bit Addressing mode, software loads I2CxADB1 with the address high byte and I2CxADB0 with the
address low byte, and also loads I2CxTXB with the first data byte. Software must issue a Start condition to initiate
communication with the client.
When ABD is set (ABD = 1), the address buffers are inactive. In this case, communication begins as soon as
software loads the client address into I2CxTXB. Writes to the Start (S) bit are ignored.
In 7-bit Addressing mode, the Least Significant bit (LSb) of the 7-bit address byte acts as the Read/not Write (R/W)
information bit, while in 10-bit Addressing mode, the LSb of the address high byte is reserved as the R/W bit. When
R/W is set, the host intends to read data from the client (see figure below). When R/W is clear, the host intends to
write data to the client (see figure below). The host may also wish to read or write data to a specific location, such as
writing to a specific EEPROM location. In this case, the host issues a Start condition, followed by the client’s address
with the R/W bit clear. Once the client acknowledges the address, the first data byte following the 7-bit or 10-bit
address is used as the client’s specific register location. If the host intends to read data from the specific location, it
must issue a Restart condition, followed by the client address with the R/W bit set (see figure below). If the addressed
client device exists on the bus, it must respond with an Acknowledge (ACK) sequence.
Once a client has acknowledged its address, the host begins to receive data from the client or transmits data to the
client. Data is always transmitted Most Significant bit (MSb) first. When the host wishes to halt further communication,
it transmits either a Stop condition, signaling to the client that communication is to be terminated, or a Restart
condition, informing the bus that the current host wishes to hold the bus to communicate with the same or other client
devices.
Figure 37-23. 7-Bit Host Read Diagram
S
T
S A6 A5 A4 A3 A2 A1 A0 1 A D7 D6 D5 D4 D3 D2 D1 D0 N O
P
Data
7-bit address
R/W
© 2021 Microchip Technology Inc.
ACK
(from client)
Preliminary Datasheet
NACK
(from host)
DS40002213D-page 722
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
Figure 37-24. 7-Bit Host Read Diagram (from a specific memory/register location)
S A6 A5 A4 A3 A2 A1 A0 0 A RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 A
R
A6 A5 A4 A3 A2 A1 A0 1 A D7 D6 D5 D4 D3 D2 D1 D0 N
S
Register
Address
7-bit address
R/W
ACK
Data
7-bit address
NACK
R/W ACK
ACK
(from client)
(from client)
S
T
O
P
(from host )
(from client)
Restart
condition
Figure 37-25. 10-Bit Host Read Diagram
Address
high byte
S 1
1
1
1
Restart
condition
R/W
0 A9 A8 0 A A7 A6 A5 A4 A3 A2 A1 A0 A
5-digit
10-bit
address address
code
MSb s
R
1
S
Address low
byte
ACK
ACK
Address
high byte
1
1
1
0 A9 A8 1 A D7 D6 D5 D4 D3 D2 D1 D0 N
10-bit
5-digit
address address
MSb s
code
(from client)
(from client)
R/W
S
T
O
P
Data
NACK
(from host)
ACK
(from client)
Figure 37-26. 7-Bit Host Write Diagram
S A6 A5 A4 A3 A2 A1 A0 0 A D7 D6 D5 D4 D3 D2 D1 D0 N
Data
7-bit address
R/W
© 2021 Microchip Technology Inc.
S
T
O
P
ACK
(from client)
Preliminary Datasheet
NACK
(from client)
DS40002213D-page 723
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
Figure 37-27. 7-Bit Host Write Diagram (to a specific memory/register location)
S A6 A5 A4 A3 A2 A1 A0 0 A RA7RA6RA5 RA4 RA3RA2 RA1RA0 A D7 D6 D5 D4 D3 D2 D1 D0 N
Register
Address
7-bit address
R/W
S
T
O
P
Data
NACK
(from client)
ACK
ACK
(from client)
(from client)
Figure 37-28. 10-Bit Host Write Diagram
Address
high byte
S 1
1
1
1
5-digit
address
code
R/W
0 A9 A8 0 A A7 A6 A5 A4 A3 A2 A1 A0 A D7 D6 D5 D4 D3 D2 D1 D0 N
10-bit
address
MSb s
Data
Address low
byte
ACK
ACK
(from client)
S
T
O
P
(from client)
NACK
(from client)
37.4.2.1 Bus Free Time
The Bus Free Status (BFRE) bit indicates the activity status of the bus. When BFRE is set (BFRE = 1), the bus is in
an Idle state (both SDA and SCL are floating high), and any host device residing on the bus can compete for control
of the bus. When BFRE is clear (BFRE = 0), the bus is in an Active state, and any attempts by a host to control the
bus will cause a collision.
The Bus Free Time (BFRET) bits determine the length of time, in terms of I2C clock pulses, before the bus is
considered Idle. Once module hardware detects logic high levels on both SDA and SCL, it monitors the I2C clock
signal, and when the desired number of pulses have occurred, module hardware sets BFRE. The BFRET bits are
also used to ensure that the module meets the minimum Stop hold time as defined by the I2C Specification.
a
37.4.2.2 Host Clock Timing
The Serial Clock (SCL) signal is generated by module hardware via the I2C Clock Selection (I2CxCLK) Register, the
I2C Baud Rate Prescaler (I2CxBAUD) Register, and the Fast Mode Enable (FME) bit.
The figure below illustrates the SCL clock generation.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 724
Notes:
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
Figure 37-29. SCL Clock Generation
CLK[4:0]
11111
10111
10110
.
.
.
I2CxBAUD
FPRECLK =
I2CxCLK
(BAUD + 1)
FME
1
FSCL
0
00010
00001
00000
I2CxCLK contains several clock source selections. The clock source selections typically include variants of the
system clock and timer resources.
Important: When using a timer as the clock source, the timer must also be configured. Additionally,
when using the HFINTOSC as a clock source it is important to understand that the HFINTOSC frequency
selected by the OSCFRQ register is used as the clock source. The clock divider selected by the NDIV bits
is not used. For example, if OSCFRQ selects 4 MHz as the HFINTOSC clock frequency, and the NDIV
bits select a divide by four scaling factor, the I2C Clock Frequency will be 4 MHz and not 1 MHz since the
divider is ignored.
I2CxBAUD is used to determine the prescaler (clock divider) for the I2CxCLK source.
The FME bit acts as a secondary divider to the prescaled clock source.
When FME is clear (FME = 0), one SCL period (TSCL) is equal to five clock periods of the prescaled I2CxCLK source.
In other words, the prescaled I2CxCLK source is divided by five. For example, if the HFINTOSC (set to 4 MHz) clock
source is selected, I2CxBAUD is loaded with a value of ‘7’, and the FME bit is clear, the actual SCL frequency is 100
kHz (see the Equation below).
Equation 37-1. SCL Frequency (FME = 0)
Example:
• I2CxCLK: HFINTOSC (4 MHz)
•
I2CxBAUD: 7
•
FME: FME = 0
fSCL =
fI2CxCLK
BAUD + 1
FME
=
4 MHz
8
5
= 100 kHz
When FME is clear, host hardware uses the first prescaled I2CxCLK source period to drive SCL low (see figure
below). During the second period, hardware verifies that SCL is in fact low. During the third period, hardware releases
SCL, allowing it to float high. Host hardware then uses the fourth and fifth periods to sample SCL to verify that SCL
is high. If a client is holding SCL low (clock stretch) during the fourth and/or fifth period, host hardware samples each
successive prescaled I2CxCLK period until a high level is detected on SCL. Once the high level is detected, host
hardware samples SCL during the next two I2CxCLK periods to verify that SCL is high.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 725
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
Figure 37-30. SCL Timing (FME = 0)
Host
releases
SCL
Host drives
SCL low
I2C
Prescaled
Clock
1
2
Host drives
SCL low
3
4
5
1
Host releases
SCL, but client
stretches clock
2
3
TSCL
Host drives
SCL low
Client
releases SCL
4
5
1
2
TSCL
SCL
Host samples
SCL to ensure
SCL is high
Host samples SCL
to ensure SCL is
low
Host samples SCL
to ensure SCL is
low
Host samples
SCL for high
Host MUST
detect SCL
high twice
When FME is set (FME = 1), one SCL period (TSCL) is equal to four clock periods of the prescaled I2CxCLK source.
In other words, the prescaled I2CxCLK source is divided by four. Using the example from above, if the HFINTOSC
(4 MHz) clock source is selected, I2CxBAUD is loaded with a value of ‘7’and the FME bit is set, the actual SCL
frequency is 125 kHz (see the Equation below).
Equation 37-2. SCL Frequency (FME = 1)
Example:
• I2CxCLK: HFINTOSC (4 MHz)
•
I2CxBAUD: 7
•
FME: FME = 1
fSCL =
fI2CxCLK
BAUD + 1
FME
Filename:
Title:
Last Edit:
First Used:
Notes:
=
4 MHz
8
4
FME = 1.vsdx
= 125 kHz
When FME is set, host hardware uses the first prescaled I2CxCLK source period to drive SCL low (see figure below).
7/30/2019
During the second prescaled period, hardware verifies that SCL is in fact low. During the third period, hardware
releases SCL, allowing it to float high. Host hardware then uses the fourth period to sample SCL to verify that SCL is
high. If a client is holding SCL low (clock stretch) during the fourth period, host hardware samples each successive
prescaled I2CxCLK period until a high level is detected on SCL. Once the high level is detected, host hardware
samples SCL during the next period to verify that SCL is high.
Figure 37-31. SCL Timing (FME = 1)
Host
releases
SCL
Host drives
SCL low
I2C
Prescaled
Clock
1
2
3
Rev. FME = 1.v s
7/30/2019
Host drives
SCL low
4
TSCL
1
Host releases
SCL, but client
stretches clock
2
3
Client
releases SCL
4
1
TSCL
2
3
Host
drives SCL
low
4
TSCL
SCL
Host samples SCL
to ensure SCL is
low
© 2021 Microchip Technology Inc.
Host samples
SCL to
ensure SCL is
high
Host samples SCL
to ensure SCL is
low
Host samples SCL
for high
Preliminary Datasheet
Host MUST
detect SCL
high
DS40002213D-page 726
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.4.2.3 Start Condition Timing
A Start condition is initiated by either writing to the Start (S) bit (when ABD = 0), or by writing to I2CxTXB (when ABD
= 1). When the Start condition is initiated, host hardware verifies that the bus is Idle, then begins to count the number
of I2CxCLK
periods as
determined
by the Bus Free Time Status (BFRET) bits. Once the Bus Free Time period has
Filename:
Start
Condition Timing.vsdx
Title:
been reached,
hardware sets BFRE (BFRE = 1), the Start condition is asserted on the bus, which pulls the SDA
Last Edit:
1/28/2019
line low,
and
the Start Condition Interrupt Flag (SCIF) bit is set (SCIF = 1). Host hardware then waits one full SCL
First
Used:
period Notes:
(TSCL) before pulling the SCL line low, signaling the end of the Start condition. At this point, hardware loads the
transmit shift register from either I2CxADB0/I2CxADB1 (ABD = 0) or I2CxTXB (ABD = 1).
The figure below shows an example of a Start condition.
Figure 37-32. Start Condition Timing
Rev. St art Cond
1/28/2019
BFRE = 1
SCIF = 1
Start condition
asserted
Write to START (S) bit
tHD:DAT(2)
SDA
SCL
tHD:STA(1)
Change of data allowed
2
I CxCLK
(FME = 1)
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
BFRET = 00
(8 - I2C Clock Pulses)
Completion of Start
If ABD = 0: Hardware loads I2C Shift
register from I2CxADB0/1
If ABD = 1: Hardware loads I2C Shift
register with I2CxTXB
Important:
1. See device data sheet for Start condition hold time parameters.
2. SDA hold times are configured via the SDAHT bits.
37.4.2.4 Acknowledge Sequence Timing
As previously mentioned, the 9th SCL pulse for any transferred address/data byte is reserved for the Acknowledge
(ACK) sequence. During an Acknowledge sequence, the transmitting device relinquishes control of the SDA line to
the receiving device. At this time, the receiving device must decide whether to pull the SDA line low (ACK) or allow
the line to float high (NACK).
An Acknowledge sequence is enabled automatically by module hardware following an address/data byte reception.
On the 8th falling edge of SCL, the value of either the ACKDT or ACKCNT bits are copied to the SDA output,
depending on the state of I2CxCNT. When I2CxCNT holds a nonzero value (I2CxCNT != 0), the value of ACKDT is
copied to SDA (see figure below). When I2CxCNT reaches a zero count (I2CxCNT = 0), the value of ACKCNT is
copied to SDA (see figure below). In most applications, the value of ACKDT needs to be zero (ACKDT = 0), which
represents an ACK, while the value of ACKCNT needs to be one (ACKCNT = 1), which represents a NACK.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 727
Last Edit:
First Used:
Notes:
1/10/2019
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
Figure 37-33. Acknowledge (ACK) Sequence Timing
ACKDT copied to SDA
SDA
D1
D0
ACK
ACK Complete
SCL
Filename:
RXBF
Title:
Last Edit:
First Used:
Notes:
I2CxCLK
7
8
9
Software/DMA
reads I2CxRXB,
clearing I2CxRXIF
and RXBF
I2CxCNT = 1
NACK Sequence Timing.vsdx
I2CxRXIF = 1
1/10/2019
4
1
2
3
4
1
2
3
4
1
Begin ACK sequence
Figure 37-34. Not Acknowledge (NACK) Sequence Timing
ACKCNT copied to SDA
SDA
D1
SCL
7
RXBF
I2CxCLK
D0
NACK
8
NACK Complete
9
CNTIF = 1
I2CxCNT = 0
I2CxRXIF = 1
4
1
2
3
Software/DMA
reads I2CxRXB,
clearing I2CxRXIF
and RXBF
4
1
2
3
4
1
Begin NACK
sequence
37.4.2.5 Restart Condition Timing
A Restart condition is identical to a Start condition. A host device may issue a Restart instead of a Stop condition if it
intends to hold the bus after completing the current data transfer. A Restart condition occurs when the Restart Enable
(RSEN) bit is set (RSEN = 1), either I2CxCNT is zero (I2CxCNT = 0) or ACKSTAT is set (ACKSTAT = 1), and either
host hardware (ABD = 1) or user software (ABD = 0) sets the Start (S) bit.
When the Start bit is set, host hardware releases SDA (SDA floats high) for half of an SCL clock period (TSCL/2), and
then releases SCL for another half of an SCL period, then samples SDA (see figure below). If SDA is sampled low
while SCL is sampled high, a bus collision has occurred. In this case, the Bus Collision Detect Interrupt Flag (BCLIF)
is set, and if the Bus Collision Detect Interrupt Enable (BCLIE) bit is also set, the generic I2CxEIF is set, and the
module goes Idle. If SDA is sampled high while SCL is also sampled high, host hardware issues a Start condition.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 728
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
Once the Restart condition is detected on the bus, the Restart Condition Interrupt Flag (RSCIF) is set by hardware,
and if the Restart Condition Interrupt Enable (RSCIE) bit is set, the generic I2CxIF is also set.
Figure 37-35. Restart Condition Timing
Hardware
samples SDA
Write to Start (S)
bit
Completion of
Repeated Start
SDA
tSU:STA(1)
If ABD = 0: I2C Shift
register loaded from
I2CxADB0/1
If ABD = 1: I2C Shift
register loaded from
I2CxTXB
TSCL/2
SCL
TSCL/2
I2CxCLK
1
2
3
4
Host releases
SDA
1
2
3
4
Host releases
SCL
1
2
3
4
1
2
3
4
1
2
Repeated Start
condition detected
RSCIF = 1
Important:
1. See device data sheet for Restart condition setup times.
37.4.2.6 Stop Condition Timing
A Stop condition occurs when SDA transitions from an Active state to an Idle state while SCL is Idle. Host hardware
will issue a Stop condition when it has completed its current transmission and is ready to release control of the bus.
A Stop condition is also issued after an Error condition occurs, such as a bus time-out, or when a NACK condition is
detected on the bus. User software may also generate a Stop condition by setting the Stop (P) bit.
After the ACK/NACK sequence of the final byte of the transmitted/received packet, hardware pulls SCL low for half
of an SCL period (TSCL/2) (see figure below). After the half SCL period, hardware releases SCL, then samples SCL
to ensure it is in an Idle state (SCL = 1). Host hardware then waits the duration of the Stop condition setup time
(TSU:STO) and releases SDA, setting the Stop Condition Interrupt Flag (PCIF). If the Stop Condition Interrupt Enable
(PCIE) bit is also set, the generic I2CxIF is also set.
Important: At least one SCL low period must appear before a Stop condition is valid. If the SDA line
transitions low, then high again, while SCL is high, the Stop condition is ignored, and a Start condition will
be detected by the receiver.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 729
Last Edit:
First Used:
Notes:
1/28/2019
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
Figure 37-36. Stop Condition Timing
Stop detected
PCIF = 1
Stop condition
begins
D0
SDA
TSU:STO(2)
NACK
THD:STO(2)
TSCL/2(1)
SCL
8
9
NACK SEQUENCE
I2CxCLK
1
2
3
4
1
2
3
4
1
2
3
4
1
2
Important:
1. At least one SCL low period must appear before a Stop is valid.
2. See the device data sheet electrical specifications for Stop condition setup and hold times.
37.4.2.7 Host Operation in 7-Bit Addressing Modes
In Host 7-bit Addressing modes, the client’s 7-bit address and R/W bit value are loaded into either I2CxADB1 or
I2CxTXB, depending on the Address Buffer Disable (ABD) bit setting. When the host wishes to read data from the
client, software must set the R/W bit (R/W = 1). When the host wishes to write data to the client, software must clear
the R/W bit (R/W = 0).
37.4.2.7.1 Host Transmission (7-Bit Addressing Mode)
The following section describes the sequence of events that occur when the module is transmitting data in 7-bit
Addressing mode:
1.
Depending on the configuration of the Address Buffer Disable (ABD) bit, one of two methods may be used to
begin communication:
1.1.
When ABD is clear (ABD = 0), the address buffer, I2CxADB1, is enabled. In this case, the 7-bit client
address and R/W bit are loaded into I2CxADB1, with the R/W bit clear (R/W = 0). The number of data
bytes are loaded into I2CxCNT, and the first data byte is loaded into I2CxTXB. After these registers
are loaded, software must set the Start (S) bit to begin communication. Once the S bit is set, host
hardware waits for the Bus Free (BFRE) bit to be set before transmitting the Start condition to avoid
bus collisions.
1.2.
When ABD is set (ABD = 1), the address buffer is disabled. In this case, the number of data bytes are
loaded into I2CxCNT, and the client’s 7-bit address and R/W bit are loaded into I2CxTXB. A write to
I2CxTXB will cause host hardware to automatically issue a Start condition once the bus is Idle (BFRE
= 1). Software writes to the Start bit are ignored.
2.
Host hardware waits for BFRE to be set, then shifts out the Start condition. Module hardware sets the Host
Mode Active (MMA) bit and the Start Condition Interrupt Flag (SCIF). If the Start Condition Interrupt Enable
(SCIE) bit is set, the generic I2CxIF is also set.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 730
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
3.
4.
5.
6.
7.
8.
Host hardware transmits the 7-bit client address and R/W bit.
If upon the 8th falling edge of SCL, I2CxTXB is empty (Transmit Buffer Empty Status (TXBE) = 1), I2CxCNT is
nonzero (I2CxCNT != 0), and the Clock Stretching Disable (CSD) bit is clear (CSD = 0):
– The I2C Transmit Interrupt Flag (I2CxTXIF) is set. If the I2C Transmit Interrupt Enable (I2CxTXIE) bit is
also set, the generic I2CxIF is also set.
– The Host Data Request (MDR) bit is set, and the clock is stretched, allowing time for software to load
I2CxTXB with new data. Once I2CxTXB has been written, hardware releases SCL and clears MDR.
Hardware transmits the 9th clock pulse and waits for an ACK/NACK response from the client. If the host
receives an ACK, module hardware transfers the data from I2CxTXB into the transmit shift register, and
I2CxCNT is decremented by one. If the host receives a NACK, hardware will attempt to issue a Stop condition.
If the clock is currently being stretched by a client, the host must wait until the bus is free before issuing the
Stop.
Host hardware checks I2CxCNT for a zero value. If I2CxCNT is zero:
6.1.
If ABD is clear (ABD = 0), host hardware issues a Stop condition, or sets MDR if the Restart Enable
(RSEN) bit is set and waits for software to set the Start bit to issue a Restart condition. CNTIF is set.
6.2.
If ABD is set (ABD = 1), host hardware issues a Stop condition, or sets MDR if RSEN is set and waits
for software to load I2CxTXB with a new client address. CNTIF is set.
Host hardware transmits the data byte.
If upon the 8th falling edge of SCL I2CxTXB is empty (TXBE = 1), I2CxCNT is nonzero (I2CxCNT != 0), and
CSD is clear (CSD = 0):
– I2CxTXIF is set. If the I2CxTXIE bit is also set, the generic I2CxIF is also set.
– The MDR bit is set, and the clock is stretched, allowing time for software to load I2CxTXB with new data.
Once I2CxTXB has been written, hardware releases SCL and clears MDR.
If TXBE is set (TXBE = 1) and I2CxCNT is zero (I2CxCNT = 0):
9.
– I2CxTXIF is NOT set.
– CNTIF is set.
– Host hardware issues a Stop condition, setting PCIF.
Repeat Steps 5 – 8 until all data has been transmitted.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 731
Notes:
© 2021 Microchip Technology Inc.
Rev. I2C Host
1/9/2019
Figure 37-37. 7-Bit Host Mode Transmission
rotatethispage90
R/W
Start
SDA
A7 A6 A5 A4 A3 A2 A1 0
Stop
ACK (from client)
D7 D6 D5 D4 D3 D2 D1 D0
Hardware sets
PCIF
D7 D6 D5 D4 D3 D2 D1 D0
7-bit address
SCL
MMA
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
0x02
I2CxTXIF set,
data byte transferred to shift register
0x00
Data byte transferred to shift register,
I2CxTXIF NOT set
Software loads data into
I2CxTXB, clearing I2CxTXIF
DS40002213D-page 732
PIC18F27/47/57Q84
Before Start, software
loads data into I2CxTXB
0x01
I2C - Inter-Integrated Circuit Module
Preliminary Datasheet
TXBE
Hardware sets
CNTIF;
RSTEN = 0, so
host issues
Stop
Client's ACK copied
to ACKSTAT
ACKSTAT
I2CxCNT
Hardware clears
MMA
Hardware sets MMA
on detection of Start
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.4.2.7.2 Host Reception (7-Bit Addressing Mode)
The following section describes the sequence of events that occur when the module is receiving data in 7-bit
Addressing mode:
1.
Depending on the configuration of the Address Buffer Disable (ABD) bit, one of two methods may be used to
begin communication:
1.1.
When ABD is clear (ABD = 0), the address buffer, I2CxADB1, is enabled. In this case, the 7-bit client
address and R/W bit are loaded into I2CxADB1, with the R/W bit set (R/W = 1). The number of
expected received data bytes are loaded into I2CxCNT. After these registers are loaded, software
must set the Start (S) bit to begin communication. Once the S bit is set, host hardware waits for the
Bus Free (BFRE) bit to be set before transmitting the Start condition to avoid bus collisions.
1.2.
When ABD is set (ABD = 1), the address buffer is disabled. In this case, the number of expected
received data bytes are loaded into I2CxCNT, and the client’s 7-bit address and R/W bit are loaded
into I2CxTXB. A write to I2CxTXB will cause host hardware to automatically issue a Start condition
once the bus is Idle (BFRE = 1). Software writes to the Start bit are ignored.
2.
Host hardware waits for BFRE to be set, then shifts out the Start condition. Module hardware sets the Host
Mode Active (MMA) bit and the Start Condition Interrupt Flag (SCIF). If the Start Condition Interrupt Enable
(SCIE) bit is set, the generic I2CxIF is also set.
Host hardware transmits the 7-bit client address and R/W bit.
Host hardware samples SCL to determine if the client is stretching the clock, and continues to sample SCL
until the line is sampled high.
Host hardware transmits the 9th clock pulse, and receives the ACK/NACK response from the client.
If an ACK is received, host hardware receives the first seven bits of the data byte into the receive shift register.
3.
4.
5.
If a NACK is received, hardware sets the NACK Detect Interrupt Flag (NACKIF), and:
5.1.
5.2.
6.
7.
8.
ABD = 0: Host generates a Stop condition, or sets the MDR bit (if RSEN is also set) and waits for
software to set the Start bit to generate a Restart condition.
ABD = 1: Host generates a Stop condition, or sets the MDR bit (if RSEN is also set) and waits for
software to load a new address into I2CxTXB. Software writes to the Start bit are ignored.
If the NACK Detect Interrupt Enable (NACKIE) is also set, hardware sets the generic I2CxEIF bit.
If previous data remains in the I2C Receive Buffer (I2CxRXB) when the first seven bits of the new byte are
received into the receive shift register (RXBF = 1), the MDR bit is set (MDR = 1), and the clock is stretched
after the 7th falling edge of SCL. This allows the host time to read I2CxRXB, which clears the RXBF bit, and
prevents receive buffer overflows. Once RXBF is clear, hardware releases SCL.
The host clocks in the 8th bit of the data byte into the receive shift register, then transfers the full byte into
I2CxRXB. Host hardware sets the I2C Receive Interrupt Flag (I2CxRXIF) and RXBF, and if the I2C Receive
Interrupt Enable (I2CxRXIE) is set, the generic I2CxIF is also set. Finally, I2CxCNT is decremented by one.
Host hardware checks I2CxCNT for a zero value.
If I2CxCNT is nonzero (I2CxCNT != 0), hardware transmits the value of the Acknowledge Data (ACKDT) bit as
the acknowledgement response to the client. It is up to user software to properly configure ACKDT. In most
cases, ACKDT must be clear (ACKDT = 0), which indicates an ACK response.
If I2CxCNT is zero (I2CxCNT = 0), hardware transmits the value of the Acknowledge End of Count (ACKCNT)
bit as the acknowledgement response to the client. CNTIF is set, and host hardware either issues a Stop
condition or a Restart condition. It is up to user software to properly configure ACKCNT. In most cases,
ACKCNT must be set (ACKCNT = 1), which indicates a NACK response. When hardware detects a NACK on
the bus, it automatically issues a Stop condition. If a NACK is not detected, the Stop will not be generated,
which may lead to a stalled Bus condition.
9. Host hardware receives the first seven bits of the next data byte into the receive shift register.
10. Repeat Steps 6 – 9 until all expected bytes have been received.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 733
Notes:
© 2021 Microchip Technology Inc.
Rev. I2C Host
1/9/2019
Figure 37-38. 7-Bit Host Mode Reception
rotatethispage90
Start
SDA
A7 A6 A5 A4 A3 A2 A1 1
7-bit address
SCL
MMA
ACK (from
host )
R/W
D7 D6 D5 D4 D3 D2 D1 D0
Hardware sets
PCIF
D7 D6 D5 D4 D3 D2 D1 D0
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
Hardware clears
MMA
Hardware sets MMA
on detection of Start
Host's NACK copied
from ACKCNT
0x01
DS40002213D-page 734
I2CxRXIF is set
Software reads I2CxRXB,
clearing I2CxRXIF
0x00
PIC18F27/47/57Q84
0x02
I2C - Inter-Integrated Circuit Module
Preliminary Datasheet
Hardware sets
CNTIF;
RSTEN = 0, so
host issues
Stop
Host's ACK
copied from ACKDT
ACKCNT
RXBF
Stop
ACK (from client)
ACKDT
I2CxCNT
NACK (from
host )
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.4.2.8 Host Operation in 10-Bit Addressing Modes
In Host 10-bit Addressing modes, the client’s 10-bit address and R/W bit value are loaded into either the I2CxADB0
and I2CxADB1 registers (when ABD = 0), or I2CxTXB (when ABD = 1). When the host intends to read data from the
client, it must first transmit the full 10-bit address with the R/W bit clear (R/W = 0), issue a Restart condition, then
transmit the address high byte with the R/W bit set (R/W = 1). When the host intends to write data to the client, it
must transmit the full 10-bit address with the R/W bit clear (R/W = 0).
37.4.2.8.1 Host Transmission (10-Bit)
The following section describes the sequence of events that occur when the module is transmitting data in 10-bit
Addressing mode:
1.
2.
3.
4.
Depending on the configuration of the Address Buffer Disable (ABD) bit, one of two methods may be used to
begin communication:
1.1.
When ABD is clear (ABD = 0), the address buffers, I2CxADB0 and I2CxADB1, are enabled. In this
case, the address high byte is loaded into I2CxADB1 with the R/W bit clear, while the address low
byte is loaded into I2CxADB0. I2CxCNT is loaded with the total number of data bytes to transmit,
and the first data byte is loaded into I2CxTXB. After these registers are loaded, software must set the
Start bit to begin communication.
1.2.
When ABD is set (ABD = 1), the address buffers are disabled. In this case, I2CxCNT must be
loaded with the total number of bytes to transmit prior to loading I2CxTXB with the address high byte
and R/W bit. A write to I2CxTXB forces module hardware to issue a Start condition automatically;
software writes to the S bit are ignored.
Host hardware waits for BFRE to be set, then shifts out the Start condition. Module hardware sets the Host
Mode Active (MMA) bit and the Start Condition Interrupt Flag (SCIF). If the Start Condition Interrupt Enable
(SCIE) bit is also set, the generic I2CxIF is also set.
Host hardware transmits the address high byte and R/W bit from I2CxADB1.
Host hardware transmits the 9th clock pulse and shifts in the ACK/NACK response from the client.
If the host receives a NACK, it issues a Stop condition.
If the host receives and ACK and:
4.1.
ABD = 0: Hardware transmits the address low byte from I2CxADB0.
4.2.
5.
6.
7.
8.
9.
ABD = 1: Hardware sets I2CxTXIF and the Host Data Request (MDR) bit and waits for software to
load I2CxTXB with the address low byte. Software must load I2CxTXB to resume communication.
If upon the 8th falling edge of SCL I2CxTXB is empty (TXBE = 1), I2CxCNT is nonzero (I2CxCNT != 0), and
the Clock Stretching Disable (CSD) bit is clear (CSD = 0):
– I2CxTXIF is set. If the I2C Transmit Interrupt Enable (I2CxTXIE) bit is also set, the generic I2CxIF is also
set.
– MDR bit is set, and the clock is stretched, allowing time for software to load I2CxTXB with the address
low byte. Once I2CxTXB has been written, hardware releases SCL and clears MDR.
Hardware transmits the 9th clock pulse and waits for an ACK/NACK response from the client. If the host
receives an ACK, module hardware transfers the data from I2CxTXB into the transmit shift register, and
I2CxCNT is decremented by one. If the host receives a NACK, hardware will attempt to issue a Stop condition.
If the clock is currently being stretched by a client, the host must wait until the bus is free before issuing the
Stop.
Host hardware checks I2CxCNT for a zero value. If I2CxCNT is zero:
7.1.
If ABD is clear (ABD = 0), host hardware issues a Stop condition, or sets MDR if the Restart Enable
(RSEN) bit is set and waits for software to set the Start bit to issue a Restart condition. CNTIF is set.
7.2.
If ABD is set (ABD = 1), host hardware issues a Stop condition, or sets MDR if RSEN is set and waits
for software to load I2CxTXB with a new client address. CNTIF is set.
Host hardware transmits the data byte.
If upon the 8th falling edge of SCL I2CxTXB is empty (TXBE = 1), I2CxCNT is nonzero (I2CxCNT != 0), and
CSD is clear (CSD = 0):
– The I2CxTXIF bit is set. If the I2CxTXIE bit is also set, the generic I2CxIF is also set.
– The MDR bit is set, and the clock is stretched, allowing time for software to load I2CxTXB with new data.
Once I2CxTXB has been written, hardware releases SCL and clears MDR.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 735
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
If TXBE is set (TXBE = 1) and I2CxCNT is zero (I2CxCNT = 0):
– I2CxTXIF is NOT set.
– CNTIF is set.
– Host hardware issues a Stop condition, setting PCIF.
10. Repeat Steps 6 – 9 until all data has been transmitted.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 736
© 2021 Microchip Technology Inc.
Figure 37-39. 10-Bit Host Mode Transmission
rotatethispage90
Start
SDA
R/W
1 1 1 1 0 A9 A8 0
Stop
ACK (from client)
A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
Hardware sets
PCIF
High address
SCL
MMA
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
0x01
Data byte transferred to shift register,
I2CxTXIF NOT set
DS40002213D-page 737
PIC18F27/47/57Q84
Before Start, software
loads data into I2CxTXB
0x00
I2C - Inter-Integrated Circuit Module
Preliminary Datasheet
TXBE
Hardware sets
CNTIF;
RSTEN = 0, so
host issues
Stop
Client's ACK copied
to ACKSTAT
ACKSTAT
I2CxCNT
Hardware clears
MMA
Hardware sets MMA
on detection of Start
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.4.2.8.2 Host Reception (10-Bit Addressing Mode)
The following section describes the sequence of events that occur when the module is receiving data in 10-bit
Addressing mode:
1.
Depending on the configuration of the Address Buffer Disable (ABD) bit, one of two methods may be used to
begin communication:
1.1.
When ABD is clear (ABD = 0), the address buffers, I2CxADB0 and I2CxADB1, are enabled. In this
case, the address high byte and R/W bit are loaded into I2CxADB1, with R/W clear (R/W = 0). The
address low byte is loaded into I2CxADB0, and the Restart Enable (RSEN) bit is set by software.
After these registers are loaded, software must set the Start (S) bit to begin communication. Once the
S bit is set, host hardware waits for the Bus Free (BFRE) bit to be set before transmitting the Start
condition to avoid bus collisions.
1.2.
When ABD is set (ABD = 1), the address buffers are disabled. In this case, the number of expected
received bytes are loaded into I2CxCNT, the address high byte and R/W bit are loaded into I2CxTXB,
with R/W clear (R/W = 0). A write to I2CxTXB will cause host hardware to automatically issue a Start
condition once the bus is Idle (BFRE = 1). Software writes to the Start bit are ignored.
2.
Host hardware waits for BFRE to be set, then shifts out the Start condition. Module hardware sets the Host
Mode Active (MMA) bit and the Start Condition Interrupt Flag (SCIF). If the Start Condition Interrupt Enable
(SCIE) bit is set, the generic I2CxIF is also set.
Host hardware transmits the address high byte and R/W bit.
Host hardware samples SCL to determine if the client is stretching the clock, and continues to sample SCL
until the line is sampled high.
Host hardware transmits the 9th clock pulse, and receives the ACK/NACK response from the client.
If a NACK was received, the NACK Detect Interrupt Flag (NACKIF) is set and the host immediately issues a
Stop condition.
3.
4.
5.
6.
7.
If an ACK was received, module hardware transmits the address low byte.
Host hardware samples SCL to determine if the client is stretching the clock, and continues to sample SCL
until the line is sampled high.
Host hardware transmits the 9th clock pulse, and receives the ACK/NACK response from the client.
If an ACK was received, hardware sets MDR, and waits for hardware or software to set the Start bit.
If a NACK is received, hardware sets NACKIF, and:
7.1.
7.2.
8.
9.
ABD = 0: Host generates a Stop condition, or sets the MDR bit (if RSEN is also set) and waits for
software to set the Start bit to generate a Restart condition.
ABD = 1: Host generates a Stop condition, or sets the MDR bit (if RSEN is also set) and waits for
software to load a new address into I2CxTXB. Software writes to the Start bit are ignored.
If the NACK Detect Interrupt Enable (NACKIE) is also set, hardware sets the generic I2CxEIF bit.
Software loads I2CxCNT with the expected number of received bytes.
If ABD is clear (ABD = 0), software sets the Start bit. If ABD is set (ABD = 1), software writes the address high
byte with R/W bit into I2CxTXB, with R/W set (R/W = 1).
10. Host hardware transmits the Restart condition, which sets the Restart Condition Interrupt Flag (RSCIF) bit. If
the Restart Condition Interrupt Enable (RSCIE) bit is set, the generic I2CxIF is set by hardware.
11. Host hardware transmits the high address byte and R/W bit.
12. Host hardware samples SCL to determine if the client is stretching the clock, and continues to sample SCL
until the line is sampled high.
13. Host hardware transmits the 9th clock pulse, and receives the ACK/NACK response from the client.
If an ACK is received, host hardware receives the first seven bits of the data byte into the receive shift register.
If a NACK is received, and:
13.1.
13.2.
ABD = 0: Host generates a Stop condition, or sets the MDR bit (if RSEN is also set) and waits for
software to set the Start bit to generate a Restart condition.
ABD = 1: Host generates a Stop condition, or sets the MDR bit (if RSEN is also set) and waits for
software to load a new address into I2CxTXB. Software writes to the Start bit are ignored.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 738
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
14. If previous data is currently in I2CxRXB (RXBF = 1) when the first seven bits are received by the receive shift
register, hardware sets MDR, and the clock is stretched after the 7th falling edge of SCL. This allows software
to read I2CxRXB, which clears the RXBF bit, and prevents a receive buffer overflow. Once the RXBF bit is
cleared, hardware releases SCL.
15. Host hardware clocks in the 8th bit of the data byte into the receive shift register, then transfers the complete
byte into I2CxRXB, which sets the I2CxRXIF and RXBF bits. If I2CxRXIE is also set, hardware sets the
generic I2CxIF bit. I2CxCNT is decremented by one.
16. Hardware checks I2CxCNT for a zero value.
If I2CxCNT is nonzero (I2CxCNT != 0), hardware transmits the value of the Acknowledge Data (ACKDT) bit as
the acknowledgement response to the client. It is up to user software to properly configure ACKDT. In most
cases, ACKDT must be clear (ACKDT = 0), which indicates an ACK response.
If I2CxCNT is zero (I2CxCNT = 0), hardware transmits the value of the Acknowledge End of Count (ACKCNT)
bit as the acknowledgement response to the client. CNTIF is set, and host hardware either issues a Stop
condition or a Restart condition. It is up to user software to properly configure ACKCNT. In most cases,
ACKCNT must be set (ACKCNT = 1), which indicates a NACK response. When hardware detects a NACK on
the bus, it automatically issues a Stop condition. If a NACK is not detected, the Stop will not be generated,
which may lead to a stalled Bus condition.
17. Host hardware receives the first seven bits of the next data byte into the receive shift register.
18. Repeat Steps 14 – 17 until all expected bytes have been received.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 739
© 2021 Microchip Technology Inc.
Figure 37-40. 10-Bit Host Mode Reception
rotatethispage90
R/W
SDA
1 1 1 1 0 A9 A8 0
High address
ACK (from client)
A7 A6 A5 A4 A3 A2 A1 A0
Low address
NACK
(from
host )
R/W
Restart
1 1 1 1 0 A9 A8 1
High address
Stop
D7 D6 D5 D4 D3 D2 D1 D0
ACK (from client)
SCL
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
MMA
Hardware sets MMA
on detection of Start
Software clears RSTEN
before setting Start
RSTEN
Software sets RSTEN
before setting Start
0x00
0x01
0x00
Client's ACK copied
to ACKSTAT
Received data
transferred to
I2CxRXB, I2CxRXIF
is set
PIC18F27/47/57Q84
DS40002213D-page 740
RXBF
Hardware sets
RSCIF
Software loads I2CxCNT
before setting Start
I2CxCNT
ACKSTAT
Software sets Start,
clearing MDR
I2C - Inter-Integrated Circuit Module
Preliminary Datasheet
Hardware sets
MDR, wait for Start
MDR
Hardware sets
NACKIF,
CNTIF
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.4.3
I2C Multi-Host Mode Operation
In Multi-Host mode, multiple host devices reside on the same bus. A single device, or all devices, may act as both a
host and a client. Control of the bus is achieved through clock synchronization and bus arbitration.
The Bus Free (BFRE) bit is used to determine if the bus is free. When BFRE is set (BFRE = 1), the bus is in an Idle
state, allowing a host device to take control of the bus.
In Multi-Host mode, the Address Interrupt and Hold Enable (ADRIE) bit must be set (ADRIE = 1), and the Clock
Stretching Disable (CSD) bit must be clear (CSD = 0), in order for a host device to be addressed as a client.
When a matching address is received into the receive shift register, the SMA bit is set, and the Address Interrupt
Flag (ADRIF) bit is set. Since ADRIE is also set, hardware sets the Client Clock Stretching (CSTR) bit, and hardware
stretches the clock to allow time for software to respond to the host device being addressed as a client. Once the
address has been processed, software must clear CSTR to resume communication.
Important: Client hardware has priority over host hardware in Multi-Host mode. Host mode
communication can only be initiated when SMA = 0.
37.4.3.1 Multi-Host Mode Clock Synchronization
In a multi-host system, each host may begin to generate a clock signal as soon as the bus is Idle. Clock
synchronization allows all devices on the bus to use a single SCL signal.
When a high-to-low transition on SCL occurs, all active host devices begin SCL low period timing, with their clocks
held low until their low hold time expires and the high state is reached. If one host’s clock signal is still low, SCL will
be held low until that host reaches its high state. During this time, all other host devices are held in a Wait state (see
figure below).
Once all hosts have counted off their low period times, SCL is released high, and all host devices begin counting their
high periods. The first host to complete its high period pulls the SCL line low again.
This means that when the clocks are synchronized, the SCL low period is determined by the host with the longest
SCL low period, while the SCL high period is determined by the host device with the shortest SCL high period.
Important: The I2C Specification does not require the SCL signal to have a 50% duty cycle. In other
words, one host’s clock signal may have a low time that is 60% of the SCL period and a high time that is
40% of the SCL period, while another host may be 50/50. This creates a timing difference between the two
clock signals, which may result in data loss.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 741
Title:
Last Edit:
First Used:
Notes:
1/9/2019
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
Figure 37-41. Clock Synchronization During Arbitration
Wait state
Host 1
SCL
Host 2
SCL
Actual bus
SCL
Host 1 pulls
SCL low first
Host 1
releases SCL,
but Host 2
continues to
pull SCL low
Host 2
releases SCL
37.4.3.2 Multi-Host Mode Bus Arbitration
When the bus is Idle, any host device may attempt to take control of the bus. Two or more host devices may issue a
Start condition within the minimum hold time (THD:STA), which triggers a valid Start on the bus. The host devices must
then compete using bus arbitration to determine who takes control of the bus and completes their transaction.
Bus arbitration takes place bit by bit, and it may be possible for two hosts who have identical messages to complete
the entire transaction without either device losing arbitration.
During every bit period, while SCL is high each host device compares the actual signal level of SDA to the signal
level the host actually transmitted. SDA sampling is performed during the SCL high period because the SDA data
must be stable during this period; therefore, the first host to detect a low signal level on SDA while it expects a high
signal level loses arbitration. In this case, the ‘losing’ host device detects a bus collision and sets the Bus Collision
Detect Interrupt Flag (BCLIF), and if the Bus Collision Detect Interrupt Enable (BCLIE) bit is set, the generic I2CxEIF
is also set.
Arbitration can be lost in any of the following states:
•
•
•
•
•
•
Address transfer
Data transfer
Start condition
Restart condition
Acknowledge sequence
Stop condition
If a collision occurs during the data transfer phase, the transmission is halted and both SCL and SDA are released by
hardware. If a collision occurs during a Start, Restart, Acknowledge, or Stop, the operation is aborted and hardware
releases SCL and SDA. If a collision occurs during the addressing phase, the host that ‘wins’ arbitration may be
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 742
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
attempting to address the ‘losing’ host as a client. In this case, the host that lost arbitration must switch to its Client
mode and check to see if an address matches.
Filename:
Title:
Last Edit:
First Used:
Notes:
Bus Collision.vsdx
Important: The I2C Specification states that a bus collision cannot occur during a Start condition. If a
1/9/2019
collision occurs during a Start, BCLIF will be set during the addressing phase.
User software must clear BCLIF to resume operation.
Figure 37-42. Bus Collision
R
Host 2 pulls
SDA low
Host 1
releases SDA
Host 1
samples SDA
low, but
expects SDA
high
Expected SDA
(SDA = 1)
SDA
Actual SDA
(SDA = 0)
SCL
BCLIF
Change of
data allowed
© 2021 Microchip Technology Inc.
Hardware sets
BCLIF
Preliminary Datasheet
DS40002213D-page 743
Filename:
Title:
Last Edit:
First Used:
Notes:
I2C Host Mode Transmission Waveforms
.vsdx
1/9/2019
© 2021 Microchip Technology Inc.
Figure 37-43. Multi-Host Mode Transmission
rotatethispage90
Stop
Start
SCL
SDA
(Host 1 )
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
Host 1 wins arbitration, continues transmitting
1 1 0 1 0 0 0 0
D7 D6 D5 D4 D3 D2 D1 D0
R/W
SDA
(Host 2 )
1 1 1
ACK (from client)
Host 2 loses arbitration, hardware releases SDA
(Host 1)
Host 2 loses arbitration, hardware clears MMA
(Host 2 )
DS40002213D-page 744
0x02
I2CxTXIF set,
data byte transferred to
shift register
0x01
Software loads data
into I2CxTXB,
clearing I2CxTXIF
0x00
Data byte transferred to shift register,
I2CxTXIF NOT set
PIC18F27/47/57Q84
Client's ACK copied
to ACKSTAT
ACKSTAT
TXBE
Hardware clears
MMA
Host 2 loses arbitration, hardware sets BCLIF (software must clear BCLIF to
resume communication)
BCLIF
I2CxCNT
Hardware sets
CNTIF;
RSTEN = 0, so
host issues
Stop
I2C - Inter-Integrated Circuit Module
Preliminary Datasheet
MMA
MMA
Hardware sets
PCIF
D7 D6 D5 D4 D3 D2 D1 D0
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.5
Register Definitions: I2C Control
Long bit name prefixes for the I2C peripherals are shown in the following table. Refer to the “Long Bit Names”
section in the “Register and Bit Naming Conventions” chapter for more information.
Table 37-3. I2C Long Bit Name Prefixes
Peripheral
Bit Name Prefix
I2C1
I2C1
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Preliminary Datasheet
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PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.5.1
I2CxCON0
Name:
Address:
I2CxCON0
0x0294
I2C Control Register 0
Bit
7
EN
R/W
0
Access
Reset
6
RSEN
R/W
0
5
S
R/W/HS/HC
0
4
CSTR
R/C/HS/HC
0
3
MDR
R
0
2
R/W
0
1
MODE[2:0]
R/W
0
0
R/W
0
Bit 7 – EN I2C Module Enable(1,2)
Value
Description
1
The I2C module is enabled
0
The I2C module is disabled
Bit 6 – RSEN Restart Enable (used only when MODE = 1xx)
Value
Description
1
Hardware sets MDR on 9th falling SCL edge (when I2CxCNT = 0 or ACKSTAT = 1)
0
Hardware issues Stop condition on 9th falling SCL edge (when I2CxCNT = 0 or ACKSTAT = 1)
Bit 5 – S Host Start (used only when MODE = 1xx)
Value
Condition
Description
1
MMA = 0:
Set by write to I2CxTXB or S bit, hardware issues Start condition
0
MMA = 0:
Cleared by hardware after sending Start condition
1
MMA = 1 and MDR = 1: Set by write to I2CxTXB or S bit, communication resumes with a Restart
condition
0
MMA = 1 and MDR = 1: Cleared by hardware after sending Restart condition
Bit 4 – CSTR Client Clock Stretching(3)
Value
Condition
1
0
SMA = 1 and RXBF = 1(6):
SMA = 1 and TXBE = 1 and
I2CxCNT != 0:
when ADRIE = 1(4):
SMA = 1 and WRIE = 1:
SMA = 1 and ACKTIE = 1:
Description
Clock is held low (clock stretching)
Enable clocking, SCL control is released
Set by hardware on 7th falling SCL edge
User must read I2CxRXB and clear CSTR to release SCL
Set by hardware on 8th falling SCL edge
User must write to I2CxTXB and clear CSTR to release SCL
Set by hardware on 8th falling edge of matching received
address
User must clear CSTR to release SCL
Set by hardware on 8th falling SCL edge of received data byte
User must clear CSTR to release SCL
Set by hardware on 9th falling SCL edge
User must clear CSTR to release SCL
Bit 3 – MDR Host Data Request (Host pause)
Value
Condition
1
0
MMA = 1 and RXBF = 1 (pause for RX):
MMA = 1 and TXBE = 1 and I2CxCNT != 0
(pause for TX):
© 2021 Microchip Technology Inc.
Description
Host state machine pauses until data is read/written
(SCL is held low)
Host clocking of data is enabled
Set by hardware on 7th falling SCL edge
User must read I2CxRXB to release SCL
Set by hardware on the 8th falling SCL edge
User must write to I2CxTXB to release SCL
Preliminary Datasheet
DS40002213D-page 746
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
Value
Condition
RSEN = 1 and MMA = 1 and (I2CxCNT = 0
or ACKSTAT = 1) (pause for Restart):
Description
Set by hardware on 9th falling SCL edge
User must set S bit or write to I2CxTXB to release SCL
and issue a Restart condition
Bits 2:0 – MODE[2:0] I2C Mode Select
Value
Description
111
I2C Multi-Host mode (SMBus 2.0 Host)(5)
110
I2C Multi-Host mode (SMBus 2.0 Host)(5)
101
I2C Host mode, 10-bit address
100
I2C Host mode, 7-bit address
011
I2C Client mode, one 10-bit address with masking
010
I2C Client mode, two 10-bit addresses
001
I2C Client mode, two 7-bit addresses with masking
000
I2C Client mode, four 7-bit addresses
Notes:
1. SDA and SCL pins must be configured as open-drain I/Os and use either internal or external pull-up resistors.
2. SDA and SCL signals must configure both the input and output PPS registers for each signal.
3. CSTR can be set by multiple hardware sources; all sources must be addressed by user software before the
SCL line can be released.
4. SMA is set on the same SCL edge as CSTR for a matching received address.
5. In this mode, ADRIE needs to be set, allowing an interrupt to clear the BCLIF condition and the ACK of a
matching address.
6. In 10-bit Client mode (when ABD = 1), CSTR will be set when the high address has not been read from
I2CxRXB before the low address is shifted in.
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Preliminary Datasheet
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PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.5.2
I2CxCON1
Name:
Address:
I2CxCON1
0x0295
I2C Control Register 1
Bit
Access
Reset
7
ACKCNT
R/W
0
6
ACKDT
R/W
0
5
ACKSTAT
R
0
4
ACKT
R
0
3
P
R/S/HC
0
2
RXO
R/W/HS
0
1
TXU
R/W/HS
0
0
CSD
R/W
0
Bit 7 – ACKCNT Acknowledge End of Count(2)
Value
Condition
Description
1
I2CxCNT = 0
Not Acknowledge (NACK) copied to SDA output
0
I2CxCNT = 0
Acknowledge (ACK) copied to SDA output
Bit 6 – ACKDT Acknowledge Data(1,2)
Value
Condition
1
Matching received address
0
Matching received address
1
I2CxCNT != 0
0
I2CxCNT != 0
Description
Not Acknowledge (NACK) copied to SDA output
Acknowledge (ACK) copied to SDA output
Not Acknowledge (NACK) copied to SDA output
Acknowledge (ACK) copied to SDA output
Bit 5 – ACKSTAT Acknowledge Status (Transmission only)
Value
Description
1
Acknowledge was not received for the most recent transaction
0
Acknowledge was received for the most recent transaction
Bit 4 – ACKT Acknowledge Time Status
Value
Description
1
Indicates that the bus is in an Acknowledge sequence, set on the 8th falling SCL edge
0
Not in an Acknowledge sequence, cleared on the 9th rising SCL edge
Bit 3 – P Host Stop(4)
Value
Condition
1
MMA = 1
0
MMA = 1
Description
Initiate a Stop condition
Cleared by hardware after sending Stop
Bit 2 – RXO Receive Overflow Status (used only when MODE = 0xx or MODE = 11x)(3)
Value
Description
1
Set when SMA = 1 and a host receives data when RXBF = 1
0
No client receive Overflow condition
Bit 1 – TXU Transmit Underflow Status (used only when MODE = 0xx or MODE = 11x)(3)
Value
Description
1
Set when SMA = 1 and a host transmits data when TXBE = 1
0
No client transmit underflow condition
Bit 0 – CSD Clock Stretching Disable (used only when MODE = 0xx or MODE = 11x)
Value
Description
1
When SMA = 1, the CSTR bit will not be set
0
Client clock stretching proceeds normally
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 748
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
Notes:
1. Software writes to ACKDT must be followed by a minimum SDA setup time before clearing CSTR.
2. A NACK may still be generated by hardware when bus errors are present as indicated by the I2CxSTAT1 or
I2CxERR registers.
3. This bit can only be set when CSD = 1.
4.
If SCL is high (SCL = 1) when this bit is set, the current clock pulse will complete (SCL = 0) with the proper
SCL/SDA timing required for a valid Stop condition; any data in the transmit or receive shift registers will be
lost.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 749
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.5.3
I2CxCON2
Name:
Address:
I2CxCON2
0x0296
I2C Control Register 2
Bit
Access
Reset
7
ACNT
R/W
0
6
GCEN
R/W
0
5
FME
R/W
0
4
ABD
R/W
0
3
2
1
0
SDAHT[1:0]
R/W
0
BFRET[1:0]
R/W
0
R/W
0
R/W
0
Bit 7 – ACNT Auto-Load I2C Count Register Enable
Value
Description
1
The first transmitted/received byte after the address is automatically loaded into the I2CxCNT register
0
Auto-load of I2CxCNT is disabled
Bit 6 – GCEN General Call Address Enable (used when MODE = 00x or MODE = 11x)
Value
Description
1
General Call Address (0x00) causes an address match event
0
General Call Addressing is disabled
Bit 5 – FME Fast Mode Enable
Value
Description
1
SCL frequency (FSCL) = FI2CxCLK/4
0
SCL frequency (FSCL) = FI2CxCLK/5
Bit 4 – ABD Address Buffer Disable
Value
Description
1
Address buffers are disabled;
Received address is loaded into I2CxRXB, address to transmit is loaded into I2CxTXB
0
Address buffers are enabled;
Received address is loaded into I2CxADB0/I2CxADB1, address to transmit is loaded into I2CxADB0/
I2CxADB1
Bits 3:2 – SDAHT[1:0] SDA Hold Time Selection
Value
Description
11
Reserved
10
Minimum of 30 ns hold time on SDA after the falling SCL edge
01
Minimum of 100 ns hold time on SDA after the falling SCL edge
00
Minimum of 300 ns hold time on SDA after the falling SCL edge
Bits 1:0 – BFRET[1:0] Bus Free Time Selection
Value
Description
11
64 I2CxCLK pulses
10
32 I2CxCLK pulses
01
16 I2CxCLK pulses
00
8 I2CxCLK pulses
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.5.4
I2CxSTAT0
Name:
Address:
I2CxSTAT0
0x0298
I2C Status Register 0
Bit
7
BFRE
R
0
Access
Reset
6
SMA
R
0
5
MMA
R
0
4
R
R
0
3
D
R
0
2
1
0
Bit 7 – BFRE Bus Free Status(2)
Value
Description
1
Indicates an Idle bus; both SCL and SDA have been high for the time selected by the BFRET bits
0
Bus is not Idle
Bit 6 – SMA Client Mode Active Status
Value
Description
1
Client mode is active
Set after the 8th falling SCL edge of a received matching 7-bit client address
Set after the 8th falling SCL edge of a matching received 10-bit client low address
0
Set after the 8th falling SCL edge of a received matching 10-bit client high w/read address, only after a
previous received matching high and low w/write address
Client mode is not active
Cleared when any Restart/Stop condition is detected on the bus
Cleared by BTOIF and BCLIF conditions
Bit 5 – MMA Host Mode Active Status
Value
Description
1
Host mode is active
Set when Host state machine asserts a Start condition
0
Host mode is not active
Cleared when BCLIF is set
Cleared when Stop condition is issued
Cleared for BTOIF condition after the host successfully shifts out a Stop condition
Bit 4 – R Read Information(1)
Value
Description
1
Indicates that the last matching received address was a Read request
0
Indicates that the last matching received address was a Write request
Bit 3 – D Data
Value
Description
1
Indicates that the last byte received or transmitted was data
0
Indicates that the last byte received or transmitted was an address
Notes:
1. This bit holds the R/W bit information following the last received address match. Addresses transmitted by the
host do not affect the host’s R bit, and addresses appearing on the bus without a match do not affect the R bit.
2. I2CxCLK must have a valid clock source selected for this bit to function.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 751
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.5.5
I2CxSTAT1
Name:
Address:
I2CxSTAT1
0x0299
I2C Status Register 1
Bit
Access
Reset
7
TXWE
R/W/HS
0
6
5
TXBE
R
1
4
3
RXRE
R/W/HS
0
2
CLRBF
R/S
0
1
0
RXBF
R
0
Bit 7 – TXWE Transmit Write Error Status(1)
Value
Description
1
A new byte of data was written into I2CxTXB when it was full (must be cleared by software)
0
No transmit write error occurred
Bit 5 – TXBE Transmit Buffer Empty Status(2)
Value
Description
1
I2CxTXB is empty (cleared by writing to the I2CxTXB register)
0
I2CxTXB is full
Bit 3 – RXRE Receive Read Error Status(1)
Value
Description
1
A byte of data was read from I2CxRXB when it was empty (must be cleared by software)
0
No receive overflow occurred
Bit 2 – CLRBF Clear Buffer(3)
Value
Description
1
Setting this bit clears/empties the receive and transmit buffers, causing a Reset of RXBF and TXBE
Setting this bit clears the I2CxRXIF and I2CxTXIF interrupt flags
Bit 0 – RXBF Receive Buffer Full Status(2)
Value
Description
1
I2CxRXB is full (cleared by reading the I2CxRXB register)
0
I2CxRXB is empty
Notes:
1. This bit, when set, will cause a NACK to be issued.
2. Used as a trigger source for DMA operations.
3. This bit is special function; it can only be set by user software and always reads ‘0’.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 752
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.5.6
I2CxPIR
Name:
Address:
I2CxPIR
0x029A
I2C Interrupt Flag Register
Bit
Access
Reset
7
CNTIF
R/W/HS
0
6
ACKTIF
R/W/HS
0
5
4
WRIF
R/W/HS
0
3
ADRIF
R/W/HS
0
2
PCIF
R/W/HS
0
1
RSCIF
R/W/HS
0
0
SCIF
R/W/HS
0
Bit 7 – CNTIF Byte Count Interrupt Flag(1)
Value
Description
1
Set on the 9th falling SCL edge when I2CxCNT = 0
0
I2CxCNT value is not zero
Bit 6 – ACKTIF Acknowledge Status Time Interrupt Flag (used only when MODE = 0xx or MODE = 11x)(1,2)
Value
Description
1
Acknowledge sequence detected, set on the 9th falling SCL edge for any byte when addressed as a
client
0
Acknowledge sequence not detected
Bit 4 – WRIF Data Write Interrupt Flag (used only when MODE = 0xx or MODE = 11x)(1)
Value
Description
1
Data byte detected, set on the 8th falling SCL edge for a received data byte
0
Data byte not detected
Bit 3 – ADRIF Address Interrupt Flag (used only when MODE = 0xx or MODE = 11x)(1)
Value
Description
1
Address detected, set on the 8th falling SCL edge for a matching received address byte
0
Address not detected
Bit 2 – PCIF Stop Condition Interrupt Flag(1)
Value
Description
1
Stop condition detected
0
Stop condition not detected
Bit 1 – RSCIF Restart Condition Interrupt Flag(1)
Value
Description
1
Restart condition detected
0
Restart condition not detected
Bit 0 – SCIF Start Condition Interrupt Flag(1)
Value
Description
1
Start condition detected
0
Start condition not detected
Notes:
1. Enabled interrupt flags are OR’ed to produce the PIRx[I2CxIF] bit.
2. ACKTIF is not set by a matching 10-bit high address byte with the R/W bit clear. It is only set after the
matching low address byte is shifted in.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 753
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.5.7
I2CxPIE
Name:
Address:
I2CxPIE
0x029B
I2C Interrupt and Hold Enable Register
Bit
7
CNTIE
R/W
0
Access
Reset
6
ACKTIE
R/W
0
5
4
WRIE
R/W
0
3
ADRIE
R/W
0
2
PCIE
R/W
0
1
RSCIE
R/W
0
0
SCIE
R/W
0
Bit 7 – CNTIE Byte Count Interrupt Enable(1)
Value
Description
1
Enables Byte Count interrupts
0
Disables Byte Count interrupts
Bit 6 – ACKTIE Acknowledge Status Time Interrupt and Hold Enable(1,2)
Value
Description
1
Enables Acknowledge Status Time Interrupt and Hold condition
0
Disables Acknowledge Status Time Interrupt and Hold condition
Bit 4 – WRIE Data Write Interrupt and Hold Enable(1,3)
Value
Description
1
Enables Data Write Interrupt and Hold condition
0
Disables Data Write Interrupt and Hold condition
Bit 3 – ADRIE Address Interrupt and Hold Enable(1,4)
Value
Description
1
Enables Address Interrupt and Hold condition
0
Disables Address Interrupt and Hold condition
Bit 2 – PCIE Stop Condition Interrupt Enable(1)
Value
Description
1
Enables interrupt on the detection of a Stop condition
0
Disables interrupt on the detection of a Stop condition
Bit 1 – RSCIE Restart Condition Interrupt Enable(1)
Value
Description
1
Enables interrupt on the detection of a Restart condition
0
Disables interrupt on the detection of a Restart condition
Bit 0 – SCIE Stop Condition Interrupt Enable(1)
Value
Description
1
Enables interrupt on the detection of a Start condition
0
Disables interrupt on the detection of a Start condition
Notes:
1. Enabled interrupt flags are OR’ed to produce the PIRx[I2CxIF] bit.
2. When ACKTIE is set (ACKTIE = 1) and ACKTIF becomes set (ACKTIF = 1), if an ACK is generated, CSTR is
also set. If a NACK is generated, CSTR remains unchanged.
3. When WRIE is set (WRIE = 1) and WRIF becomes set (WRIF = 1), CSTR is also set.
4.
When ADRIE is set (ADRIE = 1) and ADRIF becomes set (ADRIF = 1), CSTR is also set.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 754
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.5.8
I2CxERR
Name:
Address:
I2CxERR
0x0297
I2C Error Register
Bit
Access
Reset
7
6
BTOIF
R/W/HS
0
5
BCLIF
R/W/HS
0
4
NACKIF
R/W/HS
0
3
2
BTOIE
R/W
0
1
BLCIE
R/W
0
0
NACKIE
R/W
0
Bit 6 – BTOIF Bus Time-Out Interrupt Flag(1,2)
Value
Description
1
Bus time-out event occurred
0
No bus time-out event occurred
Bit 5 – BCLIF Bus Collision Detect Interrupt Flag(1)
Value
Description
1
Bus collision detected
0
No bus collision occurred
Bit 4 – NACKIF NACK Detect Interrupt Flag(1,3,4)
Value
Description
1
NACK detected on the bus (when SMA = 1 or MMA = 1)
0
No NACK detected on the bus
Bit 2 – BTOIE Bus Time-Out Interrupt Enable
Value
Description
1
Enable bus time-out interrupts
0
Disable bus time-out interrupts
Bit 1 – BLCIE Bus Collision Detect Interrupt Enable
Value
Description
1
Enable Bus Collision interrupts
0
Disable Bus Collision interrupts
Bit 0 – NACKIE NACK Detect Interrupt Enable
Value
Description
1
Enable NACK detect interrupts
0
Disable NACK detect interrupts
Notes:
1. Enabled error interrupt flags are OR’ed to produce the PIRx[I2CxEIF] bit.
2. User software must select the bus time-out source in the I2CxBTOC register.
3. NACKIF is also set when any of the TXWE, RXRE, TXU, or RXO bits are set.
4. NACKIF is not set for the NACK response to a nonmatching client address.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 755
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.5.9
I2CxCLK
Name:
Address:
I2CxCLK
0x029E
I2C Clock Selection Register
Bit
7
6
5
Access
Reset
4
3
R/W
0
R/W
0
2
CLK[4:0]
R/W
0
1
0
R/W
0
R/W
0
Bits 4:0 – CLK[4:0] I2C Clock Selection
Table 37-4.
CLK
Selection
11000-11111
10111
10110
10101
10100
10011
10010
10001
10000
01111
01100-01110
01011
01010
01001
01000
00111
00110
00101
00100
00011
00010
00001
00000
Reserved
CLC8_out
CLC7_out
CLC6_out
CLC5_out
CLC4_out
CLC3_out
CLC2_out
CLC1_out
SMT1 overflow
Reserved
TU16B_out
TU16A_out
TMR6 post scaled output
TMR4 post scaled output
TMR2 post scaled output
TMR0 overflow
EXTOSC
Clock Reference output
MFINTOSC (500 kHz)
HFINTOSC
FOSC
FOSC/4
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Preliminary Datasheet
DS40002213D-page 756
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.5.10 I2CxBAUD
Name:
Address:
I2CxBAUD
0x029D
I2C Baud Rate Prescaler
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
BAUD[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – BAUD[7:0] Baud Rate Prescaler Selection
Value
Description
n
Prescaled I2C Clock Frequency (FPRECLK) =
I2CxCLK
BAUD + 1
Note: It is recommended to write this register only when the module is Idle (MMA = 0 or SMA = 0), or when the
module is clock stretching (CSTR = 1 or MDR = 1).
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 757
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.5.11 I2CxCNT
Name:
Address:
I2CxCNT
0x028C
I2C Byte Count Register(1,2)
Bit
15
14
13
12
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
CNT[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
CNT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – CNT[15:0] Byte Count
Condition
Description
If receiving data:
Count value decremented on 8th falling SCL edge when a new byte is loaded into I2CxRXB
If transmitting data: Count value is decremented on the 9th falling SCL edge when a new byte is moved from
I2CxTXB
Notes:
1. It is recommended to write this register only when the module is idle (MMA = 0 or SMA = 0), or when the
module is clock stretching (CSTR =1 or MDR = 1).
2.
CNTIF is set on the 9th falling SCL edge when I2CxCNT = 0.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 758
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.5.12 I2CxBTO
Name:
Address:
I2CxBTO
0x029C
I2C Bus Timeout Register(1)
Bit
7
TOREC
R/W
0
Access
Reset
6
TOBY32
R/W
0
5
4
R/W
0
R/W
0
3
2
TOTIME[5:0]
R/W
R/W
0
0
1
0
R/W
0
R/W
0
Bit 7 – TOREC Timeout Recovery Selection
Value
Description
1
A BTO event will reset the I2C module and set BTOIF.
0
A BTO event will set BTOIF, but will not reset the I2C module.
Bit 6 – TOBY32 Timeout Prescaler Extension Enable(2)
Value
Description
1
BTO time = TOTIME * TBTOCLK
0
BTO time = TOTIME * TBTOCLK * 32
Bits 5:0 – TOTIME[5:0] Timeout Time Selection
Value
Condition
Description
n
TOBY32 = 1 Timeout is TOTIME periods of the prescaled BTO clock (TOTIME = n * TBTOCLK)
n
TOBY32 = 0 Timeout is TOTIME periods of the prescaled BTO clock multiplied by 32 (TOTIME = n *
TBTOCLK * 32)
Notes:
1. It is recommended to write this register only when the module is Idle (MMA = 0 or SMA = 0), or when the
module is clock stretching (CSTR = 1 or MDR = 1).
2.
When TOBY32 is set (TOBY32 = 1) and the LFINTOSC, MFINTOSC, or SOSC is selected as the BTO clock
source, the timeout time (TOTIME) will be approximately in milliseconds.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 759
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.5.13 I2CxBTOC
Name:
Address:
I2CxBTOC
0x029F
I2C Bus Timeout Clock Source Selection
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
BTOC[3:0]
Access
Reset
R/W
0
R/W
0
Bits 3:0 – BTOC[3:0] Bus Timeout Clock Source Selection
Table 37-5.
BTOC
Selection
1111 - 1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
Reserved
SOSC
MFINTOSC (32 kHz)
LFINTOSC
TU16B_out
TU16A_out
TMR6_postscaled
TMR4_postscaled
TMR2_postscaled
Reserved
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 760
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.5.14 [I2CxADB0]
Name:
Address:
I2CxADB0
0x028E
I2C Address Buffer 0 Register(1)
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
ADB[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – ADB[7:0] I2C Address Buffer 0
Condition
Description
7-bit Client/Multi-Host modes (MODE = 00x or 11x): ADB[7:1]: Received matching 7-bit client address
ADB[0]: Received R/W value from 7-bit address
10-bit Client modes (MODE = 01x):
ADB[7:0]: Received matching lower eight bits of 10-bit client
address
7-bit Host mode (MODE = 100):
Unused in this mode
10-bit Host mode (MODE = 101):
ADB[7:0]: Eight Least Significant bits of the 10-bit client
address
Note:
1. This register is read-only except in Host 10-bit Address mode (MODE = 101).
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 761
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.5.15 I2CxADB1
Name:
Address:
I2CxADB1
0x028F
I2C Address Buffer 1 Register(1)
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
ADB[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bits 7:0 – ADB[7:0] I2C Address Buffer 1
Condition
7-bit Client modes (MODE = 00x):
10-bit Client modes (MODE = 01x):
7-bit Host mode (MODE = 100):
10-bit Host mode (MODE = 101):
7-bit Multi-Host modes (MODE = 11x):
R/W
0
Description
Unused in this mode
ADB[7:1]: Received matching 10-bit client address high byte
ADB[0]: Received R/W value from 10-bit high address byte
ADB[7:1]: 7-bit client address
ADB[0]: R/W value
ADB[7:1]: 10-bit client high address byte
ADB[0]: R/W value
ADB[7:1]: 7-bit client address
ADB[0]: R/W value
Note:
1. This register is read-only in 7-bit Client Address modes (MODE = 0xx).
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 762
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.5.16 I2CxADR0
Name:
Address:
I2CxADR0
0x0290
I2C Address 0 Register
Bit
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
ADR[7:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
Bits 7:0 – ADR[7:0] I2C Client Address 0
Condition
7-bit Client/Multi-Host modes (MODE = 00x or 11x):
10-bit Client modes (MODE = 01x):
© 2021 Microchip Technology Inc.
Description
ADR[7:1]: 7-bit client address
ADR[0]: Unused; bit state is ‘don’t care’
ADR[7:0]: Eight Least Significant bits of first 10-bit address
Preliminary Datasheet
DS40002213D-page 763
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.5.17 I2CxADR1
Name:
Address:
I2CxADR1
0x0291
I2C Address 1 Register
Bit
Access
Reset
7
6
5
R/W
1
R/W
1
R/W
1
4
ADR[6:0]
R/W
1
Bits 7:1 – ADR[6:0] I2C Client Address 1
Condition
7-bit Client/Multi-Host modes (MODE = 000 or 110):
7-bit Client/Multi-Host modes with Masking (MODE =
011 or 111):
10-bit Client mode (MODE = 010):
10-bit Client mode with Masking (MODE = 011):
3
2
1
0
R/W
1
R/W
1
R/W
1
Description
7-bit client address 1
7-bit client address mask for I2CxADR0
ADR[7:3]: Bit pattern (11110) as defined by the I2C
Specification(1)
ADR[2:1]: Two Most Significant bits of first 10-bit address
ADR[7:3]: Bit pattern (11110) as defined by the I2C
Specification(1)
ADR[2:1]: Two Most Significant bits of 10-bit address
Note:
1. The ‘11110’ bit pattern used in the 10-bit address high byte is defined by the I2C Specification. It is up to the
user to define these bits. These bit values are compared to the received address by hardware to determine a
match. The bit pattern transmitted by the host must be the same as the client address’s bit pattern used for
comparison or a match will not occur.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 764
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.5.18 I2CxADR2
Name:
Address:
I2CxADR2
0x0292
I2C Address 2 Register
Bit
7
6
5
4
3
2
1
0
R/W
1
R/W
1
R/W
1
R/W
1
ADR[7:0]
Access
Reset
R/W
1
R/W
1
R/W
1
R/W
1
Bits 7:0 – ADR[7:0] I2C Client Address 2
Condition
7-bit Client/Multi-Host modes (MODE = 000 or 110):
7-bit Client/Multi-Host modes with Masking (MODE =
001 or 111):
10-bit Client mode (MODE = 010):
10-bit Client mode with Masking (MODE = 011):
© 2021 Microchip Technology Inc.
Description
ADR[7:1]: 7-bit client address 2
ADR[0]: Unused; bit state is ‘don’t care’
ADR[7:1]: 7-bit client address
ADR[0]: Unused; bit state is ‘don’t care’
ADR[7:0]: Eight Least Significant bits of the second 10bit address
ADR[7:0]: Eight Least Significant bits of 10-bit address
mask
Preliminary Datasheet
DS40002213D-page 765
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.5.19 I2CxADR3
Name:
Address:
I2CxADR3
0x0293
I2C Address 3 Register(1)
Bit
Access
Reset
7
6
5
R/W
1
R/W
1
R/W
1
4
ADR[6:0]
R/W
1
Bits 7:1 – ADR[6:0] I2C Client Address 3
Name
7-bit Client/Multi-Host modes (MODE = 000 or 110):
7-bit Client/Multi-Host modes with Masking (MODE
= 001 or 111):
10-bit Client mode (MODE = 010):
10-bit Client mode with Masking (MODE = 011):
3
2
1
0
R/W
1
R/W
1
R/W
1
Description
7-bit client address 3
7-bit client address mask for I2CxADR2
ADR[7:3]: Bit pattern (11110) as defined by the I2C
Specification(1)
ADR[2:1]: Two Most Significant bits of second 10-bit address
ADR[7:3]: Bit pattern (11110) as defined by the I2C
Specification(1)
ADR[2:1]: Two Most Significant bits of 10-bit address mask
Note:
1. The ‘11110’ bit pattern used in the 10-bit address high byte is defined by the I2C Specification. It is up to the
user to define these bits. These bit values are compared to the received address by hardware to determine a
match. The bit pattern transmitted by the host must be the same as the client address’s bit pattern used for
comparison or a match will not occur.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 766
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.5.20 I2CxTXB
Name:
Address:
I2CxTXB
0x028B
I2C Transmit Buffer Register(1)
Bit
7
6
5
4
3
2
1
0
W
x
W
x
W
x
W
x
TXB[7:0]
Access
Reset
W
x
W
x
W
x
W
x
Bits 7:0 – TXB[7:0] I2C Transmit Buffer
Note: This register is write-only. Reading this register will return a value of 0x00.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 767
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.5.21 I2CxRXB
Name:
Address:
I2CxRXB
0x028A
I2C Receive Buffer(1)
Bit
7
6
5
4
3
2
1
0
R
x
R
x
R
x
R
x
RXB[7:0]
Access
Reset
R
x
R
x
R
x
R
x
Bits 7:0 – RXB[7:0] I2C Receive Buffer
Note: This register is read-only. Writes to this register are ignored.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 768
PIC18F27/47/57Q84
I2C - Inter-Integrated Circuit Module
37.6
Address
0x00
...
0x0289
0x028A
0x028B
Register Summary - I2C
Name
Bit Pos.
7
6
5
4
3
2
1
0
Reserved
I2C1RXB
I2C1TXB
0x028C
I2C1CNT
0x028E
0x028F
0x0290
0x0291
0x0292
0x0293
0x0294
0x0295
0x0296
0x0297
0x0298
0x0299
0x029A
0x029B
0x029C
0x029D
0x029E
0x029F
I2C1ADB0
I2C1ADB1
I2C1ADR0
I2C1ADR1
I2C1ADR2
I2C1ADR3
I2C1CON0
I2C1CON1
I2C1CON2
I2C1ERR
I2C1STAT0
I2C1STAT1
I2C1PIR
I2C1PIE
I2C1BTO
I2C1BAUD
I2C1CLK
I2C1BTOC
7:0
7:0
7:0
15:8
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
EN
ACKCNT
ACNT
BFRE
TXWE
CNTIF
CNTIE
TOREC
© 2021 Microchip Technology Inc.
RSEN
ACKDT
GCEN
BTOIF
SMA
ACKTIF
ACKTIE
TOBY32
S
ACKSTAT
FME
BCLIF
MMA
TXBE
RXB[7:0]
TXB[7:0]
CNT[7:0]
CNT[15:8]
ADB[7:0]
ADB[7:0]
ADR[7:0]
ADR[6:0]
ADR[7:0]
ADR[6:0]
CSTR
MDR
MODE[2:0]
ACKT
P
RXO
TXU
CSD
ABD
SDAHT[1:0]
BFRET[1:0]
NACKIF
BTOIE
BLCIE
NACKIE
R
D
RXRE
CLRBF
RXBF
WRIF
ADRIF
PCIF
RSCIF
SCIF
WRIE
ADRIE
PCIE
RSCIE
SCIE
TOTIME[5:0]
BAUD[7:0]
CLK[4:0]
BTOC[3:0]
Preliminary Datasheet
DS40002213D-page 769
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
38.
CAN FD - Controller Area Network, Flexible Data-Rate
This family of devices contain a Controller Area Network Flexible Data-Rate (CAN FD) module. CAN FD is a serial
interface which is useful for communicating with other peripherals or microcontroller devices. This interface, or
protocol, was designed to allow communications within noisy environments.
The CAN FD module is a communication controller, implementing the CAN FD protocol as defined in the BOSCH
specification. This module supports CAN 1.2, CAN 2.0A, CAN 2.0B Passive, CAN 2.0B Active and CAN FD versions
of the protocol. The module implementation is a full CAN FD system; however, the CAN specification is not covered
within this data sheet. Refer to the BOSCH CAN specification for further details.
CAN FD has two primary enhancements over CAN 2.0:
• The maximum data field size is increased from 8 bytes to 64 bytes.
• The data rate can optionally be switched to a faster bit rate after the arbitration field.
The CAN FD controller is capable of sending and receiving CAN 2.0 messages, and both CAN FD messages and
CAN 2.0 messages can exist on the same bus. However, this does not mean that CAN FD and CAN 2.0 controllers
need to be mixed on the same bus, as CAN 2.0 controllers will generate error frames upon receiving a CAN FD
message.
Features of the CAN FD module include:
General
•
•
•
•
Nominal (arbitration) bit rate up to 1 Mbps
Data bit rate up to 4 Mbps (dependent on oscillator selection)
CAN FD Controller modes:
– Mixed CAN 2.0B and CAN FD mode
– CAN 2.0B mode
Conforms to ISO11898-1:2015
Message FIFOs
•
•
•
3 FIFOs configurable as transmit or receive FIFOs
One Transmit Queue (TXQ)
Transmit Event FIFO (TEF) with 32-bit timestamp
Message Transmission
•
•
Message transmission prioritization:
– Based on priority bit field and/or
– Message with lowest ID gets transmitted first using the TXQ
Programmable automatic retransmission attempts: unlimited, three attempts or disabled
Message Reception
•
•
•
38.1
12 flexible filter and mask objects
Each object can be configured to filter either:
– Standard ID and first 18 data bits or
– Extended ID
32-Bit timestamp
Module Overview
The CAN FD module implements several aspects of the CAN FD protocol:
1.
The Bit Stream Processor (BSP) is an implementation of the Medium Access Control (MAC) of the CAN FD
protocol described in ISO 11898-1:2015. It serializes and deserializes the bit stream, encodes and decodes
the CAN FD frames, manages the medium access, acknowledges frames, and detects and signals errors.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 770
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
2.
3.
4.
5.
6.
7.
8.
The TX handler prioritizes the messages that are requested for transmission by the transmit FIFOs. It uses the
RAM interface to fetch the transmit data from RAM and provides it to the BSP for transmission.
The BSP provides received messages to the RX handler. The RX handler uses an acceptance filter, which
filters the messages that are to be stored in the receive FIFOs. It uses the RAM interface to store received
data into the RAM.
Each FIFO can be configured either as a transmit or receive FIFO. The FIFO control keeps track of the FIFO
head and tail and calculates the user address. In a TX FIFO, the user address points to the address in RAM
where the data for the next transmit message is stored. In an RX FIFO, the user address points to the address
in RAM where the data of the next receive message will be read. The user notifies the FIFO that a message is
written to or read from RAM by incrementing the head/tail of the FIFO.
The TXQ is a special transmit FIFO that transmits the messages, based on the ID of the messages stored in
the queue.
The TEF stores the message IDs of the transmitted messages.
A free-running Time Base Counter (TBC) is used to timestamp received messages. Messages in the TEF can
also be timestamped.
The CAN FD controller module generates interrupts when new messages are received or when messages are
transmitted successfully.
The CANRX input pin is selected with the CANRXPPS register. The CANTX output pin is selected with each pin’s
RxyPPS register.
Note: The CANRX pin defaults to pin RB3, but the CANTX has no default location and must be assigned to a pin
before CAN transmissions can occur.
In modes that enable the CANRX pin, the user must ensure that the appropriate TRIS bit for CANRX is set to
configure the pin as an input, and the associated ANSEL bit for that pin is cleared to enable the digital input buffer.
In addition, in modes that enable the CANTX pin, the appropriate TRIS bit for the associated pin must be cleared to
enable pin output.
38.1.1
Module Functionality
The CAN FD module consists of the CAN message/protocol handler and the device RAM devoted to CAN FIFOs.
The protocol handler performs the needed CAN protocol actions, transferring data in and out of the FIFOs as defined
by the firmware (see Figure 38-1).
The following sequence illustrates the necessary initialization steps before the CAN module can be used to transmit
or receive a message. Steps can be added or removed depending on the requirements of the application.
1.
2.
3.
4.
5.
6.
7.
8.
Use the CANRXPPS and appropriate RxyPPS registers to map the CANRX and CANTX functions to the
desired pins of the device.
Initialize LAT, TRIS and ANSEL bits for the selected CANRX and CANTX pins.
Ensure that the CAN module is in Configuration mode.
Set up Baud Rate registers.
Ensure FIFOs are properly configured as transmit/receive.
Set up Filter and Mask registers.
If desired, populate transmit FIFOs with data to transmit.
Set the CAN module to Normal/Normal CAN FD or any other mode required by the application logic.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 771
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
Figure 38-1. CAN FD Module Simplified Block Diagram
CX TX
TX Handler
Timestamping
TX Prioritization
Interrupt Control
CX RX
RX Handler
Error Handling Diagnostics
Filter and Masks
Device RAM
38.2
TEF
TXQ
FIFO 1
FIFO 3
Message
Object 0
Message
Object 0
Message
Object 0
Message
Object 0
Message
Object 31
Message
Object 31
Message
Object 31
Message
Object 31
Modes of Operation
The CAN FD Protocol Module has eight modes of operation:
•
•
•
•
•
•
Configuration mode
Normal CAN FD mode: Supports mixing of CAN FD and CAN 2.0 messages.
Normal CAN 2.0 mode: Will generate error frames when receiving CAN FD messages. The FDF bit is forced to
zero and only CAN 2.0 frames are sent, even if the FDF bit is set in the transmit message object.
Disable mode
Listen Only mode
Restricted Operation mode
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
•
•
Internal Loopback mode
External Loopback mode
The modes of operations can be grouped into four main groups: Configuration, Normal, Sleep and Debug (see Figure
38-2).
38.2.1
Mode Change
Figure 38-2 illustrates the possible mode transitions. New modes of operation are requested by writing to the
REQOP[2:0] (C1CON[26:24]) bits. The modes of operations do not change immediately. The modes will only change
when the bus is Idle.
The current operating mode is indicated by the OPMOD[2:0] (C1CON[23:21]) bits. The application can enable an
interrupt on an OPMODx change or poll the OPMODx bits.
38.2.1.1 Changing Between Normal Modes
Directly changing between Normal modes is not allowed. The Configuration mode must be selected before a new
Normal mode can be selected.
38.2.1.2 Changing Between Debug Modes
Directly changing between Debug modes is not allowed. The Configuration mode must be selected before a new
Debug mode can be selected.
38.2.1.3 Exiting Normal Mode
The device will transition to Configuration or Sleep mode only after the current message is transmitted.
38.2.1.4 Entering and Exiting Disable Mode
The CAN FD Protocol Module enters Disable mode after a Disable mode request. The device exits Disable mode
after a mode request.
If WAKIE is set, a dominant edge on CxRX will generate an interrupt. The CPU has to enable the CAN module by
requesting a Normal mode.
38.2.1.5 Bus Integrating Mode
The CAN FD Protocol module integrates to the bus according to the ISO11898-1:2015 specifications (eleven
consecutive recessive bits), under the following conditions:
•
•
Change from Configuration mode to one of the Normal modes or Debug modes
Change from Disable mode to one of the Normal modes
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 773
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
Figure 38-2. Modes of Operation
REQOPx = Loopback Int/Ext
and Bus Idle (Integrating)
Loopback
Modes
Configuration
Mode
Sleep Mode
Clock Off
CxTX Recessive
Listen Only
Mode
RX Only
TX Pin High
TXREQ Ignored
Normal
Modes
RX and TX
SERRLOM = 1?
c
Protocol
Exception Event
No TX
Normal Modes
Debug Modes
Normal FD
Mode
External/Internal
Loopback
Mode
Normal 2.0
Mode
Listen Only
Mode
Bus Off
Clear All TXREQx
bits (Reset TX
FIFOs/TXQ)
Restricted Operation
Mode
RX
TX: Only ACK,
TXREQx Ignored
Restricted
Operation
Mode
38.2.2
Configuration Mode
After Reset, the CAN FD Protocol Module is in Configuration mode. The error counters are cleared and all registers
contain the Reset values.
The CAN FD Protocol Module must be initialized before activation. This is only possible when the module is in
Configuration mode, OPMOD[2:0] = 100. The Configuration mode is requested by setting REQOP[2:0] = 100.
The CAN FD Protocol module will protect the user from accidentally violating the CAN protocol through programming
errors. The following registers and bit fields can only be programmed during Configuration mode:
•
•
CxCON: WAKFIL, CLKSEL, PXEDIS, ISOCRECEN, TXQEN, STEF, SERRLOM, ESIGM, RTXAT
CxNBTCFG, C1DBTCFG and C1TDC
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•
•
•
•
CxTXQCON: PLSIZE[2:0], FSIZE[4:0]
CxFIFOCON: TXEN, RXTSEN, PLSIZE[2:0], FSIZE[4:0]
CxTEFCON: TEFTSEN, FSIZE[4:0]
CxFIFOBA
The CAN FD Protocol module is not allowed to enter Configuration mode during transmission or reception to prevent
the module from causing errors on the CAN bus. The following registers are Reset when exiting Configuration mode:
•
•
•
CxTREC
CxBDIAG0
CxBDIAG1
In Configuration mode, FRESET is set in the CxFIFOCON, CxTXQCON, and CxTEFCON registers, and all FIFOs
and the TXQ are Reset.
38.2.3
Normal Modes
38.2.3.1 Normal CAN FD Mode
Once the device is configured, Normal Operation mode can be requested by setting REQOP[2:0] = 000. In this
mode, the device will be on the CAN bus. It can transmit and receive messages in CAN FD mode, Bit Rate Switching
can be enabled and up to 64 data bytes can be transmitted and received.
38.2.3.2 Normal CAN 2.0 Mode
The Normal CAN 2.0 Operation mode can be requested by setting REQOP[2:0] = 110. In this mode, the device will
be on the CAN bus. This is a the Classic CAN 2.0 mode. The module will not receive CAN FD frames. It might send
error frames if CAN FD frames are detected on the bus. The FDF, BRS and ESI bits in the TX objects will be ignored
and transmitted as ‘0’.
38.2.4
Disable Mode
Disable mode is similar to Configuration mode, except the error counters are not Reset. Disable mode is requested
by setting REQOP[2:0] = 001. The CAN module will not be allowed to enter Disable mode while a transmission or
reception is taking place to prevent causing errors on the CAN bus. The module will enter Disable mode when the
current message completes.
The OPMODx bits indicate whether the module successfully entered Disable mode. The application software needs
to use this bit field as a handshake indication for the Disable mode request. The CxTX pin will stay in the recessive
state while the module is in Disable mode to prevent inadvertent CAN bus errors.
38.2.5
Debug Modes
38.2.5.1 Listen Only Mode
Listen Only mode is a variant of Normal CAN FD Operation mode. If the Listen Only mode is activated, the module
on the CAN bus is passive. It will receive messages, but it will not transmit any bits. TXREQx bits will be ignored. No
error flags or Acknowledge signals are sent. The error counters are deactivated in this state. The Listen Only mode
can be used for detecting the baud rate on the CAN bus. It is necessary that there are at least two further nodes that
communicate with each other. The baud rate can be detected empirically by testing different values until a message
is received successfully. This mode is also useful for monitoring the CAN bus without influencing it.
38.2.5.2 Restricted Operation Mode
In Restricted Operation mode, the node is able to receive data and remote frames, and to Acknowledge valid frames,
but it does not send data frames, remote frames, error frames or overload frames. In case of an error or overload
condition, it does not send dominant bits; instead, it waits for the bus to enter the Idle condition to resynchronize itself
to the CAN communication. The error counters are not incremented.
38.2.5.3 Loopback Mode
Loopback mode is a variant of Normal CAN FD Operation mode. This mode will allow internal transmission of
messages from the transmit FIFOs to the receive FIFOs. The module does not require an external Acknowledge from
the bus. No messages can be received from the bus, because the CxRX pin is disconnected.
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38.2.5.3.1 Internal Loopback Mode
The transmit signal is internally connected to receive and the CxTX pin is driven high.
38.2.5.3.2 External Loopback Mode
The transmit signal is internally connected to receive and transmit messages and can be monitored on the CxTX pin.
38.2.6
Low-Power Modes
38.2.6.1 Sleep Mode
In the CAN module, special conditions need to be met for Sleep mode. The module must first be switched to Disable
mode by setting REQOPx = 001. When OPMODx = 001, indicating Disable mode has been achieved, the CAN FD
Protocol Module enters Sleep mode after a Sleep mode request.
In Sleep mode, the register content does not change, so the OPMODx bits do not change. At the end of Sleep, the
module will continue in the mode specified by the OPMODx bits previous to Sleep mode (which needs to be Disable
mode, OPMODx = 001). If the user executes a SLEEP instruction without switching to Disable mode, the module
assumes a clock is available to read/write from RAM. Since the system clock input is not available in Sleep mode, the
CAN module cannot run as it requires a system clock to transmit or receive. Also, the FIFO is in system RAM, which
has no clock in Sleep mode.
Recommended steps:
1. Write the REQOP[2:0] bits to ‘001’; the module will enter Disable mode.
2. Poll the OPMOD[2:0] bits to verify whether they are ‘001’, which indicates that the module has successfully
entered Disable mode.
3. Execute the SLEEP instruction.
38.2.6.2 Idle Mode
The system can be set to run in a Low Power mode, called Idle mode. When the device is in Idle mode, the CPU
is disabled and only select peripherals are active. Based on the configuration of the CAN SIDL bit, the module can
either be in or out of Idle mode:
• If SIDL = 0, the module continues operation in Idle mode. If the module generates an interrupt while in Idle mode,
the interrupt may generate a wake-up event.
• If SIDL = 1, the module stops when the device is in Idle mode. The module performs the same procedures when
stopped in Idle mode as it does in Disable mode and the same requirements apply.
The user needs to ensure that the module is not active when the CPU transitions to Idle mode with SIDL = 1. To
protect the CAN bus system from fatal consequences due to violation of this rule, the module will drive the TX pin into
the Recessive state while stopped in Idle mode. If the CAN SIDL bit is set, the recommended procedure is to bring
the module into Disable mode before the device is placed in Idle mode.
38.2.6.3 Wake-Up From Sleep
Upon a wake-up from Sleep mode, the WAKIF flag is set.
The module will monitor the CAN receive line for activity while the module is Sleeping. The device will generate a
wake-up interrupt on the falling edges of CxRX if WAKIE is enabled.
The device will exit Sleep mode after a new mode request or a negative edge on CxRX.
The module will be in Sleep mode if either of the following is true:
• The system is in Sleep mode following Disable mode.
• The system is in Idle mode with SIDL = 1.
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Notes:
1. If the module is in Sleep mode, the module generates an interrupt if the WAKIE bit (C1INT[30]) is set and bus
activity is detected. Due to delays in starting up the oscillator and CPU, the message activity that caused the
wake-up will be lost.
2. The module can be programmed to apply a low-pass filter function to the CAN receive input line while in
Disable, Sleep or Idle mode. This feature can be used to protect the module from wake-up due to short
glitches on the CAN bus lines. The WAKFIL bit (C1CON[8]) enables or disables the filter while the module is
asleep.
38.3
Configuration
38.3.1
Clock Configuration
The sample point of all nodes in a CAN FD network needs to be at the same position. Hence, it is recommended to
use the same clock frequency and bit time settings for all nodes. Therefore, a CAN Clock of 40 MHz or 20 MHz is
recommended.
The CLKSEL bit allows the selection of the clock source to the CAN FD module.
• If CLKSEL = 1, then the external clock (EXTCLK) will be selected.
• If CLKSEL = 0, then the system clock (FOSC) will be selected.
38.3.2
CAN Configuration
The C1CON register contain several bits that can only be configured in Configuration mode.
38.3.2.1 ISO CRC Enable
The module supports ISO CRC (according to ISO11898-1:2015) and non-ISO CRC (see 38.4.1 ISO vs. Non-ISO
CRC). ISO CRC is enabled by setting the ISOCRCEN bit.
38.3.2.2 Protocol Exception Disable
The negative edge between the FDF bit and the “reserved bit” in CAN FD frames is important for the calculation of
the transceiver delay and for hard synchronization. Therefore, if the “reserved bit” following the FDF bit is detected
recessive, the CAN FD Protocol Module will treat this as a form error. This is called, “Protocol Exception Event
Detection Disabled” and is configured by setting the PXEDIS bit. The Protocol Exception Event Detection Disabled
can be enabled by clearing the PXEDIS bit. As a reaction to the protocol exception event, the error counters are not
changed, hard synchronization is enabled, the module sends recessive bits and enters the bus integration state.
38.3.2.3 Wake-up Filter
The WAKFIL bit is used to enable/disable the low-pass filter on the CxRX pin. The filter is only active during Sleep
mode. The WFTx bits allow the configuration of different filter times.
38.3.2.4 Restriction of Transmission Attempts
ISO11898-1:2015 requires that frames that lost arbitration and are not Acknowledged, or are destroyed by errors, are
automatically retransmitted. Optionally, the number of retransmission attempts can be limited. When the RTXAT bit is
set, retransmission attempts can be limited using the TXAT[1:0] bits in the FIFO Control registers. If the RTXAT bit is
clear, then the TXATx bits in the FIFO Control register are ignored and the retransmission attempts are unlimited.
38.3.2.5 Error State Indicator (ESI) in Gateway Mode
Normally, the ESI bit in a transmitted message reflects the error status of the CAN FD Protocol module. ESI is
transmitted recessive when the module is error passive. In case the module is used in a gateway application, there
will be situations where the ESI bit in the message needs to be transmitted recessive, even though the gateway
module is error active. This can be configured by setting the ESIGM bit.
38.3.2.6 Mode Selection In Case of System Error
The SERRLOM bit selects which mode the module will transition to in case of a system error. The module can either
transition to Restricted Operation mode or Listen Only mode.
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38.3.2.7 Reserving Message Memory for TXQ and TEF
Setting the TXQEN bit will reserve RAM for the TXQ. If the TXQEN bit is cleared, then the TXQ cannot be used.
Setting the STEF bit will reserve RAM for the TEF and all transmitted messages will be stored in the TEF.
38.3.3
CAN FD Bit Time Configuration
In order to achieve higher bandwidth, bits in a CAN FD frame are transmitted with two different bit rates:
• Nominal Bit Rate (NBR): Used during arbitration until the sample point of the BRS bit and the sample point of
the CRC delimiter reach the EOF
• Data Bit Rate (DBR): Used during the data and CRC field
NBR is limited by the propagation delay of the CAN network (see 38.3.3.2 Propagation Delay). In the data phase,
only one transmitter remains; therefore, the bit rate can be increased. The transmitting node always compares
the intended transmitted bits with the actual bits on the CAN bus. The propagation delay in the data phase can
be longer than the bit time. In this case, the data bits are sampled at a Secondary Sample Point (SSP) (see
38.3.3.3 Transmitter Delay Compensation (TDC)).
NBR is the number of bits per second during the arbitration phase. It is the inverse of the Nominal Bit Time (NBT)
(see Equation 38-1).
Equation 38-1. Nominal Bit Rate/Time
NBR =
1
NBT
DBR is the number of bits per second during the data phase. It is the inverse of the Data Bit Time (DBT) (see
Equation 38-2).
Equation 38-2. Data Bit Rate/Time
DBR =
1
DBT
The Baud Rate Prescaler (BRP) is used to divide the SYSCLK. The divided SYSCLK is used to generate the bit
times. There are two prescalers: NBRP for the Nominal Bit Rate Prescaler and DBRP for the Data Bit Rate Prescaler.
The Time Quanta (NTQ and DTQ) are selected as shown in Equation 38-3 and Equation 38-4.
Equation 38-3. Nominal Time Quanta
NTQ = NBRP × TSYSCLK = NBRP
FSYSCLK
Equation 38-4. Data Time Quanta
DTQ = DBRP × TSYSCLK = DBRP
FSYSCLK
CAN bit times have four segments, as specified in ISO11898-1:2015 (see Figure 38-3).
Synchronization Segment (SYNC) – Synchronizes the different nodes connected on the CAN bus. A bit edge is
expected to be within this segment. The Synchronization Segment is always one TQ.
Propagation Segment (PRSEG) – Compensates for the propagation delay on the bus. PRSEG has to be longer
than the maximum propagation delay.
Phase Segment 1 (PHSEG1) – Compensates for errors that may occur due to phase shifts in the edges. The time
segment may be automatically lengthened during resynchronization to compensate for the phase shift.
Phase Segment 2 (PHSEG2) – Compensates for errors that may occur due to phase shifts in the edges. The time
segment may be automatically shortened during resynchronization to compensate for the phase shift.
In the Bit Time registers, PRSEG and PHSEG1 are combined to create TSEG1. PHSEG2 is called TSEG2. Each
segment has multiple Time Quanta (TQ). The sample point lies between TSEG1 and TSEG2. Table 38-1 and Table
38-2 show the ranges for the bit time configuration parameters.
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Figure 38-3. Partition of Bit Time
TBIT
SY
NC
PRSEG
SY
NC
PHSEG1
TSEG1
PHSEG2
TSEG2
Sample Point
The total number of TQ in a bit time is programmable and can be calculated using Equation 38-5 and Equation 38-6.
Equation 38-5. Number of NTQ in a NBT
NBT = NSYNC + NTSEG1 + NTSEG2
NTQ
Equation 38-6. Number of DTQ in a DBT
DBT = DSYNC + DTSEG1 + DTSEG2
DTQ
Table 38-1. Nominal Bit Rate Configuration Ranges
Segment
Minimum
Maximum
NSYNC
1
1
NTSEG1
2
256
NTSEG2
1
128
NSJW
1
128
NTQ per Bit
4
385
Table 38-2. Data Bit Rate Configuration Ranges
Segment
Minimum
Maximum
DSYNC
1
1
DTSEG1
1
32
DTSEG2
1
16
DSJW
1
16
DTQ per Bit
3
49
38.3.3.1 Sample Point
The sample point is the point in the bit time at which the logic level of the bit is read and interpreted. The sample point
in percent can be calculated using Equation 38-7 and Equation 38-8.
Equation 38-7. Nominal Sample Point (%)
NSP = 1 + NTSEG1 × 100
NBT
NTQ
Equation 38-8. Data Sample Point (%)
DSP = 1 + DTSEG1 × 100
DBT
DTQ
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38.3.3.2 Propagation Delay
Figure 38-4 illustrates the propagation delay between two CAN nodes on the bus, assuming Node A is transmitting
a CAN message. The transmitted bit will propagate from the transmitting CAN Node A through the transmitting CAN
transceiver, over the CAN bus, through the receiving CAN transceiver and into the receiving CAN Node B. During the
arbitration phase of a CAN message, the transmitter samples the CAN bus and checks if the transmitted bit matches
the received bit. The transmitting node has to place the sample point after the maximum propagation delay.
Equation 38-9 describes the maximum propagation delay; where tTXD – RXD is the propagation = delay of the
transceiver, a maximum of 255 ns according to ISO11898-1:2015. TBUS is the delay on the CAN bus, which is
approximately 5 ns/m. The factor 2 comes from the worst-case when Node B starts transmitting exactly when the bit
from Node A arrives.
Equation 38-9. Maximum Propagation Delay
TPROP = 2 × tTXD − RXD + TBUS
Figure 38-4. Propagation Delay
38.3.3.3 Transmitter Delay Compensation (TDC)
During the data phase of a CAN FD transmission, only one node is transmitting; the others are receiving. Therefore,
the propagation delay does not limit the maximum data rate. When transmitting via pin CxTX, the CAN FD Protocol
Module receives the transmitted data from its local CAN transceiver via pin CxRX. The received data are delayed by
the CAN transceiver’s loop delay. In case this delay is greater than 1 + DTSEG1, a bit error would be detected.
In order to enable a data phase bit time that is shorter than the transceiver loop delay, the Transmitter Delay
Compensation (TDC) is implemented. Instead of sampling after DTSEG1, a Secondary Sample Point (SSP) is
calculated and used for sampling during the data phase of a CAN FD message.
Figure 38-5 illustrates how the transceiver loop delay is measured and Equation 1-10 shows how the SSP is
calculated.
Equation 38-10. Secondary Sample Point
SSP = TDCV 5: 0 + TDCO 6: 0
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Figure 38-5. Measurement of Transceiver Delay (TDCV)
FDF
res
TXCAN Arbitration
BRS
ESI
DLC
Data
Phase
Phase
FDF
RXCAN
Arbitration
Data
Phase
Phase
Transmitter Delay
Start
Stop
CiDBTCFG.TSEG1
Transmitter
Delay
Measurement
Secondary Sample Point (SSP)
38.3.3.4 Synchronization
To compensate for phase shifts between the oscillator frequencies of the nodes on the CAN bus, each CAN controller
must be able to synchronize to the relevant edge of the incoming signal. The CAN controller expects an edge in the
received signal to occur within the SYNC segment. Only recessive-to-dominant edges are used for synchronization.
There are two mechanisms used for synchronization:
• Hard Synchronization – Forces the edge that has occurred to lie within the SYNC segment. The bit time
counter is restarted with SYNC.
• Resynchronization – If the edge falls outside the SYNC segment, PHSEG1 or PHSEG2 will be adjusted.
For a more detailed description of the CAN synchronization, please refer to ISO11898-1:2015.
38.3.3.5 Synchronization Jump Width
The Synchronization Jump Width (SJW) is the maximum amount that PHSEG1 and PHSEG2 can be adjusted during
resynchronization. SJW is programmable (see Table 38-1 and Table 38-2).
38.3.3.6 Oscillator Tolerance
The oscillator tolerance, df, around the nominal frequency of the oscillator, fnom, is defined in Equation 38-11.
Equation 38-12 through Equation 38-16 describe the conditions for the maximum tolerance of the oscillator.
Equation 38-11. Oscillator Tolerance
1 − df × fnom ≤ FSYSCLK ≤ 1 + df × fnom
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Equation 38-12. Condition 1
NSJW
df ≤
NBT
2 × 10 × NTQ
Equation 38-13. Condition 2
min NPHSEG1, NPHSEG2
df ≤
NBT
2 × 13 × NTQ
− NPHSEG2
Equation 38-14. Condition 3
DSJW
df ≤
DBT
2 × 10 × DTQ
Equation 38-15. Condition 4
min NPHSEG1, NPHSEG2
df ≤
DBT
DBRP
NBT
2 × 6 × DTQ − DPHSEG2 × NBRP
+ 7 × NTQ
Equation 38-16. Condition 5
df ≤
2×
DSJW − max 0, NBRP
DBRP − 1
NBT
DBT
2 × NTQ
× HNSEGP2 × NBRP
DBRP + DPHSEG2 + 4 × DTQ
38.3.3.7 Recommendations for Bit Time Configuration
The following recommendations need to be considered when configuring the bit time:
•
•
•
•
•
•
Select the highest available CAN clock frequency:
– Short TQ leads to high resolution to select the sample point.
– Use 20 MHz or 40 MHz for SYSCLK.
Select the lowest NBRP and DBRP:
– Low BRP leads to short TQ.
– NSYNC and DSYNC will be short and reduce the quantization error.
– The receiving node can synchronize more accurately to the transmitting node.
Set NBRP equal to DBRP:
– Identical TQ in both phases prevents quantization errors during Bit Rate Switching.
Use the same Nominal Sample Point (NSP) and Data Sample Point (DSP) in all nodes on the CAN FD network:
– Different sample points in the different nodes lead to different lengths of the BRS and CRC delimiter bits
and introduce phase errors when switching the bit rate.
– NSP need not be equal to the DSP.
– The SSP can be different in differing CAN FD nodes.
Select the largest possible NSJW and DSJW:
– Maximizes the oscillator tolerance.
– Allows the receiving nodes to quickly resynchronize to the transmitting nodes.
Enable automatic TDC for DBR of 1 Mbps and higher:
– Automatic TDC measurement compensates for transmitter delay variations.
38.3.3.8 Bit Time Configuration Example
The following tables illustrate the configuration of the CAN FD Bit Time registers, assuming there is a CAN FD
network in an automobile with the following parameters:
• 500 kbps NBR – sample point at 80%
• 2 Mbps DBR – sample point at 80%
• 40 Meters – minimum bus length
Table 38-3 and Table 38-4 illustrate how the bit time parameters are calculated. Since the parameters depend on
multiple constraints and equations, and are calculated using an iterative process, it is recommended to enter the
equations in a spreadsheet.
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Table 38-5 translates the calculated values into register values. It is recommended to let the CAN FD Protocol
module measure the Transmitter Delay Compensation Value (TDCV). This is accomplished by setting TDCMOD[1:0]
(C1TDCH[1:0]) = 10 (Automatic mode). In order to set the SSP to 80%, TDCO[6:0] are set to 1 + DTSEG1.
Table 38-3. Step-by-Step Nominal Bit Rate Configuration
Parameter
Constraint
Value
Unit
Equations and
Comments
NBT
NBT ≥ µs
2
us
Equation 38-1
FSYSCLK
FSYSCLK ≤ 40 MHz
40
MHz
CAN clock frequency
= 40 MHz
NBRP
1 to 256
1
-
Select smallest
possible BRP
value to maximize
resolution.
NTQ
NBT, FSYSCLK
12.5
ns
Equation 38-3
NBT/NTQ
4 to 385
160
-
Equation 38-5
NSYNC
Fixed
1
NTQ
Defined in
ISO11898-1:2015
NPRSEG
NPRSEG > TPROP
95
NTQ
Equation 38-9;TPROP
= 910 ns,
minimum NPRSEG =
TPROP/NTQ = 72.8
NTQ. Selecting 95
will allow up to a 60m
bus length
NTSEG1
2 to 256 NTQ
127
NTQ
Equation 38-7. Select
NTSEG1 to achieve
80% NSP.
NTSEG2
1 to 128 NTQ
32
NTQ
There are 32
NTQ left to reach
NBT/NTQ = 160
NSJW
1 to 128 NTQ; SJW
≤ min(NPHSEG1,
NPHSEG2)
32
NTQ
Maximizing NSJW
lessens the
requirement for the
oscillator tolerance.
Table 38-4. Step-by-Step Data Bit Rate Configuration
Parameter
Constraint
Value
Unit
Equations and
Comments
DBT
DBT ≥ 125 ns
500
ns
Equation 38-2
DBRP
1 to 256
1
-
Selecting the same
prescaler as for NBT
ensures that to the
TQresolution does not
change during the Bit
Rate Switching
DTQ
DBT, FSYSCLK
12.5
ns
Equation 38-4
DBT/DTQ
3 to 49
40
-
Equation 38-6
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...........continued
Parameter
Constraint
Value
Unit
Equations and
Comments
DSYNC
Fixed
1
DTQ
Defined in
ISO11898-1:2015.
DTSEG1
1 to 32 DTQ
31
DTQ
Equation 38-8
DTSEG2
1 to 16 DTQ
8
DTQ
There are 8 DTQ left
to reach DBT/DTQ =
40
DSJW
1 to 16 DTQ; SJW
≤min (DPHSEG1,
DPHSEG2)
8
DTQ
Maximizing DSJW
lessens the
requirement for the
oscillator tolerance
Oscillator Tolerance
Conditions 1-5
Minimum of
Conditions 1-5
.78
%
Equation
38-11through
Equation 38-16
Table 38-5. Bit Time Register Initialization (500k/2M)
38.3.4
CxNBTCFG
Value
CxDBTCFG
Value
CxTDC
Value
BRP[7:0]
0
BRP[7:0]
0
TDCMOD[1:0]
2
TSEG[7:0]
126
TSEG[7:0]
30
TDCO[6:0]
31
TSEG2[6:0]
31
TSEG2[6:0]
7
TDCV[5:0]
0
SJW[6:0]
31
SJW[6:0]
7
-
-
Message Memory Configuration
The message objects of the TEF, TXQ and transmit/receive FIFOs are located in RAM (see Figure 38-6). The
application must configure the number of message objects in a FIFO between Message Object 0 and Message
Object 31. Additionally, the application must configure the payload size of the message objects in each FIFO. This
configuration determines where message objects are located in RAM. The RAM allocation can only be configured in
Configuration mode.
To optimize RAM usage, the application needs to start configuring the RAM with the TEF, followed by the TXQ, and
continue with FIFO 1, FIFO 2 and FIFO 3.
Figure 38-6. Message Memory Organization
TEF
TXQ
FIFO 1
FIFO 2: Message Object 0
FIFO 2: Message Object 1
FIFO 2: Message Object n
FIFO 3
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38.3.4.1 Transmit Event FIFO Configuration
In order to reserve space in RAM for the TEF, the STEF bit (C1CON[19]) has to be set. The number of message
objects in the TEF is configured using the FSIZE[4:0] bits (C1TEFCON[27:23]). Transmitted messages can be
timestamped by setting the TEFTSEN bit (C1TEFCON[5]).
38.3.4.2 Transmit Queue Configuration
In order to reserve space in RAM for the TXQ, the TXQEN bit (C1CON[19]) has to be set. The number of message
objects in the TXQ is configured using the FSIZE[4:0] bits (C1TXQCON[27:23]). All objects in the TXQ use the same
payload size (number of data bytes), which is configured using the PLSIZE[2:0] bits (C1TXQCON[30:28]).
38.3.4.3 Transmit FIFO Configuration
FIFO 1 through FIFO 3 can be configured as transmit FIFOs by setting TXEN in the CxFIFOCONy register. The
number of message objects in each transmit FIFO is configured using the FSIZE[4:0] bits (CxFIFOCONy[27:23]).
All objects in one transmit FIFO use the same payload size (number of data bytes), which is determined by the
PLSIZE[2:0] bits (CxFIFOCONy[30:28]).
38.3.4.4 Receive FIFO Configuration
FIFO 1 through FIFO 3 can be configured as receive FIFOs by clearing TXEN in the CxFIFOCONy register. The
number of message objects in each receive FIFO is configured using the FSIZE[4:0] bits (CxFIFOCONy[27:23]).
All objects in one receive FIFO use the same payload size (number of data bytes), which is determined by
the PLSIZE[2:0] bits (CxFIFOCONy[30:28]). Received messages can be timestamped by setting the RXTSEN bit
(CxFIFOCONy[5]).
38.3.4.5 Calculation of Required Message Memory
The size of required RAM depends on the configuration of each FIFO. Equation 38-17 through Equation 38-19
specify the sizes of the TEF, TXQ and the FIFOs in bytes. The TEF or TXQ is not used if their size is zero.
Since the size of the integrated RAM is limited, the user must check that the memory configuration fits into RAM.
Equation 38-20 can be used to calculate the total RAM usage in bytes.
The size of the TEF objects depends on the enabling of timestamping. If TEFTSEN is set, then tefts = 4, else tefts =
0.
The PayLoad(i) is defined in data bytes.
The size of a message object of an RX FIFO varies dependent on the enabling of timestamping. If RXTSEN = 1 and
TXEN = 0 for FIFO(i), then rxts(i) = 4, else rxts(i) = 0.
N is defined as the number of FIFOs used in addition to the TEF and the TXQ.
Equation 38-17. Size of TEF
STEF = NELEMENTS TEF × tefts + 8
Equation 38-18. Size of TXQ
STXQ = NELEMENTS TXQ × 8 + PayLoad TXQ
Equation 38-19. Size of FIFOs
SFIFO i = NELEMENTS i × rxts i + 8 + PayLoad i
Equation 38-20. Total RAM Usage
SRAM = STEF + STXQ +
N
i=1
SFIFO i
For example:
• If TEF is 4 messages deep (NElements (TEF) = 4) and TEFTSEN is clear, then the size of TEF = STEF = 4 x (0 +
8) = 32 bytes
• If NElements (TXQ) = 1, PayLoad (TXQ) = 12, then the size of TXQ = STXQ = 1 x (8 + 12) = 20 bytes
• If NElements (FIFO) = 3, PayLoad (FIFO) = 8, then the size of FIFO = SFIFO = 3 x (8 + 8) = 48 bytes
Therefore, SRAM = STEF + STXQ + SFIFO = 32 + 20 + 48 = 100 bytes.
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38.4
CAN FD Message Frames
The ISO11898-1:2015 describes the different CAN message frames in detail. Figure 38-7 through Figure 38-12
explain and summarize the construction of the messages and fields.
There are four different CAN data/remote frames (see Figure 38-8):
• CAN Base Frame: Classic CAN 2.0 frame using Standard ID
• CAN FD Base Frame: CAN FD frame using Standard ID
• CAN Extended Frame: Classic CAN 2.0 frame using Extended ID
• CAN FD Extended Frame: CAN FD frame using Extended ID
There are no remote frames in CAN FD frames; therefore, the RTR bit is replaced with the RRS bit (see Figure 38-8).
The RRS bit in the CAN FD base frame can be used to extend the SID to 12 bits. When enabled, it is referred to as
SID11; it is the Least Significant bit (LSb) of SID[11:0].
Figure 38-9 specifies the control field of the different CAN messages. Before CAN FD was added to the
ISO11898-1:2015, the FDF bit was a reserved bit. Now the FDF bit selects between Classic and CAN FD formats.
The BRS bit selects if the bit rate needs to be switched in the data phase of CAN FD frames. Figure 38-12 illustrates
the error and overload frames. These special frames do not change.
Note: If an error is detected during the data phase of a CAN FD frame, the bit rate will be switched back to the
Nominal Bit Rate (NBR). Error frames are always transmitted at the arbitration bit rate.
38.4.1
ISO vs. Non-ISO CRC
To support the system validation of non-ISO CRC ECUs, the CAN FD Controller module supports both ISO CRC
(according to ISO11898-1:2015) and non-ISO CRC (see Figure 38-10 and Figure 38-11). The CRC field is selectable
using the ISOCRCEN bit (C1CON[5]). The ISO CRC field contains the stuff count. This count was not included in the
original CAN FD specification; it was added to fix a minor issue in the error detection of the original specification.
CAN FD frames use two different lengths of CRC: 17-bit for up to 16 data bytes and 21-bit for 20 or more data bytes.
Technically, there are a total of six different CAN data/remote frames in the CAN FD.
Figure 38-7. General Data Frame
DATA FRAME
IFS
( 3b)
SOF
(1b)
ARBITRATION(12/32b) CTRL(6/8/9b)
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DATA
(0 to 64B)
CRC(16/18/22b)
CRC(16/22/26b)
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ACK(2b) EOF(7b)
IFS
( 3b)
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Figure 38-8. Arbitration Field
ARBITRATION(12/32b)
CAN BASE
SID
RTR
CAN FD BASE
SID[10:0]
RRS
SID11
CAN EXT
EID[28:18]
SRR
IDE
EID[17:0]
RTR
CAN FD EXT
EID[28:18]
SRR
IDE
EID[17:0]
RRS
Figure 38-9. Control Field
CTRL(6/8/9b)
CAN BASE
IDE
FDF
CAN FD BASE
IDE
FDF
res
CAN EXT
FDF
r0
CAN FD EXT
FDF
res
© 2021 Microchip Technology Inc.
DLC[3:0]
BRS
ESI
DLC[3:0]
DLC[3:0]
BRS
ESI
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Figure 38-10. ISO CRC Field
CRC(16/22/26b)
CAN BASE
CRC
DEL
CRC(15b)
STUFF
CNT (4b)
CAN FD BASE
CAN EXT
CRC(17/21b)
CRC
DEL
CRC(15b)
STUFF
CNT (4b)
CAN FD EXT
CRC
DEL
CRC(17/21b)
CRC
DEL
Figure 38-11. NON_ISO CRC Field
CRC(16/18/22b)
CAN BASE
CAN FD BASE
CAN EXT
CAN FD EXT
CRC(15b)
CRC
DEL
CRC(17/21b)
CRC
DEL
CRC(15b)
CRC
DEL
CRC(17/21b)
CRC
DEL
Figure 38-12. Error and Overload Frame
ERROR
ANYWHERE WITHIN DATA FRAME
ERRFLAG(6b)
ERRDEL(8b)
IFS ( 3b) or OVL
OVERLOAD
EOF or ERRDEL or OVLDEL
OVLFLAG(6b)
OVLDEL(8b)
IFS ( 3b) or OVL
38.4.1.1 DLC Encoding
The Data Length Code (DLC) specifies the number of data bytes a message frame contains. Table 38-6 illustrates
the encoding.
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Table 38-6. DLC Encoding
38.5
Frame
DLC
Number of Data Bytes
CAN 2.0 and CAN FD
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
CAN 2.0
9-15
8
CAN FD
9
12
10
16
11
20
12
24
13
32
14
48
15
64
Message Transmission
The application needs to configure the FIFO or TXQ before it can be used for transmission (see 38.3.4.3 Transmit
FIFO Configuration and 38.3.4.2 Transmit Queue Configuration).
38.5.1
Transmit Message Object
Table 38-7 specifies the transmit message object used by the TXQ and the transmit FIFOs. The transmit objects
contain the message ID, control bits and payload.
• SID: Standard Identifier or Base Identifier.
• EID: Extended Identifier.
• DLC: Data Length Code; specifies the number of data bytes to transmit (see 38.4.1.1 DLC Encoding).
• IDE: Identifier Extension; clearing this bit will transmit a base frame, setting this bit will transmit an extended
frame.
• RTR: Remote Transmit Request; this bit is only specified in CAN 2.0 frames. Setting this bit will request a
transmission of a receiving node.
• FDF: FD Format; if this bit is set, a CAN FD frame will be transmitted; otherwise, a CAN 2.0 frame will be
transmitted. If Normal CAN 2.0 mode is selected, this bit is ignored and only CAN 2.0 frames are transmitted.
• BRS: Bit Rate Switch; the data phase of a CAN FD frame will be transmitted using DBR if this bit is set. If the bit
is clear, the whole frame will be transmitted using NBR.
• ESI: Error State Indicator; normally, the ESI bit reflects the error status of the transmitting node. A recessive
ESI bit in a CAN FD frame indicates that the transmitting node is error passive; a dominant bit shows that the
transmitting node is error active. If ESIGM (C1CON[17]) = 0, this bit in the object is ignored. If ESIGM = 1, the
ESI bit in the transmitted message will be transmitted recessive if the CAN FD Protocol Module is error passive,
or if the ESI bit in the message object is set. A gateway application would use it to signal that the ESI bit of the
transmitting node is set.
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•
•
38.5.2
SEQ: Sequence Number; SEQ is not transmitted on the CAN bus. It is used to keep track of the transmitted
messages. SEQ is stored in the TEF message object.
Transmit Buffer Data: Contains the payload of the message. Only the number of data bytes specified by the
DLC are transmitted. Byte 0 is transmitted first, followed by 1, 2 and so on.
Loading Messages into Transmit FIFO
Before loading a message into the FIFO, the application must ensure that the FIFO is not full. There is space in the
FIFO if TFNRFNIF (CxFIFOSTAy[0]) is set. Loading a message into a full FIFO can corrupt a message that is being
transmitted.
The FIFO user address (CxFIFOUAy) points to the RAM of the next transmit message object where the application
needs to store the message. T0 of the transmit message object is loaded first, followed by T1, T2 and so on. The
maximum number of data bytes is limited by the configured payload. Only the number of data bytes specified by the
DLC have to be loaded.
After the message object is loaded into RAM, the FIFO needs to be incremented by setting the UINC
(CxFIFOCONy[8]) bit. Doing so will cause the CAN FD Protocol module to increment the head of the FIFO and
update CxFIFOUAy.
Now the message is ready for transmission and the next message can be loaded at the new address.
38.5.3
Loading Messages Into Transmit Queue
Loading transmit message objects into the TXQ works similarly to loading message objects into a transmit FIFO. The
application must check the CxTXQSTA register to see if there is space in the TXQ. The CxTXQUA registers need
to be used instead of the CxFIFOUAy registers to calculate the address to load the message and set the UINC bit
(CxTXQCON[8]) to increment the head of the TXQ.
Table 38-7. Transmit Message Object (TXQ and TX FIFO)
Byte
Bit 7
Bit 6
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SID[7:0]
1
EID[4:0]
2
SID[10:8]
EID[12:5]
3
-
-
SID11
4
FDF
BRS
RTR
5
EID[17:13]
IDE
SEQ[6:0]
6
SEQ[14:7]
7
SEQ[22:15]
8
Transmit Data Byte 0
9
Transmit Data byte 1
10
Transmit Data byte 2
11
Transmit Data byte 3
12
Transmit Data byte 4
13
Transmit Data byte 5
14
Transmit Data byte 6
15
Transmit Data byte 7
DLC[3:0]
ESI
………………………………………………………………………………………………………………………………………
…………
m-3
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Transmit Data byte n-3
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m-2
Transmit Data byte n-2
m-1
Transmit Data byte n-1
m
Transmit Data byte n
bit 15:11 EID[4:0]: Extended Identifier bits
bit 10-0 SID[10:0]: Standard Identifier bits
bit 15-14 Unimplemented: Read as ‘x’
bit 13 SID11: In FD mode, the Standard ID can be Extended to 12 bits using r1 bit
bit 12-0 EID[17:5]: Extended Identifier bits
bit 15-9 SEQ[6:0]: Bits 6-0 of sequence to keep track of transmitted messages in transmit event FIFO bits
bit 8 ESI: Error Status Indicator bit - In CAN to CAN Gateway mode (ESIGM (C1CONH[1]) = 1), the transmitted ESI
flag is a “logical OR” of ESI and the Error Passive state of the CAN controller.
In Normal mode, ESI indicates the error status:
1 = Transmitting node is error passive
0 = Transmitting node is error active
bit 7 FDF: FD Frame bit - distinguishes between CAN and CAN FD formats.
bit 6 BRS: Bit Rate Switch bit - selects if data bit rate is switched
bit 5 RTR: Remote Transmission Request bit (not used in CAN FD)
bit 4 IDE: Identifier Extension bit - distinguishes between base and extended format
bit 3-0 DLC[3:0]: Data Length Code bits
bit 15:0 SEQ[22:7]:Bits 22-7 Sequence to Keep Track of Transmitted Messages in Transmit Event FIFO bits
Note:
1. Data Bytes 0-2: Payload size is configured individually in the PLSIZE[2:0] bits (CxFIFOCONy[31:29]).
38.5.4
Requesting Transmission of Message in Transmit FIFO
After a message is loaded into a transmit FIFO, the message is ready for transmission. The application initiates the
transmission of all messages in a FIFO by setting the TXREQ bit (CxFIFOCONy[9]) or by setting the corresponding
bit in the C1TXREQ register. When all messages are transmitted, TXREQ gets cleared. The application can request
transmission of multiple FIFOs and the TXQ simultaneously. The FIFO or TXQ with the highest priority will start
transmitting first. Messages in a FIFO will be transmitted First-In First-Out.
Messages can be loaded into a FIFO while the FIFO is transmitting messages. Since TXREQ is cleared by the FIFO
automatically after the FIFO empties, UINC and TXREQ of the CxFIFOCONy register must be set at the same time
after appending a message. This ensures that all messages in the FIFO are transmitted, including the appended
messages.
38.5.5
Requesting Transmission of Message in Transmit Queue
After a message is loaded into the TXQ, the message is ready for transmission. The application initiates the
transmission of all messages in the queue by setting TXREQ (CxTXQCON[9]). When all messages have been
transmitted, TXREQ will be cleared. The application can request transmission of the TXQ and multiple FIFOs
simultaneously. The TXQ or FIFO of the CxTXQCON register with the highest priority will start transmitting first.
Messages in the TXQ will be transmitted based on their ID. The message with the highest priority ID and the lowest
ID value will be transmitted first.
Messages can be loaded into the TXQ while the TXQ is transmitting messages. Since TXREQ is cleared by the
TXQ automatically after the TXQ empties, UINC and TXREQ of the CxTXQCON register must be set at the same
time after appending a message. This ensures that all messages in the TXQ are transmitted, including the appended
messages.
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38.5.6
C1TXREQ Register
The CxTXREQ register contains the TXREQ[31:0] bits of the TXQ and of all the TX FIFOs. They have the following
purposes:
• The user application can request transmission of the TXQ and/or one or more TX FIFOs, using only one SPI
instruction, by setting the corresponding bits in the CxTXREQ register. Clearing a bit does NOT abort any
transmissions.
• Reading the CxTXREQ register gives information about which transmit FIFOs have transmissions pending.
CxTXREQ[0] is mapped to the TXQ, CxTXREQ[1] is mapped to TX FIFO 1, CxTXREQ[2] is mapped to TX FIFO 2
and so on.
38.5.7
Transmit Priority
The transmit priority of the FIFOs and TXQ needs to be configured using the TXPRIx bits (CxFIFOCONy[20:16] and
CxTXQCON[20:16]).
Before transmitting a message, the priorities of the TXQ and the TX FIFOs queued for transmission are compared.
The FIFO/TXQ with the highest priority will be transmitted first. For example, if transmit FIFO 1 has a higher priority
setting than FIFO 3, all messages in FIFO 1 will be transmitted first. If multiple FIFOs have the same priority, the
FIFO with the highest index is transmitted. For example, if FIFO 1 and FIFO 3 have the same priority setting, all
messages in FIFO 3 will be transmitted first. If the TXQ and one or more FIFOs have the same priority, all messages
in the TXQ will be transmitted first.
The transmit priority will be recalculated after every successful transmission of a single message.
38.5.7.1 Transmit Priority of Messages in FIFO
In this method, the messages in a FIFO are transmitted First-In First-Out.
38.5.7.2 Transmit Priority of Messages in TXQ
Messages in the TXQ are transmitted based on the message ID. The message with the lowest message ID (highest
priority) is transmitted first.
38.5.7.3 Transmit Priority Based on ID
The goal of transmitting CAN messages based on ID is to avoid “Inner Priority Inversion”. If a low-priority message
is waiting to get transmitted due to bus traffic (arbitration), a higher priority message can be prevented from being
transmitted. The TXQ solves this issue by reprioritizing the messages in the queue based on priority (ID).
38.5.8
Transmit Bandwidth Sharing
The bandwidth sharing feature works as follows:
• After a successful transmission of a message, the module will remain Idle for n arbitration bit times before the
module attempts to transmit the next message; it suspends the next transmission.
• After the device has received a message, the module can transmit the next message as soon as the bus is Idle.
This allows other nodes on the bus to transmit their messages, even though they are of lower priority.
The number of arbitration bit times between transmissions can be configured using the TXBWS[3:0] bits
(C1CON[31:28]).
38.5.9
Retransmission Attempts
The number of retransmission attempts can be configured as follows:
• Retransmission attempts are disabled
• Three retransmission attempts
• Unlimited retransmissions
The retransmission attempts can be restricted by setting RTXAT (CxCON[16]). The number of retransmission
attempts can be configured individually for each transmit FIFO and the TXQ using TXAT[1:0] (CxFIFOCONy[22:21]
and CxTXQCON[22:21], respectively).
In case RTXAT = 0, unlimited retransmission attempts will be used for all transmit FIFOs and the TXQ, and TXATx
will be ignored.
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38.5.9.1 Retransmission Attempts Disabled
TXREQ will be cleared after the attempt to transmit the message. If the message is not successfully transmitted due
to loss of arbitration or due to an error, TXATIF in the CxFIFOSTAy or CxTXQSTA register will be set.
38.5.9.2 Three Retransmission Attempts
In case an error is detected during transmission, the CAN FD Protocol module will decrement the number of
remaining attempts and try to retransmit the message the next time the bus is Idle. In case arbitration is lost, the
number of remaining attempts will not change. If all retransmission attempts are exhausted, TXREQ will be cleared
and TXATIF in CxFIFOSTAy or CxTXQSTA will be set.
Before retransmitting the message, the transmit priority will be recalculated. The retransmission attempts will be
reinitialized if a different TX FIFO or TXQ is selected for transmission, or if a message is received after the last
transmission attempt.
38.5.9.3 Unlimited Retransmission
TXREQ will be cleared only after all messages in the TX FIFO or TXQ are successfully transmitted.
38.5.10 Aborting Transmission
A pending transmission can only be aborted before the transmission of the message starts, before the Start-of-Frame
(SOF).
The transmission of a specific FIFO can be aborted by clearing TXREQ in the CAN Transmit Queue Control register;
it cannot be aborted by clearing the bits in the CxTXREQ registers. Writing a ‘0’ to one of the bits in the CxTXREQ
registers will be ignored. The TXABT bit in the CAN FIFO Status y register will be set after a successful abortion.
TXREQ will remain set until the message either aborts or is successfully transmitted.
Setting ABAT (CxCON[27]) will abort all pending messages of all FIFOs. After all TXREQx bits are cleared, ABAT has
to be cleared in order to be able to transmit new messages.
Clearing TXREQ for a transmit FIFO will attempt to abort all transmissions in the FIFO. If a message is successfully
transmitted, the FIFO index will be updated as normal. If the message is successfully aborted, the FIFO index will not
change.
The user can then use the FIFO Message Index bits, FIFOCI[4:0] (CxFIFOSTAy[12:8]), to identify messages that are
transmitted. To reset the transmit FIFO index and erase all pending messages, the user can set the FRESET bit. The
FIFO can then be loaded with new messages to be transmitted.
38.5.11 Remote Transmit Request (RTR)
The CAN bus system has a method for allowing a host node to request data from another node. The host sends a
message with the RTR bit set. The message contains no data, only an address to trigger a filter match.
Remote frames are only specified for CAN 2.0 frames; they are not supported in CAN FD frames.
The filter that is configured to respond to a Remote Transmit Request will point to a FIFO that is configured for
transmission and RTREN has to be set.
Automatic remote data requests can be handled without MCU intervention. If a FIFO is properly configured, when a
filter matches and points to the FIFO, the FIFO will be queued for transmission.
The FIFO must be configured as follows:
• Set TXEN to ‘1’.
•
•
•
A filter must be enabled and loaded with a matching message identifier.
The Buffer Pointer for that filter must point to the TX FIFO (normally, a filter points to an RX FIFO).
RTREN bit must be set to ‘1’ to enable RTR.
•
The FIFO must be preloaded with at least one message to be sent.
When an RTR message is received and it matches a filter pointing to a properly configured transmit FIFO, the
TXREQ bit is set, queuing the object for transmission according to priorities.
A FIFO will only be transmitted if TXEN and RTREN are set, and if it is NOT empty. When a request for a remote
transmission occurs while the FIFO is empty, the event will be treated as an overflow and the RXOVIF bit will be set.
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38.5.12 Mismatch of DLC and Payload Size During Transmission
The PLSIZEx bits reserve a certain number of bytes in the transmit FIFO. The CAN FD Protocol module handles
mismatches between the DLC and payload size as follows:
• If the DLC is smaller than the reserved payload, the number of data bytes specified by the DLC will be transmitted.
• If the DLC is bigger than the reserved payload, the module will not transmit the message. Instead, it will set the
IVMIF (CxINT[15]) and DLCMM (CxBDIAG1[31]) flags and clear the TXREQ flag. The application can use the TEF to
identify the message that is not transmitted.
38.5.13 Transmit State Diagram
Figure 38-13 describes how messages are queued for transmission. It illustrates how the most important transmit
flags are set and cleared:
1. Messages are queued for transmission by setting the TXREQ flag.
2. The transmit priority will be determined. The FIFO or TXQ with the highest priority TXPRIx flag will be
selected. The index of the TX message in the FIFO or TXQ will be calculated.
3. The TX message is pending for transmission.
4. Transmission can only start when the bus is Idle.
5. A pending transmission can only be aborted before SOF is transmitted.
6. During the transmission of a message, the CAN FD Protocol module checks for the following:
6.1.
Loss of arbitration during the arbitration field.
6.2.
Transmit errors.
7. In case a message of a TX FIFO or the TXQ is transmitted successfully, the TXREQ will only be cleared
after all messages of the FIFO are transmitted. After the transmission of any message, the status flags of the
FIFO or TXQ are updated. In case STEF (CxCON[19]) is set, the message will be stored into the TEF and a
timestamp will be attached if enabled.
8. In case arbitration is lost, TXLARB of the TX FIFO or TXQ will be set and the device will switch over to
receiving the message (see 38.8 Message Reception).
9. In case an error is detected during the transmission of a message, an error frame will be transmitted and
the appropriate error flags will be set. Messages will be retransmitted according to 38.5.9 Retransmission
Attempts.
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Figure 38-13. Transmit State Diagram
IDLE
Any TXREQ
Calculate
TX Priority
Result: Index
New TX Index or
Received a Message?
Safe Msg to TEF
ABORT ALL
Clr All TXREQ
Set All TXABT
TX ABORT
Set
TXABT[Index]
c
Abort: Set ABAT
c
Re-Init TX
Attempts
Based on New
Index
TX
Pending[Index]
Wait for
Suspend Time
Clr TXREQ[Index]
Set
TXATIF[Index]
STEF = 1?
RX Message
TX Successful
Set TXIF[Index]
Clr TXREQ[Index]
Yes
TX In Progress
SOF
Transmit[Index]
c
TX Attempts Exhausted?
TX ERR
Set TXERRIF Flag
TX Attempts--
Lost Arbitration
Set
TXLARB[Index]
38.5.14 Resetting Transmit FIFO
A Transmit FIFO can be reset by:
• Setting FRESET (CxFIFOCONy[10]) or
• Placing the module in Configuration mode (OPMOD[2:0] = 100).
Resetting the FIFO will reset the head and tail pointers, and the CxFIFOSTAy register. The settings in the
CxFIFOCONy register will not change.
Before resetting a TX FIFO using FRESET, ensure no transmissions are pending.
38.5.15 Resetting Transmit Queue
The Transmit Queue can be reset by:
• Setting FRESET (CxTXQCON[10]) or
• Placing the module in Configuration mode (OPMOD[2:0] = 100).
Resetting the TXQ will reset the head and tail pointers, and the CxTXQSTA register. The settings in the CxTXQCON
register will not change.
Before resetting the TXQ using FRESET, ensure no transmissions are pending.
38.6
Transmit Event FIFO (TEF)
The TEF allows the application to keep track of the order and time in which the messages are transmitted. The TEF
works similarly to a receive FIFO. Instead of storing received messages, it stores transmitted messages. Messages
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are only saved if STEF (CxCON[19]) is set. The sequence number (SEQ) of the transmitted message is copied into
the TEF object. The payload data are not stored. Transmitted messages are timestamped if TEFTSEN is set.
Table 38-8 specifies the TEF object. The first two words of the TEF object are a copy of the transmit message object.
Optionally, the TEF object contains the timestamp when the message is transmitted.
38.6.1
Reading a TEF Object
Before reading a TEF object, the application must check that the TEF is not empty by reading the CxTEFSTA
register. The TEF is not empty if TEFNEIF is set.
The TEF user address points to the address in RAM of the next TEF object to read. The actual address in RAM is
calculated using Equation 1-21. TE0 of the TEF object is read first, followed by TE1 and TE2.
Equation 38-21. Start Address of the TEF Object
A = BaseAddress = CxFIFOBA
Note: CxFIFOBAH/L needs to be set to a value between 0x3800 and the end of RAM, leaving enough room to allow
the TEF and Transmit Queue (if enabled) as well as the FIFOs.
After the TEF object is read from RAM, the TEF needs to be incremented by setting UINC (CxTEFCON[8]). This will
cause the CAN FD Protocol module to increment the tail pointer and update CxTEFUA.
Now the next message can be read from the TEF.
38.6.1.1 Resetting the TEF
TEF can be reset by:
• Setting FRESET (CxTEFCON[10]) or
• Placing the module in Configuration mode (OPMOD[2:0] = 100).
Resetting the FIFO will reset the head and tail pointers, and the CxTEFSTA register. The settings in the CxTEFCON
register will not change.
Table 38-8. Transmit Event FIFO Object
Byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
0
Bit 2
Bit 1
Bit 0
SID[7:0]
1
EID[4:0]
SID[10:8]
2
EID[12:5]
3
-
-
SID11
4
FDF
BRS
RTR
5
EID[17:13]
IDE
SEQ[6:0]
6
SEQ[14:7]
7
SEQ[22:15]
8
TXMSGTS[7:0]
9
TXMSGTS[15:8]
10
TXMSGTS[23:16]
11
TXMSGTS[31:24]
DLC[3:0]
ESI
bit 15-11 EID[4:0]: Extended Identifier bits
bit 10-0 SID[10:0]: Standard Identifier bits
bit 15-14 Unimplemented: Read as ‘x’
bit 13 SID11: In FD mode, the Standard ID can be Extended to 12 Bits using r1 bit
bit 12-0 EID17:5: Extended Identifier bits
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bit 15-9 SEQ[6:0]: Bits 6-0 of the sequence to keep track of transmitted messages in Transmit Event FIFO
bit 8 ESI: Error Status Indicator bit
In CAN-to-CAN Gateway mode (ESIGM (CxCON[17]) = 1), the transmitted ESI flag is a “logical OR” of ESI and the
error passive state of the CAN controller.
In Normal mode, ESI indicates the error status:
1 = Transmitting node is error passive
0 = Transmitting node is error active
bit 7 FDF: FD Frame bit - distinguishes between CAN and CAN FD formats
bit 6 BRS: Bit Rate Switch bit - selects if Data Bit Rate is switched
bit 5 RTR: Remote Transmission Request bit (not used in CAN FD)
bit 4 IDE: Identifier Extension bit - distinguishes between base and extended format.
bit 3-0 DLC[3:0]: Data Length Code bits
bit 15-0 SEQ[22:7]: Bits 22-7 of the sequence to keep track of transmitted messages in Transmit Event FIFO
bit 15-0 TXMSGTS[15:0] Transmit Message Timestamp bits
bit 15-0 TXMSGTS[31:16]: Transmit Message Timestamp bits
Note:
1. TE4 and TE5 (TXMSGTSx) only exist in objects where TEFTSEN (CxTEFCON[5]) is set.
38.7
Message Filtering
All messages on a CAN network will be received by all nodes. In order to process only messages of interest, a
hardware filtering mechanism is implemented. The CAN FD Protocol module can be configured to receive only
messages of interest. The module contains 12 acceptance filters. Each acceptance filter contains a filter object and a
mask object. The user application configures the specific filter to receive a message with a given identifier by setting
the filter object and mask object to match the identifier of the message to be received.
38.7.1
Filter Configuration
The filters are controlled by the CxFLTCONy registers. The filters must be disabled by clearing the FLTEN bit before
changing the filter or mask object; the module need not be in Configuration mode. After the filter object is updated,
the Buffer Pointer, FnBP, has to be initialized and the filter can be enabled by setting the FLTEN bit. The FnBP points
to the FIFO where the matching receive message needs to be stored.
38.7.2
Filtering a Received Message
The CAN FD Protocol module starts acceptance filtering after the arbitration field and when the first three data bytes
of a message are received. Figure 38-14 describes the flow of message filtering.
The module loops through all the filters, starting with Filter 0, which is the highest priority filter. The message in the
Receive Message Assembly Buffer (RXMAB) is compared to the filter and mask. In case the message matches the
filter and it is received without any errors, the message will be stored into the RX FIFO pointed to by the FnBP.
Acceptance filtering is stopped and the associated RFIF bit is set.
In case an RTR is received, the TXREQ bit of the TX FIFO pointed to by FnBP will be set. Filtering will continue with
the next filter and RXOVIF will be set only when one of the following happens:
• A filter matches, but the RX FIFO is full.
• When multiple filters match the same message and all matching RX FIFOs are full, only the RXOVIF of the FIFO
pointed to by the highest priority filter will be set.
• The RXOVIF bit will be set if the TX FIFO is empty during an RTR (TXEN = 1, RTREN = 1).
If none of the filters match, the received message will be discarded.
Note: If the module receives a message that matches a filter, but the corresponding FIFO is a TX FIFO (TXEN = 1,
RTREN = 0), the module will discard the received message.
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Figure 38-14. Message Filtering Flow
Arbitration Done and
Required Data Bytes Received
Yes and RTR
FIFO Not Empty and
TXEN = 1 and RTREN = 1?
Index = F0BP
Match Filter Object 0
No
No
FIFO Not Full?
Index = F0BP
No
Yes
Yes and RTR
Yes and Not RTR
Yes
Match Filter Object 1
FIFO Not Empty and
TXEN = 1 and RTREN = 1?
Index = F1BP
No
Yes
Yes and Not RTR
FIFO Not Full?
Index = F1BP
No
Yes
No
Match Filter Object 2-12
Do the Same
Yes and RTR
Yes
FIFO Not Empty and
TXEN = 1 and RTREN = 1?
Index = F12BP
Set TXREQ[Index]
Match Filter Object 12
No
Yes and Not RTR
No
FIFO Not Full?
Index = F12BP
No
Yes
Discard Message
Accept Message:
Receive Rest of Message
Store in FIFO [Index]
Done
38.7.2.1 Filtering Standard or Extended Frames
The Filter Match flowchart illustrates the flow of matching a single filter object to the received message in the
RXMAB.
The filter object can be configured to accept either standard, extended or both frames. If MIDE is clear, both standard
and extended frames will be accepted.
If the filter needs to only accept standard frames, then MIDE must be set and EXIDE must be cleared. If the filter
needs to only accept extended frames, then both MIDE and EXIDE must be set.
38.7.2.2 Mask Bits
The mask object is used to ignore selected bits of the received identifier. The masked bits (mask bits with a value of
‘0’) of the RXMAB will not be compared with the bits in the filter object. For example, to receive all messages with
Identifiers 0, 1, 2 and 3, it is required to mask the lower two bits of the identifier by clearing the corresponding bits of
the mask object.
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Figure 38-15. Filter Match
Start Matching
CxMASKy.MIDE Set?
Yes
No
Check IDE:
CxFLTOBJy.EXIDE == RXMAB.IDE?
Yes
Yes
Base Format:
CxFLTOBJy.SID == RXMAB.SID,
Don t Care if CxMASKy.MSID[i] = 0
No Match
No
No Match
No
No Match
No
RXMAB.IDE == 0?
No
No
Extended Format:
CxFLTOBJy.SID == RXMAB.SID,
Don t Care if CxMASKy.MSID[i] = 0
NO Match
Yes
Yes
SID11:
CxTDCH.SID11EN and
CxMASKy.MSID11
CxFLTOBJy.EID == RXMAB.EID,
Don t Care if CxMASKy.MEID[i] = 0
Yes
Yes
No
Yes
Data Bytes:
CxCON.DNCNTx > 0 ?
Check SID11:
CxFLTOBJy.SID11 == RXMAB.SID11?
No
No
No Match
Match
Yes
Calculate Number of Bits to Compare:
N = DNCNTx
Calculate Index:
M = 18-N
Assemble Receive Data Bytes:
RXDB = {RXMAB.DB0, RXMAB.DB1, RXMAB.DB2[7:6]}
No
No Match
Compare:
CxFLTOBJy.EID[0:N] == RXDB[17 : M] ?
Don t Care if CxMASKy.MEID[i] = 0
Yes
Match
38.7.2.3 Filtering on Data Bytes
When the filter is configured to receive standard frames, the EID part of the filter and mask object can be selected
to filter the data bytes. The DNCNT[4:0] bits in the C1CONL register are used to select how many bits in the data
bytes are compared. Table 38-9 explains how many data bits are compared, and which filter bits and data bits are
compared.
If DNCNTx is:
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•
‘0’, then data byte filtering is disabled.
•
Non-zero, the filtering will commence on as many data bits as specified in DNCNTx. A filter hit will require
matching of the SIDx bits and a match of n data bits with the filter’s EID[0:17] bits. Data Byte 0[7] is always
compared to EID[0], Data Byte 0[6] to EID[1], Data Byte 2[6] to EID[17].
Greater than 18, indicating that the user-selected number of bits is greater than the total number of EIDx bits.
The filter comparison will terminate with the 18th bit of the data.
Greater than 16, and the received message has DLC = 2, indicating a payload of two data bytes. The filter
comparison will terminate with the 16th bit of the data.
Greater than 8, and the received message has DLC = 1, indicating a payload of one data byte. The filter
comparison will terminate with the 8th bit of the data.
Greater than 0, and the received message has DLC = 0, indicating no data payload. The filter comparison will
terminate with the identifier.
•
•
•
•
38.7.2.4 12-Bit Standard ID
Setting SID11EN (CxTDC[8]) allows the use of RRS as bit 12 of the SIDx (LSB). 12-Bit SID mode is only available for
CAN FD base frames. The filter is extended by SID11 and MSID11. Data bytes can also be filtered in this mode.
Table 38-9. Data Byte Filter Configuration
DNCNT[4:0]
Received Message Data Bits to be
Compared Byte [bits]
EIDx Bits Used for Acceptance
Filter
00000
No Comparison
No Comparison
00001
Data Byte 0[7]
EID[0]
00010
Data byte 0[7:6]
EID[0:1]
00011
Data byte 0[7:5]
EID[0:2]
00100
Data byte 0[7:4]
EID[0:3]
00101
Data byte 0[7:3]
EID[0:4]
00110
Data byte 0[7:2]
EID[0:5]
00111
Data byte 0[7:1]
EID[0:6]
01000
Data byte 0[7:0]
EID[0:7]
01001
Data byte 0[7:0] and Data Byte 1[7]
EID[0:8]
01010
Data byte 0[7:0] and Data Byte 1[7:6] EID[0:9]
01011
Data byte 0[7:0] and Data Byte 1[7:5] EID[0:10]
01100
Data byte 0[7:0] and Data Byte 1[7:4] EID[0:11]
01101
Data byte 0[7:0] and Data Byte 1[7:3] EID[0:12]
01110
Data byte 0[7:0] and Data Byte 1[7:2] EID[0:13]
01111
Data byte 0[7:0] and Data Byte 1[7:1] EID[0:14]
10000
Data byte 0[7:0] and Data Byte 1[7:0] EID[0:15]
10001
Byte 0[7:0] and Byte 1[7:0] and Byte
2[7]
EID[0:16]
10010 to 11111
Byte 0[7:0] and Byte 1[7:0] and Byte
2[7:6]
EID[0:17]
Figure 38-16 illustrates how the first 18 data bits of the received message data payload are compared with the
corresponding EIDx bits of the message acceptance filter (EID[17:0] bits in the C1FLTOBJxH/L registers). The IDE bit
of the received message must be ‘0’.
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™
Figure 38-16. CAN Operation with DeviceNet Filtering
STANDARD MESSAGE DATA FRAME
S
O
F
IDENTIFIER
11 Bits
MESSAGE SID[10:0]
SID10 SID9
SID0
DATA BYTE 0
Data Byte 0
76543210
DATA BYTE 1
Data Byte 1
76543210
EOF
IFS
7 bits 3 bits
DATA BYTE 2
Data Byte 2
76543210
Accept/Reject Message
SID10 SID9
SID0
MESSAGE ACCEPTANCE
FILTER SID[10:0]
Note:
38.8
EID0 EID1
The DeviceNet
EID7 EID8 EID9
EID15
EID16
EID17
MESSAGE ACCEPTANCE FILTER EID[0:17]
filtering configuration shown for the EIDx bits is DNCNT[4:0] = 10010.
Message Reception
The application has to configure the RX FIFO before it can be used for reception (see 38.3.4.4 Receive FIFO
Configuration). In addition, the application has to configure and enable at least one filter (see 38.7.1 Filter
Configuration).
The CAN FD Protocol Module continuously monitors the CAN bus. Messages that match a filter are stored in the RX
FIFO pointed to by the filter (see 38.7.2 Filtering a Received Message). The message data are stored in the receive
message objects.
38.8.1
Receive Message Object
Table 38-10 specifies the receive message object used by the RX FIFOs. The receive objects contain the message
ID, control bits, payload and timestamp.
• SID: Standard Identifier (ID) or Base ID.
• EID: Extended Identifier.
• DLC: Data Length Code; specifies the number of data bytes in the frame (see 38.4.1.1 DLC Encoding).
• IDE: Identifier Extension; IDE = 0 means a Base Identifier frame is received. IDE = 1 means an Extended
Identifier frame is received.
• RTR: Remote Transmit Request; this bit is only specified in CAN 2.0 frames. If this bit is set, the module is
requested to respond with a frame transmission.
• FDF: FD Frame; if this bit is set, a CAN FD frame is received; otherwise, a CAN 2.0 frame is received.
• BRS: Bit Rate Switch; the data phase of a CAN FD frame is received using DBR if this bit is set. If the bit is
clear, the whole frame is received using NBR.
• ESI: Error Status Indicator; the ESI bit reflects the error status of the transmitting node. A recessive ESI bit in a
CAN FD frame indicates that the transmitting node is error passive; a dominant bit shows that the transmitting
node is error active.
• FILHIT: Indicates the number of the filter that matched the received message.
• RXMSGTS: Timestamp of the received message; timestamping can be enabled for each RX FIFO individually
using RXTSEN (C1FIFOCONxL[5]). The receive message object will not contain RXMSGTS if timestamping is
disabled.
• Receive Buffer Data: Contains the payload of the message. The maximum payload is configured by the
PLSIZEx bits (CxFIFOCON[31:29]).
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38.8.1.1 Reading a Receive Message Object
Before reading a receive message object, the application must ensure that the RX FIFO is not empty by reading the
CxFIFOSTAy register. The RX FIFO is not empty if TFNRFNIF is set.
The RX FIFO user address (CxFIFOUAy) points to the RAM of the next receive message object to read. R0 of the
receive message object is read first, followed by R1, R2 and so on.
After the receive message object is read from RAM, the RX FIFO needs to be incremented by setting the UINC
bit (CxFIFOCONy[8]). This will make the CAN FD Protocol module increment to the tail of the FIFO and update
CxFIFOUAy.
Now the application can read the next message from the RX FIFO.
Table 38-10. Receive Message Object
Byte
Bit 7
Bit 6
Bit 5
Bit 4
0
Bit 3
Bit 2
Bit 1
Bit 0
SID[7:0]
1
EID[4:0]
2
SID[10:8]
EID[12:5]
3
-
-
SID11
4
EID[17:13]
FILHIT[4:0]
5
FDF
BRS
-
RTR
IDE
-
ESI
DLC[3:0]
6
-
-
-
-
-
-
-
-
7
-
-
-
-
-
-
-
-
8
Receive Data Byte 0
9
Receive Data Byte 1
10
Receive Data Byte 2
11
Receive Data Byte 3
12
Receive Data Byte 4
13
Receive Data Byte 5
14
Receive Data Byte 6
15
Receive Data Byte 7
………………………………………………………………………………………………………………………………………
…………
m-3
Receive Data Byte n-3
m-2
Receive Data Byte n-2
m-1
Receive Data Byte n-1
m
Receive Data Byte n
bit 15-11 EID[4:0]: Extended Identifier bits
bit 10-0 SID[10:0]: Standard Identifier bits
bit 15-14 Unimplemented: Read as ‘x’
bit 13 SID11: In FD mode, the Standard ID can be extended to 12 bits using r1 bit
bit 12-0 EID[17:5]: Extended Identifier bits
bit 10-9 Unimplemented: Read as ‘x’
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bit 8 ESI: Error Status Indicator bit - In CAN-to-CAN Gateway mode (ESIGM = 1), the transmitted ESI flag is a
“logical OR” of ESI and the error passive state of the CAN controller.
In Normal mode, ESI indicates the error status:
1 = Transmitting node is error passive
0 = Transmitting node is error active
bit 7 FDF: FD Frame bit - distinguishes between CAN and CAN FD formats
bit 6 BRS: Bit Rate Switch bit - selects if Data Bit Rate is switched
bit 5 RTR: Remote Transmission Request bit (not used in CAN FD)
bit 4 IDE: Identifier Extension bit - distinguishes between base and extended format.
bit 3-0 DLC[3:0]: Data Length Code bits
bit 15:0 Unimplemented: Read as ‘x’
bit 15:0 RXMSGTS[15:0]: Receive Message Timestamp bits
bit 15:0 RXMSGTS[31:16]: Receive Message Timestamp bits
Notes:
1. Receive Message Object: Data Bytes 0-n; payload size is configured individually with the PLSIZE[2:0] bits.
2. R2 (RXMSGTSx) only exists in objects where RXTSEN is set.
38.8.2
Receive State Diagram
Figure 38-17 illustrates how messages are received. It illustrates how the most important receive flags are set and
cleared.
• The CAN FD Protocol module remains Idle until a SOF is detected.
• After a SOF is detected, the module will receive the arbitration and control fields.
• Based on the DNCNTx bits and the received DLC, acceptance filtering will start. See Figure 4-14 for more
details.
• If none of the filters match, the message will still be received, but it will not be stored.
• If a filter matches, the device checks whether the receive object the filter points to is full.
• If the receive object is not full, the rest of the data bytes are received and stored to the receive object.
• If the receive object is full, the RXOVIF bit will be set.
• If a complete message is received, the message will be stored, a timestamp will be attached and the receive
flags will be set; the FIFO status flags will be updated and the FIFO head will be incremented.
• In case an error is detected during the reception of a message, an error frame will be transmitted and the
appropriate error flags will be set.
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Figure 38-17. Receive State Diagram
Idle
Store Message to
Object
Set RXIF
Transmit Error
Frame
Set Error Flags
Error
Receive Rest of
Message
Receive
Arbitration and
CTRL Field
c
DNCNTx > 0 and DLC > 0?
c
Receive
Data Bytes 0-3
Filter Match?
Receive Rest of
Message
Receive Remaining
Data Bytes
and Store them
38.8.3
c
Set RXOVIF
Object Full?
RXIF Set?
Yes
Resetting RX FIFO
A receive FIFO can be reset by:
• Setting FRESET (CxFIFOCONy[10]) or
• Placing the module in Configuration mode (OPMOD[2:0] = 100).
Resetting the FIFO will reset the head and tail pointers, and the CxFIFOSTAy register. The settings in the
CxFIFOCONy registers will not change.
Before resetting an RX FIFO using FRESET, ensure that no enabled filter is pointing to the FIFO.
38.8.4
Mismatch of DLC and Payload Size During Reception
The PLSIZEx bits reserve a certain number of bytes in the receive message object. The module handles mismatches
between DLC and payload size as follows:
• If the number of bytes specified by the DLC is smaller than the number of bytes specified by the PLSIZEx bits,
the received message bytes will be stored in the message object, without any padding.
• If the number of bytes specified by the DLC is bigger than the number of bytes specified by the PLSIZEx bits,
the data bytes that fit in the receive message object are stored and the other data bytes that do not fit are
discarded. The module ensures that the next message object in RAM does not get overwritten. The module will
store the message in the receive object and the RX FIFO status flags will be updated. In addition, the IVMIF
(CxINT[15]) and DLCMM flags (CxBDIAG1[31]) will be set.
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38.9
FIFO Behavior
This section explains the FIFO behavior when TEF and TXQ are enabled. FIFO 1 is configured as a TX FIFO and
FIFO 2 as an RX FIFO. The remaining FIFOs are not configured.
Notes:
1. The start addresses are calculated based on the number of objects in the FIFO and the PLSIZEx bits.
2. The start addresses of the FIFOs given in Table 38-11 are calculated when TEF starts at 0x1400.
Table 38-11. Example FIFO Configuration
38.9.1
FIFO
Objects in
FIFO
Payload per
Object
Timestamp
Bytes in
Object
Bytes in FIFO Start Address
TEF
12
N/A
Yes
12
144
0x1400
TXQ
8
32
N/A
40
320
0x1490
FIFO 1
5
64
N/A
72
360
0x15D0
FIFO 2
16
64
Yes
76
1216
0x1738
FIFO 3
N/A
-
-
-
-
0x1BF8
FIFO Status Flags
FIFO 1 through FIFO 3 can be configured as transmit or receive FIFOs. The same status flags in CxFIFOSTAy are
used for transmit and receive FIFOs. The status flags behave differently based on the selected configuration.
38.9.1.1 TX FIFO Status Flags
There are three transmit status flags:
• TFEIF (TFERFFIF): Transmit FIFO Empty Interrupt Flag; set when the FIFO is empty.
• TFHIF (TFHRFHIF): Transmit FIFO Half Empty Interrupt Flag; set when FIFO is less than half full.
• TFNIF (TFNRFNIF): Transmit FIFO Not Full Interrupt Flag; set when FIFO is not full.
The status flags of a transmit FIFO are set when there is space to load a new message object into the FIFO. Before
the first message object is loaded (after the FIFO is reset), all status flags are set. When the FIFO is fully loaded, all
flags are cleared.
38.9.1.2 RX FIFO Status Flags
There are three receive status flags:
• RFFIF (TFERFFIF): Receive FIFO Full Interrupt Flag; set when the FIFO is full.
• RFHIF (TFHRFHIF): Receive FIFO Half Full Interrupt Flag; set when the FIFO is at least half full.
• RFNIF (TFNRFNIF): Receive FIFO Not Empty Interrupt Flag; set when there is at least one message in the
FIFO.
The status flags of the receive FIFO are set when there are received messages in the FIFO. Before the first message
is received (after the FIFO is reset), all status flags are cleared. When the FIFO is full, all flags are set.
38.9.1.3 TXQ Status Flags
There are two TXQ status flags:
• TXQEIF: TXQ Empty Interrupt Flag; set when the TXQ is empty.
• TXQNIF: TXQ Not Full Interrupt Flag; set when TXQ is not full.
The status flags of the TXQ are set when there is space to load a new message object into the TXQ. Before the first
message object is loaded (after the TXQ is reset), all status flags are set. When the TXQ is fully loaded, all flags are
cleared.
38.9.1.4 TEF Status Flags
There are four TEF status flags:
• TEFFIF: TEF Full Interrupt Flag; set when the TEF is full.
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•
•
•
TEFHIF: TEF Half Full Interrupt Flag; set when the TEF is at least half full.
TEFNEIF: TEF Not Empty Interrupt Flag; set when there is at least one message in the TEF.
TEFOVIF: TEF Overrun Interrupt Flag; set when an overflow has occurred.
The status flags of the TEF are set when there are transmitted messages in the FIFO. Before the first message is
stored (after the TEF is reset), all status flags are cleared. When the TEF is full, all flags are set.
38.9.2
Transmit FIFO Behavior
FIFO 1 is configured as a TX FIFO. CxFIFOCON1 is used to control the FIFO. CxFIFOSTA1 contains the status flags
and the FIFO Index bits (FIFOCI[4:0]). CxFIFOUA1 contains the user address of the next transmit message object to
be loaded.
Figure Figure 38-18 through Figure 38-23 illustrate how the status flags, user address and FIFO index are updated
for FIFO 1.
Figure 38-18 shows the status of FIFO 1 after Reset. Message objects, MO0 to MO4, are empty. All status flags are
set. The user address and the FIFO index point to MO0.
Figure 38-18. FIFO 1 - Initial State
CxFIFOUA1 = 0x1D0
MO0
CxFIFOSTA1:
FIFOCI = 0
TFEIF = 1
TFHIF = 1
TFNIF = 1
MO1
CxFIFOCON1:
TXREQ = 0
MO4
MO2
MO3
Figure 38-19 illustrates the status of FIFO 1 after the first message (MSG0) is loaded. MO0 now contains MSG0. The
user application sets the UINC bit (CxFIFOCON1[8]), which causes the FIFO head to advance. The user address
now points to MO1. TFEIF is cleared since the FIFO is no longer empty. The user application now sets TXREQ to
request the transmission of MSG0.
Figure 38-19. FIFO 1 - First Message Loaded
CxFIFOUA1 = 0x218
MO0/MSG0
C1FIFOSTA1:
FIFOCI = 0
TFEIF = 0
TFHIF = 1
TFNIF = 1
MO1
CxFIFOCON1:
TXREQ = 1
MO4
MO2
MO3
Figure 38-20 illustrates the status of FIFO 1 after MSG0 is transmitted. The FIFO is empty again. TFEIF is set and
TXREQ is cleared. FIFOCIx bits now point to MO1 with user address 0x218.
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Figure 38-20. FIFO 1 - First Message Transmitted
CxFIFOUA1 = 0x218
MO0
CxFIFOSTA1:
FIFOCI = 1
TFEIF = 1
TFHIF = 1
TFNIF = 1
MO1
CxFIFOCON1:
TXREQ = 0
MO4
MO2
MO3
Figure 38-21 illustrates the status of FIFO 1 after three more messages are loaded: MSG1-MSG3. The user address
now points to MO4. TFHIF is cleared because the FIFO is now less than half empty.
Figure 38-21. FIFO 1 - Three More Messages Loaded
CxFIFOUA1 = 0x2F0
MO0
CxFIFOSTA1:
FIFOCI = 1
TFEIF = 0
TFHIF = 0
TFNIF = 1
MO1/MSG1
CxFIFOCON1:
TXREQ = 0
MO4
MO2/MSG2
MO3/MSG3
Figure 38-22 illustrates the status of FIFO 1 after two more messages are loaded: MSG4 and MSG5. CxFIFOUA1
now points to MO1. All status flags are now cleared because the FIFO is full. The user address and the FIFO index
now point to MO1. The user application now sets TXREQ to request the transmission of MSG1-MSG5.
Figure 38-22. FIFO 1- FIFO Fully Loaded
CxFIFOUA1 = 0x218
MO0/MSG5
CxFIFOSTA1:
FIFOCI = 1
TFEIF = 0
TFHIF = 0
TFNIF = 0
MO1/MSG1
CxFIFOCON1:
TXREQ = 1
MO4/MSG4
MO2/MSG2
MO3/MSG3
Figure 38-23 illustrates the status of FIFO 1 after MSG1-MSG5 are transmitted. The FIFO is empty again. All status
flags are set and TXREQ is cleared. The user address and the FIFO index point to MO1 again.
Figure 38-23. FIFO 1 - FIFO Fully Transmitted
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CxFIFOUA1 = 0x218
MO0
CxFIFOSTA1:
FIFOCI = 1
TFEIF = 1
TFHIF = 1
TFNIF = 1
MO1
CxFIFOCON1:
TXREQ = 0
MO4
MO2
MO3
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38.9.3
Receive FIFO Behavior
FIFO 2 is configured as an RX FIFO. CxFIFOCON2 is used to control the FIFO. CxFIFOSTA2 contains the status
flags and the FIFO index (FIFOCIx). CxFIFOUA2 contains the user address of the next message object to read.
Figure 38-24 through Figure 38-31 illustrate how the status flags, user address and FIFO index are updated.
Figure 38-24 shows the status of FIFO 2 after the Reset. Message objects, MO0 to MO15, are empty. All status flags
are cleared. The user address and the FIFO index point to MO0.
Figure 38-24. FIFO 2 - Initial State
CxFIFOUA2 = 0x338
MO0
CxFIFOSTA2:
FIFOCI = 0
RFFIF = 0
RFHIF = 0
RFNIF = 0
RXOVIF = 0
MO1
MO2
MO15
Figure 38-25 illustrates the status of FIFO 2 after the first message (MSG0) is received. MO0 now contains MSG0.
The FIFO index now points to MO1. RFNIF is set since the FIFO is not empty anymore.
Figure 38-25. FIFO 2 - First Message Received
CxFIFOUA2 = 0x338
CxFIFOSTA2:
FIFOCI = 1
RFFIF = 0
RFHIF = 0
RFNIF = 1
RXOVIF = 0
MO0/MSG0
MO1
MO2
MO15
Figure 38-26 illustrates the status of FIFO 2 after MSG0 is read. The user application reads the message from
RAM and sets the UINC bit (CxFIFOCON2[8]). The user address increments and points to MO1. The FIFO index is
unchanged. The FIFO is empty again. All flags are cleared.
Figure 38-26. FIFO 2 - First Message Read
CxFIFOUA2 = 0x384
MO0
CxFIFOSTA2:
FIFOCI = 1
RFFIF = 0
RFHIF = 0
RFNIF = 0
RXOVIF = 0
MO1
MO2
MO15
Figure 38-27 illustrates the status of FIFO 2 after eight more messages are received: MSG1-MSG8. The user
address still points to MO1. RFNIF and RFHIF are set because the FIFO is now half full. The FIFO index points to
MO9.
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Figure 38-27. FIFO 2 - Half Full
CxFIFOUA2 = 0x384
CxFIFOSTA2:
FIFOCI = 9
RFFIF = 0
RFHIF = 1
RFNIF = 1
RXOVIF = 0
MO0
MO1/MSG1
MO2/MSG2
MO8/MSG8
MO9
MO10
MO15
Figure 38-28 illustrates the status of FIFO 2 after ten more messages are received: MSG5-MSG15. The user address
still points to MO1. The FIFO index points to MO0. RFNIF and RFHIF are set.
Figure 38-28. FIFO 2 - FIFO Almost Full
CxFIFOUA2 = 0x384
CxFIFOSTA2:
FIFOCI = 0
RFFIF = 0
RFHIF = 1
RFNIF = 1
RXOVIF = 0
MO0
MO1/MSG1
MO2/MSG2
MO15/MSG15
Figure 38-29 illustrates the status of FIFO 2 after one more message is received: MSG16. All status flags are set
because the FIFO is full. The user address and the FIFO index point to MO1.
Figure 38-29. FIFO 2 - FIFO Full
CxFIFOUA2 = 0x384
MO0/MSG16
CxFIFOSTA2:
FIFOCI = 1
RFFIF = 1
RFHIF = 1
RFNIF = 1
RXOVIF = 0
MO1/MSG1
MO2/MSG2
MO15/MSG15
Figure 38-30 illustrates the status of FIFO 2 after one more message is received. Since FIFO 2 is already full, an
overflow occurs. The message is discarded and RXOVIF is set. The user address and FIFO index has not changed.
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Figure 38-30. FIFO 2 - FIFO Overflow
CxFIFOUA2 = 0x384
MO0/MSG16
CxFIFOSTA2:
FIFOCI = 1
RFFIF = 1
RFHIF = 1
RFNIF = 1
RXOVIF = 1
MO1/MSG1
MO2/MSG2
MO15/MSG15
Figure 38-31 illustrates the status of FIFO 2 after the application cleared RXOVIF and read two more messages.
RFFIF is clear because the FIFO is not full anymore. The user address points to MO3. The FIFO index has not
changed.
Figure 38-31. FIFO 2 - Two More Messages Read
CxFIFOUA2 = 0x41C
CxFIFOSTA2:
FIFOCI = 1
RFFIF = 0
RFHIF = 1
RFNIF = 1
RXOVIF = 0
MO0/MSG16
MO1
MO2
MO3/MSG3
MO4/MSG4
MO15/MSG15
38.9.4
Transmit Queue Behavior
C1TXQCON is used to control the TXQ. C1TXQSTA contains the status flags and the TXQ index (TXQCIx).
C1TXQUA contains the user address of the next transmit message object to be loaded.
The TXQCI[4:0] bits are used by the CAN FD Protocol module to calculate the next message to transmit. TXQCIx bits
are not incremented linearly. They are recalculated every time a message gets transmitted or TXREQ gets set.
Figure 38-32 through Figure 38-37 illustrate how the status flags and user address are updated. There is no need for
the user application to use TXQCIx; therefore, it is not shown in the figures.
Figure 38-32 shows the status of the TXQ after Reset. Message objects, MO0 to MO7, are empty. All status flags are
set. The user address points to MO0.
Figure 38-32. TXQ - Initial State
CxTXQUA = 0x090
MO0
CxTXQSTA:
TXQEIF = 1
TXQNIF = 1
MO1
CxTXQCON:
TXREQ = 0
MO2
MO7
Figure 38-33 illustrates the status of the TXQ after the first message (MSG0) is loaded. MO0 now contains MSG0.
The user application sets the UINC bit, which causes the FIFO head to advance. The user address now points to
MO1. TXQEIF is cleared, since the queue is not empty anymore. The user application now sets TXREQ to request
the transmission of MSG0.
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Figure 38-33. TXQ - First Message Loaded
CxTXQUA = 0x0B8
CxTXQSTA:
TXQEIF = 0
TXQNIF = 1
MO0/MSG0
MO1
MO2
CxTXQCON:
TXREQ = 1
MO7
Figure 38-34 illustrates the status of the TXQ after MSG0 is transmitted. The TXQ is empty again. TXQEIF is set and
TXREQ is cleared. The user address still points to MO1 because UINC is not set.
Figure 38-34. TXQ - First Message Transmitted
CxTXQUA = 0x0B8
MO0
CxTXQSTA:
TXQEIF = 1
TXQNIF = 1
MO1
MO2
CxTXQCON:
TXREQ = 0
MO7
Figure 38-35 illustrates the status of the TXQ after MSG1 is loaded and UINC is set. The user address now points to
the next free message object: MO0.
Figure 38-35. TXQ - Next Message Loaded
CxTXQUA = 0x090
CxTXQSTA:
TXQEIF = 0
TXQNIF = 1
MO0
MO1/MSG1
MO2
CxTXQCONL:
TXREQ = 0
MO7
Figure 38-36 illustrates the status of the TXQ after six more messages are loaded: MSG2-MSG7. The user address
now points to the last free message object: MO7.
Figure 38-36. TXQ - Next Six Messages Loaded
CxTXQUA = 0x1A8
MO0/MSG2
CxTXQSTA:
TXQEIF = 0
TXQNIF = 1
MO1/MSG1
CxTXQCON:
TXREQ = 0
MO2/MSG3
MO3/MSG4
MO4/MSG5
MO5/MSG6
MO6/MSG7
MO7
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Figure 38-37 illustrates the status of the TXQ after MSG8 is loaded and UINC is set. The TXQ is now full, all flags
are cleared. The user address now points to MO0. The user application now sets TXREQ. The messages will be
transmitted based on the priority of their IDs.
Figure 38-37. TXQ - Full
CxTXQUA = 0x090
MO0/MSG2
CxTXQSTA:
TXQEIF = 0
TXQNIF = 0
MO1/MSG1
MO2/MSG3
MO3/MSG4
CxTXQCON:
TXREQ = 1
MO4/MSG5
MO5/MSG6
MO6/MSG7
MO7/MSG8
38.9.5
Transmit Event FIFO Behavior
C1TEFCONL and C1TEFCONH are used to control the TEF. C1TEFSTA contains the status flags. C1TEFUAL and
C1TEFUAH contain the user address of the next message object to read.
The actual RAM address is calculated using Equation 38-21.
Figure 38-38 through Figure 38-45 illustrate how the status flags and user address are updated. The TEF stores
transmitted messages; therefore, the flags behave similarly to an RX FIFO.
Figure 38-38 shows the status of the TEF after Reset. Message objects, MO0 to MO11, are empty. All status flags
are cleared. The user address points to MO0.
Figure 38-38. TEF - Initial State
CxTEFUA = 0x000
MO0
CxTEFSTA:
TEFFIF = 0
TEFHIF = 0
TEFNEIF = 0
TEFOVIF = 0
MO1
MO2
MO11
Figure Figure 38-39 shows the status of the TEF after the first transmit message is stored. MO0 contains ID0, the ID
of MSG0. TEFNEIF is set since the TEF is not empty. The user address points to MO0.
Figure 38-39. TEF - First Transmit Message is Stored
CxTEFUA = 0x000
CxTEFSTA:
TEFFIF = 0
TEFHIF = 0
TEFNEIF = 1
TEFOVIF = 0
MO0/ID0
MO1
MO2
MO11
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Figure 38-40 illustrates the status of the TEF after ID0 is read. The user application reads the ID from RAM and sets
the UINC bit (C1TEFCONL[8]). The user address increments and points to MO1. The TEF is empty again. All flags
are cleared.
Figure 38-40. TEF - First ID Read
CxTEFUA = 0x00C
MO0
CxTEFSTA:
TEFFIF = 0
TEFHIF = 0
TEFNEIF = 0
TEFOVIF = 0
MO1
MO2
MO11
Figure 38-41 illustrates the status of the TEF after six more messages are transmitted: MSG1-MSG6. The user
address points to MO1. TEFNEIF and TEFHIF are set because the TEF is now half full.
Figure 38-41. TEF - Half Full
CxTEFUA = 0x00C
CxTEFSTA:
TEFFIF = 0
TEFHIF = 1
TEFNEIF = 1
TEFOVIF = 0
MO0
MO1/ID1
MO2/ID2
MO6/ID6
MO7
MO8
MO11
Figure 38-42 illustrates the status of the TEF after five more messages are transmitted: MSG7-MSG11. The user
address still points to MO1. TEFNEIF and TEFHIF are set.
Figure 38-42. TEF- Almost Full
CxTEFUA = 0x00C
CxTEFSTA:
TEFFIF = 0
TEFHIF = 1
TEFNEIF = 1
TEFOVIF = 0
MO0
MO1/ID1
MO2/ID2
MO11/ID11
Figure 38-43 illustrates the status of the TEF after one more message is transmitted: MSG12. All status flags are set
because the TEF is full. The user address points to MO1.
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Figure 38-43. TEF - Full
CxTEFUA = 0x00C
MO0/ID12
CxTEFSTA:
TEFFIF = 1
TEFHIF = 1
TEFNEIF = 1
TEFOVIF = 0
MO1/ID1
MO2/ID2
MO11/ID11
Figure 38-44 illustrates the status of the TEF after one more message is transmitted. Since the TEF is already full, an
overflow occurs. The ID is discarded and TEFOVIF is set. The user address remains unchanged.
Figure 38-44. TEF - Overflow
CxTEFUA = 0x00C
MO0/ID12
CxTEFSTA:
TEFFIF = 1
TEFHIF = 1
TEFNEIF = 1
TEFOVIF = 1
MO1/ID1
MO2/ID2
MO11/ID11
Figure 38-45 illustrates the status of the TEF after the application cleared TEFOVIF and read one more message.
TEFFIF is clear because the TEF is not full anymore. The user address points to MO2.
Figure 38-45. TEF - One More ID Read
CxTEFUA = 0x018
CxTEFSTA:
TEFFIF = 0
TEFHIF = 1
TEFNEIF = 1
TEFOVIF = 0
MO0/ID12
MO1
MO2/ID2
MO3/ID3
MO11/ID11
38.10
Timestamping
The CAN FD Protocol module contains a Time Base Counter (TBC). The TBC is a 32-bit free-running counter that
increments on multiples of SYSCLK and rolls over to zero when:
• TBCPRE[9:0] bits (CxTSCON[9:0]) are used to configure the prescaler for the TBC.
• Setting TBCEN (CxTSCON[16]) enables the TBC.
• Clearing TBCEN disables, stops and resets the TBC.
• The TBC has to be disabled before writing to C1TBC by clearing TBCEN.
• TEFTSEN (CxTEFCON[5]) has to be set to timestamp messages in the TEF.
• RXTSEN (CxFIFOCONy[5]) has to be set to timestamp messages in the individual RX FIFO.
• The application can read C1TBC at any time. Similar to any multibyte counter, the application has to consider
that the counter increments and might roll over while reading different bytes of the counter.
All timestamps are 32 bits, allowing timestamps to be used for system time synchronization with high resolution.
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A rollover of the TBC will generate an interrupt if TBCIE is set.
Messages can be timestamped either at the beginning of a frame or at the end, depending on the TSEOF bit
(C1TSCON[17]). When TSEOF = 0, TSRES (C1TSCON[18]) specifies if FD frames are timestamped at SOF or the
“reserved bit”. Table 38-12 specifies the reference points when the timestamping occurs. At the reference point, the
value of the TBC (C1TBC) is captured and stored into the message object:
• Receive Message Object: The TBC value is stored in the RXMSGTSx bits (see Table 38-10).
• TEF Object: The TBC value is stored in the TXMSGTSx bits (see Table 38-8).
Table 38-12. Reference Point
38.11
Frame
CAN 2.0
CAN FD
Start of TX
Sample point of SOF
Sample point of SOF or the bit after
FDF
Start of RX
Sample point of SOF
Sample point of SOF or the bit after
FDF
Valid TX
No error till end of EOF
No error till end of EOF
Valid RX
No error till the last, but one bit of
EOF
No error till the last, but one bit of
EOF
Interrupts
Interrupts can be classified into multiple layers. Lower layer interrupts propagate to higher layers by multiplexing them
into single interrupts. Figure 38-46 illustrates the layers of interrupts.
• FIFO Individual Interrupts
• FIFO Combined Interrupts
• Main Interrupts
These interrupts are then funneled into three separate module interrupts:
• Receive Interrupt
• Transmit Interrupt
• Information Interrupt
All module interrupts are persistent, meaning the condition that caused the interrupt must be cleared within the
module for the interrupt request to be removed.
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Figure 38-46. Interrupt Multiplexing
FIFO Combined
Interrupts
CxTXQCON, CxTXQSTA FIFO Individual
CxFIFOCONy, CxFIFOSTAy Interrupts
RFFIE
RFFIF
3 FIFOS
RFHIE
RFHIF
3x
RFNIE
RFNIF
CxRXIF
1x
TXQNIE
TXQNIF
TFEIE
TFEIF
3x
CxINT.RXIE
CxINT.RXIF
RX Interrupt
4x
CxINT.TXIE
CxINT.TXIF
TX Interrupt
3x
CxINT.RXOVIE
CxINT.RXOVIF
3x
CxINT.TXATIE
CxINT.TXATIF
CxTXIF.TFIF
3 FIFOS
TFHIE
TFHIF
3x
CxTXIF
TFNIE
TFNIF
1x
3x
TXATIE
TXATIF
3x
TXATIE
TXATIF
Interrupt Pins
1 TXQ
TXQEIE
TXQEIF
RXOVIE
RXOVIF
Main Interrupts
3 FIFOS
1 TXQ
3 FIFOS
CxRXOVIF
CxTXATIF
CxTXATIF
CiTEFCONL
CiTEFSTA
TEFOVIE
TEFOVIF
1 FIFO
TEFFIE
TEFFIF
TEFHIE
TEFHIF
TEFNEIE
TEFNEIF
CxINT.TEFIE
CxINT.TEFIF
CxINT.IVMIE
CxINT.IVMIF
OR
Info Interrupt
CxINT.WAKIE
CxINT.WAKIF
CxINT.CERRIE
CxINT.CERRIF
CxINT.MODIE
CxINT.MODIF
CxINT.TBCIE
CxINT.TBCIF
CxINT.SERRIE
CxINT.SERRIF
38.11.1 FIFO Individual Interrupts
CxFIFOCONy contains the interrupt enable flags and CxFIFOSTAy contains the interrupt flags for the FIFOs. There is
a separate register for each FIFO.
38.11.1.1 Transmit Queue Interrupts
CxTXQCON contains the interrupt enable flags and CxTXQSTA contains the interrupt flags for the TXQ.
The TXQ interrupt occurs when there is a change in the status of the TXQ. There are two interrupt sources:
• TXQ Not Full Interrupt Flag (TXQNIF)
• TXQ Empty Interrupt Flag (TXQEIF)
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Both interrupts can be enabled individually. The interrupts cannot be cleared by the application; they will be cleared
when the condition of the FIFO terminates.
Both interrupt sources are OR’d together and reflected in the TFIF0 flag (CxTXIF[0]).
38.11.1.2 Receive FIFO Interrupts (RFIF)
The receive FIFO interrupts occur when there is a change in the status of the receive FIFO. There are three interrupt
sources:
• Receive FIFO Full Interrupt Flag (RFFIF)
• Receive FIFO Half Full Interrupt Flag (RFHIF)
• Receive FIFO Not Empty Interrupt Flag (RFNIF)
All three interrupts can be enabled individually. The interrupts cannot be cleared by the application; they will be
cleared when the condition of the FIFO terminates.
The three interrupt sources are OR’d together and reflected in the RFIF[31:16] (CxRXIF[31:16]) and RFIF[15:1]
(CxRXIF[15:1]) flags.
38.11.1.3 Transmit FIFO Interrupts (TFIF)
The transmit FIFO interrupts occur when there is a change in the status of the transmit FIFO. There are three
interrupt sources:
• Transmit FIFO Not Full Interrupt Flag (TFNIF)
• Transmit FIFO Half Empty Interrupt Flag (TFHIF)
• Transmit FIFO Empty Interrupt Flag (TFEIF)
All three interrupts can be enabled individually. The interrupts cannot be cleared by the application; they will be
cleared when the condition of the FIFO terminates.
The three interrupt sources are OR’d together and reflected in the C1TXIF[31:1] flags.
38.11.1.4 Receive FIFO Overrun Interrupt (RXOVIF)
When a message is successfully received, but the FIFO is full, the RXOVIF of the individual FIFO is set. The flag
must be cleared by the application.
38.11.1.5 Transmit FIFO Attempt Interrupt (TXATIF)
When the retransmission of a message fails due to an error, and all retransmission attempts are exhausted, the
TXATIF flag is set. The flag must be cleared by the application.
38.11.1.6 Transmit Event FIFO Interrupts (TEFIF)
The TEF interrupts occur when there is a change in the status of the TEF. There are four interrupt sources:
• TEF Full Interrupt Flag (TEFFIF)
• TEF Half Full Interrupt Flag (TEFHIF)
• TEF Not Empty Interrupt Flag (TEFNEIF)
• TEF Overrun Interrupt Flag (TEFOVIF)
The TEF interrupts work similarly to the receive FIFO interrupts. All four interrupts can be enabled individually.
TEFFIF, TEFHIF and TEFNEIF cannot be cleared by the application; they will be cleared when the status of the FIFO
terminates.
The TEFOVIF must be cleared by the application.
The four interrupt sources are OR’d together and reflected in the TEFIF flag (C1INT[4]).
38.11.2 FIFO Combined Interrupts
The following interrupts are individual FIFO interrupts:
• FIFOs/TXQ: RFIFx, TFIFx, RFOVIFx and TFATIFx
They are combined into single Interrupt Status registers:
• CxRXIF, CxTXIF, CxRXOVIF and CxTXATIF
The bits in the status registers are mapped to the FIFOs as follows: Bit 0 to TXQ, Bit 1 to FIFO 1, Bit 2 to FIFO
2, up to Bit 3 to FIFO 3. Since Bit 0 corresponds to the TXQ, Bit 0 of CxRXIF and CxRXOVIF is reserved. Hence,
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by reading one register, the application can check the status of all FIFOs for a particular interrupt (e.g., any RFIFx
pending).
The FIFO interrupts are enabled in CxFIFOCONy.
TXQ interrupts are enabled in CxTXQCON.
Clearing of the FIFO interrupts is explained in FIFO Individual Interrupts.
38.11.3 Main Interrupts
The CxINT register contains all the main interrupts. The following interrupts are a logical ‘OR’ of all combined FIFO
interrupts: RXIF, TXIF, RXOVIF and TXATIF. These flags are read-only and must be cleared in preceding hierarchies.
The TEFIF is generated in the TEF. This flag is read-only and must be cleared in preceding hierarchies.
All interrupts in CxINT can be enabled individually.
38.11.3.1 Invalid Message Interrupt - IVMIF
If a CAN bus error or DLC mismatch is detected during the last message transmitted or received, the IVMIF bit will be
set. The CxBDIAG1 register sets a flag for each error. The flag must be cleared by the application.
The following CAN bus errors will trigger the interrupt in case an error frame is transmitted: CRC, stuff bit, form, bit or
ACK.
The flag will not be set if the ESI of a received message is set.
38.11.3.2 Wake-Up Interrupt (WAKIF)
This bit is set if bus activity has been detected while the module is in Sleep mode. The flag must be cleared by the
application.
38.11.3.3 CAN Bus Error Interrupt (CERRIF)
The CxTREC register will count the errors during transmit and receive according to the ISO11898-1:2015. The
CERRIF flag will be set based on the error counter values. The flag must be cleared by the application.
CERRIF will be set each time a threshold in the TEC/REC counter is crossed by the following conditions:
• TEC or REC exceeds the error warning state threshold.
• The transmitter or receiver transitions to the error passive state.
• The transmitter transitions to the bus off state.
• The transmitter or receiver transitions from the error passive to error active state.
• The module transitions from the bus off to error active state after the bus off recovery sequence.
When the user clears CERRIF, it will remain clear until a new counter crossing occurs.
38.11.3.4 CAN Mode Change Interrupt (MODIF)
When the OPMOD[2:0] bits change, the MODIF flag will be set. The flag must be cleared by the application.
38.11.3.5 CAN Timer Interrupt (TBCIF)
When the time base counter rolls over, TBCIF will be set. The flag must be cleared by the application.
38.11.3.6 System Error Interrupt (SERRIF)
Bus Bandwidth Error
Bandwidth errors can happen during receive and transmit.
Receive Message Assembly Buffer (RX MAB) overflow occurs when the module is unable to write a received CAN
message to RAM before the next message arrives.
Transmit Message Assembly Buffer (TX MAB) underflow occurs when the module cannot feed the TX MAB fast
enough to provide consistent data to the Bit Stream Processor.
The SERRIF flag will be set and the ICODE[6:0] bits (C1VEC[6:0]) will be set to 100 0101.
Handling of RX MAB Overflow Errors
RX MAB overflows are not acceptable for some applications. To prevent overflows, frame filtering and data saving
starts as early as possible; the latest at the beginning of the CRC field of the received message. Updating the FIFO
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status has to wait until the beginning of the 7th bit of the EOF field, since the received frame is only valid at this point.
The complete message has to be saved and the FIFO has to be updated until the end of the arbitration field of the
next message.
In case of an RX MAB overflow, the new message that caused the overflow will be discarded. The module continues
to store the message that is completely received and filtered. Afterwards, the module will be able to receive new
messages on the bus. The application will be notified using the SERRIF bit.
The SERRIF bit (CxINT[12]) will be cleared by writing a zero to the bit. This will also clear the SERRIF condition from
the ICODEx bits.
Handling of TX MAB Underflow Errors
ISO11898-1:2015 requires MAC data consistency: a transmitted message must contain consistent data. If data errors
occur due to ECC errors, or TX MAB underflow, the transmission will not start. If the transmission is in progress, it will
stop and the module will transition to either Restricted Operation or Listen Only mode, which is selectable using the
SERRLOM bit (CxCON[18]).
The module handles these errors by stopping the transmission and transitioning to Restricted Operation or Listen
Only mode. The CxTX pin will be forced high. Additionally, all TXREQs will be ignored. The application will be notified
using SERRIF. The module will continue to receive messages.
38.11.4 Interrupt Handling
The CAN FD Protocol module allows the application to handle interrupts efficiently by:
• Implementing a Look-up Table using the C1VEC registers.
• Using the status registers and deciding which interrupt to service first.
The application can also use a combination of these two methods to handle interrupts.
38.11.4.1 Interrupt Look-up Table
The ICODEx and FILHITx bits in the CxVEC register enable the application to use a Look-up Table to implement the
Interrupt Service Routine (ISR).
The following bit fields allow the application to make full use of the three interrupt pins:
• TXCODE[6:0] bits: Reflect which object has a transmit interrupt pending
• RXCODE[6:0] bits: Reflect which object has a receive interrupt pending
A separate Look-up Table can be implemented for transmit and receive interrupts. If more than one object has a
pending interrupt, the interrupt or FIFO with the highest number will show up in RXCODEx, TXCODEx and ICODEx.
Once the interrupt with the highest priority is cleared, the next highest priority interrupt will show up in C1VECH/L.
RXCODEx, TXCODEx and ICODEx are implemented with combinatorial logic using the interrupt flags as inputs.
38.11.4.2 Interrupt Status Register
The CAN FD Protocol module contains three FIFOs and a TXQ. It would be complex to use the ICODEx bits since
the interrupt priorities are determined by the module. Therefore, the following measures are taken to ensure efficient
servicing of interrupts:
• CxINT contains all main interrupt sources. The application can identify the categories of interrupts that are
pending and decide the order in which interrupts are to be serviced (e.g., RXIF).
• All categories of interrupts for all FIFOs are combined into individual registers: CxRXIF, CxTXIF, CxRXOVIF and
CxTXATIF. The application can identify the RFIFx bits that are pending by reading only one register. The same is
true for TFIFx, RXOVIF and TXATIF.
• In the register map, the Interrupt Status registers are arranged in a single block: CxVEC, followed by CxINT,
CxRXIF, CxTXIF, CxRXOVIF and CxTXATIF. This arrangement allows all status registers to be read with a
single read access.
38.11.5 Interrupt Flags
Table 1-13 summarizes all interrupt flags and lists how interrupts are cleared.
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Table 38-13. Interrupt Flags
Categories
Cleared by
Module(1)
Cleared by
Application
Read-Only(2)
CxFIFOSTAy
FIFO
X
-
-
RX FIFO
TFNIF, TFHIF,
TFEIF
CxFIFOSTAy
FIFO
X
-
-
TX FIFO
TXQNIF,
TXQEIF
CxTXQSTA
TXQ
X
-
-
Transmit
Queue
RXOVIF
CxFIFOSTAy
FIFO
-
X
-
RX Overrun
TXATIF
CxFIFOSTAy,
CxTXQSTA
FIFO, TXQ
-
X
-
TX Attempt
TEFFIF,
TEFHIF,
TEFNEIF
CxTEFSTA
FIFO
X
-
-
TEF
TEFOVIF
CxTEFSTA
FIFO
-
X
-
TEF Overrun
RFIF[3:1]
CxRXIF
Combined
-
-
X
All RX FIFOs
TFIF[3:1]
CxTXIF
Combined
-
-
X
All TX FIFOs
RFOVIF[3:1]
CxRXOVIF
Combined
-
-
X
All RX FIFO
Overruns
TFATIF[3:0]
CxTXATIF
Combined
-
-
X
All TX FIFO
Attempts
RXIF
CxINT
Main
-
-
X
RX
TXIF
CxINT
Main
-
-
X
TX
RXOVIF
CxINT
Main
-
-
X
RX Overrun
TXATIF
CxINT
Main
-
-
X
TX Attempt
TEFIF
CxINT
Main
-
-
X
TEF
IVMIF
CxINT
Main
-
X
-
Invalid
Message
WAKIF
CxINT
Main
-
X
-
Wake-up
CERRIF
CxINT
Main
-
X
-
CAN Bus Error
MODIF
CxINT
Main
-
X
-
Mode Change
TBCIF
CxINT
Main
-
X
-
Time Base
Counter
SERRIF
CxINT
Main
-
X
-
System Error
Flags
Registers
RFFIF, RFHIF,
RFNIF
Description
Notes:
1. The flags will be cleared when the condition of the FIFO terminates, initiated by the UINC bit
(CxFIFOCONy[8]).
2. The flags need to be cleared in the preceding hierarchies.
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38.12
Error Handling
Every CAN controller checks the messages on the bus for the following errors: bit, stuff, CRC, form and ACK errors.
Whenever the controller detects an error, an error frame is transmitted that deletes the message on the bus. Error
frames are always signaled using the nominal bit rate.
Error detection and fault confinement are described in the ISO11898-1:2015. CxTREC contains the error counters
TEC and REC (TERRCNTx, RERRCNTx). CxTREC contains the error warning and error state bits. TEC and REC
increment and decrement according to ISO11898-1:2015 specifications.
Figure 38-47 illustrates the different error states of the CAN FD Protocol module. The module starts in the error
Active state. If the TEC or REC exceeds 127, the module transitions to the error passive state. If the TEC exceeds
255, the module will transition to the bus Off state.
The module transmits active error frames when in an error Active state. It will transmit passive error frames while in
an error Passive state. When the module is in bus Off, the CxTX pin is always driven high and no dominant bits are
transmitted.
To avoid the module from transitioning to the error Passive state, the module will alert the application when the
TEC or REC reaches 96, using the CERRIF interrupt flag (see CAN Bus Error Interrupt (CERRIF)). This allows the
application to take action before it enters the error Passive state.
Figure 38-47. Error States
Error
Active
Error
Passive
Bus Off
TEC > 255
The error-free message counter, together with the error counters and error flags, can be used to determine the quality
of the bus.
38.12.1 Bus Diagnostic Registers
The Bus Diagnostic registers provide additional information about the health of the CAN bus:
•
CxBDIAG0 contains separate error counters for receive/transmit and for nominal/data bit rates. The counters
work differently than the counters in the CxTREC registers. They are simply incremented by one on every error.
They are never decremented, but can be cleared by writing ‘0’ to the register.
•
CxBDIAG1 keeps track of the kind of error that occurred since the last clearing of the register. The CxBDIAG1
register also contains the error-free message counter. The flags and the counter are cleared by writing ‘0’ to the
register.
38.12.2 Recovery from Bus Off State
If the TEC exceeds 255, the TXBO (CxTREC[21]) and CERRIF (CxINT[13]) bits will be set. The module will go to bus
off and start the bus off recovery sequence.
The bus off recovery sequence starts automatically. The module will transition out of the bus off state only after the
detection of 128 Idle conditions (see “ISO11898-1:2015: Bus Off Management”). The module will set FRESET for all
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transmit FIFOs when entering the bus Off state to ensure that the module does not try to retransmit indefinitely. The
application will be notified by CERRIF and has the option to queue new messages for transmission.
The module signals the exit from the bus Off state with the CERRIF bit and by setting the TXBOERR bit
(CxBDIAG1[23]). Additionally, C1TREC will be Reset.
38.13
Register Definitions: CAN FD Control
Long bit name prefixes for the comparator peripherals are shown in the table below. Refer to the “Long Bit Names”
section in the “Register and Bit Naming Conventions” chapter for more information.
Table 38-14. CAN FD Long Bit Name Prefixes
Peripheral
Bit Name Prefix
CAN FD 1
C1
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38.13.1 CxCON
Name:
Address:
CxCON
0x0100
CAN FD Control Register
Bit
Access
Reset
31
R/W
0
Bit
23
Access
Reset
R
1
Bit
Access
Reset
Bit
Access
Reset
30
29
TXBWS[3:0]
R/W
R/W
0
0
28
R/W
0
27
ABAT
S/HC
0
R/W
1
25
REQOP[2:0]
R/W
0
R/W
0
19
STEF
R/W
1
18
SERRLOM
R/W
0
17
ESIGM
R/W
0
16
RTXAT
R/W
0
10
9
22
OPMOD[2:0]
R
0
21
R
0
20
TXQEN
R/W
1
15
ON
R/W
0
14
13
SIDL
R/W
0
12
BRSDIS
R/W
0
11
BUSY
R
0
7
CLKSEL
R/W
0
6
PXEDIS
R/W
1
5
ISOCRCEN
R/W
1
4
3
R/W
0
R/W
0
26
24
R/W
1
R/W
1
8
WAKFIL
R/W
1
2
DNCNT[4:0]
R/W
0
1
0
R/W
0
R/W
0
WFT[1:0]
Bits 31:28 – TXBWS[3:0] Transmit Bandwidth Sharing
Delay between two consecutive transmissions (in arbitration bit times)
Value
Description
1111-110 4096
0
1011
2048
1010
1024
1001
512
1000
256
0111
128
0110
64
0101
32
0100
16
0011
8
0010
4
0001
2
0000
No delay
Bit 27 – ABAT Abort All Pending Transmissions
Value
Description
1
Signals all transmit buffers to abort transmission
0
Module will clear this bit when all transmissions are aborted
Bits 26:24 – REQOP[2:0] Request Operation Mode
Value
Description
111
Sets Restricted Operation mode
110
Sets Normal CAN 2.0 mode; error frames on CAN FD frames
101
Sets External Loopback mode
100
Sets Configuration mode
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Value
011
010
001
000
Description
Sets Listen Only mode
Sets Internal Loopback mode
Sets Disable mode
Sets Normal CAN FD mode; supports mixing of full CAN FD and Classic CAN 2.0 frames
Bits 23:21 – OPMOD[2:0] Operation Mode Status
Value
Description
111
Module is in Restricted Operation mode
110
Module is in Normal CAN 2.0 mode; error frames on CAN FD frames
101
Module is in External Loopback mode
100
Module is in Configuration mode
011
Module is in Listen Only mode
010
Module is in Internal Loopback mode
001
Module is in Disable mode
000
Module is in Normal CAN FD mode; supports mixing of full CAN FD and Classic CAN 2.0 frames
Bit 20 – TXQEN Enable Transmit Queue(2)
Value
Description
1
Enables TXQ and reserves space in RAM
0
Does not reserve space in RAM for TXQ
Bit 19 – STEF Store in Transmit Event FIFO(2)
Value
Description
1
Saves transmitted messages in TEF
0
Does not save transmitted messages in TEF
Bit 18 – SERRLOM Transition to Listen Only Mode on System Error(2)
Value
Description
1
Transitions to Listen Only mode on System Error
0
Transitions to Restricted Operation mode on System Error
Bit 17 – ESIGM Transmit ESI in Gateway Mode(2)
Value
Description
1
ESI is transmitted as recessive when the ESI of message is high or CAN controller is error passive
0
ESI reflects error status of the CAN controller
Bit 16 – RTXAT Restrict Retransmission Attempts(2)
Value
Description
1
Restricted retransmissions attempts, uses TXAT[1:0]
0
Unlimited number of retransmission attempts, TXAT[1:0] bits will be ignored
Bit 15 – ON CAN Enable
Value
Description
1
CAN module is enabled
0
CAN module is disabled
Bit 13 – SIDL CAN stop in Idle mode
Value
Description
1
Stops module operation in Idle mode
0
Does not stop module operation in Idle mode
Bit 12 – BRSDIS Bit Rate Switching (BRS) Disable
Value
Description
1
Bit rate switching is disabled, regardless of BRS in the transmit message object
0
Bit rate switching depends on the BRS of the transmit message object
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Bit 11 – BUSY CAN Module is Busy
Value
Description
1
The CAN module is active
0
The CAN module is inactive
Bits 10:9 – WFT[1:0] Selectable Wake-up Filter Time
Value
Description
11
T11 Filter
10
T10 Filter
01
T01 Filter
00
T00 Filter
Bit 8 – WAKFIL Enable CAN Bus Line Wake-up Filter(2)
Value
Description
1
Uses CAN bus line filter for wake-up
0
CAN bus line filter is not used for wake-up
Bit 7 – CLKSEL CAN Module Clock Source Select(2)
Value
Description
1
CAN module is run from EXTCLK
0
CAN module is run from system clock
Bit 6 – PXEDIS Protocol Exception Event Detection Disabled(2)
A recessive “reserved bit” following a recessive FDF bit is called a “Protocol Exception”
Value
Description
1
Protocol exception is treated as a form error
0
If a protocol exception is detected, CAN will enter the bus integrating state
Bit 5 – ISOCRCEN Enable ISO CRC in CAN FD Frames(2)
Value
Description
1
Includes stuff bit count in CRC field and uses non-zero CRC initialization vector
0
Does not include stuff bit count in CRC field and uses CRC initialization vector with all zeroes
Bits 4:0 – DNCNT[4:0] DeviceNet™ Filter Bit Number (see Filtering on Data Bytes and Table 38-9 for more details
Value
Description
11111-10 Invalid selection (compares up to 18 bits of data with EIDx)
011
10010
Compares up to Data Byte 2, bit 6 with EID17
10001
Compares up to Data byte 2, bit 7 with EID16
...
...
00010
Compares up to Data byte 0 bit 6 with EID1
00001
Compares up to Data byte 0 bit 7 with EID0
00000
Does not compare data bytes
Notes:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxCONT: Accesses the top byte CON[31:24]
– CxCONU: Accesses the upper byte CON[23:16]
– CxCONH: Accesses the high byte CON[15:8]
– CxCONL: Accesses the low byte CON[7:0]
2. These bits can only be modified in Configuration mode (OPMOD[2:0] = 100).
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38.13.2 CxNBTCFG
Name:
Address:
CxNBTCFG
0x0104
CAN Nominal Bit Time Configuration Register
Bit
31
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
19
18
17
16
BRP[7:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
TSEG1[7:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
0
15
14
13
12
10
9
8
R/W
0
R/W
0
R/W
0
11
TSEG2[6:0]
R/W
1
R/W
1
R/W
1
R/W
1
6
5
4
2
1
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
1
Access
Reset
Bit
Access
Reset
7
3
SJW[6:0]
R/W
1
Bits 31:24 – BRP[7:0] Nominal Baud Rate Prescaler
Value
Description
11111111 TQ=TCY/256
00000000 TQ=TCY/1
Bits 23:16 – TSEG1[7:0] Nominal Time Segment 1 (Propagation Segment+Phase Segment 1)
Value
Description
11111111 Length is 256 x TQ
00000000 Length is 1 x TQ
Bits 14:8 – TSEG2[6:0] Nominal Time Segment 2 (Phase Segment 2)
Value
Description
1111111 Length is 128 x TQ
0000000 Length is 1 x TQ
Bits 6:0 – SJW[6:0] Nominal Synchronization Jump Width
Value
Description
1111111 Length is 128 x TQ
0000000 Length is 1 x TQ
Notes:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxNBTCFGT: Accesses the top byte NBTCFG[31:24]
– CxNBTCFGU: Accesses the upper byte NBTCFG[23:16]
– CxNBTCFGH: Accesses the high byte NBTCFG[15:8]
– CxNBTCFGL: Accesses the low byte NBTCFG[7:0]
2. This register can only be modified in Configuration mode (OPMOD[2:0] = 100).
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38.13.3 CxDBTCFG
Name:
Address:
CxDBTCFG
0x0108
CAN Data Bit Time Configuration Register
Bit
31
30
29
28
27
26
25
24
BRP[7:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
17
16
R/W
0
R/W
1
18
TSEG1[4:0]
R/W
1
R/W
1
R/W
0
12
11
10
9
8
R/W
1
R/W
1
1
0
R/W
1
R/W
1
Access
Reset
Bit
15
14
13
TSEG2[3:0]
Access
Reset
Bit
7
6
5
4
R/W
0
R/W
0
3
2
SJW[3:0]
Access
Reset
R/W
0
R/W
0
Bits 31:24 – BRP[7:0] Data Baud Rate Prescaler
Value
Description
11111111 TQ=TCY/256
00000000 TQ=TCY/1
Bits 20:16 – TSEG1[4:0] Data Time Segment 1 (Propagation Segment+Phase Segment 1)
Bits 11:8 – TSEG2[3:0] Data Time Segment 2 (Phase Segment 2)
Bits 3:0 – SJW[3:0] Data Synchronization Jump Width
Notes:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxDBTCFGT: Accesses the top byte DBTCFG[31:24]
– CxDBTCFGU: Accesses the upper byte DBTCFG[23:16]
– CxDBTCFGH: Accesses the high byte DBTCFG[15:8]
– CxDBTCFGL: Accesses the low byte DBTCFG[7:0]
2. This register can only be modified in Configuration mode (OPMOD[2:0] = 100).
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38.13.4 CxTDC
Name:
Address:
CxTDC
0x010C
CAN Transmitter Delay Compensation Register
Bit
31
30
29
28
27
26
23
22
21
20
19
18
15
14
13
12
10
9
8
R/W
0
R/W
0
R/W
1
11
TDCO[6:0]
R/W
0
R/W
0
R/W
0
R/W
0
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
7
25
EDGFLTEN
R/W
0
24
SID11EN
R/W
0
17
16
TDCMOD[1:0]
R/W
R/W
1
0
TDCV[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
Bit 25 – EDGFLTEN Enable Edge Filtering During Bus Integration State
Value
Description
1
Edge filtering is enabled according to ISO11898-1:2015
0
Edge filtering is disabled
Bit 24 – SID11EN Enable 12-Bit SID in CAN FD Base Format Messages
Value
Description
1
RRS is used as SID11 in CAN FD base format messages: SID[11:0]={SID[10:0],SID11}
0
Does not use RRS; SID[10:0]
Bits 17:16 – TDCMOD[1:0] Transmitter Delay Compensation Mode (Secondary Sample Point (SSP))
Value
Description
11-10
Auto: Measures delay and adds TSEG1[4:0] (CxDBTCFG[19:16]; adds TDCO[6:0]
01
Manual: Does not measure, uses TDCV[5:0] +TDCO[6:0]
00
Disables
Bits 14:8 – TDCO[6:0] Transmitter Delay Compensation Offset (Secondary Sample Point (SSP))
Value is two’s complement, offset can be positive, zero or negative
Value
Description
0111111 63 x TCY
0000000 0 x TCY
11111111 -64 x TCY
Bits 5:0 – TDCV[5:0] Transmitter Delay Compensation Value bits (Secondary Sample Point (SSP))
Value
Description
111111
63 x TCY
000000
0 x TCY
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Notes:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxTDCT: Accesses the top byte TDC[31:24]
– CxTDCU: Accesses the upper byte TDC[23:16]
– CxTDCH: Accesses the high byte TDC[15:8]
– CxTDCL: Accesses the low byte TDC[7:0]
2. This register can only be modified in Configuration mode (OPMOD[2:0] = 100).
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38.13.5 CxTBC
Name:
Address:
CxTBC
0x0110
CAN Time Base Counter Register
Bit
31
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
TBC[31:24]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
TBC[23:16]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
TBC[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
TBC[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – TBC[31:0] CAN Time Base Counter
This is a free-running timer that increments every TBCPRE[9:0] clock when TBCEN is set
Notes:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxTBCT: Accesses the top byte TBC[31:24]
– CxTBCU: Accesses the upper byte TBC[23:16]
– CxTBCH: Accesses the high byte TBC[15:8]
– CxTBCL: Accesses the low byte TBC[7:0]
2. The Time Base Counter (TBC will be stopped and reset when TBCEN = 0 to save power).
3.
The TBC prescaler count will be reset on any write to CxTBC (TBCPREx will be unaffected).
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 830
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
38.13.6 CxTSCON
Name:
Address:
CxTSCON
0x0114
CAN Timestamp Control Register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
TSRES
R/W
0
17
TSEOF
R/W
0
16
TBCEN
R/W
0
15
14
13
12
11
10
9
7
6
5
4
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
3
TBCPRE[7:0]
R/W
R/W
0
0
8
TBCPRE[9:8]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bit 18 – TSRES Timestamp Reset (CAN FD frames only)
Value
Description
1
Timestamp resets at sample point of the bit following the FDF bit
0
Timestamp resets at sample point of Start-of-Frame (SOF)
Bit 17 – TSEOF Timestamp End-of-Frame (EOF)
Value
Description
1
Timestamp when frame is taken valid (11898-1 10.7):
• RX no error until last, but one bit of EOF
• TX no error until the end of EOF
0
Timestamp at “beginning” of frame:
• Classical Frame: At sample point of SOF
• FD Frame: see TSRES bit
Bit 16 – TBCEN Time Base Counter (TBC) Enable
Value
Description
1
Enables TBC
0
Stops and resets TBC
Bits 9:0 – TBCPRE[9:0] CAN Time Base Counter Prescaler
Value
Description
11111111 TBC increments every 1024 clocks
11
00000000 TBC increments every 1 clock
00
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 831
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
Note:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxTSCONT: Accesses the top byte TSCON[31:24]
– CxTSCONU: Accesses the upper byte TSCON[23:16]
– CxTSCONH: Accesses the high byte TSCON[15:8]
– CxTSCONL: Accesses the low byte TSCON[7:0]
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 832
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
38.13.7 CxVEC
Name:
Address:
CxVEC
0x0118
CAN Interrupt Code Register
Bit
31
Access
Reset
Bit
23
Access
Reset
Bit
15
30
29
28
R
1
R
0
R
0
22
21
20
R
1
R
0
14
13
Access
Reset
Bit
Access
Reset
7
27
RXCODE[6:0]
R
0
26
25
24
R
0
R
0
R
0
18
17
16
R
0
19
TXCODE[6:0]
R
0
R
0
R
0
R
0
12
11
9
8
R
0
R
0
10
FILHIT[4:0]
R
0
R
0
R
0
3
ICODE[6:0]
R
0
2
1
0
R
0
R
0
R
0
6
5
4
R
1
R
0
R
0
Bits 30:24 – RXCODE[6:0] Receive Interrupt Flag Code
Value
Description
1111111- Reserved
1000001
1000000 No interrupt
0111111- Reserved
0000100
0000011 FIFO 3 interrupt (RFIF[3] is set)
0000010 FIFO 2 interrupt (RFIF[2] is set)
0000001 FIFO 1 interrupt (RFIF[1] is set)
0000000 Reserved; FIFO 0 cannot receive
Bits 22:16 – TXCODE[6:0] Transmit Interrupt Flag Code
Value
Description
1111111- Reserved
1000001
1000000 No interrupt
0111111- Reserved
0000100
0000011 FIFO 3 interrupt (TFIF[3] is set)
0000010 FIFO 2 interrupt (TFIF[2] is set)
0000001 FIFO 1 interrupt (TFIF[1] is set)
0000000 FIFO 0 interrupt (TFIF[0] is set)
Bits 12:8 – FILHIT[4:0] Filter Hit Number
Value
Description
11111-01 Reserved
100
01011
Filter 11
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 833
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
Value
01010
00001
00000
Description
Filter 10
Filter 1
Filter 0
Bits 6:0 – ICODE[6:0] Interrupt Flag Code
Value
Description
1111111- Reserved
1001011
1001010 Transmit attempt interrupt (Any bit in CxTXATIF is set)
1001001 Transmit event FIFO interrupt (any bit in CxTEFSTA is set)
1001000 Invalid message occurred (IVMIF/IE)
1000111 CAN module mode change occurred (MODIF/IE)
1000110 CAN timer overflow (TBCIF/IE)
1000101 RX/TX MAB overflow/underflow (RX: Message received before previous message was saved to
memory; TX: Can’t feed TX MAB fast enough to transmit consistent data.) (SERRIF/IE)
1000100 Address error interrupt (illegal FIFO address presented to system) (SERRIF/IE)
1000011 Receive FIFO overflow interrupt (any bit in CxRXOVIF is set)
1000010 Wake-up interrupt (WAKIF/WAKIE)
1000001 Error interrupt (CERRIF/IE)
1000000 No interrupt
0111111- Reserved
0000100
0000011 FIFO 3 Interrupt (TFIF3 or RFIF3 is set)
0000010 FIFO 2 Interrupt (TFIF2 or RFIF2 is set)
0000001 FIFO 1 Interrupt (TFIF1 or RFIF1 is set)
0000000 FIFO 0 Interrupt (TFIF0 is set)
Note:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxVECT: Accesses the top byte VEC[31:24]
– CxVECU: Accesses the upper byte VEC[23:16]
– CxVECH: Accesses the high byte VEC[15:8]
– CxVECL: Accesses the low byte VEC[7:0]
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 834
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
38.13.8 CxINT
Name:
Address:
CxINT
0x011C
CAN Interrupt Register
Bit
Access
Reset
Bit
31
IVMIE
R/W
0
30
WAKIE
R/W
0
29
CERRIE
R/W
0
28
SERRIE
R/W
0
27
RXOVIE
R/W
0
26
TXATIE
R/W
0
25
24
23
22
21
20
TEFIE
R/W
0
19
MODIE
R/W
0
18
TBCIE
R/W
0
17
RXIE
R/W
0
16
TXIE
R/W
0
15
IVMIF
HS/C
0
14
WAKIF
HS/C
0
13
CERRIF
HS/C
0
12
SERRIF
HS/C
0
11
RXOVIF
R
0
10
TXATIF
R
0
9
8
7
6
5
4
TEFIF
R
0
3
MODIF
HS/C
0
2
TBCIF
HS/C
0
1
RXIF
R
0
0
TXIF
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 31 – IVMIE Invalid Message Interrupt Enable
Value
Description
1
Invalid message interrupt is enabled
0
Invalid message interrupt is disabled
Bit 30 – WAKIE Bus Wake-up Activity Interrupt Enable
Value
Description
1
Wake-up activity interrupt is enabled
0
Wake-up activity interrupt is disabled
Bit 29 – CERRIE CAN Bus Error Interrupt Enable
Value
Description
1
CAN bus error interrupt is enabled
0
CAN bus error interrupt is disabled
Bit 28 – SERRIE System Error Interrupt Enable
Value
Description
1
System error interrupt is enabled
0
System error interrupt is disabled
Bit 27 – RXOVIE Receive Buffer Overflow Interrupt Enable
Value
Description
1
Receive buffer overflow interrupt is enabled
0
Receive buffer overflow interrupt is disabled
Bit 26 – TXATIE Transmit Attempt Interrupt Enable
Value
Description
1
Transmit attempt interrupt is enabled
0
Transmit attempt interrupt is disabled
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 835
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
Bit 20 – TEFIE Transmit Event FIFO Interrupt Enable
Value
Description
1
Transmit event FIFO interrupt is enabled
0
Transmit event FIFO interrupt is disabled
Bit 19 – MODIE Mode Change Interrupt Enable
Value
Description
1
Mode change interrupt is enabled
0
Mode change interrupt is disabled
Bit 18 – TBCIE CAN Timer Interrupt Enable
Value
Description
1
CAN timer interrupt is enabled
0
CAN timer interrupt is disabled
Bit 17 – RXIE Receive Object Interrupt Enable
Value
Description
1
Receive object interrupt is enabled
0
Receive object interrupt is disabled
Bit 16 – TXIE Transmit Object Interrupt Enable
Value
Description
1
Transmit object interrupt is enabled
0
Transmit object interrupt is disabled
Bit 15 – IVMIF Invalid Message Interrupt Flag(2)
Value
Description
1
Invalid message interrupt occurred
0
No invalid message interrupt
Bit 14 – WAKIF Bus Wake-up Activity Interrupt Flag(2)
Value
Description
1
Wake-up activity interrupt occurred
0
No wake-up activity interrupt
Bit 13 – CERRIF CAN Bus Error Interrupt Flag(2)
Value
Description
1
CAN bus error interrupt occurred
0
No CAN bus error interrupt
Bit 12 – SERRIF System Error Interrupt Flag(2)
Value
Description
1
System error interrupt occurred
0
No system error interrupt
Bit 11 – RXOVIF Receive Buffer Overflow Interrupt Flag
Value
Description
1
Receive buffer overflow interrupt occurred
0
No receive buffer overflow interrupt
Bit 10 – TXATIF Transmit Attempt Interrupt Flag
Value
Description
1
Transmit attempt interrupt occurred
0
No transmit attemp interrupt
Bit 4 – TEFIF Transmit Event FIFO Interrupt Flag
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
Value
1
0
Description
Transmit event FIFO interrupt occurred
No transmit event FIFO interrupt
Bit 3 – MODIF CAN Mode Change Interrupt Flag(2)
Value
Description
1
CAN module mode change occurred (OPMOD[2:0] have changed to reflect REQOP[2:0])
0
No mode change occurred
Bit 2 – TBCIF CAN Timer Overflow Interrupt Flag(2)
Value
Description
1
TBC has overflowed
0
TBC has not overflowed
Bit 1 – RXIF Receive Object Interrupt Flag
Value
Description
1
Receive object interrupt is pending
0
No Receive object interrupts are pending
Bit 0 – TXIF Transmit Object Interrupt Flag
Value
Description
1
Transmit object interrupt is pending
0
No transmit object interrupts are pending
Notes:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxINTT: Accesses the top byte INT[31:24]
– CxINTU: Accesses the upper byte INT[23:16]
– CxINTH: Accesses the high byte INT[15:8]
– CxINTL: Accesses the low byte INT[7:0]
2. Flag is set by hardware and cleared by application.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 837
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
38.13.9 CxRXIF
Name:
Address:
CxRXIF
0x0120
CAN Receive Interrupt Status Register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
RFIF[2:0]
R
0
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
R
0
R
0
Bits 3:1 – RFIF[2:0] Receive FIFO Interrupt Pending
Value
Description
1
One or more enabled receive FIFO interrupts are pending for the respective FIFO
0
No enabled receive FIFO interrupts for the respective FIFO are pending
Notes:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxRXIFT: Accesses the top byte RXIF[31:24]
– CxRXIFU: Accesses the upper byte RXIF[23:16]
– CxRXIFH: Accesses the high byte RXIF[15:8]
– CxRXIFL: Accesses the low byte RXIF[7:0]
2. RFIFx is the ‘or’ of all enabled RX FIFO flags (individual flags need to be cleared in the FIFO register).
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 838
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
38.13.10 CxTXIF
Name:
Address:
CxTXIF
0x0124
CAN Transmit Interrupt Status Register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
TFIF[3:0]
Access
Reset
R
0
R
0
Bits 3:0 – TFIF[3:0] Transmit FIFO/TXQ Interrupt Pending
Value
Description
1
One or more enabled transmit FIFO/TXQ interrupts are pending for the respective FIFO/TXQ
0
No enabled transmit FIFO/TXQ interrupts for the respective FIFO/TXQ are pending
Notes:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxTXIFT: Accesses the top byte TXIF[31:24]
– CxTXIFU: Accesses the upper byte TXIF[23:16]
– CxTXIFH: Accesses the high byte TXIF[15:8]
– CxTXIFL: Accesses the low byte TXIF[7:0]
2. TFIFx is the ‘or’ of all enabled TX FIFO flags (individual flags need to be cleared in the FIFO register).
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
38.13.11 CxRXOVIF
Name:
Address:
CxRXOVIF
0x0128
CAN Receive Overflow Interrupt Status Register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
RFOVIF[2:0]
R
0
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
R
0
R
0
Bits 3:1 – RFOVIF[2:0] Receive FIFO Overflow Interrupt Pending
Value
Description
1
Interrupt is pending
0
Interrupt is not pending
Notes:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxRXOVIFT: Accesses the top byte RXOVIF[31:24]
– CxRXOVIFU: Accesses the upper byte RXOVIF[23:16]
– CxRXOVIFH: Accesses the high byte RXOVIF[15:8]
– CxRXOVIFL: Accesses the low byte RXOVIF[7:0]
2. RFOVIFx mirrors the overflow bit of its respective FIFO register, individual flags need to be cleared in said
FIFO register.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 840
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
38.13.12 CxTXATIF
Name:
Address:
CxTXATIF
0x012C
CAN Transmit Attempt Interrupt Status Register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
TFATIF[3:0]
Access
Reset
R
0
R
0
Bits 3:0 – TFATIF[3:0] Transmit FIFO/TXQ Attempt Interrup Pending
Value
Description
1
Interrupt is pending
0
Interrupt is not pending
Notes:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxTXATIFT: Accesses the top byte TXATIF[31:24]
– CxTXATIFU: Accesses the upper byte TXATIF[23:16]
– CxTXATIFH: Accesses the high byte TXATIF[15:8]
– CxTXATIFL: Accesses the low byte TXATIF[7:0]
2. TFATIFx mirrors the transmit attempt interrupt bit of its respective FIFO register, individual flags need to be
cleared in said FIFO register.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
38.13.13 CxTXREQ
Name:
Address:
CxTXREQ
0x0130
CAN Transmit Request Register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
R/W
0
1
TXREQ[3:0]
R/W
R/W
0
0
0
R/W
0
Bits 3:0 – TXREQ[3:0] Message Send Request
Setting each bit to ‘1’ requests sending a message in its respective object. The bit will automatically clear when the
message(s) queued in the object is (are) successfully sent. This bit can NOT be used for aborting a transmission.
Notes:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxTXREQT: Accesses the top byte TXREQ[31:24]
– CxTXREQU: Accesses the upper byte TXREQ[23:16]
– CxTXREQH: Accesses the high byte TXREQ[15:8]
– CxTXREQL: Accesses the low byte TXREQ[7:0]
2. These bits are only valid if the associated objects are configured as transmit objects (TXEN = 1). Otherwise,
setting them has no effect.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
38.13.14 CxTREC
Name:
Address:
CxTREC
0x0134
CAN Transmit/Receive Error Count Register
Bit
31
30
29
28
27
26
25
24
23
22
21
TXBO
R
1
20
TXBP
R
0
19
RXBP
R
0
18
TXWARN
R
0
17
RXWARN
R
0
16
EWARN
R
0
Bit
15
14
13
10
9
8
Access
Reset
R
0
R
0
R
0
12
11
TERRCNT[7:0]
R
R
0
0
R
0
R
0
R
0
Bit
7
6
5
2
1
0
Access
Reset
R
0
R
0
R
0
4
3
RERRCNT[7:0]
R
R
0
0
R
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit 21 – TXBO Transmitter in Error Bus Off State
In Configuration mode, TXBO is set since the module is not on the bus.
Bit 20 – TXBP Transmitter in Error Bus Passive State
Bit 19 – RXBP Receiver in Error Bus Passive State
Bit 18 – TXWARN Transmitter in Error Warning State
Bit 17 – RXWARN Receiver in Error Warning State
Bit 16 – EWARN Transmitter or Receiver is in Error Warning State
Bits 15:8 – TERRCNT[7:0] Transmit Error Counter
Bits 7:0 – RERRCNT[7:0] Receive Error Counter
Note:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxTRECT: Accesses the top byte TREC[31:24]
– CxTRECU: Accesses the upper byte TREC[23:16]
– CxTRECH: Accesses the high byte TREC[15:8]
– CxTRECL: Accesses the low byte TREC[7:0]
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 843
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
38.13.15 CxBDIAG0
Name:
Address:
CxBDIAG0
0x0138
CAN Bus Diagnostics Register 0
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
DTERRCNT[7:0]
R/W
R/W
0
0
20
19
DRERRCNT[7:0]
R/W
R/W
0
0
12
11
NTERRCNT[7:0]
R/W
R/W
0
0
4
3
NRERRCNT[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:24 – DTERRCNT[7:0] Data Bit Rate Transmit Error Counter
Bits 23:16 – DRERRCNT[7:0] Data Bit Rate Receive Error Counter
Bits 15:8 – NTERRCNT[7:0] Nominal Bit Rate Transmit Error Counter
Bits 7:0 – NRERRCNT[7:0] Nominal Bit Rate Receive Error Counter
Note:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxBDIAG0T: Accesses the top byte BDIAG0[31:24]
– CxBDIAG0U: Accesses the upper byte BDIAG0[23:16]
– CxBDIAG0H: Accesses the high byte BDIAG0[15:8]
– CxBDIAG0L: Accesses the low byte BDIAG0[7:0]
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 844
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
38.13.16 CxBDIAG1
Name:
Address:
CxBDIAG1
0x013C
CAN Bus Diagnostics Register 1
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
DLCMM
R/W
0
30
ESI
R/W
0
29
DCRCERR
R/W
0
28
DSTUFERR
R/W
0
27
DFORMERR
R/W
0
26
25
DBIT1ERR
R/W
0
24
DBIT0ERR
R/W
0
23
TXBOERR
R/W
0
22
21
NCRCERR
R/W
0
20
NSTUFERR
R/W
0
19
NFORMERR
R/W
0
18
NACKERR
R/W
0
17
NBIT1ERR
R/W
0
16
NBIT0ERR
R/W
0
15
14
13
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
12
11
EFMSGCNT[15:8]
R/W
R/W
0
0
4
3
EFMSGCNT[7:0]
R/W
R/W
0
0
Bit 31 – DLCMM DLC Mismatch
During a transmission or reception, the specified DLC is larger than the PLSIZEx of the FIFO element.
Bit 30 – ESI ESI Flag of Received CAN FD Message Set
Bit 29 – DCRCERR Received Message with CRC Incorrect Checksum in the Data Segment
The CRC Checksum of a received message is considered incorrect if the CRC of the incoming message does not
match with the CRC calculated from the received data.
Bit 28 – DSTUFERR Received Message with Illegal Sequence in the Data Segment
An Illegal Sequence occurs when more than five equal bits in sequence in a part of the received message where this
is not allowed.
Bit 27 – DFORMERR Received Frame with a Fixed Format Error in Data Segment
A fixed format error occurs when a part of the incoming frame with a fixed format has the wrong format.
Bit 25 – DBIT1ERR Transmitted Message Recessive Level in Data Segment
During the data segment of a message transmission, the device wanted to send a recessive level (bit of logical value
‘1’), but the monitored bus value was dominant.
Bit 24 – DBIT0ERR Transmitted Message Dominant Level in Data Segment
During the transmission of a message, the device wanted to send a dominant level (logical value ‘0’), but the
monitored bus value was recessive.
Bit 23 – TXBOERR Device Went to Bus Off
Bit 21 – NCRCERR Received Message with CRC Incorrect Checksum in Non-Data Segment
The CRC Checksum of a received message is considered incorrect if the CRC of the incoming message does not
match with the CRC calculated from the received data.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 845
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
Bit 20 – NSTUFERR Received Message with Illegal Sequence in Non-Data Segment
An Illegal Sequence occurs when more than five equal bits in sequence in a part of the received message where this
is not allowed
Bit 19 – NFORMERR Received Frame with a Fixed Format Error in Non-Data Segment
A fixed format error occurs when a part of the incoming frame with a fixed format has the wrong format
Bit 18 – NACKERR Transmitted Message Not Acknowledged
Transmitted message was not Acknowledged
Bit 17 – NBIT1ERR Transmitted Message Dominant Level in Non-Data Segment
During the non-data segment of a message transmission, the device wanted to send a recessive level (bit of logical
value ‘1’), but the monitored bus value was dominant
Bit 16 – NBIT0ERR Transmitted Message Dominant Level in Non-Data Segment
During the transmission of a message(or Acknowledge bit, or active error flag or overload flag), the device wanted
to send a dominant level (logical value ‘0’), but the monitored bus value was recessive. During bus off recovery, this
status is set each time a sequence of 11 recessive bits have been monitored. This enables the CPU to monitor the
proceeding of the bus off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).
Bits 15:0 – EFMSGCNT[15:0] Error-Free Message Counter
Note:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxBDIAG1T: Accesses the top byte BDIAG1[31:24]
– CxBDIAG1U: Accesses the upper byte BDIAG1[23:16]
– CxBDIAG1H: Accesses the high byte BDIAG1[15:8]
– CxBDIAG1L: Accesses the low byte BDIAG1[7:0]
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 846
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
38.13.17 CxTEFCON
Name:
Address:
CxTEFCON
0x0140
CAN Transmit Event FIFO Control Register
Bit
31
30
29
Access
Reset
Bit
28
27
25
24
R/W
0
26
FSIZE[4:0]
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
18
17
16
15
14
13
12
11
10
FRESET
S/HC
1
9
8
UINC
S/HC
0
7
6
5
TEFTSEN
R/W
0
4
3
TEFOVIE
R/W
0
2
TEFFIE
R/W
0
1
TEFHIE
R/W
0
0
TEFNEIE
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 28:24 – FSIZE[4:0] FIFO Size(2)
Value
Description
11111
FIFO is 32 messages deep
00010
FIFO is 3 messages deep
00001
FIFO is 2 messages deep
00000
FIFO is 1 message deep
Bit 10 – FRESET FIFO Reset
Value
Description
1
FIFO will be reset when bit is set, cleared by hardware when FIFO is reset; the user needs to poll
whether this bit is clear before taking any action
0
No effect
Bit 8 – UINC Increment Tail
Value
Description
1
When this bit is set, the FIFO tail will increment by a single message
0
FIFO tail will not increment
Bit 5 – TEFTSEN Transmit Event FIFO Timestamp Enable(2)
Value
Description
1
Timestamps elements in TEF
0
Does not timestamp elements in TEF
Bit 3 – TEFOVIE Transmit Event FIFO Overflow Interrupt Enable
Value
Description
1
Interrupt is enabled for overflow event
0
Interrupt is disabled for overflow event
Bit 2 – TEFFIE Transmit Event FIFO Full Interrupt Enable
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 847
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
Value
1
0
Description
Interrupt is enabled for FIFO full
Interrupt is disabled for FIFO full
Bit 1 – TEFHIE Transmit Event FIFO Half Full Interrupt Enable
Value
Description
1
Interrupt is enabled for FIFO half full
0
Interrupt is disabled for FIFO half full
Bit 0 – TEFNEIE Transmit Event FIFO Not Empty Interrupt Enable
Value
Description
1
Interrupt is enabled for FIFO not empty
0
Interrupt is disabled for FIFO not empty
Notes:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxTEFCONT: Accesses the top byte TEFCON[31:24]
– CxTEFCONU: Accesses the upper byte TEFCON[23:16]
– CxTEFCONH: Accesses the high byte TEFCON[15:8]
– CxTEFCONL: Accesses the low byte TEFCON[7:0]
2. These bits can only be modified in Configuration mode (OPMOD[2:0] = 100.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 848
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
38.13.18 CxTEFSTA
Name:
Address:
CxTEFSTA
0x0144
CAN Transmit Event FIFO Status Register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
TEFOVIF
HS/C
0
2
TEFFIF
R
0
1
TEFHIF
R
0
0
TEFNEIF
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 3 – TEFOVIF Transmit Event FIFO Overflow Interrupt Flag
Value
Description
1
Overflow event has occurred
0
No overflow event has occurred
Bit 2 – TEFFIF Transmit Event FIFO Full Interrupt Flag(2)
Value
Description
1
FIFO is full
0
FIFO is not full
Bit 1 – TEFHIF Transmit Event FIFO Half Full Interrupt Flag(2)
Value
Description
1
FIFO is greater than or equal to half full
0
FIFO is less than half full
Bit 0 – TEFNEIF Transmit Event FIFO Not Empty Interrupt Flag(2)
Value
Description
1
FIFO is not empty
0
FIFO is empty
Notes:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxTEFSTAT: Accesses the top byte TEFSTA[31:24]
– CxTEFSTAU: Accesses the upper byte TEFSTA[23:16]
– CxTEFSTAH: Accesses the high byte TEFSTA[15:8]
– CxTEFSTAL: Accesses the low byte TEFSTA[7:0]
2. These bits are read-only and reflect the status of the FIFO.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
38.13.19 CxTEFUA
Name:
Address:
CxTEFUA
0x0148
CAN Transmit Event FIFO User Address Register
Bit
31
30
29
28
27
TEFUA[31:24]
R
R
x
x
26
25
24
Access
Reset
R
x
R
x
R
x
R
x
R
x
R
x
Bit
23
22
21
18
17
16
R
x
20
19
TEFUA[23:16]
R
R
x
x
Access
Reset
R
x
R
x
R
x
R
x
R
x
Bit
15
14
13
12
11
10
9
8
R
x
R
x
R
x
R
x
3
2
1
0
R
x
R
x
R
x
R
x
TEFUA[15:8]
Access
Reset
R
x
R
x
R
x
R
x
Bit
7
6
5
4
TEFUA[7:0]
Access
Reset
R
x
R
x
R
x
R
x
Bits 31:0 – TEFUA[31:0] Transmit Event FIFO User Address
A read of this register will return the address where the ntext event is to be read (FIFO tail).
Notes:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxTEFUAT: Accesses the top byte TEFUA[31:24]
– CxTEFUAU: Accesses the upper byte TEFUA[23:16]
– CxTEFUAH: Accesses the high byte TEFUA[15:8]
– CxTEFUAL: Accesses the low byte TEFUA[7:0]
2. This register is not ensured to read correctly in Configuration mode and needs to only be accessed when the
module is not in Configuration mode.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 850
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
38.13.20 CxFIFOBA
Name:
Address:
CxFIFOBA
0x014C
CAN Message Memory Base Address Register
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
FIFOBA[31:24]
R/W
R/W
0
0
20
19
FIFOBA[23:16]
R/W
R/W
0
0
12
11
FIFOBA[15:8]
R/W
R/W
0
0
4
3
FIFOBA[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – FIFOBA[31:0] Message Memory Base Address
Defines the base address for the transmit event FIFO followed by the message objects
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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CAN FD - Controller Area Network, Flexible ...
38.13.21 CxTXQCON
Name:
Address:
CxTXQCON
0x0150
CAN Transmit Queue Control Register
Bit
Access
Reset
Bit
31
29
28
27
R/W
0
30
PLSIZE[2:0]
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
R/W
1
R/W
1
R/W
0
R/W
0
Bit
15
14
13
12
7
TXEN
R
1
6
5
4
TXATIE
R/W
0
Access
Reset
24
R/W
0
R/W
0
17
16
R/W
0
R/W
0
11
10
FRESET
S/HC
1
9
TXREQ
R/W/HC
0
8
UINC
S/HC
0
3
2
TXQEIE
R/W
0
1
0
TXQNIE
R/W
0
Access
Reset
Bit
25
18
TXPRI[4:0]
R/W
0
TXAT[1:0]
Access
Reset
26
FSIZE[4:0]
R/W
0
Bits 31:29 – PLSIZE[2:0] Payload Size(2)
Value
Description
111
64 data bytes
110
48 data bytes
101
32 data bytes
100
24 data bytes
011
20 data bytes
010
16 data bytes
001
12 data bytes
000
8 data bytes
Bits 28:24 – FSIZE[4:0] FIFO Size(2)
Value
Description
11111
FIFO is 32 messages deep
00010
FIFO is 3 messages deep
00001
FIFO is 2 messages deep
00000
FIFO is 1 messages deep
Bits 22:21 – TXAT[1:0] Retransmission Attempts
This feature is enabled when RTXAT (CxCON[16]) is set
Value
Description
11
Unlimited number of retransmission attempts
10
Unlimited number of retransmission attempts
01
Three retransmission attempts
00
Disable retransmission attempts
Bits 20:16 – TXPRI[4:0] Message Transmit Priority
Value
Description
11111
Highest message priority
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 852
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
Value
00000
Description
Lowest message priority
Bit 10 – FRESET FIFO Reset
Value
Description
1
FIFO will be reset when this bit is set, cleared by hardware when FIFO is reset; user needs to poll
whether this bit is clear before taking any action
0
No effect
Bit 9 – TXREQ Message Send Request
Value
Description
1
Requests sending a message; the bit will automatically clear when all the messages queued in the
TXQ are successfully sent
0
Clearing the bit to ‘0’ while set (‘1’) will request a message abort.
Bit 8 – UINC Increment Head/Tail
When this bit is set, the FIFO head will increment by a single message.
Bit 7 – TXEN TX Enable
Value
Description
1
The transmit message queue is always configured as a transmitter; this bit will always read as ‘1’
Bit 4 – TXATIE Transmit Attempts Exhausted Interrupt Enable
Value
Description
1
Enables interrupt
0
Disables interrupt
Bit 2 – TXQEIE Transmit Queue Empty Interrupt Enable
Value
Description
1
Interrupt is enabled for TXQ empty
0
Interrupt is disabled for TXQ empty
Bit 0 – TXQNIE Transmit QUeue Not Full Interrupt Enable
Value
Description
1
Interrupt is enabled for TXQ not full
0
Interrupt is disabled for TXQ not full
Notes:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxTXQCONT: Accesses the top byte TXQCON[31:24]
– CxTXQCONU: Accesses the upper byte TXQCON[23:16]
– CxTXQCONH: Accesses the high byte TXQCON[15:8]
– CxTXQCONL: Accesses the low byte TXQCON[7:0]
2. These bits can only be modified in Configuration mode (OPMOD[2:0] = 100.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 853
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
38.13.22 CxTXQSTA
Name:
Address:
CxTXQSTA
0x0154
CAN Transmit Queue Status Register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
9
8
R
0
R
0
10
TXQCI[4:0]
R
0
R
0
R
0
4
TXATIF
HS/C
0
3
1
0
TXQNIF
R
1
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
7
TXABT
R
0
6
TXLARB
R
0
5
TXERR
R
0
2
TXQEIF
R
1
Bits 12:8 – TXQCI[4:0] Transmit Queue Message Index(2)
A read of this register will return an index to the message the FIFO will next attempt to transmit.
Bit 7 – TXABT Message Aborted Status(3)
Value
Description
1
Message was aborted
0
Message completed successfully
Bit 6 – TXLARB Message Lost Arbitration Status(3)
Value
Description
1
Message lost arbitration while being sent
0
Message did not lose arbitration while being sent
Bit 5 – TXERR Error Detected During Transmission(3)
Value
Description
1
A bus error occurred while the message was being sent
0
A bus error did not occur while the message was being sent
Bit 4 – TXATIF Transmit Attempts Exhausted Interrupt Pending
Value
Description
1
Interrupt is pending
0
Interrupt is not pending
Bit 2 – TXQEIF Transmit Queue Empty Interrupt Flag
Value
Description
1
TXQ is empty
0
TXQ is not empty, at least one message is queued to be transmitted
Bit 0 – TXQNIF Transmit Queue Not Full Interrupt Flag
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
Value
1
0
Description
TXQ is not full
TXQ is full
Notes:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxTXQSTAT: Accesses the top byte TXQSTA[31:24]
– CxTXQSTAU: Accesses the upper byte TXQSTA[23:16]
– CxTXQSTAH: Accesses the high byte TXQSTA[15:8]
– CxTXQSTAL: Accesses the low byte TXQSTA[7:0]
2. The TXQCI[4:0] bits give a zero-indexed value to the message in the TXQ. IF the TXQ is four messages deep
(FSIZE = 3), TXQCIx will take on a value of 0 to 3, depending on the state of the TXQ
3.
These bits are updated when a message completes (or aborts) or when the TXQ is reset.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 855
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
38.13.23 CxTXQUA
Name:
Address:
CxTXQUA
0x0158
CAN Transmit Queue User Address Register
Bit
31
30
29
28
27
TXQUA[31:24]
R
R
x
x
26
25
24
Access
Reset
R
x
R
x
R
x
R
x
R
x
R
x
Bit
23
22
21
18
17
16
R
x
20
19
TXQUA[23:16]
R
R
x
x
Access
Reset
R
x
R
x
R
x
R
x
R
x
Bit
15
14
13
12
11
10
9
8
R
x
R
x
R
x
R
x
3
2
1
0
R
x
R
x
R
x
R
x
TXQUA[15:8]
Access
Reset
R
x
R
x
R
x
R
x
Bit
7
6
5
4
TXQUA[7:0]
Access
Reset
R
x
R
x
R
x
R
x
Bits 31:0 – TXQUA[31:0] TXQ User Address
A read of this register will return the address where the next message is to be written (TXQ head)
Notes:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxTXQUAT: Accesses the top byte TXQUA[31:24]
– CxTXQUAU: Accesses the upper byte TXQUA[23:16]
– CxTXQUAH: Accesses the high byte TXQUA[15:8]
– CxTXQUAL: Accesses the low byte TXQUA[7:0]
2. This register is not ensured to read correctly in Configuration mode and needs to only be accessed when the
module is not in Configuration mode.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 856
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
38.13.24 CxFIFOCONy
Name:
Address:
CxFIFOCONy
0x00
CAN FIFO y Control Register
Bit
Access
Reset
Bit
31
29
28
27
R/W
0
30
PLSIZE[2:0]
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
19
R/W
1
R/W
1
R/W
0
R/W
0
Bit
15
14
13
12
7
TXEN
R/W
0
6
RTREN
R/W
0
5
RXTSEN
R/W
0
4
TXATIE
R/W
0
Access
Reset
24
R/W
0
R/W
0
17
16
R/W
0
R/W
0
11
10
FRESET
S/HC
1
9
TXREQ
R/W/HC
0
8
UINC
S/HC
0
3
RXOVIE
R/W
0
2
TFERFFIE
R/W
0
1
TFHRFHIE
R/W
0
0
TFNRFNIE
R/W
0
Access
Reset
Bit
25
18
TXPRI[4:0]
R/W
0
TXAT[1:0]
Access
Reset
26
FSIZE[4:0]
R/W
0
Bits 31:29 – PLSIZE[2:0] Payload Size(3)
Value
Description
111
64 data bytes
110
48 data bytes
101
32 data bytes
100
24 data bytes
011
20 data bytes
010
16 data bytes
001
12 data bytes
000
8 data bytes
Bits 28:24 – FSIZE[4:0] FIFO Size(3)
Bits 22:21 – TXAT[1:0] Retransmission Attempts
This feature is enabled when RTXAT (CxCON[16]) is set.
Value
Description
11
Unlimited number of retransmission attempts
10
Unlimited number of retransmission attempts
01
Three retransmission attempts
00
Disables retransmission attempts
Bits 20:16 – TXPRI[4:0] Message Transmit Priority
Value
Description
11111
Highest message priority
00000
Lowest message priority
Bit 10 – FRESET FIFO Reset
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
Value
1
0
Description
FIFO will be reset when bit is set, cleared by hardware whenever FIFO is reset, user needs to poll
whether this bit is clear before taking any action
No effect
Bit 9 – TXREQ Message Send Request
Value
Condition
1
TXEN = 1 (FIFO configured as a transmit
FIFO)
0
x
TXEN = 1 (FIFO configured as a transmit
FIFO)
TXEN = 0 (FIFO configured as a receive
FIFO)
Bit 8 – UINC Increment Head/Tail
Value
Condition
1
TXEN = 1 (FIFO configured as a transmit
FIFO)
1
TXEN = 0 (FIFO configured as a receive
FIFO)
Description
Requests sending a message; the bit will automatically
clear when all the messages queued in the FIFO are
successfully sent
Clearing the bit to ‘0’ while set (‘1’) will request a
message abort
This bit has no effect
Description
When this bit is set, the FIFO head will increment by a
single message
When this bit is set, the FIFO tail will increment by a
single message
Bit 7 – TXEN TX/RX Buffer Selection
Value
Description
1
Transmits message object
0
Receives message object
Bit 6 – RTREN Auto-Remove Transmit (RTR) Enable
Value
Description
1
When a Remote Transmit is received, TXREQ will be set
0
When a Remote Transmit is received, TXREQ will be unaffected
Bit 5 – RXTSEN Received Message Timestamp Enable(3)
Value
Description
1
Captures timestamp in a received message object in RAM
0
Does not capture time stamp
Bit 4 – TXATIE Transmit Attempts Exhausted Interrupt Enable
Value
Description
1
Enables interrupt
0
Disables interrupt
Bit 3 – RXOVIE Overflow Interrupt Enable
Value
Description
1
Interrupt is enabled for overflow event
0
Interrupt is disabled for overflow event
Bit 2 – TFERFFIE Transmit/Receive FIFO Empty/Full Interrupt Enable
Value
Condition
1
TXEN = 1 (FIFO configured as a transmit FIFO)
0
TXEN = 1 (FIFO configured as a transmit FIFO)
1
TXEN = 0 (FIFO configured as a receive FIFO)
0
TXEN = 0 (FIFO configured as a receive FIFO)
Description
Interrupt is enabled for FIFO empty
Interrupt is disabled for FIFO empty
Interrupt is enabled for FIFO full
Interrupt is disabled for FIFO full
Bit 1 – TFHRFHIE Transmit/Receive FIFO Half Empty/Half Full Interrupt Enable
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
Value
1
0
1
0
Condition
TXEN = 1 (FIFO configured as a transmit FIFO)
TXEN = 1 (FIFO configured as a transmit FIFO)
TXEN = 0 (FIFO configured as a receive FIFO)
TXEN = 0 (FIFO configured as a receive FIFO)
Description
Interrupt is enabled for FIFO half empty
Interrupt is disabled for FIFO half empty
Interrupt is enabled for FIFO half full
Interrupt is disabled for FIFO half full
Bit 0 – TFNRFNIE Transmit/Receive FIFO Not Full/Not Empty Interrupt Enable
Value
Condition
Description
1
TXEN = 1 (FIFO configured as a transmit FIFO)
Interrupt is enabled for FIFO not full
0
TXEN = 1 (FIFO configured as a transmit FIFO)
Interrupt is disabled for FIFO not full
1
TXEN = 0 (FIFO configured as a receive FIFO)
Interrupt is enabled for FIFO not empty
0
TXEN = 0 (FIFO configured as a receive FIFO)
Interrupt is disabled for FIFO not empty
Notes:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxFIFOCONyT: Accesses the top byte FIFOCONy[31:24]
– CxFIFOCONyU: Accesses the upper byte FIFOCONy[23:16]
– CxFIFOCONyH: Accesses the high byte FIFOCONy[15:8]
– CxFIFOCONyL: Accesses the low byte FIFOCONy[7:0]
2. [y] denotes FIFO number, from 1 to 3.
3. These bits can only be modified in Configuration mode (OPMOD[2:0] = 100).
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 859
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
38.13.25 CxFIFOSTAy
Name:
Address:
CxFIFOSTAy
0x00
CAN FIFO y Status Register
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
9
8
[R
0
[R
0
10
FIFOCI[4:0]
[R
0
[R
0
[R
0
4
TXATIF
HS/C
0
3
RXOVIF
HS/C
0
2
TFERFFIF
R
0
1
TFHRFHIF
R
0
0
TFNRFNIF
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
7
TXABT
R
0
6
TXLARB
R
0
5
TXERR
R
0
Bits 12:8 – FIFOCI[4:0] FIFO Message Index(3)
Condition
Description
TXEN = 1(FIFO configured as a
A read of this register will return an index to the message that the FIFO will
next attempt to transmit
transmit buffer)
TXEN = 0(FIFO configured as a
A read of this register will return an index to the message that the FIFO will
use to save the next message
receive buffer)
Bit 7 – TXABT Message Aborted Status(5)
Value
Description
1
Message was aborted
0
Message completed successfully
Bit 6 – TXLARB Message Lost Arbitration Status(4)
Value
Description
1
Message lost arbitration while being sent
0
Message did not lose arbitration while being sent
Bit 5 – TXERR Error Detected During Transmission(4)
Value
Description
1
A bus error occurred while the message was being sent
0
A bus error did not occur while the message was being sent
Bit 4 – TXATIF Transmit Attempts Exhausted Interrupt Pending
Value
Condition
1
TXEN = 1(FIFO configured as a transmit buffer)
0
TXEN = 1(FIFO configured as a transmit buffer)
x
TXEN = 0(FIFO configured as a receive buffer)
Description
Interrupt is pending
Interrupt is not pending
Unused, reads as ‘0’
Bit 3 – RXOVIF Receive FIFO Overflow Interrupt Flag
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 860
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
Value
x
1
0
Condition
TXEN = 1(FIFO configured as a transmit buffer)
TXEN = 0(FIFO configured as a receive buffer)
TXEN = 0(FIFO configured as a receive buffer)
Description
Unused, reads as ‘0’
Overflow event has occurred
No overflow event occurred
Bit 2 – TFERFFIF Transmit/Receive FIFO Empty/Full Interrupt Flag
Value
Condition
Description
1
TXEN = 1(FIFO configured as a transmit buffer) FIFO is empty
0
TXEN = 1(FIFO configured as a transmit buffer) FIFO is not empty, at least one message is queued to
be transmitted
1
TXEN = 0(FIFO configured as a receive buffer) FIFO is full
0
TXEN = 0(FIFO configured as a receive buffer) FIFO is not full
Bit 1 – TFHRFHIF Transmit/Receive FIFO Half Empty/Half Full Interrupt Flag
Value
Condition
Description
1
TXEN = 1(FIFO configured as a transmit buffer)
FIFO is less than or equal to half full
0
TXEN = 1(FIFO configured as a transmit buffer)
FIFO is greater than half full
1
TXEN = 0(FIFO configured as a receive buffer)
FIFO is greater than or equal to half full
0
TXEN = 0(FIFO configured as a receive buffer)
FIFO is less than half full
Bit 0 – TFNRFNIF Transmit/Receive FIFO Not Full/Not Empty Interrupt Flag
Value
Condition
Description
1
TXEN = 1(FIFO configured as a transmit buffer)
FIFO is not full
0
TXEN = 1(FIFO configured as a transmit buffer)
FIFO is full
1
TXEN = 0(FIFO configured as a receive buffer)
FIFO is not empty, has at least one message
0
TXEN = 0(FIFO configured as a receive buffer)
FIFO is empty
Notes:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxFIFOSTAyT: Accesses the top byte FIFOSTAy[31:24]
– CxFIFOSTAyU: Accesses the upper byte FIFOSTAy[23:16]
– CxFIFOSTAyH: Accesses the high byte FIFOSTAy[15:8]
– CxFIFOSTAyL: Accesses the low byte FIFOSTAy[7:0]
2. [y] denotes FIFO number, from 1 to 3.
3. FIFOCI[4:0] gives a zero-indexed value to the message in the FIFO. If the FIFO is four message deep (FSIZE
= 3), FIFOCIx will take on a value of 0 to 3, depending on the state of the FIFO.
4. This bit is updated when a message completes (or aborts) or when the FIFO is reset.
5. This bit is reset on any read of this register or when the TXQ is reset.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 861
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
38.13.26 CxFIFOUAy
Name:
Address:
CxFIFOUAy
0x00
CAN FIFO y User Address Register
Bit
31
30
29
28
27
FIFOUA[31:24]
R
R
x
x
26
25
24
Access
Reset
R
x
R
x
R
x
R
x
R
x
R
x
Bit
23
22
21
18
17
16
R
x
20
19
FIFOUA[23:16]
R
R
x
x
Access
Reset
R
x
R
x
R
x
R
x
R
x
Bit
15
14
13
12
11
10
9
8
R
x
R
x
R
x
R
x
3
2
1
0
R
x
R
x
R
x
R
x
FIFOUA[15:8]
Access
Reset
R
x
R
x
R
x
R
x
Bit
7
6
5
4
FIFOUA[7:0]
Access
Reset
R
x
R
x
R
x
R
x
Bits 31:0 – FIFOUA[31:0] FIFO User Address bits
Condition
Description
TXEN = 1 (FIFO configured as transmit A read of this register will return the address where the next message is
to be written (FIFO head)
buffer
TXEN = 0 (FIFO configured as receive
A read of the register will return the address where the next message is
to be read (FIFO tail)
buffer
Notes:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxFIFOCONyT: Accesses the top byte FIFOCONy[31:24]
– CxFIFOCONyU: Accesses the upper byte FIFOCONy[23:16]
– CxFIFOCONyH: Accesses the high byte FIFOCONy[15:8]
– CxFIFOCONyL: Accesses the low byte FIFOCONy[7:0]
2. [y] denotes FIFO number, from 1 to 3.
3. This register is not ensured to read correctly in Configuration mode and needs to only be accessed when the
module is not in Configuration mode.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 862
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
38.13.27 CxFLTCON0
Name:
Address:
CxFLTCON0
0x0180
CAN Filter Control Register 0
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
FLTEN3
R/W
0
30
23
FLTEN2
R/W
0
22
15
FLTEN1
R/W
0
14
7
FLTEN0
R/W
0
6
29
21
13
5
28
27
R/W
0
R/W
0
20
19
R/W
0
R/W
0
12
11
R/W
0
R/W
0
4
3
R/W
0
R/W
0
26
F3BP[4:0]
R/W
0
18
F2BP[4:0]
R/W
0
10
F1BP[4:0]
R/W
0
2
F0BP[4:0]
R/W
0
25
24
R/W
0
R/W
0
17
16
R/W
0
R/W
0
9
8
R/W
0
R/W
0
1
0
R/W
0
R/W
0
Bit 31 – FLTEN3 Enable Filter 3 to Accept Messages
Value
Description
1
Filter is enabled
0
Filter is disabled
Bits 28:24 – F3BP[4:0] Pointer to FIFO when Filter 3 Hits
Value
Description
11111-00 Reserved
100
00011
Message matching filter is stored in FIFO 3
00010
Message matching filter is stored in FIFO 2
00001
Message matching filter is stored in FIFO 1
00000
Reserved, FIFO 0 is the TX Queue and cannot receive messages
Bit 23 – FLTEN2 Enable Filter 2 to Accept Messages
Value
Description
1
Filter is enabled
0
Filter is disabled
Bits 20:16 – F2BP[4:0] Pointer to FIFO when Filter 2 Hits
Value
Description
11111-00 Reserved
100
00011
Message matching filter is stored in FIFO 3
00010
Message matching filter is stored in FIFO 2
00001
Message matching filter is stored in FIFO 1
00000
Reserved, FIFO 0 is the TX Queue and cannot receive messages
Bit 15 – FLTEN1 Enable Filter 1 to Accept Messages
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 863
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
Value
1
0
Description
Filter is enabled
Filter is disabled
Bits 12:8 – F1BP[4:0] Pointer to FIFO when Filter 1 Hits
Value
Description
11111-00 Reserved
100
00011
Message matching filter is stored in FIFO 3
00010
Message matching filter is stored in FIFO 2
00001
Message matching filter is stored in FIFO 1
00000
Reserved, FIFO 0 is the TX Queue and cannot receive messages
Bit 7 – FLTEN0 Enable Filter 0 to Accept Messages
Value
Description
1
Filter is enabled
0
Filter is disabled
Bits 4:0 – F0BP[4:0] Pointer to FIFO when Filter 0 Hits
Value
Description
11111-00 Reserved
100
00011
Message matching filter is stored in FIFO 3
00010
Message matching filter is stored in FIFO 2
00001
Message matching filter is stored in FIFO 1
00000
Reserved, FIFO 0 is the TX Queue and cannot receive messages
Note:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxFLTCON0T: Accesses the top byte FLTCON0[31:24]
– CxFLTCON0U: Accesses the upper byte FLTCON0[23:16]
– CxFLTCON0H: Accesses the high byte FLTCON0[15:8]
– CxFLTCON0L: Accesses the low byte FLTCON0[7:0]
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 864
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
38.13.28 CxFLTCON1
Name:
Address:
CxFLTCON1
0x0184
CAN Filter Control Register 1
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
FLTEN7
R/W
0
30
23
FLTEN6
R/W
0
22
15
FLTEN5
R/W
0
14
7
FLTEN4
R/W
0
6
29
21
13
5
28
27
R/W
0
R/W
0
20
19
R/W
0
R/W
0
12
11
R/W
0
R/W
0
4
3
R/W
0
R/W
0
26
F7BP[4:0]
R/W
0
18
F6BP[4:0]
R/W
0
10
F5BP[4:0]
R/W
0
2
F4BP[4:0]
R/W
0
25
24
R/W
0
R/W
0
17
16
R/W
0
R/W
0
9
8
R/W
0
R/W
0
1
0
R/W
0
R/W
0
Bit 31 – FLTEN7 Enable Filter 7 to Accept Messages
Value
Description
1
Filter is enabled
0
Filter is disabled
Bits 28:24 – F7BP[4:0] Pointer to FIFO when Filter 7 Hits
Value
Description
11111-00 Reserved
100
00011
Message matching filter is stored in FIFO 3
00010
Message matching filter is stored in FIFO 2
00001
Message matching filter is stored in FIFO 1
00000
Reserved, FIFO 0 is the TX Queue and cannot receive messages
Bit 23 – FLTEN6 Enable Filter 6 to Accept Messages
Value
Description
1
Filter is enabled
0
Filter is disabled
Bits 20:16 – F6BP[4:0] Pointer to FIFO when Filter 6 Hits
Value
Description
11111-00 Reserved
100
00011
Message matching filter is stored in FIFO 3
00010
Message matching filter is stored in FIFO 2
00001
Message matching filter is stored in FIFO 1
00000
Reserved, FIFO 0 is the TX Queue and cannot receive messages
Bit 15 – FLTEN5 Enable Filter 5 to Accept Messages
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 865
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
Value
1
0
Description
Filter is enabled
Filter is disabled
Bits 12:8 – F5BP[4:0] Pointer to FIFO when Filter 5 Hits
Value
Description
11111-00 Reserved
100
00011
Message matching filter is stored in FIFO 3
00010
Message matching filter is stored in FIFO 2
00001
Message matching filter is stored in FIFO 1
00000
Reserved, FIFO 0 is the TX Queue and cannot receive messages
Bit 7 – FLTEN4 Enable Filter 4 to Accept Messages
Value
Description
1
Filter is enabled
0
Filter is disabled
Bits 4:0 – F4BP[4:0] Pointer to FIFO when Filter 4 Hits
Value
Description
11111-00 Reserved
100
00011
Message matching filter is stored in FIFO 3
00010
Message matching filter is stored in FIFO 2
00001
Message matching filter is stored in FIFO 1
00000
Reserved, FIFO 0 is the TX Queue and cannot receive messages
Note:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxFLTCON1T: Accesses the top byte FLTCON1[31:24]
– CxFLTCON1U: Accesses the upper byte FLTCON1[23:16]
– CxFLTCON1H: Accesses the high byte FLTCON1[15:8]
– CxFLTCON1L: Accesses the low byte FLTCON1[7:0]
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 866
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
38.13.29 CxFLTCON2
Name:
Address:
CxFLTCON2
0x0188
CAN Filter Control Register 2
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
FLTEN11
R/W
0
30
23
FLTEN10
R/W
0
22
15
FLTEN9
R/W
0
14
7
FLTEN8
R/W
0
6
29
21
13
5
28
27
R/W
0
R/W
0
20
19
R/W
0
R/W
0
12
11
R/W
0
R/W
0
4
3
R/W
0
R/W
0
26
F11BP[4:0]
R/W
0
18
F10BP[4:0]
R/W
0
10
F9BP[4:0]
R/W
0
2
F8BP[4:0]
R/W
0
25
24
R/W
0
R/W
0
17
16
R/W
0
R/W
0
9
8
R/W
0
R/W
0
1
0
R/W
0
R/W
0
Bit 31 – FLTEN11 Enable Filter 11 to Accept Messages
Value
Description
1
Filter is enabled
0
Filter is disabled
Bits 28:24 – F11BP[4:0] Pointer to FIFO when Filter 11 Hits
Value
Description
11111-00 Reserved
100
00011
Message matching filter is stored in FIFO 3
00010
Message matching filter is stored in FIFO 2
00001
Message matching filter is stored in FIFO 1
00000
Reserved, FIFO 0 is the TX Queue and cannot receive messages
Bit 23 – FLTEN10 Enable Filter 10 to Accept Messages
Value
Description
1
Filter is enabled
0
Filter is disabled
Bits 20:16 – F10BP[4:0] Pointer to FIFO when Filter 10 Hits
Value
Description
11111-00 Reserved
100
00011
Message matching filter is stored in FIFO 3
00010
Message matching filter is stored in FIFO 2
00001
Message matching filter is stored in FIFO 1
00000
Reserved, FIFO 0 is the TX Queue and cannot receive messages
Bit 15 – FLTEN9 Enable Filter 9 to Accept Messages
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
Value
1
0
Description
Filter is enabled
Filter is disabled
Bits 12:8 – F9BP[4:0] Pointer to FIFO when Filter 9 Hits
Value
Description
11111-00 Reserved
100
00011
Message matching filter is stored in FIFO 3
00010
Message matching filter is stored in FIFO 2
00001
Message matching filter is stored in FIFO 1
00000
Reserved, FIFO 0 is the TX Queue and cannot receive messages
Bit 7 – FLTEN8 Enable Filter 8 to Accept Messages
Value
Description
1
Filter is enabled
0
Filter is disabled
Bits 4:0 – F8BP[4:0] Pointer to FIFO when Filter 8 Hits
Value
Description
11111-00 Reserved
100
00011
Message matching filter is stored in FIFO 3
00010
Message matching filter is stored in FIFO 2
00001
Message matching filter is stored in FIFO 1
00000
Reserved, FIFO 0 is the TX Queue and cannot receive messages
Note:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxFLTCON2T: Accesses the top byte FLTCON2[31:24]
– CxFLTCON2U: Accesses the upper byte FLTCON2[23:16]
– CxFLTCON2H: Accesses the high byte FLTCON2[15:8]
– CxFLTCON2L: Accesses the low byte FLTCON2[7:0]
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 868
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
38.13.30 CxFLTOBJy
Name:
Address:
CxFLTOBJy
0x00
CAN Filter y Object Register
Bit
31
Access
Reset
Bit
23
30
EXIDE
R/W
0
29
SID11
R/W
0
28
27
25
24
R/W
0
26
EID[17:13]
R/W
0
R/W
0
R/W
0
R/W
0
22
21
20
19
18
17
16
EID[12:5]
Access
Reset
Bit
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
12
11
10
R/W
0
R/W
0
R/W
0
R/W
0
9
SID[10:8]
R/W
0
8
R/W
0
13
EID[4:0]
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
SID[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit 30 – EXIDE Extended Identifier Enable
Value
Condition
Description
1
MIDE = 1
Matches only messages with Extended Identifier addresses
0
MIDE = 1
Matches only messages with Standard Identifier addresses
x
MIDE = 0
Reserved
Bit 29 – SID11 12th bit of Standard Identifier Filter
Bits 28:11 – EID[17:0] Extended Identifier Filter
In DeviceNet™ mode, these are the filter its for the first two data bytes
Bits 10:0 – SID[10:0] Standard Identifier Filter
Notes:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxFLTOBJyT: Accesses the top byte FLTOBJy[31:24]
– CxFLTOBJyU: Accesses the upper byte FLTOBJy[23:16]
– CxFLTOBJyH: Accesses the high byte FLTOBJy[15:8]
– CxFLTOBJyL: Accesses the low byte FLTOBJy[7:0]
2. [y] denotes Filter number, from 0 to 11.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
38.13.31 CxMASKy
Name:
Address:
CxMASKy
0x00
CAN Mask y Register
Bit
31
Access
Reset
Bit
23
30
MIDE
R/W
0
29
MSID11
R/W
0
28
27
25
24
R/W
0
26
MEID[17:13]
R/W
0
R/W
0
R/W
0
R/W
0
22
21
20
19
18
17
16
MEID[12:5]
Access
Reset
Bit
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
12
11
10
R/W
0
R/W
0
R/W
0
R/W
0
9
MSID[10:8]
R/W
0
8
R/W
0
13
MEID[4:0]
R/W
0
R/W
0
7
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
MSID[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bit 30 – MIDE Identifier Receive Mode
Value
Description
1
Matches only message types (standard or extended address) that correspond to the EXIDE bit of in the
filter
0
Matches either standard or extended address message if filters match (i.e., if (Filter SID) = (Message
SID) or if (Filter SID/EID) = (Message SID/EID))
Bit 29 – MSID11 12th bit of Standard Identifier Mask
Bits 28:11 – MEID[17:0] Extended Identifier Mask
In DeviceNet™ mode, these are the mask bits for the first two data bytes
Bits 10:0 – MSID[10:0] Standard Identifier Mask
Notes:
1. The individual bytes in this multibyte register can be accessed with the following register names:
– CxMASKyT: Accesses the top byte MASKy[31:24]
– CxMASKyU: Accesses the upper byte MASKy[23:16]
– CxMASKyH: Accesses the high byte MASKy[15:8]
– CxMASKyL: Accesses the low byte MASKy[7:0]
2. Each Mask is associated with a filter,[y] denotes Filter number, from 0 to 11.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 870
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
38.14
Register Summary - CAN FD
Address
Name
0x00
...
0xFF
Reserved
0x0100
C1CON
0x0104
C1NBTCFG
0x0108
0x010C
C1DBTCFG
C1TDC
0x0110
C1TBC
0x0114
C1TSCON
0x0118
0x011C
0x0120
0x0124
0x0128
0x012C
0x0130
C1VEC
C1INT
C1RXIF
C1TXIF
C1RXOVIF
C1TXATIF
C1TXREQ
Bit Pos.
7
6
5
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
CLKSEL
ON
PXEDIS
ISOCRCEN
SIDL
OPMOD[2:0]
TXBWS[3:0]
4
3
BRSDIS
TXQEN
BUSY
STEF
ABAT
SJW[6:0]
TSEG2[6:0]
TSEG1[7:0]
BRP[7:0]
2
1
DNCNT[4:0]
WFT[1:0]
SERRLOM
ESIGM
REQOP[2:0]
0
WAKFIL
RTXAT
SJW[3:0]
TSEG2[3:0]
TSEG1[4:0]
BRP[7:0]
TDCV[5:0]
TDCO[6:0]
TDCMOD[1:0]
EDGFLTEN
SID11EN
TBC[7:0]
TBC[15:8]
TBC[23:16]
TBC[31:24]
TBCPRE[7:0]
TSRES
TBCPRE[9:8]
TSEOF
TBCEN
ICODE[6:0]
FILHIT[4:0]
IVMIF
WAKIF
CERRIF
IVMIE
WAKIE
CERRIE
© 2021 Microchip Technology Inc.
TEFIF
SERRIF
TEFIE
SERRIE
TXCODE[6:0]
RXCODE[6:0]
MODIF
RXOVIF
MODIE
RXOVIE
TBCIF
TXATIF
TBCIE
TXATIE
RFIF[2:0]
RXIF
TXIF
RXIE
TXIE
TFIF[3:0]
RFOVIF[2:0]
TFATIF[3:0]
TXREQ[3:0]
Preliminary Datasheet
DS40002213D-page 871
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
...........continued
Address
Name
0x0134
C1TREC
0x0138
C1BDIAG0
0x013C
C1BDIAG1
0x0140
0x0144
C1TEFCON
C1TEFSTA
0x0148
C1TEFUA
0x014C
C1FIFOBA
0x0150
C1TXQCON
0x0154
C1TXQSTA
0x0158
C1TXQUA
0x015C
C1FIFOCON1
0x0160
C1FIFOSTA1
0x0164
C1FIFOUA1
0x0168
C1FIFOCON2
Bit Pos.
7
6
5
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
4
3
2
1
0
TXWARN
RXWARN
EWARN
NACKERR
NBIT1ERR
DBIT1ERR
TEFHIE
NBIT0ERR
DBIT0ERR
TEFNEIE
UINC
TEFHIF
TEFNEIF
TXREQ
TXQNIE
UINC
RERRCNT[7:0]
TERRCNT[7:0]
TXBO
TXBOERR
DLCMM
ESI
NCRCERR
DCRCERR
TEFTSEN
TXBP
RXBP
NRERRCNT[7:0]
NTERRCNT[7:0]
DRERRCNT[7:0]
DTERRCNT[7:0]
EFMSGCNT[7:0]
EFMSGCNT[15:8]
NSTUFERR NFORMERR
DSTUFERR DFORMERR
TEFOVIE
TEFOVIF
TEFUA[7:0]
TEFUA[15:8]
TEFUA[23:16]
TEFUA[31:24]
FIFOBA[7:0]
FIFOBA[15:8]
FIFOBA[23:16]
FIFOBA[31:24]
TXATIE
TXEN
TXABT
TXEN
TXABT
TXEN
© 2021 Microchip Technology Inc.
TXAT[1:0]
PLSIZE[2:0]
TXLARB
TXERR
RTREN
RXTSEN
TXAT[1:0]
PLSIZE[2:0]
TXLARB
TXERR
RTREN
RXTSEN
TXATIF
TXQUA[7:0]
TXQUA[15:8]
TXQUA[23:16]
TXQUA[31:24]
TXATIE
RXOVIE
TXATIF
RXOVIF
FIFOUA[7:0]
FIFOUA[15:8]
FIFOUA[23:16]
FIFOUA[31:24]
TXATIE
RXOVIE
TXAT[1:0]
PLSIZE[2:0]
Preliminary Datasheet
TEFFIE
FRESET
FSIZE[4:0]
TEFFIF
TXQEIE
FRESET
TXPRI[4:0]
FSIZE[4:0]
TXQEIF
TXQCI[4:0]
TXQNIF
TFERFFIE
FRESET
TXPRI[4:0]
FSIZE[4:0]
TFERFFIF
FIFOCI[4:0]
TFHRFHIE
TXREQ
TFNRFNIE
UINC
TFHRFHIF
TFNRFNIF
TFERFFIE
FRESET
TXPRI[4:0]
FSIZE[4:0]
TFHRFHIE
TXREQ
TFNRFNIE
UINC
DS40002213D-page 872
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
...........continued
Address
Name
0x016C
C1FIFOSTA2
0x0170
C1FIFOUA2
0x0174
C1FIFOCON3
0x0178
C1FIFOSTA3
0x017C
C1FIFOUA3
0x0180
C1FLTCON0
0x0184
C1FLTCON1
0x0188
C1FLTCON2
0x018C
C1FLTOBJ0
0x0190
0x0194
0x0198
0x019C
0x01A0
C1MASK0
C1FLTOBJ1
C1MASK1
C1FLTOBJ2
C1MASK2
Bit Pos.
7
6
5
4
3
2
1
0
7:0
15:8
TXABT
TXLARB
TXERR
TXATIF
RXOVIF
TFERFFIF
FIFOCI[4:0]
TFHRFHIF
TFNRFNIF
TFERFFIE
FRESET
TXPRI[4:0]
FSIZE[4:0]
TFERFFIF
FIFOCI[4:0]
TFHRFHIE
TXREQ
TFNRFNIE
UINC
TFHRFHIF
TFNRFNIF
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
TXEN
TXABT
RTREN
RXTSEN
TXAT[1:0]
PLSIZE[2:0]
TXLARB
TXERR
FIFOUA[7:0]
FIFOUA[15:8]
FIFOUA[23:16]
FIFOUA[31:24]
TXATIE
RXOVIE
TXATIF
RXOVIF
FIFOUA[7:0]
FIFOUA[15:8]
FIFOUA[23:16]
FIFOUA[31:24]
FLTEN0
FLTEN1
FLTEN2
FLTEN3
FLTEN4
FLTEN5
FLTEN6
FLTEN7
FLTEN8
FLTEN9
FLTEN10
FLTEN11
© 2021 Microchip Technology Inc.
F0BP[4:0]
F1BP[4:0]
F2BP[4:0]
F3BP[4:0]
F4BP[4:0]
F5BP[4:0]
F6BP[4:0]
F7BP[4:0]
F8BP[4:0]
F9BP[4:0]
F10BP[4:0]
F11BP[4:0]
SID[7:0]
EID[4:0]
SID[10:8]
EID[12:5]
EXIDE
SID11
EID[17:13]
MSID[7:0]
MEID[4:0]
MSID[10:8]
MEID[12:5]
MIDE
MSID11
MEID[17:13]
SID[7:0]
EID[4:0]
SID[10:8]
EID[12:5]
EXIDE
SID11
EID[17:13]
MSID[7:0]
MEID[4:0]
MSID[10:8]
MEID[12:5]
MIDE
MSID11
MEID[17:13]
SID[7:0]
EID[4:0]
SID[10:8]
EID[12:5]
EXIDE
SID11
EID[17:13]
MSID[7:0]
MEID[4:0]
MSID[10:8]
MEID[12:5]
MIDE
MSID11
Preliminary Datasheet
MEID[17:13]
DS40002213D-page 873
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
...........continued
Address
Name
0x01A4
C1FLTOBJ3
0x01A8
0x01AC
0x01B0
0x01B4
0x01B8
0x01BC
0x01C0
0x01C4
0x01C8
0x01CC
0x01D0
0x01D4
0x01D8
C1MASK3
C1FLTOBJ4
C1MASK4
C1FLTOBJ5
C1MASK5
C1FLTOBJ6
C1MASK6
C1FLTOBJ7
C1MASK7
C1FLTOBJ8
C1MASK8
C1FLTOBJ9
C1MASK9
Bit Pos.
7
6
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
© 2021 Microchip Technology Inc.
5
4
3
2
1
0
SID[7:0]
EID[4:0]
SID[10:8]
EID[12:5]
EXIDE
SID11
EID[17:13]
MSID[7:0]
MEID[4:0]
MSID[10:8]
MEID[12:5]
MIDE
MSID11
MEID[17:13]
SID[7:0]
EID[4:0]
SID[10:8]
EID[12:5]
EXIDE
SID11
EID[17:13]
MSID[7:0]
MEID[4:0]
MSID[10:8]
MEID[12:5]
MIDE
MSID11
MEID[17:13]
SID[7:0]
EID[4:0]
SID[10:8]
EID[12:5]
EXIDE
SID11
EID[17:13]
MSID[7:0]
MEID[4:0]
MSID[10:8]
MEID[12:5]
MIDE
MSID11
MEID[17:13]
SID[7:0]
EID[4:0]
SID[10:8]
EID[12:5]
EXIDE
SID11
EID[17:13]
MSID[7:0]
MEID[4:0]
MSID[10:8]
MEID[12:5]
MIDE
MSID11
MEID[17:13]
SID[7:0]
EID[4:0]
SID[10:8]
EID[12:5]
EXIDE
SID11
EID[17:13]
MSID[7:0]
MEID[4:0]
MSID[10:8]
MEID[12:5]
MIDE
MSID11
MEID[17:13]
SID[7:0]
EID[4:0]
SID[10:8]
EID[12:5]
EXIDE
SID11
EID[17:13]
MSID[7:0]
MEID[4:0]
MSID[10:8]
MEID[12:5]
MIDE
MSID11
MEID[17:13]
SID[7:0]
EID[4:0]
SID[10:8]
EID[12:5]
EXIDE
SID11
EID[17:13]
MSID[7:0]
MEID[4:0]
MSID[10:8]
MEID[12:5]
MIDE
MSID11
Preliminary Datasheet
MEID[17:13]
DS40002213D-page 874
PIC18F27/47/57Q84
CAN FD - Controller Area Network, Flexible ...
...........continued
Address
Name
0x01DC
C1FLTOBJ10
0x01E0
0x01E4
0x01E8
C1MASK10
C1FLTOBJ11
C1MASK11
Bit Pos.
7
6
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
© 2021 Microchip Technology Inc.
5
4
3
2
1
0
SID[7:0]
EID[4:0]
SID[10:8]
EID[12:5]
EXIDE
SID11
EID[17:13]
MSID[7:0]
MEID[4:0]
MSID[10:8]
MEID[12:5]
MIDE
MSID11
MEID[17:13]
SID[7:0]
EID[4:0]
SID[10:8]
EID[12:5]
EXIDE
SID11
EID[17:13]
MSID[7:0]
MEID[4:0]
MSID[10:8]
MEID[12:5]
MIDE
MSID11
Preliminary Datasheet
MEID[17:13]
DS40002213D-page 875
PIC18F27/47/57Q84
JTAG Boundary Scan
JTAG Boundary Scan
As the complexity and density of board design increases, testing electrical connections between the components on
fully assembled circuit boards poses many challenges. To address these challenges, the Joint Test Action Group
(JTAG) developed a method for boundary scan testing that was later standardized as IEEE 1149.1-2001, “IEEE
Standard Test Access Port and Boundary Scan Architecture”.
The JTAG boundary scan method is the process of adding a Shift register stage adjacent to each of the component’s
I/O pins. This permits signals at the component boundaries to be controlled and observed, using a defined set of
scan test principles. An external tester or controller provides instructions and reads the results in a serial format. The
external device also provides common clock and control signals. Depending on the implementation, access to all test
signals is provided through a standardized 4-pin or 5-pin interface.
In system-level applications, individual JTAG enabled components are connected through their individual testing
interfaces (in addition to their more standard application-specific connections). Devices are connected in a series or
daisy-chained format, with the test output of one device connected exclusively to the test input of the next device in
the chain. Instructions in the JTAG boundary scan protocol allow the testing of any one device in the chain, or any
combination of devices, without testing the entire chain. In this method, connections between components, as well as
connections at the boundary of the application, may be tested.
A typical application incorporating the JTAG boundary scan interface is shown in Figure 39-1. In this example, a PIC
microcontroller is daisy-chained to a second JTAG compliant device. Note that the TDI line from the external tester
supplies data to the TDI pin of the first device in the chain (in this case, the microcontroller). The resulting test data
for this two-device chain is provided from the TDO pin of the second device to the TDO line of the tester. This section
describes the JTAG module and its general boundary scan use. The PIC18-Q84 JTAG module does not currently
support programming over JTAG.
Figure 39-1. Overview of PIC18F-Based JTAG Compliant Application Showing Daisy-Chaining of
Components
PIC18F-Based Application
TMS
TCK
TDO
TDI
PIC18F(or other
JTAG compliant
device)
TMS
TCK
JTAG
Controller
TDO
PIC18F
TDI
39.
Standard
JTAG Connector
TDI
TDO
TCK
TMS
TRST
(optional)
In PIC18-Q84 devices, hardware for the JTAG boundary scan is a Core Independent Peripheral (CIP) with additional
integrated logic in all I/O ports. A logical block diagram of the JTAG module is shown in Figure 39-2. It consists of the
following key elements:
•
•
•
•
TAP Interface Pins (TDI, TMS, TCK and TDO)
TAP Controller
Instruction Shift Register and Instruction Register (IR)
Data Registers
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 876
PIC18F27/47/57Q84
JTAG Boundary Scan
Figure 39-2. JTAG Logical Block Diagram
TDO
Output Data
Sampling
Register
Instruction Register
TMS
TCK
TDO Selector
(MUX)
Instruction Shift Register
TDI
Instruction Decode
TAP
Controller
Data Registers
Bypass Register
Device ID Registers
Data Selector
(MUX)
Boundary Scan Cell Registers
MCHP Scan Data
39.1
Test Access Port (TAP) and TAP Controller
39.1.1
TAP
The Test Access Port (TAP) on the PIC18-Q84 is a general-purpose port that provides test access to many built-in
support functions and test logic defined in IEEE Standard 1149.1. The TAP is disabled by programming the JTAGEN
bit in CONFIGx (the TAP, by default, is enabled in the bit’s unprogrammed state). While enabled, the designated I/O
pins become dedicated TAP pins. The PIC implements a 4-pin JTAG interface with these pins:
• TCK (Test Clock): Provides the clock for test logic.
• TMS (Test Mode Select): Input used by the TAP to control test operations.
• TDI (Test Data Input): Serial input for test instructions and data.
• TDO (Test Data Output): Serial output for test instructions and data.
To minimize I/O loss due to JTAG, the optional TAP Reset (TRST) input pin, specified in the standard, is not
implemented on PIC18-Q84 devices. For convenience, a “soft” TAP Reset has been included in the TAP controller,
using the TMS and TCK pins. To force a port Reset, apply a logic high to the TMS pin for at least five rising edges of
TCK. Note that device Resets (including POR) do not automatically result in a TAP Reset; this must be done by the
external JTAG controller using the soft TAP Reset.
39.1.2
TAP Controller
The TAP controller on PIC18-Q84 family devices is a synchronous finite state machine that implements the standard
16 states for JTAG. Figure 39-3 shows all the module states of the TAP controller. All Boundary Scan Test (BST)
instructions and test results are communicated through the TAP via the TDI pin in a serial format, Least Significant bit
first.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 877
PIC18F27/47/57Q84
JTAG Boundary Scan
Figure 39-3. TAP Controller Module State Diagram
Test-Logic
Reset
TMS = 0
Run-Test/Idle
TMS = 1
Select-DR-Scan
TMS = 1
TMS = 0
TMS = 1
TMS = 0
TMS = 1
Capture-DR
TMS = 0 TMS = 0
Capture-IR
TMS = 0
Shift-DR
TMS = 1
Exit-1-DR
Exit-1-IR
TMS = 0
TMS = 0
Pause-DR
TMS = 0
TMS = 0
Pause-IR
TMS = 1
TMS = 1
Exit-2-DR
TMS = 0
TMS = 1
Update-DR
TMS = 1
TMS = 0
Shift-IR
TMS = 1
TMS = 0
TMS = 1
Select-IR-Scan
Exit-2-IR
TMS = 1
Update-IR
TMS = 0
TMS = 1
TMS = 0
By manipulating the state of TMS and the clock pulses on TCK, the TAP controller can be moved through all of
the defined module states to capture, shift and update various instruction and/or data registers. Figure 39-3 shows
the state changes on TMS as the controller cycles through its state machine. Figure 39-4 shows the timing of TMS
and TCK while transitioning the controller through the appropriate module states for shifting in an instruction. In this
example, the sequence shown demonstrates how an instruction is read by the TAP controller. All TAP controller
states are entered on the rising edge of the TCK pin. In this example, the TAP controller starts in the Test-Logic Reset
state. Since the state of the TAP controller is dependent on the previous instruction, and therefore may be unknown,
it is good programming practice to begin in the Test-Logic Reset state.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 878
PIC18F27/47/57Q84
JTAG Boundary Scan
Figure 39-4. TAP State Transitions for Shifting in an Instruction
TCK
TMS
Instruction Da ta (LSB)
TDI
Run_Test
Idle
Sele ct_IR_Scan
Shift_IR
Update_IR
TAP
State
Sele ct_DR_Scan
Capture_IR
Exit_IR
Run_Test
Idle
TDO
(1)
Note
1:
2:
3:
(2)
(3)
TDO pin is always in a high-impedance state, until the first falling edge of TCK, in either the Shift_IR or Shift_DR
states.
TDO is no longer high-impedance; the initial state of the Instruction Register (IR) is shifted out on the falling edge of
TCK.
TDO returns to high-impedance again on the first falling edge of TCK in the Exit_IR state.
When TMS is asserted low on the next rising edge of TCK, the TAP controller will move into the Run-Test/Idle state.
On the next two rising edges of TCK, TMS is high; this moves the TAP controller to the Select-IR-Scan state.
On the next two rising edges of TCK, TMS is held low; this moves the TAP controller into the Shift-IR state. An
instruction is shifted into the Instruction Shift register via the TDI on the next four rising edges of TCK. After the TAP
controller enters this state, the TDO pin goes from a High-Impedance state to Active. The controller shifts out the
initial state of the Instruction Register (IR) on the TDO pin, on the falling edges of TCK, and continues to shift out the
contents of the Instruction Register while in the Shift-IR state. The TDO returns to the High-Impedance state on the
first falling edge of TCK upon exiting the Shift state.
On the next three rising edges of TCK, the TAP controller exits the Shift-IR state, updates the Instruction Register
and then moves back to the Run-Test/Idle state. Data, or another instruction, can now be shifted into the appropriate
Data or Instruction Register.
39.2
JTAG Registers
The JTAG module uses a number of registers of various sizes as part of its operation. In terms of bit count, most
of the JTAG registers are single-bit register cells, integrated into the I/O ports. Regardless of their location within
the module, none of the JTAG registers are located within the device data memory space, and cannot be directly
accessed by the user in normal operating modes.
39.2.1
Instruction Shift Register and Instruction Register
The Instruction Shift register is a 4-bit shift register used for selecting the actions to be performed and/or what
data registers to be accessed. Instructions are shifted in, Least Significant bit first, and then decoded. A list and
description of implemented instructions is given in JTAG Instructions.
39.2.2
Data Registers
Once an instruction is shifted in and updated into the Instruction register, the TAP controller places certain data
registers between the TDI and TDO pins. Additional data values can then be shifted into these data registers as
needed. The PIC18-Q84 device family supports two data registers:
© 2021 Microchip Technology Inc.
Preliminary Datasheet
DS40002213D-page 879
PIC18F27/47/57Q84
JTAG Boundary Scan
•
•
39.3
Bypass register: A single-bit register which allows the boundary scan test data to pass through the selected
device to adjacent devices. The Bypass register is placed between the TDI and TDO pins when the BYPASS
instruction is active.
Device ID Register: A 32-bit part identifier. It consists of an 11-bit manufacturer ID assigned by the IEEE (29h for
Microchip Technology), device part number and device revision identifier. When the IDCODE instruction is active,
the Device ID register is placed between the TDI and TDO pins. The device data ID is then shifted out onto the
TDO pin, on the next 32 falling edges of TCK, after the TAP controller is in the Shift-DR.
Boundary Scan Register (BSR)
The BSR is a large shift register that is comprised of all the I/O Boundary Scan Cells (BSCs), daisy-chained together
Figure 39-5. Each I/O pin has one BSC, each containing three BSC registers: An input cell, an output cell and a
control cell. When the SAMPLE/PRELOAD or EXTEST instructions are active, the BSR is placed between the TDI and
TDO pins, with the TDI pin as the input and the TDO pin as the output. The size of the BSR depends on the number
of I/O pins on the device. For example, the PIC18F57Q84 has 44 I/O pins. With three BSC registers for each of the
44 I/Os, this yields a Boundary Scan register length of 132 bits.
Figure 39-5. Daisy-Chained Boundary Scan Cell Registers on a PIC18F Microcontroller
BSC with Three Register Cells:
Input Cell (I)
Control Cell (C)
Output Cell (O)
I C O
I C O
I C O
O
C
I
O
C
I
I
C
O
PIC18F
Internal
Logic
I
C
O
O
C
I
I
C
O
TAP Controller
TDI
39.3.1
TMS
TCK
TDO
Boundary Scan Cell (BSC)
The function of the BSC is to capture and override I/O input or output data values when JTAG is active. The BSC
consists of three Single-Bit Capture register cells and two Single-Bit Holding register cells. The capture cells are
daisy-chained to capture the port’s input, output and control (output-enable) data, as well as pass JTAG data along
the Boundary Scan register. Command signals from the TAP controller determine if the port of JTAG data is captured,
and how and when it is clocked out of the BSC. The first register either captures internal data destined to the output
driver or provides serially scanned in data for the output driver. The second register captures internal output-enable
control from the output driver and also provides serially scanned in output-enable values. The third register captures
the input data from the I/O’s input buffer.
Figure 39-5 shows a typical BSC and its relationship to the I/O port’s structure.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
JTAG Boundary Scan
Figure 39-6. Boundary Scan Cell and Its Relationship to the I/O Port
Boundary Scan Cell
Port I/O Cell
JTAG Enable
JTAG Clocks
Capture
Update
Port Output
JTAG SDI from
Previous BSC
Output Buffer
O
Port
Output Data
C
Data Out
Enable
I/O Pin
Port Output
Enable from
Output Multiplexor
JTAG SDO
to Next BSC
I
Input Buffer
Port Input
39.4
JTAG Instructions
PIC18-Q84 family devices support the mandatory instruction set specified by IEEE 1149.1, as well as several optional
public instructions defined in the specification.
The mandatory JTAG instructions are:
• BYPASS (Fh): Used for bypassing a device in a test chain; this allows the testing of off-chip circuitry and
board-level interconnections.
• SAMPLE/PRELOAD (2h): Captures the I/O states of the component, providing a snapshot of its operation.
•
EXTEST (6h): Allows the external circuitry and interconnections to be tested, by either forcing various test
patterns on the output pins, or capturing test results from the input pins.
The optional JTAG instructions implemented in PIC18-Q84 devices are:
• IDCODE (1h): Causes the 32-bit device identification word to be shifted out on the TDO pin.
•
39.5
HIGHZ (0h): Places the device into a state in which all I/O pins are in a High-impedance state (driven inactive).
Boundary Scan Testing
Boundary Scan Testing (BST) is the method of controlling and observing the boundary pins of the JTAG compliant
device, like those of the PIC18-Q84 family, utilizing software control. BST can be used to test connectivity between
devices by daisy-chaining JTAG compliant devices to form a single scan chain. Several scan chains can exist on
a PCB to form multiple scan chains. These multiple scan chains can then be driven simultaneously to test many
components in parallel. Scan chains can contain both JTAG compliant devices and non-JTAG compliant devices.
A key advantage of BST is that it can be implemented without physical test probes; all that is needed is a 4-wire
or 5-wire interface and an appropriate test platform. Since JTAG boundary scan has been available for many years,
many software tools exist for testing scan chains without the need for extensive physical probing. The main drawback
to BST is that it can only evaluate digital signals and circuit continuity; it cannot measure input or output voltage
levels or currents.
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Preliminary Datasheet
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PIC18F27/47/57Q84
JTAG Boundary Scan
39.5.1
Related JTAG Files
To implement BST, all JTAG test tools will require a Boundary Scan Description Language (BSDL) file. BSDL is
a subset of VHDL (VHSIC Hardware Description Language), and is described as part of IEEE Std. 1149.1. The
device-specific BSDL file describes how the standard is implemented on a particular device and how it operates.
The BSDL file for a particular device includes the following:
• The pinout and package configuration for the particular device
• The physical location of the TAP pins
• The Device ID register and the device ID
• The length of the Instruction Register
• The supported BST instructions and their binary codes
• The length and structure of the Boundary Scan register
• The boundary scan cell definition
Device-specific BSDL files are available at Microchip’s web site, www.microchip.com. The name for each BSDL file is
the device name and silicon revision. For example, PIC18F57Q84_QFN.BSD, is the BSDL file for the PIC18F57Q84
in the QFN package.
39.6
Effects of Reset
The JTAG Boundary Scan module is affected by all device Reset sources. If a Reset source is triggered during a
boundary scan operation, the TAP controller state machine may reset and, therefore, the boundary scan operation
may exhibit unexpected and undesirable results. Hence, all potential device Resets need to be avoided while
performing a boundary scan operation.
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Preliminary Datasheet
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PIC18F27/47/57Q84
HLVD - High/Low-Voltage Detect
40.
HLVD - High/Low-Voltage Detect
The HLVD module can be configured to monitor the device voltage. This is useful in battery monitoring applications.
Complete control of the HLVD module is provided through the HLVDCON0 and HLVDCON1 registers.
Refer below for a simplified block diagram of the HLVD module.
Figure 40-1. HLVD Module Block Diagram
VDD
SEL
Rev. 10-000256B
2/5/2019
EN
OUT
Trigger/
Interrupt
Generation
+
RDY
EN
INTH
HLVDIF
INTL
Bandgap
Reference
Volatge
Since the HLVD can be software enabled through the EN bit, setting and clearing the enable bit does not produce a
false HLVD event glitch. Each time the HLVD module is enabled, the RDY bit can be used to detect when the module
is stable and ready to use.
The INTH and INTL bits determine the overall operation of the module. When INTH is set, the module monitors for
rises in VDD above the trip point set by the bits. When INTL is set, the module monitors for drops in VDD below the trip
point set by the SEL bits. When both the INTH and INTL bits are set, any changes above or below the trip point set
by the SEL bits can be monitored.
The OUT bit can be read to determine if the voltage is greater than or less than the selected trip point.
40.1
Operation
When the HLVD module is enabled, a comparator uses an internally generated voltage reference as the set point.
The set point is compared with the trip point, where each node in the resistor divider represents a trip point voltage.
The “trip point” voltage is the voltage level at which the device detects a high or low-voltage event, depending on the
configuration of the module.
When the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the internal
reference voltage generated by the voltage reference module. The comparator then generates an interrupt signal by
setting the HLVDIF bit.
The trip point voltage is software programmable using the SEL bits.
40.2
Setup
To set up the HLVD module:
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Preliminary Datasheet
DS40002213D-page 883
PIC18F27/47/57Q84
HLVD - High/Low-Voltage Detect
1.
2.
3.
4.
5.
Select the desired HLVD trip point by writing the value to the SEL bits.
Depending on the application to detect high-voltage peaks or low-voltage drops or both, set the INTH or INTL
bit appropriately.
Enable the HLVD module by setting the EN bit.
Clear the HLVD interrupt flag (HLVDIF), which may have been set from a previous interrupt.
If interrupts are desired, enable the HLVD interrupt by setting the HLVDIE and GIE bits.
An interrupt will not be generated until the RDY bit is set.
Important: Before changing any module settings (interrupts and tripping point), first disable the
module (EN = 0), make the changes and re-enable the module. This prevents the generation of
false HLVD events.
40.3
Current Consumption
When the module is enabled, the HLVD comparator and voltage divider are enabled and consume static current. The
total current consumption, when enabled, is specified in the “Electrical Specification” chapter.
Depending on the application, the HLVD module does not need to operate constantly. To reduce the current
consumption, the module can disabled when not in use. Refer to the “PMD - Peripheral Module Disable” chapter
for more details.
40.4
HLVD Start-up Time
If the HLVD or other circuits using the internal voltage reference are disabled to lower the device’s current
consumption, the reference voltage circuit will require time to become stable before a Low or High-voltage condition
can be reliably detected. This start-up time, TFVRST, is an interval that is independent of device clock speed. It is
specified in electrical specification section of the device specific data sheet.
The HLVD interrupt flag is not enabled until TFVRST has expired and a stable reference voltage is reached. For this
reason, brief excursions beyond the set point may not be detected during this interval (see the figures below).
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
HLVD - High/Low-Voltage Detect
Figure 40-2. Low-Voltage Detect Operation (INTL = 1)
Rev. 30-000141A
5/26/2017
CASE 1:
HLVDIF may not be Set
VDD
VHLVD
HLVDIF
EN
TFVRST
RDY
Band Gap Reference Voltage is Stable
CASE 2:
HLVDIF Cleared in Software
VDD
VHLVD
HLVDIF
EN
RDY
TFVRST
Band Gap Reference Voltage is Stable
HLVDIF Cleared in Software
HLVDIF Cleared in Software,
HLVDIF Remains Set since HLVD Condition still Exists
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Preliminary Datasheet
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PIC18F27/47/57Q84
HLVD - High/Low-Voltage Detect
Figure 40-3. High-Voltage Detect Operation (INTH = 1)
Rev. 30-000142A
5/26/2017
CASE 1:
HLVDIF may not be Set
VHLVD
VDD
HLVDIF
EN
TIRVST
RDY
HLVDIF Cleared in Software
Band Gap Reference Voltage is Stable
CASE 2:
VHLVD
VDD
HLVDIF
EN
TIRVST
RDY
Band Gap Reference Voltage is Stable
HLVDIF Cleared in Software
HLVDIF Cleared in Software,
HLVDIF Remains Set since HLVD Condition still Exists
40.5
Applications
In many applications, it is desirable to detect a drop below, or rise above, a particular voltage threshold. For
example, the HLVD module can be periodically enabled to detect Universal Serial Bus (USB) attach or detach. This
assumes the device is powered by a lower voltage source than the USB when detached. An attach would indicate a
High-Voltage Detect from, for example, 3.3V to 5V (the voltage on USB) and vice versa for a detach. This feature can
save a design a few extra components and an attach signal (input pin).
For general battery applications, the figure below shows a possible voltage curve. Over time, the device voltage
decreases. When the device voltage reaches voltage, VA, the HLVD logic generates an interrupt at time, TA. The
interrupt can cause the execution of an Interrupt Service Routine (ISR), which would allow the application to perform
“housekeeping tasks” and a controlled shutdown before the device voltage exits the valid operating range at TB. This
would give the application a time window, represented by the difference between TA and TB, to safely exit.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
HLVD - High/Low-Voltage Detect
Figure 40-4. Typical Low-Voltage Detect Application
Rev. 30-000143A
5/26/2017
Voltage
VA
VB
Time
TA
TB
Legend: VA = HLVD trip point
VB = Minimum valid device
operating voltage
40.6
Operation During Sleep
When enabled, the HLVD circuitry continues to operate during Sleep. When the device voltage crosses the trip point,
the HLVDIF bit will be set and the device will wake up from Sleep. If interrupts are enabled, the device will execute
code from the interrupt vector. If interrupts are disabled, the device will continue execution from the next instruction
after SLEEP.
40.7
Operation During Idle and Doze Modes
The performance of the module is independent of the Idle and Doze modes. The module will generate the events
based on the trip points. The response to these events will depend on the Doze and Idle mode settings.
40.8
Effects of a Reset
A device Reset forces all registers to their Reset state. This forces the HLVD module to be turned off. User firmware
has to configure the module again.
40.9
Register Definitions: HLVD Control
Long bit name prefixes for the HLVD peripheral is shown in the following table. Refer to the “Long Bit Names”
section in the “Register and Bits Naming Conventions” chapter for more information.
Table 40-1. HLVD Long Bit Name Prefixes
Peripheral
Bit Name Prefix
HLVD
HLVD
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Preliminary Datasheet
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PIC18F27/47/57Q84
HLVD - High/Low-Voltage Detect
40.9.1
HLVDCON0
Name:
Address:
HLVDCON0
0x04A
High/Low-Voltage Detect Control Register 0
Bit
Access
Reset
7
EN
R/W
0
6
5
OUT
R
x
4
RDY
R
x
3
2
1
INTH
R/W
0
0
INTL
R/W
0
Bit 7 – EN High/Low-voltage Detect Power Enable
Value
Description
1
Enables the HLVD module
0
Disables the HLVD module
Bit 5 – OUT HLVD Comparator Output
Value
Description
1
Voltage < selected detection limit (SEL)
0
Voltage > selected detection limit (SEL)
Bit 4 – RDY Band Gap Reference Voltages Stable Status Flag
Value
Description
1
Indicates HLVD Module is ready and output is stable
0
Indicates HLVD Module is not ready
Bit 1 – INTH HLVD Positive going (High Voltage) Interrupt Enable
Value
Description
1
HLVDIF will be set when voltage ≥ selected detection limit (SEL)
0
HLVDIF will not be set
Bit 0 – INTL HLVD Negative going (Low Voltage) Interrupt Enable
Value
Description
1
HLVDIF will be set when voltage ≤ selected detection limit (SEL)
0
HLVDIF will not be set
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Preliminary Datasheet
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PIC18F27/47/57Q84
HLVD - High/Low-Voltage Detect
40.9.2
HLVDCON1
Name:
Address:
HLVDCON1
0x04B
Low-Voltage Detect Control Register 1
Bit
7
6
5
4
3
2
1
0
R/W
0
R/W
0
SEL[3:0]
Access
Reset
R/W
0
R/W
0
Bits 3:0 – SEL[3:0] High/Low-Voltage Detection Limit Selection
Table 40-2. HLVD Detection Limits
SEL
Detection Limit
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
Reserved
4.63V
4.32V
4.12V
3.91V
3.71V
3.60V
3.40V
3.09V
2.88V
2.78V
2.57V
2.47V
2.26V
2.06V
1.85V
Reset States: POR/BOR = 0000
All other Resets = uuuu
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Preliminary Datasheet
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PIC18F27/47/57Q84
HLVD - High/Low-Voltage Detect
40.10
Address
0x00
...
0x49
0x4A
0x4B
Register Summary - HLVD
Name
Bit Pos.
7
7:0
7:0
EN
6
5
4
OUT
RDY
3
2
1
0
INTH
INTL
Reserved
HLVDCON0
HLVDCON1
© 2021 Microchip Technology Inc.
SEL[3:0]
Preliminary Datasheet
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PIC18F27/47/57Q84
FVR - Fixed Voltage Reference
41.
FVR - Fixed Voltage Reference
The Fixed Voltage Reference (FVR) is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V
selectable output levels. The output of the FVR can be configured to supply a reference voltage to analog peripherals
such as those listed below.
•
•
•
•
ADC input channel
ADC positive reference
Comparator input
Digital-to-Analog Converter (DAC)
The FVR can be enabled by setting the EN bit to ‘1’.
Note: Fixed Voltage Reference output cannot exceed VDD.
41.1
Independent Gain Amplifiers
The output of the FVR is routed through two independent programmable gain amplifiers. Each amplifier can be
programmed for a gain of 1x, 2x or 4x, to produce the three possible voltage levels.
The ADFVR bits are used to enable and configure the gain amplifier settings for the reference supplied to the ADC
module. Refer to the “ADCC - Analog-to-Digital Converter with Computation Module” chapter for additional
information.
The CDAFVR bits are used to enable and configure the gain amplifier settings for the reference supplied to the DAC
and comparator modules. Refer to the “DAC - Digital-to-Analog Converter Module” and “CMP - Comparator
Module” chapters for additional information.
Refer to the figure below for block diagram of the FVR module.
Figure 41-1. Fixed Voltage Reference Block Diagram
ADFVR
To ADC module
as reference and
input channel
1x
2x
4x
FVR Buffer 1
CDAFVR
To DAC and
Comparator modules,
To ADC module as
input channel only
1x
2x
4x
FVR Buffer 2
EN
Any peripheral
requiring Fixed
Reference
41.2
+
_
RDY
FVR Stabilization Period
When the Fixed Voltage Reference module is enabled, it requires time for the reference and amplifier circuits to
stabilize. Once the circuits stabilize and are ready for use, the RDY bit will be set.
41.3
Register Definitions: FVR
Long bit name prefixes for the FVR peripherals are shown in the following table. Refer to the “Long Bit Names”
section in the “Register and Bits Naming Conventions” chapter for more information.
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Preliminary Datasheet
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PIC18F27/47/57Q84
FVR - Fixed Voltage Reference
Table 41-1. FVR Long Bit Name Prefixes
Peripheral
Bit Name Prefix
FVR
FVR
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Preliminary Datasheet
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PIC18F27/47/57Q84
FVR - Fixed Voltage Reference
41.3.1
FVRCON
Name:
Address:
FVRCON
0x3D7
FVR Control Register
Important: This register is shared between the Fixed Voltage Reference (FVR) module and the
temperature indicator module.
Bit
Access
Reset
7
EN
R/W
0
6
RDY
R
q
5
TSEN
R/W
0
4
TSRNG
R/W
0
3
2
CDAFVR[1:0]
R/W
R/W
0
0
1
0
ADFVR[1:0]
R/W
0
R/W
0
Bit 7 – EN Fixed Voltage Reference Enable
Value
Description
1
Enables module
0
Disables module
Bit 6 – RDY Fixed Voltage Reference Ready Flag
Value
Description
1
Fixed Voltage Reference output is ready for use
0
Fixed Voltage Reference output is not ready for use or not enabled
Bit 5 – TSEN Temperature Indicator Enable
Value
Description
1
Temperature Indicator is enabled
0
Temperature Indicator is disabled
Bit 4 – TSRNG Temperature Indicator Range Selection
Value
Description
1
VOUT = 3VT (High Range)
0
VOUT = 2VT (Low Range)
Bits 3:2 – CDAFVR[1:0] FVR Buffer 2 Gain Selection(1)
Value
Description
11
FVR Buffer 2 Gain is 4x, (4.096V)(3)
10
FVR Buffer 2 Gain is 2x, (2.048V)(3)
01
FVR Buffer 2 Gain is 1x, (1.024V)
00
FVR Buffer 2 is OFF
Bits 1:0 – ADFVR[1:0] FVR Buffer 1 Gain Selection(2)
Value
Description
11
FVR Buffer 1 Gain is 4x, (4.096V)(3)
10
FVR Buffer 1 Gain is 2x, (2.048V)(3)
01
FVR Buffer 1 Gain is 1x, (1.024V)
00
FVR Buffer 1 is OFF
Notes:
1. This output goes to the DAC and comparator modules, and to the ADC module as an input channel only.
2. This output goes to the ADC module as a reference and an input channel.
3. Fixed Voltage Reference output cannot exceed VDD.
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Preliminary Datasheet
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PIC18F27/47/57Q84
FVR - Fixed Voltage Reference
41.4
Address
0x00
...
0x03D6
0x03D7
Register Summary - FVR
Name
Bit Pos.
7
6
5
4
7:0
EN
RDY
TSEN
TSRNG
3
2
1
0
Reserved
FVRCON
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Preliminary Datasheet
CDAFVR[1:0]
ADFVR[1:0]
DS40002213D-page 894
PIC18F27/47/57Q84
Temperature Indicator Module
42.
Temperature Indicator Module
This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the
silicon die. The temperature indicator module provides a temperature-dependent voltage that can be measured by
the internal Analog-to-Digital Converter.
The circuit’s range of operating temperature falls between -40℃ and +125℃. The circuit may be used as a
temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration
performed. A one-point calibration allows the circuit to indicate a temperature closely surrounding that point. A
two-point calibration allows the circuit to sense the entire range of temperature more accurately.
42.1
Module Operation
The temperature indicator module consists of a temperature-sensing circuit that provides a voltage to the device
ADC. The analog voltage output varies inversely to the device temperature. The output of the temperature indicator is
referred to as VMEAS.
The following figure shows a simplified block diagram of the temperature indicator module.
Figure 42-1. Temperature Indicator Module Block Diagram
VDD
TSRNG
TSEN
Temperature Indicator
Module
Rev. 10-000069D
11/13/2017
VMEAS
To ADC
GND
The output of the circuit is measured using the internal Analog-to-Digital Converter. A channel is reserved for the
temperature circuit output. Refer to the “ADCC - Analog-to-Digital Converter with Computation Module” chapter
for more details.
The ON/OFF bit for the module is located in the FVRCON register. The circuit is enabled by setting the TSEN bit.
When the module is disabled, the circuit draws no current. Refer to the “FVR - Fixed Reference Voltage” chapter
for more details.
42.1.1
Temperature Indicator Range
The temperature indicator circuit operates in either high or low range. The high range, selected by setting the TSRNG
bit, provides a wider output voltage. This provides more resolution over the temperature range. High range requires
a higher bias voltage to operate and thus, a higher VDD is needed. The low range is selected by clearing the TSRNG
bit. The low range generates a lower sensor voltage and thus, a lower VDD voltage is needed to operate the circuit.
The output voltage of the sensor is the highest value at -40℃ and the lowest value at +125℃.
• High Range: The high range is used in applications with the reference for the ADC, VREF = 2.048V. This range
may not be suitable for battery-powered applications.
• Low Range: This mode is useful in applications in which the VDD is too low for high-range operation. The VDD in
this mode can be as low as 1.8V. However, VDD must be at least 0.5V higher than the maximum sensor voltage
depending on the expected low operating temperature.
Important: The standard parameters for the Temperature Sensor for both high range and low range are
stored in the DIA table. Refer to the DIA table in “Memory Organization” chapter for more details.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
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PIC18F27/47/57Q84
Temperature Indicator Module
42.1.2
Minimum Operating VDD
When the temperature circuit is operated in low range, the device may be operated at any operating voltage that is
within the device specifications. When the temperature circuit is operated in high range, the device operating voltage,
VDD, must be high enough to ensure that the temperature circuit is correctly biased.
The following table shows the recommended minimum VDD vs. Range setting.
Table 42-1. RECOMMENDED VDD vs. RANGE
42.2
Min. VDD, TSRNG = 1
(High Range)
Min. VDD, TSRNG = 0
(Low Range)
≥ 2.5
≥ 1.8
Temperature Calculation
This section describes the steps involved in calculating the die temperature, TMEAS:
1. Obtain the ADC count value of the measured analog voltage: The analog output voltage, VMEAS is converted to
a digital count value by the Analog-to-Digital Converter (ADC) and is referred to as ADCMEAS.
2. Obtain the Gain value, from the DIA table. This parameter is TSLR1 for the low range setting or TSHR1 for the
high range setting of the temperature indicator module. Refer to the DIA table in the “Memory Organization”
chapter for more details.
3. Obtain the Offset value, from the DIA table. This parameter is TSLR3 for the low range setting or TSHR3
for the high range setting of the temperature indicator module. Refer to the DIA table in the “Memory
Organization” chapter for more details.
The following equation provides an estimate for the die temperature based on the above parameters:
Equation 42-1. Sensor Temperature (in ℃)
TMEAS =
ADCMEAS × Gain
+ Offset
256
10
Where:
ADCMEAS = ADC reading at temperature being estimated
Gain = Gain value stored in the DIA table
Offset = Offset Value stored in the DIA table
Note: It is recommended to take the average of ten measurements of ADCMEAS to reduce noise and improve
accuracy.
Example 42-1. Temperature Calculation (C)
//
//
//
//
offset is int16_t data type
gain is int16_t data type
ADC_MEAS is uint16_t data type
Temp_in_C is int24_t data type
ADC_MEAS = ((ADRESH ADPREV
no math functions
Vref = Vdd & Vss
select RA0/AN0
software controlled acquisition time
default S&H capacitance
no repeat measurements
auto-conversion disabled
ADC On, right-justified, ADCRC clock
;
; Set RA0 to input
;
; Set RA0 to analog
; Acquisiton delay
;
;
;
;
;
;
;
;
Start conversion
Is conversion done?
No, test again
Read upper byte
store in GPR space
Read lower byte
Store in GPR space
Example 43-2. ADC Conversion (C)
/*This code block configures the ADC for polling, VDD and VSS references,
ADCRC oscillator and AN0 input. Conversion start & polling for completion
are included. */ void main() { //System Initialize initializeSystem(); //
Setup ADC ADCON0bits.FM = 1; //right justify ADCON0bits.CS = 1; //ADCRC
Clock ADPCH = 0x00; //RA0 is Analog channel TRISAbits.TRISA0 = 1; //Set
RA0 to input ANSELAbits.ANSELA0 = 1; //Set RA0 to analog ADCON0bits.ON =
1; //Turn ADC On while (1) { ADCON0bits.GO = 1; //Start conversion while
(ADCON0bits.GO); //Wait for conversion done resultHigh = ADRESH; //Read
result resultLow = ADRESL; //Read result } }
43.3
ADC Acquisition Requirements
For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to
the input channel voltage level. The analog input model is shown in Figure 43-4. The source impedance (RS) and
the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The
sampling switch (RSS) impedance varies over the device voltage (VDD). The maximum recommended impedance for
analog sources is 10 kΩ. As the source impedance is decreased, the acquisition time may be decreased. After the
analog input channel is selected (or changed), an ADC acquisition time must be completed before the conversion can
be started. To calculate the minimum acquisition time, Equation 43-1 may be used. This equation assumes an error
of 1/2 LSb. The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution.
Equation 43-1. Acquisition Time Example
Assumptions: Temperature = 50°C; External impedance = 10 kΩ; VDD = 5.0V
TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
TACQ = TAMP + TC + TCOFF
TACQ = 2μs + TC + Temperature − 25°C 0.05μs/°C
The value for TC can be approximated with the following equations:
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Preliminary Datasheet
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VAPPLIED 1 −
1
n+1
2
−TC
− 1
= VCHOLD ; [1] VCHOLD charged to within ½ lsb
VAPPLIED 1 − e RC
= VCHOLD ; [2] VCHOLD charge response to VAPPLIED
VAPPLIED 1 − e RC
= VAPPLIED 1 −
−TC
Note: Where n = ADC resolution in bits
1
n+1
2
− 1
; Combining [1] and [2]
Solving for TC:
TC = − CHOLD RIC + RSS + RS ln 1/8191
TC = − 28pF 1kΩ + 7kΩ + 10kΩ ln 0.0001221
TC = 4.54μs
Therefore:
TACQ = 2μs + 4.54μs +
50°C − 25°C
TACQ = 7.79 μs
0.05μs/°C
Important:
• The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
• The charge holding capacitor (CHOLD) is not discharged after each conversion.
• The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin
leakage specification.
Figure 43-4. Analog Input Model
Sampling
Switch
VDD
RS
Analog
Input pin
VA
Legend: CPIN
ILE AKAG E
RIC
RS
VA
VT
SS
RSS
CHOLD
CPIN
5pF
VT
0.6V
VT
0.6V
RIC
1K
SS
RSS
ILEAKAGE(1)
CHOLD = 28 PF
VSS
Ref-
= Input Capacitance
= Leakage Current at the pin due to various junctions
= Interconnect Resistance
= Source Impedance
= Analog Voltage
= Diode Forward Voltage
= Sampling Switch
= Resistance of the Sampling Switch
= Sample/Hold Capacitance
Sampling
Switch
(K )
11
10
9
8
7
6
5
Note:
1. Refer to the Electrical Specifications chapter of the device data sheet for more details.
© 2021 Microchip Technology Inc.
Preliminary Datasheet
RSS
2 3 4 5 6
VDD
(V)
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Figure 43-5. ADC Transfer Function
Rev. 30-000115B
6/27/2017
Full-Scale Range
FFFh
FFEh
ADC Output Code
FFDh
FFCh
FFBh
03h
02h
01h
00h
Analog Input Voltage
0.5 LSB
REF-
43.4
Zero-Scale
Transition
1.5 LSB
Full-Scale
Transition
REF+
ADC Charge Pump
The ADC module has a dedicated charge pump which can be controlled through the ADCP register. The primary
purpose of the charge pump is to supply a constant voltage to the gates of transistor devices in the Analog-to-Digital
Converter, signal and reference input pass-gates, to prevent degradation of transistor performance at low operating
voltage.
The charge pump can be enabled by setting the CPON bit. Once enabled, the pump will undergo a start-up time to
stabilize the charge pump output. Once the output stabilizes and is ready for use, the CPRDY bit will be set.
43.5
Computation Operation
The ADC module hardware is equipped with post-conversion computation features. These features provide postprocessing functions such as digital filtering/averaging and threshold comparison. Based on computation results, the
module can be configured to take additional samples or stop conversions and an interrupt may be asserted.
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Figure 43-6. Computational Features Simplified Block Diagram
CALC
TMD
ADRES
CRS
Average/
Filter
ADFLTR
1
0
Error
Calculation
ADERR
Threshold
Logic
Set
Interrupt
Flag
ADPREV
ADSTPT
ADUTH
ADLTH
PSIS
The operation of the ADC computational features is controlled by the MD bits.
The module can be operated in one of five modes:
•
•
•
•
•
Basic: This is a legacy mode. In this mode, ADC conversion occurs on single (DSEN = 0) or double (DSEN = 1)
samples. ADIF is set after each conversion is complete. ADCHxIF is set according to the calculation mode.
Accumulate: With each trigger, the ADC conversion result is added to the accumulator and CNT increments.
ADIF is set after each conversion. ADCHxIF is set according to the calculation mode.
Average: With each trigger, the ADC conversion result is added to the accumulator. When the RPT number
of samples have been accumulated, a threshold test is performed. Upon the next trigger, the accumulator is
cleared. For the subsequent tests, additional RPT samples are required to be accumulated.
Burst Average: At the trigger, the accumulator is cleared. The ADC conversion results are then collected
repetitively until RPT samples are accumulated and finally the threshold is tested.
Low-Pass Filter (LPF): With each trigger, the ADC conversion result is sent through a filter. When RPT
samples have occurred, a threshold test is performed. Every trigger after that the ADC conversion result is sent
through the filter and another threshold test is performed.
The five modes are summarized in the following table.
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Preliminary Datasheet
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Table 43-2. Computation Modes
© 2021 Microchip Technology Inc.
Mode
rotatethispage90
MD
Register Clear
Event
ADACC and CNT
Basic
0
Accumulate
1
Average
2
Burst
Average
4
Threshold Operations
Value at ADCHmIF Interrupt
ADACC
ADCNT
Retrigger
Threshold Test
Interrupt
AOV
ADFLTR
ADCNT
Unchanged
Unchanged
No
Every Sample
If threshold=true
N/A
N/A
count
S1 + ADACC or If (ADCNT=0xFF):
(S2-S1)(2) +
ADCNT, otherwise:
ADACC
ADCNT+1
No
Every Sample
If threshold=true
ADACC
Overflow
ADACC/
2CRS
count
ACLR = 1 or
S1 + ADACC or If (ADCNT=0xFF):
(S2-S1) +
ADCNT, otherwise:
ADCNT≥ADRPT at
ADACC
ADCNT+1
GO set or retrigger
No
If ADCNT≥ADRPT If threshold=true
ADACC
Overflow
ADACC/
2CRS
count
Repeat while
ADACC
If ADCNT≥ADRPT If threshold=true
ADCNT 0
External analog I/O pin is connected to VDD
0
ADPRE > 0
Internal AD sampling capacitor (CHOLD) is connected to VSS
External analog I/O pin is connected to VSS
Internal AD sampling capacitor (CHOLD) is connected to VDD
Bit 6 – IPEN A/D Inverted Precharge Enable
Value
Condition Description
x
DSEN = 0 Bit has no effect
1
DSEN = 1 The precharge and guard signals in the second conversion cycle are the opposite polarity
of the first cycle
0
DSEN = 1 Both Conversion cycles use the precharge and guards specified by PPOL and GPOL
Bit 5 – GPOL Guard Ring Polarity Selection
Value
Description
1
ADC guard Ring outputs start as digital high during Precharge stage
0
ADC guard Ring outputs start as digital low during Precharge stage
Bit 0 – DSEN Double-Sample Enable
Value
Description
1
Two conversions are processed as a pair. The selected computation is performed after every second
conversion.
0
Selected computation is performed after every conversion
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43.7.3
ADCON2
Name:
Address:
ADCON2
0x3F5
ADC Control Register 2
Bit
7
PSIS
R/W
0
Access
Reset
6
R/W
0
5
CRS[2:0]
R/W
0
4
R/W
0
3
ACLR
R/W/HC
0
2
R/W
0
1
MD[2:0]
R/W
0
0
R/W
0
Bit 7 – PSIS ADC Previous Sample Input Select
Value
Description
1
ADFLTR is transferred to ADPREV at the start of conversion
0
ADRES is transferred to ADPREV at the start of conversion
Bits 6:4 – CRS[2:0] ADC Accumulated Calculation Right Shift Select
Value
Condition
Description
1 to 6
MD ='b100
Low-pass filter time constant is 2CRS, filter gain is 1:1(2)
1 to 6
MD ='b011 to 'b001
The accumulated value is right-shifted by CRS (divided by 2CRS)(1,2)
x
MD ='b000
These bits are ignored
Bit 3 – ACLR A/D Accumulator Clear Command(3)
Value
Description
1
Registers ADACC, ADCNT and the AOV bit are cleared
0
Clearing action is complete (or not started)
Bits 2:0 – MD[2:0] ADC Operating Mode Selection(4)
Value
Description
111-101 Reserved
100
Low-Pass Filter mode
011
Burst Average mode
010
Average mode
001
Accumulate mode
000
Basic (Legacy) mode
Notes:
1. To correctly calculate an average, the number of samples (set in ADRPT) must be 2CRS.
2. CRS = 'b111 and 'b000 are reserved.
3.
4.
This bit is cleared by hardware when the accumulator operation is complete; depending on oscillator
selections, the delay may be many instructions.
See the section for full mode descriptions.
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43.7.4
ADCON3
Name:
Address:
ADCON3
0x3F6
ADC Control Register 3
Bit
7
Access
Reset
6
R/W
0
5
CALC[2:0]
R/W
0
4
R/W
0
3
SOI
R/W/HC
0
2
R/W
0
1
TMD[2:0]
R/W
0
0
R/W
0
Bits 6:4 – CALC[2:0] ADC Error Calculation Mode Select
Table 43-6. ADC Error Calculation Mode
ADERR
CALC
DSEN = 0 Single-Sample
Mode
DSEN = 1 CVD DoubleSample Mode(1)
Application
111
110
101
Reserved
Reserved
ADFLTR-ADSTPT
Reserved
Reserved
ADFLTR-ADSTPT
100
ADPREV-ADFLTR
ADPREV-ADFLTR
011
010
001
Reserved
ADRES-ADFLTR
ADRES-ADSTPT
Reserved
(ADRES-ADPREV)-ADFLTR
(ADRES-ADPREV)-ADSTPT
000
ADRES-ADPREV
ADRES-ADPREV
Reserved
Reserved
Average/filtered value vs. setpoint
First derivative of filtered value(3)
(negative)
Reserved
Actual result vs. averaged/filtered value
Actual result vs. setpoint
First derivative of single measurement(2)
Actual CVD result(2)
Notes:
1. When DSEN = 1 and PSIS = 0, ADERR is computed only after every second sample.
2.
When PSIS = 0.
3.
When PSIS = 1.
Bit 3 – SOI ADC Stop-on-Interrupt
Value
Condition Description
x
CONT = 0 This bit is not used
1
CONT = 1 GO is cleared when the threshold conditions are met, otherwise the conversion is
retriggered
0
CONT = 1 GO is not cleared by hardware, must be cleared by software to stop retriggers
Bits 2:0 – TMD[2:0] Threshold Interrupt Mode Select
Value
Description
111
Interrupt regardless of threshold test results
110
Interrupt if ADERR > ADUTH
101
Interrupt if ADERR ≤ ADUTH
100
Interrupt if ADERR < ADLTH or ADERR > ADUTH
011
Interrupt if ADERR > ADLTH and ADERR < ADUTH
010
Interrupt if ADERR ≥ ADLTH
001
Interrupt if ADERR < ADLTH
000
Never interrupt
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43.7.5
ADSTAT
Name:
Address:
ADSTAT
0x3F7
ADC Status Register
Bit
Access
Reset
7
AOV
R/C/HS/HC
0
6
UTHR
R
0
5
LTHR
R
0
4
MATH
R/W/HS
0
3
2
R
0
1
STAT[2:0]
R
0
0
R
0
Bit 7 – AOV ADC Accumulator Overflow
Value
Description
1
ADACC or ADFLTR or ADERR registers have overflowed
0
ADACC, ADFLTR and ADERR registers have not overflowed
Bit 6 – UTHR ADC Module Greater-than Upper Threshold Flag
Value
Description
1
ADERR > ADUTH
0
ADERR ≤ ADUTH
Bit 5 – LTHR ADC Module Less-than Lower Threshold Flag
Value
Description
1
ADERR
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