PL123E-09HOC-R

PL123E-09 (Preliminary) Low Skew Zero Delay Buffer FEATURES DESCRIPTION     The PL123E-09 (-09H for High Drive) is a high performance, low skew, low jitter zero delay buffer d esigned to distribute high speed clocks. It has two low-skew output banks, of 4 outputs each, that are synchronized with the input. Control of the two banks o f outputs is achieved by using the S1 and S2 inputs as shown in the Selector Definition table on page 2.   Frequency Range 10MHz to 220MHz Zero input - output delay. Low Output to Output Skew Optional Drive Strength: Standard (8mA) PL123E-09 High (12mA) PL123E-09H 2.5V or 3.3V, ±10% operation. Available in 16-Pin SOP or TSSOP packages The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than 100ps, the device acts as a zero delay buffer. The input output propagation delay can be advanced or delayed by adjusting the load on the CLKOUT pin. These parts are not intended for 5V input-tolerant applications. BLOCK DIAGRAM PLL REF Mux CLKOUT CLKA2 CLKA3 Bank A CLKA1 CLKA4 S2 Selector Inputs CLKB2 CLKB3 Bank B S1 CLKB1 REF 1 16 CLKOUT CLKA1 2 15 CLKA4 CLKA2 3 14 CLKA3 VDD 4 13 VDD GND 5 12 GND CLKB1 6 11 CLKB4 CLKB2 7 10 CLKB3 S2 8 9 S1 CLKB4 Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 1 (Preliminary) PL123E-09 Low Skew Zero Delay Buffer PIN DESCRIPTIONS Package Type Name REF [1 ] TSSOP-16L SOP-16L Type Description 1 1 I Input reference frequency. [2 ] 2 2 O Buffered clock output, Bank A CLKA2 [2 ] 3 3 O Buffered clock output, Bank A VDD 4,13 4,13 P VDD connection GND 5,12 5,12 P GND connection CLKB1 [2 ] 6 6 O Buffered clock output, Bank B CLKB2 [2 ] 7 7 O Buffered clock output, Bank B S2 [3 ] 8 8 I Selector input CLKA1 S1 [3 ] 9 9 I Selector input [2 ] 10 10 O Buffered clock output, Bank B CLKB4 [2 ] 11 11 O Buffered clock output, Bank B CLKA3 [2 ] 14 14 O Buffered clock output, Bank A CLKA4 [2 ] 15 15 O Buffered clock output, Bank A CLKOUT [2 ] 16 16 O Buffered clock output. Internal feedback on this pin. CLKB3 Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs. 3: Weak Pull-Up on S1 and S2 SELECTOR DEFINITION S2 S1 CLOCK A1–A4 (Bank A) CLOCK B1–B4 (Bank B) CLKOUT Output Source PLL Shutdown 0 0 Three-state Three-state Driven PLL N 0 1 Driven Three-state Driven PLL N 1 0 Driven Driven Driven Reference Y 1 1 Driven Driven Driven PLL N INPUT / OUTPUT SKEW CONTROL The PL123E-09 will achieve Zero Delay from input to output when all the outputs are loaded equally . Adjustments to the input/output delay can be made by adding additional loading to the CLKOUT pin. Please contact Micrel for more information. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 2 (Preliminary) PL123E-09 Low Skew Zero Delay Buffer LAYOUT RECOMMENDATIONS The following guidelines are to assist you with a pe rformance optimized PCB design: Signal Integrity and Termination Considerations Decoupling and Power Supply Considerations - Keep traces short! - Place decoupling capacitors as close as possible to the VDD pin(s) to limit noise from the power supply - Trace = Inductor. With a capacitive load this equals ringing! - Long trace = Transmission Line. Without proper termination this will cause reflections ( looks like ringing ). - Design long traces as “striplines” or “microstrips” with defined impedance. - Match trace at one side to avoid reflections bouncing back and forth. - Addition of a ferrite bead in series with VDD can help prevent noise from other board sources - Value of decoupling capacitor is frequency dependant. Typical values to use are 0.1 F for designs using frequencies < 50MHz and 0.01F for designs using frequencies > 50MHz. Typical CMOS termination Place Series Resistor as close as possible to CMOS output CMOS Output Buffer To CMOS Input ( Typical buffer impedance 20  50 line Connect a 33 series resistor at each of the output clocks to enhance the stability of the output signal Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 3 PL123E-09 (Preliminary) Low Skew Zero Delay Buffer ABSOLUTE M AXIM UM CONDITIONS Supply Voltage to Ground Potenti al ...... –0.5V to 4.6V DC Input Voltage ............................ V SS – 0.5V to 4.6V Storage Temperature ..........................–65°C to 150°C Junction Temperature ..................................... 150°C Static Discharge Voltage (per MIL-STD-883, Method 3015)……………..> 2000V OPERATING CONDITIONS Description Parameter Min Max Unit Supply Voltage V DD 2.25 3.63 V Load Capacitance,