PL520-30DC

PL520-30 PECL and LVDS Low Phase Noise VCXO (for 65 -130MHz Fund Xtal) DIE CONFIGURATION FEATURES DESCRIPTION BLOCK DIAGRAM OE OESEL^ VDD VDD VDD VDD N/C Reserved Reserved 24 23 22 21 20 19 18 17 26 Die ID: A1313-13B XOUT 27 N/C 28 N/C 29 OE CTRL 30 VCON 31 Amplifier w/ integrated varicaps 4 5 6 GND GND Reserved X 7 8 GNDBUF 3 GNDBUF 2 GND (0,0) 16 N/C 15 LVDSB 14 PECLB 13 12 VDDBUF VDDBUF 11 PECL 10 LVDS OUTSEL^ DIE SPECIFICATIONS Name Value Size Reverse side Pad dimensions Thickness 62 x 65 m il GND 80 m icron x 80 micron 10 m il OUTPUT SELECTION AND ENABLE OUTSEL (Pad #9) Q 0 1 PL520-30 GNDBUF 9 1 GND Y Q VCON Oscillator XOUT 25 C502A The PL520-30 is a VCXO IC specifically designed to pull frequency fundamental crystals from 65MHz to 130MHz, with selectable PECL or LVDS outputs and OE logic (enable high or enable low). Its design was optimized to tolerate higher limits of interelectrodes capacitance and bonding capacitance to improve yield. It achieves very low current into the crystal resulting in better overall stability. Its internal varicaps allow an on chip frequency pulling, controlled by the VCON input. XIN XIN (1550,1475) GND        65MHz to 130MHz Fundamental Mode Crystals. Output range (no PLL):  65MHz – 130MHz (3.3V).  65MHz – 105MHz (2.5V). Low Injection Power for crystal 50uW. Complementary outputs: PECL or LVDS. Selectable OE Logic Integrated variable capacitors. Supports 2.5V or 3.3V-Power Supply. Available in die form. Thickness 10 mil. 62 mil   65 mil OESEL (Pad #25) 0 1 (default) Selected Output LVDS PECL (default) OE_CTRL (Pad #30) 0 1 0 1 State Tri-state Output enabled (default) Output enabled (default) Tri-state Pad # 9, # 25: Bond to GND to set to “0”. Internal pull up. Pad # 30: Logical states defined by PECL levels if OESEL is “1” Logical states defined by CMOS levels if OESEL is “0” Micrel Inc. • 2180 Fortune Drive • San Jose, CA 951 31 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 2/9/09 Page 1 PL520-30 PECL and LVDS Low Phase Noise VCXO (for 65 -130MHz Fund Xtal) ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage Input Voltage, dc Output Voltage, dc VDD VI VO Storage Temperature Ambient Operating Temperature* Junction Temperature TS TA TJ MIN. MAX. UNITS -0.5 -0.5 4.6 VDD +0.5 VDD +0.5 V V V 150 85 125 C C C 260 2 C kV -65 -40 Lead Temperature (soldering, 10s) ESD Protection, Human Body Model Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade on ly. 2. Crystal Specifications PARAMETERS Built-in Capacitance Inter-electrode capacitance C0/C1 ratio (gamma) Oscillation Frequency SYMBOL CONDITIONS CX+ CXC0 65MHz to 130MHz (at VDD ) MIN. TYP. OF UNITS 2 2 pF 2.6 300 130 105  Fund., 3.3V Supplies Fund., 2.5V Supplies MAX. 65 65 MHz 3. Voltage Control Crystal Oscillator (3.3V) PARAMETERS VCXO Stabilization Time * VCXO Tuning Range * VCXO pullability * On-chip Varicaps control range * SYMBOL T VC XOS TB CONDITIONS From power valid XTAL C 0/C 1 < 250 0V  VCON  VDD VCON=1.65V, 1.65V VCON = 0 to VDD 3.3V Supplies 2.5V Supplies MIN. MAX. UNITS 10 ms 200 ppm ppm 100 4 – 18 7 – 18 Linearity * VCXO Tuning Characteristic VCON input impedance VCON modulation BW TYP. pF 10 65 60 0V  VCON  VDD , -3dB 25 % ppm/V k kHz Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 951 31 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 2/9/09 Page 2 PL520-30 PECL and LVDS Low Phase Noise VCXO (for 65 -130MHz Fund Xtal) 4. General Electrical Specifications PARAMETERS SYMBOL CONDITIONS Supply Current (Loaded Outputs) IDD PECL/LVDS Operating Voltage VDD 3.3V Supplies 2.5V Supplies @ @ @ @ Output Clock Duty Cycle MIN. TYP. 2.97 2.375 45 45 43 43 1.25V (LVDS), 3.3V Supply V DD – 1.3V (PECL), 3.3V Supply 1.25V (LVDS), 2.5V Supply V DD – 1.3V (PECL), 2.5V Supply Short Circuit Current 50 50 50 50 50 MAX. UNITS 70/40 mA 3.63 2.625 55 55 57 57 V % % mA 5. Jitter Specifications PARAMETERS CONDITIONS MIN. TYP. MAX. UNITS Period jitter RMS 77.76MHz 2.5 ps Period jitter peak-to-peak Integrated jitter RMS 77.76MHz Integrated 12 kHz to 20 MHz at 77.76MHz 18.5 0.5 ps ps 6. Phase Noise Specifications PARAMETERS Phase Noise relative to carrier FREQUENCY @10Hz @100Hz @1kHz @10kHz @100kHz UNITS 77.76MHz -75 -95 -125 -145 -155 dBc/Hz Note: Phase Noise at VCON = 0V Micrel Inc. • 2180 Fortune Drive • San Jose, CA 951 31 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 2/9/09 Page 3 PL520-30 PECL and LVDS Low Phase Noise VCXO (for 65 -130MHz Fund Xtal) 7. LVDS Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS 355 454 mV 50 1.6 Output Differential Voltage VOD 247 VDD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change V OD VOH VOL VOS -50 Power-off Leakage I OXD Output Short Circuit Current I OSD R L = 100  (see figure) 0.9 1.125 0 V OS Vout = VDD or GND VDD = 0V 1.4 1.1 1.2 3 1.375 25 mV V V V mV 1 10 uA -5.7 -8 mA 8. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf R L = 100  C L = 10 pF (see figure) 0.2 0.7 1.0 ns LVDS Levels Test Circuit LVDS Switching Test Circuit OUT OUT CL = 10pF 50 VO D VO S VDIF F RL = 100  50 CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIF F 80% 0V 20% 20% tR tF Micrel Inc. • 2180 Fortune Drive • San Jose, CA 951 31 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 2/9/09 Page 4 PL520-30 PECL and LVDS Low Phase Noise VCXO (for 65 -130MHz Fund Xtal) 9. PECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. MAX. UNITS VOH VOL R L = 50 to (VDD – 2V) (see figure) VDD – 1.025 VDD – 1.900 VDD – 0.750 VDD – 1.620 V V Output High Voltage Output Low Voltage 10. PECL Switching Characteristics PARAMETERS SYMBOL Clock Rise Time Clock Fall Time tr tf CONDITIONS MIN. @20/80% - PECL @80/20% - PECL PECL Levels Test Circuit OUT MAX. UNITS 0.6 0.5 1.5 1.5 ns ns PECL Output Skew VDD 50 TYP. OUT 2.0V 50% 50 OUT tSKEW OUT PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF Micrel Inc. • 2180 Fortune Drive • San Jose, CA 951 31 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 2/9/09 Page 5 PL520-30 PECL and LVDS Low Phase Noise VCXO (for 65 -130MHz Fund Xtal) PAD ASSIGNMENT Pad # Name X (m) Y (m) Description 1 Optional GND 248 109 Optional Ground. 2 3 Optional GND Optional GND 361 473 109 109 Optional Ground. Optional Ground. 4 5 6 Optional GND GND Reserved 587 702 874 109 109 109 Optional Ground. Ground. Reserved for future use. 7 8 Optional GNDBUF GNDBUF 1042 1171 109 109 9 OUTSEL 1400 125 10 11 12 LVDS PECL VDDBUF 1400 1400 1400 259 476 616 Optional Ground, buffer circuitry. Ground, buffer circuitry. Output type selector. Internal pull up. See Output Selection and Enable table on page 1. Internal pull up. LVDS output. PECL output. 3.3V power supply, buffer circuitry. 13 14 15 Optional VDDBUF PECLB LVDSB 1400 1400 1400 716 871 1089 Optional 3.3V power supply, buffer circuitry. Complementary PECL output. Complementary LVDS output. 16 17 18 19 20 21 22 Not connected GNDBUF Reserved Reserved Not connected Optional VDD Optional VDD 1400 1389 1232 1042 854 659 559 1227 1365 1365 1365 1365 1365 1365 Not Connected. Ground, buffer circuitry. Reserved for future use. Reserved for future use. Not Connected. Optional 3.3V power supply. Optional 3.3V power supply. 23 24 VDD Optional VDD 459 358 1365 1365 25 OESEL 194 1365 26 27 28 XIN XOUT Not connected 109 109 109 1223 1017 858 3.3V power supply. Optional 3.3V power supply. Used to choose between PECL and CMOS OE logic levels. See Output Selection and Enable table on page 1. Internal pull up Crystal input. See Crystal Specifications on page 2. Crystal output. See Crystal Specifications on page 2. Not Connected. 29 Not connected 109 646 30 OE_CTRL 109 397 31 VCON 109 181 Not Connected. Used to enable/disable the output(s). See Output Selection and Enable table on page 1. Voltage control input. Note: for optimal Phase Noise performance, it is recommended to bond all optional VDD and GND pads. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 951 31 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 2/9/09 Page 6 PL520-30 PECL and LVDS Low Phase Noise VCXO (for 65 -130MHz Fund Xtal) ORDERING INFORM ATION For part ordering, please contact our Sales Departm ent: 2180 Fortune Drive, San Jose, CA 95131, USA Tel: (408) 944-0800 Fax: (408) 474-1000 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PL 520-30 D C PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRIAL PACKAGE TYPE D=DIE Order Number Marking Package Option PL520-30DC P520-30DC Die – Waffle Pack Micrel Inc., reserves the right to make changes in its products or specifications, or both at any time without notice. The in formation furnished by Micrel is believed to be accurate and reliable. However, Micrel makes no guarantee or warr anty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: Micrel’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Micrel Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 951 31 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 2/9/09 Page 7