SY100E156JZ

SY10E156 SY100E156 FINAL 3-BIT 4:1 MUX-LATCH DESCRIPTION FEATURES ■ ■ ■ ■ ■ ■ ■ The SY10/100E156 offer three 4:1 multiplexers followed by latches with differential outputs, designed for use in new, high-performance ECL systems. The two external latch enable signals (LEN1 and LEN2) are gated through a logical OR operation before use as control for the three latches. When both LEN1 and LEN 2 are at a logic LOW, the latches are transparent, thus presenting the data from the multiplexers at the output pins. If either LEN1 or LEN2 (or both) are at a logic HIGH, the outputs are latched. The multiplexer operation is controlled by the Select (SEL0, SEL1) signals which select one of the four bits of input data at each mux to be passed through. The MR (Master Reset) signal operates asynchronously to take all outputs to a logic LOW. 900ps max. D to output Extended 100E VEE range of –4.2V to –5.5V 800ps max. LEN to output Differential outputs Asynchronous Master Reset Dual latch enables Fully compatible with industry standard 10KH, 100K ECL levels ■ Internal 75KΩ input pulldown resistors ■ Fully compatible with Motorola MC10E/100E156 ■ Available in 28-pin PLCC package BLOCK DIAGRAM E N R Q0 E N R 26 18 Q2 SEL1 MR 27 17 28 16 Q1 VEE 1 15 Q2 VCC Q1 2 14 Q1 Q1 LEN1 LEN2 3 13 VCCO D1c 4 12 Q0 PLCC TOP VIEW J28-1 D2a D2b D2c D2d 4:1 MUX D Q2 E N R Q2 6 D1d D0a 5 SEL0 7 8 9 10 11 VCCO Q0 4:1 MUX 25 24 23 22 21 20 19 SEL0 D0d D D2b D2a VCCO Q0 D2d D2c D D0b D0c D1a D1b D1c D1d 4:1 MUX D1b D1a D0a D0b D0c D0d PIN CONFIGURATION PIN NAMES SEL1 Pin LEN1 LEN2 MR Function D0x–D2x Input Data SEL0, SEL1 Select Inputs LEN1, LEN2 Latch Enables MR Master Reset Q0–Q2 True Outputs Q0–Q2 Inverted Outputs VCCO VCC to Output Rev.: C 1 Amendment: /1 Issue Date: February, 1998 SY10E156 SY100E156 Micrel TRUTH TABLES LEN1 LEN2 Latch SEL0 SEL1 Data L L Transparent L L a H X Latched H L b X H Latched L H c H H d DC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0°C Symbol Parameter TA = +25°C Min. Typ. Max. Min. Typ. IIH Input HIGH Current IEE Power Supply Current 10E 100E TA = +85°C Max. Min. Typ. Max. Unit Condition µA — mA — Unit Condition ps — ps — ps — — — 150 — — 150 — — 150 — — 75 75 90 90 — — 75 75 90 90 — — 75 86 90 103 AC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. tPLH tPHL Propagation Delay to Output D SEL0 SEL1 LEN MR 400 550 450 350 350 600 775 650 500 600 900 1050 900 800 825 400 550 450 350 350 600 775 650 500 600 900 1050 900 800 825 400 550 450 350 350 600 775 650 500 600 900 1050 900 800 825 tS Set-up Time D SEL0 SEL1 400 700 600 275 300 400 — — — 400 700 600 275 300 400 — — — 400 700 600 275 300 400 — — — Hold Time D SEL0 SEL1 300 100 200 –275 –300 –400 — — — 300 100 200 –275 –300 –400 — — — 300 100 200 –275 –300 –400 — — — tRR Reset Recovery Time 800 600 — 800 600 — 800 600 — ps — tPW Minimum Pulse Width, MR 400 — — 400 — — 400 — — ps — tskew Within-Device Skew — 50 — — 50 — — 50 — ps 1 tr tf Rise/Fall Time 20% to 80% 275 475 700 275 475 700 275 475 700 ps — tH NOTE: 1. Within-device skew is defined as identical transitions on similar paths through a device. PRODUCT ORDERING CODE Ordering Code 2 Package Type Operating Range SY10E156JC J28-1 Commercial SY10E156JCTR J28-1 Commercial SY100E156JC J28-1 Commercial SY100E156JCTR J28-1 Commercial SY10E156 SY100E156 Micrel 28 LEAD PLCC (J28-1) Rev. 03 3 SY10E156 SY100E156 Micrel MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. © 2000 Micrel Incorporated 4