SY100E167JC-TR

NOT RECOMMENDED FOR NEW DESIGNS SY10E167 SY100E167 SY10E167 SY100E167 6-BIT 2:1 MUX-REGISTER SYNERGY SEMICONDUCTOR FEATURES The SY10/100E167 offer six 2:1 multiplexers followed by D flip-flops with single-ended outputs, designed for use in new, high-performance ECL systems. The Select (SEL) control allows one of the two data inputs to the multiplexer to pass through. The two external clock signals (CLK1, CLK2) are gated through a logical OR operation before use as control for the six flip-flops. The selected data are transferred to the flip-flops on the rising edge of CLK1 or CLK2 (or both). The multiplexer operation is controlled by the Select (SEL) signal which selects one of the two bits of input data at each mux to be passed through. When a logic HIGH is applied to the Master Reset (MR) signal, it operates asychronously to take all outputs Q to a logic LOW. BLOCK DIAGRAM MUX D0b Q D SEL Q0 D5a D0a PIN CONFIGURATION D3b D3a NC VCCO ■ ■ ■ ■ 1000MHz min. operating frequency Extended 100E VEE range of –4.2V to –5.5V 800ps max. clock to output Single-ended outputs Asynchronous Master Reset Dual clocks Fully compatible with industry standard 10KH, 100K ECL levels Internal 75KΩ input pulldown resistors ESD protection of 2000V Fully compatible with Motorola MC10E/100E167 Available in 28-pin PLCC package D4b D4a ■ ■ ■ ■ ■ ■ ■ DESCRIPTION R 25 24 23 22 21 20 19 D2a MUX D2b SEL D3a MUX D3b MUX MUX D5b D SEL 28 16 VCC Q3 Q2 TOP VIEW PLCC J28-1 1 MR SEL 2 D0a 4 Q Q3 Q Q4 15 6 7 8 13 Q2 VCCO 12 Q1 14 3 5 D 9 10 11 PIN NAMES R Q D Pin Q5 R SEL CLK1 CLK2 MR © 1999 Micrel-Synergy Q4 CLK2 VEE R SEL D5a Q 17 R SEL D4a D4b R D Q5 27 VCCO Q0 SEL 18 CLK1 Q1 D2a D2b D1b Q D D1a D1b MUX 26 D0b D1a D5b Function D0a–D5a Input Data a D0b–D5b Input Data b SEL Select Input CLK1, CLK2 Clock Inputs MR Master Reset Q0–Q5 Data Outputs VCCO VCC to Output Rev.: C 5-127 Amendment: /1 Issue Date: February, 1998 SY10E167 SY100E167 SYNERGY SEMICONDUCTOR TRUTH TABLE SEL Data H a L b DC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0°C Symbol Parameter TA = +25°C Min. Typ. Max. Min. Typ. IIH Input HIGH Current IEE Power Supply Current 10E 100E TA = +85°C Max. Min. Typ. Max. Unit Condition µA — mA — Max. Unit Condition — MHz — ps — ps — ps — — — 150 — — 150 — — 150 — — 94 94 113 113 — — 94 94 113 113 — — 94 108 113 130 AC ELECTRICAL CHARACTERISTICS VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND TA = 0°C Symbol Parameter TA = +25°C Min. Typ. Max. Min. Typ. — 1000 1400 Max. Min. Typ. fMAX Max. Toggle Frequency tPLH tPHL Propagation Delay to Output CLK MR 450 450 650 650 800 850 450 450 650 650 800 850 450 450 650 650 800 850 tS Set-up Time D SEL 100 275 –50 125 — — 100 275 –50 125 — — 100 275 –50 125 — — Hold Time D SEL 300 75 50 –125 — — 300 75 50 –125 — — 300 75 50 –125 — — tRR Reset Recovery Time 750 550 — 750 550 — 750 550 — ps — tPW Minimum Pulse Width CLK, MR 400 — — 400 — — 400 — — ps — tskew Within-Device Skew — 75 — — 75 — — 75 — ps 1 tr tf Rise/Fall Time 20% to 80% 300 450 800 300 450 800 300 450 800 ps — tH 1000 1400 TA = +85°C — NOTE: 1. Within-device skew is defined as identical transitions on similar paths through a device. PRODUCT ORDERING CODE Ordering Code Package Type Operating Range SY10E167JC J28-1 Commercial SY10E167JCTR J28-1 Commercial SY100E167JC J28-1 Commercial SY100E167JCTR J28-1 Commercial 5-128 1000 1400 SY10E167 SY100E167 SYNERGY SEMICONDUCTOR 28 LEAD PLASTIC LEADED CHIP CARRIER (J28-1) 5-129