SY100S834LZI

SY100S834/SY100S834L (÷1, ÷2, ÷4) or (÷2, ÷4, ÷8) Clock Generation Chip Precision Edge® General Description The SY100S834/L is low skew (÷1, ÷2, ÷4) or (÷2, ÷4, ÷8) clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be ACcoupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01µF capacitor. The VBB output is designed to act as the switching reference for the input of the SY100S834/L under single-ended input conditions. As a result, this pin can only source/sink up to 0.5mA of current. The Function Select (FSEL) input is used to determine what clock generation chip function is. When FSEL input is LOW, SY100S834/L functions as a divide by 2, by 4 and by 8 clock generation chip. However, if FSEL input is HIGH, it functions as a divide by 1, by 2 and by 4 clock generation chip. This latter feature will increase the clock frequency by two folds. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon start-up, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as for multiple SY100S834/Ls in a system. Data sheets and support documentation can be found on Micrel’s web site at www.micrel.com. Precision Edge® Features • 3.3V (SY100S834L) and 5V (SY100S834) power supply options • 50ps output-to-output skew • Synchronous enable/disable • Master reset for synchronization • Internal 75KΩ input pulldown resistors • Available in 16-pin SOIC package Truth Table MR Function Z EN L L Divide ZZ H L Hold Q0−2 X X H Reset Q0−2 Q1 Outputs Divide by 4 Divide by 2 Q2 Outputs Divide by 8 Divide by 4 CLK Notes: Z = LOW-to-HIGH transition. ZZ = HIGH-to-LOW transition. FSEL L H Q0 Outputs Divide by 2 Divide by 1 Precision Edge is a registered trademark of Micrel, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com June 2011 M9999-060911 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY100S834/SY100S834L Ordering Information Part Number Package Type Operating Range Package Marking Lead Finish Z16-2 Commercial SY100S834ZC Sn-Pb SY100S834ZCTR Z16-2 Commercial SY100S834ZC Sn-Pb SY100S834LZC Z16-2 Commercial SY100S834LZC Sn-Pb SY100S834LZCTR(1) Z16-2 Commercial SY100S834LZC Sn-Pb SY100834ZI Z16-2 Industrial SY100S834ZI Sn-Pb SY100S834ZC (1) SY100834ZITR(1) Z16-2 Industrial SY100S834ZI Sn-Pb SY100834LZI Z16-2 Industrial SY100S834LZI Sn-Pb Z16-2 Industrial SY100S834LZI Sn-Pb Z16-2 Industrial SY100S834ZG with Pb-Free bar-line indicator NiPdAu Pb-Free SY100834ZGTR(1, 2) Z16-2 Industrial SY100S834ZG with Pb-Free bar-line indicator NiPdAu Pb-Free SY100834LZG(2) Z16-2 Industrial SY100S834LZG with Pb-Free bar-line indicator NiPdAu Pb-Free SY100834LZGTR(1, 2) Z16-2 Industrial SY100S834LZG with Pb-Free bar-line indicator NiPdAu Pb-Free (1) SY100834LZITR SY100834ZG (2) Notes: 1. Tape and reel. 2. Pb-Free package is recommended for new designs. Pin Configuration 16-Pin SOIC (Z16-2) June 2011 2 M9999-060911 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY100S834/SY100S834L Pin Description Pin Name Pin Function CLK Differential clock inputs. FSEL Function select, single-sided ECL logic. EN Synchronous enable, single-sided ECL logic. MR Master reset, single-sided ECL logic. VBB Reference output. Q0 Differential ÷1 or ÷2 outputs. Q1 Differential ÷2 or ÷4 outputs. Q2 Differential ÷4 or ÷8 outputs. 3.3V PECL Output DC Electrical Characteristics(1) VCC = 3.3V ±10%; RL = 50Ω to VCC −2V; VEE = GND. Symbol Parameter TA = −40°C TA = +25°C TA = 0°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit IEE Power Supply Current − − 49 − − 49 − − 49 − − 54 mA VCH Output HIGH Voltage 2.215 2.295 2.42 2.275 2.235 2.42 2.275 2.345 2.42 2.275 2.345 2.42 V VOL Output LOW Voltage 1.47 1.605 1.745 1.49 1.595 1.68 1.49 1.595 1.68 1.49 1.595 1.68 V VIH Input HIGH Voltage 2.135 − 2.42 2.135 − 2.42 2.135 − 2.42 2.135 − 2.42 V VIL Input LOW Voltage 1.49 − 1.825 1.49 − 1.825 1.49 − 1.825 1.49 − 1.825 V VBB Output Reference Voltage 1.92 − 2.04 1.92 − 2.04 1.92 − 2.04 1.92 − 2.04 V VCMR Common (2) Mode Range 2 − 2.9 1.9 − 2.9 1.9 − 2.9 1.9 − 2.9 V IIH Input HIGH Current − − 150 − − 150 − − 150 − − 150 µA IIL Input LOW Current 0.5 − − 0.5 − − 0.5 − − 0.5 − − µA Notes: 1. These values are for VCC = 3.3V. Level specifications will vary 1:1 with VCC. 2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP (min.) and 1V. The lower end of the CMR range varies 1:1 with VEE. Note for PECL operation that the VCMR (min.) will be fixed at 3.3V − IVCMR (min.)I. June 2011 3 M9999-060911 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY100S834/SY100S834L 5V PECL Output DC Electrical Characteristics(2) VCC = 3.3V ±10%; RL = 50Ω to VCC −2V; VEE = GND. Symbol Parameter TA = −40°C TA = +25°C TA = 0°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit IEE Power Supply Current − − 49 − − 49 − − 49 − − 54 mA VCH Output HIGH Voltage 3.915 3.995 4.12 3.975 4.045 4.12 3.975 4.045 4.12 3.975 4.045 4.12 V VOL Output LOW Voltage 3.17 3.305 3.445 3.19 3.295 3.38 3.19 3.295 3.38 3.19 3.295 3.38 V VIH Input HIGH Voltage 3.835 − 4.12 3.835 − 4.12 3.835 − 4.12 3.835 − 4.12 V VIL Input LOW Voltage 3.19 − 3.525 3.19 − 3.525 3.19 − 3.525 3.19 − 3.525 V VBB Output Reference Voltage 3.62 − 3.74 3.62 − 3.74 3.62 − 3.74 3.62 − 3.74 V VCMR Common (2) Mode Range 2 − 4.6 1.9 − 4.6 1.9 − 4.6 1.9 − 4.6 V IIH Input HIGH Current − − 150 − − 150 − − 150 − − 150 µA IIL Input LOW Current 0.5 − − 0.5 − − 0.5 − − 0.5 − − µA Notes: 1. These values are for VCC = 5V. Level specifications will vary 1:1 with VCC. 2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP (min.) and 1V. The lower end of the CMR range varies 1:1 with VEE. Note for PECL operation that the VCMR (min.) will be fixed at 3.3V − IVCMR (min.)I. June 2011 4 M9999-060911 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY100S834/SY100S834L NECL Output DC Electrical Characteristics VCC = GND; RL = 50Ω to VCC −2V; VEE = −3.0V to −5.5V. Symbol Parameter IEE TA = −40°C TA = +25°C TA = 0°C TA = +85°C Unit Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Power Supply Current − − 49 − − 49 − − 49 − − 54 mA VCH Output HIGH Voltage −1085 −1005 −880 −1025 −955 −880 −1025 −955 −880 −1025 −955 −880 V VOL Output LOW Voltage −1830 −1695 −1555 −1830 −1705 −1620 −1810 −1705 −1620 −1810 −1705 −1620 V VIH Input HIGH Voltage −1165 − −880 −1165 − −880 −1165 − −880 −1165 − −880 V VIL Input LOW Voltage −1810 − −1475 −1810 − −1475 −1810 − −1475 −1810 − −1475 V VBB Output Reference Voltage −1.38 − −1.26 −1.38 − −1.26 −1.38 − −1.26 −1.38 − −1.26 V VCMR Common Mode (1) Range −1.3 − −0.4 −1.4 − −0.4 −1.4 − −0.4 −1.4 − −0.4 V IIH Input HIGH Current − − 150 − − 150 − − 150 − − 150 µA IIL Input LOW Current 0.5 − − 0.5 − − 0.5 − − 0.5 − − µA Note: 1. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPP (min.) and 1V. The lower end of the CMR range varies 1:1 with VEE. The numbers in the spec table assume a nominal VEE = −3.3V. Note for PECL operation, the VCMR (min.) will be fixed at 3.3V − IVCMR (min.)I. June 2011 5 M9999-060911 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY100S834/SY100S834L AC Electrical Characteristics(1) VEE = VEE (min.) to VEE (max.); VCC = GND. Symbol tPLH TA = −40°C Parameter TA = +25°C TA = 0°C TA = +85°C Unit Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Propagation Delay to Output CLK 960 1100 1200 960 1100 1200 960 1100 1200 960 1100 1200 ps MR 650 800 1010 650 800 1010 650 800 1010 650 800 1010 ps − − 50 − − 50 − − 50 − − 50 ps tPHL tSKEW Within-Device (2) Skew tS Set-Up Time EN 400 − − 400 − − 400 − − 400 − − ps tH Hold Time EN 200 − − 200 − − 200 − − 200 − − ps VPP Minimum Input Swing 250 − − 250 − − 250 − − 250 − − mV tr Output Rise/Fall Times 275 400 525 275 400 525 275 400 525 275 400 525 ps tf Q (20% − 80%) Notes: 1. 2. Parametric values specified at: − 5V power supply range, 100S834 series: −4.2V to −5.5V − 3V power supply range, 100S834L series: −3.0V to −3.8V Within-Device Skew is specified for identical transition. June 2011 6 M9999-060911 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY100S834/SY100S834L Timing Diagram The EN signal will freeze the internal clocks to the flip-flops on the first falling edge of CLK after its assertion. The internal dividers will maintain their state during the internal clock freeze and will return to clocking once the internal clocks are unfrozen. The outputs will transition to their next states in the same manner, time, and relationship as they would have had the EN signal not been asserted. June 2011 7 M9999-060911 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY100S834/SY100S834L Package Information xx-Pin Package Type (code) MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2006 Micrel, Incorporated. June 2011 8 M9999-060911 hbwhelp@micrel.com or (408) 955-1690