SY87701LZG

3.3V 32-1250Mbps AnyRate® SY87701L SY87701L CLOCK AND DATA RECOVERY Use lower-power SY87701AL for new designs Micrel, Inc. DESCRIPTION FEATURES ■ Industrial temperature range (–40°C to +85°C) ■ 3.3V power supply ■ Clock and data recovery from 32Mbps up to 1.25Gbps NRZ data stream, clock generation from 32Mbps to 1.25Gbps ■ Complies with Bellcore, ITU/CCITT and ANSI specifications for applications such as OC-1, OC-3, OC-12, ATM, FDDI, Fibre Channel and Gigabit Ethernet as well as proprietary applications ■ Two on-chip PLLs: one for clock generation and another for clock recovery ■ Selectable reference frequencies ■ Differential PECL high-speed serial I/O ■ Line receiver input: no external buffering needed ■ Link fault indication ■ 100k ECL compatible I/O ■ Available in 32-pin EPAD-TQFP and 28-pin SOIC packages (28-pin SOIC is available, but NOT recommended for new designs.) The SY87701L is a complete Clock Recovery and Data Retiming integrated circuit for data rates from 32Mbps up to 1.25Gbps NRZ. The device is ideally suited for SONET/SDH/ATM and Fibre Channel applications and other high-speed data transmission systems. Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the incoming data stream. The VCO center frequency is controlled by the reference clock frequency and the selected divide ratio. On-chip clock generation is performed through the use of a frequency multiplier PLL with a byte rate source as reference. The SY87701L also includes a link fault detection circuit. All support documentation can be found on Micrel’s web site at www.micrel.com. APPLICATIONS ■ ■ ■ ■ SONET/SDH/ATM OC-1, OC-3, OC-12, OC-24 Fibre Channel, Escon, SMPTE 259 Gigabit Ethernet/Fast Ethernet Proprietary architecture up to 1.25Gbps BLOCK DIAGRAM PLLR P/N RDINP (PECL) RDINN RDOUTP (PECL) PHASE DETECTOR RDOUTN RCLKP (PECL) 0 1 CHARGE PUMP VCO RCLKN PHASE/ FREQUENCY DETECTOR LINK FAULT DETECTOR CD (PECL) REFCLK (TTL) PHASE/ FREQUENCY DETECTOR CHARGE PUMP VCO 1 LFIN (TTL) TCLKP (PECL) 0 TCLKN VCC VCCA VCCO GND DIVIDER BY 8, 10, 16, 20 SY87701L DIVSEL 1/2 (TTL) FREQSEL 1/2/3 (TTL) PLLS P/N CLKSEL (TTL) AnyRate is a registered trademark of Micrel, Inc. M9999-111506 hbwhelp@micrel.com or (408) 955-1690 Rev.: G 1 Amendment: /0 Issue Date: Novembe 2006 Micrel, Inc. SY87701L PACKAGE/ORDERING INFORMATION Ordering Information(1) VCCA 1 28 VCC LFIN 2 27 CD DIVSEL1 3 26 DIVSEL2 RDINP 4 25 RDOUTP RDINN 5 24 RDOUTN FREQSEL1 6 23 VCCO REFCLK 7 22 RCLKP FREQSEL2 8 21 RCLKN FREQSEL3 9 20 VCCO N/C 10 19 TCLKP PLLSP 11 18 TCLKN PLLSN 12 17 CLKSEL GND 13 16 PLLRP GND 14 15 PLLRN Part Number Package Type Operating Range Package Marking Lead Finish SY87701LZI Z28-1 Industrial SY87701LZI Sn-Pb SY87701LZITR(2) Z28-1 Industrial SY87701LZI Sn-Pb SY87701LHI H32-1 Industrial SY87701LHI Sn-Pb SY87701LHITR(2) H32-1 Industrial SY87701LHI Sn-Pb SY87701LZG(3) Z28-1 Industrial SY87701LZG with Pb-Free bar line indicator NiPdAu Pb-Free SY87701LZGTR(2, 3) Z28-1 Industrial SY87701LZG with Pb-Free bar line indicator NiPdAu Pb-Free SY87701LHG H32-1 Industrial SY87701LHG with Pb-Free bar line indicator NiPdAu Pb-Free SY87701LHGTR(2, 3) H32-1 Industrial SY87701LHG with Pb-Free bar line indicator NiPdAu Pb-Free Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs. DIVSEL1 LFIN VCCA VCCA VCC VCC CD DIVSEL2 28-Pin SOIC (Z28-1) 32 31 30 29 28 27 26 25 NC RDINP RDINN FREQSEL1 REFCLK FREQSEL2 FREQSEL3 NC 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 RDOUTP RDOUTN VCCO RCLKP RCLKN VCCO TCLKP TCLKN PLLSP PLLSN GNDA GND GND PLLRN PLLRP CLKSEL 9 10 11 12 13 14 15 16 32-Pin EPAD TQFP (H32-1) M9999-111506 hbwhelp@micrel.com or (408) 955-1690 2 Micrel, Inc. SY87701L PIN DESCRIPTIONS Pin Number SOIC Pin Number TQFP Pin Name 4 5 2 3 RDINP, RDINN Serial Data Input (Differential PECL): These built-in line receiver inputs are connected to the differential receive serial data stream. An internal receive PLL recovers the embedded clock (RCLK) and data (RDOUT) information. The incoming data rate can be within one of five frequency ranges depending on the state of the FREQSEL pins. See “Frequency Selection” table. 7 5 REFCLK Reference Clock (TTL Inputs): This input is used as the reference for the internal frequency synthesizer and the “training” frequency for the receiver PLL to keep it centered in the absence of data coming in on the RDIN inputs. 27 26 CD Carrier Detect (PECL Input): This input controls the recovery function of the Receive PLL and can be driven by the carrier detect output of optical modules or from external transition detection circuitry. When this input is HIGH the input data stream (RDIN) is recovered normally by the Receive PLL. When this input is LOW the data on the inputs RDIN will be internally forced to a constant LOW, the data outputs RDOUT will remain LOW, the Link Fault Indicator output LFIN forced LOW and the clock recovery PLL forced to look onto the clock frequency generated from REFCLK. 6 8 9 4 6 7 FREQSEL1, FREQSEL2, FREQSEL3 3 26 32 25 DIVSEL1, DIVSEL2 Divider Select (TTL Inputs): These inputs select the ratio between the output clock frequency (RCLK/TCLK) and the REFCLK input frequency as shown in the “Reference Frequency Selection” table. 17 16 CLKSEL Clock Select (TTL Inputs): This input is used to select either the recovered clock of the receiver PLL (CLKSEL = HIGH) or the clock of the frequency synthesizer (CLKSEL = LOW) to the TCLK outputs. 2 31 LFIN Link Fault Indicator (TTL Output): This output indicates the status of the input data stream RDIN. Active HIGH signal is indicating when the internal clock recovery PLL has locked onto the incoming data stream. LFIN will go HIGH if CD is HIGH and RDIN is within the frequency range of the Receive PLL (1000ppm). LFIN is an asynchronous output. 25 24 24 23 RDOUTP, RDOUTN 22 21 21 20 RCLKP, RCLKN Clock Output (Differential PECL): These ECL 100k outputs represent the recovered clock used to sample the recovered data (RDOUT). 19 18 18 17 TCLKP, TCLKN Clock Output (Differential PECL): These ECL 100k outputs represent either the recovered clock (CLKSEL = HIGH) used to sample the recovered data (RDOUT) or the transmit clock of the frequency synthesizer (CLKSEL = LOW). 11 12 9 10 PLLSP, PLLSN Clock Synthesis PLL Loop Filter. External loop filter pins for the clock synthesis PLL. 16 15 15 14 PLLRP, PLLRN Clock Recovery PLL Loop Filter. External loop filter pins for the receiver PLL. 27, 28, VCC Supply Voltage(1) 1 29, 30 VCCA Analog Supply Voltage(1) 20, 23 19, 22 VCCO Output Supply Voltage(1) 13, 14 12, 13 GND Ground 10 1, 8 NC Pin Function Frequency Select (TTL Inputs): These inputs select the output clock frequency range as shown in the “Frequency Selection” table. Receive Data Output (Differential PECL): These ECL 100k outputs represent the recovered data from the input data stream (RDIN). This recovered data is specified against the rising edge of RCLK. No Connect Note: 1. VCC, VCCA, VCCO must be the same value. M9999-111506 hbwhelp@micrel.com or (408) 955-1690 3 Micrel, Inc. SY87701L FUNCTIONAL DESCRIPTION Lock Detect The SY87701L contains a link fault indication circuit which monitors the integrity of the serial data inputs. If the received serial data fails the frequency test, the PLL will be forced to lock to the local reference clock. This will maintain the correct frequency of the recovered clock output under loss of signal or loss of lock conditions. If the recovered clock frequency deviates from the local reference clock frequency by more than approximately 1000ppm, the PLL will be declared out of lock. The lock detect circuit will poll the input data stream in an attempt to reacquire lock to data. If the recovered clock frequency is determined to be within approximately 1000ppm, the PLL will be declared in lock and the lock detect output will go active. Clock Recovery Clock Recovery, as shown in the block diagram generates a clock that is at the same frequency as the incoming data bit rate at the Serial Data input. The clock is phase aligned by a PLL so that it samples the data in the center of the data eye pattern. The phase relationship between the edge transitions of the data and those of the generated clock are compared by a phase/frequency detector. Output pulses from the detector indicate the required direction of phase correction. These pulses are smoothed by an integral loop filter. The output of the loop filter controls the frequency of the Voltage Controlled Oscillator (VCO), which generates the recovered clock. Frequency stability without incoming data is guaranteed by an alternate reference input (REFCLK) that the PLL locks onto when data is lost. If the Frequency of the incoming signal varies by greater than approximately 1000ppm with respect to the synthesizer frequency, the PLL will be declared out of lock, and the PLL will lock to the reference clock. The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the minimum transition density expected in a received SONET data signal. This transfer function yields a 30µs data stream of continuous 1's or 0's for random incoming NRZ data. The total loop dynamics of the clock recovery PLL provides jitter tolerance which is better than the specified tolerance in GR-253-CORE. M9999-111506 hbwhelp@micrel.com or (408) 955-1690 4 Micrel, Inc. SY87701L CHARACTERISTICS Performance The SY87701L PLL complies with the jitter specifications proposed for SONET/SDH equipment defined by the Bellcore Specifications: GR-253-CORE, Issue 2, December 1995 and ITU-T Recommendations: G.958 document, when used with differential inputs and outputs. Jitter Transfer Jitter transfer function is defined as the ratio of jitter on the output OC-N/STS-N signal to the jitter applied on the input OC-N/STS-N signal versus frequency. Jitter transfer requirements are shown in Figure 2. Jitter Generation The jitter of the serial clock and serial data outputs shall not exceed .01 U.I. rms when a serial data input with no jitter is presented to the serial data inputs. Input Jitter Tolerance Input jitter tolerance is defined as the peak-to-peak amplitude of sinusoidal jitter applied on the input signal that causes an equivalent 1dB optical/electrical power penalty. SONET input jitter tolerance requirement condition is the input jitter amplitude which causes an equivalent of 1dB power penalty. A Jitter Transfer (dB) Sinusoidal Input Jitter Amplitude (UI p-p) 0.1 15 -20dB/decade -20dB/decade 1.5 -20dB/decade Acceptable Range -20 0.40 f0 f1 f2 f4 ft fc Frequency Frequency OC/STS-N Level f0 (Hz) f1 (Hz) f2 (Hz) f3 (kHz) ft (kHz) OC/STS-N Level fc (kHz) P (dB) 3 10 30 300 6.5 65 3 130 0.1 12 10 30 300 25 250 12 225 0.1 Figure 1. Input Jitter Tolerance M9999-111506 hbwhelp@micrel.com or (408) 955-1690 Figure 2. Jitter Transfer 5 Micrel, Inc. SY87701L FREQUENCY SELECTION TABLE FREQSEL1 FREQSEL2 FREQSEL3 fVCO/fRCLK fRCLK Data Rates (Mbps) 0 0 0 1 750 - 1250 0 0 1 2 375 - 625 0 1 0 4 188 - 313 0 1 1 6 125 - 208 1 0 0 8 94 - 157 1 0 1 12 63 - 104 1 1 0 16 47 - 78 1 1 1 24 32 - 52 LOOP FILTER COMPONENTS(1) REFERENCE FREQUENCY SELECTION DIVSEL1 DIVSEL2 fRCLK/fREFCLK 0 0 8 0 1 10 1 0 16 1 1 20 R5 C3 PLLSP PLLSN Wide Range R5 = 350Ω C3 = 1.0µF (X7R Dielectric) R6 PLLRP C4 PLLRN Wide Range R6 = 680Ω C4 = 1.0µF (X7R Dielectric) Note: 1. Suggested Values. Values may vary for different applications. M9999-111506 hbwhelp@micrel.com or (408) 955-1690 6 Micrel, Inc. SY87701L Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VCC) .................................. –0.5V to +4.0V Input Voltage (VIN) ......................................... –0.5V to VCC Output Current (IOUT) Continuous ............................................................. 50mA Surge .................................................................... 100mA Lead Temperature (soldering, 20 sec.) ..................... 260°C Storage Temperature (TS) ....................... –65°C to +150°C Supply Voltage (VCC) .............................. +3.15V to +3.45V Ambient Temperature (TA) ......................... –40°C to +85°C Package Thermal Resistance(3) SOIC (θJA)(4) ..................................................................... 80°C/W EPAD TQFP (θJA)(5) 0lfpm airflow ................................................. 27.6°C/W 200lfpm airflow ............................................. 22.6°C/W 500lfpm airflow ............................................. 20.7°C/W DC ELECTRICAL CHARACTERISTICS Symbol Parameter VCC Power Supply Voltage ICC Power Supply Current Condition Min Typ Max Units 3.15 3.3 3.45 V 170 230 mA PECL 100K DC ELECTRICAL CHARACTERISTICS VCC = VCCO = VCCA = 3.3V ±5%; TA = –40°C to +85°C; unless noted. Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VOH Output HIGH Voltage VOL IIL Condition Min Typ Max Units VCC –1.165 VCC –0.880 V VCC –1.810 VCC –1.475 V 50Ω to VCC –2V VCC –1.075 VCC –0.830 V Output LOW Voltage 50Ω to VCC –2V VCC –1.860 VCC –1.570 V Input LOW Current VIN = VIL(min) 0.5 µA TTL DC ELECTRICAL CHARACTERISTICS VCC = VCCO = VCCA = 3.3V ±5%; TA = –40°C to +85°C; unless noted. Symbol Parameter Condition Min VIH Input HIGH Voltage VIL Input LOW Voltage VOH Output HIGH Voltage IOH = –0.4mA VOL Output LOW Voltage IOL = 4mA IIH Input HIGH Current VIN = 2.7V, VCC = max. VIN = VCC, VCC = max. –175 2.0 Typ Max Units VCC V 0.8 V 2.0 IIL Input LOW Current VIN = 0.5V, VCC = max. –300 IOS Output Short Circuit Current VOUT = 0V (maximum 1 sec) –15 V 0.5 V +100 µA µA µA –100 mA Notes: 1. Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to “Absolute Maximum Ratings” conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Airflow of 500lfpm recommended for 28-pin SOIC. 4. 28-pin SOIC package is NOT recommended for new designs. 5. Using JEDEC standard test boards with die attach pad soldered to PCB. See www.amkor.com for additional package details. M9999-111506 hbwhelp@micrel.com or (408) 955-1690 7 Micrel, Inc. SY87701L AC ELECTRICAL CHARACTERISTICS VCC = VCCO = VCCA = 3.3V ±5%; TA = –40°C to +85°C; unless noted. Symbol Parameter Condition Min fVCO VCO Center Frequency fREFCLK × Byte Rate 750 ∆fVCO VCO Center Frequency Tolerance Nominal tACQ Acquisition Lock Time tCPWH REFCLK Pulse Width HIGH 4 ns tCPWL REFCLK Pulse Width LOW 4 ns tir REFCLK Input Rise Time tODC Output Duty Cycle (RCLK/TCLK) tr, tf ECL Output Rise/Fall Time (20% to 80%) tSKEW Recovered Clock Skew tDV Data Valid 1/(2 × fRCLK) – 200 ps tDH Data Hold 1/(2 × fRCLK) – 200 ps Max Units 1250 MHz 5 % 15 0.5 50Ω to VCC –2V tCPWL ns 45 55 % of UI 100 500 ps –200 +200 ps tCPWH REFCLK tODC tODC RCLK tSKEW tDV tDH RDOUT 8 µs 2 TIMING WAVEFORMS M9999-111506 hbwhelp@micrel.com or (408) 955-1690 Typ Micrel, Inc. SY87701L 32-PIN APPLICATION EXAMPLE R13 VCC LED D2 R12 Q1 2N2222A 27 26 DIVSEL2 28 CD 29 VCC 30 VCC 31 VCCA 32 VCCA DIODE D1 LFIN DIVSEL1 VEE 25 VCC NC 1N4148 R8 R9 R7 R6 R5 R3 R4 RDINP R10 RDINN 1 FREQSEL1 2 REFCLK 3 FREQSEL2 CLKSEL 4 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 CD 7 10 14 VCCA (+2V) L1 C6 0.1µF C7 6.8µF C8 6.8µF C9 6.8µF C11 0.1µF C13 0.1µF C15 0.1µF C12 0.01µF C14 0.01µF C16 0.01µF GND C10 6.8µF C17 0.1µF C18 0.01µF VEE (–3V) VEE C19 1.0µF C21 0.01µF C20 0.1µF VEEA (–3V) Note: C3, C4 are optional. C1 = C2 = 1.0µF R1 = 350Ω R2 = 680Ω R3 through R10 = 5kΩ R12 = 12kΩ R13 = 130Ω M9999-111506 hbwhelp@micrel.com or (408) 955-1690 9 CLKSEL VCC (+2V) L2 PLLRP VEE PLLRN VEE C2 VCCO (+2V) L3 16 R2 R1 Ferrite Bead BLM21A102 15 C4 C1 C5 22µF 13 C3 GND VCC 12 VEEA SW1 11 PLLSN PLLSP R11 1kΩ NC 24 DIVSEL2 6 VEE FREQSEL3 DIVSEL1 5 1 RDOUTP RDOUTN VCCO RCLKP RCLKN VCCO TCLKP TCLKN Micrel, Inc. SY87701L SW1 GND 28-PIN APPLICATION EXAMPLE VCC 1 2 3 4 5 (R17 - R22) 5kΩ x 6 6 R8 130Ω VCC Ferrite Bead BLM21A102 LED D2 0.1µF FB1 Stand Off 22µF C9 GND 1 VCC 2 LFIN R1 R2 C1 RDIN C2 R3 R4 See Table 1 GND 80Ω LOOP FILTER NETWORK 1.5µF REFCLK (TTL) C6 J1 VCC CD 27 DIVSEL2 26 4 RDINP RDOUTP 25 5 RDINN RDOUTN 24 R7 1kΩ 0.1µF 0.1µF C14 C15 7 REFCLK RCLKP 22 8 FREQSEL2 RCLKN 21 9 FREQSEL3 VCCO 20 10 N/C TCLKP 19 11 PLLSP TCLKN 18 12 PLLSN CLKSEL 17 0.1µF 0.1µF 13 GND PLLRP 16 14 GND PLLRN 15 C16 C17 0.1µF 0.1µF C18 C19 R6 50Ω If VCC = +3.3V: R9 through R14 = 220Ω C4 1.0µF VCC GND NC C5 DPDT Slide Switch XTAL Oscillator 14 0.1µF VCC Pin 1 (VCCA) 0.1µF C10 1
C13 8 Pin 28 (VCC) 0.1µF C11 7 Pin 23 (VCCO) 0.1µF C12 120Ω R21 Pin 20 (VCCO) 0.1µF For AC-Coupling Only For DC Mode Only C1 = C2 = 0.1µF C1 = C2 = Shorted R1 = R2 = 680Ω R1 = R2 = 130Ω R3 = R4 = 1kΩ R3 = R4 = 82Ω M9999-111506 hbwhelp@micrel.com or (408) 955-1690 Diode D1 1N4148 VCCO 23 R5 C3 22µF C7 VCC 28 3 DIVSEL1 6 FREQSEL1 C8 R11 R12 R13 R14 R15 R16 Capacitor Pads (1206 format) VCCA 0.1µF Note: 1. C5 and C10-C12 are decoupling capacitors and should be kept as close to the power pins as possible. 10 Micrel, Inc. SY87701L BILL OF MATERIALS (32-PIN EPAD-TQFP) Item Part Number Manufacturer C1, C2 VJ0603Y105JXJAT Vishay 1.0µF Ceramic Capacitor, Size 0603 X7R Dielectric, Loop Filter, Critical 2 C3, C4 VJ0603Y105JXJAT Vishay 1.0µF Ceramic Capacitor, Size 0603 X7R Dielectric, Loop Filter, Optional 2 C5 ECS-T1ED226R Panasonic 22µF Tantalum Electrolytic Capacitor, Size D 1 C6 ECU-V1H104KBW Panasonic 0.1µF Ceramic Capacitor, Size 1206 X7R Dielectric, Power Supply Decoupling 1 C7, C8, C9, C10 ECS-T1EC685R Panasonic 6.8µF Tantalum Electrolytic Capacitor, Size C 4 C19 ECJ-3YB1E105K Panasonic 1.0µF Ceramic Capacitor, Size 1206 X7R Dielectric, VEEA Decoupling 1 C11, C13 ECU-V1H104KBW Panasonic 0.1µF Ceramic Capacitor, Size 1206 X7R Dielectric, VCCO/VCC Decoupling 1 C15, C17 ECU-V1H104KBW Panasonic 0.1µF Ceramic Capacitor, Size 1206 X7R Dielectric, VCCA/VEEA Decoupling 1 C20 ECU-V1H104KBW Panasonic 0.1µF Ceramic Capacitor, Size 1206 X7R Dielectric, VEEA Decoupling 1 C12, C14 ECU-V1H103KBW Panasonic 0.01µF Ceramic Capacitor, Size 1206 X7R Dielectric, VCCO/VCC Decoupling 1 C16, C18 ECU-V1H103KBW Panasonic 0.01µF Ceramic Capacitor, Size 1206 X7R Dielectric, VCCA/VEEA Decoupling 1 C21 ECU-V1H103KBW Panasonic 0.01µF Ceramic Capacitor, Size 1206 X7R Dielectric, VEEA Decoupling 1 D1 1N4148 Diode 1 D2 P300-ND/P301-ND T-1 3/4 Red LED 1 J1, J2, J3, J4, J5 J6, J7, J8, J9, J10, J11, J12 142-0701-851 Johnson Components Gold Plated, Jack, SMA, PCB Mount 12 L1, L2, L3 BLM21A102F Murata Ferrite Beads, Power Noise Suppression 3 Q1 NTE123A Panasonic Qty 2N2222A Buffer/Driver Transistor, NPN 1 R1 350Ω Resistor, 2%, Size 0402 Loop Filter Component, Critical 1 R2 680Ω Resistor, 2%, Size 0402 Loop Filter Component, Critical 1 R3, R4, R5, R6 R7, R8, R9, R10 5kΩ Pull-up Resistors, 2%, Size 1206 8 R11 1kΩ Pull-down Resistor, 2%, Size 1206 1 R12 12kΩ Resistor, 2%, Size 1206 1 R13 130Ω Pull-up Resistor, 2%, Size 1206 1 SPST, Gold Finish, Sealed Dip Switch 1 SW1 206-7 M9999-111506 hbwhelp@micrel.com or (408) 955-1690 NTE Description CTS 11 Micrel, Inc. SY87701L 28 LEAD SOIC .300" WIDE (Z28-1) Rev. 02 Note: The 28 Lead SOIC package is NOT recommended for new designs. M9999-111506 hbwhelp@micrel.com or (408) 955-1690 12 Micrel, Inc. SY87701L 32 LEAD EPAD TQFP (DIE UP) (H32-1) Rev. 01 Package EP- Exposed Pad Die CompSide Island Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane PCB Thermal Consideration for 32-Pin EPAD-TQFP Package M9999-111506 hbwhelp@micrel.com or (408) 955-1690 13 Micrel, Inc. SY87701L APPENDIX A Layout and General Suggestions 1. 2. 3. 4. 5. 6. 7. 8. Establish controlled impedance stripline, microstrip, or co-planar construction techniques. Signal paths should have, approximately, the same width as the device pads. All differential paths are critical timing paths, where skew should be matched to within ±10ps. Signal trace impedance should not vary more than ±5%. If in doubt, perform TDR analysis of all high-speed signal traces. Maintain compact filter networks as close to filter pins as possible. Provide ground plane relief under filter path to reduce stray capacitance. Be careful of crosstalk coupling into the filter network. Maintain low jitter on the REFCLK input. Isolate the XTAL oscillator from power supply noise by adequately decoupling. Keep XTAL oscillator close to device, and minimize capacitive coupling from adjacent signals. Higher speed operation may require use of fundamental-tone (third-overtone typically have more jitter) crystal based oscillator for optimum performance. Evaluate and compare candidates by measuring TXCLK jitter. All unused outputs must be terminated. To conserve power, unused PECL outputs can be terminated with a 1kΩ resistor to VEE. MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2006 Micrel, Incorporated. M9999-111506 hbwhelp@micrel.com or (408) 955-1690 14