TC500COE

TC500/A/510/514 Precision Analog Front Ends with Dual Slope ADC Features: General Description: • Precision (up to 17 bits) A/D Converter “Front End” • 3-Pin Control Interface to Microprocessor • Flexible: User Can Trade-off Conversion Speed for Resolution • Single-Supply Operation (TC510/TC514) • 4 Input, Differential Analog MUX (TC514) • Automatic Input Voltage Polarity Detection • Low Power Dissipation: - (TC500/TC500A): 10 mW - (TC510/TC514): 18 mW • Wide Analog Input Range: - ±4.2V (TC500A/TC510) • Directly Accepts Bipolar and Differential Input Signals TheTC500/A/510/514 family are precision analog front ends that implement dual slope A/D converters having a maximum resolution of 17 bits plus sign. As a minimum, each device contains the integrator, zero crossing comparator and processor interface logic. The TC500 is the base (16-bit max) device and requires both positive and negative power supplies. The TC500A is identical to the TC500 with the exception that it has improved linearity, allowing it to operate to a maximum resolution of 17 bits. The TC510 adds an onboard negative power supply converter for singlesupply operation. The TC514 adds both a negative power supply converter and a 4-input differential analog multiplexer. Applications: • Precision Analog Signal Processor • Precision Sensor Interface • High Accuracy DC Measurements Each device has the same processor control interface consisting of 3 wires: control inputs (A and B) and zerocrossing comparator output (CMPTR). The processor manipulates A, B to sequence the TC5XX through four phases of conversion: auto-zero, integrate, deintegrate and integrator zero. During the auto-zero phase, offset voltages in the TC5XX are corrected by a closed loop feedback mechanism. The input voltage is applied to the integrator during the integrate phase. This causes an integrator output dv/dt directly proportional to the magnitude of the input voltage. The higher the input voltage, the greater the magnitude of the voltage stored on the integrator during this phase. At the start of the de-integrate phase, an external voltage reference is applied to the integrator and, at the same time, the external host processor starts its onboard timer. The processor maintains this state until a transition occurs on the CMPTR output, at which time the processor halts its timer. The resulting timer count is the converted analog data. Integrator zero (the final phase of conversion) removes any residue remaining in the integrator in preparation for the next conversion. The TC500/A/510/514 offer high resolution (up to 17 bits), superior 50/60 Hz noise rejection, low-power operation, minimum I/O connections, low input bias currents and lower cost compared to other converter technologies having similar conversion speeds. © 2008 Microchip Technology Inc. DS21428E-page 1 TC500/A/510/514 Package Types 16-Pin PDIP/SOIC/CERDIP 28-Pin PDIP/SOIC CINT 1 16 VDD VOUT – 1 28 CAP– VSS 2 15 DGND CINT 2 27 DGND CAZ 3 14 CMPTR OUT CAZ 3 26 CAP+ BUF 4 13 B 25 VDD TC500/ ACOM 5 TC500A 12 A BUF 4 ACOM 5 24 OSC CREF – 6 11 VIN+ CREF – 6 23 CMPTR OUT CREF+ 7 10 VIN – CREF+ 7 VREF – 8 VREF+ 9 20 A0 CH4– 10 19 A1 VREF − 8 9 VREF+ 24-Pin PDIP/SOIC 22 A TC514 21 B VOUT – 1 24 CAP– CH3– 11 18 CH1+ CINT 2 23 DGND CH2– 12 17 CH2+ CAZ 3 22 CAP+ CH1– 13 16 CH3+ N/C 14 15 CH4+ BUF 4 21 VDD ACOM 5 20 OSC CREF – 6 19 CMPTR OUT CREF+ 7 18 A VREF – 8 17 B VREF+ 9 16 VIN+ N/C 10 15 VIN – N/C 11 14 N/C N/C 12 13 N/C TC510 Typical Application RINT CREF A0 CH1+ CH2+ CH3+ CH4+ CH1CH2CH3CH4- A1 CREF+ DIF. MUX (TC514) CAZ BUF CREFBuffer + SWRI- SWRI- + A 0 0 1 1 B 0 1 0 1 SWZ SWIZ SWZ SW1 Analog Switch Control Signals VOUT- COUT- Level Shift CMPTR Output Polarity Detection SWRI+ SWRI- DC-TO-DC Converter (TC510 & TC514) Control Logic Converter Sate Zero Integrator Output Auto-Zero Signal Integrate De-integrate TC500 TC500A TC510 CMPTR 1 CMPTR 2 TC514 + + Phase Decoding Logic DGND CAP- CAP+ 1.0 μF DS21428E-page 2 CINT CAZ Integrator - SWI SWI VSS VREF- SWR SWR ACOM OSC VREF+ CINT 1.0 μF VSS (TC500 TC500A) A B Control Logic © 2008 Microchip Technology Inc. TC500/A/510/514 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† TC510/TC514 Positive Supply Voltage (VDD to GND) ......................................... +10.5V TC500/TC500A Supply Voltage (VDD to VSS) .............................................. +18V † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. TC500/TC500A Positive Supply Voltage (VDD to GND) ............................................ +12V TC500/TC500A Negative Supply Voltage (VSS to GND)................................................-8V Analog Input Voltage (VIN+ or VIN-) ............VDD to VSS Logic Input Voltage...............VDD +0.3V to GND - 0.3V Voltage on OSC: ........................... -0.3V to (VDD +0.3V) for VDD < 5.5V Ambient Operating Temperature Range: ................................................................ 0°C to +70°C Storage Temperature Range: ............. -65°C to +150°C DC CHARACTERISTICS Electrical Specifications: Unless otherwise specified, TC510/TC514: VDD = +5V, TC500/TC500A: VSS = ±5V. CAZ = CREF = 0.47 μF. Parameters TA = +25°C Sym Min. Typ. TA = 0°C to 70°C Max. Min. Typ. Units Conditions Max. Analog 60 — — — — — μV Zero-scale Error with Auto-zero Phase ZSE — — 0.005 — 0.005 0.012 % F.S. — — 0.003 — 0.003 0.009 End Point Linearity ENL — 0.005 0.015 — 0.015 0.060 % F.S. TC500/TC510/TC514 — — 0.010 — 0.010 0.045 % F.S. Note 1, Note 2, TC500A NL — 0.003 0.008 — — — % F.S. TC500/TC510/TC514, Note 1, Note 2 — — 0.005 — — — % F.S. TC500A Zero-scale Temp. Coefficient ZSTC — — — — 1 2 μV/°C Over Operating Temperature Range Full-scale Symmetry Error (Rollover Error) SYE — 0.01 — — 0.03 — % F.S. Note 1 Full-scale Temperature Coefficient FSTC — — — — 10 — ppm/°C Over Operating Temperature Range; External Reference TC = 0 ppm/°C Resolution Best-Case Straight Line Linearity Input Current TC500A IIN — 6 — — — — pA VCMR VSS + 1.5 — VDD – 1.5 VSS + 1.5 — VDD – 1.5 V Integrator Output Swing VSS + 0.9 — VDD – 0.9 VSS + 0.9 — VSS + 0.9 V Analog Input Signal Range VSS + 1.5 — VDD – 1.5 VSS + 1.5 — VSS + 1.5 V Common Mode Voltage Range Note 1: 2: 3: Note 1 TC500/TC510/TC514 VIN = 0V ACOM = GND = 0V Integrate time ≥ 66 ms, auto-zero time ≥ 66 ms, VINT (peak) ≈ 4V. End point linearity at ±1/4, ±1/2, ±3/4 F.S. after full-scale adjustment. Rollover error is related to CINT, CREF, CAZ characteristics. © 2008 Microchip Technology Inc. DS21428E-page 3 TC500/A/510/514 DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise specified, TC510/TC514: VDD = +5V, TC500/TC500A: VSS = ±5V. CAZ = CREF = 0.47 μF. Parameters TA = +25°C Sym TA = 0°C to 70°C Units Conditions Min. Typ. Max. Min. Typ. Max. VREF VSS +1 — VDD – 1 VSS +1 — VDD – 1 V VREF- VREF+ Comparator Logic 1, Output High VOH 4 — — 4 — — V ISOURCE = 400 μA Comparator Logic 0, Output Low VOL — — 0.4 — — 0.4 V ISINK = 2.1 mA Logic 1, Input High Voltage VIH 3.5 — — 3.5 — — V Logic 0, Input Low Voltage VIL — — 1 — — 1 V Logic Input Current IL — — — — 0.3 Comparator Delay tD — 2 — — 3 — μs -2.5 — 2.5 -2.5 — 2.5 V VDD = 5V — 6 10 — — — kΩ VDD = 5V Voltage Reference Range Digital μA Logic ‘1’ or ‘0’ Multiplexer (TC514 Only) Maximum Input Voltage Drain/Source ON Resistance RDSON Power (TC510/TC514 Only) Supply Current IS — 1.8 2.4 — — 3.5 mA VDD = 5V, A = 1, B = 1 Power Dissipation PD — 18 — — — — mW VDD = 5V Positive Supply Operating Voltage Range VDD 4.5 — 5.5 4.5 — 5.5 V Operating Source Resistance ROUT — 60 85 — — 100 Ω — 100 — — — — kHz Note 1 — — -10 — — -10 mA VDD = 5V Oscillator Frequency Maximum Current Out IOUT IOUT = 10 mA Power (TC500/TC500A Only) Supply Current IS — 1 1.5 — — 2.5 mA VS = ±5V, A = B = 1 Power Dissipation PD — 10 — — — — mW VDD = 5V, VSS = -5V Positive Supply Operating Range VDD 4.5 — 7.5 4.5 — 7.5 V Negative Supply Operating Range VSS -4.5 — -7.5 - 4.5 — -7.5 V Note 1: 2: 3: Integrate time ≥ 66 ms, auto-zero time ≥ 66 ms, VINT (peak) ≈ 4V. End point linearity at ±1/4, ±1/2, ±3/4 F.S. after full-scale adjustment. Rollover error is related to CINT, CREF, CAZ characteristics. DS21428E-page 4 © 2008 Microchip Technology Inc. TC500/A/510/514 2.0 TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: -0 5 4 TA = +25°C V+ = 5V Output Voltage (V) Output Voltage (V) 3 2 1 0 -1 -2 -3 -4 -5 Slope 60Ω -3 -4 -5 -6 -7 0 10 20 30 40 60 50 Load Current (mA) 70 0 80 Output Voltage vs. Load 4 6 8 10 12 14 Output Current (mA) 16 18 20 Output Voltage vs. Output 100 Output Source Resistance (Ω) V+ = 5V, TA = +25°C Osc. Freq. = 100 kHz 175 150 CAP = 1 µF 125 100 CAP = 10 µF 75 50 25 0 2 FIGURE 2-4: Current. 200 Output Ripple (mV PK-PK) -2 -8 FIGURE 2-1: Current. 0 1 FIGURE 2-2: Current. 2 3 4 5 6 7 Load Current (mA) 8 Output Ripple vs. Load 90 V+ = 5V IOUT = 10 mA 80 70 60 50 40 -50 9 10 0 25 50 Temperature (°C) -25 FIGURE 2-5: vs. Temperature. 100 10 1 1 FIGURE 2-3: Capacitance. 10 100 Oscillator Capacitance (pF) 1000 Oscillator Frequency vs. © 2008 Microchip Technology Inc. 75 100 Output Source Resistance 150 TA = +25°C V+ = 5V Oscillator Frequency (kHz) Oscillator Frequency (kHz) TA = +25°C -1 V+ = 5V 125 100 75 50 -50 -25 FIGURE 2-6: Temperature. 0 25 75 50 Temperature (°C) 100 125 Oscillator Frequency vs. DS21428E-page 5 TC500/A/510/514 NOTES: DS21428E-page 6 © 2008 Microchip Technology Inc. TC500/A/510/514 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: TC500, TC500A PIN FUNCTION TABLE TC510 CERDIP, PDIP, SOIC PDIP, SOIC TC514 Symbol Function PDIP, SOIC 1 2 2 CINT Integrator output. Integrator capacitor connection. 2 Not Used Not Used VSS Negative power supply input (TC500/TC500A only). 3 3 3 CAZ Auto-zero input. The auto-zero capacitor connection. 4 4 4 BUF Buffer output. The Integrator capacitor connection. 5 5 5 ACOM This pin is grounded in most applications. It is recommended that ACOM and the input common pin (Ven- or CHn-) be within the analog Common Mode Range (CMR). 6 6 6 CREF- Input. Negative reference capacitor connection. 7 7 7 CREF+ Input. Positive reference capacitor connection. 8 8 8 VREF- Input. External voltage reference (-) connection. 9 9 9 VREF+ Input. External voltage reference (+) connection. 10 15 Not Used VIN- Negative analog input. 11 16 Not Used VIN+ Positive analog input. 12 18 22 A Input. Converter phase control MSB. (See input B.) 13 17 21 B Input. Converter phase control LSB. The states of A, B place the TC5XX in one of four required phases. A conversion is complete when all four phases have been executed: Phase control input pins: AB = 00: Integrator zero 01: Auto-zero 10: Integrate 11: De-integrate 14 19 23 CMPTR OUT Zero crossing comparator output. CMPTR is high during the integration phase when a positive input voltage is being integrated and is low when a negative input voltage is being integrated. A highto-low transition on CMPTR signals the processor that the Deintegrate phase is completed. CMPTR is undefined during the autozero phase. It should be monitored to time the integrator zero phase. 15 23 27 DGND 16 21 25 VDD — 22 26 CAP+ Input. Negative power supply converter capacitor (+) connection. — 24 28 CAP- Input. Negative power supply converter capacitor (-) connection. — 1 1 VOUT- Output. Negative power supply converter output and reservoir capacitor connection. This output can be used to power other devices in the circuit requiring a negative bias voltage. — 20 24 OSC Oscillator control input. The negative power supply converter normally runs at a frequency of 100 kHz. The converter oscillator frequency can be slowed down (to reduce quiescent current) by connecting an external capacitor between this pin and VDD (see Section 2.0 “Typical Performance Curves”). — — 18 CH1+ Positive analog input pin. MUX channel 1. — — 13 CH1- Negative analog input pin. MUX channel 1. — — 17 CH2+ Positive analog input pin. MUX channel 2. — — 12 CH2- Negative analog input pin. MUX channel 2. — — 16 CH3+ Positive analog input pin. MUX channel 3. — — 11 CH3- Negative analog input pin. MUX channel 3. — — 15 CH4+ Positive analog input pin. MUX channel 4. — — 10 CH4- — — 20 A0 © 2008 Microchip Technology Inc. Input. Digital ground. Input. Power supply positive connection. Negative analog input pin. MUX channel 4 Multiplexer input channel select input LSB (see A1). DS21428E-page 7 TC500/A/510/514 TABLE 3-1: TC500, TC500A PIN FUNCTION TABLE (CONTINUED) TC510 CERDIP, PDIP, SOIC PDIP, SOIC — DS21428E-page 8 — TC514 Symbol Function PDIP, SOIC 19 A1 Multiplexer input channel select input MSB. Phase control input pins: A1, A0 = 00 = Channel 1 01 = Channel 2 10 = Channel 3 11 = Channel 4 © 2008 Microchip Technology Inc. TC500/A/510/514 4.1 Dual Slope Conversion Principles Actual data conversion is accomplished in two phases: input signal integration and reference voltage de-integration. The integrator output is initialized to 0V prior to the start of integration. During integration, analog switch S1 connects VIN to the integrator input where it is maintained for a fixed time period (TINT). The application of VIN causes the integrator output to depart 0V at a rate determined by the magnitude of VIN and a direction determined by the polarity of VIN. The deintegration phase is initiated immediately at the expiration of TINT. During de-integration, S1 connects a reference voltage (having a polarity opposite that of VIN) to the integrator input. At the same time, an external precision timer is started. The de-integration phase is maintained until the comparator output changes state, indicating the integrator has returned to its starting point of 0V. When this occurs, the precision timer is stopped. The deintegration time period (TDEINT), as measured by the precision timer, is directly proportional to the magnitude of the applied input voltage (see Figure 4-3). A simple mathematical equation relates the input signal, reference voltage and integration time: EQUATION 4-1: V REF C DEINT T 1 ------------------------ ∫ INT V IN ( T )DT = ------------------------------0 R INT C INT R INT C INT Where: VREF = Reference Voltage TINT = Signal Integration time (fixed) tDEINT = Reference Voltage Integration time (variable) For a constant VIN: EQUATION 4-2: V IN T DEINT = V REF -----------------T INT The dual slope converter accuracy is unrelated to the integrating resistor and capacitor values as long as they are stable during a measurement cycle. Integrating converters provide inherent noise rejection with at least a 20dB/decade attenuation rate. Interference signals with frequencies at integral multiples of the integration period are, theoretically, completely removed, since the average value of a sine wave of frequency (1/T) averaged over a period (T) is zero. Integrating converters often establish the integration period to reject 50/60 Hz line frequency interference signals. The ability to reject such signals is shown by a normal mode rejection plot (Figure 4-1). Normal mode rejection is limited in practice to 50 to 65 dB, since the line frequency can deviate by a few tenths of a percent (Figure 4-2). Normal Mode Rejection (dB) DETAILED DESCRIPTION 30 T = Measurment Period 20 10 0 0.1/T 1/T Input Frequency 10/T FIGURE 4-1: Integrating Converter Normal Mode Rejection. 80 Normal Mode Rejeciton (dB) 4.0 70 t = 0.1 sec 60 50 40 30 DEV SIN 60 p t (1 – 100 ) 60 p t (1 – DEV) 100 DEV = Deviation from 60 Hz t = Integration Period Normal Mode = 20 LOG Rejection 20 0.01 0.1 1.0 Line Frequency Deviation from 60 Hz (%) FIGURE 4-2: Line Frequency Deviation. An inherent benefit is noise immunity. Input noise spikes are integrated (averaged to zero) during the integration periods. Integrating ADCs are immune to the large conversion errors that plague successive approximation converters in high noise environments. © 2008 Microchip Technology Inc. DS21428E-page 9 TC500/A/510/514 CINT RINT Analog Input (VIN) Integrator – + ± VINT – Comparator Switch Driver Polarity Control Phase Control Control Logic Integrator Output A VIN ≈ VREF VIN ≈ 1/2 VREF TINT FIGURE 4-3: DS21428E-page 10 CMPTR Out + S1 Ref Voltage TC510 VSUPPLY VINT B I/O Microcomputer ROM Timer RAM Counter TDEINT Basic Dual Slope Converter. © 2008 Microchip Technology Inc. TC500/A/510/514 5.0 The internal analog switch status for each of these phases is summarized in Table 5-1. This table references the Typical Application. TC500/A/510/514 CONVERTER OPERATION The TC500/A/510/514 incorporates an auto-zero and Integrator phase in addition to the input signal Integrate and reference De-integrate phases. The addition of these phases reduce system errors, calibration steps and shorten overrange recovery time. A typical measurement cycle uses all four phases in the following order: 1. 2. 3. 4. Auto-zero. Input signal integration. Reference de-integration. Integrator output zero. TABLE 5-1: INTERNAL ANALOG GATE STATUS Conversion Phase Auto-zero (A = 0, B = 1) Input Signal Integration (A = 1, B = 0) SWI SWR+ SWR- SWZ SWR SW1 SWIZ — — — Closed Closed Closed — — — — Closed — — — Reference Voltage De-integration (A =1, B = 1) — * Closed — — — Closed — Integrator Output Zero (A = 0, B = 0) — — — — Closed Closed Closed * Assumes a positive polarity input signal. SW–RI would be closed for a negative input signal. 5.1 Auto-zero Phase (AZ) During this phase, errors due to buffer, integrator and comparator offset voltages are nulled out by charging CAZ (auto-zero capacitor) with a compensating error voltage. The external input signal is disconnected from the internal circuitry by opening the two SWI switches. The internal input points connect to analog common. The reference capacitor is charged to the reference voltage potential through SWR. A feedback loop, closed around the integrator and comparator, charges the capacitor (CAZ) with a voltage to compensate for buffer amplifier, integrator and comparator offset voltages. 5.2 Analog Input Signal Integration Phase (INT) The TC5XX integrates the differential voltage between the VIN+ and VIN– inputs. The differential voltage must be within the device’s Common mode range VCMR. The input signal polarity is normally checked via software at the end of this phase: CMPTR = 1 for positive polarity; CMPTR = 0 for negative polarity. © 2008 Microchip Technology Inc. 5.3 Reference Voltage De-integration Phase (DINT) The previously charged reference capacitor is connected with the proper polarity to ramp the integrator output back to zero. An externally-provided, precision timer is used to measure the duration of this phase. The resulting time measurement is proportional to the magnitude of the applied input voltage. 5.4 Integrator Output Zero Phase (IZ) This phase ensures the integrator output is at 0V when the auto-zero phase is entered, and that only system offset voltages are compensated. This phase is used at the end of the reference voltage de-integration phase and MUST be used for ALL TC5XX applications having resolutions of 12-bits or more. If this phase is not used, the value of the auto-zero capacitor (CAZ) must be about 2 to 3 times the value of the integration capacitor (CINT) to reduce the effects of charge sharing. The integrator output zero phase should be programmed to operate until the output of the comparator returns high. The overall timing system is shown in Figure 5-1. DS21428E-page 11 TC500/A/510/514 TTIME Converter Status Auto-zero Integrate Full-scale Input Reference De-integrate Overshoot Integrator Output Zero Integrator 0 Voltage VINT Comparator Delay Undefined Comparator Output A 0 For Negative Input 1 For Positive Input A=0 A=1 A=1 A=0 B=1 B=0 B=1 B=0 AB Inputs B Controller Operation Begin Conversion with Auto-Zero Phase Time Input Integration Phase Capture De-integration Time Integrator Ready for Next Output Conversion Zero Phase (Auto-Zero is Complete Idle State) Sample Input Polarity Typically = TINT TINT (Positive Input Shown) Comparator Delay + Processor Latency Minimizing Overshoot will Minimize I.O.Z. Time Notes: The length of this phase is chosen almost arbitrarily but needs to be long enough to null out worst case errors (see text). FIGURE 5-1: DS21428E-page 12 Typical Dual Slope A/D Converter System Timing. © 2008 Microchip Technology Inc. TC500/A/510/514 6.0 ANALOG SECTION 6.1 Differential Inputs (VIN+, VIN–) The difference in reference for (+) or (-) input voltages will cause a rollover error. This error can be minimized by using a large reference capacitor in comparison to the stray capacitance. The TC5XX operates with differential voltages within the input amplifier Common mode range. The amplifier Common mode range extends from 1.5V below positive supply to 1.5V above negative supply. Within this Common mode voltage range, Common mode rejection is typically 80 dB. Full accuracy is maintained, however, when the inputs are no less than 1.5V from either supply. 6.4 Phase Control Inputs (A, B) The A, B unlatched logic inputs select the TC5XX operating phase. The A, B inputs are normally driven by a microprocessor I/O port or external logic. 6.5 Comparator Output The integrator output also follows the Common mode voltage. The integrator output must not be allowed to saturate. A worst-case condition exists, for example, when a large, positive Common mode voltage, with a near full-scale negative differential input voltage, is applied. The negative input signal drives the integrator positive when most of its swing has been used up by the positive Common mode voltage. For these critical applications, the integrator swing can be reduced. The integrator output can swing within 0.9V of either supply without loss of linearity. By monitoring the comparator output during the fixed signal integrate time, the input signal polarity can be determined by the microprocessor controlling the conversion. The comparator output is high for positive signals and low for negative signals during the signal integrate phase (see Figure 6-1). 6.2 The internal comparator delay is 2 μs, typically. Figure 6-1 shows the comparator output for large positive and negative signal inputs. For signal inputs at or near zero volts, however, the integrator swing is very small. If Common mode noise is present, the comparator can switch several times during the beginning of the signal integrate period. To ensure that the polarity reading is correct, the comparator output should be read and stored at the end of the signal integrate phase. Analog Common Analog common is used as VIN return during system zero and reference de-integrate. If VIN– is different from analog common, a Common mode voltage exists in the system. This signal is rejected by the excellent CMR of the converter. In most applications, VIN– will be set at a fixed known voltage (i.e., power supply common). A Common mode voltage will exist when VIN– is not connected to analog common. 6.3 Differential Reference (VREF+, VREF–) The reference voltage can be anywhere within 1V of the power supply voltage of the converter. Rollover error is caused by the reference capacitor losing or gaining charge due to stray capacitance on its nodes. Integrator Output Signal Integrate Zero Crossing Comparator Output The comparator output is undefined during the autozero phase and is used to time the integrator output zero phase. (See Section 8.6 “Integrator Output Zero Phase”). Signal Integrate Reference De-integrate Integrator Output Zero Crossing Comparator Output A. Positive Input Signal FIGURE 6-1: Reference Deintegrate During the reference de-integrate phase, the comparator output will make a high-to-low transition as the integrator output ramp crosses zero. The transition is used to signal the processor that the conversion is complete. B. Negative Input Signal Comparator Output. © 2008 Microchip Technology Inc. DS21428E-page 13 TC500/A/510/514 NOTES: DS21428E-page 14 © 2008 Microchip Technology Inc. TC500/A/510/514 7.0 TYPICAL APPLICATIONS 7.1 Component Value Selection TABLE 7-1: Conversions Per Second Typical Value of CREF, CAZ (μF) Suggested* Part Number >7 0.1 SMR5 104K50J01L4 2 to 7 0.22 SMR5 224K50J02L4 2 or less 0.47 SMR5 474K50J04L4 The procedure outlined below allows the user to arrive at values for the following TC5XX design variables: 1. 2. 3. 4. Integration Phase Timing. Integrator Timing Components (RINT, CINT). Auto-zero and Reference Capacitors. Voltage Reference. 7.2 Select Integration Time Integration time must be picked as a multiple of the period of the line frequency. For example, TINT times of 33 ms, 66 ms and 132 ms maximize 60 Hz line rejection. 7.3 DINT and IZ Phase Timing The duration of the DINT phase is a function of the amount of voltage stored on the integrator during TINT and the value of VREF. The DINT phase must be initiated immediately following INT and terminated when an integrator output zero-crossing is detected. In general, the maximum number of counts chosen for DINT is twice that of INT (with VREF chosen at VIN(MAX) /2). 7.4 The value of RINT is, therefore, directly calculated in the following equation: 7.6 The integrating capacitor must be selected to maximize integrator output voltage swing. The integrator output voltage swing is defined as the absolute value of VDD (or VSS) less 0.9V (i.e., IVDD - 0.9VI or IVSS + 0.9VI). Using the 20 μA buffer maximum output current, the value of the integrating capacitor is calculated using the following equation. EQUATION 7-2: –6 ( T INT ) ( 20 × 10 ) C INT = -------------------------------------------( V S – 0.9 ) Where: TINT = Integration Period VS = IVDDI or IVSSI, whichever is less (TC500/A) VS = IVDDI (TC510, TC514) It is critical that the integrating capacitor has a very low dielectric absorption. Polypropylene capacitors are an example of one such dialectic. Polyester and polybicarbonate capacitors may also be used in less critical applications. Table 7-2 summarizes recommended capacitors for CINT. V IN ( MAX ) R INT ( in M Ω ) = ---------------------20 Where: VIN(MAX) = RINT = Calculate Integrating Capacitor (CINT) TABLE 7-2: EQUATION 7-1: RECOMMENDED CAPACITOR FOR CINT Suggested Part Number* Value Maximum input voltage (full count voltage) 0.1 SMR5 104K50J01L4 0.22 SMR5 224K50J02L4 Integrating Resistor (in MΩ) 0.33 SMR5 334K50J03L4 0.47 SMR5 474K50J04L4 For loop stability, RINT should be ≥ 50 kΩ 7.5 * Manufactured by Evox Rifa, Inc. Calculate Integrating Resistor (RINT) The desired full-scale input voltage and amplifier output current capability determine the value of RINT. The buffer and integrator amplifiers each have a full-scale current of 20 μA. CREF AND CAZ SELECTION Select Reference (CREF) and Autozero (CAZ) Capacitors CREF and CAZ must be low leakage capacitors (such as polypropylene). The slower the conversion rate, the larger the value CREF must be. Recommended capacitors for CREF and CAZ are shown in Table 7-1. Larger values for CAZ and CREF may also be used to limit rollover errors. © 2008 Microchip Technology Inc. * Manufactured by Evox Rifa, Inc. 7.7 Calculate VREF The reference de-integration voltage is calculated using the following equation: EQUATION 7-3: ( V S – 0.9 ) ( C INT ) ( R INT ) V REF = ----------------------------------------------------------- V 2 ( T INT ) DS21428E-page 15 TC500/A/510/514 NOTES: DS21428E-page 16 © 2008 Microchip Technology Inc. TC500/A/510/514 8.0 DESIGN CONSIDERATIONS 8.1 Noise 8.3 The threshold noise (NTH) is the algebraic sum of the integrator and comparator noise and is typically 30 μV. Figure 8-1 illustrates how the value of the reference voltage can affect the final count. Such errors can be reduced by increased integration times, in the same way that 50/60 Hz noise is rejected. The signal-tonoise ratio is related to the integration time (TINT) and the integration time constant (RINT, CINT) as follows: EQUATION 8-1: t INT ⎛ V IN ⎞ - • --------------------------------------⎟ S/N (dB) = 20 log ⎜ ---------------------–6 ( R ⎝ 30 × 10 INT ) • ( C INT )⎠ 8.2 System Timing To obtain maximum performance from the TC5XX, the overshoot at the end of the de-integration phase must be minimized. Also, the integrator output zero phase must be terminated as soon as the comparator output returns high (see Figure 5-1). Figure 5-1 shows the overall timing for a typical system in which a TC5XX is interfaced to a microcontroller. The microcontroller drives the A, B inputs with I/O lines and monitors the comparator output (CMPTR) using an I/O line or dedicated timer capture control pin. It may be necessary to monitor the state of the CMPTR output in addition to having it control a timer directly for the Reference de-integration phase (this is further explained below.) The timing diagram in Figure 5-1 is not to scale, as the timing in a real system depends on many system parameters and component value selections. There are four critical timing events (as shown in Figure 5-1): sampling the input polarity, capturing the de-integration time, minimizing overshoot and properly executing the integrator output zero phase. Auto-zero Phase The length of this phase is usually set to be equal to the input signal integration time. This decision is virtually arbitrary since the magnitudes of the various system errors are not known. Setting the auto-zero time equal to the Input Integrate time should be more than adequate to null out system errors. The system may remain in this phase indefinitely (i.e., auto-zero is the appropriate Idle state for a TC5XX device). 8.4 Input Signal Integrate Phase The length of this phase is constant from one conversion to the next and depends on system parameters and component value selections. The calculation of TINT is shown elsewhere in this data sheet. At some point near the end of this phase, the microcontroller should sample CMPTR to determine the input signal polarity. This value is, in effect, the Sign Bit for the overall conversion result. Optimally, CMPTR should be sampled just before this phase is terminated by changing AB from 10 to 11. The consideration here is that, during the initial stage of input integration when the integrator voltage is low, the comparator may be affected by noise and its output unreliable. Once integration is well underway, the comparator will be in a defined state. 8.5 Reference De-integration The length of this phase must be precisely measured from the transition of AB from 10 to 11 to the fallingedge of CMPTR. The comparator delay contributes some error in timing this phase. The typical delay is specified to be 2 μs. This should be considered in the context of the length of a single count when determining overall system performance and possible single count errors. Additionally, overshoot will result in charge accumulating on the integrator once its output crosses zero. This charge must be nulled during the integrator output zero phase. S S 30 µV NTH NTH NTH Normal VREF Low VREF Slope (S) = FIGURE 8-1: S High VREF VREF N = Noise Threshold RINT CINT TH Noise Threshold. © 2008 Microchip Technology Inc. DS21428E-page 17 TC500/A/510/514 8.6 Integrator Output Zero Phase The comparator delay and the controller’s response latency may result in overshoot, causing charge buildup on the integrator at the end of a conversion. This charge must be removed or performance will degrade. The integrator output zero phase should be activated (AB = 00) until CMPTR goes high. It is absolutely critical that this phase be terminated immediately so that overshoot is not allowed to occur in the opposite direction. At this point, it can be assured that the integrator is near zero. Auto-zero should be entered (AB = 01) and the TC5XX held in this state until the next cycle is begun (see Figure 8-2). Zero Crossing Integrator Output Overshoot Comparator Output Comp Integrate Phase FIGURE 8-2: DS21428E-page 18 De-integrate Phase Integrator Zero Phase 8.7 8.7.1 Using the TC510/TC514 NEGATIVE SUPPLY VOLTAGE CONVERTER (TC510, TC514) A capacitive charge pump is employed to invert the voltage on VDD for negative bias within the TC510/ TC514. This voltage is also available on the VOUT– pin to provide negative bias elsewhere in the system. Two external capacitors are required to perform the conversion. Timing is generated by an internal state machine driven from an on-board oscillator. During the first phase, capacitor CF is switched across the power supply and charged to VS+. This charge is transferred to capacitor COUT– during the second phase. The oscillator normally runs at 100 kHz to ensure minimum output ripple. This frequency can be reduced by placing a capacitor from OSC to VDD. The relationship between the capacitor value is shown in Section 2.0 “Typical Performance Curves”. 8.7.2 ANALOG INPUT MULTIPLEXER (TC514) The TC514 is equipped with a four-input differential analog multiplexer. Input channels are selected using select inputs (A1, A0). These are high-true control signals (i.e., channel 0 is selected when (A1, A0 = 00). Overshoot. © 2008 Microchip Technology Inc. TC500/A/510/514 9.0 DESIGN EXAMPLES Refer to Figures 9-1 to 9-4. Given: Required Resolution: 16 bits (65,536 counts). Maximum VIN: ±2V Power Supply Voltage: +5V 60 Hz System Step 1. Pick integration time (tINT) as a multiple of the line frequency: 1/60 Hz = 16.6 ms. Use 4x line frequency. = 66 ms Step 2. Calculate RINT: RINT = VIN(MAX) /20 μA 2 /20 μA = 100 kΩ Step 3. Calculate CINT for maximum (4V) integrator output swing. CINT = (tINT) (20 x 10 –6) / (VS - 0.9) = (.066) (20 x 10 –6) / (4.1) = 0.32 μF (use closest value: 0.33 μF) Note: Step 4. Microchip recommended capacitor: Evox Rifa p/n: 5MR5 334K50J03L4. Choose CREF and CAZ based on conversion rate. Conversions/sec: = 1/(TAZ + TINT + 2 TINT + 2 ms) = 1/(66 ms +66 ms +132 ms +2 ms) = 3.7 conversions/sec From which CAZ = CREF = 0.22 μF (see Table 7-1) Note: Step 5. Microchip recommended capacitor: Evox Rifa p/n: 5MR5 224K50J02L4 Calculate VREF: EQUATION 9-1: ( V S – 0.9 ) ( C INT ) ( R INT ) V REF = ---------------------------------------------------------2 ( T INT ) –6 3 4.1 ) ( 0.33 × 10 ) ( 100 × 10 )= (------------------------------------------------------------------------–3 2 ( 66 × 10 ) = 1.025 ( V ) © 2008 Microchip Technology Inc. DS21428E-page 19 TC500/A/510/514 1 VOUTCINT 0.33 μF 2 CINT CAZ 0.22 μF 3 CAZ 1 μF 4 +5V RINT 100 kΩ MCP1525 5 6 CREF R2 0.22 μF 10 kΩ R3, 10 kΩ 1 μF 7 CAP+ VDD BUF 23 Typical Waveforms +5V 1 μF Pin 2 22 21 VIN+ +5V Pin 19 ACOM CREF- CMPTR CREF+ A B VIN+ ® PIC MCU 19 Pin 2 18 VIN- 17 Pin 19 16 INPUT+ INPUT- TC510 Design Sample. 1 CINT 0.33 μF CAZ 0.22 μF +5V RINT 100 kΩ CREF R2 0.22 μF 10 kΩ R3, 10 kΩ C1 0.01 μF VOUT- CAP- 2 C INT 3 4 1 μF TC510 24 VIN- 15 1 μF MCP1525 DGND 9 V REF+ 8 VREF- C1 0.01 μF FIGURE 9-1: CAP- 5 6 7 CAZ BUF DGND CAP+ TC514 A0 ACOM CREFCREF+ 9 V REF+ 8 VDD VREF- A1 CMPTR 28 27 25 +5V 22 19 Analog Mux Logic PIC®MCU 23 22 B 21 CH1- +5V 26 A CH1+ 1 μF 18 13 INPUT 1+ INPUT 1Typical Waveforms CH2+ 17 CH2- 12 CH3+ 16 CH3- 11 CH4+ 15 CH4- 10 INPUT 2+ INPUT 2- PIN 2 VIN+ INPUT 3+ INPUT 3- PIN 23 INPUT4+ INPUT4- PIN 2 VINPIN 23 FIGURE 9-2: DS21428E-page 20 TC514 Design Example. © 2008 Microchip Technology Inc. TC500/A/510/514 +5V 21 VDD 1 VOUT- CAP- 1 μF 24 CAP+ 22 7 CREF+ 1 μF CREF- 6 0.22 μF MCP1525 VREF+ 9 TC510 VREFPC Printer Port PORT 0378 Hex BUF 8 0.22 μF CAZ 3 B CINT 2 19 CMPTR VIN+ 16 18 3 17 10 VIN- 15 DGND 23 FIGURE 9-3: 0.01 μF 10 kΩ 1 μF 4 100 kΩ A 2 10 kΩ ACOM 5 0.33 μF 100 kΩ + 0.01 μF Input – TC510 To IBM® Compatible Printer Port. © 2008 Microchip Technology Inc. DS21428E-page 21 TC500/A/510/514 +5V + Input 1 – + Input 2 – + Input 3 – + Input 4 – 18 13 17 12 Port 0378 Hex CH1– CAP+ CH2+ 11 15 22 3 21 10 23 1 μF 26 10 kΩ MCP1525 0.22 μF CREF- 6 10 kΩ CH3– VREF+ 9 CH4+ 10 CH4– 19 1 μF CREF+ 7 CH2– 16 CH3+ 20 Analog Mux Control Logic IBM® Printer Port 2 25 1 28 CH1+ VDD VOUT CAP– TC514 VREF- 0.01 μF 8 10 kΩ A0 A1 BUF 4 A CAZ 3 100 kΩ 0.22 μF CINT 2 B 0.33 μF CMPTR ACOM 5 DGND 27 FIGURE 9-4: DS21428E-page 22 TC514 To IBM® Compatible Printer Port. © 2008 Microchip Technology Inc. TC500/A/510/514 10.0 PACKAGING INFORMATION 10.1 Package Marking Information 16-Lead CERDIP (300 mil) (TC500/TC500A) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 16-Lead PDIP (300 mil) (TC500/TC500A) TC500AIJE 0818256 Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN 16-Lead SOIC (300 mil) (TC500/TC500A) XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: TC500CPE e^^ 3 0818256 Example: TC500ACOE e^^ 3 0818256 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2008 Microchip Technology Inc. DS21428E-page 23 TC500/A/510/514 Package Marking Information (Continued) 24-Lead PDIP (300 mil) (TC510) Example: XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 24-Lead SOIC (300 mil) (TC510) TC510CPF 0818256 Example: XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead PDIP (300 mil) (TC514) 3 TC510COG e^^ 0818256 Example: XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SOIC (300 mil) (TC514) XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN DS21428E-page 24 TC514CPJ e^^ 3 0818256 Example: TC514COI e^^ 3 0818256 © 2008 Microchip Technology Inc. TC500/A/510/514           !"# $%' 2 %& %! %3" ) '  % 3$%  %"% %%144)))&  &43 N E1 NOTE 1 1 2 D E A2 A c L A1 b1 b E2 e 5% &  8&% 6!&(  $ 6+7- 6 6 69 : ; %  % %  < < %" $$*  / < < + &37%   < /  !" %  !" ="% -  < ,/ + &3="% - / >> , 9 8%   ; > % % 8 / <  8" 3  > < / ( / < ;/ ( / < , - , <  5 8"="% 8 ) 8"="% 9  ) 0+ $%&'   !"#$%! & '(!%&! %( %")%%%"   *$%+ %  % , &  "%   -./ 0+1 0 &    %#%!  ))% !%%           ) +,0 © 2008 Microchip Technology Inc. DS21428E-page 25 TC500/A/510/514  "&%     "      ""# $%' 2 %& %! %3" ) '  % 3$%  %"% %%144)))&  &43 N NOTE 1 E1 1 2 3 D E A A2 L A1 c b1 b e eB 5% &  8&% 6!&(  $ 6+7- 6 6 69 : ; %  % %  < <   ""3 3  / , / 0 % %  / < <  !" %  !" ="% -  , ,/  ""3="% -  / > 9 8%  ,/ // / % % 8 / , / 8" 3  >  / ( / ;  (  >  0 < < 5 8"="% 8 ) 8"="% 9  )* 0+ , $%&'   !"#$%! & '(!%&! %( %")%%%"   *$%+ %  % , &   "-"  %!"& "$   % !    "$   % !     %#"?  "  &  "%   -./ 0+1 0 &    %#%!  ))% !%%          ) +0 DS21428E-page 26 © 2008 Microchip Technology Inc. TC500/A/510/514  "&%  ( )%  )  * + ,-   () # $%' 2 %& %! %3" ) '  % 3$%  %"% %%144)))&  &43  D N E E1 NOTE 1 1 2 3 e b h α h A c φ A2 L A1 5% &  8&% 6!&(  $ β L1 88- - 6 6 69 : ; %  9 7%  < 0+ <  ""3 3  / < < %" $$*   < , 9 ="% -  ""3="% - /0+ 9 8%  ,0+ ;/ ,0+ +&$ @ % A  / < / 2 %8% 8  <  2 % % 8 -2 2 % I B < >B 8" 3   < ,, 8"="% ( , < /  " $%  D /B < /B  " $%0 %% & E /B < /B $%&'   !"#$%! & '(!%&! %( %")%%%"   *$%+ %  % , &   "-"  %!"& "$   % !    "$   % !     %#"/&&  "  &  "%   -./ 0+1 0 &    %#%!  ))% !%%    -21 $ &  '! !)% !%%  '$ $ &% !           ) +0 © 2008 Microchip Technology Inc. DS21428E-page 27 TC500/A/510/514  "&%  ( )%  )  * + ,-   () #  "%% $%' 2 %& %! %3" ) '  % 3$%  %"% %%144)))&  &43 DS21428E-page 28 © 2008 Microchip Technology Inc. TC500/A/510/514 ./ (0  "&%     "1      (""# $%' 2 %& %! %3" ) '  % 3$%  %"% %%144)))&  &43 N NOTE 1 E1 1 3 2 D E A2 A L A1 b1 c e b eB 5% &  8&% 6!&(  $ 6+7- 6 6 69 :  %  % %  < <   ""3 3  / , / 0 % %  / < <  !" %  !" ="% - > , ,/  ""3="% -  / > 9 8%  // / > % % 8 / , ; 8" 3  >  / ( / ;  (  > , 0 < < 5 8"="% 8 ) 8"="% 9  )* 0+ , $%&'   !"#$%! & '(!%&! %( %")%%%"   *$%+ %  % , &   "-"  %!"& "$   % !    "$   % !     %#"?  "  &  "%   -./ 0+1 0 &    %#%!  ))% !%%          ) +,0 © 2008 Microchip Technology Inc. DS21428E-page 29 TC500/A/510/514 ./ "&%  ( )%  OG  * + ,-   () # $%' 2 %& %! %3" ) '  % 3$%  %"% %%144)))&  &43 D N E E1 NOTE 1 1 2 3 b e α h h A A2 c φ L A1 β L1 5% &  8&% 6!&(  $ 88- - 6 6 69 :  %  9 7%  < 0+ <  ""3 3  / < < %" $$*   < , 9 ="% -  ""3="% - /0+ 9 8%  /0+ ;/ ,0+ +&$ @ % A  / < / 2 %8% 8  <  2 % % 8 -2 2 % I B < >B 8" 3   < ,, 8"="% ( , < /  " $%  D /B < /B  " $%0 %% & E /B < /B $%&'   !"#$%! & '(!%&! %( %")%%%"   *$%+ %  % , &   "-"  %!"& "$   % !    "$   % !     %#"/&&  "  &  "%   -./ 0+1 0 &    %#%!  ))% !%%    -21 $ &  '! !)% !%%  '$ $ &% !           ) +/0 DS21428E-page 30 © 2008 Microchip Technology Inc. TC500/A/510/514 .2 (0  "&%     "      (""# $%' 2 %& %! %3" ) '  % 3$%  %"% %%144)))&  &43 N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 5% &  8&% 6!&(  $ 6+7- 6 6 69 : > %  % %  < <   ""3 3   ,/ / 0 % %  / < <  !" %  !" ="% -  , ,,/  ""3="% -  >/ / 9 8%  ,/ ,;/  % % 8  , / 8" 3  >  / (  /  (  >  0 < < 5 8"="% 8 ) 8"="% 9  )* 0+ , $%&'   !"#$%! & '(!%&! %( %")%%%"   *$%+ %  % , &   "-"  %!"& "$   % !    "$   % !     %#"?  "  &  "%   -./ 0+1 0 &    %#%!  ))% !%%          ) +0 © 2008 Microchip Technology Inc. DS21428E-page 31 TC500/A/510/514 .2 "&%  ( )%  )  * + ,-   () # $%' 2 %& %! %3" ) '  % 3$%  %"% %%144)))&  &43 D N E E1 NOTE 1 1 2 3 b e h α A2 A h c φ L A1 L1 5% &  8&% 6!&(  $ β 88- - 6 6 69 : > %  9 7%  < 0+ <  ""3 3  / < < %" $$*   < , 9 ="% -  ""3="% - /0+ 9 8%  0+ ;/ ,0+ +&$ @ % A  / < / 2 %8% 8  <  2 % % 8 -2 2 %  I B < >B 8" 3  > < ,, 8"="% ( , < /  " $%  D /B < /B  " $%0 %% & E /B < /B $%&'   !"#$%! & '(!%&! %( %")%%%"   *$%+ %  % , &   "-"  %!"& "$   % !    "$   % !     %#"/&&  "  &  "%   -./ 0+1 0 &    %#%!  ))% !%%    -21 $ &  '! !)% !%%  '$ $ &% !           ) +/0 DS21428E-page 32 © 2008 Microchip Technology Inc. TC500/A/510/514 APPENDIX A: REVISION HISTORY Revision E (November 2008) • Updated Section 10.0 “Packaging Information”. Revision D (January 2006) • Undocumented changes. Revision C (January 2004) • Undocumented changes. Revision B (May 2002) • Undocumented changes. Revision A (March 2001) • Initial release of this document. © 2008 Microchip Technology Inc. DS21428E-page 33 TC500/A/510/514 NOTES: DS21428E-page 34 © 2008 Microchip Technology Inc. TC500/A/510/514 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Device Temperature Range Package Device Temperature Range Package TC500 TC500A TC510 TC514 16 Bit Analog Processor 16 Bit Analog Processor Precision Analog Front End Precision Analog Front End C I = 0°C to +70°C (Commercial) = 25°C to +85°C (Industrial) JE PE OE OE713 = = = = PF OG OG713 = = = PJ OI OI713 = = = Ceramic Dual In-line, (300 mil Body), 16-lead Plastic DIP, (300 mil Body), 16-lead Plastic SOIC, (300 mil Body), 16-lead Plastic SOIC, (300 mil Body), 16-lead (Tape and Reel) Plastic DIP, (300 mil Body), 24-lead Plastic SOIC, (300 mil Body), 24-lead Plastic SOIC, (300 mil Body), 24-lead (Tape and Reel) Plastic DIP, (300 mil Body), 28-lead Plastic SOIC, (300 mil Body), 28-lead Plastic SOIC, (300 mil Body), 28-lead (Tape and Reel) © 2008 Microchip Technology Inc. Examples: a) TC500ACOE: b) TC500ACOE713: c) TC500ACPE: d) TC500AIJE: a) TC500COE: b) TC500COE713: c) TC500CPE: d) TC500IJE: a) TC510COG: b) TC510COG713: c) TC510CPF: a) TC514COI: b) TC514COI713: c) TC514CPJ: Commercial Temp., 16LD SOIC package. Commercial Temp., 16LD SOIC package, Tape and Reel. Commercial Temp., 16LD PDIP package. Industrial Temp., 16LD CERDIP package. Commercial Temp., 16LD SOIC package. Commercial Temp., 16LD SOIC package, Tape and Reel. Commercial Temp., 16LD PDIP package. Industrial Temp., 16LD CERDIP package. Commercial Temp., 24LD PDIP package. Commercial Temp., 24LD PDIP package, Tape and Reel. Commercial Temp., 24LD PDIP package. Commercial Temp., 28LD PDIP package. Commercial Temp., 28LD PDIP package, Tape and Reel. Commercial Temp., 28LD PDIP package. DS21428E-page 35 TC500/A/510/514 NOTES: DS21428E-page 36 © 2008 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2008 Microchip Technology Inc. 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