TC7109/A
12-Bit A-Compatible Analog-to-Digital Converters
Features:
General Description:
• Zero Integrator Cycle for Fast Recovery from
Input Overloads
• Eliminates Cross-Talk in Multiplexed Systems
• 12-Bit Plus Sign Integrating A/D Converter with
Over Range Indication
• Sign Magnitude Coding Format
• True Differential Signal Input and Differential
Reference Input
• Low Noise: 15VP-P Typ.
• Input Current: 1pA Typ.
• No Zero Adjustment needed
• TTL Compatible, Byte Organized Tri-State
Outputs
• UART Handshake Mode for simple Serial Data
Transmissions
The TC7109A is a 12-bit plus sign, CMOS low power
Analog-to-Digital Converter (ADC). Only eight passive
components and a crystal are required to form a
complete dual slope integrating ADC.
Device Selection Table
Part Number
(TC7109X)*
Package
Temperature
Range
TC7109CKW
44-Pin PQFP
0°C to +70°C
TC7109CLW
44-Pin PLCC
0°C to +70°C
TC7109CPL
TC7109IJL
40-Pin PDIP
0°C to +70°C
40-Pin CERDIP
-25°C to +85°C
*The “A” version has a higher IOUT on the digital lines.
2002-2012 Microchip Technology Inc.
The improved VOH source current and other TC7109A
features make it an attractive per-channel alternative to
analog multiplexing for many data acquisition applications. These features include typical input bias current
of 1pA, drift of less than 1V/°C, input noise typically
15VP-P, and auto-zero. True differential input and reference allow measurement of bridge type transducers,
such as load cells, strain gauges and temperature
transducers.
The TC7109A provides a versatile digital interface. In
the Direct mode, Chip Select and HIGH/LOW byte
enable control parallel bus interface. In the Handshake
mode, the TC7109A will operate with industry standard
UARTs in controlling serial data transmission – ideal for
remote data logging. Control and monitoring of conversion timing is provided by the RUN/HOLD input and
Status output.
For applications requiring more resolution, see the
TC500, 15-bit plus sign ADC data sheet. The TC7109A
has improved over range recovery performance and
higher output drive capability than the original TC7109.
All new (or existing) designs should specify the
TC7109A wherever possible.
DS21456D-page 1
TC7109/A
Package Type
B11 1
B10 2
STATUS
GND
NC
5
4
3
2
1 44 43 42 41 40
REF IN+
POL
REF CAP+
OR
6
V+
B12
REF IN+
REF CAP+
REF CAP-
REF IN-
V+
NC
STATUS
GND
POL
OR
B12
44 43 42 41 40 39 38 37 36 35 34
REF INREF CAP-
44-Pin PLCC
44-Pin PQFP
33 IN HI
B11 7
39 IN HI
32 IN LO
B10 8
38 IN LO
B9 3
31 COMMON
B9 9
37 COMMON
B8 4
30 INT
B8 10
36 INT
B7
29 AZ
B7 11
28 NC
NC 12
33 BUFF
5
TC7109ACKW
TC7109CKW
NC 6
35 AZ
TC7109ACLW
TC7109CLW
34 NC
B6
7
27 BUFF
B6 13
B5
8
26 REF OUT
B5 14
32 REF OUT
B4
9
25 V-
B4 15
31 V-
B3 10
24 SEND
B3 16
30 SEND
B2 11
23 RUN/HOLD
B2 17
OSC SEL
BUFF
OSC OUT
OSC IN
OSC OUT
MODE
NC
CE/LOAD
LBEN
HBEN
B1
TEST
OSC SEL
BUFF
OSC OUT
OSC OUT
MODE
OSC IN
NC
CE/LOAD
HBEN
TEST
LBEN
B1
29 RUN/HOLD
18 19 20 21 22 23 24 25 26 27 28
12 13 14 15 16 17 18 19 20 21 22
40-Pin PDIP/CERDIP
GND
1
40 V+
STATUS
2
39 REF IN-
POL
3
38 REF CAP-
OR
B12
4
37 REF CAP+
5
36 REF IN+
B11
6
35 IN HI
B10
7
B9
8
B8
9
B7 10
B6 11
34 IN LO
TC7109A
TC7109
33 COMMON
32 INT
31 AZ
30 BUFF
B5 12
29 REF OUT
B4 13
28 V-
B3 14
B2 15
27 SEND
B1 16
25 BUFF OSC OUT
26 RUN/HOLD
TEST 17
24 OSC SEL
LBEN 18
23 OSC OUT
HBEN 19
22 OSC IN
CE/LOAD 20
21 MODE
NC = No internal connection
DS21456D-page 2
2002-2012 Microchip Technology Inc.
TC7109/A
Typical Application
AZ
ZI
Input 35
High
REF
IN39
AZ
ZI
30
Buffer
–
INT
33
Input Low 34
AZ
DE (±)
ZI
INT
17
High Order
Byte Inputs
Low Order
Byte Inputs
3 4 5 6 7 8 9 10 11 12 13 14 15 16
18
19
20
Integrator
–
+
DE
(+)
16 Three-State Outputs
Comparator
Comp
Out
LBEN
HBEN
CE/LOAD
14 Latches
AZ
ZI
DE
(+)
CINT
BUFF AZ
INT
31
32
+
DE
(–)
AZ
Common
REF
CAP38
CAZ
POL
OR
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
REF REF
CAP+ IN+
37
36
RINT
TEST
TC7109A
C REF
12-Bit Counter
Latch
DE
(–)
Clock
To Analog
Section
10mA
–
Comp Out
AZ
INT
DE (±)
ZI
Conversion
Control Logic
Oscillator and
Clock Circuitry
Handshake
Logic
+
6.2V
29
28
REF VOUT
2002-2012 Microchip Technology Inc.
40
V+
2
Status
26
22 23
RUN/
HOLD
OSC OSC OSC BUFF Mode
IN OUT SEL OSC
OUT
24
25
21
27
1
Send
GND
DS21456D-page 3
TC7109/A
1.0
ELECTRICAL
CHARACTERISTICS
*Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. These are stress ratings only and functional
operation of the device at these or any other conditions
above those indicated in the operation sections of the
specifications is not implied. Exposure to Absolute
Maximum Rating conditions for extended periods may
affect device reliability.
Absolute Maximum Ratings*
Positive Supply Voltage (GND to V+) ..................+6.2V
Negative Supply Voltage (GND to V-) .....................-9V
Analog Input Voltage (Low to High) (Note 1).... V+ to VReference Input Voltage:
(Low to High) (Note 1) ............................. V+ to VDigital Input Voltage:
(Pins 2-27) (Note 2) ...........................GND – 0.3V
Power Dissipation, TA < 70°C (Note 3)
CERDIP ......................................................2.29W
Plastic DIP ..................................................1.23W
PLCC ..........................................................1.23W
PQFP ..........................................................1.00W
Operating Temperature Range
Plastic Package (C) ......................... 0°C to +70°C
Ceramic Package (I) .....................-25°C to +85°C
Storage Temperature Range ..............-65°C to +150°C
TC7109/TC7109A ELECTRICAL SPECIFICATIONS
Electrical Characteristics: All parameters with V+ = +5V, V- = -5V, GND = 0V, TA = +25°C, unless otherwise indicated.
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
—
0
1
Measurement
Cycle
Zero Input Reading
-00008
±00008
+00008
Octal Reading VIN = 0V; Full Scale = 409.6mV
Ratio Metric Reading
37778
37778
40008
40008
Octal Reading VIN = VREF
VREF = 204.8mV
Non-Linearity (Max Deviation
from Best Straight Line Fit)
-1
±0.2
+1
Count
Full Scale = 409.6mV to 2.048V
Over Full Operating
Temperature Range
Rollover Error (Difference in Reading for
Equal Positive and Inputs near
(Full Scale)
-1
±0.02
+1
Count
Full Scale = 409.6mV to
2.048V Over Full Operating
Temperature Range
CMRR
Input Common Mode
Rejection Ratio
—
50
—
V/V
VCM ±1V, VIN = 0V
Full Scale = 409.6mV
VCMR
Common Mode Voltage Range
V- +1.5
—
V+ -1.5
V
Input High, Input Low and
Common Pins
eN
Noise (P-P Value Not
Exceeded 95% of Time)
—
15
—
V
VIN = 0V, Full Scale = 409.6mV
IIN
Leakage Current at Input
Analog
Overload Recovery Time (TC7109A)
NL
TCZS
Zero Reading Drift
—
1
10
pA
VIN, All Packages: +25°C
—
20
100
pA
C Device: 0°C TA +70°C
—
100
250
pA
I Device: -25°C TA +85°C
—
0.2
1
V/°C
VIN = 0V
Note 1: Input voltages may exceed supply voltages if input current is limited to ±100A.
2: Connecting any digital inputs or outputs to voltages greater than V+ or less than GND may cause destructive device
latch-up. Therefore, it is recommended that inputs from sources other than the same power supply should not be applied
to the TC7109A before its power supply is established. In multiple supply systems, the supply to the device should be
activated first.
3: This limit refers to that of the package and will not occur during normal operation.
DS21456D-page 4
2002-2012 Microchip Technology Inc.
TC7109/A
TC7109/TC7109A ELECTRICAL SPECIFICATIONS (Continued)
Electrical Characteristics: All parameters with V+ = +5V, V- = -5V, GND = 0V, TA = +25°C, unless otherwise indicated.
Symbol
Parameter
Min
Typ
Max
Unit
TCFS
Scale Factor Temperature Coefficient
—
1
5
V/°C
I+
Supply Current (V+ to GND)
—
700
1500
A
IS
Supply Current (V+ to V-)
VREF
Reference Out Voltage
TCREF
Test Conditions
VIN = 408.9mV = >77708
Reading, Ext Ref = 0ppm/°C
VIN = 0V, Crystal Oscillator
3.58MHz Test Circuit
—
700
1500
A
Pins 2-21, 25, 26, 27, 29 Open
-2.4
-2.8
-3.2
V
Referenced to V+, 25k
Between V+ and Ref Out
Ref Out Temperature Coefficient
—
80
—
ppm/°C
Output High Voltage
IOUT = 700A
3.5
4.3
—
V
25k Between V+ and Ref Out
0°C TA +70°C
Digital
VOH
VOL
TC7109: IOUT = 100A
Pins 3 -16, 18, 19, 20
TC7109A: IOUT = 700A
Output Low Voltage
—
0.2
0.4
A
IOUT = 1.6mA
Output Leakage Current
—
±0.01
±1
A
Pins 3 -16 High-Impedance
Control I/O Pull-up Current
—
5
—
F
Pins 18, 19, 20 VOUT = V+ – 3V
Mode Input at GND
Control I/O Loading
—
—
50
pF
HBEN, Pin 19; LBEN, Pin 18
VIH
Input High Voltage
2.5
—
—
V
Pins 18 -21, 26, 27
Referenced to GND
VIL
Input Low Voltage
—
—
1
V
Pins 18-21, 26, 27
Referenced to GND
Input Pull-up Current
—
—
5
25
—
—
A
A
Pins 26, 27; VOUT = V+ – 3V
Pins 17, 24; VOUT = V+ – 3V
tW
Input Pull-down Current
—
1
—
A
Pins 21, VOUT = GND = +3V
Oscillator Output Current, High
—
1
—
mA
VOUT – 2.5V
Oscillator Output Current, Low
—
1.5
—
mA
VOUT – 2.5V
Buffered Oscillator Output Current High
—
2
—
mA
VOUT – 2.5V
Buffered Oscillator Output Current Low
—
5
—
mA
VOUT – 2.5V
Mode Input Pulse Width
60
—
—
nsec
Note 1: Input voltages may exceed supply voltages if input current is limited to ±100A.
2: Connecting any digital inputs or outputs to voltages greater than V+ or less than GND may cause destructive device
latch-up. Therefore, it is recommended that inputs from sources other than the same power supply should not be applied
to the TC7109A before its power supply is established. In multiple supply systems, the supply to the device should be
activated first.
3: This limit refers to that of the package and will not occur during normal operation.
HANDLING PRECAUTIONS: These devices are CMOS and must be handled correctly to prevent damage. Package
and store only in conductive foam, antistatic tubes, or other conducting material. Use proper antistatic handling procedures. Do not connect in circuits under “power-on” conditions, as high transients may cause permanent damage.
2002-2012 Microchip Technology Inc.
DS21456D-page 5
TC7109/A
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Pin Number
(40-Pin PDIP)
PIN FUNCTION TABLE
Symbol
Description
1
GND
2
STATUS
Digital ground, 0V, ground return for all digital logic.
3
POL
Polarity – High for positive input.
4
OR
Over Range – High if over ranged (Three-State Data bit).
Output HIGH during integrate and de-integrate until data is latched. Output LOW when
analog section is in auto-zero or zero integrator configuration.
5
B12
Bit 12 (Most Significant bit) (Three-State Data bit).
6
B11
Bit 11 (Three-State Data bit).
7
B10
Bit 10 (Three-State Data bit).
8
B9
Bit 9 (Three-State Data bit).
9
B8
Bit 8 (Three-State Data bit).
10
B7
Bit 7 (Three-State Data bit).
11
B6
Bit 6 (Three-State Data bit).
12
B5
Bit 5 (Three-State Data bit).
13
B4
Bit 4 (Three-State Data bit).
14
B3
Bit 3 (Three-State Data bit).
15
B2
Bit 2 (Three-State Data bit).
16
B1
Bit 1 (Least Significant bit) (Three-State Data bit).
17
TEST
Input High – Normal operation. Input LOW – Forces all bit outputs HIGH.
Note: This input is used for test purposes only.
18
LBEN
Low Byte Enable – with MODE (Pin 21) LOW, and CE/LOAD (Pin 20) LOW, taking this pin
LOW activates low order byte outputs, B1–B8. With MODE (Pin 21) HIGH, this pin serves as
low byte flag output used in Handshake mode. (See Figure 3-7, Figure , and Figure 3-9.)
19
HBEN
High Byte Enable – with MODE (Pin 21) LOW, and CE/LOAD (Pin 20) LOW, taking this pin
LOW activates high order byte outputs, B9–B12, POL, OR. With MODE (Pin 21) HIGH, this
pin serves as high byte flag output used in Handshake mode. See Figures 3-7, 3-8, and 3-9.
20
CE/LOAD
Chip Enable/Load – with MODE (Pin 21) LOW, CE/LOAD serves as a master output enable.
When HIGH, B1–B12, POL, OR outputs are disabled. When MODE (Pin 21) is HIGH, a load
strobe is used in handshake mode. (See Figure 3-7, Figure , and Figure 3-9.)
21
MODE
Input LOW – Direct Output mode where CE/LOAD (Pin 20), HBEN (Pin 19), and LBEN (Pin
18) act as inputs directly controlling byte outputs. Input Pulsed HIGH - Causes immediate
entry into Handshake mode and output of data as in Figure 3-9.
Input HIGH – enables CE/LOAD (Pin 20), HBEN (Pin 19), and LBEN (Pin 18) as outputs,
Handshake mode will be entered and data output as in Figure 3-7 and Figure 3-9
at conversions completion.
22
OSC IN
23
OSC OUT
Oscillator Output.
24
OSC SEL
Oscillator Select – Input HIGH configures OSC IN, OSC OUT, BUFF OSC OUT as RC
oscillator – clock will be same phase and duty cycle as BUFF OSC OUT. Input LOW
configures OSC IN, OSC OUT for crystal oscillator - clock frequency will be 1/58 of frequency
at BUFF OSC OUT.
25
Oscillator Input.
BUFF OSC OUT Buffered Oscillator Output.
26
RUN/HOLD
Input HIGH – Conversions continuously performed every 8192 clock pulses.
Input LOW – Conversion in progress completed; converter will stop in auto-zero seven
counts before integrate.
27
SEND
Input - Used in Handshake mode to indicate ability of an external device to accept data.
Connect to V+ if not used.
28
V-
29
REF OUT
DS21456D-page 6
Analog Negative Supply – Nominally -5V with respect to GND (Pin 1).
Reference Voltage Output – Nominally 2.8V down from V+ (Pin 40).
2002-2012 Microchip Technology Inc.
TC7109/A
TABLE 2-1:
PIN FUNCTION TABLE (CONTINUED)
Pin Number
(40-Pin PDIP)
Symbol
30
BUFF
Note:
Description
Buffer Amplifier Output.
31
AZ
Auto-Zero Node – Inside foil of CAZ.
32
INT
Integrator Output – Outside foil of CINT.
33
COMMON
34
IN LO
Analog Common – System is auto-zeroed to COMMON.
Differential Input Low Side.
35
IN HI
36
REF IN+
Differential Input High Side.
37
REF CAP+
Reference Capacitor Positive.
38
REF CAP-
Reference Capacitor Negative.
39
REF IN-
40
V+
Differential Reference Input Positive.
Differential Reference Input Negative.
Positive Supply Voltage – Nominally +5V with respect to GND (Pin 1).
All Digital levels are positive true.
2002-2012 Microchip Technology Inc.
DS21456D-page 7
TC7109/A
3.0
DETAILED DESCRIPTION
(All Pin Designations Refer to 40-Pin DIP.)
3.1
Analog Section
The Typical Application diagram on page 3 shows a
block diagram of the analog section of the TC7109A.
The circuit will perform conversions at a rate determined by the clock frequency (8192 clock periods per
cycle), when the RUN/HOLD input is left open or
connected to V+. Each measurement cycle is divided
into four phases, as shown in Figure 3-1. They are:
(1) Auto-Zero (AZ), (2) Signal Integrate (INT), (3)
Reference De-integrate (DE), and (4) Zero Integrator
(ZI).
3.1.1
AUTO-ZERO PHASE
The buffer and the integrator inputs are disconnected
from input high and input low and connected to analog
common. The reference capacitor is charged to the reference voltage. A feedback loop is closed around the
system to charge the auto-zero capacitor, CAZ, to compensate for offset voltage in the buffer amplifier, integrator, and comparator. Since the comparator is
included in the loop, the AZ accuracy is limited only by
the noise of the system. The offset referred to the input
is less than 10V.
3.1.2
SIGNAL INTEGRATE PHASE
The buffer and integrator inputs are removed from common and connected to input high and input low. The
auto-zero loop is opened. The auto-zero capacitor is
placed in series in the loop to provide an equal and
opposite compensating offset voltage. The differential
voltage between input high and input low is integrated
for a fixed time of 2048 clock periods. At the end of this
phase, the polarity of the integrated signal is
determined. If the input signal has no return to the
converter’s power supply, input low can be tied to
analog common to establish the correct Common
mode voltage.
3.1.3
DE-INTEGRATE PHASE
Input high is connected across the previously charged
reference capacitor and input low is internally
connected to analog common. Circuitry within the chip
ensures the capacitor will be connected with the correct
polarity to cause the integrator output to return to the
zero crossing (established by auto-zero), with a fixed
slope. The time, represented by the number of clock
periods counted for the output to return to zero, is
proportional to the input signal.
DS21456D-page 8
3.1.4
ZERO INTEGRATOR PHASE
The ZI phase only occurs when an input over range
condition exists. The function of the ZI phase is to
eliminate residual charge on the integrator capacitor
after an over range measurement. Unless removed,
the residual charge will be transferred to the auto-zero
capacitor and cause an error in the succeeding
conversion.
The ZI phase virtually eliminates hysteresis, or “crosstalk” in multiplexed systems. An over range input on
one channel will not cause an error on the next channel
measured. This feature is especially useful in thermocouple measurements, where unused (or broken
thermocouple) inputs are pulled to the positive supply
rail.
During ZI, the reference capacitor is charged to the reference voltage. The signal inputs are disconnected
from the buffer and integrator. The comparator output is
connected to the buffer input, causing the integrator
output to be driven rapidly to 0V (Figure 3-1). The ZI
phase only occurs following an over range and lasts for
a maximum of 1024 clock periods.
3.1.5
DIFFERENTIAL INPUT
The TC7109A has been optimized for operation with
analog common near digital ground. With +5V and -5V
power supplies, a full ±4V full scale integrator swing
maximizes the analog section’s performance.
A typical CMRR of 86dB is achieved for input differential voltages anywhere within the typical Common
mode range of 1V below the positive supply, to 1.5V
above the negative supply. However, for optimum performance, the IN HI and IN LO inputs should not come
within 2V of either supply rail. Since the integrator also
swings with the Common mode voltage, care must be
exercised to ensure the integrator output does not saturate. A worst-case condition is near a full scale negative differential input voltage with a large positive
Common mode voltage. The negative input signal
drives the integrator positive when most of its swing
has been used up by the positive Common mode voltage. In such cases, the integrator swing can be
reduced to less than the recommended ±4V full scale
value, with some loss of accuracy. The integrator
output can swing to within 0.3V of either supply without
loss of linearity.
2002-2012 Microchip Technology Inc.
TC7109/A
3.1.6
DIFFERENTIAL REFERENCE
The reference voltage can be generated anywhere
within the power supply voltage of the converter. Rollover voltage is the main source of Common mode
error, caused by the reference capacitor losing or gaining charge, due to stray capacity on its nodes. With a
large Common mode voltage, the reference capacitor
can gain charge (increase voltage) when called upon to
de-integrate a positive signal and lose charge
(decrease voltage) when called upon to de-integrate a
negative input signal. This difference in reference for
(+) or (–) input voltages will cause a rollover error. This
error can be held to less than 0.5 count, worst-case, by
using a large reference capacitor in comparison to the
stray capacitance. To minimize rollover error from
these sources, keep the reference Common mode
voltage near or at analog common.
3.2
Digital Section
The digital section is shown in Figure 3-2 and includes
the clock oscillator and scaling circuit, a 12-bit binary
counter with output latches and TTL compatible threestate output drivers, UART handshake logic, polarity,
over range, and control logic. Logic levels are referred
to as LOW or HIGH.
Inputs driven from TTL gates should have 3k to 5k
pull-up resistors added for maximum noise immunity.
For minimum power consumption, all inputs should
swing from GND (LOW) to V+ (HIGH).
3.2.1
STATUS OUTPUT
During a conversion cycle, the Status output goes high
at the beginning of signal integrate and goes low onehalf clock period after new data from the conversion
has been stored in the output latches (see Figure 3-1).
The signal may be used as a “data valid” flag to drive
interrupts, or for monitoring the status of the converter.
(Data will not change while status is low.)
3.2.2
3.2.3
RUN/HOLD INPUT
With the RUN/HOLD input high, or open, the circuit
operates normally as a dual slope ADC, as shown in
Figure 3-1. Conversion cycles operate continuously
with the output latches updated after zero crossing in
the De-integrate mode. An internal pull-up resistor is
provided to ensure a HIGH level with an open input.
The RUN/HOLD input may be used to shorten conversion time. If RUN/HOLD goes LOW any time after zero
crossing in the De-integrate mode, the circuit will jump
to auto-zero and eliminate that portion of time normally
spent in de-integrate.
If RUN/HOLD stays or goes LOW, the conversion will
complete with minimum time in de-integrate. It will stay
in auto-zero for the minimum time and wait in auto-zero
for a HIGH at the RUN/HOLD input. As shown in
Figure 3-3, the Status output will go HIGH, 7 clock periods after RUN/HOLD is changed to HIGH, and the
converter will begin the integrate phase of the next
conversion.
The RUN/HOLD input allows controlled conversion
interface. The converter may be held at Idle in autozero with RUN/HOLD LOW. The conversion is started
when RUN/HOLD goes HIGH, and the new data is
valid when the Status output goes LOW (or is transferred to the UART; see “Handshake Mode”). RUN/
HOLD may now go LOW, terminating de-integrate and
ensuring a minimum auto-zero time before stopping to
wait for the next conversion. Conversion time can be
minimized by ensuring RUN/HOLD goes LOW during
de-integrate, after zero crossing, and goes HIGH after
the hold point is reached.
The required activity on the RUN/HOLD input can be
provided by connecting it to the buffered oscillator
output. In this mode, the input value measured
determines the conversion time.
MODE INPUT
The Output mode of the converter is controlled by the
MODE input. The converter is in its “Direct” Output
mode, when the MODE input is LOW or left open. The
output data is directly accessible under the control of
the chip and byte enable inputs (this input is provided
with a pull-down resistor to ensure a LOW level when
the pin is left open). When the MODE input is pulsed
high, the converter enters the UART Handshake mode
and outputs the data in 2 bytes, then returns to “Direct”
mode. When the MODE input is kept HIGH, the
converter will output data in the Handshake mode at
the end of every conversion cycle. With MODE = 0
(direct bus transfer), the send input should be tied to
V+. (See “Handshake Mode”.)
2002-2012 Microchip Technology Inc.
DS21456D-page 9
TC7109/A
ZI
Integrator
Saturates
AZ
Integrator Output
for Over Range Input
Zero Integrator
Phase forces
Integrator Output
to 0V
No Zero Crossing
Zero Crossing
Occurs
Zero Crossing
Detected
Integrator Output
for Normal Input
AZ
Phase I
INT
Phase II
DE
Phase III
AZ
Internal Clock
Internal Latch
Status Output
2048
Fixed
Counts
2048
Min.
Counts
Number of Counts to Zero Crossing
Proportional to VIN
FIGURE 3-1:
4096
Counts
Max
After Zero Crossing, Analog section will
be in Auto-Zero Configuration
Conversion Timing (RUN/HOLD) Pin High
TEST
High Order
Byte Outputs
B B B
POL OR 12 11 10
17
3
4
5
6
7
B
9
8
B
8
Low Order
Byte Outputs
B B B B
6 5 4 3
B
7
B
2
B
1
9 10 11 12 13 14 15 16
18
19
14 Three-State Outputs
20
LBEN
HBEN
CE/LOAD
14 Latches
12-Bit Counter
Latch
Clock
To
Analog
Section
COMP OUT
AZ
INT
DE (±)
ZI
Conversion
Control Logic
2
STATUS
FIGURE 3-2:
DS21456D-page 10
Oscillator and
Clock Circuitry
26
22
23
24
25
Handshake
Logic
21
RUN/ OSC OSC OSC BUFF MODE
IN OUT SEL OSC
HOLD
OUT
27
SEND
1
GND
Digital Section
2002-2012 Microchip Technology Inc.
TC7109/A
Determinated at
Zero Crossing
Detection
Auto-Zero Phase I
Min 1790 Counts
Max 2041 Counts
Static in
Hold State
INT
Phase II
Integrator Output
7 Counts
Internal Clock
Internal Latch
Status Output
RUN/HOLD Input
*
*Note: RUN/HOLD input is ignored until end of auto-zero phase.
FIGURE 3-3:
3.2.4
TC7109A RUN/HOLD Operation
TABLE 3-1:
DIRECT MODE
The data outputs (bits 1 through 8, low order bytes; bits
9 through 12, polarity and over range high order bytes)
are accessible under control of the byte and chip
enable terminals as inputs, with the MODE pin at a
LOW level. These three inputs are all active LOW.
Internal pull-up resistors are provided for an inactive
HIGH level when left open. When chip enable is LOW,
a byte enable input LOW will allow the outputs of the
byte to become active. A variety of parallel data
accessing techniques may be used, as shown in the
“Interfacing” section. (See Figure 3-4 and Table 3-1.)
The access of data should be synchronized with the
conversion cycle by monitoring the Status output. This
prevents accessing data while it is being updated and
eliminates the acquisition of erroneous data.
tCEA
CE/LOAD
As Input
tBEA
HBEN
As Input
LBEN
As Input
tDAB
High Byte
Data
tDAB
Data
Valid
Data
Valid
tDAC
Low Byte
Data
tDHC
Data
Valid
Symbol
TC7109A DIRECT MODE
TIMING REQUIREMENTS
Description
Min
Typ
Max
Units
tBEA
Byte Enable Width
200
500
—
nsec
tDAB
Data Access Time
from Byte Enable
—
150
300
nsec
tDHB
Data Hold Time
from Byte Enable
—
150
300
nsec
tCEA
Chip Enable Width
300
500
tDAC
Data Access Time
from Chip Enable
—
200
400
tDHC
Data Hold Time
from Chip Enable
—
200
400
3.2.5
nsec
nsec
nsec
HANDSHAKE MODE
An alternative means of interfacing the TC7109A to
digital systems is provided when the Handshake Output mode of the TC7109A becomes active in controlling
the flow of data, instead of passively responding to chip
and byte enable inputs. This mode allows a direct interface between the TC7109A and industry standard
UARTs with no external logic required. The TC7109A
provides all the control and flag signals necessary to
sequence the two bytes of data into the UART and initiate their transmission in serial form when triggered
into the Handshake mode. The cost of designing
remote data acquisition stations is reduced using serial
data transmission to minimize the number of lines to
the central controlling processor.
= High-Impedance
FIGURE 3-4:
Output Timing
TC7109A Direct Mode
2002-2012 Microchip Technology Inc.
DS21456D-page 11
TC7109/A
The MODE input controls the Handshake mode. When
the MODE input is held HIGH, the TC7109A enters the
Handshake mode after new data has been stored in the
output latches at the end of every conversion performed (see Figure 3-7 and Figure ). Entry into the
Handshake mode may be triggered on demand by the
MODE input. At any time during the conversion cycle,
the LOW-to-HIGH transition of a short pulse at the
MODE input will cause immediate entry into the Handshake mode. If this pulse occurs while new data is
being stored, the entry into Handshake mode is
delayed until the data is stable. The MODE input is
ignored in the Handshake mode, and until the
converter completes the output cycle and clears the
Handshake mode, data updating will be inhibited (see
Figure 3-9).
When the MODE input is HIGH, or when the converter
enters the Handshake mode, the chip and byte enable
inputs become TTL compatible outputs, which provide
the output cycle control signals (see Figure 3-7, Figure
and Figure 3-9). The SEND input is used by the converter as an indication of the ability of the receiving
device (such as a UART) to accept data in the Handshake mode. The sequence of the output cycle with
SEND held HIGH is shown in Figure 3-7. The Handshake mode (internal MODE HIGH) is entered after the
data latch pulse (the CE/LOAD, LBEN and HBEN
terminals are active as outputs, since MODE remains
HIGH).
The HIGH level at the SEND input is sensed on the
same HIGH-to-LOW internal clock edge. On the next
LOW-to-HIGH internal clock edge, the high order byte
(bits 9 through 12, POL, and OR) outputs are enabled
and the CE/LOAD and the HBEN outputs assume a
LOW level. The CE/LOAD output remains LOW for one
full internal clock period only; the data outputs remain
active for 1-1/2 internal clock periods; and the high byte
enable remains LOW for 2 clock periods.
The CE/LOAD output LOW level, or LOW-to-HIGH
edge, may be used as a synchronizing signal to ensure
valid data, and the byte enable as an output may be
used as a byte identification flag. With SEND remaining
HIGH, the converter completes the output cycle using
CE/LOAD and LBEN, while the low order byte outputs
(bits 1 through 8) are activated. When both bytes are
sent, the Handshake mode is terminated. The typical
UART interfacing timing is shown in Figure .
The SEND input is used to delay portions of the
sequence, or handshake, to ensure correct data transfer. This timing diagram shows an industry standard
HD6403 or CDP1854 CMOS UART to interface to
serial data channels. The SEND input to the TC7109A
is driven by the TBRE (Transmitter Buffer Register
Empty) output of the UART, and the CE/LOAD input of
the TC7109A drives the TBRL (Transmitter Buffer
Register Load) input to the UART. The eight transmitter
buffer register inputs accept the parallel data outputs.
With the UART transmitter buffer register empty, the
DS21456D-page 12
SEND input will be HIGH when the Handshake mode is
entered, after new data is stored. The high order byte
outputs become active and the CE/LOAD and HBEN
inputs will go LOW after SEND is sensed. When CE/
LOAD goes HIGH at the end of one clock period, the
high order byte data is clocked into the UART transmitter buffer register. The UART TBRE output will go LOW,
which halts the output cycle with the HBEN output
LOW, and the high order byte outputs active. When the
UART has transferred the data to the transmitter register and cleared the transmitter buffer register, the
TBRE returns HIGH. The high order byte outputs are
disabled on the next TC7109A internal clock HIGH-toLOW edge, and one-half internal clock later, the HBEN
output returns HIGH. The CE/LOAD and LBEN outputs
go LOW at the same time as the low order byte outputs
become active. When the CE/LOAD returns HIGH at
the end of one clock period, the low order data is
clocked into the UART transmitter buffer register, and
TBRE again goes LOW. The next TC7109A internal
clock HIGH-to-LOW edge will sense when TBRE
returns to a HIGH, disabling the data inputs. One-half
internal clock later, the Handshake mode is cleared,
and the CE/LOAD, HBEN and LBEN terminals return
HIGH and stay active, if MODE still remains HIGH.
Handshake output sequences may be performed on
demand by triggering the converter into Handshake
mode with a LOW-to-HIGH edge on the MODE input. A
handshake output sequence triggered is shown in
Figure 3-9. The SEND input is LOW when the
converter enters Handshake mode. The whole output
sequence is controlled by the SEND input, and the
sequence for the first (high order) byte is similar to the
sequence for the second byte.
Figure 3-9 also shows that the output sequence can
take longer than a conversion cycle. New data will not
be latched when the Handshake mode is still in progress and is, therefore, lost.
3.3
Oscillator
The oscillator may be over driven, or may be operated
as an RC or crystal oscillator. The OSCILLATOR
SELECT input optimizes the internal configuration of
the oscillator for RC or crystal operation. The OSCILLATOR SELECT input is provided with a pull-up resistor. When the OSCILLATOR SELECT input is HIGH or
left open, the oscillator is configured for RC operation.
The internal clock will be the same frequency and
phase as the signal at the BUFFERED OSCILLATOR
OUTPUT. Connect the resistor and capacitor as in
Figure . The circuit will oscillate at a frequency given by
f = 0.45/RC. A 100k resistor is recommended for useful ranges of frequency. The capacitor value should be
chosen such that 2048 clock periods are close to an
integral multiple of the 60Hz period for optimum 60Hz
line rejection.
2002-2012 Microchip Technology Inc.
TC7109/A
Clock
V+
24
22
23
25
OSC
SEL
OSC
IN
OSC
OUT
R
Buffered
OSC OUT
÷ 58
FOSC = 0.45/RC
FIGURE 3-5:
GND
TC7109A RC Oscillator
With OSCILLATOR SELECT input LOW, two on-chip
capacitors and a feedback device are added to the
oscillator. In this configuration, the oscillator will operate with most crystals in the 1MHz to 5MHz range, with
no external components (Figure ). The OSCILLATOR
SELECT input LOW inserts a fixed 458 divider circuit
between the BUFFERED OSCILLATOR OUTPUT and
the internal clock. A 3.58MHz TV crystal gives a
division ratio, providing an integration time given by:
EQUATION 3-1:
t = (2048 clock periods)
58
3.58 MHz
22
OSC OSC
SEL IN
C
V+ or Open
24
= 33.18 msec
23
25
OSC
OUT
Buffered
OSC OUT
Crystal
FIGURE 3-6:
Crystal Oscillator
The error is less than 1% from two 60Hz periods, or
33.33msec, which will give better than 40dB, 60Hz
rejection. The converter will operate reliably at conversion rates up to 30 per second, corresponding to a
clock frequency of 245.8kHz.
When the oscillator is to be over driven, the OSCILLATOR OUTPUT should be left open, and the over driving
signal should be applied at the OSCILLATOR INPUT.
The internal clock will be of the same duty cycle, frequency and phase as the input signal. When the
OSCILLATOR SELECT is at GND, the clock will be
1/58 of the input frequency.
Zero Crossing Occurs
Zero Crossing Detected
Integrator Output
Internal Clock
Internal Latch
Status Output
Mode Input
Internal Mode
UART
Norm
Send Sensed
Send Sensed
Terminates
UART Mode
Mode Low, not
in Handshake Mode
Disables Outputs
Send Input
CE/LOAD
CE/LOAD,
HBEN,
LBEN
HBEN
High Byte Data
Data Valid
LBEN
Mode High Activates
CE/LOAD, HBEN, LBEN
Low Byte Data
Data Invalid
= Don't Care
FIGURE 3-7:
= Three-State
High-Impendance
= Three-State
will Pull-up
TC7109A Handshake with Send Input Held Positive
2002-2012 Microchip Technology Inc.
DS21456D-page 13
TC7109/A
Zero Crossing Occurs
Zero Crossing Detected
Integrator Output
Internal Clock
Internal Latch
Status Output
Mode Input
Internal Mode
UART
Norm
Send
Sensed
Send
Sensed
Send
Sensed
Terminates
UART Mode
Send Input (UART TBRE)
CE/LOAD Output (UART TBRL)
HBEN
High Byte Data
Data Valid
LBEN
Low Byte Data
Data Valid
= Three-State High-Impedance
= Don't Care
FIGURE 3-8:
TC7109A Handshake – Typical UART Interface Timing
Zero Crossing Occurs
Zero Crossing Detected
Positive Transiton causes
Entry into UART Mode
Status Output unchanged
in UART Mode
Latch Pulse inhibited in UART Mode
Internal Clock
Internal Latch
Status Output
Mode Input
Internal Mode
DE Phase III
UART
Norm
Send
Sensed
Send
Sensed
Send
Sensed
Terminates
UART Mode
Send Input
CE/LOAD as Output
HBEN
High Byte Data
Data Valid
LBEN
Low Byte Data
Data Valid
= Don't Care
FIGURE 3-9:
DS21456D-page 14
= Three-State
High-Impedance
= Three-State
with Pull-up
TC7109A Handshake Triggered by Mode Input
2002-2012 Microchip Technology Inc.
TC7109/A
3.4
Test Input
The counter and its outputs may be tested easily. When
the TEST input is connected to GND, the internal clock
is disabled and the counter outputs are all forced into
the HIGH state. When the input returns to the 1/2
(V+ – GND) voltage or to V+ and one clock is input, the
counter outputs will all be clocked to the LOW state.
this very linear region over the input voltage range, but
small enough that undue leakage requirements are not
placed on the PC board. For 2.048V full scale, a 100k
resistor is recommended and for 409.6mV full scale, a
20k resistor is recommended. RINT may be selected for
other values of full scale by:
EQUATION 3-3:
The counter output latches are enabled when the TEST
input is taken to a level halfway between V+ and GND,
allowing the counter contents to be examined any time.
3.5
Component Value Selection
The integrator output swing for full scale should be as
large as possible. For example, with ±5V supplies and
COMMON connected to GND, the nominal integrator
output swing at full scale is ±4V. Since the integrator
output can go to 0.3V from either supply without significantly effecting linearity, a 4V integrator output swing
allows 0.7V for variations in output swing, due to component value and oscillator tolerances. With ±5V supplies and a Common mode voltage range of ±1V
required, the component values should be selected to
provide ±3V integrator output swing. Noise and rollover errors will be slightly worse than in the ±4V case.
For large Common mode voltage ranges, the integrator
output swing must be reduced further. This will
increase both noise and rollover errors. To improve
performance, ±6V supplies may be used.
3.5.1
INTEGRATING CAPACITOR
The integrating capacitor, CINT, should be selected to
give the maximum integrator output voltage swing that
will not saturate the integrator to within 0.3V from either
supply. A ±3.5V to ±4V integrator output swing is nominal for the TC7109A, with ±5V supplies and analog
common connected to GND. For 7-1/2 conversions per
second (61.72kHz internal clock frequency), nominal
values CINT and CAZ are 0.15F and 0.33F, respectively. These values should be changed if different
clock frequencies are used to maintain the integrator
output voltage swing. The value of CINT is given by:
EQUATION 3-2:
CINT =
(2048 Clock Period) (20 A)
Integrator Output Voltage Swings
The integrating capacitor must have low dielectric
absorption to prevent rollover errors. Polypropylene
capacitors give undetectable errors, at reasonable
cost, up to +85°C.
3.5.2
INTEGRATING RESISTOR
The integrator and buffer amplifiers have a class A output stage with 100A of quiescent current. They supply
20A of drive current with negligible non-linearity. The
integrating resistor should be large enough to remain in
2002-2012 Microchip Technology Inc.
Full Scale Voltage
RINT =
3.5.3
20 A
AUTO-ZERO CAPACITOR
As the auto-zero capacitor is made large, the system
noise is reduced. Since the TC7109A incorporates a
zero integrator cycle, the size of the auto-zero capacitor does not affect overload recovery. The optimal value
of the auto-zero capacitor is between 2 and 4 times
CINT. A typical value for CAZ is 0.33F.
The inner foil of CAZ should be connected to Pin 31 and
the outer foil to the RC summing junction. The inner foil
of CINT should be connected to the RC summing
junction and the outer foil to Pin 32, for best rejection of
stray pickups.
3.5.4
REFERENCE CAPACITOR
A 1F capacitor is recommended for most circuits.
However, where a large Common mode voltage exists,
a larger value is required to prevent rollover error (e.g.,
the reference low is not analog common), and a
409.6mV scale is used. The rollover error will be held
to 0.5 count with a 10F capacitor.
3.5.5
REFERENCE VOLTAGE
To generate full scale output of 4096 counts, the analog
input required is VIN = 2VREF. For 409.6mV full scale,
use a reference of 204.8mV. In many applications,
where the ADC is connected to a transducer, a scale
factor will exist between the input voltage and the digital
reading. For instance, in a measuring system, the
designer might like to have a full scale reading when
the voltage for the transducer is 700mV. Instead of
dividing the input down to 409.6mV, the designer
should use the input voltage directly and select
VREF = 350mV. Suitable values for integrating resistor
and capacitor would be 34k and 0.15F. This makes
the system slightly quieter and also avoids a divider
network on the input. Another advantage of this system
occurs when temperature and weight measurements,
with an offset or tare, are desired for non-zero input.
The offset may be introduced by connecting the voltage
output of the transducer between common and analog
high, and the offset voltage between common and analog low, observing polarities carefully. In processor
based systems using the TC7109A, it may be more
desirable to use software and perform this type of
scaling or tare subtraction digitally.
DS21456D-page 15
TC7109/A
3.5.6
REFERENCE SOURCES
A major factor in the absolute accuracy of the ADC is
the stability of the reference voltage. The 12-bit resolution of the TC7109A is one part in 4096, or 244 ppm.
Thus, for the on-board reference temperature coefficient of 70ppm/°C, a temperature difference of 3°C will
introduce a one-bit absolute error. Where the ambient
temperature is not controlled, or where high accuracy
absolute measurements are being made, it is
recommended that an external high quality reference
be used.
A reference output (Pin 29) is provided, which may be
used with a resistive divider to generate a suitable reference voltage (20mA may be sunk without significant
variation in output voltage). A pull-up bias device is provided, which sources about 10A. The output voltage is
nominally 2.8V below V+. When using the on-board
reference, REF OUT (Pin 29) should be connected to
REF IN- (pin 39), and REF IN+ should be connected to
the wiper of a precision potentiometer between REF
OUT and V+. The test circuit shows the circuit for a
204.8mV reference, generated by a 2k precision
potentiometer in series with a 24k fixed resistor.
DS21456D-page 16
2002-2012 Microchip Technology Inc.
TC7109/A
4.0
INTERFACING
4.1
Direct Mode
Combinations of chip enable and byte enable control
signals, which may be used when interfacing the
TC7109A to parallel data lines, are shown in Figure .
The CE/LOAD input may be tied low, allowing either byte
to be controlled by its own enable (see Figure (A)).
Figure (B) shows the HBEN and LBEN as flag inputs,
and CE/LOAD as a master enable, which could be the
READ strobe available from most microprocessors.
Figure (C) shows a configuration where the two byte
enables are connected together. The CE/LOAD is a
chip enable, and the HBEN and LBEN may be used as
a second chip enable, or connected to ground. The 14
data outputs will be enabled at the same time. In the
direct MODE, SEND should be tied to V+.
Figure shows interfacing several TC7109A’s to a bus,
ganging the HBEN and LBEN signals to several
converters together, and using the CE/LOAD input to
select the desired converter.
A.
B.
GND
MODE
CE/LOAD
B9 - B12
POL, OR
Analog In
MODE
LBEN
Figure 4-8 is a typical connection diagram. To ensure
requirements for setup and hold times, minimum pulse
widths, and the drive limitations on long busses are
met, it is necessary to carefully consider the system
timing in this type of interface. This type of interface is
used when the memory peripheral address density is
low, providing simple address decoding. Interrupt
handling can be simplified by using an interface to
reduce the component count.
C.
Chip Select
GND
CE/LOAD
MODE
14
Analog In
B1 - B8
Analog In
RUN/HOLD
Convert
HBEN
LBEN
CE/LOAD
B9 - B12
POL, OR
6
TC7109A
TC7109A
8
Control
FIGURE 4-1:
Direct interfacing to most microcontroller busses is
easily accomplished through the three-state output of
the TC7109A.
B1 - B12
POL, OR
6
RUN/HOLD
HBEN
The RUN/HOLD input is also used to initiate
conversions under software control.
Chip Select 1
GND
TC7109A
B1 - B8
Figure through Figure give practical circuits utilizing
the parallel three-state output capabilities of the
TC7109A. Figure shows parallel interface to the 8748/
49 systems via an 8255 PPI, where the TC7109A data
outputs are active at all times. This interface can be
used in a read-after-update sequence, as shown in
Figure . The data is accessed by the high-to-low
transition of the Status driving an interrupt to the
microcontroller.
8
RUN/HOLD
Convert
GND or
Chip Select 2
HBEN
LBEN
Convert
Byte Flags
Direct Mode Chip and Byte Enable Combination
2002-2012 Microchip Technology Inc.
DS21456D-page 17
TC7109/A
Converter Select
Converter Select
GND
Converter Select
GND
MODE
CE/LOAD
MODE
B9 - B12
POL, OR
MODE
6
RUN/HOLD
Analog In
HBEN
B1 - B8
8
Analog In
RUN/HOLD
+5V
LBEN
6
TC7109A
B1 - B8
8
CE/LOAD
B9 - B12
POL, OR
6
TC7109A
B1 - B8
HBEN
CE/LOAD
B9 - B12
POL, OR
TC7109A
Analog In
GND
RUN/HOLD
+5V
LBEN
HBEN
8
+5V
LBEN
Byte Select Flags
FIGURE 4-2:
Three-Stating Several TC7109As to a Small Bus
Address Bus
Control Bus
Data Bus
GND
Analog In
MODE CE/LOAD
B9 - B12
POL, OR
RUN/HOLD
TC7109A
B1 - B8
STATUS
HBEN
6
+5V
8
See Text
RD WR D7 - D0 A0 - A1
CS
PA5 - PA0
μPD8255A
(Mode 0)
PB7 - PB0
μPD8748H/49H
PC5
LBEN
GND
FIGURE 4-3:
DS21456D-page 18
Full Time Parallel Interface to PD8748H/494 Microcontrollers
2002-2012 Microchip Technology Inc.
TC7109/A
Address Bus
Control Bus
Data Bus
GND
Analog In
MODE CE/LOAD
B9 - B12
POL, OR
RD WR D7 - D0 A0 - A1
CS
6
PA5 - PA0
PC6
RUN/HOLD
TC7109A
B1 - B8
HBEN
LBEN
GND
FIGURE 4-4:
PB7 - PB0
8
STBA
STATUS
1mF
μPD8748H/49H
μPD8255A
PC6
PC4
INTRA
INTR
10kW
+5V
(See Text)
Full Time Parallel Interface to PD8748H/494 Microcontrollers
Address Bus
Control Bus
Data Bus
Analog In
B9 - B12
POL, OR
6
B1 - B8
8
TC7109A
CE/LOAD
SEND
FIGURE 4-5:
RD WR D7 - D0 A0 - A1
CS
STBA
IBFA
PA7 - PA0
μPD8255A
(Mode 1)
PC4
μPD8748H/49H
PC5
RUN/HOLD
PC6
PC
MODE
PC7
PC3
INTR
TC7109A Handshake Interface to PD8748H/494 Microcontrollers
2002-2012 Microchip Technology Inc.
DS21456D-page 19
TC7109/A
4.2
Handshake Mode
Conversions may be obtained on command under software control by driving the RUN/HOLD input to the
TC7109A by a bit of the 8255. Another peripheral
device may be serviced by the unused port of the 8255.
The Handshake mode provides an interface to a wide
variety of external devices. The byte enables may be
used as byte identification flags, or as load enables,
and external latches may be clocked by the rising edge
of CE/LOAD. A handshake interface to Intel® microprocessors using an 8255 PPI is shown in Figure . The
handshake operation with the 8255 is controlled by
inverting its Input Buffer Full (IBF) flag to drive the
SEND input to the TC7109A, and using the CE/LOAD
to drive the 8255 strobe. The internal control register of
the PPI should be set in MODE 1 for the port used. If
the 8255 IBF flag is LOW and the TC7109A is in Handshake mode, the next word will be strobed into the port.
The strobe will cause IBF to go HIGH (SEND goes
LOW), which will keep the enabled byte outputs active.
The PPI will generate an interrupt which, when
executed, will result in the data being read. The IBF will
be reset LOW when the byte is read, causing the
TC7109A to sequence into the next byte. The MODE
input to the TC7109A is connected to the control line on
the PPI.
The Handshake mode is particularly useful for directly
interfacing to industry standard UARTs (such as Intersil
HD-6402), providing a means of serially transmitting
converted data with minimum component count.
A typical UART connection is shown in Figure . In this
circuit, any word received by the UART causes the
UART DR (Data Ready) output to go HIGH. The MODE
input to the TC7109A goes HIGH, triggering the
TC7109A into Handshake mode. The high order byte is
output to the UART and when the UART has transferred the data to the Transmitter register, TBRE
(SEND) goes HIGH again, LBEN will go HIGH, driving
the UART DRR (Data Ready Reset), which will signal
the end of the transfer of data from the TC7109A to the
UART.
An extension of the typical connection to several
TC7109A’s with one UART is shown in Figure 4-7. In
this circuit, the word received by the UART (available at
the RBR outputs when DR is HIGH) is used to select
which converter will handshake with the UART. Up to
eight TC7109A’s may interface with one UART, with no
external components. Up to 256 converters may be
accessed on one serial line with additional
components.
The data from every conversion will be sequenced in
two bytes in the system, if this output is left HIGH, or
tied HIGH separately. (The data access must take less
time than a conversion.) The output sequence can be
obtained on demand if this output is made to go from
LOW to HIGH and the interrupt may be used to reset
the MODE bit.
15 Q3 CD4060B
RESET
CLK
11
10
1 V
+5V
TRC
RRC
3 GND
4 RRD
GND
+5V
EPE
CLS1
CLS2
5–12 RBR1–8
SBS
40
GND
25
17
39
2
+5V
38
19
37
36
35
HD-640R
GND
PI
13 PE CMOS UART
34
+5V
CRL
14 FE
GND
15 OE
16 SFD
20
*TBR1–8
TRE
DRR
RR1
Serial
Input
25 TRO
Serial
Output
DR
TBRL
TBRE
MR
V+
1
26–33
6
8
3–8
8 9–16
24
17
18
18
19
21
23
20
22
27
21
GND
40
39
REF IN38
BUFF OSC OUT REF CAP37
REF
CAP+
STATUS
REF IN+ 36
35
IN HI
HBEN
34
IN LO
TC7109A COM 33
32
B9 - B12,
INT
POL, OR
31
AZ
30
BUFF
B1 - B8
29
REF OUT
TEST
28
VLBEN
26
RUN/HOLD
MODE
24
OSC SEL
CE/LOAD
23
OSC OUT
SEND
OSC IN 22
+5V
–
GND
1μF
External
Reference
1MΩ
+
+
0.01μF
Input
–
Analog GND
CINT
CAZ 0.15μF
0.33μF
RINT 20kΩ 0.2VREF
100kΩ 1VREF
-5V
+5V or Open
GND
3.58MHz
Crystal
*Note: For lowest power consumption, TBR1-TBR8 inputs should have 100kΩ pull-up resistors to +5V.
Send any word to UART to transmit latest result.
FIGURE 4-6:
DS21456D-page 20
TC7109 Typical UART Interface
2002-2012 Microchip Technology Inc.
TC7109/A
Serial Output
6402 CMOS UART
TBRL DRR
TBRE
Serial Input
RBR1 - RBR8
2
SFD
3
TBR1 - TBR8
GND
8-Bit Data Bus
MODE CE/ SEND
LOAD
B9 - B12
POL, OR
MODE CE/ SEND
LOAD
B9 - B12
POL, OR
6
TC7109A
B1 - B8
HBEN
4
5
6
7
10
9
+5V
RUN/HOLD
HBEN
3
XTAL2
8
TC7109A
+5V
LBEN
T0
RESET
P20 - P27
SS
INT
+5V
2
GND
EA
40
1
17
21-24,
35-38
8
μPD8748H/49H
CMOS
Microcomputer
Other I/O
P14 - P17
31-34
5
WR
PSEN
11
ALE
+5V 25 PROG
+5V 26 VDD
+5V 39 T1
+5V 40 VCC
P13
P12
P11
P10
GND 20 GND
26
30
29
2
28
18
27
19
3-8
6
DB0 - DB7
FIGURE 4-8:
B1 - B8
B1 - B8
6
8
RUN/HOLD
HBEN
+5V
LBEN
Handshake Interface for Multiplexed Converters
2
XTAL1
1
TC7109A
LBEN
FIGURE 4-7:
GND
Analog In
8
RUN/HOLD
+5V
6
Analog In
Analog In
MODE CE/ SEND
LOAD
B9 - B12
POL, OR
RD
12-19
8
9-16
8
8
20
39
REF IN38
REF CAPGND
REF CAP+ 37
TEST
36
REF IN+
35
IN HI
34
HI LO
33
COM
TC7109A
32
INT
31
AZ
30
BUFF
RUN/HOLD
29
REF OUT
STATUS
28
VLBEN
27
SEND
HBEN
25
BUFF OSC OUT
B9 - B12,
24
OSC SEL
POL, OR
23
OSC OUT
22
B1 - B8
OSC IN
21
CE/LOAD
MODE
–
V+
External
Reference
1μF
1MΩ
+
+
0.01μF
CINT
–
Input
Analog
GND
CAZ 0.15μF
0.33μF
RINT
-5V
20k Ω 0.2 VREF
10 k Ω 1 VREF
GND
3.58MHz
Crystal
Connection Diagram
2002-2012 Microchip Technology Inc.
DS21456D-page 21
TC7109/A
INTEGRATING CONVERTER
FEATURES
The output of integrating ADCs represents the integral,
or average, of an input voltage over a fixed period of
time. Compared with techniques in which the input is
sampled and held, the integrating converter averages
the effects of noise. A second important characteristic
is that time is used to quantize the answer, resulting in
extremely small non-linearity errors and no missing
output codes. The integrating converter also has very
good rejection of frequencies whose periods are an
integral multiple of the measurement period. This
feature can be used to advantage in reducing line
frequency noise (Figure ).
30
Normal Mode Rejection Plan
5.0
t = Measurement
Period
20
10
0
0.1/t
1/t
Input Frequency
10/t
FIGURE 5-1:
Normal Mode Rejection of
Dual Slope Converter as a Function of
Frequency
DS21456D-page 22
2002-2012 Microchip Technology Inc.
TC7109/A
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
Package marking data not available at this time.
6.2
Taping Form
Component Taping Orientation for 44-Pin PQFP Devices
User Direction of Feed
Pin 1
W
P
Standard Reel Component Orientation
for 713 Suffix Device
Carrier Tape, Number of Components Per Reel and Reel Size
Package
44-Pin PQFP
Carrier Width (W)
Pitch (P)
Part Per Full Reel
Reel Size
24 mm
16 mm
500
13 in
Note: Drawing does not represent total number of pins.
2002-2012 Microchip Technology Inc.
DS21456D-page 23
TC7109/A
Note:
For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
44-Pin PQFP
7° Max.
.009 (0.23)
.005 (0.13)
Pin 1
.018 (0.45)
.012 (0.30)
.398 (10.10)
.390 (9.90)
.557 (14.15)
.537 (13.65)
.031 (0.80) TYP.
.398 (10.10)
.390 (9.90)
.557 (14.15)
.537 (13.65)
DS21456D-page 24
.041 (1.03)
.026 (0.65)
.010 (0.25) Typ.
.083 (2.10)
.075 (1.90)
.096 (2.45) Max.
2002-2012 Microchip Technology Inc.
TC7109/A
6.3
Package Dimensions
Note:
For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
40-Pin PDIP (Wide)
Pin1
.555 (14.10)
.530 (13.46)
2.065 (52.45)
2.027 (51.49)
.610 (15.49)
.590 (14.99)
.200 (5.08)
.140 (3.56)
.040 (1.02)
.020 (0.51)
.150 (3.81)
.115 (2.92)
.110 (2.79)
.090 (2.29)
Note:
.070 (1.78)
.045 (1.14)
.015 (0.38)
.008 (0.20)
3° Min.
Dimensions: inches (mm)
.700 (17.78)
.610 (15.50)
.022 (0.56)
.015 (0.38)
For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
40-Pin CERDIP (Wide)
Pin 1
.540 (13.72)
.510 (12.95)
.030 (0.76) Min.
.098 (2.49) Max.
2.070 (52.58)
2.030 (51.56)
.620 (15.75)
.590 (15.00)
.060 (1.52)
.020 (0.51)
.210 (5.33)
.170 (4.32)
.150 (3.81)
MIN.
.200 (5.08)
.125 (3.18)
.110 (2.79)
.090 (2.29)
.065 (1.65)
.045 (1.14)
2002-2012 Microchip Technology Inc.
.020 (0.51)
.016 (0.41)
.015 (0.38)
.008 (0.20)
3° Min.
Dimensions: inches (mm)
.700 (17.78)
.620 (15.75)
DS21456D-page 25
TC7109/A
6.3
Package Dimensions (Continued)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
44-Pin PQFP
7° Max.
.009 (0.23)
.005 (0.13)
Pin 1
.018 (0.45)
.012 (0.30)
.041 (1.03)
.026 (0.65)
.398 (10.10)
.390 (9.90)
.557 (14.15)
.537 (13.65)
.031 (0.80) TYP.
.010 (0.25) Typ.
Dimensions: inches (mm)
.083 (2.10)
.075 (1.90)
.398 (10.10)
.390 (9.90)
.557 (14.15)
.537 (13.65)
.096 (2.45) Max.
Component Taping Orientation for 44-Pin PLCC Devices
User Direction of Feed
Pin 1
W
P
Standard Reel Component Orientation
for 713 Suffix Device
Dimensions: inches (mm)
Carrier Tape, Number of Components Per Reel and Reel Size
Package
44-Pin PLCC
Carrier Width (W)
Pitch (P)
Part Per Full Reel
Reel Size
32 mm
24 mm
500
13 in
Note: Drawing does not represent total number of pins.
DS21456D-page 26
2002-2012 Microchip Technology Inc.
TC7109/A
7.0
REVISION HISTORY
Revision D (December 2012)
Added a note to each package outline drawing.
2002-2012 Microchip Technology Inc.
DS21456D-page 27
TC7109/A
DS21456D-page 28
2002-2012 Microchip Technology Inc.
TC7109/A
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
2002-2012 Microchip Technology Inc.
DS21456D-page 29
TC7109/A
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO:
Technical Publications Manager
RE:
Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Device: TC7109/A
Literature Number: DS21456D
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS21456D-page 30
2002-2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2002-2012, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620768358
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2002-2012 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS21456D-page 31
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
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Tel: 61-2-9868-6733
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Tel: 65-6334-8870
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Tel: 86-24-2334-2829
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Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Shenzhen
Tel: 86-755-8864-2200
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Taiwan - Kaohsiung
Tel: 886-7-213-7828
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Tel: 86-27-5980-5300
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Taiwan - Taipei
Tel: 886-2-2508-8600
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Tel: 86-29-8833-7252
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Thailand - Bangkok
Tel: 66-2-694-1351
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UK - Wokingham
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Tel: 86-592-2388138
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Tel: 86-756-3210040
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DS21456D-page 32
Italy - Milan
Tel: 39-0331-742611
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11/29/12
2002-2012 Microchip Technology Inc.
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