TC7660S
Super Charge Pump DC-to-DC Voltage Converter
Features
•
•
•
•
•
•
•
Oscillator boost from 10 kHz to 45 kHz
Converts +5V Logic Supply to ±5V System
Wide Input Voltage Range: +1.5V to +12V
Efficient Voltage Conversion (99.9%, typical)
Excellent Power Efficiency (98%, typical)
Low Power Consumption: 80 µA (typical) @ VIN = 5V
Low Cost and Easy to Use
- Only Two External Capacitors Required
• Available in 8-Pin Small Outline (SOIC) and 8-Pin
PDIP Packages
• Improved ESD Protection (10 kV HBM)
• No External Diode Required for High-Voltage
Operation
Applications
•
•
•
•
RS-232 Negative Power Supply
Simple Conversion of +5V to ±5V Supplies
Voltage Multiplication VOUT = ± n V+
Negative Supplies for Data Acquisition Systems
and Instrumentation
Package Types
PDIP/SOIC
BOOST
1
CAP+
2
GND
3
CAP-
4
TC7660S
8
V+
7
OSC
6
LOW
VOLTAGE (LV)
5
VOUT
General Description
The TC7660S device is a pin-compatible replacement
for the industry standard 7660 charge pump voltage
converter. It converts a +1.5V to +12V input to a corresponding -1.5V to -12V output using only two low-cost
capacitors, eliminating inductors and their associated
cost, size and electromagnetic interference (EMI).
Added features include an extended supply range to
12V, and a frequency boost pin for higher operating frequency, allowing the use of smaller external capacitors.
The on-board oscillator operates at a nominal frequency of 10 kHz. Frequency is increased to 45 kHz
when pin 1 is connected to V+. Operation below 10 kHz
(for lower supply current applications) is possible by
connecting an external capacitor from OSC to ground
(with pin 1 open).
The TC7660S is available in 8-Pin PDIP and 8-Pin
Small Outline (SOIC) packages in commercial and
extended temperature ranges.
2001-2015 Microchip Technology Inc.
DS20001467C-page 1
TC7660S
Functional Block Diagram
V+ CAP+
8
BOOST
OSC
LV
2
1
7
RC
Oscillator
2
Voltage
Level
Translator
4
6
5
CAP-
VOUT
Internal
Internal
Voltage
Voltage
Regulator
Regulator
Logic
Network
TC7660S
3
GND
DS20001467C-page 2
2001-2015 Microchip Technology Inc.
TC7660S
1.0
Notice†: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational sections of this
specification is not intended. Exposure to maximum
rating conditions for extended periods may affect
device reliability.
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings†
Supply Voltage ................................................................+13V
LV, Boost, and OSC Inputs Voltage: (Note 1)
...................................-0.3V to (V+ + 0.3V) for V+ < 5.5V
......................... (V+ – 5.5V) to (V+ + 0.3V) for V+ > 5.5V
Current into LV ......................................... 20 µA for V+ > 3.5V
Output Short Duration (VSUPPLY 5.5V)............... Continuous
Package Power Dissipation: (TA +70°C) (Note 2)
8-Pin PDIP ..........................................................730 mW
8-Pin SOIC ..........................................................470 mW
Lead Temperature (Soldering, 10s) .... ....................... +300°C
Note 1: Connecting any input terminal to
voltages greater than V+ or less than
GND may cause destructive latch-up. It
is recommended that no inputs from
sources operating from external
supplies be applied prior to “power up” of
the TC7660S.
2: Derate linearly
5.5 mW/°C.
above
+50°C
by
ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise noted, specifications measured over operating temperature range with
V+ = 5V, COSC = 0, refer to test circuit in Figure 4-1.
Parameters
Supply Current
(Boost pin OPEN or GND)
Supply Current
(Boost pin = V+)
Sym.
Min.
Typ.
Max.
Units
I+
—
80
160
µA
—
—
180
0°C TA +70°C
—
—
180
-40°C TA +85°C
—
—
200
-55°C TA +125°C
—
—
300
—
—
350
-40°C TA +85°C
-55°C TA +125°C
I
+
µA
Conditions
RL =
0°C TA +70°C
—
—
400
Supply Voltage Range,
High
V+H
3.0
—
12
V
Min. TAMax, RL = 10 k, LV Open
Supply Voltage Range, Low
V+L
1.5
—
3.5
V
Min. TAMax, RL = 10 k, LV to GND
ROUT
—
60
100
IOUT = 20 mA
—
70
120
IOUT = 20 mA, 0°C TA +70°C
—
70
120
IOUT = 20 mA, -40°C TA +85°C
—
105
150
IOUT = 20 mA, -55°C TA +125°C
—
—
250
V+ = 2V, IOUT = 3 mA, LV to GND
0°C TA +70°C
—
—
400
V+ = 2V, IOUT = 3 mA, LV to GND
-55°C TA +125°C
—
10
—
Output Source Resistance
Oscillator Frequency
fOSC
kHz
Boost Pin = V+
45
Power Efficiency
PEFF
2001-2015 Microchip Technology Inc.
Pin 7 open, Pin 1 open or GND
96
98
—
%
RL = 5 kBoost Pin Open
95
98
—
TMIN TA TMAX; Boost Pin Open
—
88
—
Boost Pin = V+
DS20001467C-page 3
TC7660S
ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise noted, specifications measured over operating temperature range with
V+ = 5V, COSC = 0, refer to test circuit in Figure 4-1.
Parameters
Voltage Conversion
Efficiency
Sym.
Min.
Typ.
Max.
Units
VOUTEFF
99
99.9
—
%
RL =
ZOSC
—
1
—
M
V+ = 2V
—
100
—
k
V+ = 5V
Oscillator Impedance
Conditions
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise noted, specifications measured over operating temperature range with
V+ = 5V, COSC = 0, refer to test circuit in Figure 4-1.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
TA
0
—
+70
°C
C suffix
TA
-40
—
+85
°C
E suffix
TA
-40
—
+125
°C
V suffix
TA
-65
—
+150
°C
Thermal Resistance, 8LD PDIP
JA
—
89.3
—
°C/W
Thermal Resistance, 8LD SOIC
JA
—
148.5
—
°C/W
Temperature Ranges
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistances
DS20001467C-page 4
2001-2015 Microchip Technology Inc.
TC7660S
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, C1 = C2 = 10 µF, ESRC1 = ESRC2 = 1 , TA = 25°C. See Figure 4-1.
OSCILLATOR FREQUENCY (kHz)
OSCILLATOR FREQUENCY (kHz)
10
8
VIN = 5V
6
4
VIN = 12V
2
0
-40
IN
60
12
-20
0
20
40
60
80
50
40
VIN = 5V
30
VIN = 12V
20
10
0
-40
100
-20
0
800
VIN = 12V
IDD (μA)
600
400
200
VIN = 5V
0
20
40
60
80
100
VOLTAGE CONVERSION EFFICIENCY (%)
1000
-20
60
80
100
101.0
100.5
Without Load
100.0
99.5
10K Load
99.0
98.5
TA = 25°C
98.0
1
2
TEMPERATURE (°C)
3
4
5
6
7
8
9
10 11 12
INPUT VOLTAGE VIN (V)
FIGURE 2-2:
Supply Current vs.
Temperature (with Boost Pin = VIN).
FIGURE 2-5:
Voltage Conversion.
100
70
50
30
IOUT = 20mA
TA = 25°C
10
1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 10.5 11.5 12
OUTPUT SOURCE RESISTANCE (Ω)
100
OUTPUT SOURCE RESISTANCE (Ω)
40
FIGURE 2-4:
Unloaded Oscillator
Frequency vs. Temperature with Boost Pin = VIN.
FIGURE 2-1:
Unloaded Oscillator
Frequency vs. Temperature.
0
-40
20
TEMPERATURE (°C)
TEMPERATURE (°C)
VIN = 2.5V
80
60
VIN = 5.5V
40
20
0
-40
-20
FIGURE 2-3:
Output Source Resistance
vs. Supply Voltage.
2001-2015 Microchip Technology Inc.
0
20
40
60
80
100
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
FIGURE 2-6:
vs. Temperature.
Output Source Resistance
DS20001467C-page 5
TC7660S
Note: Unless otherwise indicated, C1 = C2 = 10 µF, ESRC1 = ESRC2 = 1 , TA = 25°C. See Figure 4-1.
100
0
POWER EFFICIENCY (%)
-4
-6
-8
-10
-12
Boost Pin = V+
70
60
50
40
30
20
10
0
0
10
20
30
40
50
60
70
80
90 100
OUTPUT CURRENT (mA)
FIGURE 2-7:
Current.
LOAD CURRENT (mA)
Output Voltage vs. Output
FIGURE 2-10:
Power Conversion
Efficiency vs. Load.
200
200
175
175
SUPPLY CURRENT IDD (μA)
SUPPLY CURRENT IDD (μA)
Boost Pin = Open
80
150
125
VIN = 12.5V
100
75
50
VIN = 5.5V
25
0
-40
-20
0
20
40
1.0
1.5
2.0
3.0
4.5
6.0
7.5
9.0
10.0
15.0
20.0
25.0
30.0
35.0
40.0
50.0
55.0
60.0
OUTPUT VOLTAGE VOUT (V)
90
-2
60
80
100
150
125
VIN = 12.5V
100
75
50
VIN = 5.5V
25
0
-40
-20
FIGURE 2-8:
Temperature.
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Supply Current vs.
FIGURE 2-11:
Temperature.
Supply Current vs.
200
SUPPLY CURRENT IDD (μA)
175
150
125
VIN = 12.5V
100
75
50
VIN = 5.5V
25
0
-40
-20
0
20
40
60
80
100
TEMPERATURE (°C)
FIGURE 2-9:
Temperature.
DS20001467C-page 6
Supply Current vs.
2001-2015 Microchip Technology Inc.
TC7660S
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
3.1
PIN FUNCTION TABLE
Pin No.
Symbol
Description
1
BOOST
2
CAP+
Charge pump capacitor positive terminal
3
GND
Ground terminal
4
CAP-
Charge pump capacitor negative terminal
5
VOUT
6
LV
7
OSC
8
V+
Switching Frequency boost pin
Output voltage
Low voltage pin. Connect to GND for V+ < 3.5V
Oscillator control input. Bypass with an external capacitor to slow the oscillator.
Power supply positive voltage input
Switching Frequency Boost Pin
(Boost)
By connecting the boost pin (pin 1), the switching
frequency of the charge pump is increased from 10 kHz
typical to 45 kHz typical. By connecting the boost pin
(pin1), to the V+ pin (pin 8), the switching frequency of
the charge pump is increased from 10 kHz typical to
45 kHz typical.
3.2
Charge Pump Capacitor (CAP+)
Positive connection for the charge pump capacitor, or
flying capacitor, used to transfer charge from the input
source to the output. In the voltage-inverting
configuration, the charge pump capacitor is charged to
the input voltage during the first half of the switching
cycle. During the second half of the switching cycle, the
charge pump capacitor is inverted and charge is
transferred to the output capacitor and load.
It is recommended that a low ESR (equivalent series
resistance) capacitor be used. Additionally, larger
values will lower the output resistance.
3.3
It is recommended that a low ESR capacitor be used.
Additionally, larger values will lower the output ripple.
3.6
Low Voltage Pin (LV)
The low voltage pin ensures proper operation of the
internal oscillator for input voltages below 3.5V. The low
voltage pin should be connected to ground (GND) for
input voltages below 3.5V. Otherwise, the low voltage
pin should be allowed to float.
3.7
Oscillator Control Input (OSC)
The oscillator control input can be utilized to slow down
or speed up the operation of the TC7660S. Refer to
Section 5.4 “Changing the TC7660S Oscillator
Frequency”, for details on altering the oscillator
frequency.
3.8
Power Supply (V+)
Positive power supply input voltage connection. It is
recommended that a low ESR capacitor be used to
bypass the power supply input to ground (GND).
Ground (GND)
Input and output zero volt reference.
3.4
Charge Pump Capacitor (CAP-)
Negative connection for the charge pump capacitor, or
flying capacitor, used to transfer charge from the input
to the output. Proper orientation is imperative when
using a polarized capacitor.
3.5
Output Voltage (VOUT)
Negative connection for the charge pump output
capacitor. In the voltage-inverting configuration, the
charge pump output capacitor supplies the output load
during the first half of the switching cycle. During the
second half of the switching cycle, charge is restored to
the charge pump output capacitor.
2001-2015 Microchip Technology Inc.
DS20001467C-page 7
TC7660S
4.0
DETAILED DESCRIPTION
4.1
V+
Theory of Operation
The four switches in Figure 4-2 are MOS power
switches; S1 is a P-channel device, and S2, S3 and S4
are N-channel devices. The main difficulty with this
approach is that in integrating the switches, the substrates of S3 and S4 must always remain
reverse-biased with respect to their sources, but not so
much as to degrade their ON resistances. In addition,
at circuit start-up, and under output short circuit conditions (VOUT = V+), the output voltage must be sensed
and the substrate bias adjusted accordingly. Failure to
accomplish this will result in high power losses and
probable device latch-up.
This problem is eliminated in the TC7660S by a logic
network which senses the output voltage (VOUT)
together with the level translators, and switches the
substrates of S3 and S4 to the correct level to maintain
necessary reverse bias.
V+
C1
10 µF
+
3
IS
8
2
7
TC7660S
4
6
5
IL
COSC
V+
(+5V)
RL
VOUT
C2
+ 10 µF
Note:
For large values of COSC (>1000 pF), the
values of C1 and C2 should be increased to
100F.
FIGURE 4-1:
TC7660S Test Circuit.
The voltage regulator portion of the TC7660S is an
integral part of the anti-latch-up circuitry. Its inherent
voltage drop can, however, degrade operation at low
voltages.
DS20001467C-page 8
S2
+
The TC7660S contains all the necessary circuitry to
implement a voltage inverter, with the exception of two
external capacitors, which may be inexpensive 10 µF
polarized electrolytic capacitors. Operation is best
understood by considering Figure 4-2, which shows an
idealized voltage inverter. Capacitor C1 is charged to a
voltage V+ for the half cycle when switches S1 and S3
are closed. (Note that switches S2 and S4 are open
during this half cycle.) During the second half cycle of
operation, switches S2 and S4 are closed, with S1 and
S3 open, thereby shifting capacitor C1 negatively by V+
volts. Charge is then transferred from C1 negatively by
V+ volts. Charge is then transferred from C1 to C2, such
that the voltage on C2 is exactly V+ assuming ideal
switches and no load on C2.
1
S1
GND S
3
FIGURE 4-2:
C1
S4
C2
+
VOUT = -VIN
Ideal Charge Pump Inverter.
To improve low-voltage operation, the “LV” pin should
be connected to GND, disabling the regulator. For
supply voltages greater than 3.5V, the LV terminal must
be left open to ensure latch-up-proof operation and
prevent device damage.
4.2
Theoretical Power Efficiency
Considerations
In theory, a capacitive charge pump can approach
100% efficiency if certain conditions are met:
(1) The drive circuitry consumes minimal power.
(2) The output switches have extremely low ON
resistance and virtually no offset.
(3) The impedances of the pump and reservoir
capacitors are negligible at the pump frequency.
The TC7660S approaches these conditions for negative voltage multiplication if large values of C1 and C2
are used. Energy is lost only in the transfer of charge
between capacitors if a change in voltage occurs. The
energy lost is defined by:
E = 1/2 C1 (V12 – V22)
V1 and V2 are the voltages on C1 during the pump and
transfer cycles. If the impedances of C1 and C2 are relatively high at the pump frequency (refer to Figure 4-2)
compared to the value of RL, there will be a substantial
difference in voltages V1 and V2. Therefore, it is desirable not only to make C2 as large as possible to
eliminate output voltage ripple, but also to employ a
correspondingly large value for C1 in order to achieve
maximum efficiency of operation.
4.3
Dos and Don'ts
• Do not exceed maximum supply voltages.
• Do not connect the LV terminal to GND for supply
voltages greater than 3.5V.
• Do not short circuit the output to V+ supply for
voltages above 5.5V for extended periods; however, transient conditions including start-up are
okay.
• When using polarized capacitors in the inverting
mode, the + terminal of C1 must be connected to
pin 2 of the TC7660S and the + terminal of C2
must be connected to GND.
2001-2015 Microchip Technology Inc.
TC7660S
5.0
APPLICATIONS INFORMATION
5.1
Simple Negative Voltage
Converter
The dynamic output impedance of the TC7660S is due,
primarily, to capacitive reactance of the charge transfer
capacitor (C1). Since this capacitor is connected to the
output for only half of the cycle, the equation is:
Figure 5-1 shows typical connections to provide a
negative supply where a positive supply is available. A
similar scheme may be employed for supply voltages
anywhere in the operating range of +1.5V to +12V,
keeping in mind that pin 6 (LV) is tied to the supply
negative (GND) only for supply voltages below 3.5V.
EQUATION
2
X C = ----------- = 3.18
2fC 1
where:
f = 10 kHz and C1 = 10 µF.
5.2
V+
C1
10 µF
2
+
3
Any number of TC7660S voltage converters may be
paralleled to reduce output resistance (Figure 5-2). The
reservoir capacitor, C2, serves all devices, while each
device requires its own pump capacitor, C1. The resultant output resistance would be approximately:
8
1
7
TC7660S
VOUT*
C2
+ 10 µF
6
5
4
EQUATION
* VOUT = -V+ for 1.5V V+ 12V
FIGURE 5-1:
Paralleling Devices
R OUT of TC7660S
ROUT = --------------------------------------------------n number of devices
Simple Negative Converter.
The output characteristics of the circuit in Figure 5-1
are those of a nearly ideal voltage source in series with
a 70resistor. Thus, for a load current of -10 mA and
a supply voltage of +5V, the output voltage would be
-4.3V.
V+
1
C1
8
2
+
3
4
“1”
8
1
7
TC7660S
6
C1
5
+
2
3
4
RL
7
TC7660S
“n”
6
5
+
FIGURE 5-2:
C2
Paralleling Devices Lowers Output Impedance.
V+
8
1
10 µF
+
2
3
4
7
TC7660S
“1”
1
6
5
10 µF
+
2
3
4
* VOUT = -n V+ for 1.5V V+ 12V
FIGURE 5-3:
+
8
7
TC7660S
“n”
10 µF
6
VOUT *
5
+
10 µF
Increased Output Voltage By Cascading Devices.
2001-2015 Microchip Technology Inc.
DS20001467C-page 9
TC7660S
5.3
Cascading Devices
The TC7660S may be cascaded as shown (Figure 5-3)
to produce larger negative multiplication of the initial
supply voltage. However, due to the finite efficiency of
each device, the practical limit is 10 devices for light
loads. The output voltage is defined by:
C1
+
2
3
7
TC7660S
COSC
6
VOUT
5
4
EQUATION
V+
8
1
+
VOUT = – n V
+
where n is an integer representing the number of
devices cascaded. The resulting output resistance
would be approximately the weighted sum of the
individual TC7660S ROUT values.
5.4
Changing the TC7660S Oscillator
Frequency
It may be desirable in some applications (due to noise
or other considerations) to increase the oscillator frequency. Pin 1, frequency boost pin, may be connected
to V+ to increase oscillator frequency to 45 kHz from a
nominal of 10 kHz for an input supply voltage of 5.0V.
The oscillator may also be synchronized to an external
clock as shown in Figure 5-4. In order to prevent possible device latch-up, a 1 kΩ resistor must be used in
series with the clock output. In a situation where the
designer has generated the external clock frequency
using TTL logic, the addition of a 10 kΩ pull-up resistor
to V+ supply is required. Note that the pump frequency
with external clocking, as with internal clocking, will be
half of the clock frequency. Output transitions occur on
the positive-going edge of the clock.
V+
1
10 µF
+
2
3
4
8
TC7660S
“1”
7
5.5
Lowering Oscillator
Positive Voltage Multiplication
The TC7660S may be employed to achieve positive
voltage multiplication using the circuit shown in
Figure 5-6. In this application, the pump inverter
switches of the TC7660S are used to charge C1 to a
voltage level of V+–VF (where V+ is the supply voltage
and VF is the forward voltage drop of diode D1). On the
transfer cycle, the voltage on C1 plus the supply voltage
(V+) is applied through diode D2 to capacitor C2. The
voltage thus created on C2 becomes (2V+) – (2VF), or
twice the supply voltage minus the combined forward
voltage drops of diodes D1 and D2.
The source impedance of the output (VOUT) will depend
on the output current, but for V+ = 5V and an output
current of 10 mA, it will be approximately 60Ω.
V+
V+
1 k
CMOS
GATE
6
8
1
2
3
VOUT
5
+
FIGURE 5-4:
FIGURE 5-5:
Frequency.
C2
7
TC7660S
4
10 µF
External Clocking.
FIGURE 5-6:
6
5
D1
+
D2
C1
VOUT =
(2 V+) - (2 VF)
+
C2
Positive Voltage Multiplier.
It is also possible to increase the conversion efficiency
of the TC7660S at low load levels by lowering the
oscillator frequency. This reduces the switching losses,
and is achieved by connecting an additional capacitor,
COSC, as shown in Figure 5-5. Lowering the oscillator
frequency will cause an undesirable increase in the
impedance of the pump (C1) and the reservoir (C2)
capacitors. To overcome this, increase the values of C1
and C2 by the same factor that the frequency has been
reduced. For example, the addition of a 100 pF
capacitor between pin 7 (OSC) and pin 8 (V+) will lower
the oscillator frequency to 1 kHz from its nominal
frequency of 10 kHz (a multiple of 10), and necessitate
a corresponding increase in the values of C1 and C2
(from 10 µF to 100 µF).
DS20001467C-page 10
2001-2015 Microchip Technology Inc.
TC7660S
5.6
Combined Negative Voltage
Conversion and Positive Supply
Multiplication
Figure 5-7 combines the functions shown in Figure 5-3
and Figure 5-6 to provide negative voltage conversion
and positive voltage multiplication simultaneously. For
example, this approach would be suitable for generating +9V and -5V from an existing +5V supply. In this
instance, capacitors C1 and C3 perform the pump and
reservoir functions, respectively, for the generation of
the negative voltage, while capacitors C2 and C4 are
pump and reservoir, respectively, for the multiplied positive voltage. There is a penalty in this configuration
which combines both functions, however, in that the
source impedances of the generated supplies will be
somewhat higher due to the finite impedance of the
common charge pump driver at pin 2 of the device.
V+
2
3
+
C1
VOUT
= -V+
8
1
7
TC7660S
6
5
4
+
C2
D1
+
C3
VOUT =
D2 (2 V+) - (2 VF)
+
VOUT = -V -
C1
+
1
8
2
7
3
10 µF
TC7660S
4
+
1 M
10 µF
6
5
V - input
FIGURE 5-8:
Conversion.
5.8
Positive Voltage
Voltage Splitting
The same bidirectional characteristics used in
Figure 5-8 can also be used to split a higher supply in
half, as shown in Figure 5-9. The combined load will be
evenly shared between the two sides. Once again, a
high value resistor to the LV pin ensures start-up.
Because the switches share the load in parallel, the
output impedance is much lower than in the standard
circuits, and higher currents can be drawn from the
device. By using this circuit, and then the circuit of
Figure 5-3, +15V can be converted (via +7.5V and -7.5V)
to a nominal -15V, though with rather high series
resistance (~250Ω).
C4
V
+
+
50μF
R
L1
FIGURE 5-7:
Combined Negative
Converter and Positive Multiplier.
5.7
Efficient Positive Voltage
Multiplication/Conversion
Since the switches that allow the charge pumping
operation are bidirectional, the charge transfer can be
performed backwards as easily as forwards.
Figure 5-8 shows a TC7660S transforming -5V to +5V
(or +5V to +10V, etc.). The only problem is that the
internal clock and switch-drive section will not operate
until some positive voltage has been generated. An initial inefficient pump, as shown in Figure 5-7, could be
used to start this circuit up, after which it will bypass the
other (D1 and D2 in Figure 5-7 would never turn on), or
else the diode and resistor shown dotted in Figure 5-8
can be used to “force” the internal regulator on.
V
=
OUT
+
–
V –V
2
1
8
2
50μF
7
100 kΩ
+
1 MΩ
3
–
4
R
TC7660S
6
5
L2
+
50μF
–
V
FIGURE 5-9:
5.9
–
Splitting a Supply in Half.
Negative Voltage Generation for
Display ADCs
The TC7106 is designed to work from a 9V battery.
With a fixed power supply system, the TC7106 will
perform conversions with input signal referenced to
power supply ground.
5.10
Negative Supply Generation for
4½ Digit Data Acquisition System
The TC7135 is a 4½ digit ADC operating from ±5V
supplies. The TC7660S provides an inexpensive -5V
source. (See AN16 and AN17 for TC7135 interface
details and software routines.)
2001-2015 Microchip Technology Inc.
DS20001467C-page 11
TC7660S
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
8-Lead PDIP (300 mil)
XXXXXXXX
XXXXXNNN
YYWW
8-Lead SOIC (3.90 mm)
Example
TC7660S
CPA e3 256
1545
Example
TC7660S
EPA e3256
1545
Example
TC7660SE
OA e3 1545
NNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS20001467C-page 12
256
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
2001-2015 Microchip Technology Inc.
TC7660S
/HDG3ODVWLF'XDO,Q/LQH 3$ PLO%RG\>3',3@
1RWH
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
N
B
E1
NOTE 1
1
2
TOP VIEW
E
C
A2
A
3/$1(
L
c
A1
e
eB
8X b1
8X b
.010
C
SIDE VIEW
END VIEW
Microchip Technology Drawing No. C04-018D Sheet 1 of 2
2001-2015 Microchip Technology Inc.
DS20001467C-page 13
TC7660S
/HDG3ODVWLF'XDO,Q/LQH 3$ PLO%RG\>3',3@
1RWH
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
ALTERNATE LEAD DESIGN
(VENDOR DEPENDENT)
DATUM A
DATUM A
b
b
e
2
e
2
e
Units
Dimension Limits
Number of Pins
N
e
Pitch
Top to Seating Plane
A
Molded Package Thickness
A2
Base to Seating Plane
A1
Shoulder to Shoulder Width
E
Molded Package Width
E1
Overall Length
D
Tip to Seating Plane
L
c
Lead Thickness
Upper Lead Width
b1
b
Lower Lead Width
Overall Row Spacing
eB
§
e
MIN
.115
.015
.290
.240
.348
.115
.008
.040
.014
-
INCHES
NOM
8
.100 BSC
.130
.310
.250
.365
.130
.010
.060
.018
-
MAX
.210
.195
.325
.280
.400
.150
.015
.070
.022
.430
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-018D Sheet 2 of 2
DS20001467C-page 14
2001-2015 Microchip Technology Inc.
TC7660S
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2001-2015 Microchip Technology Inc.
DS20001467C-page 15
TC7660S
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20001467C-page 16
2001-2015 Microchip Technology Inc.
TC7660S
!"#$%&
'
!
" # $ % &"' ""
( $ )
%
*++&&&!
!+ $
2001-2015 Microchip Technology Inc.
DS20001467C-page 17
TC7660S
NOTES:
DS20001467C-page 18
2001-2015 Microchip Technology Inc.
TC7660S
APPENDIX A:
REVISION HISTORY
Revision C (November 2015)
The following is the list of modifications.
1.
2.
3.
4.
Updated Section 1.0 “Electrical Characteristics”.
Added Temperature Specifications table.
Updated Product Identification System
section.
Minor typographical errors.
Revision B (August 2013)
The following is the list of modifications.
1.
2.
Added Appendix A and the “Product Identification System” page.
Updated
Section 6.0
“Packaging
Information”.
Revision A (May 2001)
• Original release of this document.
2001-2015 Microchip Technology Inc.
DS20001467C-page 19
TC7660S
NOTES:
DS20001467C-page 20
2001-2015 Microchip Technology Inc.
TC7660S
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
/XX
[X](1)
Package
Tape and Reel
Option
X
Temperature
Range
Device:
TC7660S: DC-to-DC Voltage Converter
Temperature
Range:
C
E
V
Examples:
a)
a)
a)
b)
=
=
=
0°C to +70°C (Commercial)
-40°C to +85°C (Extended)
-40°C to +125°C (Various)
Package:
PA
OA
= 8-Lead Plastic Dual In-Line - 300 mil Body (PDIP)
= 8-Lead Plastic Small Outline - Narrow, 3.90 mm Body (SOIC)
Tape and
Reel
Blank
713
723
= Tube
= Tape and Reel (SOIC only)
= Reverse Tape and Reel (SOIC only)
c)
d)
e)
f)
TC7660SCPA:
Commercial temperature,
PDIP package
TC7660SCPA:
Commercial temperature,
PDIP package
TC7660SEPA: Extended temperature, PDIP
package
TC7660SCOA:
Commercial temperature,
SOIC package
TC7660SCOA713: Tape and Reel,
Commercial temperature, SOIC package
TC7660SEOA: Extended temperature, SOIC
package
TC7660SEOA713: Tape and Reel, Extended
temperature, SOIC package
TC7660SEOA723: Reverse Tape and Reel,
Extended temperature, SOIC package
Note 1:
2001-2015 Microchip Technology Inc.
Tape and Reel identifier only appears in
the catalog part number description. This
identifier is used for ordering purposes and
is not printed on the device package.
Check with your Microchip Sales Office for
package availability with the Tape and
Reel option.
DS20001467C-page 21
TC7660S
NOTES:
DS20001467C-page 22
2001-2015 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet,
KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O,
Total Endurance, TSHARC, USBCheck, VariSense,
ViewSpan, WiperLock, Wireless DNA, and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2001-2015, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-0013-4
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2001-2015 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS20001467C-page 23
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
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Tel: 86-592-2388138
Fax: 86-592-2388130
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Fax: 43-7242-2244-393
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Tel: 86-756-3210040
Fax: 86-756-3210049
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Tel: 45-4450-2828
Fax: 45-4485-2829
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Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
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Tel: 33-1-69-53-63-20
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Tel: 91-11-4160-8631
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Tel: 678-957-9614
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Tel: 512-257-3370
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Tel: 949-462-9523
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Tel: 408-735-9110
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Tel: 905-673-0699
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Tel: 852-2943-5100
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Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
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Tel: 86-25-8473-2460
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Poland - Warsaw
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07/14/15
DS20001467C-page 24
2001-2015 Microchip Technology Inc.
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