TC850ILW

TC850 15-Bit, Fast Integrating CMOS A/D Converter Package Types 40-Pin PDIP/CERDIP CS 1 CE 2 40 VDD 39 REF1+ WR 3 38 CREF1+ RD 4 37 CREF1- CONT/DEMAND 5 36 REF- OVR/POL 6 35 CREF2- L/H 7 DB7 8 DB6 9 Device Selection Table Part Number TC850CPL Package 32 IN+ 31 INANALOG 30 COMMON 29 CINTB DB4 11 DB3 12 DB2 13 28 CINTA DB1 14 27 CBUFA DB0 15 26 CBUFB BUSY 16 25 BUFFER OSC1 17 24 INTIN OSC2 18 23 INTOUT TEST 19 22 VSS 21 COMP DGND 20 2 1 44 43 42 41 40 CREF1- 3 REF- NC 4 CREF1+ CS 5 REF1+ CE 6 VDD WR 44-Pin PLCC OVR/POL 7 L/H 8 39 CREF2- DB7 9 37 REF2+ 38 CREF2+ DB6 10 Temperature Range DB5 11 DB4 13 40-Pin PDIP 0C to +70C 40-Pin CERDIP -25C to +85C TC850CLW 44-Pin PLCC 0C to +70C TC850ILW 44-Pin PLCC -25C to +85C TC850IJL 33 REF2+ DB5 10 Applications: • Precision Analog Signal Processor • Precision Sensor Interface • High Accuracy DC Measurements 34 CREF2+ TC850CPL TC850IJL RD • 15-bit Resolution Plus Sign Bit • Up to 40 Conversions per Second • Integrating ADC Technique: - Monotonic - High Noise Immunity - Auto-Zeroed Amplifiers Eliminate Offset Trimming • Wide Dynamic Range: 96 dB • Low Input Bias Current: 30 pA • Low Input Noise: 30 VP-P • Sensitivity: 100 V • Flexible Operational Control • Continuous or On Demand Conversions • Data Valid Output • Bus Compatible, 3-State Data Outputs: - 8-Bit Data Bus - Simple P Interface - Two Chip Enables - Read ADC Result Like Memory • ± 5V Power Supply Operation: 20 m • 40-Pin Dual-in-Line or 44-Pin PLCC Packages CONT/DEMAND Features: 36 IN+ 35 IN- TC850CLW TC850ILW NC 12 34 NC DB3 14 33 ANALOG COMMON 32 CINTB DB2 15 31 CINTA DB1 16 30 CBUFA 29 CBUFB DB0 17 BUFFER INTIN INTOUT VSS COMP NC TEST DGND OSC2 OSC1 BUSY 18 19 20 21 22 23 24 25 26 27 28 NC = No Internal Connection  2001-2012 Microchip Technology Inc. DS21479D-page 1 TC850 General Description: for precision external amplifiers. The internal amplifiers are auto-zeroed, ensuring a zero digital output, with 0V analog input. Zero adjustment potentiometers or calibrations are not required. The TC850 is a monolithic CMOS A/D converter (ADC) with resolution of 15-bits plus sign. It combines a chopper-stabilized buffer and integrator with a unique multiple-slope integration technique that increases conversion speed. The result is 16 times improvement in speed over previous 15-bit, monolithic integrating ADCs (from 2.5 conversions per second up to 40 per second). Faster conversion speed is especially welcome in systems with human interface, such as digital scales. The TC850 outputs data on an 8-bit, 3-state bus. Digital inputs are CMOS compatible while outputs are TTL/ CMOS compatible. Chip-enable and byte-select inputs, combined with an end-of-conversion output, ensures easy interfacing to a wide variety of microprocessors. Conversions can be performed continuously or on command. In Continuous mode, data is read as three consecutive bytes and manipulation of address lines is not required. The TC850 incorporates an ADC and a P-compatible digital interface. Only a voltage reference and a few, noncritical, passive components are required to form a complete 15-bit plus sign ADC. CMOS processing provides the TC850 with high-impedance, differential inputs. Input bias current is typically only 30 pA, permitting direct interface to sensors. Input sensitivity of 100 V per Least Significant bit (LSb) eliminates the need Operating from ±5V supplies, the TC850 dissipates only 20 m. The TC850 is packaged in a 40-pin plastic or ceramic dual-in-line package (DIPs) and in a 44-pin plastic leaded chip carrier (PLCC), surface-mount package. Functional Block Diagram Pinout of 40-Pin Package RINT REF2+ REF1+ REF- 25 –5V +5V 22 40 INT OUT INT IN BUF 39 34 36 CINT 24 23 IN+ INCOMMON 32 31 30 + Analog Mux Comparator Buffer + + Integrator TC850 6-Bit 9-Bit Up/Down Up/Down Counter Counter A/D Control Sequencer Data Latch ÷4 Bus Interface Decode Logic Clock Oscillator Octal 2-Input Mux 3-State Data Bus DS21479D-page 2 17 18 OSC1 OSC2 5 7 6 3 4 1 2 CONT/ L/H OVR/ WR RD CS CE POL DEMAND 15 . . . .8 DB0 DB7  2001-2012 Microchip Technology Inc. TC850 1.0 ELECTRICAL SPECIFICATIONS *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings* Positive Supply Voltage..........................................+6V Negative Supply Voltage ....................................... - 9V Analog Input Voltage (IN+ pr IN-) .............. VDD to VSS Voltage Reference Input: (REF1+, REF1–, REF2+).................. VDD to VSS Logic Input Voltage.............VDD + 0.3V to GND – 0.3V Current Into Any Pin...........................................10 mA While Operating .....................................100 A Ambient Operating Temperature Range C Device.......................................0°C to +70°C I Device......................................-25°C to +85°C Package Power Dissipation (TA  70°C) CerDIP .....................................................2.29 Plastic DIP................................................1.23 Plastic PLCC ...........................................1.23 TABLE 1-1: TC850 ELECTRICAL SPECIFICATIONS Electrical Characteristics: VS = ±5V; FCLK = 61.44kHz, VFS = 3.2768V, TA = 25°C, Figure 1-1, unless otherwise specified. Symbol Parameter Min Zero Scale Error IIN VCMR CMRR Typ Max Unit Test Conditions ±0.25 ±0.5 LSB VIN = 0V End Point Linearity Error — ±1 ±2 LSB -VFS  VIN  +VFS Differential Nonlinearity — ±0.1 ±0.5 LSB Input Leakage Current — 30 75 pA VIN = 0V, TA = 25°C — 1.1 3 nA -25°  TA  +85°C Common Mode Voltage Range VSS + 1.5 — VSS – 1.5 V Over Operating Temperature Range dB VIN = 0V, VCM = ±1V Common Mode Rejection Ratio — 80 — Full Scale Gain Temperature Coefficient — 2 5 Zero Scale Error Temperature Coefficient — 0.3 2 V/°C Full Scale Magnitude Symmetry Error — 0.5 2 LSB ppm/°C External Ref. Temperature Coefficient = 0 ppm/°C 0°C  TA  +70°C eN Input Noise — 30 — VP-P IS+ Positive Supply Current — 2 3.5 mA VIN = 0V 0°C  TA  +70°C VIN = ±3.275V Not Exceeded 95% of Time IS– Negative Supply Current — 2 3.5 mA VOH Output High Voltage 3.5 4.9 — V IO = 500 A VOL Output Low Voltage — 0.15 0.4 V IO = 1.6 mA IOP Output Leakage Current — 0.1 1 A VIH Input High Voltage 3.5 2.3 — V Note 3 VIL Input Low Voltage — 2.1 1 V Note 3 A A A IPU Input Pull-Up Current — 4 — IPD Input Pull-Down Current — 14 — IOSC Oscillator Output Current — 140 — Pins 8 -15, High-impedance State Pins 2, 3, 4, 6, 7; VIN = 0V Pins 1, 5; VIN = 5V Pin 18, VOUT = 2.5V Note 1: Demand mode, CONT/DEMAND = LOW. Figure 8-2 timing diagram. CL = 100 pF. 2: Continuous mode, CONT/DEMAND = HIGH. Figure 8-4 timing diagram. 3: Digital inputs have CMOS logic levels and internal pull-up/pull-down resistors. For TTL compatibility, external pull-up resistors to VDD are recommended.  2001-2012 Microchip Technology Inc. DS21479D-page 3 TC850 TABLE 1-1: TC850 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: VS = ±5V; FCLK = 61.44kHz, VFS = 3.2768V, TA = 25°C, Figure 1-1, unless otherwise specified. Symbol CIN COUT Parameter Min Typ Max Unit Test Conditions Input Capacitance — 1 — pF Pins 1 - 7, 17 Output Capacitance — 15 — pF Pins 8 -15, High-impedance State TCE Chip-Enable Access Time — 230 450 nsec TRE Read-Enable Access Time — 190 450 nsec CS = HIGH, CE = LOW, (Note 1) TDHC Data Hold From CS or CE — 250 450 nsec RD = LOW, (Note 1) TDHR Data Hold From RD — 210 450 nsec CS = HIGH, CE = LOW, (Note 1) TOP OVR/POL Data Access Time — 140 300 nsec CS = HIGH, CE = LOW, RD = LOW, (Note 1) TLH Low/High Byte Access Time — 140 300 nsec CS = HIGH, CE = LOW, RD = LOW, (Note 1) CS or CE, RD = LOW (Note 1) Clock Setup Time 100 — — nsec Positive or Negative Pulse Width TWRE RD Minimum Pulse Width 450 230 — nsec CS = HIGH, CE = LOW, (Note 2) TWRD RD Minimum Delay Time 150 50 — nsec CS = HIGH, CE = LOW, (Note 2) TWWD WR Minimum Pulse Width 75 25 — nsec CS = HIGH, CE = LOW, (Note 1) Note 1: Demand mode, CONT/DEMAND = LOW. Figure 8-2 timing diagram. CL = 100 pF. 2: Continuous mode, CONT/DEMAND = HIGH. Figure 8-4 timing diagram. 3: Digital inputs have CMOS logic levels and internal pull-up/pull-down resistors. For TTL compatibility, external pull-up resistors to VDD are recommended. DS21479D-page 4  2001-2012 Microchip Technology Inc. TC850 -5V +5V 40 VDD 16 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 17 61.44 kHz 20 DGND 22 VSS BUSY DB7 INDB6 ANALOG COMMON DB5 REF1+ DB4 REF2+ DB3 REFDB2 TC850 CREF1+ DB1 DB0 CREF1CS CREF2+ CE CREF2WR BUFFER RD INTIN CONT/DEMAND OVR/POL INTOUT L/H OSC1 ** 21 32 100 MΩ 31 30 39 33 36 38 37 34 0.01 μF Input +1.6384V +0.0256V 1 μF* 1 μF* 35 25120 MkW 24 23 TEST 19 ** 18 IN+ RINT 0.1 μF CINT NC OSC2 COMP CINTA CINTB CBUFA CBUFB 26 28 29 27 0.1 μF 0.1 μF 0.1 μF 0.1 μF 0.1 μF NOTES: Unless otherwise specified, all 0.1 μF capacitors are film dielectric. Ceramic capacitors are not recommended. NC = No Connection *Polypropylene capacitors. ** 100 pF Mica capacitors. FIGURE 1-1: Standard Test Circuit Configuration  2001-2012 Microchip Technology Inc. DS21479D-page 5 TC850 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Pin Number (40-Pin PDIP/CERDIP) Pin Number (44-Pin PLCC) Symbol 1 2 CS Chip Select, active HIGH. Logically ANDed, with CE to enable read and write inputs (Note 1). 2 3 CE Chip enable, active LOW (Note 2). 3 4 WR Write input, active LOW. When chip is selected (CS = HIGH and CE = LOW) and in Demand mode (CONT/DEMAND = LOW), a logic LOW on WR starts a conversion (Note 1). 4 5 RD Read input, active LOW. When CS = HIGH and CE = LOW, a logic LOW on RD enables the 3-state data outputs (Note 2). 5 6 CONT/ DEMAND Conversion control input. When CONT/DEMAND = LOW, conversions are initiated by the WR input. When CONT/DEMAND = HIGH, conversions are performed continuously (Note 1). 6 7 OVR/POL Overrange/polarity data-select input. When making conversions in the Demand mode (CONT/DEMAND = LOW), OVR/POL controls the data output on DB7 when the high-order byte is active (Note 2). 7 8 L/H Low/high byte-select input. When CONT/DEMAND = LOW, this input controls whether low-byte or high-byte data is enabled on DB0 through DB7 (Note 2). 8 9 DB7 Most Significant data bit output. When reading the A/D conversion result, the polarity, overrange and DB7 data are output on this pin. 9-15 10-17 DB6-DB0 16 18 BUSY A/D conversion status output. BUSY goes to a logic HIGH at the beginning of the de-integrate phase, then goes LOW when conversion is complete. The falling edge of BUSY can be used to generate a P interrupt. 17 19 OSC1 Crystal oscillator connection or external oscillator input. 18 20 OSC2 Crystal oscillator connection. 19 21 TEST For factory testing purposes only. Do not make external connection to this pin. 20 22 DGND Digital ground connection. Connection for comparator auto-zero capacitor. Bypass to VSS with 0.1 F. Description Data outputs DB6-DB0. 3-state, bus compatible. 21 24 COMP 22 25 VSS 23 26 INTOUT 24 27 INTIN 25 28 BUFFER 26 29 CBUFB Connection for buffer auto-zero capacitor. Bypass to VSS with 0.1 F. 27 30 CBUFA Connection to buffer auto-zero capacitor. Bypass to VSS with 0.1 F. 28 31 CINTA Connection for integrator auto-zero capacitor. Bypass to VSS with 0.1 F. 29 32 CINTB 30 33 ANALOG COMMON Negative power supply connection, typically -5V. Output of the integrator amplifier. Connect to CINT. Input to the integrator amplifier. Connect to summing node of RINT and CINT. Output of the input buffer. Connect to RINT. Connection for integrator auto-zero capacitor. Bypass to VSS with 0.1 F. Analog common. 31 35 IN– Negative differential analog input. 32 36 IN+ Positive differential analog input. Note 1: This pin incorporates a pull-down resistor to DGND. 2: This pin incorporates a pull-up resistor to VDD. 3: Pins 1, 23 and 34 (44-PLCC) package are NC “No Internal connection”. DS21479D-page 6  2001-2012 Microchip Technology Inc. TC850 TABLE 2-1: PIN FUNCTION TABLE (CONTINUED) Pin Number (40-Pin PDIP/CERDIP) Pin Number (44-Pin PLCC) 33 37 REF2+ 34 38 CREF2+ Positive connection for VREF2 reference capacitor. 35 39 CREF2– Negative connection for VREF2 reference capacitor. 36 40 REF– 37 41 CREF1– 38 42 CREF1+ Positive connection for VREF1 reference capacitor. 39 43 REF1+ Positive input for VREF1. 40 44 VDD Symbol Description Positive input for reference voltage VREF2. (VREF2 = VREF1/64) Negative input for reference voltages. Negative connection for VREF1 reference capacitor. Positive power supply connection, typically +5V. Note 1: This pin incorporates a pull-down resistor to DGND. 2: This pin incorporates a pull-up resistor to VDD. 3: Pins 1, 23 and 34 (44-PLCC) package are NC “No Internal connection”.  2001-2012 Microchip Technology Inc. DS21479D-page 7 TC850 3.0 DETAILED DESCRIPTION EQUATION 3-1: The TC850 is a multiple-slope, integrating A/D converter (ADC). The multiple-slope conversion process, combined with chopper-stabilized amplifiers, results in a significant increase in ADC speed, while maintaining very high resolution and accuracy. 3.1  where: Dual-Slope Conversion Principles The conventional dual-slope converter measurement cycle (shown in Figure 3-1) has two distinct phases: 1. 2. TINT VREF TDEINT 1 VIN(T)DT = R C RINTCINT 0 INT INT VREF = Reference voltage TINT = Signal integration time (fixed) TDEINT = Reference voltage integration time (variable). 3.2 Multiple-Slope Conversion Principles Input signal integration Reference voltage integration (de-integration). Signal De-integrate Reference De-integrate End of Conversion Integrator Output Auto Zero FIGURE 3-1: 0V Time Dual-Slope ADC Cycle The input signal being converted is integrated for a fixed time period, measured by counting clock pulses. An opposite polarity constant reference voltage is then de-integrated until the integrator output voltage returns to zero. The reference integration time is directly proportional to the input signal. One limitation of the dual-slope measurement technique is conversion speed. In a typical dual-slope method, the auto-zero and integrate times are each one-half of the de-integrate time. For a 15-bit conversion, 214 + 214 + 215 (65,536) clock pulses are required for auto-zero, integrate and de-integrate phases, respectively. The large number of clock cycles effectively limits the conversion rate to about 2.5 conversions per second, when a typical analog CMOS fabrication process is used. The TC850 uses a multiple-slope conversion technique to increase conversion speed (Figure 3-2). This technique makes use of a two-slope de-integration phase and permits 15-bit resolution up to 40 conversions per second. In a simple dual-slope converter, complete conversion requires the integrator output to “ramp-up” and “rampdown.” Most dual-slope converters add a third phase, auto-zero. During auto-zero, offset voltages of the input buffer, integrator and comparator are nulled, thereby eliminating the need for zero offset adjustments. During the TC850’s de-integration phase, the integration capacitor is rapidly discharged to yield a resolution of 9 bits. At this point, some charge will remain on the capacitor. This remaining charge is then slowly de-integrated, producing an additional 6 bits of resolution. The result is 15 bits of resolution achieved with only 29 + 26 (512 + 64, or 576) clock pulses for de-integration. A complete conversion cycle occupies only 1280 clock pulses. Dual-slope converter accuracy is unrelated to the integrating resistor and capacitor values, as long as they are stable during a measurement cycle. By converting the unknown analog input voltage into an easily measured function of time, the dual-slope converter reduces the need for expensive, precision passive components. In order to generate “fast-slow” de-integration phases, two voltage references are required. The primary reference (VREF1) is set to one-half of the full scale voltage (typically VREF1 = 1.6384V, and VFS = 3.2768V). The secondary voltage reference (VREF2) is set to VREF1/64 (typically 25.6 mV). To maintain 15-bit linearity, a tolerance of 0.5% for VREF2 is recommended. Noise immunity is an inherent benefit of the integrating conversion method. Noise spikes are integrated, or averaged, to zero during the integration period. Integrating ADCs are immune to the large conversion errors that plague successive approximation converters in high-noise environments. "Fast" Reference De-integrate (9-Bit Resolution) "Slow" Reference De-integrate (6-Bit Resolution) Signal Integrate A simple mathematical equation relates the input signal, reference voltage and integration time: End of Conversion Integrator Output Auto Zero 0V Time FIGURE 3-2: Integration Cycle DS21479D-page 8 “Fast Slow” Reference De-  2001-2012 Microchip Technology Inc. TC850 4.0 ANALOG SECTION DESCRIPTION 4.1 Each conversion consists of three phases: The TC850 analog section consists of an input buffer amplifier, integrator amplifier, comparator and analog switches. A simplified block diagram is shown in Figure 4-1. CREF1 REF1+ REF1- Conversion Timing 1. 2. 3. Zero Integrator Signal Integrate Reference Integrate (or De-integrate) Each conversion cycle requires 1280 internal clock cycles (Figure 4-2). CINT RINT CREF2 CREF2- REF2+ CREF2- BUFF CREF1- CREF1+ DE DE DE DE - Integrator* + Buffer* IN+ DE1 (-) INT ANALOG COMMON DE1 (+) DE1 (+) INT INTOUT INTIN DE1 (-) DE1 (-) – + DE1 (+) DE2 (+) DE2 (-) – To Digital Section + Comparator* Z1 TC850 INT IN- *Auto Zeroed Amplifiers FIGURE 4-1: Analog Section Simplified Schematic 1280 Clock Cyles Internal Clock . . . . . . . 246 Conversion Phase FIGURE 4-2: Zero Integrator . . 256 Signal Integrate . . . . . . . . . . . . 778 Reference Integrate Conversion Timing  2001-2012 Microchip Technology Inc. DS21479D-page 9 TC850 4.2 Zero Integrator Phase During the zero integrator phase, the differential input signal is disconnected from the circuit by opening internal analog gates. The internal nodes are shorted to analog common (ground) to establish a zero input condition. At the same time, a feedback loop is closed around the input buffer, integrator and comparator. The feedback loop ensures the integrator output is near 0V before the signal integrate phase begins. During this phase, a chopper-stabilization technique is used to cancel offset errors in the input buffer, integrator and comparator. Error voltages are stored on the CBUFF, CINT and COMP capacitors. The zero integrate phase requires 246 clock cycles. 4.3 Signal Integrate Phase 4.4 Reference Integrate Phase During reference integrate phase, the charge stored on the integrator capacitor is discharged. The time required to discharge the capacitor is proportional to the analog input voltage. The reference integrate phase is divided into three subphases: 1. 2. 3. Fast Slow Overrange de-integrate During fast de-integrate, VIN- is internally connected to analog common and VIN+ is connected across the previously-charged reference capacitor (CREF1). The integrator capacitor is rapidly discharged for a maximum of 512 internal clock pulses, yielding 9 bits of resolution. The zero integrator loop is opened and the internal differential inputs are connected to IN+ and IN-. The differential input signal is integrated for a fixed time period. The TC850 signal integrate period is 256 clock periods, or counts. The crystal oscillator frequency is before clocking the internal counters. During the slow de-integrate phase, the internal VIN+ node is now connected to the CREF2 capacitor and the residual charge on the integrator capacitor is further discharged a maximum of 64 clock pulses. At this point, the analog input voltage has been converted with 15 bits of resolution. The integration time period is: If the analog input is greater than full scale, the TC850 performs up to three overrange de-integrate subphases. Each subphase occupies a maximum of 64 clock pulses. The overrange feature permits analog inputs up to 192 LSBs greater than full scale to be correctly converted. This feature permits the user to digitally null up to 192 counts of input offset, while retaining full 15-bit resolution. EQUATION 4-1: TINT = 4 x 256 FOSC In addition to 512 counts of fast, 64 counts of slow and 192 counts of overrange de-integrate, the reference integrate phase uses 10 clock pulses to permit internal nodes to settle. Therefore, the reference integrate cycle occupies 778 clock pulses. DS21479D-page 10  2001-2012 Microchip Technology Inc. TC850 5.0 PIN DESCRIPTION (ANALOG) 5.1 Differential Inputs (IN+ and IN–) The analog signal to be measured is applied at the IN+ and IN– inputs. The differential input voltage must be within the Common mode range of the converter. The input Common mode range extends from VDD - 1.5V to VSS +1.5V. Within this Common mode voltage range, an 80 dB CMRR is typical. The integrator output also follows the Common mode voltage. The integrator output must not be allowed to saturate. A worst-case condition exists, for example, when a large, positive Common mode voltage, with a near full scale negative differential input voltage, is applied. The negative input signal drives the integrator positive when most of its available swing has been used up by the positive Common mode voltage. For applications where maximum Common mode range is critical, integrator swing can be reduced. The integrator output can swing within 0.4V of either supply without loss of linearity. 5.2 5.3 Analog Common (ANALOG COMMON) Analog common is used as the IN- return during the zero integrator and de-integrate phases of each conversion. If IN- is at a different potential than analog common, a Common mode voltage exists in the system. This signal is rejected by the 80dB CMRR of the converter. However, in most applications, IN- will be set at a fixed, known voltage (power supply common, for instance). In this case, analog common should be tied to the same point so that the Common mode voltage is eliminated. Differential Reference (VREF) The TC850 requires two reference voltage sources in order to generate the “fast-slow” de-integrate phases. The main voltage reference (VREF1) is applied between the REF1+ and REF- pins. The secondary reference (VREF2) is applied between the REF2+ and REF- pins. The reference voltage inputs are fully differential and the reference voltage can be generated anywhere within the power supply voltage of the converter. However, to minimize rollover error, especially at high conversion rates, keep the reference Common mode voltage (i.e., REF-) near or at the analog common potential. All voltage reference inputs are high-impedance. Average reference input current is typically only 30 pA.  2001-2012 Microchip Technology Inc. DS21479D-page 11 TC850 6.0 DIGITAL SECTION DESCRIPTION The TC850 digital section consists of two sets of conversion counters, control and sequencing logic, clock oscillator and divider, data latches and an 8-bit, 3-state interface bus. A simplified schematic of the bus interface logic is shown in Figure 6-1 6.1 Clock Oscillator The TC850 includes a crystal oscillator on-chip. All that is required is to connect a crystal across OSC1 and OSC2 pins and to add two inexpensive capacitors DBO–DB7 8 3-State Buffer 8 Output Enable Octal 2-Input Mux (Figure 1-1). The oscillator output is ÷ 4 prior to clocking the A/D internal counters. For example, a 100 kHz crystal produces a system clock frequency of 25 kHz. Since each conversion requires 1280 clock periods, in this case the conversion rate will be 25,000/1280, or 19.5 conversions per second. In most applications, however, an external clock is divided down from the microprocessor clock. In this case, the OSC1 pin is used as the external oscillator input and OSC2 is left unconnected. The external clock driver should swing from digital ground to VDD. The ÷ 4 function is active for both external clock and crystal oscillator operations. 8 Low-Byte Up/Down Counter 7 Select High-Byte Up/Down Counter L/H RD CE To A/D Control Logic CS TC850 POL/OVR Select Polarity 2-Input Mux Overrange Start Conversion WR CONT/ DEMAND End of Conversion FIGURE 6-1: 6.2 Bus Interface Simplified Schematic Digital Operating Modes Two modes of operation are available with the TC850, continuous conversions and on-demand. The Operating mode is controlled by the CONT/DEMAND input. The bus interface method is different for Continuous and Demand modes of operation. 6.2.1 DEMAND MODE OPERATION When CONT/DEMAND is low, the TC850 performs one conversion each time the chip is selected and the WR input is pulsed low. Data is valid on the falling edge of the BUSY output and can be accessed using the interface truth table (Table 6-1). DS21479D-page 12 6.2.2 CONTINUOUS MODE OPERATION When CONT/DEMAND is high, the TC850 continuously performs conversions. Data will be valid on the falling edge of the BUSY output and remains valid for 443-1/2 clock cycles. The low/high (L/H) byte-select and overrange/polarity (OVR/POL) inputs are disabled during Continuous mode operation. Data must be read in three consecutive bytes, as shown in Table 6-1. Note: In Continuous mode, the conversion result must be read within 443-1/2 clock cycles of the BUSY output falling edge. After this time (i.e.,1/2 clock cycle before BUSY goes high) the internal counters are reset and the data is lost.  2001-2012 Microchip Technology Inc. TC850 TABLE 6-1: BUS INTERFACE TRUTH TABLE CE • CS Pins 1 and 2 RD Pin 4 CONT/DEMAND Pin 5 L/H Pin 7 OVR/POL Pin 6 DB7 Pin 8 DB6–DB0 Pin 9-Pin 15 (Note 1) 0 0 0 0 0 “1” = Input Positive Data Bits 14 - 8 0 0 0 0 1 “1” = Input Overrange (Note 2) Data Bits 14 - 8 0 0 0 1 X Data Bit 7 Data Bits 6 - 0 0 0 1 X X Note 3 0 1 X X X High-Impedance State 1 X X X X High-Impedance State Note 1: Pin numbers refer to 40-pin PDIP. 2: Extended overrange operation: Although rated at 15 bits (±32,767 counts) of resolution, the TC850 provides an additional 191 counts above full scale. For example, with a full-scale input of 3.2768V, the maximum analog input voltage which will be properly converted is 3.2958V. The extended resolution is signified by the overrange bit being high and the low-order byte contents being between 0 and 190. For example, with a full-scale voltage of 3.2768V: VIN Overrange Bit Low Byte Data Bits 14–8 3.2767V Low 25510 12710 3.2768V High 00010 010 3.2769V High 00110 010 3.2867V High 09910 010 3: Continuous mode data transfer: a. In Continuous mode, data MUST be read in three sequential bytes after the BUSY output goes low: (1) The first byte read will be the high-order byte, with DB7 = polarity. (2) The second byte read will contain the low-order byte. (3) The third byte read will again be the high-order byte, but with DB7 = overrange. b. All three data bytes must be read within 443-1/2 clock cycles after the falling edge of BUSY. c. The c input must go high after each byte is read, so that the internal byte counter will be incremented. However, the CS and CEinputs can remain enabled through the entire data transfer sequence.  2001-2012 Microchip Technology Inc. DS21479D-page 13 TC850 6.3 6.3.1 Pin Description (Digital) CHIP SELECT AND CHIP ENABLE (CS AND CE) The CS and CE inputs permit easy interfacing to a variety of digital bus systems. CE is active LOW while CS is active HIGH. These inputs are logically ANDed internally and are used to enable the RD and WR inputs. 6.3.6 CONTINUOUS/DEMAND MODE INPUT (CONT/DEMAND) This input controls the TC850 Operating mode. When CONT/DEMAND is HIGH, the TC850 performs conversions continuously. In Continuous mode, data must be read in the prescribed sequence shown in Table 6-1. Also, all three data bytes must be read within 443-1/2 internal clock cycles after the BUSY output goes low. After 443-1/2 clock cycles data will be lost. The write input is used to initiate a conversion when the TC850 is in Demand mode. CS and CE must be active for the WR input to be recognized. The status of the data bus is meaningless during the WR pulse, because no data is actually written into the TC850. When CONT/DEMAND is LOW, the TC850 begins a conversion each time CS and CE are active and WR is being pulsed LOW. The conversion is complete and data can be read after the falling edge of the BUSY output. In Demand mode, data can be read in any sequence and remains valid until WR is again pulsed LOW. 6.3.3 6.3.7 6.3.2 WRITE ENABLE INPUT (WR) READ ENABLE INPUT (RD) The read input, combined with CS and CE, enable the 3-state data bus outputs. Also, in Continuous mode, the rising edge of the RD input activates an internal byte counter to sequentially read the three data bytes. 6.3.4 LOW/HIGH BYTE SELECT (L/H) The L/H input determines whether the low (Least Significant) Byte or high (Most Significant) Byte of data is placed on the 3-state data bus. This input is meaningful only when the TC850 is in the Demand mode. In the Continuous mode, data must be read in three predetermined bytes, so the L/H input is ignored. 6.3.5 BUSY OUTPUT (BUSY) The BUSY output is used to convey an end-of-conversion to external logic. BUSY goes HIGH at the beginning of the de-integrate phase and goes LOW at the end of the conversion cycle. Data is valid on the falling edge of BUSY. The output-high period is fixed at 836 clock periods, regardless of the analog input value. BUSY is active during Continuous and Demand mode operation. This output can also be used to generate an end-ofconversion interrupt in P-based systems. Noninterrupt-driven systems can poll BUSY to determine when data is valid. OVERRANGE/POLARITY BIT SELECT (OVR/POL) The TC850 provides 15 bits of resolution, plus polarity and overrange bits. Thus, 17 bits of information must be transferred on an 8-bit data bus. To accomplish this, the overrange and polarity bits are multiplexed onto data bit DB7 of the Most Significant Byte. When OVR/POL is HIGH, DB7 of the high byte contains the overrange status (HIGH = analog input overrange, LOW = input within full scale). When OVR/POL is LOW, DB7 is HIGH for positive analog input polarity and LOW for negative polarity. The OVR/POL input is meaningful only when CS, CE and RD are active, and L/H is LOW (i.e., the Most Significant Byte is selected). OVR/POL is ignored when the TC850 is in Continuous mode. DS21479D-page 14  2001-2012 Microchip Technology Inc. TC850 7.0 ANALOG SECTION TYPICAL APPLICATIONS 7.1 Component Selection 7.1.1 REFERENCE VOLTAGE The typical value for reference voltage VREF1 is 1.6384V. This value yields a full scale voltage of 3.2768V and resolution of 100 V per step. The VREF2 value is derived by dividing VREF1 by 64. Thus, typical VREF2 value is 1.6384V/64, or 25.6 mV. The VREF2 value should be adjusted within ±1% to maintain 15-bit accuracy for the total conversion process; EQUATION 7-1: : VREF = VREF1 ± 1% 64 The reference voltage is not limited to exactly 1.6384V, however, because the TC850 performs a ratiometric conversion. Therefore, the conversion result will be: EQUATION 7-2: Digital Counts = VIN • 16384 VREF1 The full scale voltage can range from 3.2V to 3.5V. Full scale voltages of less than 3.2V will result in increased noise in the Least Significant bits, while a full scale above 3.5V will exceed the input common-mode range. 7.1.2 7.1.3 INTEGRATION CAPACITOR The integration capacitor should be selected to produce an integrator swing of 4V at full scale. The capacitor value is easily calculated: EQUATION 7-4: C= VFS RINT • 4 • 256 4V FCLOCK where: FCLOCK is the crystal or external oscillator frequency and VFS is the maximum input voltage. The integration capacitor should be selected for low dielectric absorption to prevent rollover errors. A polypropylene, polyester or polycarbonate dielectric capacitor is recommended. 7.1.4 REFERENCE CAPACITORS The reference capacitors require a low-leakage dielectric, such as polypropylene, polyester or polycarbonate. A value of 1 F is recommended for operation over the temperature range. If high-temperature operation is not required, the CREF values can be reduced. 7.1.5 AUTO-ZERO CAPACITORS Five capacitors are required to auto-zero the input buffer, integrator amplifier and comparator. Recommended capacitors are 0.1 F film dielectric (such as polyester or polypropylene). Ceramic capacitors are not recommended. INTEGRATION RESISTOR The TC850 buffer supplies 25 A of integrator charging current with minimal linearity error. RINT is easily calculated: EQUATION 7-3: RINT = VFULLSCALE 25 A For a full scale voltage of 3.2768V, values of RINT between 120 k and 150 k are acceptable.  2001-2012 Microchip Technology Inc. DS21479D-page 15 TC850 8.0 8.1 DIGITAL SECTION TYPICAL APPLICATIONS 10 MΩ Oscillator The TC850 may operate with a crystal oscillator. The crystal selected should be designed for a Pierce oscillator, such as an AT-cut quartz crystal. The crystal oscillator schematic is shown in Figure 8-1. Since low-frequency crystals are very large and ceramic resonators are too lossy, the TC850 clock should be derived from an external source, such as a microprocessor clock. The clock should be input on the OSC1 pin and no connection should be made to the OSC2 pin. The external clock should swing between DGND and VDD. Since oscillator frequency is ÷ 4 internally and each conversion requires 1280 internal clock cycles, the conversion time will be: EQUATION 8-1: Conversion Time = System Clock ¸4 4 x 1280 FCLOCK An important advantage of the integrating ADC is the ability to reject periodic noise. This feature is most often used to reject line frequency (50 Hz or 60 Hz) noise. Noise rejection is accomplished by selecting the integration period equal to one or more line frequency cycles. The desired clock frequency is selected as follows: TC850 17 61.44 kHz 100 pF 100 pF FIGURE 8-1: 8.2 18 Crystal Oscillator Schematic Data Bus Interfacing The TC850 provides an easy and flexible digital interface. A 3-state data bus and six control inputs permit the TC850 to be treated as a memory device, in most applications. The conversion result can be accessed over an 8-bit bus or via a P I/O port. A typical P bus interface for the TC850 is shown in Figure 8-2. In this example, the TC850 operates in the Demand mode and conversion begins when a write operation is performed to any decoded address space. The BUSY output interrupts the P at the end-of-conversion. The A/D conversion result is read as three memory bytes. The two LSBs of the address bus select high/low byte and overrange/polarity bit data, while high-order address lines enable the CE input. EQUATION 8-2: FCLOCK = FNOISE x 4 x 256 TC850 where: FNOISE is the noise frequency to be rejected, 4 represents the clock divider, 256 is the number of integrate cycles. If noise rejection is not important, other clock frequencies can be used. The TC850 will typically operate at conversion rates ranging from 3 to 40 conversions/sec, corresponding to oscillator frequencies from 15.36 kHz to 204.8 kHz. L/H OVR/POL RD WR BUSY CS CONT/DEMAND Address X00 X01 X10 FIGURE 8-2: Bus DS21479D-page 16 Address Decode +5V DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 A2 μP ... For example, 60 Hz noise will be rejected with a clock frequency of 61.44 kHz, giving a conversion rate of 12 conversions/sec. Integer submultiples of 61.44 kHz (such as 30.72 kHz, etc.) will also reject 60 Hz noise. For 50 Hz noise rejection, a 51.2 kHz frequency is recommended. DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 CE A15 A0 A1 RD WR INTERRUPT Data Bus High Byte Polarity Low Byte High Byte Overrange Interface to Typical P Data  2001-2012 Microchip Technology Inc. TC850 Figure 8-3 shows a typical interface to a P I/O port or single-chip C. The TC850 operates in the Continuous mode and can either interrupt the C/P or be polled with an input pin. PA0 PA1 PA2 PA3 PA4 PA5 mC OR mP PA6 I/O PORT PA7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 INTERRUPT BUSY PB0 RD CONT/DEMAND CS CE WR +5V TC850 NC FIGURE 8-3: Interface to Typical P I/O Port or Single Chip C Since the PA0-PA7 inputs are dedicated to reading A/D data, the A/D CS/CE inputs can be enabled continuously. In Continuous mode, data must be read in 3 bytes, as shown in Table 6-1. The required RD pulses are provided by a C/P output pin. The circuit of Figure 8-3 can also operate in the Demand mode, with the start-up conversion strobe generated by a C/P output pin. In this case, the L/H and CONT/DEMAND inputs can be controlled by I/O pins and the RD input connected to digital ground.  2001-2012 Microchip Technology Inc. 8.3 Demand Mode Interface Timing When CONT/DEMAND input is LOW, the TC850 performs a conversion each time CE and CS are active and WR is strobed LOW. The Demand mode conversion timing is shown in Figure 8-1. BUSY goes LOW and data is valid 1155 clock pulses after WR goes LOW. After BUSY goes low, 125 additional clock cycles are required before the next conversion cycle will begin. Once conversion is started, WR is ignored for 1100 internal clock cycles. After 1100 clock cycles, another WR pulse is recognized and initiates a new conversion when the present conversion is complete. A negative edge on WR is required to begin conversion. If WR is held LOW, conversions will not occur continuously. The A/D conversion data is valid on the falling edge of BUSY and remains valid until one-half internal clock cycle before BUSY goes HIGH on the succeeding conversion. BUSY can be monitored with an I/O pin to determine end of conversion or to generate a P interrupt. In Demand mode, the three data bytes can be read in any desired order. The TC850 is simply regarded as three bytes of memory and accessed accordingly. The bus output timing is shown in Figure 8-2. 8.4 Continuous Mode Interface Timing When the CONT/DEMAND input is HIGH, the TC850 performs conversions continuously. Data will be valid on the falling edge of BUSY and all three bytes must be read within 443-1/2 internal clock cycles of BUSY going LOW. The timing diagram is shown in Figure 8-3. In Continuous mode, OVR/POL and L/H byte-select inputs are ignored. The TC850 automatically cycles through three data bytes, as shown in Table 6-1. Bus output timing in the Continuous mode is shown in Figure 8-4. DS21479D-page 17 TC850 . . . . . . . . . . . . Internal Clock CS . CE 1100 Clock Cycles Next Convert Command will be Recognized WR Pulses are Ignored WR Next Conversion can Begin 836 Clock Cycles 319 Clock Cycles 125 Clock Cycles BUSY DB0-DB7 FIGURE 8-4: Previous Conversion Data Valid Data Meaningless New Conversion Data Valid Conversion Timing, Demand Mode TDHC TCE CS . CE TDHR TRE * RD DB0-DB6 HI-Z DB7 HI-Z Data Bits 0 tp 6 Data Bits 8 to 14 "1"= Input Overrange "1"= Positive Polarity Data Bit 7 High-Impedance High-Impedance tOP OVR/POL Don't Care TLH Don't Care L/H NOTE: CONT/DEMAND = LOW *RD (as well as CS and CE) can go HIGH after each byte is read (i.e., in a mP bus interface) or remain LOW during the entire DATA-READ sequence (i.e., mP I/O port interface). FIGURE 8-5: DS21479D-page 18 Bus Output Timing, Demand Mode  2001-2012 Microchip Technology Inc. TC850 . . . . . . . . . . . . Internal Clock . . . . . 1280 Internal Clock Cycles Busy 443-1/2 Clock Cycles 836 Clock Cycles 1/2 Clock Cycle DB0-DB7 Data Valid Data Meaningless FIGURE 8-6: Data Meaningless Conversion Timing, Continuous Mode CONT/DEMAND BUSY TWRE RD TRE DB0-DB7 HI-Z TWRD Data Bits 8-14 Polarity Data Bits 0-7 Data Bits 8-14 Overrange High-Impedance State NOTES: CS = HIGH; CE = LOW FIGURE 8-7: Bus Output Timing, Continuous Mode  2001-2012 Microchip Technology Inc. DS21479D-page 19 TC850 9.0 PACKAGING INFORMATION 9.1 Package Marking Information Package marking data not available at this time 9.2 Taping Form Component Taping Orientation for 44-Pin PLCC Devices User Direction of Feed Pin 1 W P Standard Reel Component Orientation for 713 Suffix Device Carrier Tape, Number of Components Per Reel and Reel Size Package 44-Pin PLCC Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 32 mm 24 mm 500 13 in NOTE: Drawing does not represent total number of pins. DS21479D-page 20  2001-2012 Microchip Technology Inc. TC850 9.3 Package Dimensions Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 40-Pin CERDIP (Wide) Pin 1 .540 (13.72) .510 (12.95) .030 (0.76) Min. .098 (2.49) Max. 2.070 (52.58) 2.030 (51.56) .620 (15.75) .590 (15.00) .060 (1.52) .020 (0.51) .210 (5.33) .170 (4.32) .150 (3.81) Min. .200 (5.08) .125 (3.18) .110 (2.79) .090 (2.29) .065 (1.65) .045 (1.14) .015 (0.38) .008 (0.20) 3° Min. .700 (17.78) .620 (15.75) .020 (0.51) .016 (0.41) Dimensions: inches (mm) 9.3 Package Dimensions (Continued) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 40-Pin PDIP (Wide) Pin 1 .555 (14.10) .530 (13.46) 2.065 (52.45) 2.027 (51.49) .610 (15.49) .590 (14.99) .200 (5.08) .140 (3.56) .040 (1.02) .020 (0.51) .150 (3.81) .115 (2.92) .110 (2.79) .090 (2.29) .070 (1.78) .045 (1.14) .015 (0.38) .008 (0.20) 3° Min. .700 (17.78) .610 (15.50) .022 (0.56) .015 (0.38) Dimensions: inches (mm)  2001-2012 Microchip Technology Inc. DS21479D-page 21 TC850 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 44-Pin PLCC Pin 1 .021 (0.53) .013 (0.33) .050 (1.27) Typ. .695 (17.65) .685 (17.40) .630 (16.00) .591 (15.00) .656 (16.66) .650 (16.51) .032 (0.81) .026 (0.66) .020 (0.51) Min. .656 (16.66) .650 (16.51) .120 (3.05) .090 (2.29) .695 (17.65) .685 (17.40) .180 (4.57) .165 (4.19) Dimensions: inches (mm) DS21479D-page 22  2001-2012 Microchip Technology Inc. TC850 10.0 REVISION HISTORY Revision D (December 2012) Added a note to each package outline drawing.  2001-2012 Microchip Technology Inc. DS21479D-page 23 TC850 NOTES: DS21479D-page 24  2001-2012 Microchip Technology Inc. TC850 SALES AND SUPPORT Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. Your local Microchip sales office The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.  2001-2012 Microchip Technology Inc. DS21479D-page 25 TC850 NOTES: DS21479D-page 26  2001-2012 Microchip Technology Inc. TC850 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2001-2012 Microchip Technology Inc. DS21479D-page 27 TC850 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: TC850 Literature Number: DS21479D Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21479D-page 28  2001-2012 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2001-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620768433 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==  2001-2012 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS21479D-page 29 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Osaka Tel: 81-6-6152-7160 Fax: 81-6-6152-9310 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8569-7000 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 China - Hangzhou Tel: 86-571-2819-3187 Fax: 86-571-2819-3189 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Hong Kong SAR Tel: 852-2943-5100 Fax: 852-2401-3431 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Taiwan - Hsin Chu Tel: 886-3-5778-366 Fax: 886-3-5770-955 China - Shenzhen Tel: 86-755-8864-2200 Fax: 86-755-8203-1760 Taiwan - Kaohsiung Tel: 886-7-213-7828 Fax: 886-7-330-9305 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Taipei Tel: 886-2-2508-8600 Fax: 886-2-2508-0102 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 DS21479D-page 30 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Japan - Tokyo Tel: 81-3-6880- 3770 Fax: 81-3-6880-3771 11/29/12  2001-2012 Microchip Technology Inc.