TCN75-3.3MOA713G

TCN75 2-Wire Serial Temperature Sensor and Thermal Monitor Features: • Solid-State Temperature Sensing: 0.5°C Accuracy (Typ.) • Operates from -55°C to +125°C • Operating Supply Range: 2.7V to 5.5V • Programmable Trip Point and Hysteresis with Power-up Defaults • Standard 2-Wire Serial Interface • Thermal Event Alarm Output Functions as Interrupt or Comparator/Thermostat Output • Up to 8 TCN75s may Share the Same Bus • Shutdown Mode for Low Standby Power Consumption • 5V Tolerant I/O at VDD = 3V • Low Power: - 250 A (Typ.) Operating - 1 A (Typ.) Shutdown Mode • 8-Pin SOIC and MSOP Packaging Package Type SOIC SDA 1 8 VDD SCL 2 7 A0 INT/CMPTR 3 6 A1 GND 4 5 A2 TCN75MOA MSOP SDA 1 8 VDD 7 A0 INT/CMPTR 3 6 A1 GND 4 5 A2 SCL 2 TCN75MUA General Description: Applications: • • • • Thermal Protection for High-Performance CPUs Solid-State Thermometer Fire/Heat Alarms Thermal Management in Electronic Systems: - Computers - Telecom Racks - Power Supplies/UPS/Amplifiers • Copiers/Office Electronics • Consumer Electronics • Process Control The TCN75 is a serially programmable temperature sensor that notifies the host controller when ambient temperature exceeds a user programmed set point. Hysteresis is also programmable. The INT/CMPTR output is programmable as either a simple comparator for thermostat operation or as a temperature event interrupt. Communication with the TCN75 is accomplished via a two-wire bus that is compatible with industry standard protocols. This permits reading the current temperature, programming the set point and hysteresis, and configuring the device. The TCN75 powers up in Comparator mode with a default set point of 80°C with 5°C hysteresis. Defaults allow independent operation as a stand-alone thermostat. A shutdown command may be sent via the 2-wire bus to activate the low-power Standby mode. Address selection inputs allow up to eight TCN75s to share the same 2-wire bus for multizone monitoring. All registers can be read by the host and the INT/ CMPTR output’s polarity is user programmable. Both polled and interrupt driven systems are easily accommodated. Small physical size, low installed cost, and ease-of-use make the TCN75 an ideal choice for implementing sophisticated system management schemes.  2001-2012 Microchip Technology Inc. DS21490D-page 1 TCN75 Device Selection Table Part Number Supply Voltage Package Junction Temperature Range TCN75-3.3MOA 3.3 8-Pin SOIC -55°C to +125°C TCN75-5.0MOA 5.0 8-Pin SOIC -55°C to +125°C TCN75-3.3MUA 3.3 8-Pin MSOP -55°C to +125°C TCN75-5.0MUA 5.0 8-PIn MSOP -55°C to +125°C Functional Block Diagram INT/CMPTR TCN75 9-Bit DS A/D Converter VDD Temp Sensor Control Logic Register Set Configuration Temperature TSET THYST SDA SCL A0 A1 A2 DS21490D-page 2 Two Wire Serial Port Interface  2001-2012 Microchip Technology Inc. TCN75 1.0 ELECTRICAL CHARACTERISTICS *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings* Supply Voltage (VDD) ............................................ 6.0V ESD Susceptibility (Note 3) ............................... 1000V Voltage on Pins: A0, A1, A2 .......... (GND – 0.3V) to (VDD + 0.3V) Voltage on Pins: SDA, SCL, INT/CMPTR .. (GND – 0.3V) to 5.5V Thermal Resistance (Junction to Ambient) 8-Pin SOIC.......................................... 170°C/W 8-Pin MSOP ....................................... 250°C//W Operating Temperature Range (TJ): -55°C to +125°C Storage Temperature Range (TSTG): -65°C to +150°C TCN75 ELECTRICAL SPECIFICATIONS Electrical Characteristics: VDD = 2.7V – 5.5V, -55°C  (TA = TJ)  125°C, unless otherwise noted. Symbol Parameter Min Typ Max Units Test Conditions Power Supply VDD Power Supply Voltage 2.7 — 5.5 — IDD Operating Current — — 0.250 — — 1.0 mA Serial Port Inactive (TA = TJ = 25°C) Serial Port Active IDD1 Standby Supply Current — 1 — A Shutdown Mode, Serial Port Inactive (TA = TJ = 25°C) — 1 4 mA Note 1 INT/CMPTR Output IOL Sink Current: INT/CMPTR, SDA Outputs tTRIP INT/CMPTR Response Time 1 — 6 VOL Output Low Voltage — — 0.8 tCONV User Programmable V IOL = 4.0 mA — ±3 — C -55°C  TA  +125°C Temp-to-Bits Converter T Temperature Accuracy (Note 2) VDD = 3.3V: TCN75-3.3 MOA, TCN75-3.3 MUA VDD = 5.0V: TCN75-5.0 MOA, TCN75-5.0 MUA — ±0.5 ±3 C — 55 — msec 25°C  TA  100°C tCONV Conversion Time TSET(PU) TEMP Default Value — 80 — C Power-up THYST(PU) THYST Default Value — 75 — C Power-up 2-Wire Serial Bus Interface VIH Logic Input High VDD x 0.7 — — V VIL Logic Input Low — — VDD x 0.3 V VOL Logic Output Low — — 0.4 V CIN Input Capacitance SDA, SCL — 15 — pF ILEAK I/O Leakage — ±100 — pA IOL(SDA) SDA Output Low Current — — 6 mA  2001-2012 Microchip Technology Inc. IOL = 3 mA (TA = TJ = 25°C) DS21490D-page 3 TCN75 TCN75 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: 2.7V  VDD  5.5V; -55°C  (TA = TJ)  125°C, CL = 80 pF, unless otherwise noted. Symbol Parameter Min Typ Max Unit Test Conditions Serial Port Timing fSC Serial Port Frequency 0 100 400 kHz tLOW Low Clock Period 1250 — — nsec tHIGH High Clock Period 1250 — — nsec tR SCL and SDA Rise Time — — 250 nsec tF SCL and SDA Fall Time — — 250 nsec tSU(START) Start Condition Setup Time (for repeated Start Condition) 1250 — — nsec tSC SCL Clock Period 2.5 — — sec tH(START) Start Condition Hold Time 100 — — nsec tDSU Data in Setup Time to SCL High 100 — — nsec tDH Data in Hold Time after SCL Low 0 — — nsec tSU(STOP) Stop Condition Setup Time 100 — — nsec tIDLE Bus Free Time Prior to New Transition 1250 — — nsec Note 1: Output current should be minimized for best temperature accuracy. Power dissipation within the TCN75 will cause self-heating and temperature drift. At maximum rated output current and saturation voltage, 4 mA and 0.8V, respectively, the error amounts to 0.544°C for the SOIC. 2: All part types of the TCN75 will operate properly over the wider power supply range of 2.7V to 5.5V. Each part type is tested and specified for rated accuracy at its nominal supply voltage. As VDD varies from the nominal value, accuracy will degrade 1°C/V of VDD change. 3: Human body model, 100 pF discharged through a 1.5k resistor. TIMING DIAGRAM tSC SCL tH (Start) tSU (Stop) SDA Data In tDSU SDA Data Out tDH DS21490D-page 4  2001-2012 Microchip Technology Inc. TCN75 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Pin Number (8-Pin SOIC) 8-Pin MSOP) Symbol 1 SDA Bidirectional Serial Data. 2 SCL Serial Data Clock Input. 3 INT/CMPTR 4 GND 5 A2 Address Select Pin (MSB). 6 A1 Address Select Pin. 7 A0 Address Select Pin (LSB). 8 VDD  2001-2012 Microchip Technology Inc. Description Interrupt or Comparator Output. System Ground. Power Supply Input. DS21490D-page 5 TCN75 3.0 DETAILED DESCRIPTION A typical TCN75 hardware connection is shown in Figure 3-1. +VDD (3V to 5.5V) CBypass 0.1 µF Recommended Unless Device is Mounted Close to CPU 8 A0 Address (Set as Desired) A1 A2 7 6 5 I2C™ Interface SDA SCL 1 2 3 TCN75 To Controller INT/CMPTR 4 FIGURE 3-1: 3.1 Typical Application Serial Data (SDA) Bidirectional. Serial data is transferred in both directions using this pin. 3.4 Address (A2, A1, A0) Input. Clocks data into and out of the TCN75. Inputs. Sets the three Least Significant bits of the TCN75 8-bit address. A match between the TCN75’s address and the address specified in the serial bit stream must be made to initiate communication with the TCN75. Many protocol-compatible devices with other addresses may share the same 2-wire bus. 3.3 3.5 3.2 Serial Clock (SCL) INT/CMPTR Open Collector, Programmable Polarity. In Comparator mode, unconditionally driven active any time temperature exceeds the value programmed into the TSET register. INT/CMPTR will become inactive when temperature subsequently falls below the THYST setting. (See Section 5.0 “Register Set and Programmer’s ModeL”, Register Set and Programmer’s Model). In Interrupt mode, INT/CMPTR is also made active by TEMP exceeding TSET; it is unconditionally reset to its inactive state by reading any register via the 2-wire bus. If and when temperature falls below THYST, INT/CMPTR is again driven active. Reading any register will clear the THYST interrupt. In Interrupt mode, the INT/CMPTR output is unconditionally reset upon entering Shutdown mode. If programmed as an active-low output, it can be wire-ORed with any number of other open collector devices. Most systems will require a pull-up resistor for this configuration. Slave Address The four Most Significant bits of the Address Byte (A6, A5, A4, A3) are fixed to 1001[B]. The states of A2, A1 and A0 in the serial bit stream must match the states of the A2, A1 and A0 address inputs for the TCN75 to respond with an Acknowledge (indicating the TCN75 is on the bus and ready to accept data). The Slave Address is represented in Table 3-1. TABLE 3-1: 1 MSB 0 TCN75 SLAVE ADDRESS 0 1 A2 A1 A0 LSBS Note that current sourced from the pull-up resistor causes power dissipation and may cause internal heating of the TCN75. To avoid affecting the accuracy of ambient temperature readings, the pull-up resistor should be made as large as possible. INT/CMPTR’s output polarity may be programmed by writing to the INT/CMPTR POLARITY bit in the CONFIG register. The default is active low. DS21490D-page 6  2001-2012 Microchip Technology Inc. TCN75 3.6 Comparator/Interrupt Modes INT/CMPTR behaves differently depending on whether the TCN75 is in Comparator mode or Interrupt mode. Comparator mode is designed for simple thermostatic operation. INT/CMPTR will go active anytime TEMP exceeds TSET. When in Comparator mode, INT/ CMPTR will remain active until TEMP falls below THYST, whereupon it will reset to its inactive state. The state of INT/CMPTR is maintained in Shutdown mode when the TCN75 is in Comparator mode. In Interrupt mode, INT/CMPTR will remain active indefinitely, even if TEMP falls below THYST, until any register is read via the 2-wire bus. Interrupt mode is better suited to interrupt driven microprocessor-based systems. The INT/ CMPTR output may be wire-OR’ed with other interrupt sources in such systems. Note that a pull-up resistor is necessary on this pin since it is an open-drain output. Entering Shutdown mode will unconditionally reset INT/ CMPTR when in Interrupt mode.  2001-2012 Microchip Technology Inc. DS21490D-page 7 TCN75 4.0 SHUTDOWN MODE When the appropriate bit is set in the configuration register (CONFIG) the TCN75 enters its low-power Shutdown mode (IDD = 1 A, typical) and the temperatureto-digital conversion process is halted. The TCN75’s bus interface remains active and TEMP, TSET, and THYST may be read from and written to. Transitions on SDA or SCL due to external bus activity may increase the standby power consumption. If the TCN75 is in Interrupt mode, the state of INT/CMPTR will be reset upon entering Shutdown mode. 4.1 Term Serial Port Operation The Serial Clock input (SCL) and bidirectional data port (SDA) form a 2-wire bidirectional serial port for programming and interrogating the TCN75. The following table indicates TCN75 conventions that are used in this bus scheme. SERIAL BUS CONVENTIONS Explanation Transmitter Receiver The device sending data to the bus. The device receiving data from the bus. Master The device which controls the bus: initiating transfers (Start), generating the clock, and terminating transfers (Stop). Slave The device addressed by the master. Start A unique condition signaling the beginning of a transfer indicated by SDA falling (High – Low) while SCL is high. Stop A unique condition signaling the end of a transfer indicated by SDA rising (Low – High) while SCL is high. ACK A Receiver acknowledges the receipt of each byte with this unique condition. The Receiver drives SDA low during SCL high of the ACK clock-pulse. The Master provides the clock pulse for the ACK cycle. Fault Queue To lessen the probability of spurious activation of INT/ CMPTR the TCN75 may be programmed to filter out transient events. This is done by programming the desired value into the Fault Queue. Logic inside the TCN75 will prevent the device from triggering INT/ CMPTR unless the programmed number of sequential temperature-to-digital conversions yield the same qualitative result. In other words, the value reported in TEMP must remain above TSET or below THYST for the consecutive number of cycles programmed in the Fault Queue. Up to a six-cycle “filter” may be selected. See Section 5.0 “Register Set and Programmer’s ModeL”, Register Set and Programmer’s Model. 4.2 TABLE 4-1: NOT Busy When the bus is idle, both SDA & SCL will remain high. Data Valid The state of SDA must remain stable during the High period of SCL in order for a data bit to be considered valid. SDA only changes state while SCL is low during normal data transfers. (See Start and Stop conditions). All transfers take place under control of a host, usually a CPU or microcontroller, acting as the Master, which provides the clock signal for all transfers. The TCN75 always operates as a Slave. This serial protocol is illustrated in Figure 5-1. All data transfers have two phases; and all bytes are transferred MSB first. Accesses are initiated by a Start condition, followed by a device address byte and one or more data bytes. The device address byte includes a Read/Write selection bit. Each access must be terminated by a Stop condition. A convention called Acknowledge (ACK) confirms receipt of each byte. Note that SDA can change only during periods when SCL is LOW (SDA changes while SCL is HIGH are reserved for Start and Stop conditions). 4.3 Start Condition (Start) The TCN75 continuously monitors the SDA and SCL lines for a Start condition (a HIGH-to-LOW transition of SDA while SCL is HIGH), and will not respond until this condition is met. DS21490D-page 8  2001-2012 Microchip Technology Inc. TCN75 4.3.1 ADDRESS BYTE Immediately following the Start condition, the host must next transmit the address byte to the TCN75. The four Most Significant bits of the Address Byte (A6, A5, A4, A3) are fixed to 1001(B). The states of A2, A1 and A0 in the serial bit stream must match the states of the A2, A1 and A0 address inputs for the TCN75 to respond with an Acknowledge (indicating the TCN75 is on the bus and ready to accept data). The eighth bit in the Address Byte is a Read/Write Bit. This bit is a ‘1’ for a read operation or ‘0’ for a write operation. 4.3.2 ACKNOWLEDGE (ACK) Acknowledge (ACK) provides a positive handshake between the host and the TCN75. The host releases SDA after transmitting eight bits then generates a ninth clock cycle to allow the TCN75 to pull the SDA line LOW to acknowledge that it successfully received the previous eight bits of data or address. 4.3.3 4.3.4 STOP CONDITION (STOP) Communications must be terminated by a Stop condition (a LOW-to-HIGH transition of SDA while SCL is HIGH). The Stop condition must be communicated by the transmitter to the TCN75. 4.3.5 POWER SUPPLY To minimize temperature measurement error, the TCN75-3.3 MOA and TCN75-3.3 MUA are factory calibrated at a supply voltage of 3.3V ±5% and the TCN75-5.0 MOA and TCN75-5.0 MUA are factory calibrated at a supply voltage of 5V ±5%. Either device is fully operational over the power supply voltage range of 2.7V to 5.5V, but with a lower measurement accuracy. The typical value of this power supply-related error is ±2°C. DATA BYTE After a successful ACK of the address byte, the host must next transmit the data byte to be written or clock out the data to be read. (See the appropriate timing diagrams.) ACK will be generated after a successful write of a data byte into the TCN75.  2001-2012 Microchip Technology Inc. DS21490D-page 9 TCN75 5.0 REGISTER SET AND PROGRAMMER’S MODEL TABLE 5-1: D[7] D[6] D3 – D4: Fault Queue: Number of sequential temperature-to-digital conversions with the same result before the INT/CMPTR output is updated: REGISTER (POINT), 8 BITS, WRITE ONLY D[5] D[4] D[3] D[2] D[1] Must Be Set To Zero D[0] Pointer Register Selection Via the Pointer Register D1 D0 0 0 TEMP 0 1 CONFIG 1 0 THYST 1 1 TSET D [6] D3 Number of Conversions 0 0 1 (Power-up default) 0 1 2 1 0 4 1 1 6 Register Selection TABLE 5-2: D [7] D4 CONFIGURATION REGISTER (CONFIG), 8 BITS, READ/ WRITE D [5] D [4] Must Be Set To Zero D [3] Fault Queue D [2] D [1] INT/ COM CMPTR, P/INT Polarity D [0] Shutdown D0: Shutdown: 0 = Normal Operation 1 = Shutdown Mode D1: CMPTR/INT: 0 = Comparator Mode 1 = Interrupt Mode D2: INT/CMPTR POLARITY: 0 = Active Low 1 = Active High DS21490D-page 10  2001-2012 Microchip Technology Inc. TCN75 TABLE 5-3: TEMPERATURE (TEMP) REGISTER, 16 BITS, READ ONLY The binary value in this register represents ambient temperature following a conversion cycle. D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] MSB D7 D6 D5 D4 D3 D2 D1 LSB X X X X TABLE 5-4: X X D[0] X TEMPERATURE SET POINT (TSET) REGISTER, 16 BITS, READ/WRITE D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] MSB D7 D6 D5 D4 D3 D2 D1 LSB X X X X TABLE 5-5: D[2] D[1] D[2] D[1] X X D[0] X HYSTERESIS (THYST) REGISTER, 16 BITS, READ/WRITE D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] MSB D7 D6 D5 D4 D3 D2 D1 LSB X X X X D[2] D[1] X X D[0] X In the TEMP, TSET, and THYST registers, each unit value represents one-half degree (Celsius). The value is in 2’s – complement binary format such that a reading of 000000000b corresponds to 0°C. Examples of this temperature to binary value relationship are shown in Table 5-6. TABLE 5-6: TEMPERATURE TO DIGITAL VALUE CONVERSION Temperature Binary Value HEX Value +125°C 0 11111010 0FA +25°C 0 00110010 032 +0.5°C 0 00000001 001 0°C 0 00000000 00 0.5°C 1 11111111 1FF -25°C 1 11001110 1CE -40°C 1 10110000 1B0 -55°C 1 10010010 192 TABLE 5-7: TCN75’S REGISTER SET SUMMARY Name Description Width Read Write TEMP Ambient Temperature 16 X TSET Temperature Setpoint 16 X X 2’s Complement Format 2’s Complement Format 2’s Complement Format THYST Temperature Hysteresis 16 X X POINT Register Pointer 8 X X CONFIG Configuration Register 8 X X  2001-2012 Microchip Technology Inc. Notes DS21490D-page 11 TCN75 9 1 1 0 Start by Master 0 1 D7 D6 D5 D4 D3 D2 D1 D0 1 A2 A1 A0 R/W Ack by Address Byte 9 Most Significant Data Byte TCN75 1 9 D7 D6 D5 D4 D3 D2 D1 D0 Ack Least Significant Data Byte by Master Stop No Ack Cond by by Master Master (a) Typical 2-Byte Read From Preset Pointer Location Such as Temp, TOS, THYST 9 1 1 9 ..... 1 0 Start by Master 0 1 A2 A1 A0 R/W 0 0 Ack by Address Byte 0 0 0 TCN75 9 1 1 Repeat Start by Master 0 0 Ack by Pointer Byte TCN75 1 A2 A1 A0 R/W 1 9 D7 D6 D5 D4 D3 D2 D1 D0 Ack by Address Byte ..... 0 D1 D0 Most Significant Data Byte TCN75 1 9 D7 D6 D5 D4 D3 D2 D1 D0 Ack Least Significant Data Byte by Master Stop No Ack Cond by by Master Master (b) Typical Pointer Set Followed by Immediate Read for 2-Byte Register Such as Temp, TOS, THYST 1 1 9 0 Start by Master 0 1 A2 A1 A0 R/W Address Byte 1 9 D7 D6 D5 D4 D3 D2 D1 D0 Ack by Data Byte TCN75T Stop No Ack Cond by by Master Master (c) Typical 1-Byte Read From Configuration Register with Preset Pointer FIGURE 5-1: DS21490D-page 12 Timing Diagrams  2001-2012 Microchip Technology Inc.  2001-2012 Microchip Technology Inc. 0 0 1 A2 A1 A0 R/W Ack by 9 0 1 0 0 0 0 0 0 D0 9 1 1 1 0 1 0 0 1 Ack by 9 0 1 TCN75 1 A2 A1 A0 R/W Address Byte 0 (f) TOS and THYST Write Start by Master 1 Ack by 9 TCN75T 1 A2 A1 A0 R/W Address Byte 0 (e) Configuration Register Write Start by Master 1 0 0 0 0 0 0 Pointer Byte 0 Pointer Byte 0 Ack by 0 1 1 0 1 Configuration Byte Most Significant Data Byte Ack by 9 Stop Cond by Master Least Significant Data Byte Ack by 9 Stop Cond by Master Stop No Ack Cond by by Master Master 9 TCN75 D7 D6 D5 D4 D3 D2 D1 D0 1 TCN75 Ack by 9 TCN75 Ack by 9 Data Byte D7 D6 D5 D4 D3 D2 D1 D0 1 TCN75 A2 A1 A0 R/W Address Byte 0 0 D4 D3 D2 D1 D0 0 D7 D6 D5 D4 D3 D2 D1 D0 TCN75 Ack by 0 D1 D0 9 TCN75 0 D1 D0 9 Ack Repeat Address Byte Pointer Byte by Start TCN75 TCN75 by Master (d) Typical Pointer Set Followed by Immediate Read from Configuration Register Start by Master 1 1 TCN75 Timing Diagrams (Continued) DS21490D-page 13 TCN75 6.0 PACKAGING INFORMATION 6.1 Package Marking Information Package marking data not available at this time. 6.2 Taping Form Component Taping Orientation for 8-Pin MSOP Devices User Direction of Feed Pin 1 W P Standard Reel Component Orientation for 713 Suffix Device Carrier Tape, Number of Components Per Reel and Reel Size Package 8-Pin MSOP Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 12 mm 8 mm 2500 13 in Component Taping Orientation for 8-Pin SOIC (Narrow) Devices User Direction of Feed Pin1 W P Standard Reel Component Orientation for 713 Suffix Device Carrier Tape, Number of Components Per Reel and Reel Size Package 8-Pin SOIC (N) DS21490D-page 14 Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 12 mm 8 mm 2500 13 in  2001-2012 Microchip Technology Inc. TCN75 6.3 Package Dimensions Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 8-Pin MSOP Pin 1 .122 (3.10) .197 (5.00) .114 (2.90) .189 (4.80) .026 (0.65) Typ. .122 (3.10) .114 (2.90) .043 (1.10) Max. .016 (0.40) .010 (0.25) .002 (0.05) .008 (0.20) .005 (0.13) 6° Max. .006 (0.15) .028 (0.70) .016 (0.40) Dimensions: inches (mm) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 8-Pin SOIC Pin 1 .157 (3.99) .150 (3.81) .244 (6.20) .228 (5.79) .050 (1.27) Typ. .197 (5.00) .189 (4.80) .069 (1.75) .053 (1.35) .020 (0.51) .010 (0.25) .013 (0.33) .004 (0.10) .010 (0.25) .007 (0.18) 8° Max. .050 (1.27) .016 (0.40) Dimensions: inches (mm)  2001-2012 Microchip Technology Inc. DS21490D-page 15 TCN75 7.0 REVISION HISTORY Revision D (December 2012) Added a note to each package outline drawing. DS21490D-page 16  2001-2012 Microchip Technology Inc. TCN75 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. 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What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21490D-page 18  2001-2012 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. 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Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MTP, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. Analog-for-the-Digital Age, Application Maestro, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O, Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA and Z-Scale are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. GestIC and ULPP are registered trademarks of Microchip Technology Germany II GmbH & Co. & KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2001-2012, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 9781620768815 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==  2001-2012 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS21490D-page 19 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Osaka Tel: 81-6-6152-7160 Fax: 81-6-6152-9310 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8569-7000 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 China - Hangzhou Tel: 86-571-2819-3187 Fax: 86-571-2819-3189 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Hong Kong SAR Tel: 852-2943-5100 Fax: 852-2401-3431 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Taiwan - Hsin Chu Tel: 886-3-5778-366 Fax: 886-3-5770-955 China - Shenzhen Tel: 86-755-8864-2200 Fax: 86-755-8203-1760 Taiwan - Kaohsiung Tel: 886-7-213-7828 Fax: 886-7-330-9305 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Taipei Tel: 886-2-2508-8600 Fax: 886-2-2508-0102 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 DS21490D-page 20 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Japan - Tokyo Tel: 81-3-6880- 3770 Fax: 81-3-6880-3771 11/29/12  2001-2012 Microchip Technology Inc.