TN5325
N-Channel Enhancement-Mode Vertical DMOS FET
Features
General Description
•
•
•
•
The TN5325 is a low-threshold, Enhancement-mode
(normally-off) transistor that utilizes a vertical DMOS
structure and a well-proven silicon gate manufacturing
process. This combination produces a device with the
power handling capabilities of bipolar transistors and
the high input impedance and positive temperature
coefficient inherent in MOS devices. Characteristic of
all MOS structures, this device is free from thermal
runaway and thermally induced secondary breakdown.
Low Threshold (2V Maximum)
High Input Impedance and High Gain
Free from Secondary Breakdown
Low CISS and Fast Switching Speeds
Applications
•
•
•
•
•
•
•
Logic-level Interfaces (Ideal for TTL and CMOS)
Solid State Relays
Battery-operated Systems
Photo-voltaic Drives
Analog Switches
General Purpose Line Drivers
Telecommunication Switches
Microchip’s vertical DMOS FETs are ideally suited to a
wide range of switching and amplifying applications
where very low threshold voltage, high breakdown
voltage, high input impedance, low input capacitance
and fast switching speeds are desired.
Package Types
3-lead SOT-23 (TO-236AB)
(Top view)
3-lead TO-92
(Top view)
3-lead SOT-89 (243AA)
(Top view)
DRAIN
DRAIN
SOURCE
GATE
DRAIN
SOURCE
SOURCE
DRAIN
GATE
GATE
See Table 2-1, Table 2-2 and Table 2-3 for pin information.
2017 Microchip Technology Inc.
DS20005709A-page 1
TN5325
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
Drain-to-source Voltage ....................................................................................................................................... BVDSX
Drain-to-gate Voltage .......................................................................................................................................... BVDGX
Gate-to-source Voltage ......................................................................................................................................... ±20V
Operating Ambient Temperature, TA ................................................................................................... –55°C to +150°C
Storage Temperature, TS ..................................................................................................................... –55°C to +150°C
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS 1
Electrical Specifications: Unless otherwise specified, for all specifications TA = TJ = +25°C.
Parameter
Sym.
Min. Typ. Max.
Drain-to-source Breakdown Voltage
BVDSS
250
—
—
V
VGS = 0V, ID = 100 µA
Gate Threshold Voltage
VGS(th)
0.6
—
2
V
VGS = VDS, ID = 1 mA
∆VGS(th)
—
—
–4.5
IGSS
—
—
100
—
—
1
—
—
10
—
—
1
0.6
—
—
1.2
—
—
Change in VGS(th) with Temperature
Gate Body Leakage
Zero-gate Voltage Drain Current
On-state Drain Current
IDSS
ID(ON)
Static Drain-to-source On-state
Resistance
RDS(ON)
Change in RDS(ON) with Temperature
∆RDS(ON)
Note 1:
2:
—
—
8
—
—
7
—
—
1
Unit
Conditions
mV/°C VGS = VDS, ID = 1 mA (Note 2)
nA
µA
mA
A
Ω
%/°C
VGS = ± 20V, VDS = 0V
VGS = 0V, VDS = 100V
VGS = 0V, VDS = Maximum Rating
VDS = 0.8 Maximum Rating,
VGS = 0V, TA = 125°C (Note 2)
VGS = 4.5V, VDS = 25V
VGS = 10V, VDS = 25V
VGS = 4.5V, ID = 150 mA
VGS = 10V, ID = 1A
VGS = 4.5V, ID = 150 mA (Note 2)
All DC parameters are 100% tested at 25°C unless otherwise stated. Pulse test: 300 µs pulse, 2% duty
cycle.
Specification is obtained by characterization and is not 100% tested.
DS20005709A-page 2
2017 Microchip Technology Inc.
TN5325
AC ELECTRICAL CHARACTERISTICS 2
Electrical Specifications: Unless otherwise specified, for all specifications TA = TJ = +25°C.
Parameter
Forward Transconductance
Sym.
Min. Typ. Max.
GFS
150
—
—
Input Capacitance
CISS
—
—
110
Common Source Output Capacitance
COSS
—
—
60
Reverse Transfer Capacitance
CRSS
—
—
23
Turn-on Delay Time
td(ON)
—
—
20
tr
—
—
15
td(OFF)
—
—
25
tf
—
—
25
VSD
—
—
trr
—
300
Rise Time
Turn-off Delay Time
Fall Time
Unit
Conditions
mmho VDS = 25V, ID = 200 mA
pF
VGS = 0V,
VDS = 25V,
f = 1 MHz
ns
VDD = 25V,
ID = 150 mA,
RGEN = 25Ω
1.8
V
VGS = 0V, ISD = 200 mA (Note 1)
—
ns
VGS = 0V, ISD = 200 mA (Note 2)
DIODE PARAMETER
Diode Forward Voltage Drop
Reverse Recovery Time
Note 1:
2:
All DC parameters are 100% tested at 25°C unless otherwise stated. Pulse test: 300 µs pulse, 2% duty
cycle.
Specification is obtained by characterization and is not 100% tested.
TEMPERATURE SPECIFICATIONS
Parameter
Sym.
Min. Typ. Max.
Unit
Conditions
TEMPERATURE RANGE
Operating Ambient Temperature
TA
–55
—
+150
°C
Storage Temperature
TS
–55
—
+150
°C
JA
—
350
—
°C/W
JC
—
200
—
°C/W
JA
—
170
—
°C/W
JC
—
125
—
°C/W
JA
—
78
—
°C/W
JC
—
15
—
°C/W
PACKAGE THERMAL RESISTANCE
3-lead SOT-23
3-lead TO-92
3-lead SOT-89
Note 1:
Note 1
Mounted on FR5 25 mm x 25 mm x 1.57 mm
THERMAL CHARACTERISTICS
ID ( 1)
(Continuous)
(mA)
ID
(Pulsed)
(A)
Power Dissipation at
TA = 25°C
(W)
IDR ( 1)
(mA)
IDRM
(A)
3-lead SOT-23
150
0.4
0.36
150
0.4
3-lead TO-92
215
0.8
0.74
215
0.8
3-lead SOT-89
316
1.5
1.6 ( 2)
316
1.5
Package
Note 1:
2:
ID (continuous) is limited by maximum TJ.
Mounted on FR5 board, 25 mm x 25 mm x 1.57 mm
2017 Microchip Technology Inc.
DS20005709A-page 3
TN5325
2.0
PIN DESCRIPTION
Table 2-1, Table 2-2 and Table 2-3 show the
description of pins in TN5325 3-lead SOT-23, 3-lead
TO-92 and 3-lead SOT-89, respectively. Refer to
Package Types for the location of pins.
TABLE 2-1:
SOT-23 PIN FUNCTION TABLE
Pin Number
Pin Name
1
Gate
2
Source
3
Drain
TABLE 2-2:
Description
Gate
Source
Drain
TO-92 PIN FUNCTION TABLE
Pin Number
Pin Name
Description
1
Source
2
Gate
Gate
3
Drain
Drain
TABLE 2-3:
Source
SOT-89 PIN FUNCTION TABLE
Pin Number
Pin Name
Description
1
Gate
Gate
2
Drain
Drain
3
Source
4
Drain
DS20005709A-page 4
Source
Drain
2017 Microchip Technology Inc.
TN5325
3.0
FUNCTIONAL DESCRIPTION
Figure 3-1 illustrates the switching waveforms and test
circuit for TN5325.
10V
VDD
90%
Pulse
Generator
INPUT
0V
10%
t(ON)
td(ON)
VDD
OUTPUT
td(OFF)
tr
RGEN
INPUT
10%
90%
OUTPUT
tf
10%
0V
FIGURE 3-1:
t(OFF)
RL
D.U.T.
90%
Switching Waveforms and Test Circuit.
PRODUCT SUMMARY
BVDSS/BVDGS
(V)
RDS(ON)
(Maximum)
(Ω)
ID(ON)
(Minimum)
(A)
VGS(th)
(Maximum)
(V)
250V
7
1.2
2
2017 Microchip Technology Inc.
DS20005709A-page 5
TN5325
4.0
PACKAGING INFORMATION
4.1
Package Marking Information
3-lead SOT-23
XXXNNN
N3C232
3-lead TO-92
Example
XXXXXX
XXXX e3
YWWNNN
TN5325
N3 e3
725698
3-lead SOT-89
Example
XXXXYWW
NNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS20005709A-page 6
Example
TN3C714
478
Product Code or Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
2017 Microchip Technology Inc.
TN5325
3-Lead TO-236AB (SOT-23) Package Outline (K1/T)
2.90x1.30mm body, 1.12mm height (max), 1.90mm pitch
D
3
E1 E
Gauge
Plane
0.25
1
Seating
Plane
L
2
e
L1
b
e1
View B
Top View
View B
A
A
A2
Seating
Plane
A1
Side View
View A - A
A
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
Symbol
Dimension
(mm)
A
A1
A2
b
D
E
E1
MIN
0.89
0.01
0.88
0.30
2.80
2.10
1.20
NOM
-
-
0.95
-
2.90
-
1.30
MAX
1.12
0.10
1.02
0.50
3.04
2.64
1.40
e
0.95
BSC
e1
1.90
BSC
L
0.20†
0.50
0.60
L1
0.54
REF
ș
0O
8O
JEDEC Registration TO-236, Variation AB, Issue H, Jan. 1999.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
2017 Microchip Technology Inc.
DS20005709A-page 7
TN5325
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
DS20005709A-page 8
2017 Microchip Technology Inc.
TN5325
3-Lead TO-243AA (SOT-89) Package Outline (N8)
D
D1
C
E H
L
1
2
E1
3
b
b1
e
A
e1
Side View
Top View
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
Symbol
Dimensions
(mm)
A
b
b1
C
D
D1
E
E1
MIN
1.40
0.44
0.36
0.35
4.40
1.62
2.29
2.00†
NOM
-
-
-
-
-
-
-
-
MAX
1.60
0.56
0.48
0.44
4.60
1.83
2.60
2.29
e
1.50
BSC
e1
3.00
BSC
H
L
3.94
0.73†
-
-
4.25
1.20
JEDEC Registration TO-243, Variation AA, Issue C, July 1986.
† This dimension differs from the JEDEC drawing
Drawings not to scale.
2017 Microchip Technology Inc.
DS20005709A-page 9
TN5325
NOTES:
DS20005709A-page 10
2017 Microchip Technology Inc.
TN5325
APPENDIX A:
REVISION HISTORY
Revision A (April 2017)
• Converted Supertex Doc# DSFP-TN5325 to
Microchip DS20005709A
• Changed the part marking format
• Removed the N3 P003, N3 P005, N3 P013 and
N3 P014 media types
• Made minor text changes throughout the document
2017 Microchip Technology Inc.
DS20005709A-page 11
TN5325
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
XX
PART NO.
Package
Options
Device
Device:
Packages:
-
TN5325
=
X
-
Environmental
X
Media Type
N-Channel Enhancement-Mode Vertical
DMOS FET
K1
=
3-lead SOT-23
N3
=
3-lead TO-92
N8
=
3-lead SOT-89
Environmental:
G
=
Lead (Pb)-free/RoHS-compliant Package
Media Types:
(blank)
P002
DS20005709A-page 12
=
3000/Reel for a K1 Package
=
1000/Bag for an N3 Package
=
2000/Reel for an N8 Package
=
2000/Reel for an N3 Package
Examples:
a) TN5325K1-G:
N-Channel EnhancementMode Vertical DMOS FET,
3-lead SOT-23, 3000/Reel
b) TN5325N3-G:
N-Channel EnhancementMode Ver-tical DMOS FET,
3-lead TO-92, 1000/Bag
c) TN5325N3-G-P002:
N-Channel EnhancementMode Vertical DMOS FET,
3-lead TO-92, 2000/Reel
d) TN5325N8-G:
N-Channel EnhancementMode Vertical DMOS FET,
3-lead SOT-89, 2000/Reel
2017 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
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are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
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CERTIFIED BY DNV
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© 2017, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-1556-5
== ISO/TS 16949 ==
2017 Microchip Technology Inc.
DS20005709A-page 13
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DS20005709A-page 14
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2017 Microchip Technology Inc.
11/07/16