TS87C51RD2-VIL

TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 High Performance 8-bit Microcontrollers 1. Description Atmel Wireless & Microcontrollers TS80C51Rx2 is high performance CMOS ROM, OTP, EPROM and ROMless versions of the 80C51 CMOS single chip 8-bit microcontroller. The fully static design of the TS80C51Rx2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The TS80C51Rx2 retains all features of the 80C51 with extended ROM/EPROM capacity (16/32/64 Kbytes), 256 bytes of internal RAM, a 7-source , 4-level interrupt system, an on-chip oscilator and three timer/counters. The TS80C51Rx2 has 2 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the timers, the serial port and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. In addition, the TS80C51Rx2 has a Programmable Counter Array, an XRAM of 256 or 768 bytes, a Hardware Watchdog Timer, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a X2 speed improvement mechanism. 2. Features • 80C52 Compatible • • 8051 pin and instruction compatible • Four 8-bit I/O ports • Three 16-bit timer/counters • 256 bytes scratchpad RAM High-Speed Architecture • 40 MHz @ 5V, 30MHz @ 3V • X2 Speed Improvement capability (6 clocks/ machine cycle) 30 MHz @ 5V, 20 MHz @ 3V (Equivalent to 60 MHz @ 5V, 40 MHz @ 3V) Dual Data Pointer • • On-chip ROM/EPROM (16K-bytes, 32K-bytes, 64Kbytes) • On-chip eXpanded RAM (XRAM) (256 or 768 bytes) • Programmable Clock Out and Up/Down Timer/ Counter 2 • Programmable Counter Array with • • • • High Speed Output, Compare / Capture, Pulse Width Modulator, Watchdog Timer Capabilities Rev. C - 06 March, 2001 • Hardware Watchdog Timer (One-time enabled with Reset-Out) • 2 extra 8-bit I/O ports available on RD2 with high pin count packages • Asynchronous port reset • Interrupt Structure with • • 7 Interrupt sources, • 4 level priority interrupt system Full duplex Enhanced UART • Framing error detection • Automatic address recognition Low EMI (inhibit ALE) • • Power Control modes • Idle mode • Power-down mode • Power-off Flag Once mode (On-chip Emulation) • • Power supply: 4.5-5V, 2.7-5.5V • Temperature ranges: Commercial (0 to 70oC) and Industrial (-40 to 85oC) • Packages: PDIL40, PLCC44, VQFP44 1.4, CQPJ44 (window), CDIL40 (window), PLCC68, VQFP64 1.4, JLCC68 (window) 1 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 PDIL40 ROM (bytes) EPROM (bytes) XRAM (bytes) TOTAL RAM (bytes) I/O TS80C51RA2 TS80C51RD2 0 0 0 0 256 768 512 1024 32 32 TS83C51RB2 TS83C51RC2 TS83C51RD2 16k 32k 64k 0 0 0 256 256 768 512 512 1024 32 32 32 TS87C51RB2 TS87C51RC2 TS87C51RD2 0 0 0 16k 32k 64k 256 256 768 512 512 1024 32 32 32 ROM (bytes) EPROM (bytes) XRAM (bytes) TOTAL RAM (bytes) I/O TS80C51RD2 0 0 768 1024 48 TS83C51RD2 64k 0 768 1024 48 TS87C51RD2 0 64k 768 1024 48 PLCC44 VQFP44 1.4 PLCC68 VQFP64 1.4 (3) (3) (1) XTAL1 EUART XTAL2 ALE/ PROG RAM 256x8 C51 CORE PSEN ROM /EPROM 0/16/32/64Kx8 XRAM 256/768x8 (1) (1) PCA T2 T2EX PCA ECI Vss Vcc TxD RxD 3. Block Diagram (1) Timer2 IB-bus CPU EA/VPP Parallel I/O Ports & Ext. Bus Watch Dog P5 P4 P3 P2 P1 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 (2) (2) P0 (3) (3) INT1 (3) (3) T1 (3) INT Ctrl INT0 Timer 0 Timer 1 RESET WR (3) T0 RD (1): Alternate function of Port 1 (2): Only available on high pin count packages (3): Alternate function of Port 3 2 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 4. SFR Mapping The Special Function Registers (SFRs) of the TS80C51Rx2 fall into the following categories: • • • • • • • • • C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 I/O port registers: P0, P1, P2, P3, P4, P5 Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H Serial I/O port registers: SADDR, SADEN, SBUF, SCON Power and clock control registers: PCON HDW Watchdog Timer Reset: WDTRST, WDTPRG PCA registers: CL, CH, CCAPiL, CCAPiH, CCON, CMOD, CCAPMi Interrupt system registers: IE, IP, IPH Others: AUXR, CKCON Table 1. All SFRs with their address and their reset value Bit addressable 0/8 F8h Non Bit addressable 1/9 2/A 3/B 4/C 5/D 6/E CH 0000 0000 CCAP0H XXXX XXXX CCAP1H XXXX XXXX CCAPL2H XXXX XXXX CCAPL3H XXXX XXXX CCAPL4H XXXX XXXX F0h B 0000 0000 E8h P5 bit addressable 1111 1111 E0h ACC 0000 0000 D8h CCON 00X0 0000 D0h PSW 0000 0000 C8h T2CON 0000 0000 C0h P4 bit addressable 1111 1111 B8h IP X000 000 B0h P3 1111 1111 A8h IE 0000 0000 A0h P2 1111 1111 98h SCON 0000 0000 90h P1 1111 1111 88h TCON 0000 0000 TMOD 0000 0000 TL0 0000 0000 TL1 0000 0000 80h P0 1111 1111 SP 0000 0111 DPL 0000 0000 DPH 0000 0000 0/8 1/9 2/A 3/B 7/F FFh F7h CL 0000 0000 CCAP0L XXXX XXXX CCAP1L XXXX XXXX CCAPL2L XXXX XXXX CCAPL3L XXXX XXXX EFh CCAPL4L XXXX XXXX E7h CMOD 00XX X000 CCAPM0 X000 0000 CCAPM1 X000 0000 CCAPM2 X000 0000 CCAPM3 X000 0000 T2MOD XXXX XX00 RCAP2L 0000 0000 RCAP2H 0000 0000 TL2 0000 0000 TH2 0000 0000 CCAPM4 X000 0000 DFh D7h CFh P5 byte addressable 1111 1111 SADEN 0000 0000 C7h BFh IPH X000 0000 SADDR 0000 0000 B7h AFh AUXR1 XXXX0XX0 WDTRST XXXX XXXX WDTPRG XXXX X000 SBUF XXXX XXXX A7h 9Fh 97h TH0 0000 0000 4/C TH1 0000 0000 5/D AUXR XXXXXX00 6/E CKCON XXXX XXX0 8Fh PCON 00X1 0000 87h 7/F reserved Rev. C - 06 March, 2001 3 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 5. Pin Configuration P0.0 / A0 P1.2 3 4 P1.0/T2 VSS1/NIC* P1.7 6 7 8 P1.1/T2EX P1.6 P0.3 / A3 P0.4 / A4 36 35 34 33 5 P1.2 P1.5 P1.3 P1.4 P0.1 / A1 P0.2 / A2 37 P1.4 P1.3 6 5 4 3 2 1 44 43 42 41 40 P0.2/AD2 P0.3/AD3 VCC 39 38 P0.1/AD1 40 2 P0.0/AD0 1 VCC P1.0 / T2 P1.1 / T2EX P0.5 / A5 P0.6 / A6 P1.5 39 38 P0.4/AD4 P1.6 7 8 P1.7 9 37 P0.6/AD6 9 32 P0.7 / A7 P3.0/RxD 10 P3.1/TxD 11 12 13 31 30 EA/VPP ALE/PROG PSEN P2.7 / A15 P2.6 / A14 P2.5 / A13 RST 10 36 P0.7/AD7 P3.0/RxD 35 34 33 EA/VPP P3.1/TxD 11 12 13 P2.4 / A12 P2.3 / A11 P3.2/INT0 P3.3/INT1 14 15 32 31 PSEN P2.2 / A10 P3.4/T0 P3.5/T1 16 30 P2.6/A14 17 29 P2.5/A13 23 22 21 P2.1 / A9 ALE/PROG P2.7/A15 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC VSS1/NIC* P1.0/T2 P1.1/T2EX P1.2 P1.3 NIC* 18 19 20 21 22 23 24 25 26 27 28 P2.0 / A8 P1.4 P0.5/AD5 P2.3/A11 P2.4/A12 24 P2.2/A10 17 18 19 20 P3.6/WR VSS 25 P2.1/A9 XTAL1 16 PLCC/CQPJ 44 NIC* P2.0/A8 P3.7/RD XTAL2 26 NIC* VSS P3.5/T1 P3.6/WR 14 15 XTAL1 P3.4/T0 CDIL40 29 28 27 XTAL2 P3.2/INT0 P3.3/INT1 PDIL/ P3.7/RD RST 44 43 42 41 40 39 38 37 36 35 34 P1.5 1 P1.6 2 P1.7 RST 3 4 P3.0/RxD 5 NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 33 32 P0.4/AD4 31 P0.6/AD6 30 P0.7/AD7 29 28 27 EA/VPP PSEN 9 26 25 10 24 P2.6/A14 11 23 P2.5/A13 VQFP44 1.4 6 7 8 P0.5/AD5 NIC* ALE/PROG P2.7/A15 P2.3/A11 P2.4/A12 P2.2/A10 P2.1/A9 NIC* P2.0/A8 VSS XTAL1 XTAL2 P3.7/RD P3.6/WR 12 13 14 15 16 17 18 19 20 21 22 *NIC: No Internal Connection 4 Rev. C - 06 March, 2001 ALE/PROG PSEN NIC P2.7/A15 P2.6/A14 P5.2 P5.1 P2.5/A13 P0.4/AD4 P5.4 P5.3 P0.5/AD5 P0.6/AD6 NIC P0.7/AD7 EA/VPP NIC TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 PLCC 68 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 P5.0 P2.4/A12 P2.3/A11 P4.7 P2.2/A10 P2.1/A9 P2.0/A8 P4.6 NIC VSS P4.5 XTAL1 XTAL2 P3.7/RD P4.4 P3.6/WR P4.3 P0.4/AD4 P5.4 P5.3 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP NIC ALE/PROG PSEN P2.7/A15 P2.6/A14 P5.2 P5.1 P2.5/A13 P5.0 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 P1.5 P1.6 P1.7 RST NIC NIC NIC P3.0/RxD NIC NIC NIC NIC P3.1/TxD P5.5 P0.3/AD3 P0.2/AD2 P5.6 P0.1/AD1 P0.0/AD0 P5.7 VCC NIC P1.0/T2 P4.0 P1.1/T2EX P1.2 P1.3 P4.1 P1.4 P4.2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VQFP64 1.4 P2.4/A12 P2.3/A11 P4.7 P2.2/A10 P2.1/A9 P2.0/A8 P4.6 NIC VSS P4.5 XTAL1 XTAL2 P3.7/RD P4.4 P3.6/WR P4.3 P4.2 P1.5 P1.6 P1.7 RST NIC NIC NIC P3.0/RxD NIC NIC P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P5.5 P0.3/AD3 P0.2/AD2 P5.6 P0.1/AD1 P0.0/AD0 P5.7 VCC VSS P1.0/T2 P4.0 P1.1/T2EX P1.2 P1.3 P4.1 P1.4 NIC: No InternalConnection Rev. C - 06 March, 2001 5 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Pin Number Mnemonic Type Name And Function DIL LCC VQFP 1.4 20 22 16 I Ground: 0V reference 1 39 I Optional Ground: Contact the Sales Office for ground connection. 40 44 38 I Power Supply: This is the power supply voltage for normal, idle and powerdown operation P0.0-P0.7 39-32 43-36 37-30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. Port 0 pins must be polarized to Vcc or Vss in order to prevent any parasitic current consumption. Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. In this application, it uses strong internal pull-up when emitting 1s. Port 0 also inputs the code bytes during EPROM programming. External pull-ups are required during program verification during which P0 outputs the code bytes. P1.0-P1.7 1-8 2-9 40-44 1-3 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. Port 1 also receives the low-order address byte during memory programming and verification. Alternate functions for Port 1 include: 1 2 40 I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout VSS Vss1 VCC 2 3 41 I T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control 3 4 42 I ECI (P1.2): External Clock for the PCA 4 5 43 I/O CEX0 (P1.3): Capture/Compare External I/O for PCA module 0 5 6 44 I/O CEX1 (P1.4): Capture/Compare External I/O for PCA module 1 6 7 45 I/O CEX0 (P1.5): Capture/Compare External I/O for PCA module 2 7 8 46 I/O CEX0 (P1.6): Capture/Compare External I/O for PCA module 3 8 9 47 I/O CEX0 (P1.7): Capture/Compare External I/O for PCA module 4 P2.0-P2.7 21-28 24-31 18-25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR).In this application, it uses strong internal pull-ups emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. Some Port 2 pins (P2.0 to P2.5) receive the high order address bits during EPROM programming and verification: P3.0-P3.7 10-17 11, 13-19 5, 7-13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pull-ups. Some Port 3 pins (P3.4 to P3.5) receive the high order address bits during EPROM programming and verification. Port 3 also serves the special features of the 80C51 family, as listed below. 10 11 5 I RXD (P3.0): Serial input port 6 11 13 7 O TXD (P3.1): Serial output port 12 14 8 I INT0 (P3.2): External interrupt 0 13 15 9 I INT1 (P3.3): External interrupt 1 14 16 10 I T0 (P3.4): Timer 0 external input 15 17 11 I T1 (P3.5): Timer 1 external input 16 18 12 O WR (P3.6): External data memory write strobe 17 19 13 O RD (P3.7): External data memory read strobe Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Reset 9 10 Rev. C - 06 March, 2001 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. If the hardware watchdog reaches its time-out, the reset pin becomes an output during the time the internal reset is activated. 7 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Pin Number Mnemonic Type Name And Function ALE/PROG 30 33 27 O (I) Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during EPROM programming. ALE can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during internal fetches. PSEN 29 32 26 O Program Store ENable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EA/VPP 31 35 29 I External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H and 3FFFH (RB) or 7FFFH (RC), or FFFFH (RD). If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 3FFFH (RB) or 7FFFH (RC) EA must be held low for ROMless devices. This pin also receives the 12.75V programming supply voltage (VPP) during EPROM programming. If security level 1 is programmed, EA will be internally latched on Reset. XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier 8 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 5.1. Pin Description for 64/68 pin Packages Port 4 and Port 5 are 8-bit bidirectional I/O ports with internal pull-ups. Pins that have 1 written to them are pulled high by the internal pull ups and can be used as inputs. As inputs, pins that are externally pulled low will source current because of the internal pull-ups. Refer to the previous pin description for other pins. Table 2. 64/68 Pin Packages Configuration VSS VCC P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 Rev. C - 06 March, 2001 PLCC68 SQUARE VQFP64 1.4 51 17 15 14 12 11 9 6 5 3 19 21 22 23 25 27 28 29 54 55 56 58 59 61 64 65 34 39 9/40 8 6 5 3 2 64 61 60 59 10 12 13 14 16 18 19 20 43 44 45 47 48 50 53 54 25 28 9 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 RESET ALE/PROG PSEN EA/VPP XTAL1 XTAL2 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 10 PLCC68 SQUARE VQFP64 1.4 40 41 42 43 45 47 30 68 67 2 49 48 20 24 26 44 46 50 53 57 60 62 63 7 8 10 13 16 29 30 31 32 34 36 21 56 55 58 38 37 11 15 17 33 35 39 42 46 49 51 52 62 63 1 4 7 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6. TS80C51Rx2 Enhanced Features In comparison to the original 80C52, the TS80C51Rx2 implements some new features, which are: • • • • • • • • • • The X2 option. The Dual Data Pointer. The extended RAM. The Programmable Counter Array (PCA). The Watchdog. The 4 level interrupt priority system. The power-off flag. The ONCE mode. The ALE disabling. Some enhanced features are also located in the UART and the timer 2. 6.1. X2 Feature The TS80C51Rx2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following advantages: • • • • Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power. Save power consumption while keeping same CPU power (oscillator power saving). Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes. Increase CPU power by 2 while keeping same crystal frequency. In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by software. 6.1.1. Description The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 1. shows the clock generation block diagram. X2 bit is validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD mode. Figure 2. shows the mode switching waveforms. 2 XTAL1 FXTAL XTAL1:2 0 1 state machine: 6 clock cycles. CPU control FOSC X2 CKCON reg Figure 1. Clock Generation Diagram Rev. C - 06 March, 2001 11 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 XTAL1 XTAL1:2 X2 bit CPU clock STD Mode X2 Mode STD Mode Figure 2. Mode Switching Waveforms The X2 bit in the CKCON register (See Table 3.) allows to switch from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature (X2 mode). CAUTION In order to prevent any incorrect operation while operating in X2 mode, user must be aware that all peripherals using clock frequency as time reference (UART, timers, PCA...) will have their time reference divided by two. For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. UART with 4800 baud rate will have 9600 baud rate. 12 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Table 3. CKCON Register CKCON - Clock Control Register (8Fh) 7 6 5 4 3 2 1 0 - - - - - - - X2 Bit Number Bit Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 - Reserved The value read from this bit is indeterminate. Do not set this bit. 1 - Reserved The value read from this bit is indeterminate. Do not set this bit. 0 X2 Description CPU and peripheral clock bit Clear to select 12 clock periods per machine cycle (STD mode, FOSC=FXTAL/2). Set to select 6 clock periods per machine cycle (X2 mode, FOSC=FXTAL). Reset Value = XXXX XXX0b Not bit addressable For further details on the X2 feature, please refer to ANM072 available on the web (http://www.atmel-wm.com) Rev. C - 06 March, 2001 13 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6.2. Dual Data Pointer Register Ddptr The additional data pointer can be used to speed up code execution and reduce code size in a number of ways. The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 (See Table 4.) that allows the program code to switch between them (Refer to Figure 3). External Data Memory 7 0 DPS DPTR1 DPTR0 AUXR1(A2H) DPH(83H) DPL(82H) Figure 3. Use of Dual Pointer Table 4. AUXR1: Auxiliary Register 1 AUXR1 Address 0A2H Reset value Symbol DPS GF3 a. b. - - - - GF3 - - DPS X X X X 0 X X 0 Function Not implemented, reserved for future use.a Data Pointer Selection. DPS Operating Mode 0 DPTR0 Selected 1 DPTR1 Selected This bit is a general purpose user flagb. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new feature. In that case, the reset value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. GF3 will not be available on first version of the RC devices. Application Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’ pointer and the other one as a "destination" pointer. 14 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Destroys DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 EQU 0A2H ; 0000 909000 MOV DPTR,#SOURCE 0003 05A2 INC AUXR1 0005 90A000 MOV DPTR,#DEST 0008 LOOP: 0008 05A2 INC AUXR1 000A E0 MOVX A,@DPTR 000B A3 INC DPTR 000C 05A2 INC AUXR1 000E F0 MOVX @DPTR,A 000F A3 INC DPTR 0010 70F6 JNZ LOOP 0012 05A2 INC AUXR1 ; address of SOURCE ; switch data pointers ; address of DEST ; switch data pointers ; get a byte from SOURCE ; increment SOURCE address ; switch data pointers ; write the byte to DEST ; increment DEST address ; check for 0 terminator ; (optional) restore DPS INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state. Rev. C - 06 March, 2001 15 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6.3. Expanded RAM (XRAM) The TS80C51Rx2 provide additional Bytes of ramdom access memory (RAM) space for increased data parameter handling and high level language usage. RA2, RB2 and RC2 devices have 256 bytes of expanded RAM, from 00H to FFH in external data space; RD2 devices have 768 bytes of expanded RAM, from 00H to 2FFH in external data space. The TS80C51Rx2 has internal data memory that is mapped into four separate segments. The four segments are: • 1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable. • 2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only. • 3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly addressable only. • 4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and with the EXTRAM bit cleared in the AUXR register. (See Table 5.) The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128 bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same address space as the SFR. That means they have the same address, but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the CPU knows whether the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction. • Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data ,accesses the SFR at location 0A0H (which is P2). • Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For example: MOV @R0, # data where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H). • The 256 or 768 XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions. This part of memory which is physically located on-chip, logically occupies the first 256 or 768 bytes of external data memory. • With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in combination with any of the registers R0, R1 of the selected bank or DPTR. An access to XRAM will not affect ports P0, P2, P3.6 (WR) and P3.7 (RD). For example, with EXTRAM = 0, MOVX @R0, # data where R0 contains 0A0H, accesses the XRAM at address 0A0H rather than external memory. An access to external data memory locations higher than FFH (i.e. 0100H to FFFFH) (higher than 2FFH (i.e. 0300H to FFFFH for RD devices) will be performed with the MOVX DPTR instructions in the same way as in the standard 80C51, so with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and read timing signals. Refer to Figure . For RD devices, accesses to expanded RAM from 100H to 2FFH can only be done thanks to the use of DPTR. • With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51. MOVX @ Ri will provide an eight-bit address multiplexed with data on Port0 and any output port pins can be used to output higher order address bits. This is to provide the external paging capability. MOVX @DPTR will generate a sixteen-bit address. Port2 outputs the high-order eight address bits (the contents of DPH) while Port0 multiplexes the low-order eight address bits (DPL) with data. MOVX @ Ri and MOVX @DPTR will generate either read or write signals on P3.6 (WR) and P3.7 (RD). The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the XRAM. 16 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 FF(RA, RB, RC)/2FF (RD) FF Upper 128 bytes Internal Ram indirect accesses 80 XRAM 256 bytes Special Function Register direct accesses External Data Memory 80 Lower 128 bytes Internal Ram direct or indirect accesses 0100 (RA, RB, RC) or 0300 (RD) 0000 00 00 FFFF FF Figure 4. Internal and External Data Memory Address Table 5. Auxiliary Register AUXR Address 08EH Reset value - - - - - - EXTRA M AO X X X X X X 0 0 Symbol AO Function Not implemented, reserved for future use.a Disable/Enable ALE AO EXTRAM Rev. C - 06 March, 2001 Operating Mode 0 ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode is used) 1 ALE is active only during a MOVX or MOVC instruction Internal/External RAM (00H-FFH) access using MOVX @ Ri/ @ DPTR EXTRAM a. AUXR Operating Mode 0 Internal XRAM access using MOVX @ Ri/ @ DPTR 1 External data memory access User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. 17 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6.4. Timer 2 The timer 2 in the TS80C51RX2 is compatible with the timer 2 in the 80C52. It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2, connected in cascade. It is controlled by T2CON register (See Table 6) and T2MOD register (See Table 7). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects FOSC/12 (timer operation) or external pin T2 (counter operation) as the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input. Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON), as described in the Atmel Wireless & Microcontrollers 8bit Microcontroller Hardware description. Refer to the Atmel Wireless & Microcontrollers 8-bit Microcontroller Hardware description for the description of Capture and Baud Rate Generator Modes. In TS80C51RX2 Timer 2 includes the following enhancements: • Auto-reload mode with up or down counter • Programmable clock-output 6.4.1. Auto-Reload Mode The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. If DCEN bit in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the Atmel Wireless & Microcontrollers 8-bit Microcontroller Hardware description). If DCEN bit is set, timer 2 acts as an Up/down timer/counter as shown in Figure 5. In this mode the T2EX pin controls the direction of count. When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2. When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers. The EXF2 bit toggles when timer 2 overflows or underflows according to the the direction of the count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit resolution. 18 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 (:6 in X2 mode) XTAL1 FXTAL :12 FOSC 0 1 T2 C/T2 T2CONreg TR2 T2CONreg (DOWN COUNTING RELOAD VALUE) FFh FFh (8-bit) (8-bit) T2EX: if DCEN=1, 1=UP if DCEN=1, 0=DOWN if DCEN = 0, up counting TOGGLE T2CONreg EXF2 TL2 TH2 (8-bit) (8-bit) TF2 TIMER 2 INTERRUPT T2CONreg RCAP2L (8-bit) RCAP2H (8-bit) (UP COUNTING RELOAD VALUE) Figure 5. Auto-Reload Mode Up/Down Counter (DCEN = 1) 6.4.2. Programmable Clock-Output In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 6) . The input clock increments TL2 at frequency FOSC/2. The timer repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer 2 overflows do not generate interrupts. The formula gives the clock-out frequency as a function of the system oscillator frequency and the value in the RCAP2H and RCAP2L registers : F osc Clock – OutFrequency = -------------------------------------------------------------------------------------4 × ( 65536 – RCAP2H ⁄ RCAP2L ) For a 16 MHz system clock, timer 2 has a programmable frequency range of 61 Hz (FOSC/216) to 4 MHz (FOSC/4). The generated clock signal is brought out to T2 pin (P1.0). Timer 2 is programmed for the clock-out mode as follows: • • • • Set T2OE bit in T2MOD register. Clear C/T2 bit in T2CON register. Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers. Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or a different one depending on the application. • To start the timer, set TR2 run control bit in T2CON register. Rev. C - 06 March, 2001 19 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers. XTAL1 :2 (:1 in X2 mode) TR2 T2CON reg TL2 (8-bit) TH2 (8-bit) OVERFLOW RCAP2L RCAP2H (8-bit) (8-bit) Toggle T2 Q D T2OE T2MOD reg T2EX EXF2 EXEN2 T2CON reg TIMER 2 INTERRUPT T2CON reg Figure 6. Clock-Out Mode C/T2 = 0 20 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Table 6. T2CON Register T2CON - Timer 2 Control Register (C8h) 7 6 5 4 3 2 1 0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2# Bit Number Bit Mnemonic 7 TF2 Description Timer 2 overflow Flag Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0. 6 EXF2 Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode (DCEN = 1) 5 RCLK Receive Clock bit Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3. 4 TCLK Transmit Clock bit Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3. 3 EXEN2 Timer 2 External Enable bit Clear to ignore events on T2EX pin for timer 2 operation. Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to clock the serial port. 2 TR2 1 C/T2# 0 CP/RL2# Timer 2 Run control bit Clear to turn off timer 2. Set to turn on timer 2. Timer/Counter 2 select bit Clear for timer operation (input from internal clock system: FOSC). Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode. Timer 2 Capture/Reload bit If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow. Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1. Reset Value = 0000 0000b Bit addressable Rev. C - 06 March, 2001 21 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Table 7. T2MOD Register T2MOD - Timer 2 Mode Control Register (C9h) 7 6 5 4 3 2 1 0 - - - - - - T2OE DCEN Bit Number Bit Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 - Reserved The value read from this bit is indeterminate. Do not set this bit. 1 T2OE Timer 2 Output Enable bit Clear to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output. 0 DCEN Down Counter Enable bit Clear to disable timer 2 as up/down counter. Set to enable timer 2 as up/down counter. Description Reset Value = XXXX XX00b Not bit addressable 22 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6.5. Programmable Counter Array PCA The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/ capture modules. Its clock input can be programmed to count any one of the following signals: • Oscillator frequency ÷ 12 (÷ 6 in X2 mode) • Oscillator frequency ÷ 4 (÷ 2 in X2 mode) • Timer 0 overflow • External input on ECI (P1.2) Each compare/capture modules can be programmed in any one of the following modes: • rising and/or falling edge capture, • software timer, • high-speed output, or • pulse width modulator. Module 4 can also be programmed as a watchdog timer (See Section "PCA Watchdog Timer", page 33). When the compare/capture modules are programmed in the capture mode, software timer, or high speed output mode, an interrupt can be generated when the module executes its function. All five modules plus the PCA timer overflow share one interrupt vector. The PCA timer/counter and compare/capture modules share Port 1 for external I/O. These pins are listed below. If the port is not used for the PCA, it can still be used for standard I/O. PCA component External I/O Pin 16-bit Counter P1.2 / ECI 16-bit Module 0 P1.3 / CEX0 16-bit Module 1 P1.4 / CEX1 16-bit Module 2 P1.5 / CEX2 16-bit Module 3 P1.6 / CEX3 16-bit Module 4 P1.7 / CEX4 The PCA timer is a common time base for all five modules (See Figure 7). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD SFR (See Table 8) and can be programmed to run at: • • • • 1/12 the oscillator frequency. (Or 1/6 in X2 Mode) 1/4 the oscillator frequency. (Or 1/2 in X2 Mode) The Timer 0 overflow The input on the ECI pin (P1.2) Rev. C - 06 March, 2001 23 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 To PCA modules Fosc /12 overflow Fosc / 4 CH T0 OVF It CL 16 bit up/down counter P1.2 CIDL WDTE CF CR CPS1 CPS0 ECF CMOD 0xD9 CCF2 CCF1 CCF0 CCON 0xD8 Idle CCF4 CCF3 Figure 7. PCA Timer/Counter Table 8. CMOD: PCA Counter Mode Register CMOD Address 0D9H Reset value Symbol CIDL WDTE - - - CPS1 CPS0 ECF 0 0 X X X 0 0 0 Function CIDL Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs it to be gated off during idle. WDTE Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it. - Not implemented, reserved for future use.a CPS1 PCA Count Pulse Select bit 1. CPS0 PCA Count Pulse Select bit 0. CPS1 ECF a. b. CPS0 Selected PCA input.b 0 0 Internal clock fosc/12 ( Or fosc/6 in X2 Mode). 0 1 1 0 Internal clock fosc/4 ( Or fosc/2 in X2 Mode). Timer 0 Overflow 1 1 External clock at ECI/P1.2 pin (max rate = fosc/ 8) PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables that function of CF. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. fosc = oscillator frequency The CMOD SFR includes three additional bits associated with the PCA (See Figure 7 and Table 8). • The CIDL bit which allows the PCA to stop during idle mode. • The WDTE bit which enables or disables the watchdog function on module 4. 24 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 • The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set when the PCA timer overflows. Rev. C - 06 March, 2001 25 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 The CCON SFR contains the run control bit for the PCA and the flags for the PCA timer (CF) and each module (Refer to Table 9). • Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this bit. • Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can only be cleared by software. • Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. These flags also can only be cleared by software. Table 9. CCON: PCA Counter Control Register CCON Address 0D8H Reset value Symbol CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 0 0 X 0 0 0 0 0 Function CF PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be cleared by software. CR PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA counter off. - Not implemented, reserved for future use.a CCF4 PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF3 PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF2 PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF1 PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF0 PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. The watchdog timer function is implemented in module 4 (See Figure 10). The PCA interrupt system is shown in Figure 8 26 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 CF CR CCF4 CCF3 CCF2 CCF1 CCF0 CCON 0xD8 PCA Timer/Counter Module 0 Module 1 To Interrupt priority decoder Module 2 Module 3 Module 4 CMOD.0 ECF ECCFn CCAPMn.0 IE.6 EC IE.7 EA Figure 8. PCA Interrupt System PCA Modules: each one of the five compare/capture modules has six possible functions. It can perform: • 16-bit Capture, positive-edge triggered, • 16-bit Capture, negative-edge triggered, • 16-bit Capture, both positive and negative-edge triggered, • 16-bit Software Timer, • 16-bit High Speed Output, • 8-bit Pulse Width Modulator. In addition, module 4 can be used as a Watchdog Timer. Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. (See Table 10). The registers contain the bits that control the mode that each module will operate in. • The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module. • PWM (CCAPMn.1) enables the pulse width modulation mode. • The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module's capture/compare register. • The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module's capture/compare register. • The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition. • The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function. Table 11 shows the CCAPMn settings for the various PCA functions. . Rev. C - 06 March, 2001 27 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Table 10. CCAPMn: PCA Modules Compare/Capture Control Registers CCAPM0=0DAH CCAPM1=0DBH CCAPM2=0DCH CCAPM3=0DDH CCAPM4=0DEH CCAPMn Address n=0-4 Reset value ECOMn CAPPn CAPNn X 0 0 0 MATn TOGn 0 0 PWMm ECCFn 0 0 Function Symbol Not implemented, reserved for future use.a ECOMn Enable Comparator. ECOMn = 1 enables the comparator function. CAPPn Capture Positive, CAPPn = 1 enables positive edge capture. CAPNn Capture Negative, CAPNn = 1 enables negative edge capture. MATn Match. When MATn = 1, a match of the PCA counter with this module's compare/capture register causes the CCFn bit in CCON to be set, flagging an interrupt. TOGn Toggle. When TOGn = 1, a match of the PCA counter with this module's compare/capture register causes the CEXn pin to toggle. PWMn Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width modulated output. ECCFn Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt. a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Table 11. PCA Module Modes (CCAPMn Registers) ECOMn CAPPn CAPNn 0 0 0 MATn TOGn 0 0 PWMm ECCFn 0 0 Module Function No Operation X 1 0 0 0 0 X 16-bit capture by a positive-edge trigger on CEXn X 0 1 0 0 0 X 16-bit capture by a negative trigger on CEXn X 1 1 0 0 0 X 16-bit capture by a transition on CEXn 1 0 0 1 0 0 X 16-bit Software Timer / Compare mode. 1 0 0 1 1 0 X 16-bit High Speed Output 1 0 0 0 0 1 0 8-bit PWM 1 0 0 1 X 0 X Watchdog Timer (module 4 only) There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module is used in the PWM mode these registers are used to control the duty cycle of the output (See Table 12 & Table 13) 28 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Table 12. CCAPnH: PCA Modules Capture/Compare Registers High CCAPnH Address n=0-4 CCAP0H=0FAH CCAP1H=0FBH CCAP2H=0FCH CCAP3H=0FDH CCAP4H=0FEH Reset value 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Table 13. CCAPnL: PCA Modules Capture/Compare Registers Low CCAPnL Address n=0-4 CCAP0L=0EAH CCAP1L=0EBH CCAP2L=0ECH CCAP3L=0EDH CCAP4L=0EEH Reset value 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Table 14. CH: PCA Counter High CH Address 0F9H Reset value 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Table 15. CL: PCA Counter Low CL Address 0E9H Reset value Rev. C - 06 March, 2001 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 29 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6.5.1. PCA Capture Mode To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module's capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated (Refer to Figure 9). CF CR CCF4 CCF3 CCF2 CCF1 CCF0 CCON 0xD8 PCA IT PCA Counter/Timer Cex.n CH CL CCAPnH CCAPnL Capture ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n= 0 to 4 0xDA to 0xDE Figure 9. PCA Capture Mode 30 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6.5.2. 16-bit Software Timer / Compare Mode The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMn register. The PCA timer will be compared to the module's capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (See Figure 10). CF Write to CCAPnL CR CCF4 CCF3 CCF2 CCF1 CCF0 CCON 0xD8 Reset PCA IT Write to CCAPnH 1 CCAPnH 0 CCAPnL Enable Match 16 bit comparator CH RESET * CL PCA counter/timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CIDL WDTE CPS1 CPS0 ECF CCAPMn, n = 0 to 4 0xDA to 0xDE CMOD 0xD9 * Only for Module 4 Figure 10. PCA Compare Mode and PCA Watchdog Timer Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen. Writing to CCAPnH will set the ECOM bit. Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this reason, user software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register. Rev. C - 06 March, 2001 31 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6.5.3. High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA counter and the module's capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must be set (See Figure 11). A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit. CF Write to CCAPnL CR CCF4 CCF3 CCF2 CCF1 CCF0 CCON 0xD8 Reset PCA IT Write to CCAPnH 1 CCAPnH 0 CCAPnL Enable 16 bit comparator CH Match CEXn CL PCA counter/timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n = 0 to 4 0xDA to 0xDE Figure 11. PCA High Speed Output Mode Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen. Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t occur while modifying the compare value. Writing to CCAPnH will set ECOM. For this reason, user software should write CCAPnL first, and then CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register. 32 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6.5.4. Pulse Width Modulator Mode All of the PCA modules can be used as PWM outputs. Figure 12 shows the PWM function. The frequency of the output depends on the source for the PCA timer. All of the modules will have the same frequency of output because they all share the PCA timer. The duty cycle of each module is independently variable using the module's capture register CCAPLn. When the value of the PCA CL SFR is less than the value in the module's CCAPLn SFR the output will be low, when it is equal to or greater than the output will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. This allows updating the PWM without glitches. The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode. CCAPnH Overflow CCAPnL “0” Enable 8 bit comparator CEXn < ≥ “1” CL PCA counter/timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn CCAPMn, n= 0 to 4 0xDA to 0xDE Figure 12. PCA PWM Mode 6.5.5. PCA Watchdog Timer An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic discharge. Module 4 is the only PCA module that can be programmed as a watchdog. However, this module can still be used for other modes if the watchdog is not needed. Figure 10 shows a diagram of how the watchdog works. The user pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This will not cause the RST pin to be driven high. In order to hold off the reset, the user has three options: • 1. periodically change the compare value so it will never match the PCA timer, • 2. periodically change the PCA timer value so it will never match the compare values, or • 3. disable the watchdog by clearing the WDTE bit before a match occurs and then re-enable it. The first two options are more reliable because the watchdog timer is never disabled as in option #3. If the program counter ever goes astray, a match will eventually occur and cause an internal reset. The second option is also not recommended if other PCA modules are being used. Remember, the PCA timer is the time base for all modules; changing the time base for other modules would not be a good idea. Thus, in most applications the first solution is the best option. This watchdog timer won’t generate a reset out on the reset pin. Rev. C - 06 March, 2001 33 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6.6. TS80C51Rx2 Serial I/O Port The serial I/O port in the TS80C51Rx2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates Serial I/O port includes the following enhancements: • Framing error detection • Automatic address recognition 6.6.1. Framing Error Detection Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 13). SM0/FE SM1 SM2 REN TB8 RB8 TI RI SCON (98h) Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1) SM0 to UART mode control (SMOD = 0) SMOD1 SMOD0 - POF GF1 GF0 PD IDL PCON (87h) To UART framing error control Figure 13. Framing Error Block Diagram When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table 16.) bit is set. 34 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure 14. and Figure 15.). RXD D0 D1 D2 Start bit D3 D4 D5 D6 D7 Data byte Stop bit RI SMOD0=X FE SMOD0=1 Figure 14. UART Timings in Mode 1 RXD D0 Start bit D1 D2 D3 D4 D5 D6 Data byte D7 D8 Ninth Stop bit bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 Figure 15. UART Timings in Modes 2 and 3 6.6.2. Automatic Address Recognition The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU is not interrupted by command frames addressed to other devices. If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the device’s address and is terminated by a valid stop bit. To support automatic address recognition, a device is identified by a given address and a broadcast address. NOTE: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect). Rev. C - 06 March, 2001 35 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6.6.3. Given Address Each device has an individual address that is specified in SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example: SADDR SADEN Given 0101 0110b 1111 1100b 0101 01XXb The following is an example of how to use given addresses to address different slaves: Slave A: SADDR SADEN Given 1111 0001b 1111 1010b 1111 0X0Xb Slave B: SADDR SADEN Given 1111 0011b 1111 1001b 1111 0XX1b Slave C: SADDR SADEN Given 1111 0010b 1111 1101b 1111 00X1b The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b). For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b). 6.6.4. Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don’t-care bits, e.g.: SADDR SADEN Broadcast =SADDR OR SADEN 0101 0110b 1111 1100b 1111 111Xb The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses: Slave A: SADDR 1111 0001b SADEN 1111 1010b Broadcast 1111 1X11b, Slave B: SADDR 1111 0011b SADEN 1111 1001b Broadcast 1111 1X11B, Slave C: SADDR= 1111 0010b SADEN 1111 1101b Broadcast 1111 1111b For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh. 36 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6.6.5. Reset Addresses On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. SADEN - Slave Address Mask Register (B9h) 7 6 5 4 3 2 1 0 4 3 2 1 0 Reset Value = 0000 0000b Not bit addressable SADDR - Slave Address Register (A9h) 7 6 5 Reset Value = 0000 0000b Not bit addressable Rev. C - 06 March, 2001 37 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Table 16. SCON Register SCON - Serial Control Register (98h) 7 6 5 4 3 2 1 0 FE/SM0 SM1 SM2 REN TB8 RB8 TI RI Bit Number Bit Mnemonic 7 FE SM0 Description Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. SMOD0 must be set to enable access to the FE bit Serial port Mode bit 0 Refer to SM1 for serial port mode selection. SMOD0 must be cleared to enable access to the SM0 bit Serial port Mode bit 1 SM0 SM1 6 0 0 1 1 SM1 0 1 0 1 Mode 0 1 2 3 Description Shift Register 8-bit UART 9-bit UART 9-bit UART SM2 4 REN Reception Enable bit Clear to disable serial reception. Set to enable serial reception. 3 TB8 Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3. Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit. RB8 FXTAL/12 (/6 in X2 mode) Variable FXTAL/64 or FXTAL/32 (/32, /16 in X2 mode) Variable Serial port Mode 2 bit / Multiprocessor Communication Enable bit Clear to disable multiprocessor communication feature. Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should be cleared in mode 0. 5 2 Baud Rate Receiver Bit 8 / Ninth bit received in modes 2 and 3 Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used. 1 TI Transmit Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. 0 RI Receive Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 14. and Figure 15. in the other modes. Reset Value = 0000 0000b Bit addressable 38 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Table 17. PCON Register PCON - Power Control Register (87h) 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - POF GF1 GF0 PD IDL Bit Number Bit Mnemonic 7 SMOD1 Serial port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. 6 SMOD0 Serial port Mode bit 0 Clear to select SM0 bit in SCON register. Set to to select FE bit in SCON register. 5 - 4 POF Power-Off Flag Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. 3 GF1 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. 2 GF0 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. 1 PD Power-Down mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. 0 IDL Idle mode bit Clear by hardware when interrupt or reset occurs. Set to enter idle mode. Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit. Rev. C - 06 March, 2001 39 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6.7. Interrupt System The TS80C51Rx2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt and the PCA global interrupt. These interrupts are shown in Figure 16. WARNING: Note that in the first version of RC devices, the PCA interrupt is in the lowest priority. Thus the order in INT0, TF0, INT1, TF1, RI or TI, TF2 or EXF2, PCA. High priority interrupt IPH, IP 3 INT0 IE0 0 3 TF0 0 3 INT1 IE1 0 3 Interrupt polling sequence, decreasing from high to low priority TF1 0 3 PCA IT 0 RI TI 3 TF2 EXF2 3 0 0 Individual Enable Global Disable Low priority interrupt Figure 16. Interrupt Control System Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register (See Table 19.). This register also contains a global disable bit, which must be cleared to disable all interrupts at once. Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority register (See Table 20.) and in the Interrupt Priority High register (See Table 21.). shows the bit values and priority levels associated with each combination. The PCA interrupt vector is located at address 0033H. All other vector addresses are the same as standard C52 devices. 40 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Table 18. Priority Level Bit Values IPH.x IP.x Interrupt Level Priority 0 0 0 (Lowest) 0 1 1 1 0 2 1 1 3 (Highest) A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence. Table 19. IE Register IE - Interrupt Enable Register (A8h) 7 6 5 4 3 2 1 0 EA EC ET2 ES ET1 EX1 ET0 EX0 Bit Mnemonic Description 7 EA Enable All interrupt bit Clear to disable all interrupts. Set to enable all interrupts. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its own interrupt enable bit. 6 EC PCA interrupt enable bit Clear to disable . Set to enable. 5 ET2 Timer 2 overflow interrupt Enable bit Clear to disable timer 2 overflow interrupt. Set to enable timer 2 overflow interrupt. 4 ES Serial port Enable bit Clear to disable serial port interrupt. Set to enable serial port interrupt. 3 ET1 Timer 1 overflow interrupt Enable bit Clear to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt. 2 EX1 External interrupt 1 Enable bit Clear to disable external interrupt 1. Set to enable external interrupt 1. 1 ET0 Timer 0 overflow interrupt Enable bit Clear to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. 0 EX0 External interrupt 0 Enable bit Clear to disable external interrupt 0. Set to enable external interrupt 0. Bit Number Reset Value = 0000 0000b Bit addressable Rev. C - 06 March, 2001 41 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Table 20. IP Register IP - Interrupt Priority Register (B8h) 7 6 5 4 3 2 1 0 - PPC PT2 PS PT1 PX1 PT0 PX0 Bit Number Bit Mnemonic 7 - 6 PPC PCA interrupt priority bit Refer to PPCH for priority level. 5 PT2 Timer 2 overflow interrupt Priority bit Refer to PT2H for priority level. 4 PS Serial port Priority bit Refer to PSH for priority level. 3 PT1 Timer 1 overflow interrupt Priority bit Refer to PT1H for priority level. 2 PX1 External interrupt 1 Priority bit Refer to PX1H for priority level. 1 PT0 Timer 0 overflow interrupt Priority bit Refer to PT0H for priority level. 0 PX0 External interrupt 0 Priority bit Refer to PX0H for priority level. Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reset Value = X000 0000b Bit addressable 42 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Table 21. IPH Register IPH - Interrupt Priority High Register (B7h) 7 6 5 4 3 2 1 0 - PPCH PT2H PSH PT1H PX1H PT0H PX0H Bit Number Bit Mnemonic 7 - 6 5 4 3 2 1 0 PPCH Description Reserved The value read from this bit is indeterminate. Do not set this bit. PCA interrupt priority bit high. PPCH PPC Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest PT2H Timer 2 overflow interrupt Priority High bit PT2H PT2 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest PSH Serial port Priority High bit PSH PS 0 0 0 1 1 0 1 1 Priority Level Lowest Highest PT1H Timer 1 overflow interrupt Priority High bit PT1H PT1 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest PX1H External interrupt 1 Priority High bit PX1H PX1 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest PT0H Timer 0 overflow interrupt Priority High bit PT0H PT0 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest PX0H External interrupt 0 Priority High bit PX0H PX0 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Reset Value = X000 0000b Not bit addressable Rev. C - 06 March, 2001 43 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6.8. Idle mode An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirely : the Stack Pointer, Program Counter, Program Status Word, Accumulator and all other registers maintain their data during Idle. The port pins hold the logical states they had at the time Idle was activated. ALE and PSEN hold at logic high levels. There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be serviced, and following RETI the next instruction to be executed will be the one following the instruction that put the device into idle. The flag bits GF0 and GF1 can be used to give an indication if an interrupt occured during normal operation or during an Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset. 6.9. Power-Down Mode To save maximum power, a power-down mode can be invoked by software (Refer to Table 17., PCON register). In power-down mode, the oscillator is stopped and the instruction that invoked power-down mode is the last instruction executed. The internal RAM and SFRs retain their value until the power-down mode is terminated. VCC can be lowered to save further power. Either a hardware reset or an external interrupt can cause an exit from power-down. To properly terminate power-down, the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize. Only external interrupts INT0 and INT1 are useful to exit from power-down. For that, interrupt must be enabled and configured as level or edge sensitive interrupt input. Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 17. When both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and power down exit will be completed when the first input will be released. In this case the higher priority interrupt service routine is executed. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put TS80C51Rx2 into power-down mode. INT0 INT1 XTAL1 Active phase Power-down phase Oscillator restart phase Active phase Figure 17. Power-Down Exit Waveform Exit from power-down by reset redefines all the SFRs, exit from power-down by external interrupt does no affect the SFRs. Exit from power-down by either reset or external interrupt does not affect the internal RAM content. NOTE: If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and idle mode is not entered. 44 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Table 22. The state of ports during idle and power-down mode Mode Program Memory ALE PSEN PORT0 Idle Idle Power Down Power Down Internal External Internal External 1 1 0 0 1 1 0 0 Port Data* Floating Port Data* Floating PORT1 PORT2 PORT3 Port Port Port Port Port Data Address Port Data Port Data Port Port Port Port Data Data Data Data Data Data Data Data * Port 0 can force a "zero" level. A "one" will leave port floating. Rev. C - 06 March, 2001 45 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6.10. Hardware Watchdog Timer The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST-pin. 6.10.1. Using the WDT To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST-pin. The RESET pulse duration is 96 x TOSC , where TOSC = 1/FOSC . To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset. To have a more powerful WDT, a 27 counter has been added to extend the Time-out capability, ranking from 16ms to 2s @ FOSC = 12MHz. To manage this feature, refer to WDTPRG register description, Table 24. (SFR0A7h). Table 23. WDTRST Register WDTRST Address (0A6h) Reset value 7 6 5 4 3 2 1 X X X X X X X Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence. 46 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Table 24. WDTPRG Register WDTPRG Address (0A7h) 7 6 5 4 3 2 1 0 T4 T3 T2 T1 T0 S2 S1 S0 Bit Number Bit Mnemonic 7 T4 6 T3 5 T2 4 T1 3 T0 2 S2 WDT Time-out select bit 2 1 S1 WDT Time-out select bit 1 0 S0 WDT Time-out select bit 0 Description Reserved Do not try to set or clear this bit. S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Selected Time-out (214 - 1) machine cycles, 16.3 ms @ 12 MHz (215 - 1) machine cycles, 32.7 ms @ 12 MHz (216 - 1) machine cycles, 65.5 ms @ 12 MHz (217 - 1) machine cycles, 131 ms @ 12 MHz (218 - 1) machine cycles, 262 ms @ 12 MHz (219 - 1) machine cycles, 542 ms @ 12 MHz (220 - 1) machine cycles, 1.05 s @ 12 MHz (221 - 1) machine cycles, 2.09 s @ 12 MHz Reset value XXXX X000 6.10.2. WDT during Power Down and Idle In Power Down mode the oscillator stops, which means the WDT also stops. While in Power Down mode the user does not need to service the WDT. There are 2 methods of exiting Power Down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power Down mode. When Power Down is exited with hardware reset, servicing the WDT should occur as it normally should whenever the TS80C51Rx2 is reset. Exiting Power Down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service routine. To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is best to reset the WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the TS80C51Rx2 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode. Rev. C - 06 March, 2001 47 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6.11. ONCETM Mode (ON Chip Emulation) The ONCE mode facilitates testing and debugging of systems using TS80C51Rx2 without removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the TS80C51Rx2; the following sequence must be exercised: • Pull ALE low while the device is in reset (RST high) and PSEN is high. • Hold ALE low as RST is deactivated. While the TS80C51Rx2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit Table 26. shows the status of the port pins during ONCE mode. Normal operation is restored when normal reset is applied. Table 25. External Pin Status during ONCE Mode 48 ALE PSEN Port 0 Port 1 Port 2 Port 3 XTAL1/2 Weak pull-up Weak pull-up Float Weak pull-up Weak pull-up Weak pull-up Active Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6.12. Power-Off Flag The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. A cold start reset is the one induced by VCC switch-on. A warm start reset occurs while VCC is still applied to the device and could be generated for example by an exit from power-down. The power-off flag (POF) is located in PCON register (See Table 26.). POF is set by hardware when VCC rises from 0 to its nominal voltage. The POF can be set or cleared by software allowing the user to determine the type of reset. The POF value is only relevant with a Vcc range from 4.5V to 5.5V. For lower Vcc value, reading POF bit will return indeterminate value. Table 26. PCON Register PCON - Power Control Register (87h) 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - POF GF1 GF0 PD IDL Bit Number Bit Mnemonic 7 SMOD1 Serial port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. 6 SMOD0 Serial port Mode bit 0 Clear to select SM0 bit in SCON register. Set to to select FE bit in SCON register. 5 - 4 POF Power-Off Flag Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. 3 GF1 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. 2 GF0 General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. 1 PD Power-Down mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. 0 IDL Idle mode bit Clear by hardware when interrupt or reset occurs. Set to enter idle mode. Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reset Value = 00X1 0000b Not bit addressable Rev. C - 06 March, 2001 49 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 6.13. Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit. The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer output but remains active during MOVX and MOVC instructions and external fetches. During ALE disabling, ALE pin is weakly pulled high. Table 27. AUXR Register AUXR - Auxiliary Register (8Eh) 7 6 5 4 3 2 1 0 - - - - - - EXTRAM AO Bit Number Bit Mnemonic 7 - Reserved The value read from this bit is indeterminate. Do not set this bit. 6 - Reserved The value read from this bit is indeterminate. Do not set this bit. 5 - Reserved The value read from this bit is indeterminate. Do not set this bit. 4 - Reserved The value read from this bit is indeterminate. Do not set this bit. 3 - Reserved The value read from this bit is indeterminate. Do not set this bit. 2 - Reserved The value read from this bit is indeterminate. Do not set this bit. 1 EXTRAM 0 AO Description EXTRAM bit See Table 5. ALE Output bit Clear to restore ALE operation during internal fetches. Set to disable ALE operation during internal fetches. Reset Value = XXXX XX00b Not bit addressable 50 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 7. TS83C51RB2/RC2/RD2 ROM 7.1. ROM Structure The TS83C51RB2/RC2/RD2 ROM memory is divided in three different arrays: • the code array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16/32/64 Kbytes. • the encryption array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 bytes. • the signature array:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 bytes. 7.2. ROM Lock System The program Lock system, when programmed, protects the on-chip program against software piracy. 7.2.1. 7.2.1. Encryption Array Within the ROM array are 64 bytes of encryption array that are initially unprogrammed (all FF’s). Every time a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This byte is then exclusive-NOR’ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with the encryption array in the unprogrammed state, will return the code in its original, unmodified form. When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a verification routine will display the content of the encryption array. For this reason all the unused code bytes should be programmed with random values. This will ensure program protection. 7.2.2. Program Lock Bits The lock bits when programmed according to Table 28. will provide different level of protection for the on-chip code and data. Table 28. Program Lock bits Program Lock Bits Protection description Security level LB1 LB2 LB3 1 U U U No program lock features enabled. Code verify will still be encrypted by the encryption array if programmed. MOVC instruction executed from external program memory returns non encrypted data. 2 P U U MOVC instruction executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset. 3 U P U Same as level 1+ Verify disable. This security level is only available for 51RDX2 devices. U: unprogrammed P: programmed 7.2.3. Signature bytes The TS83C51RB2/RC2/RD2 contains 4 factory programmed signatures bytes. To read these bytes, perform the process described in section 8.3. 7.2.4. Verify Algorithm Refer to 8.3.4. Rev. C - 06 March, 2001 51 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 8. TS87C51RB2/RC2/RD2 EPROM 8.1. EPROM Structure The TS87C51RB2/RC2/RD2 EPROM is divided in two different arrays: • the code array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16/32/64 Kbytes. • the encryption array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 bytes. In addition a third non programmable array is implemented: • the signature array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 bytes. 8.2. EPROM Lock System The program Lock system, when programmed, protects the on-chip program against software piracy. 8.2.1. Encryption Array Within the EPROM array are 64 bytes of encryption array that are initially unprogrammed (all FF’s). Every time a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This byte is then exclusive-NOR’ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with the encryption array in the unprogrammed state, will return the code in its original, unmodified form. When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a verification routine will display the content of the encryption array. For this reason all the unused code bytes should be programmed with random values. This will ensure program protection. 8.2.2. Program Lock Bits The three lock bits, when programmed according to Table 29.8.2.3. , will provide different level of protection for the on-chip code and data. Table 29. Program Lock bits Program Lock Bits Protection description Security level LB1 LB2 LB3 1 U U U No program lock features enabled. Code verify will still be encrypted by the encryption array if programmed. MOVC instruction executed from external program memory returns non encrypted data. 2 P U U MOVC instruction executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the EPROM is disabled. 3 U P U Same as 2, also verify is disabled. 4 U U P Same as 3, also external execution is disabled. U: unprogrammed, P: programmed WARNING: Security level 2 and 3 should only be programmed after EPROM and Core verification. 8.2.3. Signature bytes The TS87C51RB2/RC2/RD2 contains 4 factory programmed signatures bytes. To read these bytes, perform the process described in section 8.3. 52 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 8.3. EPROM Programming 8.3.1. Set-up modes In order to program and verify the EPROM or to read the signature bytes, the TS87C51RB2/RC2/RD2 is placed in specific set-up modes (See Figure 18.). Control and program signals must be held at the levels indicated in Table 30. 8.3.2. Definition of terms Address Lines: P1.0-P1.7, P2.0-P2.5, P3.4, P3.5 respectively for A0-A15 (P2.5 (A13) for RB, P3.4 (A14) for RC, P3.5 (A15) for RD) Data Lines: P0.0-P0.7 for D0-D7 Control Signals: RST, PSEN, P2.6, P2.7, P3.3, P3.6, P3.7. Program Signals: ALE/PROG, EA/VPP. Table 30. EPROM Set-Up Modes Mode RST PSEN Program Code data 1 0 Verify Code data 1 0 Program Encryption Array Address 0-3Fh 1 0 Read Signature Bytes 1 0 Program Lock bit 1 1 Program Lock bit 2 Program Lock bit 3 Rev. C - 06 March, 2001 ALE/ PROG EA/VPP P2.6 P2.7 P3.3 P3.6 P3.7 12.75V 0 1 1 1 1 1 0 0 1 1 12.75V 0 1 0 1 1 0 0 0 0 0 12.75V 1 1 1 1 1 1 0 12.75V 1 1 1 0 0 1 0 12.75V 1 0 1 1 0 1 1 1 53 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 +5V EA/VPP PROGRAM SIGNALS* VCC ALE/PROG RST PSEN P2.6 P2.7 P3.3 P3.6 P3.7 CONTROL SIGNALS* 4 to 6 MHz P0.0-P0.7 D0-D7 P1.0-P1.7 A0-A7 P2.0-P2.5 P3.4-P3.5 A8-A15 XTAL1 VSS GND * See Table 31. for proper value on these inputs Figure 18. Set-Up Modes Configuration 8.3.3. Programming Algorithm The Improved Quick Pulse algorithm is based on the Quick Pulse algorithm and decreases the number of pulses applied during byte programming from 25 to 1. To program the TS87C51RB2/RC2/RD2 the following sequence must be exercised: • • • • • • Step 1: Activate the combination of control signals. Step 2: Input the valid address on the address lines. Step 3: Input the appropriate data on the data lines. Step 4: Raise EA/VPP from VCC to VPP (typical 12.75V). Step 5: Pulse ALE/PROG once. Step 6: Lower EA/VPP from VPP to VCC Repeat step 2 through 6 changing the address and data for the entire array or until the end of the object file is reached (See Figure 19.). 8.3.4. Verify algorithm Code array verify must be done after each byte or block of bytes is programmed. In either case, a complete verify of the programmed array will ensure reliable programming of the TS87C51RB2/RC2/RD2. P 2.7 is used to enable data output. To verify the TS87C51RB2/RC2/RD2 code the following sequence must be exercised: • Step 1: Activate the combination of program and control signals. • Step 2: Input the valid address on the address lines. • Step 3: Read data on the data lines. Repeat step 2 through 3 changing the address for the entire array verification (See Figure 19.) The encryption array cannot be directly verified. Verification of the encryption array is done by observing that the code array is well encrypted. 54 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Programming Cycle Read/Verify Cycle A0-A12 Data In D0-D7 Data Out 100µs ALE/PROG EA/VPP 12.75V 5V 0V Control signals Figure 19. Programming and Verification Signal’s Waveform 8.4. EPROM Erasure (Windowed Packages Only) Erasing the EPROM erases the code array, the encryption array and the lock bits returning the parts to full functionality. Erasure leaves all the EPROM cells in a 1’s state (FF). 8.4.1. Erasure Characteristics The recommended erasure procedure is exposure to ultraviolet light (at 2537 Å) to an integrated dose at least 15 W-sec/cm2. Exposing the EPROM to an ultraviolet lamp of 12,000 µW/cm2 rating for 30 minutes, at a distance of about 25 mm, should be sufficient. An exposure of 1 hour is recommended with most of standard erasers. Erasure of the EPROM begins to occur when the chip is exposed to light with wavelength shorter than approximately 4,000 Å. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in room-level fluorescent lighting) could cause inadvertent erasure. If an application subjects the device to this type of exposure, it is suggested that an opaque label be placed over the window. Rev. C - 06 March, 2001 55 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 9. Signature Bytes The TS83/87C51RB2/RC2/RD2 has four signature bytes in location 30h, 31h, 60h and 61h. To read these bytes follow the procedure for EPROM verify but activate the control lines provided in Table 31. for Read Signature Bytes. Table 31. shows the content of the signature byte for the TS87C51RB2/RC2/RD2. Table 31. Signature Bytes Content 56 Location Contents 30h 58h Manufacturer Code: Atmel Wireless & Microcontrollers Comment 31h 57h Family Code: C51 X2 60h 7Ch Product name: TS83C51RD2 60h FCh Product name: TS87C51RD2 60h 37h Product name: TS83C51RC2 60h B7h Product name: TS87C51RC2 60h 3Bh Product name: TS83C51RB2 60h BBh Product name: TS87C51RB2 61h FFh Product revision number Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 10. Electrical Characteristics 10.1. Absolute Maximum Ratings (1) Ambiant Temperature Under Bias: C = commercial I = industrial Storage Temperature Voltage on VCC to VSS Voltage on VPP to VSS Voltage on Any Pin to VSS Power Dissipation 0°C to 70°C -40°C to 85°C -65°C to + 150°C -0.5 V to + 7 V -0.5 V to + 13 V -0.5 V to VCC + 0.5 V 1 W(2) NOTES 1. Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. 2. This value is based on the maximum allowable die temperature and the thermal resistance of the package. 10.2. Power consumption measurement Since the introduction of the first C51 devices, every manufacturer made operating Icc measurements under reset, which made sense for the designs were the CPU was running under reset. In Atmel Wireless & Microcontrollers new devices, the CPU is no more active during reset, so the power consumption is very low but is not really representative of what will happen in the customer system. That’s why, while keeping measurements under Reset, Atmel Wireless & Microcontrollers presents a new way to measure the operating Icc: Using an internal test ROM, the following code is executed: Label: SJMP Label (80 FE) Ports 1, 2, 3 are disconnected, Port 0 is tied to FFh, EA = Vcc, RST = Vss, XTAL2 is not connected and XTAL1 is driven by the clock. This is much more representative of the real operating Icc. Rev. C - 06 March, 2001 57 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 10.3. DC Parameters for Standard Voltage TA = 0°C to +70°C; VSS = 0 V; VCC = 5 V ± 10%; F = 0 to 40 MHz. TA = -40°C to +85°C; VSS = 0 V; VCC = 5 V ± 10%; F = 0 to 40 MHz. Table 32. DC Parameters in Standard Voltage Symbol Parameter VIL Input Low Voltage VIH Input High Voltage except XTAL1, RST VIH1 Input High Voltage, XTAL1, RST VOL Output Low Voltage, ports 1, 2, 3, 4, 5(6) VOL1 VOL2 VOH Min Typ Max Unit -0.5 0.2 VCC - 0.1 V 0.2 VCC + 0.9 VCC + 0.5 V 0.7 VCC VCC + 0.5 V 0.3 0.45 1.0 V V V IOL = 100 µA(4) 0.3 0.45 1.0 V V V IOL = 200 µA(4) 0.3 0.45 1.0 V V V IOL = 100 µA(4) Output Low Voltage, port 0 (6) Output Low Voltage, ALE, PSEN Output High Voltage, ports 1, 2, 3, 4, 5 VCC - 0.3 V V V VCC - 0.7 VCC - 1.5 VOH1 Output High Voltage, port 0 VCC - 0.3 V V V VCC - 1.5 Output High Voltage,ALE, PSEN VCC - 0.3 V V V VCC - 1.5 50 IOL = 3.2 mA(4) IOL = 7.0 mA(4) IOL = 1.6 mA(4) IOL = 3.5 mA(4) IOH = -10 µA IOH = -30 µA IOH = -60 µA IOH = -200 µA IOH = -3.2 mA IOH = -7.0 mA IOH = -100 µA IOH = -1.6 mA IOH = -3.5 mA VCC = 5 V ± 10% 90 (5) 200 kΩ IIL Logical 0 Input Current ports 1, 2, 3, 4, 5 -50 µA Vin = 0.45 V ILI Input Leakage Current ±10 µA 0.45 V < Vin < VCC ITL Logical 1 to 0 Transition Current, ports 1, 2, 3, 4, 5 -650 µA Vin = 2.0 V CIO Capacitance of I/O Buffer 10 pF Fc = 1 MHz TA = 25°C IPD Power Down Current 50 µA 2.0 V < VCC < 5.5 V(3) ICC Power Supply Current Maximum values, X1 mode: (7) under RESET 58 RST Pulldown Resistor IOL = 3.5 mA(4) VCC = 5 V ± 10% VCC - 0.7 RRST IOL = 1.6 mA(4) VCC = 5 V ± 10% VCC - 0.7 VOH2 Test Conditions 20 (5) 1 + 0.4 Freq (MHz) @12MHz 5.8 @16MHz 7.4 VCC = 5.5 V(1) mA Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Symbol Parameter ICC Power Supply Current Maximum values, X1 mode: (7) operating ICC idle Min Typ Max Unit 3 + 0.6 Freq (MHz) mA VCC = 5.5 V(8) mA VCC = 5.5 V(2) @12MHz 10.2 @16MHz 12.6 Power Supply Current Maximum values, X1 mode: (7) 0.25+0.3Freq (MHz) @12MHz 3.9 @16MHz 5.1 Test Conditions 10.4. DC Parameters for Low Voltage TA = 0°C to +70°C; VSS = 0 V; VCC = 2.7 V to 5.5 V ± 10%; F = 0 to 30 MHz. TA = -40°C to +85°C; VSS = 0 V; VCC = 2.7 V to 5.5 V ± 10%; F = 0 to 30 MHz. Table 33. DC Parameters for Low Voltage Symbol Parameter Min Typ Max Unit -0.5 0.2 VCC - 0.1 V 0.2 VCC + 0.9 VCC + 0.5 V 0.7 VCC VCC + 0.5 V Test Conditions VIL Input Low Voltage VIH Input High Voltage except XTAL1, RST VIH1 Input High Voltage, XTAL1, RST VOL Output Low Voltage, ports 1, 2, 3, 4, 5 (6) 0.45 V IOL = 0.8 mA(4) VOL1 Output Low Voltage, port 0, ALE, PSEN (6) 0.45 V IOL = 1.6 mA(4) VOH Output High Voltage, ports 1, 2, 3, 4, 5 0.9 VCC V IOH = -10 µA VOH1 Output High Voltage, port 0, ALE, PSEN 0.9 VCC V IOH = -40 µA IIL Logical 0 Input Current ports 1, 2, 3, 4, 5 -50 µA Vin = 0.45 V ILI Input Leakage Current ±10 µA 0.45 V < Vin < VCC ITL Logical 1 to 0 Transition Current, ports 1, 2, 3, 4, 5 -650 µA Vin = 2.0 V 200 kΩ 10 pF Fc = 1 MHz TA = 25°C µA VCC = 2.0 V to 5.5 V(3) RRST RST Pulldown Resistor CIO Capacitance of I/O Buffer IPD Power Down Current 50 90 (5) 20 (5) 10 ICC under RESET ICC operating Power Supply Current Maximum values, X1 mode: (7) Power Supply Current Maximum values, X1 mode: (7) Rev. C - 06 March, 2001 (5) 50 30 1 + 0.2 Freq (MHz) @12MHz 3.4 @16MHz 4.2 1 + 0.3 Freq (MHz) @12MHz 4.6 @16MHz 5.8 VCC = 2.0 V to 3.3 V(3) VCC = 3.3 V(1) mA VCC = 3.3 V(8) mA 59 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Symbol ICC idle Parameter Min Typ Power Supply Current Maximum values, X1 mode: (7) Max 0.15 Freq (MHz) + 0.2 @12MHz 2 @16MHz 2.6 Unit mA Test Conditions VCC = 3.3 V(2) NOTES 1. ICC under reset is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 24.), VIL = VSS + 0.5 V, VIH = VCC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used.. 2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, VIL = VSS + 0.5 V, VIH = VCC - 0.5 V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 22.). 3. Power Down ICC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Figure 23.). 4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary. 5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V. 6. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1, 2, 3 and 4 and 5 when available: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 7. For other values, please contact your sales office. 8. Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 24.), VIL = VSS + 0.5 V, VIH = VCC - 0.5V; XTAL2 N.C.; EA = Port 0 = VCC; RST = VSS. The internal ROM runs the code 80 FE (label: SJMP label). ICC would be slightly higher if a crystal oscillator is used. Measurements are made with OTP products when possible, which is the worst case. VCC ICC VCC P0 VCC RST (NC) CLOCK SIGNAL VCC EA XTAL2 XTAL1 VSS All other pins are disconnected. Figure 20. ICC Test Condition, under reset 60 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 VCC ICC VCC VCC P0 Reset = Vss after a high pulse during at least 24 clock cycles RST EA XTAL2 XTAL1 (NC) CLOCK SIGNAL All other pins are disconnected. VSS Figure 21. Operating ICC Test Condition VCC ICC VCC VCC P0 Reset = Vss after a high pulse during at least 24 clock cycles RST EA XTAL2 XTAL1 VSS (NC) CLOCK SIGNAL All other pins are disconnected. Figure 22. ICC Test Condition, Idle Mode VCC ICC VCC P0 Reset = Vss after a high pulse during at least 24 clock cycles RST (NC) VCC EA XTAL2 XTAL1 VSS All other pins are disconnected. Figure 23. ICC Test Condition, Power-Down Mode VCC-0.5V 0.45V TCLCH TCHCL TCLCH = TCHCL = 5ns. 0.7VCC 0.2VCC-0.1 Figure 24. Clock Signal Waveform for ICC Tests in Active and Idle Modes Rev. C - 06 March, 2001 61 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 10.5. AC Parameters 10.5.1. Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. Example:TAVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low. TA TA TA TA = = = = 0 to +70°C (commercial temperature range); VSS = -40°C to +85°C (industrial temperature range); VSS 0 to +70°C (commercial temperature range); VSS = -40°C to +85°C (industrial temperature range); VSS 0 V; VCC = 5 V ± 10%; -M and -V ranges. = 0 V; VCC = 5 V ± 10%; -M and -V ranges. 0 V; 2.7 V < VCC < 5.5 V; -L range. = 0 V; 2.7 V < VCC < 5.5 V; -L range. Table 34. gives the maximum applicable load capacitance for Port 0, Port 1, 2 and 3, and ALE and PSEN signals. Timings will be guaranteed if these capacitances are respected. Higher capacitance values can be used, but timings will then be degraded. Table 34. Load Capacitance versus speed range, in pF Port 0 Port 1, 2, 3 ALE / PSEN -M -V -L 100 80 100 50 50 30 100 80 100 Table 36., Table 39. and Table 42. give the description of each AC symbols. Table 37., Table 40. and Table 43. give for each range the AC parameter. Table 38., Table 41. and Table 44. give the frequency derating formula of the AC parameter. To calculate each AC symbols, take the x value corresponding to the speed grade you need (-M, -V or -L) and replace this value in the formula. Values of the frequency must be limited to the corresponding speed grade: Table 35. Max frequency for derating formula regarding the speed grade Freq (MHz) T (ns) -M X1 mode -M X2 mode -V X1 mode -V X2 mode -L X1 mode -L X2 mode 40 25 20 50 40 25 30 33.3 30 33.3 20 50 Example: TLLIV in X2 mode for a -V part at 20 MHz (T = 1/20E6 = 50 ns): x= 22 (Table 38.) T= 50ns TLLIV= 2T - x = 2 x 50 - 22 = 78ns 62 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 10.5.2. External Program Memory Characteristics Table 36. Symbol Description Symbol T Parameter Oscillator clock period TLHLL ALE pulse width TAVLL Address Valid to ALE TLLAX Address Hold After ALE TLLIV ALE to Valid Instruction In TLLPL ALE to PSEN TPLPH PSEN Pulse Width TPLIV PSEN to Valid Instruction In TPXIX Input Instruction Hold After PSEN TPXIZ Input Instruction FloatAfter PSEN TPXAV PSEN to Address Valid TAVIV Address to Valid Instruction In TPLAZ PSEN Low to Address Float Table 37. AC Parameters for Fix Clock Speed -M 40 MHz Min Min Min Min Units 25 33 25 50 33 ns TLHLL 40 25 42 35 52 ns TAVLL 10 4 12 5 13 ns TLLAX 10 4 12 5 13 ns 78 Max -L standard mode 30 MHz T 45 Max -L X2 mode 20 MHz 40 MHz equiv. Min 70 Max -V standard mode 40 MHz Symbol TLLIV Max -V X2 mode 30 MHz 60 MHz equiv. 65 Max 98 ns TLLPL 15 9 17 10 18 ns TPLPH 55 35 60 50 75 ns TPLIV TPXIX 35 0 25 0 50 0 30 0 55 0 ns ns TPXIZ 18 12 20 10 18 ns TAVIV 85 53 95 80 122 ns TPLAZ 10 10 10 10 10 ns Rev. C - 06 March, 2001 63 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Table 38. AC Parameters for a Variable Clock: derating formula Symbol Type Standard Clock X2 Clock -M -V -L Units TLHLL Min 2T-x T-x 10 8 15 ns TAVLL Min T-x 0.5 T - x 15 13 20 ns TLLAX Min T-x 0.5 T - x 15 13 20 ns TLLIV Max 4T-x 2T-x 30 22 35 ns TLLPL Min T-x 0.5 T - x 10 8 15 ns TPLPH Min 3T-x 1.5 T - x 20 15 25 ns TPLIV Max 3T-x 1.5 T - x 40 25 45 ns TPXIX Min x x 0 0 0 ns TPXIZ Max T-x 0.5 T - x 7 5 15 ns TAVIV Max 5T-x 2.5 T - x 40 30 45 ns TPLAZ Max x x 10 10 10 ns 10.5.3. External Program Memory Read Cycle 12 TCLCL TLHLL TLLIV ALE TLLPL TPLPH PSEN TLLAX TAVLL PORT 0 INSTR IN TPLIV TPLAZ A0-A7 TPXAV TPXIZ TPXIX INSTR IN A0-A7 INSTR IN TAVIV PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 ADDRESS A8-A15 Figure 25. External Program Memory Read Cycle 64 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 10.5.4. External Data Memory Characteristics Table 39. Symbol Description Symbol Parameter TRLRH RD Pulse Width TWLWH WR Pulse Width TRLDV RD to Valid Data In TRHDX Data Hold After RD TRHDZ Data Float After RD TLLDV ALE to Valid Data In TAVDV Address to Valid Data In TLLWL ALE to WR or RD TAVWL Address to WR or RD TQVWX Data Valid to WR Transition TQVWH Data set-up to WR High TWHQX Data Hold After WR TRLAZ RD Low to Address Float TWHLH RD or WR High to ALE high Rev. C - 06 March, 2001 65 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Table 40. AC Parameters for a Fix Clock Speed -M 40 MHz 85 135 125 175 ns TWLWH 130 85 135 125 175 ns 0 Min 102 0 Max Min 95 0 Max 137 0 ns ns TRHDZ 30 18 35 25 42 ns TLLDV 160 98 165 155 222 ns TAVDV 165 100 175 160 235 ns 130 ns TLLWL 50 TAVWL 75 47 80 70 103 ns TQVWX 10 7 15 5 13 ns TQVWH 160 107 165 155 213 ns TWHQX 15 9 17 10 18 ns TRLAZ TWHLH 66 60 Max Units 130 0 Min -L standard mode 30 MHz TRLRH 100 Max -L X2 mode 20 MHz 40 MHz equiv. Min TRHDX Min -V standard mode 40 MHz Symbol TRLDV Max -V X2 mode 30 MHz 60 MHz equiv. 100 30 0 10 40 70 55 0 7 27 95 45 0 15 35 105 70 0 5 45 13 0 ns 53 ns Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Table 41. AC Parameters for a Variable Clock: derating formula Symbol Type Standard Clock X2 Clock -M -V -L Units TRLRH Min 6T-x 3T-x 20 15 25 ns TWLWH Min 6T-x 3T-x 20 15 25 ns TRLDV Max 5T-x 2.5 T - x 25 23 30 ns TRHDX Min x x 0 0 0 ns TRHDZ Max 2T-x T-x 20 15 25 ns TLLDV Max 8T-x 4T -x 40 35 45 ns TAVDV Max 9T-x 4.5 T - x 60 50 65 ns TLLWL Min 3T-x 1.5 T - x 25 20 30 ns TLLWL Max 3T+x 1.5 T + x 25 20 30 ns TAVWL Min 4T-x 2T-x 25 20 30 ns TQVWX Min T-x 0.5 T - x 15 10 20 ns TQVWH Min 7T-x 3.5 T - x 15 10 20 ns TWHQX Min T-x 0.5 T - x 10 8 15 ns TRLAZ Max x x 0 0 0 ns TWHLH Min T-x 0.5 T - x 15 10 20 ns TWHLH Max T+x 0.5 T + x 15 10 20 ns 10.5.5. External Data Memory Write Cycle TWHLH ALE PSEN TLLWL TWLWH WR TLLAX PORT 0 A0-A7 TQVWX TQVWH TWHQX DATA OUT TAVWL PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 OR SFR P2 Figure 26. External Data Memory Write Cycle Rev. C - 06 March, 2001 67 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 10.5.6. External Data Memory Read Cycle TWHLH TLLDV ALE PSEN TLLWL TRLRH TRLDV RD TLLAX PORT 0 TRHDZ TAVDV TRHDX A0-A7 DATA IN TRLAZ TAVWL ADDRESS OR SFR-P2 PORT 2 ADDRESS A8-A15 OR SFR P2 Figure 27. External Data Memory Read Cycle 10.5.7. Serial Port Timing - Shift Register Mode Table 42. Symbol Description Symbol Parameter TXLXL Serial port clock cycle time TQVHX Output data set-up to clock rising edge TXHQX Output data hold after clock rising edge TXHDX Input data hold after clock rising edge TXHDV Clock rising edge to input data valid Table 43. AC Parameters for a Fix Clock Speed Max -V X2 mode 30 MHz 60 MHz equiv. Max Max Max 200 300 300 400 ns TQVHX 200 117 200 200 283 ns TXHQX 30 13 30 30 47 ns TXHDX 0 0 0 0 0 ns 117 Min Units 300 117 Min -L standard mode 30 MHz TXLXL 34 Min -L X2 mode 20 MHz 40 MHz equiv. Min 117 Min -V standard mode 40 MHz Symbol TXHDV 68 -M 40 MHz Max 200 ns Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Table 44. AC Parameters for a Variable Clock: derating formula -M -V Units Symbol Type Standard Clock X2 Clock -L TXLXL Min 12 T 6T TQVHX Min 10 T - x 5T-x 50 50 50 ns TXHQX Min 2T-x T-x 20 20 20 ns TXHDX Min x x 0 0 0 ns TXHDV Max 10 T - x 5 T- x 133 133 133 ns ns 10.5.8. Shift Register Timing Waveforms 0 INSTRUCTION 1 2 3 4 5 6 7 8 ALE TXLXL CLOCK TXHQX TQVXH OUTPUT DATA 0 WRITE to SBUF TXHDV INPUT DATA 1 2 3 4 5 6 7 TXHDX VALID VALID VALID SET TI VALID VALID VALID VALID VALID SET RI CLEAR RI Figure 28. Shift Register Timing Waveforms Rev. C - 06 March, 2001 69 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 10.5.9. EPROM Programming and Verification Characteristics TA = 21°C to 27°C; VSS = 0V; VCC = 5V ± 10% while programming. VCC = operating range while verifying Table 45. EPROM Programming Parameters Symbol Parameter VPP Programming Supply Voltage IPP Programming Supply Current 1/TCLCL Min Max Units 12.5 13 V 75 mA 6 MHz Oscillator Frquency 4 TAVGL Address Setup to PROG Low 48 TCLCL TGHAX Adress Hold after PROG 48 TCLCL TDVGL Data Setup to PROG Low 48 TCLCL TGHDX Data Hold after PROG 48 TCLCL TEHSH (Enable) High to VPP 48 TCLCL TSHGL VPP Setup to PROG Low 10 µs TGHSL VPP Hold after PROG 10 µs TGLGH PROG Width 90 TAVQV Address to Valid Data 48 TCLCL TELQV ENABLE Low to Data Valid 48 TCLCL TEHQZ Data Float after ENABLE 0 µs 110 48 TCLCL 10.5.10. EPROM Programming and Verification Waveforms PROGRAMMING VERIFICATION ADDRESS ADDRESS P1.0-P1.7 P2.0-P2.5 P3.4-P3.5* TAVQV P0 DATA OUT DATA IN TGHDX TGHAX TDVGL TAVGL ALE/PROG TSHGL TGLGH EA/VPP CONTROL SIGNALS (ENABLE) TGHSL VPP VCC TEHSH VCC TELQV TEHQZ * 8KB: up to P2.4, 16KB: up to P2.5, 32KB: up to P3.4, 64KB: up to P3.5 Figure 29. EPROM Programming and Verification Waveforms 70 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 10.5.11. External Clock Drive Characteristics (XTAL1) Table 46. AC Parameters Symbol Parameter Min Max Units TCLCL Oscillator Period 25 ns TCHCX High Time 5 ns TCLCX Low Time 5 ns TCLCH Rise Time 5 ns TCHCL Fall Time 5 ns 60 % TCHCX/TCLCX Cyclic ratio in X2 mode 40 10.5.12. External Clock Drive Waveforms VCC-0.5 V 0.45 V 0.7VCC 0.2VCC-0.1 V TCHCL TCHCX TCLCH TCLCX TCLCL Figure 30. External Clock Drive Waveforms 10.5.13. AC Testing Input/Output Waveforms VCC-0.5 V INPUT/OUTPUT 0.2VCC+0.9 0.2VCC-0.1 0.45 V Figure 31. AC Testing Input/Output Waveforms AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”. 10.5.14. Float Waveforms FLOAT VOH-0.1 V VLOAD VOL+0.1 V VLOAD+0.1 V VLOAD-0.1 V Figure 32. Float Waveforms Rev. C - 06 March, 2001 71 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH ≥ ± 20mA. 10.5.15. Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by two. STATE4 INTERNAL CLOCK P1 P2 STATE5 STATE6 STATE1 STATE2 P1 P1 P1 P1 P2 P2 P2 P2 STATE3 P1 P2 STATE4 P1 P2 STATE5 P1 P2 XTAL2 ALE THESE SIGNALS ARE NOT ACTIVATED DURING THE EXECUTION OF A MOVX INSTRUCTION EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED PCL OUT DATA SAMPLED FLOAT P2 (EXT) PCL OUT DATA SAMPLED PCL OUT FLOAT FLOAT INDICATES ADDRESS TRANSITIONS READ CYCLE RD PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) P0 DPL OR Rt OUT FLOAT P2 INDICATES DPH OR P2 SFR TO PCH TRANSITION WRITE CYCLE WR P0 PCL OUT (EVEN IF PROGRAM MEMORY IS INTERNAL) DPL OR Rt OUT DATA OUT P2 PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) INDICATES DPH OR P2 SFR TO PCH TRANSITION PORT OPERATION OLD DATA P0 PINS SAMPLED NEW DATA P0 PINS SAMPLED MOV DEST P0 MOV DEST PORT (P1, P2, P3) (INCLUDES INT0, INT1, TO, T1) P1, P2, P3 PINS SAMPLED SERIAL PORT SHIFT CLOCK TXD (MODE 0) RXD SAMPLED P1, P2, P3 PINS SAMPLED RXD SAMPLED Figure 33. Clock Waveforms This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (TA=25°C fully loaded) RD and WR propagation delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. 72 Rev. C - 06 March, 2001 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 11. Ordering Information TS -M 87C51RD2 -M: -V: -L: -E: VCC: 5V +/- 10% 40 MHz, X1 mode 20 MHz, X2 mode VCC: 5V +/- 10% 40 MHz, X1 mode 30 MHz, X2 mode VCC: 2.7 to 5.5 V 30 MHz, X1 mode 20 MHz, X2 mode Samples R B C Packages: A: PDIL 40 B: PLCC 44 E: VQFP 44 (1.4mm) J: Window CDIL 40* K: Window CQPJ 44* L: PLCC68 (RD devices only)* M: VQFP64, square package, 1.4mm (RD devices only)* N: JLCC68 (RD devices only)* Part Number 80C51RA2 (ROMless, 256 bytes XRAM) 80C51RD2 (ROMless, 768bytes XRAM) 83C51RB2zzz (16k ROM, zzz is the customer code) 83C51RC2zzz (32k ROM, zzz is the customer code) 83C51RD2zzz (64k ROM, zzz is the customer code) 87C51RB2 (16k OTP EPROM) 87C51RC2 (32k OTP EPROM) 87C51RD2 (64k OTP EPROM) Temperature Range C: Commercial 0 to 70oC I: Industrial -40 to 85oC Conditioning R: Tape & Reel D: Dry Pack B: Tape & Reel and Dry Pack (*) Check with Atmel Wireless & Microcontrollers Sales Office for availability. Ceramic packages (J, K, N) are available for proto typing, not for volume production. Ceramic packages are available for OTP only. Table 47. Maximum Clock Frequency Code -M -V -L Standard Mode, oscillator frequency Standard Mode, internal frequency X2 Mode, oscillator frequency X2 Mode, internal equivalent frequency 40 40 20 40 40 40 30 60 30 30 20 40 Rev. C - 06 March, 2001 Unit MHz MHz 73 TS80C51RA2/RD2 TS83C51RB2/RC2/RD2 TS87C51RB2/RC2/RD2 Table 48. Possible Ordering Entries TS80C51RA2/RD2 ROMless -MCA -MCB -MCE -MCL -MCM -VCA -VCB -VCE -VCL -VCM -LCA -LCB -LCE -LCL -LCM -MIA -MIB -MIE -MIL -MIM -VIA -VIB -VIE -VIL -VIM -LIA -LIB -LIE -LIL -LIM -EA -EB -EE -EL -EM -EJ -EK -EN TS83C51RB2/RC2/RD2zzz ROM X X X RD2 only RD2 only X X X RD2 only RD2 only X X X RD2 only RD2 only X X X RD2 only RD2 only X X X RD2 only RD2 only X X X RD2 only RD2 only X X X RD2 only RD2 only X X X RD2 only RD2 only X X X RD2 only RD2 only X X X RD2 only RD2 only X X X RD2 only RD2 only X X X RD2 only RD2 only X X X RD2 only RD2 only TS87C51RB2/RC2/RD2 OTP X X X RD2 only RD2 only X X X RD2 only RD2 only X X X RD2 only RD2 only X X X RD2 only RD2 only X X X RD2 only RD2 only X X X RD2 only RD2 only X X X RD2 only RD2 only RC2 and RD2 only RC2 and RD2 only RD2 only • -Ex for samples • Tape and Reel available for B, E, L and M packages • Dry pack mandatory for E and M packages 74 Rev. C - 06 March, 2001