UPD1002
USB Power Delivery Controller
Highlights
Key Benefits
•
•
•
•
•
•
•
• Integrated USB Power Delivery (PD) PHY
Integrated USB Power Delivery (PD) PHY
Support for Power Delivery Message Protocol
Integrated Voltage and Current ADC Inputs
Configuration Profile Selection
On-chip Microcontroller
SPI Interface
Commercial and Industrial Grade Temperature
Support
• Available in 32-SQFN Package
Target Applications
•
•
•
•
•
•
Notebooks
Ultrabooks
Desktop PCs
Docking Stations
Monitors
Printers
- Integrated receive termination
- Requires minimal external components
• Support for Power Delivery Message Protocol
-
Message Generation/Consumption
Retry Generation
Error Handling
State Behavior
• Cable Detect Logic
- Cable attachment type
• CFG_SEL pins allow selection of multiple profiles
-
Provider
Provider/Consumer
Consumer
Consumer/Provider
• Integrated Voltage (VMON) and Current (IMON)
ADC Inputs
• Dead Battery Support
• On-chip Microcontroller
- Manages I/Os and other signals
- Implements power delivery policy engine and
device policy manager
• Configuration Programming via OTP, or Vendor
Defined Messaging
• Supports Low Power Modes
• Serial Peripheral Interface (SPI) Bus
• Internal 3.3 V and 1.8 V Voltage Regulators
• Integrated Oscillator Reduces BOM Costs
• Package
- 32-pin SQFN (5 x 5 mm)
• Environmental
- Commercial temperature range (0°C to +70°C)
- Industrial temperature range (-40°C to +85°C
2014 Microchip Technology Inc.
DS00001760B-page 1
UPD1002
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Documentation
To obtain the most up-to-date version of this documentation, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the
revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are
using.
Customer Notification System
Register on our web site at www.microchip.com to receive the most current information on all of our products.
DS00001760B-page 2
2014 Microchip Technology Inc.
UPD1002
Table of Contents
1.0 Introduction ..................................................................................................................................................................................... 4
2.0 Pin Descriptions and Configuration ................................................................................................................................................. 7
3.0 Functional Descriptions ................................................................................................................................................................. 23
4.0 Operational Characteristics ........................................................................................................................................................... 37
5.0 Package Outline ............................................................................................................................................................................ 41
6.0 Revision History ............................................................................................................................................................................ 42
The Microchip Web Site ...................................................................................................................................................................... 43
Customer Change Notification Service ............................................................................................................................................... 43
Customer Support ............................................................................................................................................................................... 43
Product Identification System ............................................................................................................................................................. 44
2014 Microchip Technology Inc.
DS00001760B-page 3
UPD1002
1.0
INTRODUCTION
1.1
General Description
The UPD1002 is a USB Power Delivery (PD) controller designed to adhere to the USB Power Delivery Specification.
USB Power Delivery allows a host (or device) to provide or consume up to 5 Amps and/or up to 20 Volts of power from
a USB PD capable partner device on the other end of the USB cable. USB PD capable standard and custom cables/
connectors are supported, which in most cases are backward compatible with standard USB connections.
The UPD1002 provides a complete USB Power Delivery solution for notebooks/ultrabooks, desktop PCs, monitors, and
docking stations, (see Table 1-1, “UPD1002 Package/Pin Configuration Summary,” on page 6 for available configurations and corresponding applications). The functionality of the UPD1002 is selected via two configuration selection pins,
CFG_SEL0 and CFG_SEL1, which can be used to select unique PD and system configurations. Designing the
UPD1002 into a system can be as simple as selecting a configuration, with no external EEPROM required. Advanced
programmability options exist with an external EEPROM installed.
The integrated USB Power Delivery MAC and PHY support provider and consumer operation via the PD communication
protocol, as specified in Revision 1.0 (Version 1.2) of the USB Power Delivery Specification. Monitoring of VBUS and
battery charging is accomplished via the integrated voltage and current ADC inputs. The PHY supports cable ID detection/identification and loopback modes. The PHY includes a 24MHz FSK modulator/demodulator and provides integrated terminations. The USB PD MAC supports both USB PD insertion detection (cold socket) and dead battery cases.
The device provides an integrated voltage switch which is used to detect whether the VBUS or VTR (battery) power
supply is active, enabling selection of the appropriate power supply at any given time.
The on-chip microcontroller manages the IOs and implements the power delivery local policy engine and device manager. The SPI ROM controller is used by the microcontroller for optional external code execution from ROM. A One Time
Programmable (OTP) ROM is integrated in the UPD1002. Integrated 3.3 V and 1.8 V regulators allow device operation
from a single power supply. The UPD1002 is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C)
temperature ranges. An internal block diagram of the UPD1002 is shown in Figure 1-1.
Power Delivery applications introduce two different types of USB ports. The Upstream Facing Port (UFP) and the Downstream Facing Port (DFP). The UFP and DFP have different usages and attributes due to the nature of their use cases,
as detailed below. For a list of available UPD1002 configurations and corresponding target applications, refer to Table 11, “UPD1002 Package/Pin Configuration Summary,” on page 6.
The Upstream Facing Port (UFP)
The primary use case of the UFP is to connect to a host computer. In this case, the UFP of the UPD1002 must have a
Standard-B (STD-B) USB connector to connect to the host’s Standard-A (STD-A) USB connector. If the host is a notebook/ultrabook, it may request to be charged from the UPD1002 UFP, requiring the system to be wall powered instead
of bus-powered. In this case, the UFP must offer a Consumer/Provider role.
The Downstream Facing Port (DFP)
The primary use case of the DFP is to connect to other downstream USB devices such as speakers, keyboard, mice,
scanners, external hard drives, external optical drives, printers, etcetera. These devices are mainly Consumers in
nature in the first phase of adoption. DFPs are Providers by default and have Standard-A USB connectors. Battery
Charging 1.2 support can be provided by a parallel USB hub or a Microchip UCS100x or other enhanced port power
controller device.
DS00001760B-page 4
2014 Microchip Technology Inc.
UPD1002
FIGURE 1-1:
INTERNAL BLOCK DIAGRAM
PD_ID
PD_DATA
Power
Delivery
AFE
Power
Delivery
MAC
VBUS
VTR
VMON
IMON
Voltage
Switch
Microcontroller
SPI ROM
Controller
I/O
Controller†
SPI ROM
I/O
Voltage
Monitor
Current
Monitor
Reset
Controller
Configuration
Select
Clocks
RESET_N
CFG_SEL0
CFG_SEL1
UPD1002
†
Specific I/O functions are determined by package and CFG_SEL0/CFG_SEL1 profile selection.
2014 Microchip Technology Inc.
DS00001760B-page 5
UPD1002
The UPD1002 is offered in a 32-pin SQFN package. The package provides multiple pin configurations, based upon the
CFG_SEL0 and CFG_SEL1 Configuration Select signals. Table 1-1 summarizes the available pin combinations and
their target applications. Refer to Section 2.0, "Pin Descriptions and Configuration," on page 7 for detailed information
on specific pin configurations.
TABLE 1-1:
Package
UPD1002 PACKAGE/PIN CONFIGURATION SUMMARY
Pin Config. DFP/
Name
UFP
PD Role
32-P_A
DFP
Provider
32-CP_B
UFP
32-PC_A
DFP
32-SQFN
32-PC_uAB DFP
DS00001760B-page 6
USB
Receptacle
Standard-A
(STD-A)
Target Applications
•
•
•
•
Notes
Monitors
Docking stations
Desktop PCs
Printers
See Section 2.1
Consumer/Provider Standard-B
(STD-B)
• Monitors
• Docking stations
• Printers
See Section 2.1
Provider/Consumer Standard-A
(STD-A)
• Notebooks
See Section 2.1
No VSELx_N
Provider/Consumer Micro-AB
(uAB)
• Notebooks
• Ultrabooks
See Section 2.1
No VSELx_N
2014 Microchip Technology Inc.
UPD1002
2.0
PIN DESCRIPTIONS AND CONFIGURATION
The pinouts for the package, along with system-level application diagrams, are detailed in the following section:
• 32-Pin SQFN (32-SQFN)
Note:
For a summary of the available pin combinations and their corresponding target applications, refer to
Table 1-1.
Pin descriptions are detailed in Section 2.2, "Pin Descriptions," on page 14. For details on the CFG_SEL0 and CFG_SEL1 Configuration Select signals, refer to Section 3.3, "Configuration Selection (CFG_SEL0/CFG_SEL1)," on
page 24.
32-SQFN PIN DIAGRAM
FAULT_IN_N
FAULT_N
VSEL1_N/USB_ID_IND/NC*
VSEL0_N/VBUS_OUT/NC*
RESET_N
TEST
CHG_EMU_EN/VSAFEDB_EN/
PPC_PWR_EN*
30
29
28
27
26
25
32-SQFN PIN ASSIGNMENTS (TOP VIEW)
31
FIGURE 2-1:
VSEL2_N/VBUS_OUT/
VBUS_DISCHARGE*
2.1.1
32-Pin SQFN (32-SQFN)
32
2.1
CFG_SEL0
1
24
PD_DATA
CFG_SEL1
2
23
PD_ID
PD_EN/PD_GOOD*
3
22
HUB_PWR_EN/VSEL2_N*
VDD33_CAP
4
21
PD_VDD18
20
VDD18_CAP
VBUS
5
VSW_CAP
6
VTR
7
UPD1002
32-SQFN
(Top View)
VSS
19
VDDIO
18
IMON
17
VMON
(Connect exposed pad to ground with a via field)
9
10
11
12
13
14
15
16
SPI_ROM_CLK
SPI_ROM_DO
SPI_ROM_DI
VDDIO
VBUS_DISCHARGE/EXT_PWR_DET*
INSERTION_DETECT/VSEL0_N/NC*
PD_DETECT/VSEL1_N/NC*
8
SPI_ROM_CE_N
VDD18A_CAP
*The functionality of this pin is dependent on the CFG_SEL0/CFG_SEL1 profile selection.
Note: Exposed pad (VSS) on bottom of package must be connected to ground with a via field.
Note:
When an “_N” is used at the end of the signal name, it indicates that the signal is active low. For example,
RESET_N indicates that the reset signal is active low.
2014 Microchip Technology Inc.
DS00001760B-page 7
UPD1002
Note:
2.1.2
The buffer type for each signal is indicated in the BUFFER TYPE column of Table 2-2, "Pin Descriptions".
A description of the buffer types is provided in Section 2.3, "Buffer Types".
32-SQFN PIN ASSIGNMENTS
The UPD1002 32-SQFN provides four distinct pin configurations (32-P_A, 32-CP_B, 32-PC_A, and 32-PC_uAB) based
upon the CFG_SEL0 and CFG_SEL1 Configuration Select signals. These configurations are designed for specific applications, as outlined in Table 1-1, “UPD1002 Package/Pin Configuration Summary,” on page 6. The 32-SQFN package
pin assignments for each configuration are detailed in Table 2-1. For pin descriptions, refer to Section 2.2, "Pin Descriptions". For example connection diagrams, refer to Section 2.4, "Power Connection Diagram," on page 22. For information on the Configuration Select signals, refer to Section 3.3, "Configuration Selection (CFG_SEL0/CFG_SEL1)".
TABLE 2-1:
Pin
Number
32-SQFN PACKAGE PIN ASSIGNMENTS
Configuration
32-P_A
Pin Name
Configuration
32-CP_B
Pin Name
1
CFG_SEL0
2
CFG_SEL1
3
PD_EN
Configuration
32-PC_A
Pin Name
Configuration
32-PC_uAB
Pin Name
PD_GOOD
PD_GOOD
PD_EN
4
VDD33_CAP
5
VBUS
6
VSW_CAP
7
VTR
8
VDD18A_CAP
9
SPI_ROM_CE_N
10
SPI_ROM_CLK
11
SPI_ROM_DO
12
SPI_ROM_DI
13
VDDIO
14
VBUS_DISCHARGE
VBUS_DISCHARGE
EXT_PWR_DET
EXT_PWR_DET
15
INSERTION_DETECT
VSEL0_N
INSERTION_DETECT
NC
16
PD_DETECT
VSEL1_N
PD_DETECT
NC
17
VMON
18
IMON
19
VDDIO
20
VDD18_CAP
21
PD_VDD18
22
HUB_PWR_EN
VSEL2_N
23
PD_ID
24
PD_DATA
25
CHG_EMU_EN
VSAFEDB_EN
26
TEST
27
RESET_N
DS00001760B-page 8
HUB_PWR_EN
HUB_PWR_EN
PPC_PWR_EN
PPC_PWR_EN
2014 Microchip Technology Inc.
UPD1002
TABLE 2-1:
32-SQFN PACKAGE PIN ASSIGNMENTS (CONTINUED)
Pin
Number
Configuration
32-P_A
Pin Name
Configuration
32-CP_B
Pin Name
Configuration
32-PC_A
Pin Name
Configuration
32-PC_uAB
Pin Name
28
VSEL0_N
NC
NC
VBUS_OUT
29
VSEL1_N
NC
NC
USB_ID_IND
VBUS_DISCHARGE
VBUS_DISCHARGE
30
FAULT_N
31
FAULT_IN_N
32
VSEL2_N
Exposed
Pad
2014 Microchip Technology Inc.
VBUS_OUT
VSS
DS00001760B-page 9
UPD1002
2.1.3
32-SQFN SYSTEM LEVEL DIAGRAMS
Figure 2-2, Figure 2-3, Figure 2-4, and Figure 2-5 provide typical system level diagrams of the UPD1002 for configurations 32-P_A, 32-CP_B, 32-PC_A, and 32-PC_uAB, respectively.
FIGURE 2-2:
CONFIGURATION 32-P_A SYSTEM-LEVEL DIAGRAM
System Power
Standard
24V AC
Adapter
FAULT_IN_N
VDDIO
CFG_SEL0
VSEL0_N
DC-to-DC
Power
Regulator
VSEL1_N
VDDIO
CFG_SEL1
VSEL2_N
PD_EN
VDDIO
FAULT_N
Microchip
UPD1002
32-SQFN
To SPI ROM
SPI_ROM_CLK
35.7k
VMON
5.1k
Filter
Cap
VBUS
IMON
5V
CSA
Configuration
32-P_A
SPI_ROM_CE_N
VBUS_DISCHARGE
SPI_ROM_DI
PD_ID
PD_DATA
SPI_ROM_DO
Couple/Filter
PD_DETECT
VDDIO
CHG_EMU_EN
VBUS
PD_DETECT 1
INSERTION_DETECT
INSERTION_DETECT 2
HUB_PWR_EN
INSERTION_DETECT 1
VSS
SHIELD
FAULT_IN_N
D+
USB Hub
with BC1.2
USB
Power
Delivery
Enabled
Standard-A
Receptacle
D-
GND
DS00001760B-page 10
2014 Microchip Technology Inc.
UPD1002
FIGURE 2-3:
CONFIGURATION 32-CP_B SYSTEM-LEVEL DIAGRAM
System Power
FAULT_IN_N
VDDIO
CFG_SEL0
Filter
Cap
Bank
VSEL0_N
DC-to-DC
Power
Regulator
VSEL1_N
VDDIO
CFG_SEL1
VSEL2_N
VDDIO
Dead
Battery
Standard
24V AC
Adapter
VSAFEDB_EN
PD_EN
FAULT_N
Microchip
UPD1002
32-SQFN
To SPI ROM
SPI_ROM_CLK
VMON
35.7k
5.1k
VBUS
IMON
5V
CSA
Configuration
32-CP_B
SPI_ROM_CE_N
VBUS_DISCHARGE
SPI_ROM_DI
SPI_ROM_DO
PD_DATA
Couple/Filter
PD_ID
VDDIO
VBUS
ID
D+
VBUS_OUT
VSAFEDB_EN
VSS
2014 Microchip Technology Inc.
USB Hub
with BC1.2
USB
Power
Delivery
Enabled
Standard-B
Receptacle
D-
GND
DS00001760B-page 11
UPD1002
FIGURE 2-4:
CONFIGURATION 32-PC_A SYSTEM-LEVEL DIAGRAM
System Power
Battery
Battery Charger
Rsense
Standard
20V AC
Adapter
VDDIO
EXT_PWR_DET
CFG_SEL0
PD_GOOD
VDDIO
CFG_SEL1
PPC_PWR_EN
VDDIO
FAULT_N
Microchip
UPD1002
32-SQFN
To SPI ROM
SPI_ROM_CLK
SPI_ROM_CE_N
Port
Power
Controller
FAULT_IN_N
Configuration
32-PC_A
SPI_ROM_DI
Filter
Cap
Bank
VBUS_DISCHARGE
35.7k
VMON
5.1k
VBUS
IMON
5V
CSA
PD_ID
SPI_ROM_DO
PD_DATA
VDDIO
Couple/Filter
PD_DETECT
VBUS
PD_DETECT 1
INSERTION_DETECT
INSERTION_DETECT 2
HUB_PWR_EN
INSERTION_DETECT 1
VSS
SHIELD
D+
FAULT_IN_N
USB Hub
with BC1.2
USB
Power
Delivery
Enabled
Standard-A
Receptacle
D-
GND
DS00001760B-page 12
2014 Microchip Technology Inc.
UPD1002
FIGURE 2-5:
CONFIGURATION 32-PC_UAB SYSTEM-LEVEL DIAGRAM
System Power
Battery
Battery Charger
Rsense
Standard
20V AC
Adapter
EXT_PWR_DET
VDDIO
CFG_SEL0
PD_GOOD
CFG_SEL1
PPC_PWR_EN
VDDIO
VDDIO
FAULT_N
Microchip
UPD1002
32-SQFN
USB_ID_IND
Configuration
32-PC_uAB
SPI_ROM_CE_N
35.7k
VMON
5.1k
VBUS
IMON
5V
CSA
Couple/Filter
PD_ID
SPI_ROM_DI
VBUS
ID
HUB_PWR_EN
SPI_ROM_DO
VDDIO
VBUS_DISCHARGE
PD_DATA
SPI_ROM_CLK
To SPI ROM
Port
Power
Controller
FAULT_IN_N
Filter
Cap
Bank
VBUS_OUT
VSS
D+
FAULT_IN_N
USB Hub
with BC1.2
USB
Power
Delivery
Enabled
Micro-AB
Receptacle
DGND
2014 Microchip Technology Inc.
DS00001760B-page 13
UPD1002
2.2
Pin Descriptions
TABLE 2-2:
PIN DESCRIPTIONS
Name
Symbol
Buffer
Type
Description
Power Delivery
Power Delivery Cable ID
PD_ID
AIO
USB connector signal used to indicate a high-current
power delivery capable cable is inserted. This signal is to
be connected to the PD_ID pin located on the USB PD
Standard-B receptacle.
Power Delivery VBUS Data
PD_DATA
AIO
Modulated power delivery VBUS data. Requires in-line
isolation filter. Reference schematic available on request.
Power Delivery Detect
PD_DETECT
IS
(PU)
This signal is to be connected to the PD DETECT pins
located on the USB PD Standard-A receptacle. This signal is pulled high via an internal pull-up resistor by
default. Assertion (low value) of PD_DETECT qualifies a
USB-PD plug detection event.
Power
Delivery
Enable
(Active High)
PD_EN
O8
This active high signal is used to drive the enable pin of
the DC-to-DC solution direction directly. Alternatively, this
signal may be used to drive an N-channel MOSFET into
cuttoff and isolate the input power of the DC-to-DC solution.
Note:
Power
Delivery Good
PD_GOOD
O8
This function is only available in specific
device configurations.
This active high signal is asserted whenever a valid USB
power delivery contract has been established and the
device is operating as a sink in a configuration other than
VSafe5V-0A. A valid contract is defined as a PD contract
that matches one of the supported PD consumer/provider
profiles, as determined by the CFG_SEL0/CFG_SEL1
configuration. When there is no valid contract established, this signal de-asserts.
Note:
This signal will not be asserted, or become deasserted, if the VBUS voltage is not within the
desired range, as determined by the VMON
voltage monitoring (despite a contract being
established).
Note:
This function is only available in specific
device configurations.
Miscellaneous
VBUS Voltage
Monitor
DS00001760B-page 14
VMON
AI
Stepped down voltage representation of the VBUS voltage. This signal must be connected to a voltage divider
circuit as specified in Section 2.4, "Power Connection
Diagram," on page 22. Voltage must not exceed 5 V on
this signal. Refer to Section 3.4, "Voltage/Current Monitors (VMON/IMON)," on page 29 for additional information.
2014 Microchip Technology Inc.
UPD1002
TABLE 2-2:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
Charger Current Monitor
IMON
AI
Voltage representation of the charger current. This signal
should be fed by a current sense amplifier tuned to output
3.0 V when 6.0 A is flowing on VBUS. Voltage must not
exceed 5 V on this signal. Refer to Section 3.4, "Voltage/
Current Monitors (VMON/IMON)," on page 29 for additional information.
Power Supply
Fault Indicator
FAULT_N
OD8
This active low signal can be connected to an external
LED or SoC and is used by the device to indicate power
supply exceptions/failures as determined by the integrated voltage/current monitors. Refer to Section 3.4,
"Voltage/Current Monitors (VMON/IMON)," on page 29
for additional information.
Fault Input
FAULT_IN_N
IS
This active low signal is asserted by the power supplying
device (DC to DC controller or port power controller) to
notify the device when a system fault condition has
occurred. Typically, this signal is used for overcurrent or
overvoltage conditions, but it can be used for any system
related failure. This signal should be debounced to 1 ms.
Description
Note:
The board design must ensure this signal is in
a valid state by the time PPC_PWR_EN or
PD_GOOD asserts.
Power Delivery Profile
Configuration
Selector 0
CFG_SEL0
AIO
This pin is used in conjunction with CFG_SEL1 to select
the power delivery profile of the device via an externally
connected RC circuit. Refer to Section 3.3, "Configuration
Selection (CFG_SEL0/CFG_SEL1)" for additional information.
Power Delivery Profile
Configuration
Selector 1
CFG_SEL1
AIO
This pin is used in conjunction with CFG_SEL0 to select
the power delivery profile of the device via an externally
connected RC circuit. Refer to Section 3.3, "Configuration
Selection (CFG_SEL0/CFG_SEL1)" for additional information.
2014 Microchip Technology Inc.
DS00001760B-page 15
UPD1002
TABLE 2-2:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
Source
Voltage
Select 0
VSEL0_N
OD8
Description
This active low signal is one in a series of output pins
(VSEL0_N, VSEL1_N, and VSEL2_N) used to select the
correct source voltage from the DC-to-DC solution. Each
VSELx_N pin is dedicated to one voltage, assigned in
order of increasing supported voltage.
For example, if 5, 12 and 20 V capabilities are supported,
the VSELx_N selections will be as follows:
VSEL0_N = 5 V
VSEL1_N = 12 V
VSEL2_N = 20 V
In another example, if only 5 and 20 V care supported,
the VSELx_N selections will be as follows:
VSEL0_N = 5 V
VSEL1_N = 20 V
VSEL2_N = RESERVED
The VSELx_N pins are also used to set the overvoltage
protection (OVP) voltage on the VMON pin. The OVP
fault will trigger when the measured voltage on VMON is
10% above the selected voltage setting.
For a mapping of the VSELx_N voltage assignments for
each CFG_SEL1/CFG_SEL0 configuration profile, refer
to Section 3.3, "Configuration Selection (CFG_SEL0/
CFG_SEL1)," on page 24.
Note:
Source
Voltage
Select 1
VSEL1_N
OD8
This function is only available in specific
device configurations.
This active low signal is one in a series of output pins
(VSEL0_N, VSEL1_N, and VSEL2_N) used to select the
correct source voltage from the DC-to-DC solution. Each
VSELx_N pin is dedicated to one voltage, assigned in
order of increasing supported voltage.
Refer to the VSEL0_N definition for additional information.
Note:
Source
Voltage
Select 2
VSEL2_N
OD8
This function is only available in specific
device configurations.
This active low signal is one in a series of output pins
(VSEL0_N, VSEL1_N, and VSEL2_N) used to select the
correct source voltage from the DC-to-DC solution. Each
VSELx_N pin is dedicated to one voltage, assigned in
order of increasing supported voltage.
Refer to the VSEL0_N definition for additional information.
Note:
DS00001760B-page 16
This function is only available in specific
device configurations.
2014 Microchip Technology Inc.
UPD1002
TABLE 2-2:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
VBUS
Discharge
VBUS_DISCHARGE
O8
This active high output is used to drive a power NFET to
discharge VBUS during high-to-low voltage transitions in
order to achieve vSafe0V. When asserted, the external
MOSFET should conduct to GND through a current limiting resistor. This signal de-asserts when the VMON signal voltage reaches a preset value (a percentage of the
destination voltage).
VBUS
Out
VBUS_OUT
O8
This active high output is used on an Upstream Facing
Port (UFP) to tell the hub to stay connected. This signal
will remain asserted at all times that a valid VBUS level is
present (VBUS minimum of 4.5 V to PD VBUS maximum
20 V+10%) on the UFP, as well as during any voltage
transitions or role swaps where the voltage may drop
below 4.5V.
Description
Note:
Per the OTG specification, data connectivity
roles can be swapped and a micro-AB connector with a micro-A plug inserted can operate as an “upstream” port (as a device).
Therefore, VBUS_OUT assertion behavior as
per above is not only valid with a micro-B
cable, but also a micro-A cable so that the
USB data link is not lost during PD swaps.
Note:
This function is only available in specific
device configurations.
USB ID
Indicator
USB_ID_IND
O8
This signal is used in micro-AB pinouts to indicate to the
OTG host whether a micro-A plug (Legacy, Low Power or
PD) is present. If a micro-A plug is present, this pin is low.
Otherwise it is high.
Emulation
Enable
CHG_EMU_EN
O8
This active high output signal can be used to drive the
Emulation Enable pin of a Microchip UCS1001 or similar
device that supports BC 1.2. The device will assert this
signal whenever operating at VSafe5V without a PD contract. Whenever a PD contract is established (even at
5 V), this signal is de-asserted.
Note:
2014 Microchip Technology Inc.
This function is only available in specific
device configurations.
DS00001760B-page 17
UPD1002
TABLE 2-2:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Insertion
Detect
INSERTION_DETECT
Dead Battery
Enable
VSAFEDB_EN
Buffer
Type
IS
(PU)
O8
Description
This active low input signal should be connected to the
Insertion Detect pin on the USB Standard-A (STD-A)
receptacle. This signal is pulled high via an internal pullup resistor by default. Assertion (low value) qualifies a
STD-A plug insertion event and triggers transition out of
the “Startup” state of the Source Policy engine.
The device firmware implements cold socket detection
using the INSERTION_DETECT signal. Even when
operating as a provider, if the signal is high, the device
will not output voltage on VBUS. VSafe5V will only be
output upon assertion of this signal (low).
Note:
Cold socket (insertion detect) is an optional
feature in the USB PD specification. If this feature is not being used in a design, the INSERTION_DETECT signal must be grounded.
Note:
This function is only available in specific
device configurations.
This active high output signal is used to enable the dead
battery supply on a USB Standard-B (STD-B) receptacle
(consumer/provider) AC adapter. When no voltage has
been detected on VBUS, this signal is asserted every
10 s to back power an attached provider/consumer and
determine whether the attached device has specified to
be powered per the dead battery mechanisms specified
in the PD specification.
Note:
External Power
Source Detect
EXT_PWR_DET
IS
This function is only available in specific
device configurations.
This active high signal is used to indicate an external
power source is installed. This input can be utilized as a
standard digital input, or a resistive voltage divider can be
used to determine if the wall power AC adapter or charger is plugged into the platform (i.e., a qualifying “Externally Powered” status has occurred, according to the
USB Power Delivery Specification). In a typical application, this signal level will be set by a resistor divider of the
DC barrel voltage to satisfy the device logic levels and
level tolerance.
When this signal is high, the “externally powered” bit of
the VSafe5V Fixed Supply PDO for a provider will be set.
This signal will also help determine the preferences on
role swaps. Refer to Section 3.3.4, "USB Power Delivery
Role Selection," on page 26 for additional information.
Note:
DS00001760B-page 18
This function is only available in specific
device configurations.
2014 Microchip Technology Inc.
UPD1002
TABLE 2-2:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
Hub Power
Enable
HUB_PWR_EN
IS
Port Power
Controller
Enable
PPC_PWR_EN
O8
Description
This active high signal is driven by either the PCH of a
notebook or a downstream facing port (DFP) on a USB
hub. The hub or USB host may request the port to be
turned off by de-asserting this signal. Upon de-assertion,
if the device is NOT operating as a sink under a PD contract, the device will de-assert the PD_EN signal to turn
off VBUS to the port, which will remain off until HUB_PWR_EN asserts again.
Note:
In the case that the port supports insertion
detect or has a micro-AB receptacle (which
must support plug detection), the HUB_PWR_EN signal is ignored unless there is a
STD-A or micro-A plug inserted.
Note:
This function is only available in specific
device configurations.
This active high signal is used to enable an attached port
power controller. It should only be used in cases in which
the only source capability offered is 5 V.
Note:
In cases where the port power controller supports BC or other charging profiles, this single
signal will be enabling both power sourcing as
well as enabling the handshake emulation. BC
handshaking will occur before PD negotiation
and if in a headless/DCP charging mode, the
handshake will persist even after a PD negotiation was completed successfully.
Note:
This function is only available in specific
device configurations.
System Reset
RESET_N
IS
(PU)
System reset. This signal is active low.
Test
TEST
IS
Test signal. This signal is used for internal purposes only
and must be connected to ground through a 1 K resistor
for normal operation.
No Connect
NC
-
No connect. For proper operation, this signal must not be
connected.
SPI ROM Interface
SPI ROM
Clock
SPI_ROM_CLK
O8
SPI clock output to the serial ROM
SPI ROM Chip
Enable
SPI_ROM_CE_N
O8
This is the active low SPI ROM chip enable output. If the
SPI ROM interface is enabled, this signal should be
pulled up to the SPI ROM Vcc rail.
SPI ROM Data
In
SPI_ROM_DI
IS
SPI ROM data in
2014 Microchip Technology Inc.
DS00001760B-page 19
UPD1002
TABLE 2-2:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
SPI ROM Data
Out
SPI_ROM_DO
Buffer
Type
O8
(PD)
Description
SPI ROM data out
Note:
This signal must be pulled-up to VDDIO with
an external 10 kΩ resistor for proper operation.
Power/Ground
VTR Supply
Input
VTR
P
+3.3 to +5.0 V main power supply input. This signal must
be connected to a 2.2 µF capacitor to ground. Refer to
Figure 2-6 for additional power connection information.
+3.3 to +5.0 V
Variable Voltage I/O Power
VDDIO
P
+3.3 V to +5.0 V variable I/O power supply input. Refer to
Figure 2-6 for additional power connection information.
+5.0 V VBUS
Input
VBUS
P
+5.0 V VBUS input. This signal provides power in the
dead battery case. This signal must be connected to a
2.2 µF capacitor to ground. Refer to Figure 2-6 for additional power connection information.
+1.8V Power
Delivery
PD_VDD18
P
+1.8 V power for Power Delivery PHY. Refer to Figure 2-6
for additional power connection information.
Note:
Note:
When using internal +3.3 V regulator, these
pins must be externally connected to
VDD33_CAP.
This pin must be connected to VDD18_CAP
pin externally when using the internal VDD18
regulator.
+1.8 V Power
Capacitance
VDD18_CAP
P
This pin is used to provide capacitance for the integrated
+1.8 V regulator and must be connected to a 1 µF
(
工商网监
湘ICP备2023018690号
