VP2450N8-G

VP2450 P-Channel Enhancement-Mode Vertical DMOS FET Features General Description • • • • • • • The VP2450 is a low-threshold, Enhancement-mode (normally-off) transistor that utilizes a vertical Double-diffused Metal-Oxide Semiconductor (DMOS) structure and a well-proven silicon gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally induced secondary breakdown. Free from Secondary Breakdown Low Power Drive Requirement Ease of Paralleling Low CISS and Fast Switching Speeds High Input Impedance and High Gain Excellent Thermal Stability Integral Source-drain Diode Applications • • • • • • Motor Controls Converters Amplifiers Switches Power Supply Circuits Drivers: Relays, Hammers, Solenoids, Lamps, Memory, Displays, Bipolar Transistors, etc. This Vertical DMOS Field-Effect Transistor (FET) is ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Package Types TO-92 SOT-89 DRAIN DRAIN SOURCE DRAIN GATE SOURCE GATE See Table 3-1 for pin information.  2016 Microchip Technology Inc. DS20005569A-page 1 VP2450 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Drain-to-source Voltage......................................................................................................................................... BVDSS Drain-to-gate Voltage ............................................................................................................................................BVDGS Gate-to-source Voltage ........................................................................................................................................... ±20V Operating and Storage Temperatures .................................................................................................. –55°C to +150°C † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Electrical Specifications: For all specifications, TA = TJ = +25°C unless otherwise noted. Parameter Sym. Min. Typ. Max. Unit Conditions DC PARAMETER (Note 1 unless otherwise stated) Drain-to-source Breakdown Voltage BVDSS –500 — — V VGS = 0V, ID = –250 µA Gate Threshold Voltage VGS(th) –1.5 — –3.5 V VGS = VDS, ID = –1 mA Change in VGS(th) with Temperature ∆VGS(th) — — –4.8 Gate Body Leakage Current IGSS — — –100 nA — — –10 µA VGS = 0V, VDS = Maximum Rating Zero Gate Voltage Drain Current IDSS mA VDS = 0.8 Maximum Rating, VGS = 0V, TA = 125°C (Note 2) On-state Drain Current ID(ON) — — –1 –75 — — –200 — — — — 35 — — 30 ∆RDS(ON) — — 0.75 GFS 150 320 — Input Capacitance CISS — — 190 Common Source Output Capacitance COSS — — 75 Reverse Transfer Capacitance CRSS — — 20 Turn-on Delay Time td(ON) — — 10 Static Drain-to-source On-state Resistance Change in RDS(ON) with Temperature RDS(ON) mV/°C VGS = VDS, ID = –1 mA (Note 2) mA Ω %/°C VGS = ±20V, VDS = 0V VGS = –4.5V, VDS = –15V VGS = –10V, VDS = –15V VGS = –4.5V, ID = –50 mA VGS = –10V, ID = –100 mA VGS = –10V, ID = –100 mA (Note 2) AC PARAMETER (Note 2) Forward Transconductance Rise Time Turn-off Delay Time Fall Time mmho VDS = –15V, ID = –100 mA pF VGS = 0V, VDS = –25V, f = 1 MHz ns VDD = –25V, ID = –200 mA, RGEN = 25Ω tr — — 25 td(OFF) — — 45 tf — — 25 VSD — — –1.8 V VGS = 0V, ISD = –100 mA (Note 1) trr — 300 — ns VGS = 0V, ISD = –100 mA (Note 2) DIODE PARAMETER Diode Forward Voltage Drop Reverse Recovery Time Note 1: 2: All DC parameters are 100% tested at 25°C unless otherwise stated.  (Pulse test: 300 µs pulse, 2% duty cycle) Specification is obtained by characterization and is not 100% tested. DS20005569A-page 2  2016 Microchip Technology Inc. VP2450 TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, for all specifications TA =TJ = +25°C. Parameter Sym. Min. Typ. Max. Unit Operating Temperature TA –55 — +150 °C Storage Temperature TS –55 — +150 °C TO-92 JA — 132 — °C/W SOT-89 JA — 133 — °C/W Conditions TEMPERATURE RANGE PACKAGE THERMAL RESISTANCE THERMAL CHARACTERISTICS ID (Note 1) (Continuous) (mA) ID (Pulsed) (mA) TO-92 –100 –300 SOT-89 –160 –800 Package Note 1: 2: Power Dissipation at TA= 25°C (W) IDR (Note 1) (mA) IDRM (mA) 0.74 –100 –300 1.6 (Note 2) –160 –800 ID (continuous) is limited by maximum TJ. Mounted on FR5 board, 25 mm x 25 mm X 1.57 mm  2016 Microchip Technology Inc. DS20005569A-page 3 VP2450 TYPICAL PERFORMANCE CURVES BVDSS (normalized) Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g. outside specified power supply range) and therefore outside the warranted range. 1.2 80 1.1 60 RDS(ON) (ohms) 2.0 1.0 40 0.9 VGS = -4.5V 20 VGS = -10V 0.8 -50 0 50 100 0 150 0 -0.2 -0.4 FIGURE 2-1: Temperature. -0.6 -0.8 -1.0 -1.2 ID (amperes) Tj (OC) BVDSS Variation with -1.2 TA = -55OC VDS = -20V On-resistance vs. Drain FIGURE 2-4: Current. 1.5 2.2 1.3 1.8 VGS(th) (normalized) ID (amperes) 25OC -0.8 -0.6 -0.4 125OC VTH @ -1.0 mA 1.1 1.4 0.9 1.0 -0.2 RDS(ON) @ -10V, -0.1A 0.7 0 0 -1.0 -2.0 -3.0 -4.0 0.6 -50 0 50 VGS (volts) 100 150 Tj (OC) Transfer Characteristics. FIGURE 2-2: FIGURE 2-5: VGS(th) and RDS(ON) Variation with Temperature. 400 -10 ID = -100mA f = 1.0 MHz -8.0 VDS = -20V VGS (volts) 300 C (picofarads) RDS(ON) (normalized) -1.0 200 VDS = -40V -6.0 -4.0 CISS 100 -2.0 COSS CRSS 0 0 -10 -20 -30 VDS (volts) FIGURE 2-3: Capacitance vs. Drain-to-source Voltage. DS20005569A-page 4 -40 0 0 1.0 2.0 3.0 QG (nanocoulombs) FIGURE 2-6: Characteristics. Gate Drive Dynamic  2016 Microchip Technology Inc. VP2450 -1.0 -0.6 VGS = -10V VGS = -10V VGS = -4.5V -0.8 VGS = -6.0V -0.5 VGS = -6.0V ID (amperes) ID (amperes) -0.4 -0.6 VGS = -3.5V -0.4 VGS = -4.5V -0.3 VGS = -3.5V -0.2 -0.2 -0.1 0 0 -10 -20 -30 -40 0 0 -50 -2.0 -4.0 VDS (volts) FIGURE 2-7: -6.0 -8.0 -10 VDS (volts) Output Characteristics. Saturation Characteristics. FIGURE 2-10: 1.0 2.0 VDS = -20V TO-243AA 0.8 1.5 0.6 PD (watts) GFS (siemens) TA = -55OC 25OC 0.4 125OC TO-92 1.0 0.5 0.2 0 0 0 -100 -200 -300 -400 0 -500 25 50 FIGURE 2-8: Current. -1.0 Transconductance vs. Drain Thermal Resistance (normalized) TO-92 (DC) -0.01 TA = 25OC -0.001 -1.0 -100 -1000 Maximum Rated Safe  2016 Microchip Technology Inc. 150 Power Dissipation vs. Case TO-243AA TA = 25OC PD = 1.6W 0.6 0.4 0.2 TO-92 TC = 25OC PD = 1.0W 0.001 0.01 0.1 1.0 10 tP (seconds) VDS (volts) FIGURE 2-9: Operating Area. 125 0.8 0 -10 100 1.0 TO-243AA (DC) ID (amperes) FIGURE 2-11: Temperature. TO-243AA (pulsed) TO-92 (pulsed) -0.1 75 TC (OC) ID (milliamperes) FIGURE 2-12: Characteristics. Thermal Response DS20005569A-page 5 VP2450 3.0 PIN DESCRIPTION The details on the pins of VP2450 (TO-92 and SOT-89) are listed on Table 3-1. Refer to Package Types for the location of pins. TABLE 3-1: PIN FUNCTION TABLE TO-92 Pin Number SOT-89 Pin Number Pin Name 1 3 Source 2 1 Gate Gate 3 2,4 Drain Drain DS20005569A-page 6 Description Source  2016 Microchip Technology Inc. VP2450 4.0 FUNCTIONAL DESCRIPTION Figure 4-1 illustrates the switching waveforms and test circuit for VP2450. 0V Pulse Generator 10% INPUT RGEN 90% t(OFF) -10V t(ON) D.U.T. td(ON) tr td(OFF) tf INPUT OUTPUT 0V 90% OUTPUT RL 90% 10% 10% VDD VDD FIGURE 4-1: Switching Waveforms and Test Circuit. PRODUCT SUMMARY BVDSS/BVDGS (V) RDS(ON) (Maximum) (Ω) ID(ON) (Minimum) (mA) VGS(th) (Maximum) (V) –500 30 –200 –0.4  2016 Microchip Technology Inc. DS20005569A-page 7 VP2450 5.0 PACKAGING INFORMATION 5.1 Package Marking Information 3-lead TO-92 Example XXXXXX XXXX e3 YWWNNN VP2450 N3 e3 616343 3-lead SOT-89 XXXXYWW NNN Legend: XX...X Y YY WW NNN e3 * Note: DS20005569A-page 8 Example VP4E612 343 Product Code or Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for product code or customer-specific information. Package may or not include the corporate logo.  2016 Microchip Technology Inc. VP2450 Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.  2016 Microchip Technology Inc. DS20005569A-page 9 VP2450 3-Lead TO-243AA (SOT-89) Package Outline (N8) D D1 C E H L 1 2 E1 3 b b1 e A e1 Side View Top View Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging. Symbol Dimensions (mm) A b b1 C D D1 E E1 MIN 1.40 0.44 0.36 0.35 4.40 1.62 2.29 2.00† NOM - - - - - - - - MAX 1.60 0.56 0.48 0.44 4.60 1.83 2.60 2.29 e e1 1.50 BSC 3.00 BSC H L 3.94 0.73† - - 4.25 1.20 JEDEC Registration TO-243, Variation AA, Issue C, July 1986. † This dimension differs from the JEDEC drawing Drawings not to scale. DS20005569A-page 10  2016 Microchip Technology Inc. VP2450 APPENDIX A: REVISION HISTORY Revision A (September 2016) • Converted Supertex Doc# DSFP-VP2450 to Microchip DS20005569A. • Changed the “TO-243AA (SOT-89)” package to “SOT-89.” • Limited package options to TO-92 (1000/Bag) and SOT-89 (2000/Reel). • Made minor text changes throughout the document. DS20005569A-page 11  2016 Microchip Technology Inc. VP2450 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. XX PART NO. Package Options Device Device: Packages: - VP2450 = X - Environmental X Examples: a) VP2450N3-G: P-Channel Enhancement-Mode Vertical DMOS FET, 3-lead  TO-92 Package, 1000/Bag b) VP2450N8-G: P-Channel Enhancement-Mode Vertical DMOS FET, 3-lead SOT-89 Package, 2000/Reel Media Type P-Channel Enhancement-Mode Vertical DMOS FET N3 = 3-lead TO-92 N8 = 3-lead SOT-89 Environmental: G = Lead (Pb)-free/RoHS-compliant Package Media Type: (Blank) = 1000/Bag for an N3 Package 2000/Reel for an N8 Package  2016 Microchip Technology Inc. DS20005569A-page 12 Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. 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QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==  2016 Microchip Technology Inc. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. 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