ZL30321GGG2

ZL30321 GbE/SONET/SDH/PDH Network Interface Synchronizer Short Form Data Sheet July 2009 Features • Ordering Information Provides synchronous clocks for network interface cards that support synchronous Ethernet (SyncE) in addition to telecom interfaces (e.g. T1/E1, DS3/E3, etc) • Two independant DPLLs provides timing for the transmit path (backplane to line rate) and the receive path (recovered line rate to backplane) • Supports the requirements of ITU-T G.8262 for Synchronous Ethernet equipment slave clocks (EEC option 1 and 2) when combined with a system synchronizer such as the ZL30116, ZL30121, ZL30130, ZL30138 ZL30321GGG 100 Pin CABGA Trays ZL30321GGG2 100 Pin CABGA* Trays *Pb Free Tin/Silver/Copper in sampling phase -40oC to +85oC • Supports automatic hitless reference switching and short term holdover during loss of reference inputs • DPLLs can be configured to provide synchronous or asynchronous clock outputs • Generates several styles of output frame pulses with selectable pulse width, polarity, and frequency Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities • Supports the requirements of Telcordia GR-253 SONET clocks and ITU-T G.813 SDH equipment slave clocks (SEC) • • Synchronizes to any standard telecom system reference with a multiple of 8 kHz up to 77.76 MHz or to Ethernet clock rates including 25 MHz, 50 MHz, 62.5 MHz, and 125 MHz Applications • Low jitter APLL generates either Ethernet clock rates (25 MHz, 50 MHz, 62.5 MHz, and 125 MHz) or SONET/SDH (6.48 MHz, 19.44 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz) clock rates Carrier Grade Ethernet/SONET/SDH/PDH Network Interface Cards • GPON ONT/ONU • T1/E1 line cards • DS3/E3 line cards • • Programmable output synthesizers (P0, P1) generate clock frequencies with any multiple of 8 kHz up to 100 MHz osci SPI/I2C mode lock hold ref0 ref1 ref2 ref3 ref4 ref5 ref6 ref7 sync0 sync1 sync2 Master Osc SSI osco refn Input Ports & Ref Monitors syncn refm DPLL 1 APLL apll_clk0 apll_clk1 P0 Synthesizer p0_clk0 p0_clk1 p0_fp0 p0_fp1 P1 Synthesizer p1_clk1 p1_clk0 DPLL2 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2008-2009, Zarlink Semiconductor Inc. All Rights Reserved. ZL30321 Short Form Data Sheet Pin Description 100BGA Pin # Name I/O Type Description Input Reference C1 B2 A3 C3 B3 B4 C4 A4 ref0 ref1 ref2 ref3 ref4 ref5 ref6 ref7 Iu Input References 7:0 (LVCMOS, Schmitt Trigger). These input references are available to both DPLL1 and DPLL2 for synchronizing output clocks. All eight input references can lock to any multiple of 8 kHz up to 77.76 MHz including 25 MHz and 50 MHz. Input ref0 and ref1 have additional configurable pre-dividers allowing input frequencies such as 62.5 MHz, 125 MHz. These pins are internally pulled up to Vdd. B1 A1 A2 sync0 sync1 sync2 Iu Frame Pulse Synchronization References 2:0 (LVCMOS, Schmitt Trigger). These are optional frame pulse synchronization inputs associated with input references 0, 1 and 2. These inputs accept frame pulses in a clock format (50% duty cycle) or a basic frame pulse format with minimum pulse width of 5 ns. These pins are internally pulled up to Vdd. Output Clocks and Frame Pulses D10 apll_clk0 O APLL Output Clock 0 (LVCMOS). Output clock 0 of the APLL. The APLL can be configured to provide either SONET/SDH or Ethernet clock rates. The default frequency for this output is 77.76 MHz. G10 apll_clk1 O APLL Output Clock 1 (LVCMOS). Output clock 1 of the APLL. The APLL can be configured to provide either SONET/SDH or Ethernet clock rates. The default frequency for this output is 19.44 MHz. K9 p0_clk0 O Programmable Synthesizer 0 - Output Clock 0 (LVCMOS). This output can be configured to provide any frequency with a multiple of 8 kHz up to 100 MHz, in addition to 2 kHz. The default frequency for this output is 65.536 MHz. K7 p0_clk1 O Programmable Synthesizer 0 - Output Clock 1 (LVCMOS). This is a programmable clock output configurable as a multiple or division of the p0_clk0 frequency within the range of 2 kHz to 100 MHz. The default frequency for this output is 32.768 MHz. K8 p0_fp0 O Programmable Synthesizer 0 - Output Frame Pulse 0 (LVCMOS). This output can be configured to provide virtually any style of output frame pulse associated with the p0 clocks. The default frequency for this frame pulse output is 8 kHz. J7 p0_fp1 O Programmable Synthesizer 0 - Output Frame Pulse 1 (LVCMOS). This output can be configured to provide virtually any style of output frame pulse associated with the p0 clocks. The default frequency for this frame pulse output is 8 kHz J10 p1_clk0 O Programmable Synthesizer 1 - Output Clock 0 (LVCMOS). This output can be configured to provide any frequency with a multiple of 8 kHz up to 100 MHz in addition to 2 kHz. The default frequency for this output is 34.368 MHz. K10 p1_clk1 O Programmable Synthesizer1 - Output Clock 1 (LVCMOS). This is a programmable clock output configurable as a multiple or division of the p1_clk0 frequency within the range of 2 kHz to 100 MHz. The default frequency for this output is 68.736 MHz. 2 Zarlink Semiconductor Inc. ZL30321 Short Form Data Sheet 100BGA Pin # Name I/O Type E1 ref_out O DPLL2 Selected Output Reference (LVCMOS). This is a buffered copy of the output of the reference selector for DPLL2. Switching between input reference clocks at this output is not hitless. H5 rst_b I Reset (LVCMOS, Schmitt Trigger). A logic low at this input resets the device. To ensure proper operation, the device must be reset after power-up. Reset should be asserted for a minimum of 300 ns. J5 hs_en Iu DPLL1 Hitless Switching Enable (LVCMOS, Schmitt Trigger). A logic high at this input enables hitless reference switching. A logic low disables hitless reference switching and re-aligns DPLL1’s output phase to the phase of the selected reference input. This feature can also be controlled through software registers. This pin is internally pulled up to Vdd. C2 D2 mod0 mod1 Iu DPLL1 Mode Select 1:0 (LVCMOS, Schmitt Trigger). During reset, the levels on these pins determine the default mode of operation for DPLL1 (Automatic, Normal, Holdover or Freerun). After reset, the mode of operation can be controlled directly with these pins, or by accessing the dpll1_modesel register (0x1F) through the serial interface. This pin is internally pulled up to Vdd. H1 lock O Lock Indicator (LVCMOS). This is the lock indicator pin for DPLL1. This output goes high when DPLL1’s output is frequency and phase locked to the input reference. J1 hold O Holdover Indicator (LVCMOS). This pin goes high when DPLL1 enters the holdover mode. Description Control Status Serial Interface E2 sck_scl I/B Clock for Serial Interface (LVCMOS). Serial interface clock. When i2c_en = 0, this pin acts as the sck pin for the serial interface. When i2c_en = 1, this pin acts as the scl pin (bidirectional) for the I2C interface. F1 si_sda I/B Serial Interface Input (LVCMOS). Serial interface data pin. When i2c_en = 0, this pin acts as the si pin for the serial interface. When i2c_en = 1, this pin acts as the sda pin (bidirectional) for the I2C interface. G1 so O Serial Interface Output (LVCMOS). Serial interface data output. When i2c_en = 0, this pin acts as the so pin for the serial interface. When i2c_en = 1, this pin is unused and should be left unconnected. E3 cs_b_asel0 Iu Chip Select for SPI/Address Select 0 for I2C (LVCMOS). When i2c_en = 0, this pin acts as the chip select pin (active low) for the serial interface. When i2c_en = 1, this pin acts as the asel0 pin for the I2C interface. F3 asel1 Iu Address Select 1 for I2C (LVCMOS). When i2c_en = 1, this pin acts as the asel1 pin for the I2C interface. Internally pulled up to Vdd. Leave open when not in use. F2 asel2 Iu Address Select 2 for I2C (LVCMOS). When i2c_en = 1, this pin acts as the asel2 pin for the I2C interface. Internally pulled up to Vdd. Leave open when not in use. 3 Zarlink Semiconductor Inc. ZL30321 Short Form Data Sheet 100BGA Pin # Name I/O Type G2 int_b O Interrupt Pin (LVCMOS). Indicates a change of device status prompting the processor to read the enabled interrupt service registers (ISR). This pin is an open drain, active low and requires an external pulled-up to Vdd. J2 i2c_en Iu I2C Interface Enable (LVCMOS). If set high, the I2C interface is enabled, if set low, the SPI interface is enabled. Internally pull-up to Vdd. Description APLL Loop Filter A6 apll_filter A External Analog PLL Loop Filter terminal. B6 filter_ref0 A Analog PLL External Loop Filter Reference. C6 filter_ref1 A Analog PLL External Loop Filter Reference. JTAG and Test J4 tdo O Test Serial Data Out (Output). JTAG serial data is output on this pin on the falling edge of tck. This pin is held in high impedance state when JTAG scan is not enabled. K2 tdi Iu Test Serial Data In (Input). JTAG serial test instructions and data are shifted in on this pin. This pin is internally pulled up to Vdd. If this pin is not used then it should be left unconnected. H4 trst_b Iu Test Reset (LVCMOS). Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-up to ensure that the device is in the normal functional state. This pin is internally pulled up to Vdd. If this pin is not used then it should be connected to GND. K3 tck I Test Clock (LVCMOS): Provides the clock to the JTAG test logic. If this pin is not used then it should be pulled down to GND. J3 tms Iu Test Mode Select (LVCMOS). JTAG signal that controls the state transitions of the TAP controller. This pin is internally pulled up to VDD. If this pin is not used then it should be left unconnected. K4 osci I Oscillator Master Clock Input (LVCMOS). This input accepts a 20 MHz reference from a clock oscillator (TCXO, OCXO). The stability and accuracy of the clock at this input determines the free-run accuracy and the long term holdover stability of the output clocks. K5 osco O Oscillator Master Clock Output (LVCMOS). This pin must be left unconnected when the osci pin is connected to a clock oscillator. Master Clock Miscellaneous J6 IC Internal Connection. Connect to ground. C5 B5 K6 H10 E10 F10 IC Internal Connection. Leave unconnected. 4 Zarlink Semiconductor Inc. ZL30321 100BGA Pin # D3 K1 H7 G3 D1 A9 B10 A10 B9 Name I/O Type NC Short Form Data Sheet Description No Connection. Leave unconnected. Power and Ground D9 E4 G8 G9 J8 J9 H6 H8 VDD P P P P P P P P Positive Supply Voltage. +3.3VDC nominal. E8 F4 VCORE P P Positive Supply Voltage. +1.8VDC nominal. A5 A8 C10 AVDD P P P Positive Analog Supply Voltage. +3.3VDC nominal. B7 B8 H2 AVCORE P P P Positive Analog Supply Voltage. +1.8VDC nominal. D4 D5 D6 D7 E5 E6 E7 F5 F6 F7 G4 G5 G6 G7 E9 F8 F9 H9 VSS G G G G G G G G G G G G G G G G G G Ground. 0 Volts. 5 Zarlink Semiconductor Inc. ZL30321 100BGA Pin # A7 C7 C8 C9 D8 H3 IId Iu OAPG- Name AVSS I/O Type G G G G G G Short Form Data Sheet Description Analog Ground. 0 Volts. Input Input, Internally pulled down Input, Internally pulled up Output Analog Power Ground 6 Zarlink Semiconductor Inc. ZL30321 1.0 Short Form Data Sheet Pin Diagram TOP VIEW 1 1 2 3 4 5 6 7 8 9 10 sync1 sync2 ref2 ref7 AVDD apll_filter AVSS AVDD NC NC sync0 ref1 ref4 ref5 IC filter_ref0 AVCORE AVCORE NC NC ref0 mod0 ref3 ref6 IC filter_ref1 AVSS AVSS AVSS AVDD NC mod1 NC VSS VSS VSS VSS AVSS VDD apll_clk0 ref_out sck/ scl cs_b/ asel0 VDD VSS VSS VSS VCORE VSS IC si/ sdh asel2 asel1 VCORE VSS VSS VSS VSS VSS IC so int_b NC VSS VSS VSS VSS VDD VDD apll_clk1 lock AVCORE AVSS trst_b rst_b VDD NC VDD VSS IC hold i2c_en tms tdo hs_en IC p0_fp1 VDD VDD p1_clk0 NC tdi tck osci osco IC p0_clk1 p0_fp0 p0_clk0 p1_clk1 A B C D E F G H J K 1 - A1 corner is identified with a dot. 7 Zarlink Semiconductor Inc. ZL30321 2.0 Short Form Data Sheet Overview The ZL30321 SONET/SDH/GbE Mulit-Rate Line Card Synchronizer is a highly integrated device that provides timing for network interface cards. It incorporates two independent DPLLs, each capable of locking to one of eight input references and provides a wide variety of synchronized output clocks and frame pulses. This device is ideally suited for designs that require both a transmit timing path (backplane to PHY) and a receive timing path (PHY to backplane). Each path is controlled with separate DPLLs (DPLL1, DPLL1) which are both independently configurable through the serial interface (SPI or I2C). A typical application of the ZL30321 is shown in Figure 2. In this application, the ZL30321 translates the 19.44 MHz clock from the telecom rate backplane (system timing bus), translates the frequency to 125 MHz for the PHY Tx clock, and filters the jitter to ensure compliance with the related standards. A programmable synthesizer (P0) provides optional synchronous PDH clocks with multiples of 8 kHz for generating PDH interface clocks. On the receive path, DPLL2 and the P1 synthesizer translate the line recovered clock (8 kHz or 1.544 MHz) from the PHY to the 19.44 MHz telecom backplane (line recovered timing) for the central timing cards. The ZL30321 allows easy integration of Ethernet line rates with today’s telecom backplanes. BITS A Central Timing Card BITS B S P Central Timing Card P S XOVER DPLL DPLL ZL30121 ZL30121 P S 19.44 MHz S 19.44 MHz P Line Recovered Timing A P Telecom Backplane S B System Timing Bus A 19.44 MHz P1 ZL30321 B A B DPLL1 DPLL1 19.44 MHz ZL30321 P1 DPLL2 DPLL2 P0 APLL P0 125 MHz 8 kHz PHY 1.544 MHz and/or 2.048 MHz APLL 1.544 MHz PHY Ethernet Line Card T1/E1 Line Card Figure 2 - Typical Application of the ZL30321 8 Zarlink Semiconductor Inc. For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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