UF3C120040K3S

1200V-35mW SiC FET Rev. C, December 2019 DATASHEET Description UF3C120040K3S CASE CASE D (2) This SiC FET device is based on a unique ‘cascode’ circuit configuration, in which a normally-on SiC JFET is co-packaged with a Si MOSFET to produce a normally-off SiC FET device. The device’s standard gate-drive characteristics allows for a true “drop-in replacement” to Si IGBTs, Si FETs, SiC MOSFETs or Si superjunction devices. Available in the TO-247-3L package, this device exhibits ultralow gate charge and exceptional reverse recovery characteristics, making it ideal for switching inductive loads when used with recommended RC-snubbers, and any application requiring standard gate drive. Features w Typical on-resistance RDS(on),typ of 35mW w Maximum operating temperature of 175°C w Excellent reverse recovery G (1) w Low gate charge w Low intrinsic capacitance w ESD protected, HBM class 2 1 2 3 w Very low switching losses (required RC-snubber loss negligible under typical operating conditions) S (3) . Typical applications Part Number Package Marking UF3C120040K3S TO-247-3L UF3C120040K3S w EV charging w PV inverters w Switch mode power supplies w Power factor correction modules w Motor drives w Induction heating Datasheet: UF3C120040K3S Rev. C, December 2019 1 Maximum Ratings Parameter Symbol VDS VGS Drain-source voltage Gate-source voltage Continuous drain current 1 ID Pulsed drain current 2 Single pulsed avalanche energy 3 Power dissipation Maximum junction temperature Operating and storage temperature IDM EAS Ptot TJ,max TJ, TSTG Max. lead temperature for soldering, 1/8” from case for 5 seconds TL Test Conditions DC TC = 25°C TC = 100°C TC = 25°C L=15mH, IAS =4.2A TC = 25°C Value Units 1200 -25 to +25 65 47 175 132.3 429 175 -55 to 175 V V A A A mJ W °C °C 250 °C 1. Limited by TJ,max 2. Pulse width tp limited by TJ,max 3. Starting TJ = 25°C Thermal Characteristics Parameter Thermal resistance, junction-to-case Datasheet: UF3C120040K3S Symbol Test Conditions RqJC Rev. C, December 2019 Value Min Typ Max 0.27 0.35 Units °C/W 2 Electrical Characteristics (TJ = +25°C unless otherwise specified) Typical Performance - Static Parameter Drain-source breakdown voltage Total drain leakage current Total gate leakage current Drain-source on-resistance Gate threshold voltage Gate resistance Symbol Test Conditions BVDS VGS=0V, ID=1mA IDSS IGSS RDS(on) VG(th) RG Value Min Typ Max 1200 V VDS=1200V, VGS=0V, TJ=25°C 8 VDS=1200V, VGS=0V, TJ=175°C 35 VDS=0V, TJ=25°C, VGS=-20V / +20V 6 20 VGS=12V, ID=40A, TJ=25°C 35 45 VGS=12V, ID=40A, TJ=125°C VGS=12V, ID=40A, TJ=175°C VDS=5V, ID=10mA Units 150 mA mA mW 56 73 4 f=1MHz, open drain 5 4.5 6 V W Typical Performance - Reverse Diode Parameter Diode continuous forward current 1 Diode pulse current 2 Forward voltage Test Conditions IS TC=25°C 65 A IS,pulse TC=25°C 175 A VFSD Reverse recovery charge Qrr Reverse recovery time trr Reverse recovery charge Qrr Reverse recovery time trr Datasheet: UF3C120040K3S Value Symbol Min Typ VGS=0V, IF=20A, TJ=25°C 1.5 VGS=0V, IF=20A, TJ=175°C 1.95 VR=800V, IF=40A, VGS=-5V, RG_EXT=10W di/dt=2400A/ms, TJ=25°C VR=800V, IF=40A, VGS=-5V, RG_EXT=10W di/dt=2400A/ms, TJ=150°C Rev. C, December 2019 Max Units 2 V 358 nC 25 ns 259 nC 22 ns 3 Typical Performance - Dynamic Parameter Value Symbol Test Conditions Ciss Coss Crss VDS=100V, VGS=0V f=100kHz 1500 210 1.7 pF Effective output capacitance, energy related Coss(er) VDS=0V to 800V, VGS=0V 112 pF Effective output capacitance, time related Coss(tr) VDS=0V to 800V, VGS=0V 280 pF COSS stored energy Eoss VDS=800V, VGS=0V 35.6 mJ Total gate charge Gate-drain charge Gate-source charge QG QGD QGS VDS=800V, ID=40A, VGS = -5V to15V 51 11 19 nC Turn-on delay time td(on) Input capacitance Output capacitance Reverse transfer capacitance tr Rise time td(off) Turn-off delay time tf Fall time 4 EON 4 EOFF Turn-on energy including RS energy Turn-off energy including RS energy Total switching energy including RS energy4 ETOTAL Min Typ VDS=800V, ID=40A, Gate Driver =-5V to +15V, Turn-on RG,EXT=1W, Turn-off RG,EXT=22W Inductive Load, FWD: same device with VGS = -5V and RG = 22W, RC snubber: RS=5W and CS=220pF, TJ=25°C 26 61 1222 227 1449 Snubber RS energy during turn-off ERS_OFF 9.5 td(on) 37 tr td(off) Turn-off delay time tf Fall time 4 EON 4 EOFF Turn-on energy including RS energy Turn-off energy including RS energy Total switching energy including RS energy4 ETOTAL Snubber RS energy during turn-on ERS_ON Snubber RS energy during turn-off ERS_OFF VDS=800V, ID=40A, Gate Driver =-5V to +15V, Turn-on RG,EXT=1W, Turn-off RG,EXT=22W Inductive Load, FWD: same device with VGS = -5V and RG = 22W, RC snubber: RS=5W and CS=220pF, TJ=150°C ns 20 ERS_ON Rise time Units 38 Snubber RS energy during turn-on Turn-on delay time Max mJ 7.3 25 63 ns 21 1183 261 1444 mJ 7.1 9.5 4. The switching performance are evaluated with a RC snubber circuit as shown in Figure 24. Datasheet: UF3C120040K3S Rev. C, December 2019 4 120 120 100 100 Drain Current, ID (A) Drain Current, ID (A) Typical Performance Diagrams 80 Vgs = 15V 60 Vgs = 10V Vgs = 8V 40 Vgs = 7.5V Vgs = 7V 20 Vgs = 15V Vgs = 10V 60 Vgs = 8V 40 Vgs = 7V Vgs = 6.5V 20 Vgs = 6.5V 0 Vgs = 6V 0 0 1 2 3 4 5 6 7 8 Drain-Source Voltage, VDS (V) 9 10 Figure 1. Typical output characteristics at TJ = - 55°C, tp < 250ms 120 60 1 2 3 4 5 6 7 8 9 Drain-Source Voltage, VDS (V) 10 Figure 2. Typical output characteristics at TJ = 25°C, tp < 250ms On Resistance, RDS_ON (P.U.) 80 0 2.5 Vgs = 15V Vgs = 8V Vgs = 7V Vgs = 6.5V Vgs = 6V Vgs = 5.5V 100 Drain Current, ID (A) 80 40 20 2.0 1.5 1.0 0.5 0.0 0 0 1 2 3 4 5 6 7 8 Drain-Source Voltage, VDS (V) 9 Figure 3. Typical output characteristics at TJ = 175°C, tp < 250ms Datasheet: UF3C120040K3S -75 -50 -25 0 25 50 75 100 125 150 175 Junction Temperature, TJ (°C) 10 Figure 4. Normalized on-resistance vs. temperature at VGS = 12V and ID = 40A Rev. C, December 2019 5 120 Tj = 175°C Tj = 25°C Tj = - 55°C 125 100 75 50 25 Tj = 25°C Tj = 175°C 80 60 40 20 0 0 0 20 40 60 80 Drain Current, ID (A) 100 120 Figure 5. Typical drain-source on-resistances at VGS = 12V 0 2 3 4 5 6 7 8 Gate-Source Voltage, VGS (V) 9 10 Gate-Source Voltage, VGS (V) 20 5 4 3 2 1 0 -100 1 Figure 6. Typical transfer characteristics at VDS = 5V 6 Threshold Voltage, Vth (V) Tj = -55°C 100 Drain Current, ID (A) On-Resistance, RDS(on) (mW) 150 15 10 5 0 -5 -50 0 50 100 150 Junction Temperature, TJ (°C) Figure 7. Threshold voltage vs. junction temperature at VDS = 5V and ID = 10mA Datasheet: UF3C120040K3S 0 200 10 20 30 40 Gate Charge, QG (nC) 50 60 Figure 8. Typical gate charge at VDS = 800V and ID = 40A Rev. C, December 2019 6 0 0 Vgs = -5V Vgs = 0V Vgs = 5V -20 Vgs = 8V -30 -40 -50 Vgs = 0V Vgs = 5V -20 Vgs = 8V -30 -40 -50 -60 -60 -4 -3 -2 -1 Drain-Source Voltage, VDS (V) 0 Figure 9. 3rd quadrant characteristics at TJ = -55°C -4 -3 -2 -1 Drain-Source Voltage, VDS (V) 0 Figure 10. 3rd quadrant characteristics at TJ = 25°C 0 80 70 -10 60 -20 -30 EOSS (mJ) Drain Current, ID (A) Vgs = - 5V -10 Drain Current, ID (A) Drain Current, ID (A) -10 Vgs = - 5V -50 40 30 Vgs = 0V -40 50 Vgs = 5V 20 Vgs = 8V 10 0 -60 -4 -3 -2 -1 Drain-Source Voltage, VDS (V) Figure 11. 3rd quadrant characteristics at TJ = 175°C Datasheet: UF3C120040K3S 0 0 200 400 600 800 1000 Drain-Source Voltage, VDS (V) 1200 Figure 12. Typical stored energy in COSS at VGS = 0V Rev. C, December 2019 7 10,000 70 DC Drain Current, ID (A) Capacitance, C (pF) Ciss 1,000 Coss 100 10 60 50 40 30 20 10 Crss 0 1 0 -75 -50 -25 0 25 50 75 100 125 150 175 Case Temperature, TC (°C) 200 400 600 800 1000 1200 Drain-Source Voltage, VDS (V) Figure 13. Typical capacitances at f = 100kHz and VGS = 0V Figure 14. DC drain current derating 1 Thermal Impedance, ZqJC (°C/W) Power Dissipation, Ptot (W) 500 400 300 200 100 0 -75 -50 -25 0 25 50 75 100 125 150 175 Case Temperature, TC (°C) Figure 15. Total power dissipation Datasheet: UF3C120040K3S 0.1 0.01 D = 0.5 D = 0.3 D = 0.1 D = 0.05 D = 0.02 D = 0.01 Single Pulse 0.001 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 Pulse Time, tp (s) Figure 16. Maximum transient thermal impedance Rev. C, December 2019 8 400 1ms 100 350 10ms 250 10 100ms 1 Qrr (nC) Drain Current, ID (A) 300 1ms DC 200 150 100 10ms 50 0.1 0 1 10 100 1000 Drain-Source Voltage, VDS (V) 0 Figure 17. Safe operation area at TC = 25°C, D = 0, Parameter tp 2500 20 VDS = 800V, VGS = -5V/15V RC snubber: CS=220pF, RS=5W, FWD: same device with VGS=-5V, RG = 22W 2000 1500 500 50 75 100 125 150 Junction Temperature, TJ (°C) 175 Rs Etot Rs Eon Rs Eoff 18 Etot Eon Eoff 1000 25 Figure 18. Reverse recovery charge Qrr vs. junction temperture Snubber RS Energy (mJ) Switching Energy (mJ) VDS = 800V, IS = 40A, di/dt = 2400A/ms, VGS = -5V, RG =10W 16 14 12 10 8 6 4 2 0 0 0 10 20 30 40 Drain Current, ID (A) 50 60 0 10 20 30 40 Drain Current, ID (A) 50 60 (a) (b) Figure 19. Clamped inductive switching energy (a) and RC snubber energy loss (b) vs. drain current at TJ = 25°C, turn-on RG_EXT = 1W, and turn-off RG_EXT = 22W Datasheet: UF3C120040K3S Rev. C, December 2019 9 8 Turn-on Sunbber RS Energy (mJ) 1600 Turn-on Energy, Eon (mJ) 1400 1200 1000 800 VDS = 800V, ID = 40A, VGS = -5V/15V, TJ = 25°C RC snubber: CS=220pF, RS = 5W FWD: same device with VGS = -5V, RG = 22W 600 400 200 0 7 6 5 4 3 2 1 0 0 5 10 15 20 25 Total External Turn-on RG, RG_EXT (W) 30 0 5 10 15 20 25 Total External Turn-on RG, RG_EXT (W) 30 (a) (b) Figure 20. Clamped inductive switching turn-on energy including RC snubber energy loss (a) and RC snubber energy loss (b) as a function of total external turn-on gate resistor RG_EXT 400 15 Turn-off Sunbber RS Energy (mJ) Turn-Off Energy, Eoff (mJ) 350 300 250 200 150 VDS = 800V, ID = 40A, VGS = -5V/15V, TJ = 25°C RC snubber: CS=220pF, RS = 5W FWD: same device with VGS = -5V 100 50 0 12 9 6 3 0 0 10 20 30 40 Total External Turn-off RG, RG,EXT (W) 50 0 10 20 30 40 Total External Turn-off RG, RG_EXT (W) 50 (a) (b) Figure 21. Clamped inductive switching turn-off energy including RC snubber energy loss (a) and RC snubber energy loss (b) as a function of total external turn-off gate resistor RG_EXT Datasheet: UF3C120040K3S Rev. C, December 2019 10 2000 1500 16 Snubber RS Energy (mJ) 1750 Switching Energy (mJ) 18 Etot Eon Eoff 1250 1000 VDS = 800V, VGS = -5V/15V, RG_ON = 1W, RG_OFF = 22W, FWD: same device with VGS=-5V, RG=22W, RC snubber: CS = 220pF, RS = 5W 750 500 250 Rs Etot Rs Eon Rs Eoff 14 12 10 8 6 4 2 0 0 0 25 50 75 100 125 150 Junction Temperature, TJ (°C) 0 175 25 50 75 100 125 150 Junction Temperature, TJ (°C) 175 (a) (b) Figure 22. Clamped inductive switching energy including RC snubber energy loss (a) and RC snubber energy loss (b) as a function of junction temperature at ID = 40A 2000 1500 80 Snubber RS Energy (mJ) 1750 Switching Energy (mJ) 90 Etot Eon Eoff 1250 1000 VDS = 800V, VGS = -5V/15V RG_ON = 1W, RG_OFF = 22W FWD: same device with VGS=-5V, RG=22W, RC snubber: RS = 5W 750 500 250 70 Rs Etot Rs Eon Rs Eoff 60 50 40 30 20 10 0 0 200 400 600 Snubber Capacitance, CS (pF) 800 0 0 200 400 600 Snubber Capacitance, CS (pF) 800 (a) (b) Figure 23. Clamped inductive switching energy including RC snubber energy loss (a) and RC snubber energy loss (b) as a function of snubber capacitance at ID = 40A and TJ = 25°C Datasheet: UF3C120040K3S Rev. C, December 2019 11 Figure 24. Clamped inductive load switching test circuit An RC snubber (RS = 5W and CS = 220pF) is required to improve the turn-off waveforms. Applications Information SiC FETs are enhancement-mode power switches formed by a highvoltage SiC depletion-mode JFET and a low-voltage silicon MOSFET connected in series. The silicon MOSFET serves as the control unit while the SiC JFET provides high voltage blocking in the off state. This combination of devices in a single package provides compatibility with standard gate drivers and offers superior performance in terms of low on-resistance (RDS(on)), output capacitance (Coss), gate charge (QG), and reverse recovery charge (Qrr) leading to low conduction and switching losses. The SiC FETs also provide excellent reverse conduction capability eliminating the need for an external anti-parallel diode. Information on all products and contained herein is intended for description only. No license, express or implied, to any intellectual property rights is granted within this document. UnitedSiC assumes no liability whatsoever relating to the choice, selection or use of the UnitedSiC products and services described herein. Like other high performance power switches, proper PCB layout design to minimize circuit parasitics is strongly recommended due to the high dv/dt and di/dt rates. An external gate resistor is recommended when the FET is working in the diode mode in order to achieve the optimum reverse recovery performance. For more information on SiC FET operation, see www.unitedsic.com. Disclaimer UnitedSiC reserves the right to change or modify any of the products and their inherent physical and technical specifications without prior notice. UnitedSiC assumes no responsibility or liability for any errors or inaccuracies within. Datasheet: UF3C120040K3S Rev. C, December 2019 12