AD12401-400KWS

12-Bit, 400 MSPS A/D Converter AD12401 FEATURES Up to 400 MSPS sample rate SNR of 63 dBFS @128 MHz SFDR of 70 dBFS @128 MHz VSWR of 1:1.5 High or low gain grades Wideband ac-coupled input signal conditioning Enhanced spurious-free dynamic range Single-ended or differential ENCODE signal LVDS output levels Twos complement output data FUNCTIONAL BLOCK DIAGRAM AD12401 ADC A POSTPROCESSING DATA READY A DA0–DA11 CLK DISTRIBUTION AIN ADC B DB0–DB11 DR_EN APPLICATIONS Communications test equipment Radar and satellite subsystems Phased array antennas, digital beams Multichannel, multimode receivers Secure communications Wireless and wired broadband communications Wideband carrier frequency systems CLOCK DISTRIBUTION DIVIDE BY 2 DATA READY B ENC ENC OROUT Figure 1. GENERAL DESCRIPTION The AD12401 is a 12-bit analog-to-digital converter (ADC) with a transformer-coupled analog input and digital postprocessing for enhanced SFDR. The product operates at up to 400 MSPS conversion rate with outstanding dynamic performance in wideband carrier systems. The AD12401 requires a 3.7 V analog supply and 3.3 V and 1.5 V digital supplies, and provides a flexible ENCODE signal that can be differential or single ended. No external reference is required. The AD12401 package style is an enclosed 2.9" × 2.6" × 0.6" module. Performance is rated over a 0°C to 60°C case temperature range. PRODUCT HIGHLIGHTS 1. Guaranteed sample rate up to 400 MSPS. 2. Input signal conditioning with optimized dynamic performance to 175 MHz. 3. High and low gain grades available. 4. Additional performance options available (sample rates >400 MSPS or second Nyquist zone operation); contact sales. 5. Proprietary Advanced Filter Bank (AFB™) digital postprocessing from V Corp Technologies, Inc. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. 005649-001 AD12401 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications—ENCODE = 400 MSPS.............................. 4 AC Specifications—ENCODE = 360 MSPS.............................. 5 AC Specifications—ENCODE = 326 MSPS.............................. 6 Absolute Maximum Ratings............................................................ 8 Explanation of Test Levels ........................................................... 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions........................... 10 Terminology .................................................................................... 13 Typical Performance Characteristics ........................................... 15 Theory of Operation ...................................................................... 18 Time-Interleaving ADCs........................................................... 18 Analog Input ............................................................................... 18 Clock Input.................................................................................. 18 Digital Outputs ........................................................................... 19 Power Supplies............................................................................ 19 Start-Up and RESET .................................................................. 19 DR_EN......................................................................................... 19 Overrange.................................................................................... 19 Gain Select................................................................................... 20 Thermal Considerations............................................................ 20 Package Integrity/Mounting Guidelines ................................. 20 AD12401 Evaluation Kit ........................................................... 21 Data Outputs............................................................................... 21 Layout Guidelines........................................................................... 26 PCB Interface .............................................................................. 26 Outline Dimensions ....................................................................... 28 Ordering Guide .......................................................................... 28 REVISION HISTORY 4/06—Rev. 0 to Rev. A Changes to Features and Product Highlights ............................... 1 Changes to Table 1............................................................................ 3 Changes to Table 2............................................................................ 4 Changes to Table 4............................................................................ 6 Changes to Table 7............................................................................ 9 Changes to Figure 5........................................................................ 10 Changes to Table 9.......................................................................... 11 Added Gain Select Section ............................................................ 20 Added H/L_GAIN Section............................................................ 21 Changes to Figure 25...................................................................... 23 Changes to the Ordering Guide.................................................... 28 7/05—Revision 0: Initial Version Rev. A | Page 2 of 28 AD12401 SPECIFICATIONS DC SPECIFICATIONS VA = 3.7 V, VC = 3.3 V, VD = 1.5 V, 0°C ≤ TCASE ≤ 60°C, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error @ 10 MHz Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Gain Error ANALOG INPUT (AIN) Full-Scale Input Voltage Range Flatness (10 MHz to 175 MHz) Input VSWR, 50 Ω (300 kHz to 175 MHz) Analog Input Bandwidth POWER SUPPLY 1 Supply Voltage VA VC VD Supply Current IVA ( VA = 3.7 V) IVC ( VC = 3.3 V) IVD ( VD = 1.5 V) Total Power Dissipation ENCODE INPUTS Differential Inputs (ENC, ENC) Input Voltage Input Resistance Input Capacitance Common-Mode Voltage Single-Ended Inputs (ENC) Input Voltage Input Resistance LOGIC INPUTS (RESET) 2 Logic 1 Voltage Logic 0 Voltage Source IIH Sink IIL LOGIC INPUTS (DR_EN) Logic 1 Voltage Logic 0 Voltage Source IIH Sink IIL Case Temp Test Level Min AD12401-xxxKWS Typ Max 12 Guaranteed −12 −10 ±0.3 ±0.5 0.02 3.2 0.5 1.5 480 +12 +10 −12 −10 ±0.3 ±0.5 0.02 1.6 0.5 1.5 480 +12 +10 LSB %FS LSB LSB %/°C V p-p dB MHz AD12401-xxxJWS Min Typ Max Unit Bits Full Full Full 60°C 60°C 60°C 60°C Full 60°C 60°C IV I I V V V V IV V V 1 1 Full Full Full Full Full Full Full IV IV IV I I I I 3.6 3.2 1.45 0.95 400 0.8 5.7 3.8 3.4 1.55 1.2 500 1.2 6.8 3.6 3.2 1.45 0.95 400 0.8 5.7 3.8 3.4 1.55 1.2 500 1.2 6.8 V V V A mA A W Full 60°C 60°C 60°C Full 60°C Full Full 60°C 60°C Full Full 60°C 60°C IV V V V IV V IV IV IV IV IV IV IV IV 0.4 100 35 ±3 0.4 50 2.0 3.4 0.9 1.7 20 30 0.7 50 160 0.8 6 1 2 0.4 100 35 ±3 0.4 50 2.0 3.4 0.9 1.7 20 30 0.7 50 160 0.8 6 1 2 V Ω pF V V p-p Ω V V mA mA V V μA μA Rev. A | Page 3 of 28 AD12401 Parameter LOGIC OUTPUTS (DRA, DRB, OUTPUT BITS) 3 Differential Output Voltage Output Common-Mode Voltage Output High Voltage Output Low Voltage 1 2 3 Case Temp Full Full 60°C 60°C Test Level IV IV IV IV Min AD12401-xxxKWS Typ Max 350 1.25 454 1.375 1.602 AD12401-xxxJWS Min Typ Max 247 1.125 0.898 350 1.25 454 1.375 1.602 Unit mV V V V 247 1.125 0.898 Tested using input frequency of 70 MHz (see Figure 17). Refer to Table 8 for logic convention on all logic inputs. Digital output logic levels: VC = 3.3 V, CLOAD = 8 pF, 2.5 V LVDS, RT = 100 Ω. AC SPECIFICATIONS 1 —ENCODE = 400 MSPS VA = 3.7 V, VC = 3.3 V, VD = 1.5 V, ENCODE = 400 MSPS, 0°C ≤ TCASE ≤ 60°C, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE SNR Analog Input 10 MHz @ −1.0 dBFS 70 MHz 128 MHz 175 MHz SINAD 2 Analog Input 10 MHz @ −1.0 dBFS 70 MHz 128 MHz 175 MHz Spurious-Free Dynamic Range 3 Analog Input 10 MHz @ −1.0 dBFS 70 MHz 128 MHz 175 MHz Image Spur 4 Analog Input 10 MHz @ −1.0 dBFS 70 MHz 128 MHz 175 MHz Offset Spur4 Analog Input @ −1.0 dBFS Two-Tone IMD 5 F1, F2 @ −6 dBFS ANALOG INPUT Frequency Range DIGITAL INPUT (DR_EN) Minimum Time (Low) SWITCHING SPECIFICATIONS Conversion Rate 6 Encode Pulse Width High (tEH)1 Encode Pulse Width Low (tEL)1 Case Temp Test Level AD12401-400KWS Min Typ Max AD12401-400JWS Min Typ Max Unit Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 60°C 60°C Full Full Full 60°C 60°C I I I I I I I I I I I I I I I I V V IV IV IV V V 62 61.5 60 60 59 58.5 57.5 55 69 69 66 62 60 60 60 57 64 63.5 63 62.5 63.5 63 61.5 60 85 80 72 68 75 72 66 63 65 −75 60 59.5 58 57.5 57 56.5 55.5 53 69 69 66 62 60 60 60 57 62 61.5 61 60.5 61.5 61 59.5 58 85 80 72 68 75 72 66 63 65 −75 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc 175 MHz ns 10 5.0 396 400 1.25 1.25 175 10 5.0 404 396 400 1.25 1.25 404 MSPS ns ns Rev. A | Page 4 of 28 AD12401 Parameter DIGITAL OUTPUT PARAMETERS Valid Time (tV) Propagation Delay (tPD) Rise Time, tR (20% to 80%) Fall Time, tF (20% to 80%) DR Propagation Delay (tEDR) Data to DR Skew (tEDR − tPD) Pipeline Latency 7 Start-Up Time Postprocessing Configuration Time APERTURE DELAY (tA) APERTURE UNCERTAINTY (Jitter, tJ) 1 2 Case Temp Full 60°C 60°C 60°C 60°C 60°C Full Full Full 60°C 60°C Test Level IV V V V V V IV IV IV V V AD12401-400KWS Min Typ Max 3.9 8.7 0.3 0.3 11.2 2.5 74 44 2.8 2.3 0.4 AD12401-400JWS Min Typ Max 3.9 8.7 0.3 0.3 11.2 2.5 74 44 2.8 2.3 0.4 Unit ns ns ns ns ns ns Cycles ms sec ns ps rms 29 87 29 87 All ac specifications tested with a single-ended, 2.0 V p-p encode on ENCODE and ENCODE floating. The image spur is included in the SINAD measurement. 3 The image spur is not included in the SFDR specification. 4 The image spur is at fS/2 – AIN; the offset spur is at fS/2. 5 F1 = 70 MHz, F2 = 73 MHz. 6 Parts are tested with 400 MSPS encode. Device can be clocked at lower encode rates, but specifications are not guaranteed. Specifications are guaranteed by design for encode 400 MSPS ± 1%. 7 Pipeline latency is exactly 74 cycles with an additional tPD required for data to emerge. AC SPECIFICATIONS 1 —ENCODE = 360 MSPS VA = 3.7 V, VC = 3.3 V, VD = 1.5 V, encode = 360 MSPS, 0°C ≤ TCASE ≤ 60°C, unless otherwise noted. Table 3. Parameter DYNAMIC PERFORMANCE SNR Analog Input 10 MHz @ −1.0 dBFS 70 MHz 128 MHz SINAD 2 Analog Input 10 MHz @ −1.0 dBFS 70 MHz 128 MHz Spurious-Free Dynamic Range 3 Analog Input 10 MHz @ −1.0 dBFS 70 MHz 128 MHz Image Spur 4 Analog Input 10 MHz @ −1.0 dBFS 70 MHz 128 MHz Offset Spur4 Analog Input @ −1.0 dBFS Two-Tone IMD 5 F1, F2 @ −6 dBFS ANALOG INPUT Frequency Range DIGITAL INPUT (DR_EN) Minimum Time (Low) Case Temp Test Level Min AD12401-360KWS Typ Max Unit Full Full Full Full Full Full Full Full Full Full Full Full 60°C 60°C Full Full I I I I I I I I I I I I V V IV IV Rev. A | Page 5 of 28 62 61.5 60 59 58.5 57.5 69 69 66 60 60 60 64 63.5 63 63.5 63 61.5 85 80 72 75 72 66 65 −75 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc 160 MHz ns 10 5.6 AD12401 Parameter SWITCHING SPECIFICATIONS Conversion Rate 6 Encode Pulse Width High (tEH)1 Encode Pulse Width Low (tEL)1 DIGITAL OUTPUT PARAMETERS Valid Time (tV) Propagation Delay (tPD) Rise Time, tR (20% to 80%) Fall Time, tF (20% to 80%) DR Propagation Delay (tEDR) Data to DR Skew (tEDR − tPD) Pipeline Latency 7 Start-Up Time Postprocessing Configuration Time APERTURE DELAY (tA) APERTURE UNCERTAINTY (Jitter, tJ) 1 2 3 Case Temp Full 60°C 60°C Full 60°C 60°C 60°C 60°C 60°C Full Full Full 60°C 60°C Test Level IV V V IV V V V V V IV IV IV V V Min 356 AD12401-360KWS Typ Max 360 1.38 1.38 4.5 8.7 0.3 0.3 11.5 2.8 74 44 2.3 0.4 364 Unit MSPS ns ns ns ns ns ns ns ns Cycles ms sec ns ps rms 29 87 3.1 All ac specifications tested with a single-ended, 2.0 V p-p encode on ENCODE and ENCODE floating. The image spur is included in the SINAD specification. The image spur is not included in the SFDR specification. 4 The image spur is at fS/2 – AIN; the offset spur is at fS/2. 5 F1 = 70 MHz, F2 = 73 MHz. 6 Parts are tested with 360 MSPS encode. Device can be clocked at lower encode rates, but specifications are not guaranteed. Specifications are guaranteed by design for encode 360 MSPS ± 1%. 7 Pipeline latency is exactly 74 cycles with an additional tPD required for data to emerge. AC SPECIFICATIONS 1 —ENCODE = 326 MSPS VA = 3.7 V, VC = 3.3 V, VD = 1.5 V, ENCODE = 326 MSPS, 0°C ≤ TCASE ≤ 60°C, unless otherwise noted. Table 4. Parameter DYNAMIC PERFORMANCE SNR Analog Input 10 MHz @ −1.0 dBFS 70 MHz 128 MHz SINAD 2 Analog Input 10 MHz @ −1.0 dBFS 70 MHz 128 MHz Spurious-Free Dynamic Range 3 Analog Input 10 MHz @ −1.0 dBFS 70 MHz 128 MHz Image Spur 4 Analog Input 10 MHz @ −1.0 dBFS 70 MHz 128 MHz Offset Spur5 Analog Input @ −1.0 dBFS Two-Tone IMD 5 F1, F2 @ −6 dBFS Case Temp Test Level AD12401-326KWS Min Typ Max AD12401-326JWS Min Typ Max Unit Full Full Full Full Full Full Full Full Full Full Full Full 60°C 60°C I I I I I I I I I I I I V V Rev. A | Page 6 of 28 62 61.5 60 59 58.5 57.5 69 69 66 60 60 60 64 63.5 63 63.5 63 61.5 85 80 72 75 72 66 65 −75 60 59.5 58 57 56.5 55.5 69 69 66 60 60 60 62 61.5 61 61.5 61 59.5 85 80 72 75 72 66 65 −75 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBc AD12401 Parameter ANALOG INPUT Frequency Range DIGITAL INPUT (DR_EN) Minimum Time (Low) SWITCHING SPECIFICATIONS Conversion Rate 6 Encode Pulse Width High (tEH)1 Encode Pulse Width Low (tEL)1 DIGITAL OUTPUT PARAMETERS Valid Time (tV) Propagation Delay (tPD) Rise Time, tR (20% to 80%) Fall Time, tF (20% to 80%) DR Propagation Delay (tEDR) Data to DR Skew (tEDR − tPD) Pipeline Latency 7 Start-Up Time Postprocessing Configuration Time APERTURE DELAY (tA) APERTURE UNCERTAINTY (Jitter, tJ) 1 2 Case Temp Full Full Full 60°C 60°C Full 60°C 60°C 60°C 60°C 60°C Full Full Full 60°C 60°C Test Level IV IV IV V V IV V V V V V IV IV IV V V AD12401-326KWS Min Typ Max 10 6.2 323 326 1.53 1.53 5.0 8.7 0.3 0.3 11.8 3.1 74 44 2.3 0.4 329 140 AD12401-326JWS Min Typ Max 10 6.2 323 326 1.53 1.53 5.0 8.7 0.3 0.3 11.8 3.1 74 44 2.3 0.4 329 140 Unit MHz ns MSPS ns ns ns ns ns ns ns ns Cycles ms sec ns ps rms 29 87 3.4 29 87 3.4 All ac specifications tested with a single-ended, 2.0 V p-p encode on ENCODE and ENCODE floating. The image spur is included in the SINAD measurement. 3 The image spur is not included in the SFDR specification. 4 The image spur is at fS/2 − AIN; the offset spur is at fS/2. 5 F1 = 70 MHz, F2 = 73 MHz. 6 Parts are tested with 326 MSPS encode. Device can be clocked at lower encode rates, but specifications are not guaranteed. Specifications are guaranteed by design for encode 326 MSPS ±1%. 7 Pipeline latency is exactly 74 cycles with an additional tPD required for data to emerge. Rev. A | Page 7 of 28 AD12401 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter VA to AGND VC to DGND VD to DGND Analog Input Voltage Analog Input Power ENCODE Input Voltage ENCODE Input Power Logic Inputs Storage Temperature Range, Ambient Operating Temperature Range Value 5V 4V 1.6 V max 6 V (dc) 18 dBm (ac) 6 V (dc) 12 dBm (ac) −0.3 V to +4 V −65°C to +150°C 0°C to 60°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. EXPLANATION OF TEST LEVELS Table 6. Level I II III IV V VI Description 100% production tested. 100% production tested at 25°C and sample tested at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 8 of 28 AD12401 Table 7. Output Coding (Twos Complement) Code 4095 . . . 2048 2047 . . 0 KWS +1.6 . . . 0 −0.000781 to . . −1.6 to AIN ( V) JWS +0.8 . . . 0 +0.0003905 . . +0.8 Digital Output 0111 1111 1111 . . . 0000 0000 0000 1111 1111 1111 . . 1000 0000 0000 Table 8. Option Pin List with Necessary Associated Circuitry Pin Name RESET DR_EN Active High Low High Logic Level Type LVTTL LVTTL Default Level High High Associated Circuitry Within Part 3.74 kΩ Pull-Up Weak Pull-Up (>16 kΩ) 3.3V 100Ω ENCODE 3.3V 100Ω ENCODE 100Ω 100Ω PECL DRIVER 05649-002 05649-004 Figure 2. ENCODE Equivalent Circuit N–1 N N+1 N+2 N+3 tEL tEH ENC 400MHZ 1/fS 74 CLOCK CYCLES DATA OUT A DRA DRA N – 74 N – 73 N N+2 N+4 1 N+6 N+8 1 DATA OUT B DRB DRB DR_EN NOTES 1. DATA LOST DUE TO ASSERTION OF DR_EN. LATENCY OF 74 ENCODE CLOCK CYCLES BEFORE DATA VALID. 2. IF A SINGLE-ENDED SINE WAVE IS USED FOR ENCODE, USE THE ZERO CROSSING POINT (AC-COUPLED) AS THE 50% POINT AND APPLY THE SAME TIMING INFORMATION. 3. THE DR_EN PIN IS USED TO SYNCHRONIZE THE COLLECTION OF DATA INTO EXTERNAL BUFFER MEMORIES. THE DR_EN PIN CAN BE APPLIED SYNCHRONOUSLY OR ASYNCHRONOUSLY TO THE AD12401. IF APPLIED ASYNCHRONOUSLY, DR_EN MUST BE HELD LOW FOR A MINIMUM OF 5ns TO ENSURE CORRECT OPERATION. THE FUNCTION SHUTS OFF DRA AND DRB UNTIL THE DR_EN PIN IS SET HIGH AGAIN. DRA AND DRB RESUME ON THE NEXT VALID DRA AFTER DR_EN IS RETURNED HIGH. IF THIS FEATURE IS NOT REQUIRED, TIE THIS PIN TO 3.3V THROUGH A 3.74kΩ RESISTOR OR LEAVE IT FLOATING. N+1 N+3 N+5 N+7 Figure 3. Timing Diagram tEDR ENC ENC tPD DATA OUT tVD DR DR Figure 4. Highlighted Timing Diagram Rev. A | Page 9 of 28 05649-003 AD12401 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AIN PIN 1 PIN 119 VA VA VA VA AGND AGND DNC DNC H/L_GAIN DNC DNC DNC AGND AGND AGND AGND AGND AGND AGND AGND DNC DR_EN DA1 DA1 DA3 DA3 DA5 DA5 DA7 DA7 DA9 DA9 DA11 DA11 DNC DNC VD VD VD VD DB1 DB1 DB3 DB3 DB5 DB5 DB7 DB7 DB9 DB9 DB11 DB11 DNC DNC DNC DNC DNC RESET VC VC 1 ENC ENC TOP VIEW VA VA VA VA AGND AGND DNC DNC DNC DNC DNC DNC DNC AGND AGND AGND AGND AGND AGND AGND DRA DRA DA0 DA0 DA2 DA2 DA4 DA4 DA6 DA6 DA8 DA8 DA10 DA10 DNC DNC VD VD VD VD PIN 120 C JOHNSON SMA-50 Ω CONNECT NO. 142-0711-821 PIN 79 1 PIN 80 2-56 STUDS 4 ⋅ END VIEW SAMTEC CONNECTOR QTE-060-01-L-D-A-K-TR ENC BOARD B ENC 1 PIN 39 AIN BOTTOM VIEW NOTE: 1. FOR MATING CONNECTOR, USE SAMTEC, INC. PART NO. QSE-60-01-L-D-A-K. INTEGRAL GROUND PLANE CONNECTIONS. SECTION A = DGND, PINS 121–124. SECTION B = DGND, PINS 125–128. SECTION C = AGND, PINS 129–132. LEFT SIDE VIEW PIN 1 PIN 2 Figure 5. Pin Configuration Rev. A | Page 10 of 28 05649-005 DB0 DB0 DB2 DB2 DB4 DB4 DB6 DB6 DB8 DB8 DB10 DB10 OROUT OROUT DRB DRB DNC DNC VC VC PIN 40 A AD12401 Table 9. Pin Function Descriptions Pin No. 1 to 4 5 6 to 9, 11, 13 ,15, 49 to 52, 79, 96 to 102, 104 to108 10 12 14 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 to 48 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Mnemonic VC RESET DNC Description Digital Supply, 3.3 V. LVTTL. 0 = device reset. Minimum width = 200 ns. Device resumes operation after 600 ms maximum. Do Not Connect. DRB DRB OROUT OROUT DB11 DB10 DB11 DB10 DB9 DB8 DB9 DB8 DB7 DB6 DB7 DB6 DB5 DB4 DB5 DB4 DB3 DB2 DB3 DB2 DB1 DB0 DB1 DB0 VD DA11 DA10 DA11 DA10 DA9 DA8 DA9 DA8 DA7 DA6 DA7 DA6 DA5 DA4 DA5 DA4 Channel B Data Ready. Complement output. Channel B Data Ready. True output. Overrange. Complement output. Overrange. True Output 1 = overranged, 0 = normal operation. Channel B Data Bit 11. Complement output bit. Channel B Data Bit 10. Complement output bit. Channel B Data Bit 11. True output bit. Channel B Data Bit 10. True output bit. Channel B Data Bit 9. Complement output bit. Channel B Data Bit 8. Complement output bit. Channel B Data Bit 9. True output bit. Channel B Data Bit 8. True output bit. Channel B Data Bit 7. Complement output bit. Channel B Data Bit 6. Complement output bit. Channel B Data Bit 7. True output bit. Channel B Data Bit 6. True output bit. Channel B Data Bit 5. Complement output bit. Channel B Data Bit 4. Complement output bit. Channel B Data Bit 5. True output bit. Channel B Data Bit 4. True output bit. Channel B Data Bit 3. Complement output bit. Channel B Data Bit 2. Complement output bit. Channel B Data Bit 3. True output bit. Channel B Data Bit 2. True output bit. Channel B Data Bit 1. Complement output bit. Channel B Data Bit 0. Complement output bit. DB0 is LSB. Channel B Data Bit 1. True output bit. Channel B Data Bit 0. True output bit. DB0 is LSB. Digital Supply, 1.5 V. Channel A Data Bit 11. Complement output bit. Channel A Data Bit 10. Complement output bit. Channel A Data Bit 11. True output bit. Channel A Data Bit 10. True output bit. Channel A Data Bit 9. Complement output bit. Channel A Data Bit 8. Complement output bit. Channel A Data Bit 9. True output bit. Channel A Data Bit 8. True output bit. Channel A Data Bit 7. Complement output bit. Channel A Data Bit 6. Complement output bit. Channel A Data Bit 7. True output bit. Channel A Data Bit 6. True output bit. Channel A Data Bit 5. Complement output bit. Channel A Data Bit 4. Complement output bit. Channel A Data Bit 5. True output bit. Channel A Data Bit 4. True output bit. Rev. A | Page 11 of 28 AD12401 Pin No. 69 70 71 72 73 74 75 76 77 78 80 103 81 to 95, 109 to 112, 129 to 132 1 113 to 120 121 to 1281 1 Mnemonic DA3 DA2 DA3 DA2 DA1 DA0 DA1 DA0 DR_EN DRA DRA H/L GAIN AGND VA DGND Description Channel A Data Bit 3. Complement output bit. Channel A Data Bit 2. Complement output bit. Channel A Data Bit 3. True output bit. Channel A Data Bit 2. True output bit. Channel A Data Bit 1. Complement output bit. Channel A Data Bit 0. Complement output bit. DA0 is LSB. Channel A Data Bit 1. True output bit. Channel A Data Bit 0. True output bit. DA0 is LSB. Data Ready Enable, Typically DNC. See the DR_EN section. Channel A Data Ready. Complement output. Channel A Data Ready. True output. Gain Select Pin. Ground for low gain mode (KWS); pull up to 3.3 V for high gain mode (JWS). Analog Ground. Analog Supply, 3.7 V. Digital Ground. Internal ground plane connections: Section A = DGND, Pin 121 to Pin 124; Section B = DGND, Pin 125 to Pin 128; Section C = AGND, Pin 129 to Pin 132. Rev. A | Page 12 of 28 AD12401 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point on the rising edge of the ENCODE command and the instant at which the analog input is sampled. Analog Input VSWR (50 Ω) VSWR is a ratio of the transmitted and reflected signals. The VSWR can be related to input impedance. Γ = (ZL − ZS)/(ZL + ZS) where: ZL = actual load impedance. ZS = reference impedance. VSWR = (1 − |Γ|)/(1 +|Γ|) Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step. Distortion, Image Spur The ratio of the rms signal amplitude to the rms signal amplitude of the image spur, reported in dBFS. The image spur, a result of gain and phase errors between two time-interleaved conversion channels, is located at fS/2 − fAIN. Distortion, Offset Spur The ratio of the rms signal amplitude to the rms signal amplitude of the offset spur, reported in dBFS. The offset spur, a result of offset errors between two time-interleaved conversion channels, is located at fS/2. Effective Number of Bits (ENOB) Calculated from the measured SNR based on the equation Full-Scale Input Power Expressed in dBm. Computed using the equation POWERFull-Scale = 10 log ((V2Full-Scalerms)/(|ZINPUT| × 0.001)) Full-Scale Input Voltage Range The maximum peak-to-peak input signal magnitude that results in a full-scale response, 0 dBFS on a single-tone input signal case. Any magnitude increase from this value results in an overrange condition. Gain Error The difference between the measured and ideal full-scale input voltage range of the ADC. Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBFS. Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBFS. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least square curve fit. Maximum Conversion Rate The maximum ENCODE rate at which the image spur calibration degrades no more than 1 dB (when the image spur is 70 dB). Minimum Conversion Rate The minimum ENCODE rate at which the image spur calibration degrades no more than 1 dB (when the image spur is 70 dB). Offset Error The dc offset imposed on the input signal by the ADC, reported in LSB (codes). Output Propagation Delay The delay between a differential crossing of ENCODE and ENCODE (or zero crossing of a single-ended ENCODE). Pipeline Latency The number of clock cycles the output data lags the corresponding clock cycle. Power Supply Rejection Ratio (PSRR) The ratio of power supply voltage change to the resulting ADC output voltage change. ENOB = SNRMEASURED − 1.76 dB 6.02 ENCODE Pulse Width/Duty Cycle Pulse width high is the minimum amount of time the ENCODE pulse should be left in Logic 1 state to achieve rated performance; pulse width low is the minimum time the ENCODE pulse should be left in low state. Rev. A | Page 13 of 28 AD12401 Signal-to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc and image spur. Signal-to-Noise Ratio (SNR) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component, except the image spur. The peak spurious component may or may not be a harmonic. It can be reported in dBc (that is, degrades as signal level is lowered) or dBFS (always related back to converter full-scale). Total Noise Calculated as ( FSdBm − SNRdBc − SignaldBFS ) 10 VNOISE = Z × 0.001 × 10 where: Z is the input impedance. FS is the full scale of the device for the frequency in question. SNR is the value of the particular input level. Signal is the signal level within the ADC reported in dB below full scale. This value includes both thermal and quantization noise. Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product; reported in dBc. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. It can be reported in dBc (that is, degrades as signal level is lowered) or in dBFS (always related back to converter full-scale). Rev. A | Page 14 of 28 AD12401 TYPICAL PERFORMANCE CHARACTERISTICS 0 –10 –20 –30 –40 1 0 SNR = 63.26dB SFDR = 76.77dBc SINAD = 62.97dB IMAGE SPUR = –76.69dBc –10 –20 –30 –40 SNR = 60.74dB SFDR = 71.57dBc SINAD = 60.29dB IMAGE SPUR = –82.52dBc 1 dB –60 –70 X –80 2 –90 –100 –110 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 3 4 5 6 05649-006 dB –50 –50 –60 –70 2 X 5 4 3 N 6 05649-009 N –80 –90 –100 –110 0 200 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 200 Figure 6. FFT: fS = 400 MSPS, AIN = 10.123 MHz @ –1.0 dBFS; X = Image Spur, N = Interleaved Offset Spur 0 –10 –20 –30 –40 1 SNR = 62.61dB SFDR = 78.03dBc SINAD = 62.41dB IMAGE SPUR = –86.28dBc Figure 9. FFT: fS = 400 MSPS, AIN = 175.123 MHz @ –1.0 dBFS; X = Image Spur, N = Interleaved Offset Spur 0 –10 –20 –30 –40 12 dB dB –50 –60 –70 2 –80 –90 –100 –110 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 6 5 X 4 05649-007 –50 –60 2F1 – F2 3 N –80 –90 –100 –110 0 F2 – F1 2F1 + F2 2F2 + F1 –70 2F2 – F1 F2 + F1 200 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 200 Figure 7. FFT: fS = 400 MSPS, AIN = 70.123 MHz @ –1.0 dBFS; X = Image Spur, N = Interleaved Offset Spur 0 –10 –20 –30 –40 SNR = 61.54dB SFDR = 74.03dBc SINAD = 60.92dB IMAGE SPUR = –75.09dBc 0 –10 –20 –30 –40 Figure 10. Two-Tone Intermodulation Distortion (25.1 MHz and 28.1 MHz; fS = 400 MSPS); X = Image Spur, N = Interleaved Offset Spur 12 1 dB dB –50 –60 –70 –80 –90 –100 –110 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 6 4 5 05649-008 –50 –60 2F1 – F2 N –80 –90 –100 –110 0 F2 + F1 3 X 2F2 – F1 2 2F2 + F1 2F1 + F2 160 180 200 05649-011 –70 200 20 40 60 80 100 120 140 FREQUENCY (MHz) Figure 8. FFT: fS = 400 MSPS, AIN = 128.123 MHz @ –1.0 dBFS; X = Image Spur, N = Interleaved Offset Spur Figure 11. Two-Tone Intermodulation Distortion (70.1 MHz and 73.1 MHz; fS = 400 MSPS); X = Image Spur, N = Interleaved Offset Spur Rev. A | Page 15 of 28 F2 + F1 05649-010 AD12401 0 –10 –20 –30 –40 12 95 IMAGE SPUR 90 THIRD HARMONIC 85 HARMONICS (dBc) dB –50 80 75 SECOND HARMONIC 70 65 60 0 20 40 60 80 100 120 140 160 180 ANALOG INPUT FREQUENCY (MHz) 2F1 – F2 –70 –80 –90 2F1 + F2 2F2 + F1 F2 – F1 F2 + F1 2F2 – F1 –60 05649-012 –100 –110 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 200 Figure 12. Two-Tone Intermodulation Distortion (172.1 MHz and 175.1 MHz; fS = 400 MSPS), SFDR = 70 dBc; X = Image Spur, N = Interleaved Offset Spur 0.5 0.4 0.3 0.2 GAIN (dB) Figure 15. Harmonics vs. Analog Input Frequency 64.5 64.0 63.5 63.0 SNR (dBFS) 0.1 0 –0.1 –0.2 –0.3 05649-040 62.5 62.0 61.5 61.0 60.5 60.0 59.5 0 50 100 150 05649-016 –0.4 –0.5 10.7 35.0 59.3 83.6 108 132 157 181 205 229 200 FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) Figure 13. Interleaved Gain Flatness 100 THIRD HARMONIC 95 90 DISTORTION (dBFS) 0.9 1.0 Figure 16. SNR vs. Analog Input Frequency VD SUPPLY CURRENT (A) 0.8 0.7 85 80 IMAGE SPUR 75 70 05649-041 SECOND HARMONIC 0.6 0.5 0.4 60 0 10 20 30 40 50 ANALOG INPUT LEVEL (dB) 60 70 0.3 0 20 40 60 80 100 120 140 160 180 200 INPUT FREQUENCY (MHz) Figure 14. Second/Third Harmonics and Image Spur vs. Analog Input Level; fS = 400 MSPS, AIN = 70 MHz Figure 17. VD Supply Current vs. AIN Frequency Rev. A | Page 16 of 28 05649-017 65 05649-042 AD12401 –1.00 –1.42 –1.84 ANALOG INPUT LEVEL –2.26 –2.68 –3.10 –3.52 –3.94 –4.36 –4.78 05649-043 –5.20 0.100 0.530 0.960 1.390 1.820 2.250 2.680 3.110 3.540 3.970 4.400 ANALOG INPUT FREQUENCY Figure 18. Low Frequency Gain Flatness Rev. A | Page 17 of 28 AD12401 THEORY OF OPERATION The AD12401 uses two high speed, 12-bit ADCs in a timeinterleaved configuration to double the sample rate, while maintaining a high level of dynamic range performance. The digital output of each ADC channel is calibrated using a proprietary digital postprocessing technique, Advanced Filter Bank (AFB). AFB is implemented using a state-of-the-art field programmable gate array (FPGA) and provides a wide bandwidth and wide temperature match for any gain, phase, and clock timing errors between each ADC channel. The relationship between image spur and channel mismatches is captured in Table 10 for specific conditions. Table 10. Image Spur vs. Channel Mismatch Gain Error (%) 1 0.25 0.2 0.025 Aperture Delay Error (ps) 15 2.7 1.1 0.5 Image Spur (dBc) –40 –54 –62 –70 TIME-INTERLEAVING ADCS When two ADCs are time-interleaved, gain and/or phase mismatches between each channel produce an image spur at fS/2 − fAIN and an offset spur, as shown in Figure 19. These mismatches can be the result of any combination of device tolerance, temperature, and frequency deviations. 0 –10 –20 –30 –40 –50 dB For a more detailed description of time-interleaving in ADCs and a design example using the AD12401, see Advanced Digital PostProcessing Techniques Enhance Performance in Time-Interleaved ADC Systems, which was published in the August, 2003 edition of the Analog Dialogue (www.analog.com/analogDialogue). ANALOG INPUT The AD12401 analog input is ac-coupled using a proprietary transformer front-end circuit that provides 1 dB of gain flatness over the first Nyquist zone and a −3 dB bandwidth of 480 MHz. This front-end circuit provides a VSWR of 1.5 (50 Ω) over the first Nyquist zone, and the typical full-scale input is 3.2 V p-p. The Mini-Circuits® HELA-10 amplifier module can be used to drive the input at these power levels. 1 IMAGE SPUR X OFFSET SPUR –60 –70 –80 –90 –100 –110 –120 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 200 05649-018 N 2 3 6 CLOCK INPUT 4 5 Figure 19. Image Spur due to Mismatches Between Two Interleaved ADCs (No AFB Digital Postprocessing) Figure 20 shows the performance of a similar converter with on-board AFB postprocessing implemented. The –44 dBFS image spur has been reduced to –77 dBFS and, as a result, the dynamic range of this time-interleaved ADC is no longer limited by the channel matching. 0 –10 –20 –30 –40 –50 dB The AD12401 requires a 400 MSPS ENCODE that is divided by 2 and distributed to each ADC channel, 180° out of phase from each other. Internal ac-coupling and bias networks provide the framework for flexible clock input requirements that include single-ended sine wave, single-ended PECL, and differential PECL. While the AD12401 is tested and calibrated using a single-ended sine wave, properly designed PECL circuits that provide fast slew rates (>1 V/ns) and minimize ringing result in comparable dynamic range performance. Aperture jitter and harmonic content are two major factors to consider when designing the input clock circuit for the AD12401. The relationship between aperture jitter and SNR can be characterized using the following equation. The equation assumes a full-scale, single-tone input signal. SNR = 2⎤ ⎡ 2 1 ⎛ 1 + ε ⎞ ⎛ 2 2 × VNOISErms ⎞ ⎥ ⎟ − 20log ⎢ (20π × f A × 0 t JRMS ) 2 + ×⎜ N ⎟ + ⎜ ⎟⎥ ⎢ 1. 5 ⎝ 2 ⎠ ⎜ 2N ⎝ ⎠⎥ ⎢ ⎣ ⎦ 1 –60 –70 –80 –90 –100 –110 –120 0 20 40 X IMAGE SPUR 3 2 6 N OFFSET SPUR where: 5 4 60 80 100 120 140 FREQUENCY (MHz) 160 180 200 fA = input frequency. tJRMS = aperture jitter. N = ADC resolution (bits). ε = ADCDNL (LSB). VNOISErms = ADC input noise (LSB rms). Figure 20. AD12401 with AFB Digital Postprocessing Rev. A | Page 18 of 28 05649-019 AD12401 Figure 21 displays the application of this relationship to a fullscale, single-tone input signal on the AD12401, where the DNL was assumed to be 0.4 LSB, and the input noise was assumed to be 0.8 LSB rms. The vertical marker at 0.4 ps displays the SNR at the jitter level present in the AD12401 evaluation system, including the jitter associated with the AD12401 itself. 65 AIN = 10MHz 64 63 62 AIN = 65MHz While this product was designed to provide good PSRR performance, system designers need to be aware of the risks associated with switching power supplies and consider using linear regulators in their high speed ADC systems. Switching power supplies typically produces both conducted and radiated energy that result in common-/differential-mode EMI currents. Any system that requires 12-bit performance has very little room for errors associated with power supply EMI. For example, a system goal of 74 dB dynamic range performance on the AD12401 requires noise currents that are less than 4.5 μA and noise voltages of less than 225 μV in the analog input path. SNR (dB) AIN = 128MHz 61 60 59 AIN = 180MHz 05649-020 STARTUP AND RESET The AD12401’s FPGA configuration is stored in the on-board EPROM and loaded into the FPGA when power is applied to the device. The RESET pin (active low) allows the user to reload the FPGA in case of a low digital supply voltage condition or a power supply glitch. Pulling the RESET pin low pulls the dataready and output bits high until the FPGA is reloaded. The RESET pin should remain low for a minimum of 200 ns. On the rising edge of the reset pulse, the AD12401 starts loading the configuration into the FPGA. The reload process requires a maximum of 87 ms to complete. Valid signals on the data-ready pins indicate the reset process is complete. In addition, system designers must be aware of the thermal conditions of the AD12401 at startup. If large thermal imbalances are present, the AD12401 can require additional time to stabilize before providing specified image spur performance. 58 57 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 APERTURE JITTER (ps rms) 0.8 0.9 1.0 Figure 21. SNR vs. Aperture Jitter In addition to jitter, the harmonic content of the single-ended sine wave clock sources must be controlled. The clock source used in the test and calibration process has a harmonic performance that is better than 60 dBc. Additionally, when using PECL or other square-wave clock sources, unstable behavior, such as overshoot and ringing, can affect phase matching and degrade the image spur performance. DR_EN The DR_EN pin is used to synchronize the collection of data into external buffer memories. DR_EN must be held low for a minimum amount of time (see Table 2 through Table 4 for each ENCODE rate) to ensure correct operation. The function shuts off DRA and DRB until the DR_EN pin is set high again. DRA and DRB resume on the next valid DRA after DR_EN is released. If this feature is not required, tie this pin to 3.3 V through a 3.74 kΩ. DIGITAL OUTPUTS The AD12401’s digital postprocessing circuit provides two parallel, 12-bit, 200 MSPS data output buses. By providing two output busses that operate at one half the conversion rate, the AD12401 eliminates the need for large, expensive, high power demultiplexing circuits. The output data format is twos complement, maintaining the standard set by other high speed ADCs, such as the AD9430 and AD6645. Data-ready signals are provided for facilitating proper timing in the data capture circuit. OVERRANGE The differential OROUT pins are used to determine if the AD12401 input is overranged. OROUT timing is identical to the Channel B data. If the OROUT pin is high, then the Channel B data coincident with the overrange indication or the Channel A data immediately preceding it resulted from an overrange input. If the OROUT pin is low, the operation is normal. POWER SUPPLIES The AD12401 requires three different supply voltages: a 1.5 V supply for the digital postprocessing circuit, a 3.3 V supply to facilitate digital I/O through the system, and a 3.8 V supply for the analog conversion and clock distribution circuits. The AD12401 incorporates two key features that result in solid PSRR performance. First, on-board linear regulators are used to provide an extra level of power supply rejection for the analog circuits. The linear regulator used to supply the ADCs provides an additional 60 dB of rejection at 100 kHz. Second, to address higher frequency noise (where the linear regulators’ rejection degrades), the AD12401 incorporates high quality ceramic decoupling capacitors. Rev. A | Page 19 of 28 AD12401 GAIN SELECT The AD12401 is graded out for the gain mode and should be ordered accordingly: the AD12401-xxxKWS is calibrated in the low gain mode, and the AD12401-xxxJWS is calibrated in the high gain mode. Performance is not guaranteed if either grade is used in the wrong gain mode. The high gain mode sets the analog input voltage to approximately 1.6 V p-p. The low gain mode sets the analog input voltage to approximately 3.2 V p-p. For high gain mode, the user should pull Pin 103 (H/L_GAIN) up to 3.3 V using a 4.02 kΩ resistor. For low gain mode, the user should ground Pin 103. From a channel-matching perspective, the most important consideration is external thermal influences. It is possible for thermal imbalances in the end application to adversely affect the dynamic performance. Due to the temperature dependence of the image spur, substantial deviation from the factory calibration conditions can have a detrimental effect. Unbalanced thermal influences can cause gradients across the module, and performance degradation can result. Examples of unbalanced thermal influences can include large heat dissipating elements near one side of the AD12401, or obstructed airflow that does not flow uniformly across the module. The thermal sensitivity of the module can be affected by a change in thermal gradient across the module of 2°C. 110 100 TYPICAL JUNCTION 90 THERMAL CONSIDERATIONS The module is rated to operate over a case temperature of 0°C to 60°C. To maintain the tight channel matching and reliability of the AD12401, care must be taken to ensure that proper thermal and mechanical considerations have been made and addressed to ensure case temperature is kept within this range. Each application requires evaluation of the thermal management as applicable to the system design. This section provides information that should be used in the evaluation of the AD12401’s thermal management for each specific use. In addition to the radiation of heat into its environment, the AD12401 module enables the flow of heat through the mounting studs and standoffs as they contact the motherboard. As described in the Package Integrity/Mounting Guidelines section, the module should be secured to the motherboard using 2-56 nuts (washer use is optional). The torque on the nuts should not exceed 32-inch ounces. Using a thermal grease at the standoffs results in better thermal coupling between the board and module. Depending on the ambient conditions, airflow can be necessary to ensure the components in the module do not exceed their maximum operating temperature. For reliability, the most sensitive component has a maximum junction temperature rating of 125°C. Figure 22 and Figure 23 provide a basic guideline for two key thermal management decisions: the use of thermal interface material between the module bottom cover/mother board and airflow. Figure 21 characterizes the typical thermal profile of an AD12401 that is not using thermal interface material. Figure 22 provides the same information for a configuration that uses gap-filling thermal interface material. In this case, Thermagon T-flex 600 Series™, 0.040” thickness, was used. These profiles show that the maximum die temperature is reduced by approximately 2°C when thermal interface material is used. Figure 22 and Figure 23 also provide a guideline for determining the airflow requirements for given ambient conditions. For example, a goal of 120°C die temperature in a 40°C ambient environment without the use of thermal interface material requires an airflow of 100 LFM. TEMPERATURE (°C) 80 70 60 CASE 50 40 30 20 NO AIRFLOW 100 LFM AIRFLOW CONDITION 300 LFM AMBIENT 05649-021 Figure 22. Typical Temperature vs. Airflow with No Module/Board Interface Material (Normalized to 60°C Module Case Temperature) 110 100 TYPICAL JUNCTION 90 TEMPERATURE (°C) 80 70 60 CASE 50 40 30 20 NO AIRFLOW 100 LFM AIRFLOW CONDITION 300 LFM AMBIENT 05649-022 Figure 23. Typical Temperature vs. Airflow with T-flex Module/Board Interface Material (Normalized to 60°C Module Case Temperature Ambient) PACKAGE INTEGRITY/MOUNTING GUIDELINES The AD12401 is a printed circuit board (PCB)-based module designed to provide mechanical stability and to support the intricate channel-to-channel matching necessary to achieve high dynamic range performance. The module should be secured to the motherboard using 2-56 nuts (washer use is optional). The torque on the nuts should not exceed 32-inch ounces. Rev. A | Page 20 of 28 AD12401 The SMA edge connectors (AIN and ENC/ENC) are surface mounted to the board to achieve minimum height of the module. When attaching and routing the cables, one must ensure they are stress-relieved and do not apply stress to the SMA connector/board. The presence of stress on the cables can degrade electrical performance and mechanical integrity of the module. In addition to the routing precautions, the smallest torque necessary to achieve consistent performance should be used to secure the system cable to the AD12401’s SMA connectors. The torque should never exceed 5-inch pounds. Any disturbances to the AD12401 structure, including removing the covers or mounting screws, invalidates the calibration and results in degraded performance. See the Outline Dimensions section for mounting stud dimensions, see Figure 38 for PCB interface locations. Mounting stud length typically accommodates a PCB thickness of 0.093". Consult sales if board thickness requirements exceed this dimension. ENCODE The single-ended or differential ENCODE signal connects directly to SMA connector(s) on the AD12401. A single-ended sine wave at 10 dBm connected to the ENCODE SMA is recommended. A low jitter clock source (