AD1341KZ

ANALOGDEVICES fAX-ON-DEHAND HOTLINE W - Page 39 l6-Channel ANALOG DEVICES DataAcquisition System AD1341 I FEATURES 150,000 Channels/Second Throughput Rate Analog Inputs 16 Single-Ended (SE) or 8 Differential (DE); Expandable to 32 SE or 16 DE Over Voltage Protected Power Supply loss Protected Programmable Gain Amplifier (PGA) Binary Gains 1 to 128 Independent Gain Selection per Channel 12-Bit Sampling A/D Converter Processor Interface FIFOs for Channel Control and Conversion Results Fully Asynchronous 16-Bit Parallel Bus 15 ns Data Access Time Selectable 16-Bit Data Format Programmable Interrupt Structure Ceramic Surface Mount Package OBS APPLICATIONS DSP Data Acquisition Missile Guidance Vibration Analysis Process Control FUNCTIONAL BLOCK DIAGRAM AEflN MU., oU'l PGA(-) IN DIPOLAR OPISET I REF OUT ",,"102 as "" Wi< AO1341 CH1S./CIfTI I I I , C-..cHC>- £>0-°" CH1. I I I I I CHO+ RSt OLE PRODUCT DESCRIPTION The AD1341 is a complete 16-channel data acquisition system optimized for use in multichannel control and digital signal processing applications. The device consists of two 8-channel inpUt multiplexers, a programmable gain amplifier (PGA), a 12-bit sampling AiD converter, two 32-word FIFOs, a controller, and registers for statUs and control. The device is packaged in a 100lead ceramic quad fiat package. The input multiplexers can be configured for either 16 channels of single-ended input or 8 channels of differential input. The number of channels can be doubled with the addition of a single external 16-channel multiplexer. The inputs are protected against power loss for applications where the AD1341 is not powered from the same source as its inputs. The programmable gain amplifier has differential inputs and 8 binary gain ranges from 1 to 128. Each channel can be programmed for a different gain. The controller timing allows the AD1341 to operate at the full 150,000 channels/second at gains from I to g. Above g, the throughput rate decreases proportionately to the increase in gain. The I2-bit sampling AiD converter is specified and tested for both static and dynamic performance. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. ~ IAO TE The AD1341 communicates asynchronously with the microprocessor over a 16-bit wide data path. Data can be formatted in either straight binary or twos complement with left, center or right justification. A 32-word FIFO is used to control channel selection and PGA gain. A second 32-word FIFO is used to store AiD conversion results. PRODUCT HIGHLIGHTS I. High throughput rate makes the AD 1341 ideal for use in a wide range of applications in motion control, speech process. ing, PC data acquisition, medical instrumentation, and missile guidance. 2. Software development is simplified because timing for channel selection, PGA gain changing and settling, and ND conversion is internal to the AD1341. Registers are available for enabling interrupt conditions and polling interrupt conditions or real-time status. 3. Software overhead is reduced by having FIFOs store channel information and conversion results. 4. Processor interface is simplified because the AD1341 operates fully asynchronously to the processor, has a maximum IS ns data access time and is isolated by hybrid circuit construction. One Technology Tel: 617/329-4700 Telex: 924491 Way. P.O. Box 9106. Norwood. MA 02062-9106. U.S.A. Fax: 617/326-8703 Twx: 710/394-6577 Cable: ANALOG NORWOODMASS ANALOGDEVICESfAX-ON-DEMAND HOTLINE - Page B AD1341- SPECIFICATIONSmode, (TA = Parameter AN Impedance Single Ended +5 Y dc, single-ended bipolar = Voo= 3.0 MHz,and G =16-channel, unless otherwise noted) AD 1341KZ Typ Max 1. I Min T min to Tmax G = 1001125 I 80 80 OBS ANALOG OUTP Reference Voltage OutpUt Current I 80 80 ::t2 ::t2oo ::tl 9.90 ::t1O ::t2 :1:30 I :!:1 9.90 I 150,000 100,000 57,690 29,410 14,850 150,000 100,000 57,690 29,410 14,850 ::tl/2 :1:2 ::tl/2 i:l ::tl T nUn to T max 12 12 I ::t2 TE 1/2 ::t2 :1:1 ::t2 ::t8 Tmin to Tn"." 70 68 :!:2 :1:1 ::tl ::tl ::t2 :!:6 ::tl ::t2 ::tl ::t2 :!:12 :1:4 Tmin to Tmax Gain Error Chan/See Chan/Sec Chan/Sec Chan/Sec Cban/Sec ::t 1/2 :!:4 i:l 73 72 72 71 71 70 69 66 -2- :1:6 70 68 73 72 72 71 71 70 69 66 mA pmrc Chan/Sec Chan/Sec Chan/Sec Chan/Sec Chan/Sec 12 12 :1:1 MnllpF MnllpF 10.10 ::t30 :!:2 :!: Units V V dB dB nA nA J.LVrms ILV fInS ::t2 ::t300 OLE 150,000 75,000 37,500 18,750 9,375 Integral Nonlinearity \MIC CHAI SNR G = I, fs = 150:0 kHz3 G = 2, fs = 150.0 kHz G = 4, fs = 150.0 kHz G = 8, fs = 150.0 kHz G =: 16, fs = 75.0 kHz3 G = 32, fs = 37.5 kHz G = 64, fs = 18.8 kHz G = 128, fs =: 9.4 kHz ::t1O 150,000 75,000 37,500 18,750 9,375 Bipolar Zero Error 1 75 10 PGA Gain Accuracy (Any Gain) Resolution for No Missing Codes Tmin to Tmax Unipolar Offset Error Tmin to Tmax lO+G 90 90 ::to.l 10.10 Drift Max ::t1O lO+G 90 90 ::to.l 75 10 1 G = 128 RANSFER CHARACTERISTI Standard Throughput Rate! G = 1, 2, 4 or 8 G = 16 G = 32 G = 64 G = 128 Accelerated Throughput Ratel, 2 G = 1,2,4 or 8 G = 16 G = 32 G = 64 G = 128 I :1:10 ADl341TZ Typ 1001150 1001125 1001150 Differential Voltage Range Common Mode Differential CMRR @ 120 Hz, G = 1 G = 128 Bias Current (VCM = 0) Voltage Noise (RT!) Min I = +25"C, Ys =Low, j:15FcU( Y dc, ASYNCEN % LSB LSB Bits Bits LSB LSB LSB LSB LSB LSB dB dB dB dB dB dB dB dB REV. A ANALOGDEVICES FAX.ON-DEMAND HOTLINE - Page ~1 ADl341 Min Parameter THD G = 1, fs = 150.0 kHz3 fs = 150.0 kHz fs ==150.0 kHz fs = 150.0 kHz fs = 75.0 kHz3 fs = 37.5 kHz G = 64, fs = 18.8 kHz G ==128, fs ==9.4 kHz CHANNEL- TO-CHANNEL ISOLATION DIGITAL INPUTS4 Input Voltage Logic Low Logic High Input Current Input Capacitance RST Low Pulse Width CLK Input Frequency Duty Cycle DIGITAL OUTPUTS4 Output Voltage Logic Low IoL = 4.0 mA G= G = G = G = G= -90 -90 -88 -88 -88 -88 -85 -&4 80 2, 4, 8, 16, 32, = 3.2 mA Logic High 10M = -4.0 mA 10M = -3.2 mA Output Capacitance High Impedance Leakage, DO-Dl5 Off State Leakage, -90 -90 -88 -88 -88 -88 -85 -&4 80 -78 ----------- -78 :!:60 :!:200 :!:60 3,0 55 MHz % 10 3.0 55 OLE 45 0.2 45 0.4 4.5 2.4 6 :!:60 ::t1 :!:200 :!:10 + 15.75 -14.25 +5.25 + 14.25 -15.75 +4.75 41 35 5 1.2 ::t1/2 0 -65 +70 +150 0.4 V V pF 4.5 6 ::t60 +13.5 -16.5 +4.5 41 3S 5 1.2 :!:112 -55 -65 V V TE 0.2 ::tl 56 50 10 1.6 dB dB dB dB dB dB dB dB dB :!:200 2 10 Units V V f-LA pF ns 0.8 2 2.4 -80 2.25 POWER SUPPLY PSRR, :!:Vs TEMPERATURE RANGE Operating and Specified Storage . -80 2.0 IRQ Operating Voltage Range +Vs -Vs VDD QuiescentCurrent +Vs -Vs VDD POWER CONSUMPTION AD1341TZ Max Typ Min 0.& OBS IoL AD1341KZ Max Typ :!:200 :!:10 f-LA f-LA +16.5 -13.5 +5.5 V V V 56 50 10 1.6 mA mA mA W LSBN +125 +150 ac °c NOTES I All channel gains are fIXed at the specified value. 'Accelerated performance is achieved through using a pipeline architecture and constant SHA acquisition times (see page 12 of this data sheet), 'fIN ~ 4.6 kHz for G = 1,2.3 kHz for G = 16 teSts. SNR excludes harmonics 2-9- THD includes harmonics 2-9. Input amplitude is -0.3 dB relative to full-scale at each gain. 'Guaranteed over operating temperature range, tested at +25°C only. SpecifICations subject to change without notice. REV. A -3- ANALOGDEVICES FAX-ON-DEHAND HOTLINE - Page ~2 AD1341 ABSOLUTE MAXIMUM RATINGS * +VstoAPWRIASIGGND -VstoAPWRIASIGGND VontoDGND APWRIASIG GND to DGND Analog Inputs to APWRIASIG GND OUtpUt Short Circuit Duration Reference & Multiplexer Outputs. . . . . . . . . . . . Indefinite Digital Outputs. . . . . . . . . . . . . . . 1 Output for I Second Lead Soldering Temperature (10 seconds) . . . . . . . . . + 300°C +18V )8V +7V -0.3 V to +0.3 V "Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure (0 absolute maximum rating conditions for extended periods may affect device reliability. Multiplexer. . . . . . . . . . . . . . +Vs + 16V, -Vs - 16 V PGA Reference Input Digital Inputs to DGND .. -0.3 Vsto+Vs 0Vto+l1V V to VDD + 0.3 Vor 10 mA CAUTION ESD (electrostatic discharge) sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. The protective foam should be discharged to the destination socket before devices are inserted. OBS (~veroperating temperature andpowersupplyvoltagerange, CHARACTERISTICS SWITCHING withtOUT = 30pFor100pFexcept wherenoted) Parameter READ CYCLE tRC tA Min Condition Description Typ COUT Data Access Time COUT = 100 pF COUT = 30 pF 2 3 3 3 3 ns ns ns ns ns ns ns ns ns ns ns ns ns IS 5 2 3 3 3 3 3 ns ns ns ns ns ns ns ns 25 3S IS 25 35 = 100pF COUT = 150 pF Output LO-Z Time Output HI-Z Time COUT 2 15 25 = 30 pF COUT = 100 pF IoH tARO tRDA tAcs IcsA WRITE CYCLE twe twp tsu tJH tAwR tWRA tACS tCSA Output Hold Time Address Valid to RD Low RD High to Address Invalid Address Valid to CS Low CS High to Address Invalid Units OLE = 30 pF Read Cycle Time COUT tLZ tHZ Max Write Cycle Time Write Pulse Width Input Setup Time Input Hold Time Address Valid to WR Low WR High to Address Invalid Address Valid to CS Low CS High 10 Address Invalid TE ORDERING GUIDE AD134lKZ Temperature Range oce to +70°C Package Option* Z-loo AD134lTZ/883B -55°C to + 12SoC Z-loo Model "Z = Ceramic Leaded Chip Carrier Package. -4- REV. A - ANALOGDEVICES fAX-ON-DEMAND HOTLINE ~3 Page AD1341 twc tRc 11.0-11.2 11.0-11.2 CS CS WR RD DIN DOUT NOTES NOTES - CSIS VAUD - CS IS BEFORE OR COINCIDENT WITH RD HIGH TO LOW TRANSITlON. CS IS INVALID AFTER OR COINCIDENT WITH RD LOW. TO. HIGH TRANSITION. WR IS NOT ACTIVE DURING READ CYCLE. OBS Figure 1a. Timing Waveform Controlled) RD WR DIN DOUT NOTES OR COINCIDENT WITH CS HIGH - TO WITH LOW TRANSITION. for Read Cycle No.2 WR HIGH - TO . LOW TRANSITION. for Write Cycle No.1 (WR twc TE NOTES WR IS VALID BEFORE OR COiNCIDENTwrrH - WR IS INVALID RD IS INVALIDAFTER OR COINCIDENT WITH Cs LOW. TO. HIGH TRANSITION. WR IS NOT ACTIVE DURING READ CYCLE. Figure 1b. Timing Waveform Controlled) COINCIDENT 11.0-/1.2 CS CS BEFORE OR OLE 11.0-11.2 IS VALID BEFORE Figure 2a. Timing Waveform Controlfed) for Read Cycle No.1 (RO tHc AD VALID CS IS tNVALiD AFTER OR COINCIDENT WITH WR LOW. TO - HIGH TRANSITION. RD IS NOT ACTIVE DURING WRITE CYCLE. AFTER OR COINCIDENT - - Cs HIGH TO WITH Cs LOW - . TO LOW TRANSITION. HIGH TRANSITION. RD IS NOT ACTIVE DURING WRITE CYCLE. Figure 2b. Timing Waveform Controlled) (CS for Write Cycle No.2 (CS AC TEST CONDITIONS Input Pulse Levels Input RiselFall Times Timing Reference Levels Inputs Outputs LOW HIGH Enabled to LOW Enabled to HIGH Disabled from LOW Disabled from HIGH DGND to +3.0 V G, ('1 II< 81POtO.. ~ Figure 13. Functional Block Diagram REV. A -7- ANALOGDEVICES fAX-ON-DEMAND HOTLINE - Page % AD1341 +5 40 AD1341 41 42 43 42 43 «11 4411 MUX1 MUX1 45 4S 46 46 47 47 OBS M. M. 56 57 58 56 £ 58 5911 AD1341 41 -;i1 MUXO 60 !!. 62 S3 39 Figure 15. AD1341 Configured for 16 Single-Ended Channels MUXO OLE 60 61 62 53 Figure 16. AD1341 Configured Channels Input 40 41 39 TE for 8 Differential Input AD1341 42 43 44 MUX1 45 46 ADG506A 47 D MUXQ EN A3 A2 A1 AO ..-.....- 39 MUXAn ~ MUXA2 MUXA3 ENXMUX Figure 17. AD1341 with Expansion Input Channels to 32 Single-Ended REV. A -8-- ANALOGDEVICES FAX-ON-DEMAND HOTLINE - Page ~7 AD1341 AD1341 CHI5. CHI4. CHI3. C1i12. CHit. MUXI ADGS06A D OBS OLE ~ MUXAI iM7i MUXA3 EiOOWx TE Figure 18. AD1341 with Expansion SEIDE MUXPAND MUXOUTI MUXOUTO ASIGGND D (ADG506A) EN (ADG506A) AO (ADG506A) AI (ADG506A) Al (ADG506A) A3 (ADGSO6A) 16-Channels Single-Ended 8-Channels Differential 32-Channels Single-Ended 16-Channels Differential {} I {} PGA+IN PGA-IN {} 1 PGA+IN PGA -'-IN PGA-IN PGA+IN ENXMUX MUXAO MUXAI MUXAl MUXA3 I I PGA-IN PGA-IN {} PGA+IN PGA.. IN PGA-IN to 16 Differential Input Channels Data Format Selection Six data formats are available, offering a choice between natural binary and 2s complement coding with left, center, or right justification of the 12-bit result within the l6-bit field. The data format is determined by connections made to the three inputs FMTO, FMTl, and FMT2 (Pins 87, 86, and 85). These connections should be hardwired. Logical Osare assigned to all unused places in the natural binary formats. The sign bit is extended as required and Osare forced in empty least-significant places in the 2s complement formats. Tables II and III describe the data formats and their selection. PGA+IN ENXMUX MUXAO MUXAI MUXA2 MUXA3 Table I. Connections for AD1341 Input Options The AD1341's multiplexer inputs are protected against destructive latchup under power-loss and overvoltage conditions. Each input uses a 2 kO current-limiting resistor and two diodes to provide protection to at least 16 V beyond the analog supplies (Figure 14). The expanded input configurations in Figures 17 and 18 maybe similarly protected by adding 2 kO resistors in series with each external multiplexer inpUt. Interactions between channels may occur under overload conditions. Unused AD1341 and ADG506A multiplexer inputs must be grounded. Nat Bin, Nat Bin, Nat Bin, 25 Com, 25 Com, 2s Com, LJ CJ RJ LJ CJ RJ FMT2 FMTl FMTO Output Format 0 0 0 0 1 1 1 I 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Natural Binary, NaIUral Binary, NatUral Binary, Reserved 2s Complement, 25 Complement, 2s Complement, Reserved Left Justified Right Justified Center Justified Left Justified Right Justified Center Justified Table II. Data Format Selection D15 D14 DB D12 DI1 DI0 D9 D8 D7 D6 D5 D4 D3 D2 Dl DO Bll 0 0 811 811 Bll 810 0 0 BIO 811 B11 B9 811 0 B9 Bll B11 Bg 810 0 B8 810 Bll B7 B9 Bll B7 B9 Bll B6 B8 BlO B6 B8 B1O B5 B7 89 B5 B7 B9 B4 B6 88 B4 B6 B8 B3 BS B7 B3 85 B7 B2 B4 B6 B2 B4 B6 BI B3 B5 Bl 83 BS BO B2 B4 BO B2 B4 0 Bl B3 0 Bl B3 0 BO B2 0 BO BZ 0 0 Bl 0 0 Bl 0 0 BO 0 0 BO Table /II. AD1341 Data Formats. D15 Is Data 8us MS8: 81115 ADC MSB -9- REV. A - -- - HNHLOG DEVICES fAX-ON-DEMAND HOTLINE - ~B Page AD1341 Figure 19 shows the basic connections required for a data acquisition system with 16 single-ended input channels, :!:5 V input range, and left-justified 2s complement data. .,v -1OV execution. The CCR contains a channel address and an associated gain. This information can be read back after the conversion is complete and the conversion result has been read ou!. The CCR bits are as follows (the MSB is BI5): CCR Description """.""""'